This is a DRAM tuning/overclocking stability report for various Allwinner A10/A13/A20 based devices. It can be automatically generated by the tools from https://github.com/ssvb/a10meminfo. Here we primarily focus on finding optimal dram_tpr3 values, tuned individually for every sunxi device. Currently these values need to be hardcoded into the sources of the ubootsunxi bootloader. The dram_tpr3 parameter is just a hexadecimal number, composed of the following bitfields:
Results interpretation:

 Lane phase adjustments: [0, 0, 0, 0] Error statistics from memtester: [solidbits=63, bitflip=16, bitspread=6] Best number of successful memtester runs, which span over 1 columns (00): 51 Best number of successful memtester runs, which span over 2 columns (01): 82 Best number of successful memtester runs, which span over 3 columns (02): 118 Best number of successful memtester runs, which span over 4 columns (03): 138 Best number of successful memtester runs, which span over 5 columns (04): 157 Best number of successful memtester runs, which span over 6 columns (05): 157 Read errors per lane: [1, 3, 2, 2]. Lane 2 is the most noisy/problematic. Errors from the lane 0 are not intersecting with the errors from the worst line 2. Errors from the lane 1 are not intersecting with the errors from the worst line 2. Errors from the lane 3 are not intersecting with the errors from the worst line 2. Write errors per lane: [55, 55, 20, 24]. Lane 3 is the most noisy/problematic. Errors from the lane 0 are not intersecting with the errors from the worst line 3. Errors from the lane 1 are not intersecting with the errors from the worst line 3. Errors from the lane 2 are 100.0% eclipsed by the worst lane 3. 

 Lane phase adjustments: [0, 0, 0, 0] Error statistics from memtester: [bitflip=7, solidbits=2] Best number of successful memtester runs, which span over 1 columns (00): 45 Best number of successful memtester runs, which span over 2 columns (01): 75 Best number of successful memtester runs, which span over 3 columns (02): 115 Best number of successful memtester runs, which span over 4 columns (03): 135 Best number of successful memtester runs, which span over 5 columns (04): 158 Best number of successful memtester runs, which span over 6 columns (05): 158 Read errors per lane: [0, 1, 2, 0]. Lane 1 is the most noisy/problematic. Errors from the lane 2 are not intersecting with the errors from the worst line 1. Write errors per lane: [4, 4, 2, 2]. Lane 3 is the most noisy/problematic. Errors from the lane 0 are not intersecting with the errors from the worst line 3. Errors from the lane 1 are not intersecting with the errors from the worst line 3. Errors from the lane 2 are 100.0% eclipsed by the worst lane 3. 