do vector logic op extension
add support for csel - promoting constants causes scheduling problems
Readd try_emit_line()
gen6 embedded conditional if/while
extra compare in discard
Improve texture in then/else cases
Remove/disable GLSL IR optimizations
Check out ickle's batchbuffer series
Get rid of fs_reg's stride/subreg_offset
Weak pthread symbols: http://sourceforge.net/p/mesa3d/mailman/message/14410824/
Expand assembly validator
Optimize mixed-type capabilities (mostly gen <= 5, but also add dst:f, src0:d, src1:d on all platforms)
Implement ATI_fragment_shader via NIR
Convert vec4 backend to use the builder
PSPom constant combining optimization
Use VFs in constant combining
Investigate CHV DxD multiplication problems
Predicate short blocks


dot product peephole
ARB_shader_group_vote

Try to enable "Sampler Set Remmapping for 3D Disable" in CACHE_MODE_0 (set to 1--disabled, on my system)
	(Claimed to be enabled by default in docx in https://vthsd.fm.intel.com/hsd/hswgth/default.aspx#bug_de/default.aspx?bug_de_id=3991066)
	Need to also set "Sampler Cache Set XOR selection" in CACHE_MODE_1 to 0b00 at the same time
0x7004 : 0x1C0
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  1  1  1  0  0  0  0  0  0
macbook intel-gpu-tools # ./tools/intel_reg_read -d 0x7000
0x7000 : 0x6800
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  1  1  0  1  0  0  0  0  0  0  0  0  0  0  0
Ken says these registers are context-saved, so can't be read correctly with intel_reg_read


Update shader-db for ES shaders