Driver vendor: X.Org
Device vendor: AMD
Device name: AMD BONAIRE (DRM 2.42.0, LLVM 3.7.0)

draw_info: {indexed = 0, mode = triangles, start = 0, count = 3, start_instance = 0, instance_count = 1, vertices_per_patch = 3, index_bias = 0, min_index = 0, max_index = 2, primitive_restart = 0, restart_index = 0, count_from_stream_output = NULL, indirect = NULL, indirect_offset = 0, }

vertex_buffer 0: {stride = 32, buffer_offset = 0, buffer = 0x01ce5a20, user_buffer = NULL, }
  buffer: {target = buffer, format = PIPE_FORMAT_R8_UNORM, width0 = 96, height0 = 1, depth0 = 1, array_size = 1, last_level = 0, nr_samples = 0, usage = 0, bind = 16, flags = 0, }
num vertex elements = 1
  vertex_element 0: {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32B32_FLOAT, }
num stream output targets = 0

begin shader: VERTEX
shader_state: {tokens = "
VERT
DCL IN[0]
DCL OUT[0], POSITION
DCL CONST[0..3]
DCL TEMP[0], LOCAL
  0: MUL TEMP[0], CONST[0], IN[0].xxxx
  1: MAD TEMP[0], CONST[1], IN[0].yyyy, TEMP[0]
  2: MAD TEMP[0], CONST[2], IN[0].zzzz, TEMP[0]
  3: MAD TEMP[0], CONST[3], IN[0].wwww, TEMP[0]
  4: MOV OUT[0], TEMP[0]
  5: END
", }
constant_buffer 0: {buffer = NULL, buffer_offset = 0, buffer_size = 64, user_buffer = 0x03721450, }
end shader: VERTEX

viewport_state 0: {scale = {800, 450, 0.5, }, translate = {800, 450, 0.5, }, }
rasterizer_state: {flatshade = 0, light_twoside = 0, clamp_vertex_color = 0, clamp_fragment_color = 0, front_ccw = 0, cull_face = 0, fill_front = 0, fill_back = 0, offset_point = 0, offset_line = 0, offset_tri = 0, scissor = 0, poly_smooth = 0, poly_stipple_enable = 0, point_smooth = 0, sprite_coord_enable = 0, sprite_coord_mode = 1, point_quad_rasterization = 1, point_tri_clip = 0, point_size_per_vertex = 0, multisample = 1, line_smooth = 0, line_stipple_enable = 0, line_stipple_factor = 0, line_stipple_pattern = 65535, line_last_pixel = 0, flatshade_first = 0, half_pixel_center = 1, bottom_edge_rule = 0, rasterizer_discard = 0, depth_clip = 1, clip_halfz = 0, clip_plane_enable = 0, line_width = 1, point_size = 1, offset_units = 0, offset_scale = 0, offset_clamp = 0, }

begin shader: FRAGMENT
shader_state: {tokens = "
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL OUT[0], COLOR
DCL CONST[0..3]
  0: MOV OUT[0], CONST[3]
  1: END
", }
constant_buffer 0: {buffer = NULL, buffer_offset = 0, buffer_size = 64, user_buffer = 0x020da4f0, }
sampler_state 0: {wrap_s = clamp_to_edge, wrap_t = clamp_to_edge, wrap_r = repeat, min_img_filter = linear, min_mip_filter = none, mag_img_filter = linear, compare_mode = 0, compare_func = never, normalized_coords = 1, max_anisotropy = 16, seamless_cube_map = 0, lod_bias = 0, min_lod = 0, max_lod = 1000, border_color.f = {0, 0, 0, 0, }, }
end shader: FRAGMENT

depth_stencil_alpha_state: {depth = {enabled = 0, }, stencil = {{enabled = 1, func = always, fail_op = replace, zpass_op = replace, zfail_op = replace, valuemask = 255, writemask = 255, }, {enabled = 0, }, }, alpha = {enabled = 0, }, }
stencil_ref: {ref_value = {1, 1, }, }
blend_state: {dither = 1, alpha_to_coverage = 0, alpha_to_one = 0, logicop_enable = 0, independent_blend_enable = 0, rt = {{blend_enable = 1, rgb_func = add, rgb_src_factor = one, rgb_dst_factor = src1_color, alpha_func = add, alpha_src_factor = one, alpha_dst_factor = src1_color, colormask = 15, }, }, }
blend_color: {color = {0, 0, 0, 0, }, }
min_samples = 1
sample_mask = 0xffffffff

framebuffer_state: {width = 1600, height = 900, nr_cbufs = 1, cbufs = {0x02768ed0, NULL, NULL, NULL, NULL, NULL, NULL, NULL, }, zsbuf = 0x027e78c0, }
  cbufs[0]:
    surface: {format = PIPE_FORMAT_R16G16B16A16_FLOAT, width = 1600, height = 900, texture = 0x0296cf60, u.tex.level = 0, u.tex.first_layer = 0, u.tex.last_layer = 0, }
    resource: {target = 2d, format = PIPE_FORMAT_R16G16B16A16_FLOAT, width0 = 1600, height0 = 900, depth0 = 1, array_size = 1, last_level = 0, nr_samples = 2, usage = 0, bind = 2, flags = 0, }
  zsbuf:
    surface: {format = PIPE_FORMAT_Z24_UNORM_S8_UINT, width = 1600, height = 900, texture = 0x0296bc70, u.tex.level = 0, u.tex.first_layer = 0, u.tex.last_layer = 0, }
    resource: {target = 2d, format = PIPE_FORMAT_Z24_UNORM_S8_UINT, width0 = 1600, height0 = 900, depth0 = 1, array_size = 1, last_level = 0, nr_samples = 2, usage = 0, bind = 9, flags = 0, }



*****************************************************************************
Driver-specific state:

Memory-mapped registers:
        GRBM_STATUS <- ME0PIPE0_CMDFIFO_AVAIL = 8
                       SRBM_RQ_PENDING = 1
                       ME0PIPE0_CF_RQ_PENDING = 0
                       ME0PIPE0_PF_RQ_PENDING = 0
                       GDS_DMA_RQ_PENDING = 0
                       DB_CLEAN = 0
                       CB_CLEAN = 0
                       TA_BUSY = 0
                       GDS_BUSY = 0
                       WD_BUSY_NO_DMA = 0
                       VGT_BUSY = 0
                       IA_BUSY_NO_DMA = 0
                       IA_BUSY = 0
                       SX_BUSY = 1
                       WD_BUSY = 0
                       SPI_BUSY = 1
                       BCI_BUSY = 1
                       SC_BUSY = 1
                       PA_BUSY = 0
                       DB_BUSY = 1
                       CP_COHERENCY_BUSY = 0
                       CP_BUSY = 1
                       CB_BUSY = 1
                       GUI_ACTIVE = 1

Vertex shader disassembly:
SHADER KEY
  instance_divisors = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
  as_es = 0
  as_ls = 0
	s_load_dwordx4 s[4:7], s[8:9], 0x0                  ; C0820900
	v_add_i32_e32 v0, s10, v0                           ; 4A00000A
	s_waitcnt lgkmcnt(0)                                ; BF8C007F
	buffer_load_format_xyzw v[0:3], v0, s[4:7], 0 idxen ; E00C2000 80010000
	s_load_dwordx4 s[0:3], s[2:3], 0x0                  ; C0800300
	s_waitcnt vmcnt(0) lgkmcnt(0)                       ; BF8C0070
	s_buffer_load_dword s4, s[0:3], 0x0                 ; C2020100
	s_buffer_load_dword s5, s[0:3], 0x1                 ; C2028101
	s_buffer_load_dword s6, s[0:3], 0x2                 ; C2030102
	s_buffer_load_dword s7, s[0:3], 0x3                 ; C2038103
	s_buffer_load_dword s8, s[0:3], 0x4                 ; C2040104
	s_buffer_load_dword s9, s[0:3], 0x5                 ; C2048105
	s_buffer_load_dword s10, s[0:3], 0x6                ; C2050106
	s_buffer_load_dword s11, s[0:3], 0x7                ; C2058107
	s_buffer_load_dword s12, s[0:3], 0x8                ; C2060108
	s_buffer_load_dword s13, s[0:3], 0x9                ; C2068109
	s_buffer_load_dword s14, s[0:3], 0xa                ; C207010A
	s_buffer_load_dword s15, s[0:3], 0xb                ; C207810B
	s_buffer_load_dword s16, s[0:3], 0xc                ; C208010C
	s_buffer_load_dword s17, s[0:3], 0xd                ; C208810D
	s_buffer_load_dword s18, s[0:3], 0xe                ; C209010E
	s_buffer_load_dword s0, s[0:3], 0xf                 ; C200010F
	s_waitcnt lgkmcnt(0)                                ; BF8C007F
	v_mul_f32_e32 v4, s4, v0                            ; 10080004
	v_mac_f32_e32 v4, s8, v1                            ; 3E080208
	v_mul_f32_e32 v5, s5, v0                            ; 100A0005
	v_mac_f32_e32 v5, s9, v1                            ; 3E0A0209
	v_mul_f32_e32 v6, s6, v0                            ; 100C0006
	v_mac_f32_e32 v6, s10, v1                           ; 3E0C020A
	v_mul_f32_e32 v0, s7, v0                            ; 10000007
	v_mac_f32_e32 v0, s11, v1                           ; 3E00020B
	v_mac_f32_e32 v4, s12, v2                           ; 3E08040C
	v_mac_f32_e32 v5, s13, v2                           ; 3E0A040D
	v_mac_f32_e32 v6, s14, v2                           ; 3E0C040E
	v_mac_f32_e32 v0, s15, v2                           ; 3E00040F
	v_mac_f32_e32 v4, s16, v3                           ; 3E080610
	v_mac_f32_e32 v5, s17, v3                           ; 3E0A0611
	v_mac_f32_e32 v6, s18, v3                           ; 3E0C0612
	v_mac_f32_e32 v0, s0, v3                            ; 3E000600
	exp 15, 12, 0, 1, 0, v4, v5, v6, v0                 ; F80008CF 00060504
	s_endpgm                                            ; BF810000


Fragment shader disassembly:
SHADER KEY
  export_16bpc = 0x3
  last_cbuf = 0
  color_two_side = 0
  alpha_func = 7
  alpha_to_one = 0
  poly_stipple = 0
	s_load_dwordx4 s[0:3], s[2:3], 0x0  ; C0800300
	s_waitcnt lgkmcnt(0)                ; BF8C007F
	s_buffer_load_dword s4, s[0:3], 0xc ; C202010C
	s_buffer_load_dword s5, s[0:3], 0xd ; C202810D
	s_buffer_load_dword s6, s[0:3], 0xe ; C203010E
	s_buffer_load_dword s0, s[0:3], 0xf ; C200010F
	s_waitcnt lgkmcnt(0)                ; BF8C007F
	v_mov_b32_e32 v0, s5                ; 7E000205
	v_cvt_pkrtz_f16_f32_e32 v0, s4, v0  ; 5E000004
	v_mov_b32_e32 v1, s0                ; 7E020200
	v_cvt_pkrtz_f16_f32_e32 v1, s6, v1  ; 5E020206
	exp 15, 0, 1, 1, 1, v0, v1, v0, v1  ; F8001C0F 01000100
	s_endpgm                            ; BF810000


------------------ IB begin ------------------
WRITE_DATA:
        CONTROL <- ENGINE_SEL = ME
                   WR_CONFIRM = 1
                   WR_ONE_ADDR = 0
                   DST_SEL = MEMORY_SYNC
        DST_ADDR_LO <- 0x1c295000
        DST_ADDR_HI <- 0
        0x00000001
NOP:
        Trace point ID: 1
        This trace point was reached by the CP.
CONTEXT_CONTROL:
        0x80000000
        0x80000000
SET_CONTEXT_REG:
        VGT_HOS_MAX_TESS_LEVEL <- 64.0f
        VGT_HOS_MIN_TESS_LEVEL <- 0
SET_CONTEXT_REG:
        VGT_GS_PER_ES <- GS_PER_ES = 128
        VGT_ES_PER_GS <- ES_PER_GS = 64
        VGT_GS_PER_VS <- GS_PER_VS = 2
SET_CONTEXT_REG:
        VGT_PRIMITIVEID_RESET <- 0
SET_CONTEXT_REG:
        VGT_VTX_CNT_EN <- VTX_CNT_EN = 0
SET_CONTEXT_REG:
        VGT_STRMOUT_DRAW_OPAQUE_OFFSET <- 0
SET_CONTEXT_REG:
        VGT_STRMOUT_BUFFER_CONFIG <- STREAM_0_BUFFER_EN = 0
                                     STREAM_1_BUFFER_EN = 0
                                     STREAM_2_BUFFER_EN = 0
                                     STREAM_3_BUFFER_EN = 0
SET_CONTEXT_REG:
        VGT_REUSE_OFF <- REUSE_OFF = 0
        VGT_VTX_CNT_EN <- VTX_CNT_EN = 0
SET_CONTEXT_REG:
        PA_SC_CENTROID_PRIORITY_0 <- DISTANCE_0 = 0
                                     DISTANCE_1 = 1
                                     DISTANCE_2 = 2
                                     DISTANCE_3 = 3
                                     DISTANCE_4 = 4
                                     DISTANCE_5 = 5
                                     DISTANCE_6 = 6
                                     DISTANCE_7 = 7
        PA_SC_CENTROID_PRIORITY_1 <- DISTANCE_8 = 8
                                     DISTANCE_9 = 9
                                     DISTANCE_10 = 10
                                     DISTANCE_11 = 11
                                     DISTANCE_12 = 12
                                     DISTANCE_13 = 13
                                     DISTANCE_14 = 14
                                     DISTANCE_15 = 15
SET_CONTEXT_REG:
        PA_SU_PRIM_FILTER_CNTL <- TRIANGLE_FILTER_DISABLE = 0
                                  LINE_FILTER_DISABLE = 0
                                  POINT_FILTER_DISABLE = 0
                                  RECTANGLE_FILTER_DISABLE = 0
                                  TRIANGLE_EXPAND_ENA = 0
                                  LINE_EXPAND_ENA = 0
                                  POINT_EXPAND_ENA = 0
                                  RECTANGLE_EXPAND_ENA = 0
                                  PRIM_EXPAND_CONSTANT = 0
                                  XMAX_RIGHT_EXCLUSION = 0
                                  YMAX_BOTTOM_EXCLUSION = 0
SET_CONTEXT_REG:
        PA_SC_RASTER_CONFIG <- RB_MAP_PKR0 = RASTER_CONFIG_RB_MAP_2
                               RB_MAP_PKR1 = RASTER_CONFIG_RB_MAP_0
                               RB_XSEL2 = RASTER_CONFIG_RB_XSEL2_1
                               RB_XSEL = 0
                               RB_YSEL = 0
                               PKR_MAP = RASTER_CONFIG_PKR_MAP_0
                               PKR_XSEL = RASTER_CONFIG_PKR_XSEL_0
                               PKR_YSEL = RASTER_CONFIG_PKR_YSEL_0
                               PKR_XSEL2 = RASTER_CONFIG_PKR_XSEL2_0
                               SC_MAP = RASTER_CONFIG_SC_MAP_0
                               SC_XSEL = RASTER_CONFIG_SC_XSEL_8_WIDE_TILE
                               SC_YSEL = RASTER_CONFIG_SC_YSEL_8_WIDE_TILE
                               SE_MAP = RASTER_CONFIG_SE_MAP_2
                               SE_XSEL = RASTER_CONFIG_SE_XSEL_16_WIDE_TILE
                               SE_YSEL = RASTER_CONFIG_SE_YSEL_16_WIDE_TILE
        PA_SC_RASTER_CONFIG_1 <- SE_PAIR_MAP = RASTER_CONFIG_SE_PAIR_MAP_0
                                 SE_PAIR_XSEL = RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE
                                 SE_PAIR_YSEL = RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE
SET_CONTEXT_REG:
        PA_SC_WINDOW_SCISSOR_TL <- TL_X = 0
                                   TL_Y = 0
                                   WINDOW_OFFSET_DISABLE = 1
SET_CONTEXT_REG:
        PA_SC_GENERIC_SCISSOR_TL <- TL_X = 0
                                    TL_Y = 0
                                    WINDOW_OFFSET_DISABLE = 1
        PA_SC_GENERIC_SCISSOR_BR <- BR_X = 16384
                                    BR_Y = 16384
SET_CONTEXT_REG:
        PA_SC_SCREEN_SCISSOR_TL <- TL_X = 0
                                   TL_Y = 0
        PA_SC_SCREEN_SCISSOR_BR <- BR_X = 16384
                                   BR_Y = 16384
SET_CONTEXT_REG:
        PA_SC_CLIPRECT_RULE <- CLIP_RULE = 0xffff
SET_CONTEXT_REG:
        PA_SC_EDGERULE <- ER_TRI = 10
                          ER_POINT = 10
                          ER_RECT = 10
                          ER_LINE_LR = 42
                          ER_LINE_RL = 42
                          ER_LINE_TB = 10
                          ER_LINE_BT = 10
        PA_SU_HARDWARE_SCREEN_OFFSET <- HW_SCREEN_OFFSET_X = 0
                                        HW_SCREEN_OFFSET_Y = 0
SET_CONTEXT_REG:
        PA_SC_VPORT_ZMIN_0 <- 0
        PA_SC_VPORT_ZMAX_0 <- 1.0f
SET_CONTEXT_REG:
        PA_CL_NANINF_CNTL <- VTE_XY_INF_DISCARD = 0
                             VTE_Z_INF_DISCARD = 0
                             VTE_W_INF_DISCARD = 0
                             VTE_0XNANINF_IS_0 = 0
                             VTE_XY_NAN_RETAIN = 0
                             VTE_Z_NAN_RETAIN = 0
                             VTE_W_NAN_RETAIN = 0
                             VTE_W_RECIP_NAN_IS_0 = 0
                             VS_XY_NAN_TO_INF = 0
                             VS_XY_INF_RETAIN = 0
                             VS_Z_NAN_TO_INF = 0
                             VS_Z_INF_RETAIN = 0
                             VS_W_NAN_TO_INF = 0
                             VS_W_INF_RETAIN = 0
                             VS_CLIP_DIST_INF_DISCARD = 0
                             VTE_NO_OUTPUT_NEG_0 = 0
SET_CONTEXT_REG:
        PA_CL_GB_VERT_CLIP_ADJ <- 1.0f
        PA_CL_GB_VERT_DISC_ADJ <- 1.0f
        PA_CL_GB_HORZ_CLIP_ADJ <- 1.0f
        PA_CL_GB_HORZ_DISC_ADJ <- 1.0f
SET_CONTEXT_REG:
        DB_STENCIL_CLEAR <- CLEAR = 0
SET_CONTEXT_REG:
        DB_SRESULTS_COMPARE_STATE0 <- COMPAREFUNC0 = REF_NEVER
                                      COMPAREVALUE0 = 0
                                      COMPAREMASK0 = 0
                                      ENABLE0 = 0
        DB_SRESULTS_COMPARE_STATE1 <- COMPAREFUNC1 = REF_NEVER
                                      COMPAREVALUE1 = 0
                                      COMPAREMASK1 = 0
                                      ENABLE1 = 0
        DB_PRELOAD_CONTROL <- START_X = 0
                              START_Y = 0
                              MAX_X = 0
                              MAX_Y = 0
SET_CONTEXT_REG:
        DB_RENDER_OVERRIDE <- FORCE_HIZ_ENABLE = FORCE_OFF
                              FORCE_HIS_ENABLE0 = FORCE_DISABLE
                              FORCE_HIS_ENABLE1 = FORCE_DISABLE
                              FORCE_SHADER_Z_ORDER = 0
                              FAST_Z_DISABLE = 0
                              FAST_STENCIL_DISABLE = 1
                              NOOP_CULL_DISABLE = 0
                              FORCE_COLOR_KILL = 0
                              FORCE_Z_READ = 0
                              FORCE_STENCIL_READ = 0
                              FORCE_FULL_Z_RANGE = FORCE_OFF
                              FORCE_QC_SMASK_CONFLICT = 0
                              DISABLE_VIEWPORT_CLAMP = 0
                              IGNORE_SC_ZRANGE = 0
                              DISABLE_FULLY_COVERED = 0
                              FORCE_Z_LIMIT_SUMM = FORCE_SUMM_OFF
                              MAX_TILES_IN_DTT = 0
                              DISABLE_TILE_RATE_TILES = 0
                              FORCE_Z_DIRTY = 0
                              FORCE_STENCIL_DIRTY = 0
                              FORCE_Z_VALID = 0
                              FORCE_STENCIL_VALID = 0
                              PRESERVE_COMPRESSION = 0
SET_CONTEXT_REG:
        VGT_MAX_VTX_INDX <- 0xffffffff
        VGT_MIN_VTX_INDX <- 0
        VGT_INDX_OFFSET <- 0
SET_SH_REG:
        SPI_SHADER_PGM_RSRC3_LS <- CU_EN = 0xfffc
                                   WAVE_LIMIT = 0
                                   LOCK_LOW_THRESHOLD = 0
                                   GROUP_FIFO_DEPTH = 0
SET_SH_REG:
        SPI_SHADER_PGM_RSRC3_HS <- WAVE_LIMIT = 0
                                   LOCK_LOW_THRESHOLD = 0
                                   GROUP_FIFO_DEPTH = 0
SET_SH_REG:
        SPI_SHADER_PGM_RSRC3_ES <- CU_EN = 0xfffe
                                   WAVE_LIMIT = 0
                                   LOCK_LOW_THRESHOLD = 0
                                   GROUP_FIFO_DEPTH = 0
SET_SH_REG:
        SPI_SHADER_PGM_RSRC3_GS <- CU_EN = 0xffff
                                   WAVE_LIMIT = 0
                                   LOCK_LOW_THRESHOLD = 0
                                   GROUP_FIFO_DEPTH = 0
SET_SH_REG:
        SPI_SHADER_PGM_RSRC3_VS <- CU_EN = 0xffff
                                   WAVE_LIMIT = 0
                                   LOCK_LOW_THRESHOLD = 0
        SPI_SHADER_LATE_ALLOC_VS <- LIMIT = 0
SET_SH_REG:
        SPI_SHADER_PGM_RSRC3_PS <- CU_EN = 0xffff
                                   WAVE_LIMIT = 0
                                   LOCK_LOW_THRESHOLD = 0
EVENT_WRITE:
        VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_CB_META
        EVENT_INDEX <- 0
        INV_L2 <- 0
EVENT_WRITE:
        VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_DB_META
        EVENT_INDEX <- 0
        INV_L2 <- 0
ACQUIRE_MEM:
        CP_COHER_CNTL <- DEST_BASE_0_ENA = 0
                         DEST_BASE_1_ENA = 0
                         TC_SD_ACTION_ENA = 0
                         TC_NC_ACTION_ENA = 0
                         CB0_DEST_BASE_ENA = 1
                         CB1_DEST_BASE_ENA = 1
                         CB2_DEST_BASE_ENA = 1
                         CB3_DEST_BASE_ENA = 1
                         CB4_DEST_BASE_ENA = 1
                         CB5_DEST_BASE_ENA = 1
                         CB6_DEST_BASE_ENA = 1
                         CB7_DEST_BASE_ENA = 1
                         DB_DEST_BASE_ENA = 1
                         TCL1_VOL_ACTION_ENA = 0
                         TC_VOL_ACTION_ENA = 0
                         TC_WB_ACTION_ENA = 0
                         DEST_BASE_2_ENA = 0
                         DEST_BASE_3_ENA = 0
                         TCL1_ACTION_ENA = 1
                         TC_ACTION_ENA = 1
                         CB_ACTION_ENA = 1
                         DB_ACTION_ENA = 1
                         SH_KCACHE_ACTION_ENA = 1
                         SH_KCACHE_VOL_ACTION_ENA = 0
                         SH_ICACHE_ACTION_ENA = 1
                         SH_KCACHE_WB_ACTION_ENA = 0
                         SH_SD_ACTION_ENA = 0
        CP_COHER_SIZE <- 0xffffffff
        CP_COHER_SIZE_HI <- COHER_SIZE_HI_256B = 255
        CP_COHER_BASE <- 0
        CP_COHER_BASE_HI <- COHER_BASE_HI_256B = 0
        POLL_INTERVAL <- 10
SET_CONTEXT_REG:
        VGT_STRMOUT_BUFFER_CONFIG <- STREAM_0_BUFFER_EN = 0
                                     STREAM_1_BUFFER_EN = 0
                                     STREAM_2_BUFFER_EN = 0
                                     STREAM_3_BUFFER_EN = 0
SET_CONTEXT_REG:
        VGT_STRMOUT_CONFIG <- STREAMOUT_0_EN = 0
                              STREAMOUT_1_EN = 0
                              STREAMOUT_2_EN = 0
                              STREAMOUT_3_EN = 0
                              RAST_STREAM = 0
                              RAST_STREAM_MASK = 0
                              USE_RAST_STREAM_MASK = 0
SET_CONTEXT_REG:
        CB_COLOR0_BASE <- 0x001df300
        CB_COLOR0_PITCH <- TILE_MAX = 199
                           FMASK_TILE_MAX = 207
        CB_COLOR0_SLICE <- TILE_MAX = 23999
        CB_COLOR0_VIEW <- SLICE_START = 0
                          SLICE_MAX = 0
        CB_COLOR0_INFO <- ENDIAN = ENDIAN_NONE
                          FORMAT = COLOR_16_16_16_16
                          LINEAR_GENERAL = 0
                          NUMBER_TYPE = NUMBER_FLOAT
                          COMP_SWAP = SWAP_STD
                          FAST_CLEAR = 1
                          COMPRESSION = 1
                          BLEND_CLAMP = 0
                          BLEND_BYPASS = 0
                          SIMPLE_FLOAT = 0
                          ROUND_MODE = 0
                          CMASK_IS_LINEAR = 0
                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
                          FMASK_COMPRESSION_DISABLE = 0
                          FMASK_COMPRESS_1FRAG_ONLY = 0
                          DCC_ENABLE = 0
                          CMASK_ADDR_TYPE = 0
        CB_COLOR0_ATTRIB <- TILE_MODE_INDEX = 14
                            FMASK_TILE_MODE_INDEX = 14
                            FMASK_BANK_HEIGHT = 0
                            NUM_SAMPLES = 1
                            NUM_FRAGMENTS = 1
                            FORCE_DST_ALPHA_1 = 0
        CB_COLOR0_DCC_CONTROL <- OVERWRITE_COMBINER_DISABLE = 0
                                 KEY_CLEAR_ENABLE = 0
                                 MAX_UNCOMPRESSED_BLOCK_SIZE = 0
                                 MIN_COMPRESSED_BLOCK_SIZE = 0
                                 MAX_COMPRESSED_BLOCK_SIZE = 0
                                 COLOR_TRANSFORM = 0
                                 INDEPENDENT_64B_BLOCKS = 0
                                 LOSSY_RGB_PRECISION = 0
                                 LOSSY_ALPHA_PRECISION = 0
        CB_COLOR0_CMASK <- 0x001f8400
        CB_COLOR0_CMASK_SLICE <- TILE_MAX = 111
        CB_COLOR0_FMASK <- 0x001f6a00
        CB_COLOR0_FMASK_SLICE <- TILE_MAX = 26623
        CB_COLOR0_CLEAR_WORD0 <- 0x320e29ca
        CB_COLOR0_CLEAR_WORD1 <- 0x3c00382c
SET_CONTEXT_REG:
        CB_COLOR1_INFO <- ENDIAN = ENDIAN_NONE
                          FORMAT = COLOR_16_16_16_16
                          LINEAR_GENERAL = 0
                          NUMBER_TYPE = NUMBER_FLOAT
                          COMP_SWAP = SWAP_STD
                          FAST_CLEAR = 1
                          COMPRESSION = 1
                          BLEND_CLAMP = 0
                          BLEND_BYPASS = 0
                          SIMPLE_FLOAT = 0
                          ROUND_MODE = 0
                          CMASK_IS_LINEAR = 0
                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
                          FMASK_COMPRESSION_DISABLE = 0
                          FMASK_COMPRESS_1FRAG_ONLY = 0
                          DCC_ENABLE = 0
                          CMASK_ADDR_TYPE = 0
SET_CONTEXT_REG:
        CB_COLOR2_INFO <- ENDIAN = ENDIAN_NONE
                          FORMAT = COLOR_INVALID
                          LINEAR_GENERAL = 0
                          NUMBER_TYPE = NUMBER_UNORM
                          COMP_SWAP = SWAP_STD
                          FAST_CLEAR = 0
                          COMPRESSION = 0
                          BLEND_CLAMP = 0
                          BLEND_BYPASS = 0
                          SIMPLE_FLOAT = 0
                          ROUND_MODE = 0
                          CMASK_IS_LINEAR = 0
                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
                          FMASK_COMPRESSION_DISABLE = 0
                          FMASK_COMPRESS_1FRAG_ONLY = 0
                          DCC_ENABLE = 0
                          CMASK_ADDR_TYPE = 0
SET_CONTEXT_REG:
        CB_COLOR3_INFO <- ENDIAN = ENDIAN_NONE
                          FORMAT = COLOR_INVALID
                          LINEAR_GENERAL = 0
                          NUMBER_TYPE = NUMBER_UNORM
                          COMP_SWAP = SWAP_STD
                          FAST_CLEAR = 0
                          COMPRESSION = 0
                          BLEND_CLAMP = 0
                          BLEND_BYPASS = 0
                          SIMPLE_FLOAT = 0
                          ROUND_MODE = 0
                          CMASK_IS_LINEAR = 0
                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
                          FMASK_COMPRESSION_DISABLE = 0
                          FMASK_COMPRESS_1FRAG_ONLY = 0
                          DCC_ENABLE = 0
                          CMASK_ADDR_TYPE = 0
SET_CONTEXT_REG:
        CB_COLOR4_INFO <- ENDIAN = ENDIAN_NONE
                          FORMAT = COLOR_INVALID
                          LINEAR_GENERAL = 0
                          NUMBER_TYPE = NUMBER_UNORM
                          COMP_SWAP = SWAP_STD
                          FAST_CLEAR = 0
                          COMPRESSION = 0
                          BLEND_CLAMP = 0
                          BLEND_BYPASS = 0
                          SIMPLE_FLOAT = 0
                          ROUND_MODE = 0
                          CMASK_IS_LINEAR = 0
                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
                          FMASK_COMPRESSION_DISABLE = 0
                          FMASK_COMPRESS_1FRAG_ONLY = 0
                          DCC_ENABLE = 0
                          CMASK_ADDR_TYPE = 0
SET_CONTEXT_REG:
        CB_COLOR5_INFO <- ENDIAN = ENDIAN_NONE
                          FORMAT = COLOR_INVALID
                          LINEAR_GENERAL = 0
                          NUMBER_TYPE = NUMBER_UNORM
                          COMP_SWAP = SWAP_STD
                          FAST_CLEAR = 0
                          COMPRESSION = 0
                          BLEND_CLAMP = 0
                          BLEND_BYPASS = 0
                          SIMPLE_FLOAT = 0
                          ROUND_MODE = 0
                          CMASK_IS_LINEAR = 0
                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
                          FMASK_COMPRESSION_DISABLE = 0
                          FMASK_COMPRESS_1FRAG_ONLY = 0
                          DCC_ENABLE = 0
                          CMASK_ADDR_TYPE = 0
SET_CONTEXT_REG:
        CB_COLOR6_INFO <- ENDIAN = ENDIAN_NONE
                          FORMAT = COLOR_INVALID
                          LINEAR_GENERAL = 0
                          NUMBER_TYPE = NUMBER_UNORM
                          COMP_SWAP = SWAP_STD
                          FAST_CLEAR = 0
                          COMPRESSION = 0
                          BLEND_CLAMP = 0
                          BLEND_BYPASS = 0
                          SIMPLE_FLOAT = 0
                          ROUND_MODE = 0
                          CMASK_IS_LINEAR = 0
                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
                          FMASK_COMPRESSION_DISABLE = 0
                          FMASK_COMPRESS_1FRAG_ONLY = 0
                          DCC_ENABLE = 0
                          CMASK_ADDR_TYPE = 0
SET_CONTEXT_REG:
        CB_COLOR7_INFO <- ENDIAN = ENDIAN_NONE
                          FORMAT = COLOR_INVALID
                          LINEAR_GENERAL = 0
                          NUMBER_TYPE = NUMBER_UNORM
                          COMP_SWAP = SWAP_STD
                          FAST_CLEAR = 0
                          COMPRESSION = 0
                          BLEND_CLAMP = 0
                          BLEND_BYPASS = 0
                          SIMPLE_FLOAT = 0
                          ROUND_MODE = 0
                          CMASK_IS_LINEAR = 0
                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
                          FMASK_COMPRESSION_DISABLE = 0
                          FMASK_COMPRESS_1FRAG_ONLY = 0
                          DCC_ENABLE = 0
                          CMASK_ADDR_TYPE = 0
SET_CONTEXT_REG:
        DB_DEPTH_VIEW <- SLICE_START = 0
                         SLICE_MAX = 0
                         Z_READ_ONLY = 0
                         STENCIL_READ_ONLY = 0
SET_CONTEXT_REG:
        DB_HTILE_DATA_BASE <- 0x00174e40
SET_CONTEXT_REG:
        DB_DEPTH_INFO <- ADDR5_SWIZZLE_MASK = 1
                         ARRAY_MODE = ARRAY_2D_TILED_THIN1
                         PIPE_CONFIG = X_ADDR_SURF_P4_16X16
                         BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1
                         BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_2
                         MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4
                         NUM_BANKS = ADDR_SURF_16_BANK
        DB_Z_INFO <- FORMAT = Z_24
                     NUM_SAMPLES = 1
                     TILE_SPLIT = ADDR_SURF_TILE_SPLIT_128B
                     TILE_MODE_INDEX = 0
                     DECOMPRESS_ON_N_ZPLANES = 0
                     ALLOW_EXPCLEAR = 1
                     READ_SIZE = 0
                     TILE_SURFACE_ENABLE = 1
                     CLEAR_DISALLOWED = 0
                     ZRANGE_PRECISION = 1
        DB_STENCIL_INFO <- FORMAT = STENCIL_8
                           TILE_SPLIT = ADDR_SURF_TILE_SPLIT_128B
                           TILE_MODE_INDEX = 0
                           ALLOW_EXPCLEAR = 0
                           TILE_STENCIL_DISABLE = 1
                           CLEAR_DISALLOWED = 0
        DB_Z_READ_BASE <- 0x001cff40
        DB_STENCIL_READ_BASE <- 0x001dc240
        DB_Z_WRITE_BASE <- 0x001cff40
        DB_STENCIL_WRITE_BASE <- 0x001dc240
        DB_DEPTH_SIZE <- PITCH_TILE_MAX = 207
                         HEIGHT_TILE_MAX = 119
        DB_DEPTH_SLICE <- SLICE_TILE_MAX = 24959
SET_CONTEXT_REG:
        DB_HTILE_SURFACE <- LINEAR = 0
                            FULL_CACHE = 1
                            HTILE_USES_PRELOAD_WIN = 0
                            PRELOAD = 0
                            PREFETCH_WIDTH = 0
                            PREFETCH_HEIGHT = 0
                            DST_OUTSIDE_ZERO_TO_ONE = 0
                            TC_COMPATIBLE = 0
SET_CONTEXT_REG:
        DB_DEPTH_CLEAR <- 1.0f
SET_CONTEXT_REG:
        PA_SU_POLY_OFFSET_DB_FMT_CNTL <- POLY_OFFSET_NEG_NUM_DB_BITS = 232
                                         POLY_OFFSET_DB_IS_FLOAT_FMT = 0
SET_CONTEXT_REG:
        PA_SC_WINDOW_SCISSOR_BR <- BR_X = 1600
                                   BR_Y = 900
SET_CONTEXT_REG:
        PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 <- S0_X = 12
                                             S0_Y = 4
                                             S1_X = 4
                                             S1_Y = 12
                                             S2_X = 12
                                             S2_Y = 4
                                             S3_X = 4
                                             S3_Y = 12
SET_CONTEXT_REG:
        PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 <- S0_X = 12
                                             S0_Y = 4
                                             S1_X = 4
                                             S1_Y = 12
                                             S2_X = 12
                                             S2_Y = 4
                                             S3_X = 4
                                             S3_Y = 12
SET_CONTEXT_REG:
        PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 <- S0_X = 12
                                             S0_Y = 4
                                             S1_X = 4
                                             S1_Y = 12
                                             S2_X = 12
                                             S2_Y = 4
                                             S3_X = 4
                                             S3_Y = 12
SET_CONTEXT_REG:
        PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 <- S0_X = 12
                                             S0_Y = 4
                                             S1_X = 4
                                             S1_Y = 12
                                             S2_X = 12
                                             S2_Y = 4
                                             S3_X = 4
                                             S3_Y = 12
SET_CONTEXT_REG:
        DB_RENDER_CONTROL <- DEPTH_CLEAR_ENABLE = 0
                             STENCIL_CLEAR_ENABLE = 0
                             DEPTH_COPY = 0
                             STENCIL_COPY = 0
                             RESUMMARIZE_ENABLE = 0
                             STENCIL_COMPRESS_DISABLE = 0
                             DEPTH_COMPRESS_DISABLE = 0
                             COPY_CENTROID = 0
                             COPY_SAMPLE = 0
                             DECOMPRESS_ENABLE = 0
        DB_COUNT_CONTROL <- ZPASS_INCREMENT_DISABLE = 0
                            PERFECT_ZPASS_COUNTS = 0
                            SAMPLE_RATE = 0
                            ZPASS_ENABLE = 0
                            ZFAIL_ENABLE = 0
                            SFAIL_ENABLE = 0
                            DBFAIL_ENABLE = 0
                            SLICE_EVEN_ENABLE = 0
                            SLICE_ODD_ENABLE = 0
SET_CONTEXT_REG:
        DB_RENDER_OVERRIDE2 <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
                               DISABLE_COLOR_ON_VALIDATION = 0
                               DECOMPRESS_Z_ON_FLUSH = 0
                               DISABLE_REG_SNOOP = 0
                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
                               SEPARATE_HIZS_FUNC_ENABLE = 0
                               HIZ_ZFUNC = 0
                               HIS_SFUNC_FF = 0
                               HIS_SFUNC_BF = 0
                               PRESERVE_ZRANGE = 0
                               PRESERVE_SRESULTS = 0
                               DISABLE_FAST_PASS = 0
SET_CONTEXT_REG:
        DB_SHADER_CONTROL <- Z_EXPORT_ENABLE = 0
                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
                             Z_ORDER = EARLY_Z_THEN_LATE_Z
                             KILL_ENABLE = 0
                             COVERAGE_TO_MASK_ENABLE = 0
                             MASK_EXPORT_ENABLE = 0
                             EXEC_ON_HIER_FAIL = 0
                             EXEC_ON_NOOP = 0
                             ALPHA_TO_MASK_DISABLE = 0
                             DEPTH_BEFORE_SHADER = 0
                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
SET_CONTEXT_REG:
        PA_SC_LINE_CNTL <- EXPAND_LINE_WIDTH = 1
                           LAST_PIXEL = 1
                           PERPENDICULAR_ENDCAP_ENA = 0
                           DX10_DIAMOND_TEST_ENA = 0
        PA_SC_AA_CONFIG <- MSAA_NUM_SAMPLES = 1
                           AA_MASK_CENTROID_DTMN = 0
                           MAX_SAMPLE_DIST = 4
                           MSAA_EXPOSED_SAMPLES = 1
                           DETAIL_TO_EXPOSED_MODE = 0
SET_CONTEXT_REG:
        DB_EQAA <- MAX_ANCHOR_SAMPLES = 1
                   PS_ITER_SAMPLES = 0
                   MASK_EXPORT_NUM_SAMPLES = 1
                   ALPHA_TO_MASK_NUM_SAMPLES = 1
                   HIGH_QUALITY_INTERSECTIONS = 1
                   INCOHERENT_EQAA_READS = 0
                   INTERPOLATE_COMP_Z = 0
                   INTERPOLATE_SRC_Z = 0
                   STATIC_ANCHOR_ASSOCIATIONS = 1
                   ALPHA_TO_MASK_EQAA_DISABLE = 0
                   OVERRASTERIZATION_AMOUNT = 0
                   ENABLE_POSTZ_OVERRASTERIZATION = 0
SET_CONTEXT_REG:
        PA_SC_MODE_CNTL_1 <- WALK_SIZE = 0
                             WALK_ALIGNMENT = 0
                             WALK_ALIGN8_PRIM_FITS_ST = 0
                             WALK_FENCE_ENABLE = 0
                             WALK_FENCE_SIZE = 0
                             SUPERTILE_WALK_ORDER_ENABLE = 0
                             TILE_WALK_ORDER_ENABLE = 0
                             TILE_COVER_DISABLE = 0
                             TILE_COVER_NO_SCISSOR = 0
                             ZMM_LINE_EXTENT = 0
                             ZMM_LINE_OFFSET = 0
                             ZMM_RECT_EXTENT = 0
                             KILL_PIX_POST_HI_Z = 0
                             KILL_PIX_POST_DETAIL_MASK = 0
                             PS_ITER_SAMPLE = 0
                             MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE = 0
                             MULTI_GPU_SUPERTILE_ENABLE = 0
                             GPU_ID_OVERRIDE_ENABLE = 0
                             GPU_ID_OVERRIDE = 0
                             MULTI_GPU_PRIM_DISCARD_ENABLE = 0
                             FORCE_EOV_CNTDWN_ENABLE = 0
                             FORCE_EOV_REZ_ENABLE = 0
                             OUT_OF_ORDER_PRIMITIVE_ENABLE = 0
                             OUT_OF_ORDER_WATER_MARK = 0
SET_CONTEXT_REG:
        PA_CL_VS_OUT_CNTL <- CLIP_DIST_ENA_0 = 0
                             CLIP_DIST_ENA_1 = 0
                             CLIP_DIST_ENA_2 = 0
                             CLIP_DIST_ENA_3 = 0
                             CLIP_DIST_ENA_4 = 0
                             CLIP_DIST_ENA_5 = 0
                             CLIP_DIST_ENA_6 = 0
                             CLIP_DIST_ENA_7 = 0
                             CULL_DIST_ENA_0 = 0
                             CULL_DIST_ENA_1 = 0
                             CULL_DIST_ENA_2 = 0
                             CULL_DIST_ENA_3 = 0
                             CULL_DIST_ENA_4 = 0
                             CULL_DIST_ENA_5 = 0
                             CULL_DIST_ENA_6 = 0
                             CULL_DIST_ENA_7 = 0
                             USE_VTX_POINT_SIZE = 0
                             USE_VTX_EDGE_FLAG = 0
                             USE_VTX_RENDER_TARGET_INDX = 0
                             USE_VTX_VIEWPORT_INDX = 0
                             USE_VTX_KILL_FLAG = 0
                             VS_OUT_MISC_VEC_ENA = 0
                             VS_OUT_CCDIST0_VEC_ENA = 0
                             VS_OUT_CCDIST1_VEC_ENA = 0
                             VS_OUT_MISC_SIDE_BUS_ENA = 1
                             USE_VTX_GS_CUT_FLAG = 0
                             USE_VTX_LINE_WIDTH = 0
SET_CONTEXT_REG:
        PA_CL_CLIP_CNTL <- UCP_ENA_0 = 0
                           UCP_ENA_1 = 0
                           UCP_ENA_2 = 0
                           UCP_ENA_3 = 0
                           UCP_ENA_4 = 0
                           UCP_ENA_5 = 0
                           PS_UCP_Y_SCALE_NEG = 0
                           PS_UCP_MODE = 3
                           CLIP_DISABLE = 0
                           UCP_CULL_ONLY_ENA = 0
                           BOUNDARY_EDGE_FLAG_ENA = 0
                           DX_CLIP_SPACE_DEF = 0
                           DIS_CLIP_ERR_DETECT = 0
                           VTX_KILL_OR = 0
                           DX_RASTERIZATION_KILL = 0
                           DX_LINEAR_ATTR_CLIP_ENA = 1
                           VTE_VPORT_PROVOKE_DISABLE = 0
                           ZCLIP_NEAR_DISABLE = 0
                           ZCLIP_FAR_DISABLE = 0
SET_SH_REG:
        SPI_SHADER_USER_DATA_VS_0 <- 0x16b9f000
        SPI_SHADER_USER_DATA_VS_1 <- 0
SET_SH_REG:
        SPI_SHADER_USER_DATA_VS_2 <- 0x16b9ee00
        SPI_SHADER_USER_DATA_VS_3 <- 0
SET_SH_REG:
        SPI_SHADER_USER_DATA_VS_6 <- 0x016fc700
        SPI_SHADER_USER_DATA_VS_7 <- 0
SET_SH_REG:
        SPI_SHADER_USER_DATA_VS_4 <- 0x016fcc00
        SPI_SHADER_USER_DATA_VS_5 <- 0
SET_SH_REG:
        SPI_SHADER_USER_DATA_PS_0 <- 0x016fd000
        SPI_SHADER_USER_DATA_PS_1 <- 0
SET_SH_REG:
        SPI_SHADER_USER_DATA_PS_2 <- 0x16b9f100
        SPI_SHADER_USER_DATA_PS_3 <- 0
SET_SH_REG:
        SPI_SHADER_USER_DATA_PS_6 <- 0x0c80ae00
        SPI_SHADER_USER_DATA_PS_7 <- 0
SET_SH_REG:
        SPI_SHADER_USER_DATA_PS_4 <- 0x0c809f00
        SPI_SHADER_USER_DATA_PS_5 <- 0
SET_SH_REG:
        SPI_SHADER_USER_DATA_GS_0 <- 0x016fda00
        SPI_SHADER_USER_DATA_GS_1 <- 0
SET_SH_REG:
        SPI_SHADER_USER_DATA_GS_2 <- 0x016fd800
        SPI_SHADER_USER_DATA_GS_3 <- 0
SET_SH_REG:
        SPI_SHADER_USER_DATA_GS_6 <- 0x016fdb00
        SPI_SHADER_USER_DATA_GS_7 <- 0
SET_SH_REG:
        SPI_SHADER_USER_DATA_GS_4 <- 0x016fe000
        SPI_SHADER_USER_DATA_GS_5 <- 0
SET_SH_REG:
        SPI_SHADER_USER_DATA_HS_0 <- 0x016fe400
        SPI_SHADER_USER_DATA_HS_1 <- 0
SET_SH_REG:
        SPI_SHADER_USER_DATA_HS_2 <- 0x016fe200
        SPI_SHADER_USER_DATA_HS_3 <- 0
SET_SH_REG:
        SPI_SHADER_USER_DATA_HS_6 <- 0x016fe500
        SPI_SHADER_USER_DATA_HS_7 <- 0
SET_SH_REG:
        SPI_SHADER_USER_DATA_HS_4 <- 0x016fea00
        SPI_SHADER_USER_DATA_HS_5 <- 0
SET_SH_REG:
        SPI_SHADER_USER_DATA_VS_8 <- 0x16b9f300
        SPI_SHADER_USER_DATA_VS_9 <- 0
SET_CONTEXT_REG:
        DB_ALPHA_TO_MASK <- ALPHA_TO_MASK_ENABLE = 0
                            ALPHA_TO_MASK_OFFSET0 = 2
                            ALPHA_TO_MASK_OFFSET1 = 2
                            ALPHA_TO_MASK_OFFSET2 = 2
                            ALPHA_TO_MASK_OFFSET3 = 2
                            OFFSET_ROUND = 0
SET_CONTEXT_REG:
        CB_BLEND0_CONTROL <- COLOR_SRCBLEND = BLEND_ONE
                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
                             COLOR_DESTBLEND = BLEND_SRC1_COLOR
                             ALPHA_SRCBLEND = BLEND_ZERO
                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
                             ALPHA_DESTBLEND = BLEND_ZERO
                             SEPARATE_ALPHA_BLEND = 0
                             ENABLE = 1
                             DISABLE_ROP3 = 0
        CB_BLEND1_CONTROL <- COLOR_SRCBLEND = BLEND_ONE
                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
                             COLOR_DESTBLEND = BLEND_SRC1_COLOR
                             ALPHA_SRCBLEND = BLEND_ZERO
                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
                             ALPHA_DESTBLEND = BLEND_ZERO
                             SEPARATE_ALPHA_BLEND = 0
                             ENABLE = 1
                             DISABLE_ROP3 = 0
        CB_BLEND2_CONTROL <- COLOR_SRCBLEND = BLEND_ONE
                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
                             COLOR_DESTBLEND = BLEND_SRC1_COLOR
                             ALPHA_SRCBLEND = BLEND_ZERO
                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
                             ALPHA_DESTBLEND = BLEND_ZERO
                             SEPARATE_ALPHA_BLEND = 0
                             ENABLE = 1
                             DISABLE_ROP3 = 0
        CB_BLEND3_CONTROL <- COLOR_SRCBLEND = BLEND_ONE
                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
                             COLOR_DESTBLEND = BLEND_SRC1_COLOR
                             ALPHA_SRCBLEND = BLEND_ZERO
                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
                             ALPHA_DESTBLEND = BLEND_ZERO
                             SEPARATE_ALPHA_BLEND = 0
                             ENABLE = 1
                             DISABLE_ROP3 = 0
        CB_BLEND4_CONTROL <- COLOR_SRCBLEND = BLEND_ONE
                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
                             COLOR_DESTBLEND = BLEND_SRC1_COLOR
                             ALPHA_SRCBLEND = BLEND_ZERO
                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
                             ALPHA_DESTBLEND = BLEND_ZERO
                             SEPARATE_ALPHA_BLEND = 0
                             ENABLE = 1
                             DISABLE_ROP3 = 0
        CB_BLEND5_CONTROL <- COLOR_SRCBLEND = BLEND_ONE
                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
                             COLOR_DESTBLEND = BLEND_SRC1_COLOR
                             ALPHA_SRCBLEND = BLEND_ZERO
                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
                             ALPHA_DESTBLEND = BLEND_ZERO
                             SEPARATE_ALPHA_BLEND = 0
                             ENABLE = 1
                             DISABLE_ROP3 = 0
        CB_BLEND6_CONTROL <- COLOR_SRCBLEND = BLEND_ONE
                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
                             COLOR_DESTBLEND = BLEND_SRC1_COLOR
                             ALPHA_SRCBLEND = BLEND_ZERO
                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
                             ALPHA_DESTBLEND = BLEND_ZERO
                             SEPARATE_ALPHA_BLEND = 0
                             ENABLE = 1
                             DISABLE_ROP3 = 0
        CB_BLEND7_CONTROL <- COLOR_SRCBLEND = BLEND_ONE
                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
                             COLOR_DESTBLEND = BLEND_SRC1_COLOR
                             ALPHA_SRCBLEND = BLEND_ZERO
                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
                             ALPHA_DESTBLEND = BLEND_ZERO
                             SEPARATE_ALPHA_BLEND = 0
                             ENABLE = 1
                             DISABLE_ROP3 = 0
SET_CONTEXT_REG:
        CB_COLOR_CONTROL <- DEGAMMA_ENABLE = 0
                            MODE = CB_NORMAL
                            ROP3 = X_0XCC
SET_CONTEXT_REG:
        PA_SC_AA_MASK_X0Y0_X1Y0 <- AA_MASK_X0Y0 = 0xffff
                                   AA_MASK_X1Y0 = 0xffff
        PA_SC_AA_MASK_X0Y1_X1Y1 <- AA_MASK_X0Y1 = 0xffff
                                   AA_MASK_X1Y1 = 0xffff
SET_CONTEXT_REG:
        PA_SC_VPORT_SCISSOR_0_TL <- TL_X = 0
                                    TL_Y = 0
                                    WINDOW_OFFSET_DISABLE = 1
        PA_SC_VPORT_SCISSOR_0_BR <- BR_X = 1600
                                    BR_Y = 900
SET_CONTEXT_REG:
        PA_SC_VPORT_SCISSOR_1_TL <- TL_X = 0
                                    TL_Y = 0
                                    WINDOW_OFFSET_DISABLE = 1
        PA_SC_VPORT_SCISSOR_1_BR <- BR_X = 1600
                                    BR_Y = 900
SET_CONTEXT_REG:
        PA_SC_VPORT_SCISSOR_2_TL <- TL_X = 0
                                    TL_Y = 0
                                    WINDOW_OFFSET_DISABLE = 1
        PA_SC_VPORT_SCISSOR_2_BR <- BR_X = 1600
                                    BR_Y = 900
SET_CONTEXT_REG:
        PA_SC_VPORT_SCISSOR_3_TL <- TL_X = 0
                                    TL_Y = 0
                                    WINDOW_OFFSET_DISABLE = 1
        PA_SC_VPORT_SCISSOR_3_BR <- BR_X = 1600
                                    BR_Y = 900
SET_CONTEXT_REG:
        PA_SC_VPORT_SCISSOR_4_TL <- TL_X = 0
                                    TL_Y = 0
                                    WINDOW_OFFSET_DISABLE = 1
        PA_SC_VPORT_SCISSOR_4_BR <- BR_X = 1600
                                    BR_Y = 900
SET_CONTEXT_REG:
        PA_SC_VPORT_SCISSOR_5_TL <- TL_X = 0
                                    TL_Y = 0
                                    WINDOW_OFFSET_DISABLE = 1
        PA_SC_VPORT_SCISSOR_5_BR <- BR_X = 1600
                                    BR_Y = 900
SET_CONTEXT_REG:
        PA_SC_VPORT_SCISSOR_6_TL <- TL_X = 0
                                    TL_Y = 0
                                    WINDOW_OFFSET_DISABLE = 1
        PA_SC_VPORT_SCISSOR_6_BR <- BR_X = 1600
                                    BR_Y = 900
SET_CONTEXT_REG:
        PA_SC_VPORT_SCISSOR_7_TL <- TL_X = 0
                                    TL_Y = 0
                                    WINDOW_OFFSET_DISABLE = 1
        PA_SC_VPORT_SCISSOR_7_BR <- BR_X = 1600
                                    BR_Y = 900
SET_CONTEXT_REG:
        PA_SC_VPORT_SCISSOR_8_TL <- TL_X = 0
                                    TL_Y = 0
                                    WINDOW_OFFSET_DISABLE = 1
        PA_SC_VPORT_SCISSOR_8_BR <- BR_X = 1600
                                    BR_Y = 900
SET_CONTEXT_REG:
        PA_SC_VPORT_SCISSOR_9_TL <- TL_X = 0
                                    TL_Y = 0
                                    WINDOW_OFFSET_DISABLE = 1
        PA_SC_VPORT_SCISSOR_9_BR <- BR_X = 1600
                                    BR_Y = 900
SET_CONTEXT_REG:
        PA_SC_VPORT_SCISSOR_10_TL <- TL_X = 0
                                     TL_Y = 0
                                     WINDOW_OFFSET_DISABLE = 1
        PA_SC_VPORT_SCISSOR_10_BR <- BR_X = 1600
                                     BR_Y = 900
SET_CONTEXT_REG:
        PA_SC_VPORT_SCISSOR_11_TL <- TL_X = 0
                                     TL_Y = 0
                                     WINDOW_OFFSET_DISABLE = 1
        PA_SC_VPORT_SCISSOR_11_BR <- BR_X = 1600
                                     BR_Y = 900
SET_CONTEXT_REG:
        PA_SC_VPORT_SCISSOR_12_TL <- TL_X = 0
                                     TL_Y = 0
                                     WINDOW_OFFSET_DISABLE = 1
        PA_SC_VPORT_SCISSOR_12_BR <- BR_X = 1600
                                     BR_Y = 900
SET_CONTEXT_REG:
        PA_SC_VPORT_SCISSOR_13_TL <- TL_X = 0
                                     TL_Y = 0
                                     WINDOW_OFFSET_DISABLE = 1
        PA_SC_VPORT_SCISSOR_13_BR <- BR_X = 1600
                                     BR_Y = 900
SET_CONTEXT_REG:
        PA_SC_VPORT_SCISSOR_14_TL <- TL_X = 0
                                     TL_Y = 0
                                     WINDOW_OFFSET_DISABLE = 1
        PA_SC_VPORT_SCISSOR_14_BR <- BR_X = 1600
                                     BR_Y = 900
SET_CONTEXT_REG:
        PA_SC_VPORT_SCISSOR_15_TL <- TL_X = 0
                                     TL_Y = 0
                                     WINDOW_OFFSET_DISABLE = 1
        PA_SC_VPORT_SCISSOR_15_BR <- BR_X = 1600
                                     BR_Y = 900
SET_CONTEXT_REG:
        PA_CL_VPORT_XSCALE <- 800.0f
        PA_CL_VPORT_XOFFSET <- 800.0f
        PA_CL_VPORT_YSCALE <- 450.0f
        PA_CL_VPORT_YOFFSET <- 450.0f
        PA_CL_VPORT_ZSCALE <- 0.5f
        PA_CL_VPORT_ZOFFSET <- 0.5f
SET_CONTEXT_REG:
        PA_CL_VPORT_XSCALE_1 <- 800.0f
        PA_CL_VPORT_XOFFSET_1 <- 800.0f
        PA_CL_VPORT_YSCALE_1 <- 450.0f
        PA_CL_VPORT_YOFFSET_1 <- 450.0f
        PA_CL_VPORT_ZSCALE_1 <- 0.5f
        PA_CL_VPORT_ZOFFSET_1 <- 0.5f
SET_CONTEXT_REG:
        PA_CL_VPORT_XSCALE_2 <- 800.0f
        PA_CL_VPORT_XOFFSET_2 <- 800.0f
        PA_CL_VPORT_YSCALE_2 <- 450.0f
        PA_CL_VPORT_YOFFSET_2 <- 450.0f
        PA_CL_VPORT_ZSCALE_2 <- 0.5f
        PA_CL_VPORT_ZOFFSET_2 <- 0.5f
SET_CONTEXT_REG:
        PA_CL_VPORT_XSCALE_3 <- 800.0f
        PA_CL_VPORT_XOFFSET_3 <- 800.0f
        PA_CL_VPORT_YSCALE_3 <- 450.0f
        PA_CL_VPORT_YOFFSET_3 <- 450.0f
        PA_CL_VPORT_ZSCALE_3 <- 0.5f
        PA_CL_VPORT_ZOFFSET_3 <- 0.5f
SET_CONTEXT_REG:
        PA_CL_VPORT_XSCALE_4 <- 800.0f
        PA_CL_VPORT_XOFFSET_4 <- 800.0f
        PA_CL_VPORT_YSCALE_4 <- 450.0f
        PA_CL_VPORT_YOFFSET_4 <- 450.0f
        PA_CL_VPORT_ZSCALE_4 <- 0.5f
        PA_CL_VPORT_ZOFFSET_4 <- 0.5f
SET_CONTEXT_REG:
        PA_CL_VPORT_XSCALE_5 <- 800.0f
        PA_CL_VPORT_XOFFSET_5 <- 800.0f
        PA_CL_VPORT_YSCALE_5 <- 450.0f
        PA_CL_VPORT_YOFFSET_5 <- 450.0f
        PA_CL_VPORT_ZSCALE_5 <- 0.5f
        PA_CL_VPORT_ZOFFSET_5 <- 0.5f
SET_CONTEXT_REG:
        PA_CL_VPORT_XSCALE_6 <- 800.0f
        PA_CL_VPORT_XOFFSET_6 <- 800.0f
        PA_CL_VPORT_YSCALE_6 <- 450.0f
        PA_CL_VPORT_YOFFSET_6 <- 450.0f
        PA_CL_VPORT_ZSCALE_6 <- 0.5f
        PA_CL_VPORT_ZOFFSET_6 <- 0.5f
SET_CONTEXT_REG:
        PA_CL_VPORT_XSCALE_7 <- 800.0f
        PA_CL_VPORT_XOFFSET_7 <- 800.0f
        PA_CL_VPORT_YSCALE_7 <- 450.0f
        PA_CL_VPORT_YOFFSET_7 <- 450.0f
        PA_CL_VPORT_ZSCALE_7 <- 0.5f
        PA_CL_VPORT_ZOFFSET_7 <- 0.5f
SET_CONTEXT_REG:
        PA_CL_VPORT_XSCALE_8 <- 800.0f
        PA_CL_VPORT_XOFFSET_8 <- 800.0f
        PA_CL_VPORT_YSCALE_8 <- 450.0f
        PA_CL_VPORT_YOFFSET_8 <- 450.0f
        PA_CL_VPORT_ZSCALE_8 <- 0.5f
        PA_CL_VPORT_ZOFFSET_8 <- 0.5f
SET_CONTEXT_REG:
        PA_CL_VPORT_XSCALE_9 <- 800.0f
        PA_CL_VPORT_XOFFSET_9 <- 800.0f
        PA_CL_VPORT_YSCALE_9 <- 450.0f
        PA_CL_VPORT_YOFFSET_9 <- 450.0f
        PA_CL_VPORT_ZSCALE_9 <- 0.5f
        PA_CL_VPORT_ZOFFSET_9 <- 0.5f
SET_CONTEXT_REG:
        PA_CL_VPORT_XSCALE_10 <- 800.0f
        PA_CL_VPORT_XOFFSET_10 <- 800.0f
        PA_CL_VPORT_YSCALE_10 <- 450.0f
        PA_CL_VPORT_YOFFSET_10 <- 450.0f
        PA_CL_VPORT_ZSCALE_10 <- 0.5f
        PA_CL_VPORT_ZOFFSET_10 <- 0.5f
SET_CONTEXT_REG:
        PA_CL_VPORT_XSCALE_11 <- 800.0f
        PA_CL_VPORT_XOFFSET_11 <- 800.0f
        PA_CL_VPORT_YSCALE_11 <- 450.0f
        PA_CL_VPORT_YOFFSET_11 <- 450.0f
        PA_CL_VPORT_ZSCALE_11 <- 0.5f
        PA_CL_VPORT_ZOFFSET_11 <- 0.5f
SET_CONTEXT_REG:
        PA_CL_VPORT_XSCALE_12 <- 800.0f
        PA_CL_VPORT_XOFFSET_12 <- 800.0f
        PA_CL_VPORT_YSCALE_12 <- 450.0f
        PA_CL_VPORT_YOFFSET_12 <- 450.0f
        PA_CL_VPORT_ZSCALE_12 <- 0.5f
        PA_CL_VPORT_ZOFFSET_12 <- 0.5f
SET_CONTEXT_REG:
        PA_CL_VPORT_XSCALE_13 <- 800.0f
        PA_CL_VPORT_XOFFSET_13 <- 800.0f
        PA_CL_VPORT_YSCALE_13 <- 450.0f
        PA_CL_VPORT_YOFFSET_13 <- 450.0f
        PA_CL_VPORT_ZSCALE_13 <- 0.5f
        PA_CL_VPORT_ZOFFSET_13 <- 0.5f
SET_CONTEXT_REG:
        PA_CL_VPORT_XSCALE_14 <- 800.0f
        PA_CL_VPORT_XOFFSET_14 <- 800.0f
        PA_CL_VPORT_YSCALE_14 <- 450.0f
        PA_CL_VPORT_YOFFSET_14 <- 450.0f
        PA_CL_VPORT_ZSCALE_14 <- 0.5f
        PA_CL_VPORT_ZOFFSET_14 <- 0.5f
SET_CONTEXT_REG:
        PA_CL_VPORT_XSCALE_15 <- 800.0f
        PA_CL_VPORT_XOFFSET_15 <- 800.0f
        PA_CL_VPORT_YSCALE_15 <- 450.0f
        PA_CL_VPORT_YOFFSET_15 <- 450.0f
        PA_CL_VPORT_ZSCALE_15 <- 0.5f
        PA_CL_VPORT_ZOFFSET_15 <- 0.5f
SET_CONTEXT_REG:
        SPI_INTERP_CONTROL_0 <- FLAT_SHADE_ENA = 1
                                PNT_SPRITE_ENA = 1
                                PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
                                PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
                                PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
                                PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
                                PNT_SPRITE_TOP_1 = 1
SET_CONTEXT_REG:
        PA_SU_POINT_SIZE <- HEIGHT = 8
                            WIDTH = 8
        PA_SU_POINT_MINMAX <- MIN_SIZE = 8
                              MAX_SIZE = 8
        PA_SU_LINE_CNTL <- WIDTH = 8
SET_CONTEXT_REG:
        PA_SC_MODE_CNTL_0 <- MSAA_ENABLE = 1
                             VPORT_SCISSOR_ENABLE = 0
                             LINE_STIPPLE_ENABLE = 0
                             SEND_UNLIT_STILES_TO_PKR = 0
SET_CONTEXT_REG:
        PA_SU_VTX_CNTL <- PIX_CENTER = 1
                          ROUND_MODE = X_TRUNCATE
                          QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
SET_CONTEXT_REG:
        PA_SU_POLY_OFFSET_CLAMP <- 0
SET_CONTEXT_REG:
        PA_SU_SC_MODE_CNTL <- CULL_FRONT = 0
                              CULL_BACK = 0
                              FACE = 1
                              POLY_MODE = X_DISABLE_POLY_MODE
                              POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
                              POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
                              POLY_OFFSET_FRONT_ENABLE = 0
                              POLY_OFFSET_BACK_ENABLE = 0
                              POLY_OFFSET_PARA_ENABLE = 0
                              VTX_WINDOW_OFFSET_ENABLE = 0
                              PROVOKING_VTX_LAST = 1
                              PERSP_CORR_DIS = 0
                              MULTI_PRIM_IB_ENA = 0
SET_CONTEXT_REG:
        DB_DEPTH_CONTROL <- STENCIL_ENABLE = 1
                            Z_ENABLE = 0
                            Z_WRITE_ENABLE = 0
                            DEPTH_BOUNDS_ENABLE = 0
                            ZFUNC = FRAG_NEVER
                            BACKFACE_ENABLE = 0
                            STENCILFUNC = REF_ALWAYS
                            STENCILFUNC_BF = REF_NEVER
                            ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0
                            DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0
SET_CONTEXT_REG:
        DB_STENCIL_CONTROL <- STENCILFAIL = STENCIL_REPLACE_TEST
                              STENCILZPASS = STENCIL_REPLACE_TEST
                              STENCILZFAIL = STENCIL_REPLACE_TEST
                              STENCILFAIL_BF = STENCIL_KEEP
                              STENCILZPASS_BF = STENCIL_KEEP
                              STENCILZFAIL_BF = STENCIL_KEEP
SET_CONTEXT_REG:
        PA_SU_POLY_OFFSET_FRONT_SCALE <- 0
        PA_SU_POLY_OFFSET_FRONT_OFFSET <- 0
        PA_SU_POLY_OFFSET_BACK_SCALE <- 0
        PA_SU_POLY_OFFSET_BACK_OFFSET <- 0
SET_CONTEXT_REG:
        CB_TARGET_MASK <- TARGET0_ENABLE = 15
                          TARGET1_ENABLE = 0
                          TARGET2_ENABLE = 0
                          TARGET3_ENABLE = 0
                          TARGET4_ENABLE = 0
                          TARGET5_ENABLE = 0
                          TARGET6_ENABLE = 0
                          TARGET7_ENABLE = 0
SET_CONTEXT_REG:
        DB_STENCILREFMASK <- STENCILTESTVAL = 1
                             STENCILMASK = 255
                             STENCILWRITEMASK = 255
                             STENCILOPVAL = 1
        DB_STENCILREFMASK_BF <- STENCILTESTVAL_BF = 1
                                STENCILMASK_BF = 255
                                STENCILWRITEMASK_BF = 255
                                STENCILOPVAL_BF = 1
SET_CONTEXT_REG:
        VGT_SHADER_STAGES_EN <- LS_EN = LS_STAGE_OFF
                                HS_EN = 0
                                ES_EN = ES_STAGE_OFF
                                GS_EN = 0
                                VS_EN = VS_STAGE_REAL
                                DYNAMIC_HS = 0
                                DISPATCH_DRAW_EN = 0
                                DIS_DEALLOC_ACCUM_0 = 0
                                DIS_DEALLOC_ACCUM_1 = 0
                                VS_WAVE_ID_EN = 0
SET_CONTEXT_REG:
        VGT_GS_MODE <- MODE = GS_OFF
                       CUT_MODE = GS_CUT_1024
                       GS_C_PACK_EN = 0
                       ES_PASSTHRU = 0
                       COMPUTE_MODE = 0
                       FAST_COMPUTE_MODE = 0
                       ELEMENT_INFO_EN = 0
                       PARTIAL_THD_AT_EOI = 0
                       SUPPRESS_CUTS = 0
                       ES_WRITE_OPTIMIZE = 0
                       GS_WRITE_OPTIMIZE = 0
                       ONCHIP = X_0_OFFCHIP_GS
SET_CONTEXT_REG:
        VGT_PRIMITIVEID_EN <- PRIMITIVEID_EN = 0
                              DISABLE_RESET_ON_EOI = 0
SET_CONTEXT_REG:
        SPI_VS_OUT_CONFIG <- VS_EXPORT_COUNT = 0
                             VS_HALF_PACK = 0
                             VS_EXPORTS_FOG = 0
                             VS_OUT_FOG_VEC_ADDR = 0
SET_CONTEXT_REG:
        SPI_SHADER_POS_FORMAT <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
SET_SH_REG:
        SPI_SHADER_PGM_LO_VS <- 0x0016bf00
        SPI_SHADER_PGM_HI_VS <- MEM_BASE = 0
        SPI_SHADER_PGM_RSRC1_VS <- VGPRS = 1
                                   SGPRS = 2
                                   PRIORITY = 0
                                   FLOAT_MODE = 0
                                   PRIV = 0
                                   DX10_CLAMP = 1
                                   DEBUG_MODE = 0
                                   IEEE_MODE = 0
                                   VGPR_COMP_CNT = 0
                                   CU_GROUP_ENABLE = 0
                                   CACHE_CTL = 0
                                   CDBG_USER = 0
        SPI_SHADER_PGM_RSRC2_VS <- SCRATCH_EN = 0
                                   USER_SGPR = 12
                                   TRAP_PRESENT = 0
                                   OC_LDS_EN = 0
                                   SO_BASE0_EN = 0
                                   SO_BASE1_EN = 0
                                   SO_BASE2_EN = 0
                                   SO_BASE3_EN = 0
                                   SO_EN = 0
                                   EXCP_EN = 0
                                   EXCP_EN_CIK = 0
                                   DISPATCH_DRAW_EN = 0
SET_CONTEXT_REG:
        PA_CL_VTE_CNTL <- VPORT_X_SCALE_ENA = 1
                          VPORT_X_OFFSET_ENA = 1
                          VPORT_Y_SCALE_ENA = 1
                          VPORT_Y_OFFSET_ENA = 1
                          VPORT_Z_SCALE_ENA = 1
                          VPORT_Z_OFFSET_ENA = 1
                          VTX_XY_FMT = 0
                          VTX_Z_FMT = 0
                          VTX_W0_FMT = 1
SET_CONTEXT_REG:
        SPI_BARYC_CNTL <- PERSP_CENTER_CNTL = 0
                          PERSP_CENTROID_CNTL = 0
                          LINEAR_CENTER_CNTL = 0
                          LINEAR_CENTROID_CNTL = 0
                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
                          POS_FLOAT_ULC = 0
                          FRONT_FACE_ALL_BITS = 0
SET_CONTEXT_REG:
        SPI_PS_INPUT_ENA <- PERSP_SAMPLE_ENA = 1
                            PERSP_CENTER_ENA = 0
                            PERSP_CENTROID_ENA = 0
                            PERSP_PULL_MODEL_ENA = 0
                            LINEAR_SAMPLE_ENA = 0
                            LINEAR_CENTER_ENA = 0
                            LINEAR_CENTROID_ENA = 0
                            LINE_STIPPLE_TEX_ENA = 0
                            POS_X_FLOAT_ENA = 0
                            POS_Y_FLOAT_ENA = 0
                            POS_Z_FLOAT_ENA = 0
                            POS_W_FLOAT_ENA = 0
                            FRONT_FACE_ENA = 0
                            ANCILLARY_ENA = 0
                            SAMPLE_COVERAGE_ENA = 0
                            POS_FIXED_PT_ENA = 0
        SPI_PS_INPUT_ADDR <- PERSP_SAMPLE_ENA = 1
                             PERSP_CENTER_ENA = 0
                             PERSP_CENTROID_ENA = 0
                             PERSP_PULL_MODEL_ENA = 0
                             LINEAR_SAMPLE_ENA = 0
                             LINEAR_CENTER_ENA = 0
                             LINEAR_CENTROID_ENA = 0
                             LINE_STIPPLE_TEX_ENA = 0
                             POS_X_FLOAT_ENA = 0
                             POS_Y_FLOAT_ENA = 0
                             POS_Z_FLOAT_ENA = 0
                             POS_W_FLOAT_ENA = 0
                             FRONT_FACE_ENA = 0
                             ANCILLARY_ENA = 0
                             SAMPLE_COVERAGE_ENA = 0
                             POS_FIXED_PT_ENA = 0
SET_CONTEXT_REG:
        SPI_PS_IN_CONTROL <- NUM_INTERP = 0
                             PARAM_GEN = 0
                             FOG_ADDR = 0
                             BC_OPTIMIZE_DISABLE = 1
                             PASS_FOG_THROUGH_PS = 0
SET_CONTEXT_REG:
        SPI_SHADER_Z_FORMAT <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
        SPI_SHADER_COL_FORMAT <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
SET_CONTEXT_REG:
        CB_SHADER_MASK <- OUTPUT0_ENABLE = 15
                          OUTPUT1_ENABLE = 0
                          OUTPUT2_ENABLE = 0
                          OUTPUT3_ENABLE = 0
                          OUTPUT4_ENABLE = 0
                          OUTPUT5_ENABLE = 0
                          OUTPUT6_ENABLE = 0
                          OUTPUT7_ENABLE = 0
SET_SH_REG:
        SPI_SHADER_PGM_LO_PS <- 0x0016acc0
        SPI_SHADER_PGM_HI_PS <- MEM_BASE = 0
        SPI_SHADER_PGM_RSRC1_PS <- VGPRS = 0
                                   SGPRS = 1
                                   PRIORITY = 0
                                   FLOAT_MODE = 0
                                   PRIV = 0
                                   DX10_CLAMP = 1
                                   DEBUG_MODE = 0
                                   IEEE_MODE = 0
                                   CU_GROUP_DISABLE = 0
                                   CACHE_CTL = 0
                                   CDBG_USER = 0
        SPI_SHADER_PGM_RSRC2_PS <- SCRATCH_EN = 0
                                   USER_SGPR = 9
                                   TRAP_PRESENT = 0
                                   WAVE_CNT_EN = 0
                                   EXTRA_LDS_SIZE = 0
                                   EXCP_EN = 0
                                   EXCP_EN_CIK = 0
SET_CONTEXT_REG:
        SPI_TMPRING_SIZE <- WAVES = 448
                            WAVESIZE = 0
DRAW_PREAMBLE:
        VGT_PRIMITIVE_TYPE <- PRIM_TYPE = DI_PT_TRILIST
        IA_MULTI_VGT_PARAM <- PRIMGROUP_SIZE = 127
                              PARTIAL_VS_WAVE_ON = 0
                              SWITCH_ON_EOP = 0
                              PARTIAL_ES_WAVE_ON = 0
                              SWITCH_ON_EOI = 0
                              WD_SWITCH_ON_EOP = 1
                              MAX_PRIMGRP_IN_WAVE = 0
        VGT_LS_HS_CONFIG <- NUM_PATCHES = 0
                            HS_NUM_INPUT_CP = 0
                            HS_NUM_OUTPUT_CP = 0
SET_CONTEXT_REG:
        VGT_GS_OUT_PRIM_TYPE <- OUTPRIM_TYPE = OUTPRIM_TYPE_TRISTRIP
                                OUTPRIM_TYPE_1 = 0
                                OUTPRIM_TYPE_2 = 0
                                OUTPRIM_TYPE_3 = 0
                                UNIQUE_TYPE_PER_STREAM = 0
SET_CONTEXT_REG:
        VGT_MULTI_PRIM_IB_RESET_EN <- RESET_EN = 0
NUM_INSTANCES:
        VGT_NUM_INSTANCES <- 1
SET_SH_REG:
        SPI_SHADER_USER_DATA_VS_10 <- 0
        SPI_SHADER_USER_DATA_VS_11 <- 0
DRAW_INDEX_AUTO:
        VGT_NUM_INDICES <- 3
        VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX
                              MAJOR_MODE = DI_MAJOR_MODE_0
                              NOT_EOP = 0
                              USE_OPAQUE = 0
WRITE_DATA:
        CONTROL <- ENGINE_SEL = ME
                   WR_CONFIRM = 1
                   WR_ONE_ADDR = 0
                   DST_SEL = MEMORY_SYNC
        DST_ADDR_LO <- 0x1c295000
        DST_ADDR_HI <- 0
        0x00000002
NOP:
        Trace point ID: 2
        !!!!! This is the last trace point that was reached by the CP !!!!!
EVENT_WRITE:
        VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_CB_META
        EVENT_INDEX <- 0
        INV_L2 <- 0
EVENT_WRITE:
        VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_DB_META
        EVENT_INDEX <- 0
        INV_L2 <- 0
EVENT_WRITE:
        VGT_EVENT_INITIATOR <- EVENT_TYPE = PS_PARTIAL_FLUSH
        EVENT_INDEX <- 4
        INV_L2 <- 0
ACQUIRE_MEM:
        CP_COHER_CNTL <- DEST_BASE_0_ENA = 0
                         DEST_BASE_1_ENA = 0
                         TC_SD_ACTION_ENA = 0
                         TC_NC_ACTION_ENA = 0
                         CB0_DEST_BASE_ENA = 1
                         CB1_DEST_BASE_ENA = 1
                         CB2_DEST_BASE_ENA = 1
                         CB3_DEST_BASE_ENA = 1
                         CB4_DEST_BASE_ENA = 1
                         CB5_DEST_BASE_ENA = 1
                         CB6_DEST_BASE_ENA = 1
                         CB7_DEST_BASE_ENA = 1
                         DB_DEST_BASE_ENA = 1
                         TCL1_VOL_ACTION_ENA = 0
                         TC_VOL_ACTION_ENA = 0
                         TC_WB_ACTION_ENA = 0
                         DEST_BASE_2_ENA = 0
                         DEST_BASE_3_ENA = 0
                         TCL1_ACTION_ENA = 1
                         TC_ACTION_ENA = 1
                         CB_ACTION_ENA = 1
                         DB_ACTION_ENA = 1
                         SH_KCACHE_ACTION_ENA = 0
                         SH_KCACHE_VOL_ACTION_ENA = 0
                         SH_ICACHE_ACTION_ENA = 0
                         SH_KCACHE_WB_ACTION_ENA = 0
                         SH_SD_ACTION_ENA = 0
        CP_COHER_SIZE <- 0xffffffff
        CP_COHER_SIZE_HI <- COHER_SIZE_HI_256B = 255
        CP_COHER_BASE <- 0
        CP_COHER_BASE_HI <- COHER_BASE_HI_256B = 0
        POLL_INTERVAL <- 10
WRITE_DATA:
        CONTROL <- ENGINE_SEL = ME
                   WR_CONFIRM = 1
                   WR_ONE_ADDR = 0
                   DST_SEL = MEMORY_SYNC
        DST_ADDR_LO <- 0x1c295000
        DST_ADDR_HI <- 0
        0x00000003
NOP:
        Trace point ID: 3
        !!!!! This trace point was NOT reached by the CP !!!!!
------------------- IB end -------------------
Done.