Driver vendor: X.Org
Device vendor: AMD
Device name: AMD TONGA (DRM 3.0.0, LLVM 3.7.0)

clear:
  buffers: 5
  color: {f = {0.000000, 0.000000, 0.000000, 0.000000}, ui = {0, 0, 0, 0}
  depth: 1.000000
  stencil: 0x0


*****************************************************************************
Driver-specific state:

Memory-mapped registers:
        GRBM_STATUS <- ME0PIPE0_CMDFIFO_AVAIL = 8
                       SRBM_RQ_PENDING = 1
                       ME0PIPE0_CF_RQ_PENDING = 0
                       ME0PIPE0_PF_RQ_PENDING = 0
                       GDS_DMA_RQ_PENDING = 0
                       DB_CLEAN = 1
                       CB_CLEAN = 1
                       TA_BUSY = 0
                       GDS_BUSY = 0
                       WD_BUSY_NO_DMA = 0
                       VGT_BUSY = 0
                       IA_BUSY_NO_DMA = 0
                       IA_BUSY = 0
                       SX_BUSY = 0
                       WD_BUSY = 0
                       SPI_BUSY = 0
                       BCI_BUSY = 0
                       SC_BUSY = 0
                       PA_BUSY = 0
                       DB_BUSY = 0
                       CP_COHERENCY_BUSY = 0
                       CP_BUSY = 0
                       CB_BUSY = 0
                       GUI_ACTIVE = 0
        GRBM_STATUS2 <- ME0PIPE1_CMDFIFO_AVAIL = 8
                        ME0PIPE1_CF_RQ_PENDING = 0
                        ME0PIPE1_PF_RQ_PENDING = 1
                        ME1PIPE0_RQ_PENDING = 0
                        ME1PIPE1_RQ_PENDING = 0
                        ME1PIPE2_RQ_PENDING = 0
                        ME1PIPE3_RQ_PENDING = 0
                        ME2PIPE0_RQ_PENDING = 0
                        ME2PIPE1_RQ_PENDING = 0
                        ME2PIPE2_RQ_PENDING = 1
                        ME2PIPE3_RQ_PENDING = 1
                        RLC_RQ_PENDING = 0
                        RLC_BUSY = 0
                        TC_BUSY = 0
                        TCC_CC_RESIDENT = 0
                        CPF_BUSY = 0
                        CPC_BUSY = 0
                        CPG_BUSY = 0
        GRBM_STATUS_SE0 <- DB_CLEAN = 0
                           CB_CLEAN = 0
                           BCI_BUSY = 0
                           VGT_BUSY = 0
                           PA_BUSY = 0
                           TA_BUSY = 0
                           SX_BUSY = 0
                           SPI_BUSY = 0
                           SC_BUSY = 0
                           DB_BUSY = 0
                           CB_BUSY = 0
        GRBM_STATUS_SE1 <- DB_CLEAN = 0
                           CB_CLEAN = 0
                           BCI_BUSY = 0
                           VGT_BUSY = 0
                           PA_BUSY = 0
                           TA_BUSY = 0
                           SX_BUSY = 0
                           SPI_BUSY = 0
                           SC_BUSY = 0
                           DB_BUSY = 0
                           CB_BUSY = 0
        GRBM_STATUS_SE2 <- DB_CLEAN = 0
                           CB_CLEAN = 0
                           BCI_BUSY = 0
                           VGT_BUSY = 0
                           PA_BUSY = 0
                           TA_BUSY = 0
                           SX_BUSY = 0
                           SPI_BUSY = 0
                           SC_BUSY = 0
                           DB_BUSY = 0
                           CB_BUSY = 0
        GRBM_STATUS_SE3 <- DB_CLEAN = 0
                           CB_CLEAN = 0
                           BCI_BUSY = 0
                           VGT_BUSY = 0
                           PA_BUSY = 0
                           TA_BUSY = 0
                           SX_BUSY = 0
                           SPI_BUSY = 0
                           SC_BUSY = 0
                           DB_BUSY = 0
                           CB_BUSY = 0
        CP_STAT <- ROQ_RING_BUSY = 0
                   ROQ_INDIRECT1_BUSY = 0
                   ROQ_INDIRECT2_BUSY = 0
                   ROQ_STATE_BUSY = 1
                   DC_BUSY = 1
                   ATCL2IU_BUSY = 0
                   PFP_BUSY = 0
                   MEQ_BUSY = 0
                   ME_BUSY = 0
                   QUERY_BUSY = 0
                   SEMAPHORE_BUSY = 0
                   INTERRUPT_BUSY = 0
                   SURFACE_SYNC_BUSY = 0
                   DMA_BUSY = 0
                   RCIU_BUSY = 0
                   SCRATCH_RAM_BUSY = 0
                   CPC_CPG_BUSY = 0
                   CE_BUSY = 0
                   TCIU_BUSY = 0
                   ROQ_CE_RING_BUSY = 0
                   ROQ_CE_INDIRECT1_BUSY = 0
                   ROQ_CE_INDIRECT2_BUSY = 0
                   CP_BUSY = 0
        CP_STALLED_STAT1 <- RBIU_TO_DMA_NOT_RDY_TO_RCV = 0
                            RBIU_TO_SEM_NOT_RDY_TO_RCV = 0
                            RBIU_TO_MEMWR_NOT_RDY_TO_RCV = 0
                            ME_HAS_ACTIVE_CE_BUFFER_FLAG = 0
                            ME_HAS_ACTIVE_DE_BUFFER_FLAG = 0
                            ME_STALLED_ON_TC_WR_CONFIRM = 1
                            ME_STALLED_ON_ATOMIC_RTN_DATA = 1
                            ME_WAITING_ON_TC_READ_DATA = 0
                            ME_WAITING_ON_REG_READ_DATA = 0
                            RCIU_WAITING_ON_GDS_FREE = 0
                            RCIU_WAITING_ON_GRBM_FREE = 0
                            RCIU_WAITING_ON_VGT_FREE = 0
                            RCIU_STALLED_ON_ME_READ = 0
                            RCIU_STALLED_ON_DMA_READ = 0
                            RCIU_STALLED_ON_APPEND_READ = 0
                            RCIU_HALTED_BY_REG_VIOLATION = 0
        CP_STALLED_STAT2 <- PFP_TO_CSF_NOT_RDY_TO_RCV = 0
                            PFP_TO_MEQ_NOT_RDY_TO_RCV = 0
                            PFP_TO_RCIU_NOT_RDY_TO_RCV = 0
                            PFP_TO_VGT_WRITES_PENDING = 0
                            PFP_RCIU_READ_PENDING = 1
                            PFP_WAITING_ON_BUFFER_DATA = 0
                            ME_WAIT_ON_CE_COUNTER = 0
                            ME_WAIT_ON_AVAIL_BUFFER = 0
                            GFX_CNTX_NOT_AVAIL_TO_ME = 0
                            ME_RCIU_NOT_RDY_TO_RCV = 1
                            ME_TO_CONST_NOT_RDY_TO_RCV = 1
                            ME_WAITING_DATA_FROM_PFP = 0
                            ME_WAITING_ON_PARTIAL_FLUSH = 0
                            MEQ_TO_ME_NOT_RDY_TO_RCV = 0
                            STQ_TO_ME_NOT_RDY_TO_RCV = 0
                            ME_WAITING_DATA_FROM_STQ = 0
                            PFP_STALLED_ON_TC_WR_CONFIRM = 0
                            PFP_STALLED_ON_ATOMIC_RTN_DATA = 0
                            EOPD_FIFO_NEEDS_SC_EOP_DONE = 0
                            EOPD_FIFO_NEEDS_WR_CONFIRM = 0
                            STRMO_WR_OF_PRIM_DATA_PENDING = 0
                            PIPE_STATS_WR_DATA_PENDING = 0
                            APPEND_RDY_WAIT_ON_CS_DONE = 0
                            APPEND_RDY_WAIT_ON_PS_DONE = 0
                            APPEND_WAIT_ON_WR_CONFIRM = 0
                            APPEND_ACTIVE_PARTITION = 0
                            APPEND_WAITING_TO_SEND_MEMWRITE = 0
                            SURF_SYNC_NEEDS_IDLE_CNTXS = 0
                            SURF_SYNC_NEEDS_ALL_CLEAN = 0
        CP_STALLED_STAT3 <- CE_TO_CSF_NOT_RDY_TO_RCV = 0
                            CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV = 0
                            CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER = 0
                            CE_TO_RAM_INIT_NOT_RDY = 1
                            CE_TO_RAM_DUMP_NOT_RDY = 0
                            CE_TO_RAM_WRITE_NOT_RDY = 1
                            CE_TO_INC_FIFO_NOT_RDY_TO_RCV = 0
                            CE_TO_WR_FIFO_NOT_RDY_TO_RCV = 0
                            CE_WAITING_ON_BUFFER_DATA = 0
                            CE_WAITING_ON_CE_BUFFER_FLAG = 0
                            CE_WAITING_ON_DE_COUNTER = 1
                            CE_WAITING_ON_DE_COUNTER_UNDERFLOW = 1
                            TCIU_WAITING_ON_FREE = 0
                            TCIU_WAITING_ON_TAGS = 0
                            CE_STALLED_ON_TC_WR_CONFIRM = 0
                            CE_STALLED_ON_ATOMIC_RTN_DATA = 0
                            ATCL2IU_WAITING_ON_FREE = 0
                            ATCL2IU_WAITING_ON_TAGS = 0
                            ATCL1_WAITING_ON_TRANS = 0
        CP_CPC_STATUS <- MEC1_BUSY = 0
                         MEC2_BUSY = 0
                         DC0_BUSY = 0
                         DC1_BUSY = 1
                         RCIU1_BUSY = 0
                         RCIU2_BUSY = 1
                         ROQ1_BUSY = 0
                         ROQ2_BUSY = 0
                         TCIU_BUSY = 0
                         SCRATCH_RAM_BUSY = 0
                         QU_BUSY = 1
                         ATCL2IU_BUSY = 1
                         CPG_CPC_BUSY = 0
                         CPF_CPC_BUSY = 0
                         CPC_BUSY = 0
        CP_CPC_BUSY_STAT <- MEC1_LOAD_BUSY = 0
                            MEC1_SEMAPOHRE_BUSY = 0
                            MEC1_MUTEX_BUSY = 0
                            MEC1_MESSAGE_BUSY = 1
                            MEC1_EOP_QUEUE_BUSY = 0
                            MEC1_IQ_QUEUE_BUSY = 1
                            MEC1_IB_QUEUE_BUSY = 0
                            MEC1_TC_BUSY = 0
                            MEC1_DMA_BUSY = 0
                            MEC1_PARTIAL_FLUSH_BUSY = 0
                            MEC1_PIPE0_BUSY = 0
                            MEC1_PIPE1_BUSY = 0
                            MEC1_PIPE2_BUSY = 1
                            MEC1_PIPE3_BUSY = 1
                            MEC2_LOAD_BUSY = 0
                            MEC2_SEMAPOHRE_BUSY = 0
                            MEC2_MUTEX_BUSY = 0
                            MEC2_MESSAGE_BUSY = 0
                            MEC2_EOP_QUEUE_BUSY = 0
                            MEC2_IQ_QUEUE_BUSY = 0
                            MEC2_IB_QUEUE_BUSY = 0
                            MEC2_TC_BUSY = 0
                            MEC2_DMA_BUSY = 0
                            MEC2_PARTIAL_FLUSH_BUSY = 0
                            MEC2_PIPE0_BUSY = 0
                            MEC2_PIPE1_BUSY = 0
                            MEC2_PIPE2_BUSY = 0
                            MEC2_PIPE3_BUSY = 0
        CP_CPC_STALLED_STAT1 <- RCIU_TX_FREE_STALL = 1
                                RCIU_PRIV_VIOLATION = 0
                                TCIU_TX_FREE_STALL = 0
                                MEC1_DECODING_PACKET = 0
                                MEC1_WAIT_ON_RCIU = 0
                                MEC1_WAIT_ON_RCIU_READ = 0
                                MEC1_WAIT_ON_ROQ_DATA = 1
                                MEC2_DECODING_PACKET = 0
                                MEC2_WAIT_ON_RCIU = 0
                                MEC2_WAIT_ON_RCIU_READ = 0
                                MEC2_WAIT_ON_ROQ_DATA = 0
                                ATCL2IU_WAITING_ON_FREE = 0
                                ATCL2IU_WAITING_ON_TAGS = 0
                                ATCL1_WAITING_ON_TRANS = 0
        CP_CPF_STATUS <- POST_WPTR_GFX_BUSY = 0
                         CSF_BUSY = 0
                         ROQ_ALIGN_BUSY = 0
                         ROQ_RING_BUSY = 1
                         ROQ_INDIRECT1_BUSY = 0
                         ROQ_INDIRECT2_BUSY = 0
                         ROQ_STATE_BUSY = 0
                         ROQ_CE_RING_BUSY = 0
                         ROQ_CE_INDIRECT1_BUSY = 0
                         ROQ_CE_INDIRECT2_BUSY = 0
                         SEMAPHORE_BUSY = 1
                         INTERRUPT_BUSY = 1
                         TCIU_BUSY = 0
                         HQD_BUSY = 0
                         PRT_BUSY = 0
                         ATCL2IU_BUSY = 0
                         CPF_GFX_BUSY = 0
                         CPF_CMP_BUSY = 0
                         GRBM_CPF_STAT_BUSY = 0
                         CPC_CPF_BUSY = 0
                         CPF_BUSY = 0
        CP_CPF_BUSY_STAT <- REG_BUS_FIFO_BUSY = 0
                            CSF_RING_BUSY = 0
                            CSF_INDIRECT1_BUSY = 0
                            CSF_INDIRECT2_BUSY = 1
                            CSF_STATE_BUSY = 0
                            CSF_CE_INDR1_BUSY = 1
                            CSF_CE_INDR2_BUSY = 0
                            CSF_ARBITER_BUSY = 0
                            CSF_INPUT_BUSY = 0
                            OUTSTANDING_READ_TAGS = 0
                            HPD_PROCESSING_EOP_BUSY = 0
                            HQD_DISPATCH_BUSY = 1
                            HQD_IQ_TIMER_BUSY = 1
                            HQD_DMA_OFFLOAD_BUSY = 0
                            HQD_WAIT_SEMAPHORE_BUSY = 0
                            HQD_SIGNAL_SEMAPHORE_BUSY = 0
                            HQD_MESSAGE_BUSY = 0
                            HQD_PQ_FETCHER_BUSY = 0
                            HQD_IB_FETCHER_BUSY = 0
                            HQD_IQ_FETCHER_BUSY = 0
                            HQD_EOP_FETCHER_BUSY = 0
                            HQD_CONSUMED_RPTR_BUSY = 0
                            HQD_FETCHER_ARB_BUSY = 0
                            HQD_ROQ_ALIGN_BUSY = 0
                            HQD_ROQ_EOP_BUSY = 0
                            HQD_ROQ_IQ_BUSY = 0
                            HQD_ROQ_PQ_BUSY = 0
                            HQD_ROQ_IB_BUSY = 0
                            HQD_WPTR_POLL_BUSY = 0
                            HQD_PQ_BUSY = 0
                            HQD_IB_BUSY = 0
        CP_CPF_STALLED_STAT1 <- RING_FETCHING_DATA = 0
                                INDR1_FETCHING_DATA = 0
                                INDR2_FETCHING_DATA = 0
                                STATE_FETCHING_DATA = 1
                                TCIU_WAITING_ON_FREE = 1
                                TCIU_WAITING_ON_TAGS = 0
                                ATCL2IU_WAITING_ON_FREE = 0
                                ATCL2IU_WAITING_ON_TAGS = 0
                                ATCL1_WAITING_ON_TRANS = 0
        SRBM_STATUS <- UVD_RQ_PENDING = 0
                       SAMMSP_RQ_PENDING = 0
                       ACP_RQ_PENDING = 1
                       SMU_RQ_PENDING = 0
                       GRBM_RQ_PENDING = 1
                       HI_RQ_PENDING = 0
                       VMC_BUSY = 0
                       MCB_BUSY = 0
                       MCB_NON_DISPLAY_BUSY = 0
                       MCC_BUSY = 0
                       MCD_BUSY = 1
                       VMC1_BUSY = 1
                       SEM_BUSY = 0
                       ACP_BUSY = 0
                       IH_BUSY = 0
                       UVD_BUSY = 0
                       SAMMSP_BUSY = 0
                       GCATCL2_BUSY = 0
                       OSATCL2_BUSY = 0
                       BIF_BUSY = 0
        SRBM_STATUS2 <- SDMA_RQ_PENDING = 0
                        TST_RQ_PENDING = 0
                        SDMA1_RQ_PENDING = 0
                        VCE0_RQ_PENDING = 1
                        VP8_BUSY = 0
                        SDMA_BUSY = 1
                        SDMA1_BUSY = 0
                        VCE0_BUSY = 0
                        XDMA_BUSY = 0
                        CHUB_BUSY = 0
                        SDMA2_BUSY = 0
                        SDMA3_BUSY = 0
                        SAMSCP_BUSY = 1
                        ISP_BUSY = 1
                        VCE1_BUSY = 0
                        ODE_BUSY = 0
                        SDMA2_RQ_PENDING = 0
                        SDMA3_RQ_PENDING = 0
                        SAMSCP_RQ_PENDING = 0
                        ISP_RQ_PENDING = 0
                        VCE1_RQ_PENDING = 0
        SRBM_STATUS3 <- MCC0_BUSY = 0
                        MCC1_BUSY = 0
                        MCC2_BUSY = 0
                        MCC3_BUSY = 1
                        MCC4_BUSY = 0
                        MCC5_BUSY = 1
                        MCC6_BUSY = 0
                        MCC7_BUSY = 0
                        MCD0_BUSY = 0
                        MCD1_BUSY = 0
                        MCD2_BUSY = 0
                        MCD3_BUSY = 0
                        MCD4_BUSY = 1
                        MCD5_BUSY = 1
                        MCD6_BUSY = 0
                        MCD7_BUSY = 0
        SDMA0_STATUS_REG <- IDLE = 0
                            REG_IDLE = 0
                            RB_EMPTY = 0
                            RB_FULL = 1
                            RB_CMD_IDLE = 0
                            RB_CMD_FULL = 1
                            IB_CMD_IDLE = 0
                            IB_CMD_FULL = 0
                            BLOCK_IDLE = 0
                            INSIDE_IB = 0
                            EX_IDLE = 0
                            EX_IDLE_POLL_TIMER_EXPIRE = 0
                            PACKET_READY = 1
                            MC_WR_IDLE = 1
                            SRBM_IDLE = 0
                            CONTEXT_EMPTY = 0
                            DELTA_RPTR_FULL = 0
                            RB_MC_RREQ_IDLE = 0
                            IB_MC_RREQ_IDLE = 0
                            MC_RD_IDLE = 0
                            DELTA_RPTR_EMPTY = 0
                            MC_RD_RET_STALL = 0
                            MC_RD_NO_POLL_IDLE = 0
                            PREV_CMD_IDLE = 0
                            SEM_IDLE = 0
                            SEM_REQ_STALL = 0
                            SEM_RESP_STATE = 0
                            INT_IDLE = 0
                            INT_REQ_STALL = 0
        SDMA1_STATUS_REG <- IDLE = 0
                            REG_IDLE = 0
                            RB_EMPTY = 0
                            RB_FULL = 1
                            RB_CMD_IDLE = 0
                            RB_CMD_FULL = 1
                            IB_CMD_IDLE = 0
                            IB_CMD_FULL = 0
                            BLOCK_IDLE = 0
                            INSIDE_IB = 0
                            EX_IDLE = 0
                            EX_IDLE_POLL_TIMER_EXPIRE = 0
                            PACKET_READY = 1
                            MC_WR_IDLE = 1
                            SRBM_IDLE = 0
                            CONTEXT_EMPTY = 0
                            DELTA_RPTR_FULL = 0
                            RB_MC_RREQ_IDLE = 0
                            IB_MC_RREQ_IDLE = 0
                            MC_RD_IDLE = 0
                            DELTA_RPTR_EMPTY = 0
                            MC_RD_RET_STALL = 0
                            MC_RD_NO_POLL_IDLE = 0
                            PREV_CMD_IDLE = 0
                            SEM_IDLE = 0
                            SEM_REQ_STALL = 0
                            SEM_RESP_STATE = 0
                            INT_IDLE = 0
                            INT_REQ_STALL = 0

Vertex shader disassembly:
SHADER KEY
  instance_divisors = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
  as_es = 0
  as_es = 0
	s_load_dwordx4 s[0:3], s[2:3], 0x0                    ; C00A0001 00000000
	s_nop 0                                               ; BF800000
	s_load_dwordx4 s[4:7], s[8:9], 0x0                    ; C00A0104 00000000
	s_nop 0                                               ; BF800000
	s_load_dwordx4 s[12:15], s[8:9], 0x10                 ; C00A0304 00000010
	v_add_i32_e32 v0, s10, v0                             ; 3200000A
	s_waitcnt lgkmcnt(0)                                  ; BF8C007F
	s_buffer_load_dword s8, s[0:3], 0x3c                  ; C0220200 0000003C
	s_nop 0                                               ; BF800000
	s_buffer_load_dword s9, s[0:3], 0x40                  ; C0220240 00000040
	s_nop 0                                               ; BF800000
	s_buffer_load_dword s10, s[0:3], 0x44                 ; C0220280 00000044
	s_nop 0                                               ; BF800000
	s_buffer_load_dword s11, s[0:3], 0x48                 ; C02202C0 00000048
	s_nop 0                                               ; BF800000
	s_buffer_load_dword s16, s[0:3], 0x4c                 ; C0220400 0000004C
	buffer_load_format_xyzw v[1:4], v0, s[4:7], 0 idxen   ; E00C2000 80010100
	s_nop 0                                               ; BF800000
	buffer_load_format_xyzw v[5:8], v0, s[12:15], 0 idxen ; E00C2000 80030500
	s_buffer_load_dword s4, s[0:3], 0x0                   ; C0220100 00000000
	s_nop 0                                               ; BF800000
	s_buffer_load_dword s5, s[0:3], 0x4                   ; C0220140 00000004
	s_nop 0                                               ; BF800000
	s_buffer_load_dword s6, s[0:3], 0x8                   ; C0220180 00000008
	s_nop 0                                               ; BF800000
	s_buffer_load_dword s7, s[0:3], 0xc                   ; C02201C0 0000000C
	s_nop 0                                               ; BF800000
	s_buffer_load_dword s12, s[0:3], 0x10                 ; C0220300 00000010
	s_nop 0                                               ; BF800000
	s_buffer_load_dword s13, s[0:3], 0x14                 ; C0220340 00000014
	s_nop 0                                               ; BF800000
	s_buffer_load_dword s14, s[0:3], 0x18                 ; C0220380 00000018
	s_nop 0                                               ; BF800000
	s_buffer_load_dword s15, s[0:3], 0x1c                 ; C02203C0 0000001C
	s_nop 0                                               ; BF800000
	s_buffer_load_dword s17, s[0:3], 0x20                 ; C0220440 00000020
	s_nop 0                                               ; BF800000
	s_buffer_load_dword s18, s[0:3], 0x24                 ; C0220480 00000024
	s_nop 0                                               ; BF800000
	s_buffer_load_dword s19, s[0:3], 0x28                 ; C02204C0 00000028
	s_nop 0                                               ; BF800000
	s_buffer_load_dword s20, s[0:3], 0x2c                 ; C0220500 0000002C
	s_nop 0                                               ; BF800000
	s_buffer_load_dword s21, s[0:3], 0x30                 ; C0220540 00000030
	s_nop 0                                               ; BF800000
	s_buffer_load_dword s22, s[0:3], 0x34                 ; C0220580 00000034
	s_nop 0                                               ; BF800000
	s_buffer_load_dword s23, s[0:3], 0x38                 ; C02205C0 00000038
	s_waitcnt vmcnt(0) lgkmcnt(0)                         ; BF8C0070
	v_mul_f32_e32 v0, s4, v1                              ; 0A000204
	v_mul_f32_e32 v8, s5, v1                              ; 0A100205
	v_mul_f32_e32 v9, s6, v1                              ; 0A120206
	v_mul_f32_e32 v1, s7, v1                              ; 0A020207
	v_mac_f32_e32 v0, s12, v2                             ; 2C00040C
	v_mac_f32_e32 v8, s13, v2                             ; 2C10040D
	v_mac_f32_e32 v9, s14, v2                             ; 2C12040E
	v_mac_f32_e32 v1, s15, v2                             ; 2C02040F
	v_mac_f32_e32 v0, s17, v3                             ; 2C000611
	v_mac_f32_e32 v8, s18, v3                             ; 2C100612
	v_mac_f32_e32 v9, s19, v3                             ; 2C120613
	v_mac_f32_e32 v1, s20, v3                             ; 2C020614
	v_mac_f32_e32 v0, s21, v4                             ; 2C000815
	v_mac_f32_e32 v8, s22, v4                             ; 2C100816
	v_mac_f32_e32 v9, s23, v4                             ; 2C120817
	v_mac_f32_e32 v1, s8, v4                              ; 2C020808
	v_mov_b32_e32 v2, 0xff7fffff                          ; 7E0402FF FF7FFFFF
	s_buffer_load_dword s4, s[0:3], 0x50                  ; C0220100 00000050
	s_nop 0                                               ; BF800000
	s_buffer_load_dword s5, s[0:3], 0x54                  ; C0220140 00000054
	s_nop 0                                               ; BF800000
	s_buffer_load_dword s6, s[0:3], 0x58                  ; C0220180 00000058
	s_nop 0                                               ; BF800000
	s_buffer_load_dword s7, s[0:3], 0x70                  ; C02201C0 00000070
	s_nop 0                                               ; BF800000
	s_buffer_load_dword s8, s[0:3], 0x74                  ; C0220200 00000074
	s_nop 0                                               ; BF800000
	s_buffer_load_dword s12, s[0:3], 0x78                 ; C0220300 00000078
	s_nop 0                                               ; BF800000
	s_buffer_load_dword s13, s[0:3], 0x80                 ; C0220340 00000080
	s_nop 0                                               ; BF800000
	s_buffer_load_dword s14, s[0:3], 0x84                 ; C0220380 00000084
	s_nop 0                                               ; BF800000
	s_buffer_load_dword s15, s[0:3], 0x88                 ; C02203C0 00000088
	s_nop 0                                               ; BF800000
	s_buffer_load_dword s17, s[0:3], 0x90                 ; C0220440 00000090
	v_mul_f32_e32 v3, v5, v5                              ; 0A060B05
	v_mac_f32_e32 v3, v6, v6                              ; 2C060D06
	v_mac_f32_e32 v3, v7, v7                              ; 2C060F07
	v_rsq_f32_e64 v3, |v3|                                ; D1640103 00000103
	s_buffer_load_dword s18, s[0:3], 0x94                 ; C0220480 00000094
	s_nop 0                                               ; BF800000
	s_buffer_load_dword s0, s[0:3], 0x98                  ; C0220000 00000098
	v_add_f32_e64 v4, 0, s16 clamp                        ; D1018004 00002080
	v_min_f32_e32 v3, 0x7f7fffff, v3                      ; 140606FF 7F7FFFFF
	v_max_f32_e32 v2, v3, v2                              ; 16040503
	v_mul_f32_e32 v3, v2, v5                              ; 0A060B02
	v_mul_f32_e32 v5, v2, v6                              ; 0A0A0D02
	v_mul_f32_e32 v2, v2, v7                              ; 0A040F02
	v_mov_b32_e32 v6, s9                                  ; 7E0C0209
	s_waitcnt lgkmcnt(0)                                  ; BF8C007F
	v_add_f32_e32 v6, s7, v6                              ; 020C0C07
	v_mov_b32_e32 v7, s10                                 ; 7E0E020A
	v_add_f32_e32 v7, s8, v7                              ; 020E0E08
	v_mov_b32_e32 v10, s11                                ; 7E14020B
	v_add_f32_e32 v10, s12, v10                           ; 0214140C
	v_mul_f32_e32 v3, s4, v3                              ; 0A060604
	v_mac_f32_e32 v3, s5, v5                              ; 2C060A05
	v_mac_f32_e32 v3, s6, v2                              ; 2C060406
	v_max_f32_e32 v2, 0, v3                               ; 16040680
	v_cmp_lt_f32_e32 vcc, 0, v3                           ; 7C820680
	v_cndmask_b32_e64 v3, 0, 1.0, vcc                     ; D1000003 01A9E480
	v_mac_f32_e32 v6, s13, v2                             ; 2C0C040D
	v_mac_f32_e32 v7, s14, v2                             ; 2C0E040E
	v_mac_f32_e32 v10, s15, v2                            ; 2C14040F
	v_mac_f32_e32 v6, s17, v3                             ; 2C0C0611
	v_mac_f32_e32 v7, s18, v3                             ; 2C0E0612
	v_mac_f32_e32 v10, s0, v3                             ; 2C140600
	v_add_f32_e64 v2, 0, v6 clamp                         ; D1018002 00020C80
	v_add_f32_e64 v3, 0, v7 clamp                         ; D1018003 00020E80
	v_add_f32_e64 v5, 0, v10 clamp                        ; D1018005 00021480
	exp 15, 32, 0, 0, 0, v2, v3, v5, v4                   ; C400020F 04050302
	exp 15, 12, 0, 1, 0, v0, v8, v9, v1                   ; C40008CF 01090800
	s_endpgm                                              ; BF810000


Fragment shader disassembly:
SHADER KEY
  export_16bpc = 0x3
  last_cbuf = 0
  color_two_side = 0
  alpha_func = 7
  alpha_to_one = 0
  poly_stipple = 0
	s_mov_b32 m0, s9                         ; BEFC0009
	v_interp_p1_f32 v2, v0, 0, 0, [m0]       ; D4080000
	v_interp_p2_f32 v2, [v2], v1, 0, 0, [m0] ; D4090001
	v_interp_p1_f32 v3, v0, 1, 0, [m0]       ; D40C0100
	v_interp_p2_f32 v3, [v3], v1, 1, 0, [m0] ; D40D0101
	v_interp_p1_f32 v4, v0, 2, 0, [m0]       ; D4100200
	v_interp_p2_f32 v4, [v4], v1, 2, 0, [m0] ; D4110201
	v_interp_p1_f32 v0, v0, 3, 0, [m0]       ; D4000300
	v_interp_p2_f32 v0, [v0], v1, 3, 0, [m0] ; D4010301
	v_cvt_pkrtz_f16_f32_e64 v1, v2, v3       ; D2960001 00020702
	v_cvt_pkrtz_f16_f32_e64 v0, v4, v0       ; D2960000 00020104
	exp 15, 0, 1, 1, 1, v1, v0, v1, v0       ; C4001C0F 00010001
	s_endpgm                                 ; BF810000


------------------ IB begin ------------------
CONTEXT_CONTROL:
        0x80000000
        0x80000000
SET_CONTEXT_REG:
        VGT_HOS_MAX_TESS_LEVEL <- 64.0f
        VGT_HOS_MIN_TESS_LEVEL <- 0
SET_CONTEXT_REG:
        VGT_GS_PER_ES <- GS_PER_ES = 128
        VGT_ES_PER_GS <- ES_PER_GS = 64
        VGT_GS_PER_VS <- GS_PER_VS = 2
SET_CONTEXT_REG:
        VGT_PRIMITIVEID_RESET <- 0
SET_CONTEXT_REG:
        VGT_VTX_CNT_EN <- VTX_CNT_EN = 0
SET_CONTEXT_REG:
        VGT_STRMOUT_DRAW_OPAQUE_OFFSET <- 0
SET_CONTEXT_REG:
        VGT_STRMOUT_BUFFER_CONFIG <- STREAM_0_BUFFER_EN = 0
                                     STREAM_1_BUFFER_EN = 0
                                     STREAM_2_BUFFER_EN = 0
                                     STREAM_3_BUFFER_EN = 0
SET_CONTEXT_REG:
        VGT_REUSE_OFF <- REUSE_OFF = 0
        VGT_VTX_CNT_EN <- VTX_CNT_EN = 0
SET_CONTEXT_REG:
        PA_SC_CENTROID_PRIORITY_0 <- DISTANCE_0 = 0
                                     DISTANCE_1 = 1
                                     DISTANCE_2 = 2
                                     DISTANCE_3 = 3
                                     DISTANCE_4 = 4
                                     DISTANCE_5 = 5
                                     DISTANCE_6 = 6
                                     DISTANCE_7 = 7
        PA_SC_CENTROID_PRIORITY_1 <- DISTANCE_8 = 8
                                     DISTANCE_9 = 9
                                     DISTANCE_10 = 10
                                     DISTANCE_11 = 11
                                     DISTANCE_12 = 12
                                     DISTANCE_13 = 13
                                     DISTANCE_14 = 14
                                     DISTANCE_15 = 15
SET_CONTEXT_REG:
        PA_SU_PRIM_FILTER_CNTL <- TRIANGLE_FILTER_DISABLE = 0
                                  LINE_FILTER_DISABLE = 0
                                  POINT_FILTER_DISABLE = 0
                                  RECTANGLE_FILTER_DISABLE = 0
                                  TRIANGLE_EXPAND_ENA = 0
                                  LINE_EXPAND_ENA = 0
                                  POINT_EXPAND_ENA = 0
                                  RECTANGLE_EXPAND_ENA = 0
                                  PRIM_EXPAND_CONSTANT = 0
                                  XMAX_RIGHT_EXCLUSION = 0
                                  YMAX_BOTTOM_EXCLUSION = 0
SET_CONTEXT_REG:
        PA_SC_RASTER_CONFIG <- RB_MAP_PKR0 = RASTER_CONFIG_RB_MAP_2
                               RB_MAP_PKR1 = RASTER_CONFIG_RB_MAP_0
                               RB_XSEL2 = RASTER_CONFIG_RB_XSEL2_1
                               RB_XSEL = 0
                               RB_YSEL = 0
                               PKR_MAP = RASTER_CONFIG_PKR_MAP_0
                               PKR_XSEL = RASTER_CONFIG_PKR_XSEL_0
                               PKR_YSEL = RASTER_CONFIG_PKR_YSEL_0
                               PKR_XSEL2 = RASTER_CONFIG_PKR_XSEL2_0
                               SC_MAP = RASTER_CONFIG_SC_MAP_0
                               SC_XSEL = RASTER_CONFIG_SC_XSEL_8_WIDE_TILE
                               SC_YSEL = RASTER_CONFIG_SC_YSEL_8_WIDE_TILE
                               SE_MAP = RASTER_CONFIG_SE_MAP_2
                               SE_XSEL = RASTER_CONFIG_SE_XSEL_16_WIDE_TILE
                               SE_YSEL = RASTER_CONFIG_SE_YSEL_16_WIDE_TILE
        PA_SC_RASTER_CONFIG_1 <- SE_PAIR_MAP = RASTER_CONFIG_SE_PAIR_MAP_2
                                 SE_PAIR_XSEL = RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE
                                 SE_PAIR_YSEL = RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE
SET_CONTEXT_REG:
        PA_SC_WINDOW_SCISSOR_TL <- TL_X = 0
                                   TL_Y = 0
                                   WINDOW_OFFSET_DISABLE = 1
SET_CONTEXT_REG:
        PA_SC_GENERIC_SCISSOR_TL <- TL_X = 0
                                    TL_Y = 0
                                    WINDOW_OFFSET_DISABLE = 1
        PA_SC_GENERIC_SCISSOR_BR <- BR_X = 16384
                                    BR_Y = 16384
SET_CONTEXT_REG:
        PA_SC_SCREEN_SCISSOR_TL <- TL_X = 0
                                   TL_Y = 0
        PA_SC_SCREEN_SCISSOR_BR <- BR_X = 16384
                                   BR_Y = 16384
SET_CONTEXT_REG:
        PA_SC_CLIPRECT_RULE <- CLIP_RULE = 0x0000ffff
SET_CONTEXT_REG:
        PA_SC_EDGERULE <- ER_TRI = 10
                          ER_POINT = 10
                          ER_RECT = 10
                          ER_LINE_LR = 42
                          ER_LINE_RL = 42
                          ER_LINE_TB = 10
                          ER_LINE_BT = 10
        PA_SU_HARDWARE_SCREEN_OFFSET <- HW_SCREEN_OFFSET_X = 0
                                        HW_SCREEN_OFFSET_Y = 0
SET_CONTEXT_REG:
        PA_SC_VPORT_ZMIN_0 <- 0
        PA_SC_VPORT_ZMAX_0 <- 1.0f
SET_CONTEXT_REG:
        PA_CL_NANINF_CNTL <- VTE_XY_INF_DISCARD = 0
                             VTE_Z_INF_DISCARD = 0
                             VTE_W_INF_DISCARD = 0
                             VTE_0XNANINF_IS_0 = 0
                             VTE_XY_NAN_RETAIN = 0
                             VTE_Z_NAN_RETAIN = 0
                             VTE_W_NAN_RETAIN = 0
                             VTE_W_RECIP_NAN_IS_0 = 0
                             VS_XY_NAN_TO_INF = 0
                             VS_XY_INF_RETAIN = 0
                             VS_Z_NAN_TO_INF = 0
                             VS_Z_INF_RETAIN = 0
                             VS_W_NAN_TO_INF = 0
                             VS_W_INF_RETAIN = 0
                             VS_CLIP_DIST_INF_DISCARD = 0
                             VTE_NO_OUTPUT_NEG_0 = 0
SET_CONTEXT_REG:
        PA_CL_GB_VERT_CLIP_ADJ <- 1.0f
        PA_CL_GB_VERT_DISC_ADJ <- 1.0f
        PA_CL_GB_HORZ_CLIP_ADJ <- 1.0f
        PA_CL_GB_HORZ_DISC_ADJ <- 1.0f
SET_CONTEXT_REG:
        DB_STENCIL_CLEAR <- CLEAR = 0
SET_CONTEXT_REG:
        DB_SRESULTS_COMPARE_STATE0 <- COMPAREFUNC0 = REF_NEVER
                                      COMPAREVALUE0 = 0
                                      COMPAREMASK0 = 0
                                      ENABLE0 = 0
        DB_SRESULTS_COMPARE_STATE1 <- COMPAREFUNC1 = REF_NEVER
                                      COMPAREVALUE1 = 0
                                      COMPAREMASK1 = 0
                                      ENABLE1 = 0
        DB_PRELOAD_CONTROL <- START_X = 0
                              START_Y = 0
                              MAX_X = 0
                              MAX_Y = 0
SET_CONTEXT_REG:
        DB_RENDER_OVERRIDE <- FORCE_HIZ_ENABLE = FORCE_OFF
                              FORCE_HIS_ENABLE0 = FORCE_DISABLE
                              FORCE_HIS_ENABLE1 = FORCE_DISABLE
                              FORCE_SHADER_Z_ORDER = 0
                              FAST_Z_DISABLE = 0
                              FAST_STENCIL_DISABLE = 1
                              NOOP_CULL_DISABLE = 0
                              FORCE_COLOR_KILL = 0
                              FORCE_Z_READ = 0
                              FORCE_STENCIL_READ = 0
                              FORCE_FULL_Z_RANGE = FORCE_OFF
                              FORCE_QC_SMASK_CONFLICT = 0
                              DISABLE_VIEWPORT_CLAMP = 0
                              IGNORE_SC_ZRANGE = 0
                              DISABLE_FULLY_COVERED = 0
                              FORCE_Z_LIMIT_SUMM = FORCE_SUMM_OFF
                              MAX_TILES_IN_DTT = 0
                              DISABLE_TILE_RATE_TILES = 0
                              FORCE_Z_DIRTY = 0
                              FORCE_STENCIL_DIRTY = 0
                              FORCE_Z_VALID = 0
                              FORCE_STENCIL_VALID = 0
                              PRESERVE_COMPRESSION = 0
SET_CONTEXT_REG:
        VGT_MAX_VTX_INDX <- 0xffffffff
        VGT_MIN_VTX_INDX <- 0
        VGT_INDX_OFFSET <- 0
SET_SH_REG:
        SPI_SHADER_PGM_RSRC3_LS <- CU_EN = 0x0000fffc
                                   WAVE_LIMIT = 0
                                   LOCK_LOW_THRESHOLD = 0
                                   GROUP_FIFO_DEPTH = 0
SET_SH_REG:
        SPI_SHADER_PGM_RSRC3_HS <- WAVE_LIMIT = 0
                                   LOCK_LOW_THRESHOLD = 0
                                   GROUP_FIFO_DEPTH = 0
SET_SH_REG:
        SPI_SHADER_PGM_RSRC3_ES <- CU_EN = 0x0000fffe
                                   WAVE_LIMIT = 0
                                   LOCK_LOW_THRESHOLD = 0
                                   GROUP_FIFO_DEPTH = 0
SET_SH_REG:
        SPI_SHADER_PGM_RSRC3_GS <- CU_EN = 0x0000ffff
                                   WAVE_LIMIT = 0
                                   LOCK_LOW_THRESHOLD = 0
                                   GROUP_FIFO_DEPTH = 0
SET_SH_REG:
        SPI_SHADER_PGM_RSRC3_VS <- CU_EN = 0x0000ffff
                                   WAVE_LIMIT = 0
                                   LOCK_LOW_THRESHOLD = 0
        SPI_SHADER_LATE_ALLOC_VS <- LIMIT = 0
SET_SH_REG:
        SPI_SHADER_PGM_RSRC3_PS <- CU_EN = 0x0000ffff
                                   WAVE_LIMIT = 0
                                   LOCK_LOW_THRESHOLD = 0
SET_CONTEXT_REG:
        CB_DCC_CONTROL <- OVERWRITE_COMBINER_DISABLE = 0
                          OVERWRITE_COMBINER_MRT_SHARING_DISABLE = 1
                          OVERWRITE_COMBINER_WATERMARK = 0
SET_CONTEXT_REG:
        VGT_VERTEX_REUSE_BLOCK_CNTL <- VTX_REUSE_DEPTH = 30
        VGT_OUT_DEALLOC_CNTL <- DEALLOC_DIST = 32
EVENT_WRITE:
        VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_CB_META
        EVENT_INDEX <- 0
        INV_L2 <- 0
EVENT_WRITE:
        VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_DB_META
        EVENT_INDEX <- 0
        INV_L2 <- 0
EVENT_WRITE:
        VGT_EVENT_INITIATOR <- EVENT_TYPE = PS_PARTIAL_FLUSH
        EVENT_INDEX <- 4
        INV_L2 <- 0
ACQUIRE_MEM:
        CP_COHER_CNTL <- DEST_BASE_0_ENA = 0
                         DEST_BASE_1_ENA = 0
                         TC_SD_ACTION_ENA = 0
                         TC_NC_ACTION_ENA = 0
                         CB0_DEST_BASE_ENA = 1
                         CB1_DEST_BASE_ENA = 1
                         CB2_DEST_BASE_ENA = 1
                         CB3_DEST_BASE_ENA = 1
                         CB4_DEST_BASE_ENA = 1
                         CB5_DEST_BASE_ENA = 1
                         CB6_DEST_BASE_ENA = 1
                         CB7_DEST_BASE_ENA = 1
                         DB_DEST_BASE_ENA = 1
                         TCL1_VOL_ACTION_ENA = 0
                         TC_VOL_ACTION_ENA = 0
                         TC_WB_ACTION_ENA = 1
                         DEST_BASE_2_ENA = 0
                         DEST_BASE_3_ENA = 0
                         TCL1_ACTION_ENA = 1
                         TC_ACTION_ENA = 1
                         CB_ACTION_ENA = 1
                         DB_ACTION_ENA = 1
                         SH_KCACHE_ACTION_ENA = 1
                         SH_KCACHE_VOL_ACTION_ENA = 0
                         SH_ICACHE_ACTION_ENA = 1
                         SH_KCACHE_WB_ACTION_ENA = 0
                         SH_SD_ACTION_ENA = 0
        CP_COHER_SIZE <- 0xffffffff
        CP_COHER_SIZE_HI <- COHER_SIZE_HI_256B = 255
        CP_COHER_BASE <- 0
        CP_COHER_BASE_HI <- COHER_BASE_HI_256B = 0
        POLL_INTERVAL <- 10
DMA_DATA:
        0xc0000000
        0x00000000
        0x00000000
        0x01ad0000
        0x00000000
        0x40000800
EVENT_WRITE:
        VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_CB_META
        EVENT_INDEX <- 0
        INV_L2 <- 0
EVENT_WRITE:
        VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_DB_META
        EVENT_INDEX <- 0
        INV_L2 <- 0
ACQUIRE_MEM:
        CP_COHER_CNTL <- DEST_BASE_0_ENA = 0
                         DEST_BASE_1_ENA = 0
                         TC_SD_ACTION_ENA = 0
                         TC_NC_ACTION_ENA = 0
                         CB0_DEST_BASE_ENA = 1
                         CB1_DEST_BASE_ENA = 1
                         CB2_DEST_BASE_ENA = 1
                         CB3_DEST_BASE_ENA = 1
                         CB4_DEST_BASE_ENA = 1
                         CB5_DEST_BASE_ENA = 1
                         CB6_DEST_BASE_ENA = 1
                         CB7_DEST_BASE_ENA = 1
                         DB_DEST_BASE_ENA = 1
                         TCL1_VOL_ACTION_ENA = 0
                         TC_VOL_ACTION_ENA = 0
                         TC_WB_ACTION_ENA = 0
                         DEST_BASE_2_ENA = 0
                         DEST_BASE_3_ENA = 0
                         TCL1_ACTION_ENA = 0
                         TC_ACTION_ENA = 0
                         CB_ACTION_ENA = 1
                         DB_ACTION_ENA = 1
                         SH_KCACHE_ACTION_ENA = 0
                         SH_KCACHE_VOL_ACTION_ENA = 0
                         SH_ICACHE_ACTION_ENA = 0
                         SH_KCACHE_WB_ACTION_ENA = 0
                         SH_SD_ACTION_ENA = 0
        CP_COHER_SIZE <- 0xffffffff
        CP_COHER_SIZE_HI <- COHER_SIZE_HI_256B = 255
        CP_COHER_BASE <- 0
        CP_COHER_BASE_HI <- COHER_BASE_HI_256B = 0
        POLL_INTERVAL <- 10
SET_CONTEXT_REG:
        VGT_STRMOUT_BUFFER_CONFIG <- STREAM_0_BUFFER_EN = 0
                                     STREAM_1_BUFFER_EN = 0
                                     STREAM_2_BUFFER_EN = 0
                                     STREAM_3_BUFFER_EN = 0
SET_CONTEXT_REG:
        VGT_STRMOUT_CONFIG <- STREAMOUT_0_EN = 0
                              STREAMOUT_1_EN = 0
                              STREAMOUT_2_EN = 0
                              STREAMOUT_3_EN = 0
                              RAST_STREAM = 0
                              RAST_STREAM_MASK = 0
                              USE_RAST_STREAM_MASK = 0
SET_CONTEXT_REG:
        CB_COLOR0_BASE <- 0x00019000
        CB_COLOR0_PITCH <- TILE_MAX = 63
                           FMASK_TILE_MAX = 63
        CB_COLOR0_SLICE <- TILE_MAX = 3071
        CB_COLOR0_VIEW <- SLICE_START = 0
                          SLICE_MAX = 0
        CB_COLOR0_INFO <- ENDIAN = ENDIAN_NONE
                          FORMAT = COLOR_8_8_8_8
                          LINEAR_GENERAL = 0
                          NUMBER_TYPE = NUMBER_UNORM
                          COMP_SWAP = SWAP_ALT
                          FAST_CLEAR = 1
                          COMPRESSION = 0
                          BLEND_CLAMP = 1
                          BLEND_BYPASS = 0
                          SIMPLE_FLOAT = 0
                          ROUND_MODE = 0
                          CMASK_IS_LINEAR = 0
                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
                          FMASK_COMPRESSION_DISABLE = 0
                          FMASK_COMPRESS_1FRAG_ONLY = 0
                          DCC_ENABLE = 0
                          CMASK_ADDR_TYPE = 0
        CB_COLOR0_ATTRIB <- TILE_MODE_INDEX = 10
                            FMASK_TILE_MODE_INDEX = 10
                            FMASK_BANK_HEIGHT = 0
                            NUM_SAMPLES = 0
                            NUM_FRAGMENTS = 0
                            FORCE_DST_ALPHA_1 = 1
        CB_COLOR0_DCC_CONTROL <- OVERWRITE_COMBINER_DISABLE = 1
                                 KEY_CLEAR_ENABLE = 0
                                 MAX_UNCOMPRESSED_BLOCK_SIZE = 0
                                 MIN_COMPRESSED_BLOCK_SIZE = 0
                                 MAX_COMPRESSED_BLOCK_SIZE = 0
                                 COLOR_TRANSFORM = 0
                                 INDEPENDENT_64B_BLOCKS = 0
                                 LOSSY_RGB_PRECISION = 0
                                 LOSSY_ALPHA_PRECISION = 0
        CB_COLOR0_CMASK <- 0x0001ad00
        CB_COLOR0_CMASK_SLICE <- TILE_MAX = 15
        CB_COLOR0_FMASK <- 0x00019000
        CB_COLOR0_FMASK_SLICE <- TILE_MAX = 3071
        CB_COLOR0_CLEAR_WORD0 <- 0xff000000
        CB_COLOR0_CLEAR_WORD1 <- 0
        CB_COLOR0_DCC_BASE <- 0
SET_CONTEXT_REG:
        CB_COLOR1_INFO <- ENDIAN = ENDIAN_NONE
                          FORMAT = COLOR_8_8_8_8
                          LINEAR_GENERAL = 0
                          NUMBER_TYPE = NUMBER_UNORM
                          COMP_SWAP = SWAP_ALT
                          FAST_CLEAR = 1
                          COMPRESSION = 0
                          BLEND_CLAMP = 1
                          BLEND_BYPASS = 0
                          SIMPLE_FLOAT = 0
                          ROUND_MODE = 0
                          CMASK_IS_LINEAR = 0
                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
                          FMASK_COMPRESSION_DISABLE = 0
                          FMASK_COMPRESS_1FRAG_ONLY = 0
                          DCC_ENABLE = 0
                          CMASK_ADDR_TYPE = 0
SET_CONTEXT_REG:
        CB_COLOR2_INFO <- ENDIAN = ENDIAN_NONE
                          FORMAT = COLOR_INVALID
                          LINEAR_GENERAL = 0
                          NUMBER_TYPE = NUMBER_UNORM
                          COMP_SWAP = SWAP_STD
                          FAST_CLEAR = 0
                          COMPRESSION = 0
                          BLEND_CLAMP = 0
                          BLEND_BYPASS = 0
                          SIMPLE_FLOAT = 0
                          ROUND_MODE = 0
                          CMASK_IS_LINEAR = 0
                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
                          FMASK_COMPRESSION_DISABLE = 0
                          FMASK_COMPRESS_1FRAG_ONLY = 0
                          DCC_ENABLE = 0
                          CMASK_ADDR_TYPE = 0
SET_CONTEXT_REG:
        CB_COLOR3_INFO <- ENDIAN = ENDIAN_NONE
                          FORMAT = COLOR_INVALID
                          LINEAR_GENERAL = 0
                          NUMBER_TYPE = NUMBER_UNORM
                          COMP_SWAP = SWAP_STD
                          FAST_CLEAR = 0
                          COMPRESSION = 0
                          BLEND_CLAMP = 0
                          BLEND_BYPASS = 0
                          SIMPLE_FLOAT = 0
                          ROUND_MODE = 0
                          CMASK_IS_LINEAR = 0
                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
                          FMASK_COMPRESSION_DISABLE = 0
                          FMASK_COMPRESS_1FRAG_ONLY = 0
                          DCC_ENABLE = 0
                          CMASK_ADDR_TYPE = 0
SET_CONTEXT_REG:
        CB_COLOR4_INFO <- ENDIAN = ENDIAN_NONE
                          FORMAT = COLOR_INVALID
                          LINEAR_GENERAL = 0
                          NUMBER_TYPE = NUMBER_UNORM
                          COMP_SWAP = SWAP_STD
                          FAST_CLEAR = 0
                          COMPRESSION = 0
                          BLEND_CLAMP = 0
                          BLEND_BYPASS = 0
                          SIMPLE_FLOAT = 0
                          ROUND_MODE = 0
                          CMASK_IS_LINEAR = 0
                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
                          FMASK_COMPRESSION_DISABLE = 0
                          FMASK_COMPRESS_1FRAG_ONLY = 0
                          DCC_ENABLE = 0
                          CMASK_ADDR_TYPE = 0
SET_CONTEXT_REG:
        CB_COLOR5_INFO <- ENDIAN = ENDIAN_NONE
                          FORMAT = COLOR_INVALID
                          LINEAR_GENERAL = 0
                          NUMBER_TYPE = NUMBER_UNORM
                          COMP_SWAP = SWAP_STD
                          FAST_CLEAR = 0
                          COMPRESSION = 0
                          BLEND_CLAMP = 0
                          BLEND_BYPASS = 0
                          SIMPLE_FLOAT = 0
                          ROUND_MODE = 0
                          CMASK_IS_LINEAR = 0
                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
                          FMASK_COMPRESSION_DISABLE = 0
                          FMASK_COMPRESS_1FRAG_ONLY = 0
                          DCC_ENABLE = 0
                          CMASK_ADDR_TYPE = 0
SET_CONTEXT_REG:
        CB_COLOR6_INFO <- ENDIAN = ENDIAN_NONE
                          FORMAT = COLOR_INVALID
                          LINEAR_GENERAL = 0
                          NUMBER_TYPE = NUMBER_UNORM
                          COMP_SWAP = SWAP_STD
                          FAST_CLEAR = 0
                          COMPRESSION = 0
                          BLEND_CLAMP = 0
                          BLEND_BYPASS = 0
                          SIMPLE_FLOAT = 0
                          ROUND_MODE = 0
                          CMASK_IS_LINEAR = 0
                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
                          FMASK_COMPRESSION_DISABLE = 0
                          FMASK_COMPRESS_1FRAG_ONLY = 0
                          DCC_ENABLE = 0
                          CMASK_ADDR_TYPE = 0
SET_CONTEXT_REG:
        CB_COLOR7_INFO <- ENDIAN = ENDIAN_NONE
                          FORMAT = COLOR_INVALID
                          LINEAR_GENERAL = 0
                          NUMBER_TYPE = NUMBER_UNORM
                          COMP_SWAP = SWAP_STD
                          FAST_CLEAR = 0
                          COMPRESSION = 0
                          BLEND_CLAMP = 0
                          BLEND_BYPASS = 0
                          SIMPLE_FLOAT = 0
                          ROUND_MODE = 0
                          CMASK_IS_LINEAR = 0
                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
                          FMASK_COMPRESSION_DISABLE = 0
                          FMASK_COMPRESS_1FRAG_ONLY = 0
                          DCC_ENABLE = 0
                          CMASK_ADDR_TYPE = 0
SET_CONTEXT_REG:
        DB_DEPTH_VIEW <- SLICE_START = 0
                         SLICE_MAX = 0
                         Z_READ_ONLY = 0
                         STENCIL_READ_ONLY = 0
SET_CONTEXT_REG:
        DB_HTILE_DATA_BASE <- 0x00018300
SET_CONTEXT_REG:
        DB_DEPTH_INFO <- ADDR5_SWIZZLE_MASK = 1
                         ARRAY_MODE = ARRAY_2D_TILED_THIN1
                         PIPE_CONFIG = X_ADDR_SURF_P8_32X32_16X16
                         BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1
                         BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4
                         MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4
                         NUM_BANKS = ADDR_SURF_16_BANK
        DB_Z_INFO <- FORMAT = Z_24
                     NUM_SAMPLES = 0
                     TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
                     TILE_MODE_INDEX = 0
                     DECOMPRESS_ON_N_ZPLANES = 0
                     ALLOW_EXPCLEAR = 1
                     READ_SIZE = 0
                     TILE_SURFACE_ENABLE = 1
                     CLEAR_DISALLOWED = 0
                     ZRANGE_PRECISION = 1
        DB_STENCIL_INFO <- FORMAT = STENCIL_INVALID
                           TILE_SPLIT = ADDR_SURF_TILE_SPLIT_1KB
                           TILE_MODE_INDEX = 0
                           ALLOW_EXPCLEAR = 0
                           TILE_STENCIL_DISABLE = 1
                           CLEAR_DISALLOWED = 0
        DB_Z_READ_BASE <- 0x00018400
        DB_STENCIL_READ_BASE <- 0x00018400
        DB_Z_WRITE_BASE <- 0x00018400
        DB_STENCIL_WRITE_BASE <- 0x00018400
        DB_DEPTH_SIZE <- PITCH_TILE_MAX = 63
                         HEIGHT_TILE_MAX = 47
        DB_DEPTH_SLICE <- SLICE_TILE_MAX = 3071
SET_CONTEXT_REG:
        DB_HTILE_SURFACE <- LINEAR = 0
                            FULL_CACHE = 1
                            HTILE_USES_PRELOAD_WIN = 0
                            PRELOAD = 0
                            PREFETCH_WIDTH = 0
                            PREFETCH_HEIGHT = 0
                            DST_OUTSIDE_ZERO_TO_ONE = 0
                            TC_COMPATIBLE = 0
SET_CONTEXT_REG:
        DB_DEPTH_CLEAR <- 1.0f
SET_CONTEXT_REG:
        PA_SU_POLY_OFFSET_DB_FMT_CNTL <- POLY_OFFSET_NEG_NUM_DB_BITS = 232
                                         POLY_OFFSET_DB_IS_FLOAT_FMT = 0
SET_CONTEXT_REG:
        PA_SC_WINDOW_SCISSOR_BR <- BR_X = 300
                                   BR_Y = 300
SET_CONTEXT_REG:
        PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 <- S0_X = 14
                                             S0_Y = 11
                                             S1_X = 3
                                             S1_Y = 12
                                             S2_X = 15
                                             S2_Y = 5
                                             S3_X = 10
                                             S3_Y = 14
        PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 <- S4_X = 6
                                             S4_Y = 0
                                             S5_X = 0
                                             S5_Y = 0
                                             S6_X = 11
                                             S6_Y = 3
                                             S7_X = 4
                                             S7_Y = 4
        PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 <- S8_X = 0
                                             S8_Y = 0
                                             S9_X = 0
                                             S9_Y = 0
                                             S10_X = 0
                                             S10_Y = 0
                                             S11_X = 0
                                             S11_Y = 0
        PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 <- S12_X = 0
                                             S12_Y = 0
                                             S13_X = 0
                                             S13_Y = 0
                                             S14_X = 0
                                             S14_Y = 0
                                             S15_X = 0
                                             S15_Y = 0
        PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 <- S0_X = 14
                                             S0_Y = 11
                                             S1_X = 3
                                             S1_Y = 12
                                             S2_X = 15
                                             S2_Y = 5
                                             S3_X = 10
                                             S3_Y = 14
        PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 <- S4_X = 6
                                             S4_Y = 0
                                             S5_X = 0
                                             S5_Y = 0
                                             S6_X = 11
                                             S6_Y = 3
                                             S7_X = 4
                                             S7_Y = 4
        PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 <- S8_X = 0
                                             S8_Y = 0
                                             S9_X = 0
                                             S9_Y = 0
                                             S10_X = 0
                                             S10_Y = 0
                                             S11_X = 0
                                             S11_Y = 0
        PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 <- S12_X = 0
                                             S12_Y = 0
                                             S13_X = 0
                                             S13_Y = 0
                                             S14_X = 0
                                             S14_Y = 0
                                             S15_X = 0
                                             S15_Y = 0
        PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 <- S0_X = 14
                                             S0_Y = 11
                                             S1_X = 3
                                             S1_Y = 12
                                             S2_X = 15
                                             S2_Y = 5
                                             S3_X = 10
                                             S3_Y = 14
        PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 <- S4_X = 6
                                             S4_Y = 0
                                             S5_X = 0
                                             S5_Y = 0
                                             S6_X = 11
                                             S6_Y = 3
                                             S7_X = 4
                                             S7_Y = 4
        PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 <- S8_X = 0
                                             S8_Y = 0
                                             S9_X = 0
                                             S9_Y = 0
                                             S10_X = 0
                                             S10_Y = 0
                                             S11_X = 0
                                             S11_Y = 0
        PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 <- S12_X = 0
                                             S12_Y = 0
                                             S13_X = 0
                                             S13_Y = 0
                                             S14_X = 0
                                             S14_Y = 0
                                             S15_X = 0
                                             S15_Y = 0
        PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 <- S0_X = 14
                                             S0_Y = 11
                                             S1_X = 3
                                             S1_Y = 12
                                             S2_X = 15
                                             S2_Y = 5
                                             S3_X = 10
                                             S3_Y = 14
        PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 <- S4_X = 6
                                             S4_Y = 0
                                             S5_X = 0
                                             S5_Y = 0
                                             S6_X = 11
                                             S6_Y = 3
                                             S7_X = 4
                                             S7_Y = 4
SET_CONTEXT_REG:
        DB_RENDER_CONTROL <- DEPTH_CLEAR_ENABLE = 1
                             STENCIL_CLEAR_ENABLE = 0
                             DEPTH_COPY = 0
                             STENCIL_COPY = 0
                             RESUMMARIZE_ENABLE = 0
                             STENCIL_COMPRESS_DISABLE = 0
                             DEPTH_COMPRESS_DISABLE = 0
                             COPY_CENTROID = 0
                             COPY_SAMPLE = 0
                             DECOMPRESS_ENABLE = 0
        DB_COUNT_CONTROL <- ZPASS_INCREMENT_DISABLE = 0
                            PERFECT_ZPASS_COUNTS = 0
                            SAMPLE_RATE = 0
                            ZPASS_ENABLE = 0
                            ZFAIL_ENABLE = 0
                            SFAIL_ENABLE = 0
                            DBFAIL_ENABLE = 0
                            SLICE_EVEN_ENABLE = 0
                            SLICE_ODD_ENABLE = 0
SET_CONTEXT_REG:
        DB_RENDER_OVERRIDE2 <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
                               DISABLE_COLOR_ON_VALIDATION = 0
                               DECOMPRESS_Z_ON_FLUSH = 0
                               DISABLE_REG_SNOOP = 0
                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
                               SEPARATE_HIZS_FUNC_ENABLE = 0
                               HIZ_ZFUNC = 0
                               HIS_SFUNC_FF = 0
                               HIS_SFUNC_BF = 0
                               PRESERVE_ZRANGE = 0
                               PRESERVE_SRESULTS = 0
                               DISABLE_FAST_PASS = 0
SET_CONTEXT_REG:
        DB_SHADER_CONTROL <- Z_EXPORT_ENABLE = 0
                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
                             Z_ORDER = EARLY_Z_THEN_LATE_Z
                             KILL_ENABLE = 0
                             COVERAGE_TO_MASK_ENABLE = 0
                             MASK_EXPORT_ENABLE = 0
                             EXEC_ON_HIER_FAIL = 0
                             EXEC_ON_NOOP = 0
                             ALPHA_TO_MASK_DISABLE = 0
                             DEPTH_BEFORE_SHADER = 0
                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
SET_CONTEXT_REG:
        PA_SC_LINE_CNTL <- EXPAND_LINE_WIDTH = 0
                           LAST_PIXEL = 1
                           PERPENDICULAR_ENDCAP_ENA = 0
                           DX10_DIAMOND_TEST_ENA = 0
        PA_SC_AA_CONFIG <- MSAA_NUM_SAMPLES = 0
                           AA_MASK_CENTROID_DTMN = 0
                           MAX_SAMPLE_DIST = 0
                           MSAA_EXPOSED_SAMPLES = 0
                           DETAIL_TO_EXPOSED_MODE = 0
SET_CONTEXT_REG:
        DB_EQAA <- MAX_ANCHOR_SAMPLES = 0
                   PS_ITER_SAMPLES = 0
                   MASK_EXPORT_NUM_SAMPLES = 0
                   ALPHA_TO_MASK_NUM_SAMPLES = 0
                   HIGH_QUALITY_INTERSECTIONS = 1
                   INCOHERENT_EQAA_READS = 0
                   INTERPOLATE_COMP_Z = 0
                   INTERPOLATE_SRC_Z = 0
                   STATIC_ANCHOR_ASSOCIATIONS = 1
                   ALPHA_TO_MASK_EQAA_DISABLE = 0
                   OVERRASTERIZATION_AMOUNT = 0
                   ENABLE_POSTZ_OVERRASTERIZATION = 0
SET_CONTEXT_REG:
        PA_SC_MODE_CNTL_1 <- WALK_SIZE = 0
                             WALK_ALIGNMENT = 0
                             WALK_ALIGN8_PRIM_FITS_ST = 0
                             WALK_FENCE_ENABLE = 0
                             WALK_FENCE_SIZE = 0
                             SUPERTILE_WALK_ORDER_ENABLE = 0
                             TILE_WALK_ORDER_ENABLE = 0
                             TILE_COVER_DISABLE = 0
                             TILE_COVER_NO_SCISSOR = 0
                             ZMM_LINE_EXTENT = 0
                             ZMM_LINE_OFFSET = 0
                             ZMM_RECT_EXTENT = 0
                             KILL_PIX_POST_HI_Z = 0
                             KILL_PIX_POST_DETAIL_MASK = 0
                             PS_ITER_SAMPLE = 0
                             MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE = 0
                             MULTI_GPU_SUPERTILE_ENABLE = 0
                             GPU_ID_OVERRIDE_ENABLE = 0
                             GPU_ID_OVERRIDE = 0
                             MULTI_GPU_PRIM_DISCARD_ENABLE = 0
                             FORCE_EOV_CNTDWN_ENABLE = 0
                             FORCE_EOV_REZ_ENABLE = 0
                             OUT_OF_ORDER_PRIMITIVE_ENABLE = 0
                             OUT_OF_ORDER_WATER_MARK = 0
SET_CONTEXT_REG:
        PA_CL_VS_OUT_CNTL <- CLIP_DIST_ENA_0 = 0
                             CLIP_DIST_ENA_1 = 0
                             CLIP_DIST_ENA_2 = 0
                             CLIP_DIST_ENA_3 = 0
                             CLIP_DIST_ENA_4 = 0
                             CLIP_DIST_ENA_5 = 0
                             CLIP_DIST_ENA_6 = 0
                             CLIP_DIST_ENA_7 = 0
                             CULL_DIST_ENA_0 = 0
                             CULL_DIST_ENA_1 = 0
                             CULL_DIST_ENA_2 = 0
                             CULL_DIST_ENA_3 = 0
                             CULL_DIST_ENA_4 = 0
                             CULL_DIST_ENA_5 = 0
                             CULL_DIST_ENA_6 = 0
                             CULL_DIST_ENA_7 = 0
                             USE_VTX_POINT_SIZE = 0
                             USE_VTX_EDGE_FLAG = 0
                             USE_VTX_RENDER_TARGET_INDX = 0
                             USE_VTX_VIEWPORT_INDX = 0
                             USE_VTX_KILL_FLAG = 0
                             VS_OUT_MISC_VEC_ENA = 0
                             VS_OUT_CCDIST0_VEC_ENA = 0
                             VS_OUT_CCDIST1_VEC_ENA = 0
                             VS_OUT_MISC_SIDE_BUS_ENA = 1
                             USE_VTX_GS_CUT_FLAG = 0
                             USE_VTX_LINE_WIDTH = 0
SET_CONTEXT_REG:
        PA_CL_CLIP_CNTL <- UCP_ENA_0 = 0
                           UCP_ENA_1 = 0
                           UCP_ENA_2 = 0
                           UCP_ENA_3 = 0
                           UCP_ENA_4 = 0
                           UCP_ENA_5 = 0
                           PS_UCP_Y_SCALE_NEG = 0
                           PS_UCP_MODE = 3
                           CLIP_DISABLE = 0
                           UCP_CULL_ONLY_ENA = 0
                           BOUNDARY_EDGE_FLAG_ENA = 0
                           DX_CLIP_SPACE_DEF = 0
                           DIS_CLIP_ERR_DETECT = 0
                           VTX_KILL_OR = 0
                           DX_RASTERIZATION_KILL = 0
                           DX_LINEAR_ATTR_CLIP_ENA = 1
                           VTE_VPORT_PROVOKE_DISABLE = 0
                           ZCLIP_NEAR_DISABLE = 0
                           ZCLIP_FAR_DISABLE = 0
SET_SH_REG:
        SPI_SHADER_USER_DATA_VS_0 <- 0x019d6f00
        SPI_SHADER_USER_DATA_VS_1 <- 0
SET_SH_REG:
        SPI_SHADER_USER_DATA_VS_2 <- 0x019d6d00
        SPI_SHADER_USER_DATA_VS_3 <- 0
SET_SH_REG:
        SPI_SHADER_USER_DATA_VS_6 <- 0x019d0700
        SPI_SHADER_USER_DATA_VS_7 <- 0
SET_SH_REG:
        SPI_SHADER_USER_DATA_VS_4 <- 0x019d0c00
        SPI_SHADER_USER_DATA_VS_5 <- 0
SET_SH_REG:
        SPI_SHADER_USER_DATA_PS_0 <- 0x019d1000
        SPI_SHADER_USER_DATA_PS_1 <- 0
SET_SH_REG:
        SPI_SHADER_USER_DATA_PS_2 <- 0x019d0e00
        SPI_SHADER_USER_DATA_PS_3 <- 0
SET_SH_REG:
        SPI_SHADER_USER_DATA_PS_6 <- 0x019d1100
        SPI_SHADER_USER_DATA_PS_7 <- 0
SET_SH_REG:
        SPI_SHADER_USER_DATA_PS_4 <- 0x019d1600
        SPI_SHADER_USER_DATA_PS_5 <- 0
SET_SH_REG:
        SPI_SHADER_USER_DATA_GS_0 <- 0x019d1a00
        SPI_SHADER_USER_DATA_GS_1 <- 0
SET_SH_REG:
        SPI_SHADER_USER_DATA_GS_2 <- 0x019d1800
        SPI_SHADER_USER_DATA_GS_3 <- 0
SET_SH_REG:
        SPI_SHADER_USER_DATA_GS_6 <- 0x019d1b00
        SPI_SHADER_USER_DATA_GS_7 <- 0
SET_SH_REG:
        SPI_SHADER_USER_DATA_GS_4 <- 0x019d2000
        SPI_SHADER_USER_DATA_GS_5 <- 0
SET_SH_REG:
        SPI_SHADER_USER_DATA_HS_0 <- 0x019d2400
        SPI_SHADER_USER_DATA_HS_1 <- 0
SET_SH_REG:
        SPI_SHADER_USER_DATA_HS_2 <- 0x019d2200
        SPI_SHADER_USER_DATA_HS_3 <- 0
SET_SH_REG:
        SPI_SHADER_USER_DATA_HS_6 <- 0x019d2500
        SPI_SHADER_USER_DATA_HS_7 <- 0
SET_SH_REG:
        SPI_SHADER_USER_DATA_HS_4 <- 0x019d2a00
        SPI_SHADER_USER_DATA_HS_5 <- 0
SET_SH_REG:
        SPI_SHADER_USER_DATA_VS_8 <- 0x019d7000
        SPI_SHADER_USER_DATA_VS_9 <- 0
SET_CONTEXT_REG:
        DB_ALPHA_TO_MASK <- ALPHA_TO_MASK_ENABLE = 0
                            ALPHA_TO_MASK_OFFSET0 = 2
                            ALPHA_TO_MASK_OFFSET1 = 2
                            ALPHA_TO_MASK_OFFSET2 = 2
                            ALPHA_TO_MASK_OFFSET3 = 2
                            OFFSET_ROUND = 0
SET_CONTEXT_REG:
        CB_BLEND0_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO
                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
                             COLOR_DESTBLEND = BLEND_ZERO
                             ALPHA_SRCBLEND = BLEND_ZERO
                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
                             ALPHA_DESTBLEND = BLEND_ZERO
                             SEPARATE_ALPHA_BLEND = 0
                             ENABLE = 0
                             DISABLE_ROP3 = 0
        CB_BLEND1_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO
                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
                             COLOR_DESTBLEND = BLEND_ZERO
                             ALPHA_SRCBLEND = BLEND_ZERO
                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
                             ALPHA_DESTBLEND = BLEND_ZERO
                             SEPARATE_ALPHA_BLEND = 0
                             ENABLE = 0
                             DISABLE_ROP3 = 0
        CB_BLEND2_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO
                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
                             COLOR_DESTBLEND = BLEND_ZERO
                             ALPHA_SRCBLEND = BLEND_ZERO
                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
                             ALPHA_DESTBLEND = BLEND_ZERO
                             SEPARATE_ALPHA_BLEND = 0
                             ENABLE = 0
                             DISABLE_ROP3 = 0
        CB_BLEND3_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO
                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
                             COLOR_DESTBLEND = BLEND_ZERO
                             ALPHA_SRCBLEND = BLEND_ZERO
                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
                             ALPHA_DESTBLEND = BLEND_ZERO
                             SEPARATE_ALPHA_BLEND = 0
                             ENABLE = 0
                             DISABLE_ROP3 = 0
        CB_BLEND4_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO
                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
                             COLOR_DESTBLEND = BLEND_ZERO
                             ALPHA_SRCBLEND = BLEND_ZERO
                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
                             ALPHA_DESTBLEND = BLEND_ZERO
                             SEPARATE_ALPHA_BLEND = 0
                             ENABLE = 0
                             DISABLE_ROP3 = 0
        CB_BLEND5_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO
                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
                             COLOR_DESTBLEND = BLEND_ZERO
                             ALPHA_SRCBLEND = BLEND_ZERO
                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
                             ALPHA_DESTBLEND = BLEND_ZERO
                             SEPARATE_ALPHA_BLEND = 0
                             ENABLE = 0
                             DISABLE_ROP3 = 0
        CB_BLEND6_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO
                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
                             COLOR_DESTBLEND = BLEND_ZERO
                             ALPHA_SRCBLEND = BLEND_ZERO
                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
                             ALPHA_DESTBLEND = BLEND_ZERO
                             SEPARATE_ALPHA_BLEND = 0
                             ENABLE = 0
                             DISABLE_ROP3 = 0
        CB_BLEND7_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO
                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
                             COLOR_DESTBLEND = BLEND_ZERO
                             ALPHA_SRCBLEND = BLEND_ZERO
                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
                             ALPHA_DESTBLEND = BLEND_ZERO
                             SEPARATE_ALPHA_BLEND = 0
                             ENABLE = 0
                             DISABLE_ROP3 = 0
SET_CONTEXT_REG:
        CB_COLOR_CONTROL <- DEGAMMA_ENABLE = 0
                            MODE = CB_DISABLE
                            ROP3 = X_0XCC
SET_CONTEXT_REG:
        PA_SC_AA_MASK_X0Y0_X1Y0 <- AA_MASK_X0Y0 = 0x0000ffff
                                   AA_MASK_X1Y0 = 0x0000ffff
        PA_SC_AA_MASK_X0Y1_X1Y1 <- AA_MASK_X0Y1 = 0x0000ffff
                                   AA_MASK_X1Y1 = 0x0000ffff
SET_CONTEXT_REG:
        PA_SC_VPORT_SCISSOR_0_TL <- TL_X = 0
                                    TL_Y = 0
                                    WINDOW_OFFSET_DISABLE = 1
        PA_SC_VPORT_SCISSOR_0_BR <- BR_X = 300
                                    BR_Y = 300
SET_CONTEXT_REG:
        PA_SC_VPORT_SCISSOR_1_TL <- TL_X = 0
                                    TL_Y = 0
                                    WINDOW_OFFSET_DISABLE = 1
        PA_SC_VPORT_SCISSOR_1_BR <- BR_X = 300
                                    BR_Y = 300
SET_CONTEXT_REG:
        PA_SC_VPORT_SCISSOR_2_TL <- TL_X = 0
                                    TL_Y = 0
                                    WINDOW_OFFSET_DISABLE = 1
        PA_SC_VPORT_SCISSOR_2_BR <- BR_X = 300
                                    BR_Y = 300
SET_CONTEXT_REG:
        PA_SC_VPORT_SCISSOR_3_TL <- TL_X = 0
                                    TL_Y = 0
                                    WINDOW_OFFSET_DISABLE = 1
        PA_SC_VPORT_SCISSOR_3_BR <- BR_X = 300
                                    BR_Y = 300
SET_CONTEXT_REG:
        PA_SC_VPORT_SCISSOR_4_TL <- TL_X = 0
                                    TL_Y = 0
                                    WINDOW_OFFSET_DISABLE = 1
        PA_SC_VPORT_SCISSOR_4_BR <- BR_X = 300
                                    BR_Y = 300
SET_CONTEXT_REG:
        PA_SC_VPORT_SCISSOR_5_TL <- TL_X = 0
                                    TL_Y = 0
                                    WINDOW_OFFSET_DISABLE = 1
        PA_SC_VPORT_SCISSOR_5_BR <- BR_X = 300
                                    BR_Y = 300
SET_CONTEXT_REG:
        PA_SC_VPORT_SCISSOR_6_TL <- TL_X = 0
                                    TL_Y = 0
                                    WINDOW_OFFSET_DISABLE = 1
        PA_SC_VPORT_SCISSOR_6_BR <- BR_X = 300
                                    BR_Y = 300
SET_CONTEXT_REG:
        PA_SC_VPORT_SCISSOR_7_TL <- TL_X = 0
                                    TL_Y = 0
                                    WINDOW_OFFSET_DISABLE = 1
        PA_SC_VPORT_SCISSOR_7_BR <- BR_X = 300
                                    BR_Y = 300
SET_CONTEXT_REG:
        PA_SC_VPORT_SCISSOR_8_TL <- TL_X = 0
                                    TL_Y = 0
                                    WINDOW_OFFSET_DISABLE = 1
        PA_SC_VPORT_SCISSOR_8_BR <- BR_X = 300
                                    BR_Y = 300
SET_CONTEXT_REG:
        PA_SC_VPORT_SCISSOR_9_TL <- TL_X = 0
                                    TL_Y = 0
                                    WINDOW_OFFSET_DISABLE = 1
        PA_SC_VPORT_SCISSOR_9_BR <- BR_X = 300
                                    BR_Y = 300
SET_CONTEXT_REG:
        PA_SC_VPORT_SCISSOR_10_TL <- TL_X = 0
                                     TL_Y = 0
                                     WINDOW_OFFSET_DISABLE = 1
        PA_SC_VPORT_SCISSOR_10_BR <- BR_X = 300
                                     BR_Y = 300
SET_CONTEXT_REG:
        PA_SC_VPORT_SCISSOR_11_TL <- TL_X = 0
                                     TL_Y = 0
                                     WINDOW_OFFSET_DISABLE = 1
        PA_SC_VPORT_SCISSOR_11_BR <- BR_X = 300
                                     BR_Y = 300
SET_CONTEXT_REG:
        PA_SC_VPORT_SCISSOR_12_TL <- TL_X = 0
                                     TL_Y = 0
                                     WINDOW_OFFSET_DISABLE = 1
        PA_SC_VPORT_SCISSOR_12_BR <- BR_X = 300
                                     BR_Y = 300
SET_CONTEXT_REG:
        PA_SC_VPORT_SCISSOR_13_TL <- TL_X = 0
                                     TL_Y = 0
                                     WINDOW_OFFSET_DISABLE = 1
        PA_SC_VPORT_SCISSOR_13_BR <- BR_X = 300
                                     BR_Y = 300
SET_CONTEXT_REG:
        PA_SC_VPORT_SCISSOR_14_TL <- TL_X = 0
                                     TL_Y = 0
                                     WINDOW_OFFSET_DISABLE = 1
        PA_SC_VPORT_SCISSOR_14_BR <- BR_X = 300
                                     BR_Y = 300
SET_CONTEXT_REG:
        PA_SC_VPORT_SCISSOR_15_TL <- TL_X = 0
                                     TL_Y = 0
                                     WINDOW_OFFSET_DISABLE = 1
        PA_SC_VPORT_SCISSOR_15_BR <- BR_X = 300
                                     BR_Y = 300
SET_CONTEXT_REG:
        PA_CL_VPORT_XSCALE <- 1.0f
        PA_CL_VPORT_XOFFSET <- 0
        PA_CL_VPORT_YSCALE <- 1.0f
        PA_CL_VPORT_YOFFSET <- 0
        PA_CL_VPORT_ZSCALE <- 1.0f
        PA_CL_VPORT_ZOFFSET <- 0
SET_CONTEXT_REG:
        PA_CL_VPORT_XSCALE_1 <- 150.0f
        PA_CL_VPORT_XOFFSET_1 <- 150.0f
        PA_CL_VPORT_YSCALE_1 <- -150.0f
        PA_CL_VPORT_YOFFSET_1 <- 150.0f
        PA_CL_VPORT_ZSCALE_1 <- 0.5f
        PA_CL_VPORT_ZOFFSET_1 <- 0.5f
SET_CONTEXT_REG:
        PA_CL_VPORT_XSCALE_2 <- 150.0f
        PA_CL_VPORT_XOFFSET_2 <- 150.0f
        PA_CL_VPORT_YSCALE_2 <- -150.0f
        PA_CL_VPORT_YOFFSET_2 <- 150.0f
        PA_CL_VPORT_ZSCALE_2 <- 0.5f
        PA_CL_VPORT_ZOFFSET_2 <- 0.5f
SET_CONTEXT_REG:
        PA_CL_VPORT_XSCALE_3 <- 150.0f
        PA_CL_VPORT_XOFFSET_3 <- 150.0f
        PA_CL_VPORT_YSCALE_3 <- -150.0f
        PA_CL_VPORT_YOFFSET_3 <- 150.0f
        PA_CL_VPORT_ZSCALE_3 <- 0.5f
        PA_CL_VPORT_ZOFFSET_3 <- 0.5f
SET_CONTEXT_REG:
        PA_CL_VPORT_XSCALE_4 <- 150.0f
        PA_CL_VPORT_XOFFSET_4 <- 150.0f
        PA_CL_VPORT_YSCALE_4 <- -150.0f
        PA_CL_VPORT_YOFFSET_4 <- 150.0f
        PA_CL_VPORT_ZSCALE_4 <- 0.5f
        PA_CL_VPORT_ZOFFSET_4 <- 0.5f
SET_CONTEXT_REG:
        PA_CL_VPORT_XSCALE_5 <- 150.0f
        PA_CL_VPORT_XOFFSET_5 <- 150.0f
        PA_CL_VPORT_YSCALE_5 <- -150.0f
        PA_CL_VPORT_YOFFSET_5 <- 150.0f
        PA_CL_VPORT_ZSCALE_5 <- 0.5f
        PA_CL_VPORT_ZOFFSET_5 <- 0.5f
SET_CONTEXT_REG:
        PA_CL_VPORT_XSCALE_6 <- 150.0f
        PA_CL_VPORT_XOFFSET_6 <- 150.0f
        PA_CL_VPORT_YSCALE_6 <- -150.0f
        PA_CL_VPORT_YOFFSET_6 <- 150.0f
        PA_CL_VPORT_ZSCALE_6 <- 0.5f
        PA_CL_VPORT_ZOFFSET_6 <- 0.5f
SET_CONTEXT_REG:
        PA_CL_VPORT_XSCALE_7 <- 150.0f
        PA_CL_VPORT_XOFFSET_7 <- 150.0f
        PA_CL_VPORT_YSCALE_7 <- -150.0f
        PA_CL_VPORT_YOFFSET_7 <- 150.0f
        PA_CL_VPORT_ZSCALE_7 <- 0.5f
        PA_CL_VPORT_ZOFFSET_7 <- 0.5f
SET_CONTEXT_REG:
        PA_CL_VPORT_XSCALE_8 <- 150.0f
        PA_CL_VPORT_XOFFSET_8 <- 150.0f
        PA_CL_VPORT_YSCALE_8 <- -150.0f
        PA_CL_VPORT_YOFFSET_8 <- 150.0f
        PA_CL_VPORT_ZSCALE_8 <- 0.5f
        PA_CL_VPORT_ZOFFSET_8 <- 0.5f
SET_CONTEXT_REG:
        PA_CL_VPORT_XSCALE_9 <- 150.0f
        PA_CL_VPORT_XOFFSET_9 <- 150.0f
        PA_CL_VPORT_YSCALE_9 <- -150.0f
        PA_CL_VPORT_YOFFSET_9 <- 150.0f
        PA_CL_VPORT_ZSCALE_9 <- 0.5f
        PA_CL_VPORT_ZOFFSET_9 <- 0.5f
SET_CONTEXT_REG:
        PA_CL_VPORT_XSCALE_10 <- 150.0f
        PA_CL_VPORT_XOFFSET_10 <- 150.0f
        PA_CL_VPORT_YSCALE_10 <- -150.0f
        PA_CL_VPORT_YOFFSET_10 <- 150.0f
        PA_CL_VPORT_ZSCALE_10 <- 0.5f
        PA_CL_VPORT_ZOFFSET_10 <- 0.5f
SET_CONTEXT_REG:
        PA_CL_VPORT_XSCALE_11 <- 150.0f
        PA_CL_VPORT_XOFFSET_11 <- 150.0f
        PA_CL_VPORT_YSCALE_11 <- -150.0f
        PA_CL_VPORT_YOFFSET_11 <- 150.0f
        PA_CL_VPORT_ZSCALE_11 <- 0.5f
        PA_CL_VPORT_ZOFFSET_11 <- 0.5f
SET_CONTEXT_REG:
        PA_CL_VPORT_XSCALE_12 <- 150.0f
        PA_CL_VPORT_XOFFSET_12 <- 150.0f
        PA_CL_VPORT_YSCALE_12 <- -150.0f
        PA_CL_VPORT_YOFFSET_12 <- 150.0f
        PA_CL_VPORT_ZSCALE_12 <- 0.5f
        PA_CL_VPORT_ZOFFSET_12 <- 0.5f
SET_CONTEXT_REG:
        PA_CL_VPORT_XSCALE_13 <- 150.0f
        PA_CL_VPORT_XOFFSET_13 <- 150.0f
        PA_CL_VPORT_YSCALE_13 <- -150.0f
        PA_CL_VPORT_YOFFSET_13 <- 150.0f
        PA_CL_VPORT_ZSCALE_13 <- 0.5f
        PA_CL_VPORT_ZOFFSET_13 <- 0.5f
SET_CONTEXT_REG:
        PA_CL_VPORT_XSCALE_14 <- 150.0f
        PA_CL_VPORT_XOFFSET_14 <- 150.0f
        PA_CL_VPORT_YSCALE_14 <- -150.0f
        PA_CL_VPORT_YOFFSET_14 <- 150.0f
        PA_CL_VPORT_ZSCALE_14 <- 0.5f
        PA_CL_VPORT_ZOFFSET_14 <- 0.5f
SET_CONTEXT_REG:
        PA_CL_VPORT_XSCALE_15 <- 150.0f
        PA_CL_VPORT_XOFFSET_15 <- 150.0f
        PA_CL_VPORT_YSCALE_15 <- -150.0f
        PA_CL_VPORT_YOFFSET_15 <- 150.0f
        PA_CL_VPORT_ZSCALE_15 <- 0.5f
        PA_CL_VPORT_ZOFFSET_15 <- 0.5f
SET_CONTEXT_REG:
        SPI_INTERP_CONTROL_0 <- FLAT_SHADE_ENA = 1
                                PNT_SPRITE_ENA = 1
                                PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
                                PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
                                PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
                                PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
                                PNT_SPRITE_TOP_1 = 0
SET_CONTEXT_REG:
        PA_SU_POINT_SIZE <- HEIGHT = 0
                            WIDTH = 0
        PA_SU_POINT_MINMAX <- MIN_SIZE = 0
                              MAX_SIZE = 0
        PA_SU_LINE_CNTL <- WIDTH = 0
SET_CONTEXT_REG:
        PA_SC_MODE_CNTL_0 <- MSAA_ENABLE = 0
                             VPORT_SCISSOR_ENABLE = 0
                             LINE_STIPPLE_ENABLE = 0
                             SEND_UNLIT_STILES_TO_PKR = 0
SET_CONTEXT_REG:
        PA_SU_VTX_CNTL <- PIX_CENTER = 1
                          ROUND_MODE = X_TRUNCATE
                          QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
SET_CONTEXT_REG:
        PA_SU_POLY_OFFSET_CLAMP <- 0
SET_CONTEXT_REG:
        PA_SU_SC_MODE_CNTL <- CULL_FRONT = 0
                              CULL_BACK = 0
                              FACE = 1
                              POLY_MODE = X_DISABLE_POLY_MODE
                              POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
                              POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
                              POLY_OFFSET_FRONT_ENABLE = 0
                              POLY_OFFSET_BACK_ENABLE = 0
                              POLY_OFFSET_PARA_ENABLE = 0
                              VTX_WINDOW_OFFSET_ENABLE = 0
                              PROVOKING_VTX_LAST = 1
                              PERSP_CORR_DIS = 0
                              MULTI_PRIM_IB_ENA = 0
SET_CONTEXT_REG:
        DB_DEPTH_CONTROL <- STENCIL_ENABLE = 0
                            Z_ENABLE = 1
                            Z_WRITE_ENABLE = 1
                            DEPTH_BOUNDS_ENABLE = 0
                            ZFUNC = FRAG_ALWAYS
                            BACKFACE_ENABLE = 0
                            STENCILFUNC = REF_NEVER
                            STENCILFUNC_BF = REF_NEVER
                            ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0
                            DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0
SET_CONTEXT_REG:
        DB_STENCIL_CONTROL <- STENCILFAIL = STENCIL_KEEP
                              STENCILZPASS = STENCIL_KEEP
                              STENCILZFAIL = STENCIL_KEEP
                              STENCILFAIL_BF = STENCIL_KEEP
                              STENCILZPASS_BF = STENCIL_KEEP
                              STENCILZFAIL_BF = STENCIL_KEEP
SET_CONTEXT_REG:
        PA_SU_POLY_OFFSET_FRONT_SCALE <- 0
        PA_SU_POLY_OFFSET_FRONT_OFFSET <- 0
        PA_SU_POLY_OFFSET_BACK_SCALE <- 0
        PA_SU_POLY_OFFSET_BACK_OFFSET <- 0
SET_CONTEXT_REG:
        CB_TARGET_MASK <- TARGET0_ENABLE = 0
                          TARGET1_ENABLE = 0
                          TARGET2_ENABLE = 0
                          TARGET3_ENABLE = 0
                          TARGET4_ENABLE = 0
                          TARGET5_ENABLE = 0
                          TARGET6_ENABLE = 0
                          TARGET7_ENABLE = 0
SET_CONTEXT_REG:
        DB_STENCILREFMASK <- STENCILTESTVAL = 0
                             STENCILMASK = 0
                             STENCILWRITEMASK = 0
                             STENCILOPVAL = 1
        DB_STENCILREFMASK_BF <- STENCILTESTVAL_BF = 0
                                STENCILMASK_BF = 0
                                STENCILWRITEMASK_BF = 0
                                STENCILOPVAL_BF = 1
SET_CONTEXT_REG:
        VGT_SHADER_STAGES_EN <- LS_EN = LS_STAGE_OFF
                                HS_EN = 0
                                ES_EN = ES_STAGE_OFF
                                GS_EN = 0
                                VS_EN = VS_STAGE_REAL
                                DYNAMIC_HS = 0
                                DISPATCH_DRAW_EN = 0
                                DIS_DEALLOC_ACCUM_0 = 0
                                DIS_DEALLOC_ACCUM_1 = 0
                                VS_WAVE_ID_EN = 0
SET_CONTEXT_REG:
        VGT_GS_MODE <- MODE = GS_OFF
                       CUT_MODE = GS_CUT_1024
                       GS_C_PACK_EN = 0
                       ES_PASSTHRU = 0
                       COMPUTE_MODE = 0
                       FAST_COMPUTE_MODE = 0
                       ELEMENT_INFO_EN = 0
                       PARTIAL_THD_AT_EOI = 0
                       SUPPRESS_CUTS = 0
                       ES_WRITE_OPTIMIZE = 0
                       GS_WRITE_OPTIMIZE = 0
                       ONCHIP = X_0_OFFCHIP_GS
SET_CONTEXT_REG:
        VGT_PRIMITIVEID_EN <- PRIMITIVEID_EN = 0
                              DISABLE_RESET_ON_EOI = 0
SET_CONTEXT_REG:
        SPI_VS_OUT_CONFIG <- VS_EXPORT_COUNT = 0
                             VS_HALF_PACK = 0
                             VS_EXPORTS_FOG = 0
                             VS_OUT_FOG_VEC_ADDR = 0
SET_CONTEXT_REG:
        SPI_SHADER_POS_FORMAT <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
SET_SH_REG:
        SPI_SHADER_PGM_LO_VS <- 0x0001ae00
        SPI_SHADER_PGM_HI_VS <- MEM_BASE = 0
        SPI_SHADER_PGM_RSRC1_VS <- VGPRS = 2
                                   SGPRS = 9
                                   PRIORITY = 0
                                   FLOAT_MODE = 0
                                   PRIV = 0
                                   DX10_CLAMP = 1
                                   DEBUG_MODE = 0
                                   IEEE_MODE = 0
                                   VGPR_COMP_CNT = 0
                                   CU_GROUP_ENABLE = 0
                                   CACHE_CTL = 0
                                   CDBG_USER = 0
        SPI_SHADER_PGM_RSRC2_VS <- SCRATCH_EN = 0
                                   USER_SGPR = 12
                                   TRAP_PRESENT = 0
                                   OC_LDS_EN = 0
                                   SO_BASE0_EN = 0
                                   SO_BASE1_EN = 0
                                   SO_BASE2_EN = 0
                                   SO_BASE3_EN = 0
                                   SO_EN = 0
                                   EXCP_EN = 0
                                   EXCP_EN_CIK = 0
                                   DISPATCH_DRAW_EN = 0
SET_CONTEXT_REG:
        PA_CL_VTE_CNTL <- VPORT_X_SCALE_ENA = 1
                          VPORT_X_OFFSET_ENA = 1
                          VPORT_Y_SCALE_ENA = 1
                          VPORT_Y_OFFSET_ENA = 1
                          VPORT_Z_SCALE_ENA = 1
                          VPORT_Z_OFFSET_ENA = 1
                          VTX_XY_FMT = 0
                          VTX_Z_FMT = 0
                          VTX_W0_FMT = 1
SET_CONTEXT_REG:
        SPI_BARYC_CNTL <- PERSP_CENTER_CNTL = 0
                          PERSP_CENTROID_CNTL = 0
                          LINEAR_CENTER_CNTL = 0
                          LINEAR_CENTROID_CNTL = 0
                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
                          POS_FLOAT_ULC = 0
                          FRONT_FACE_ALL_BITS = 0
SET_CONTEXT_REG:
        SPI_PS_INPUT_ENA <- PERSP_SAMPLE_ENA = 1
                            PERSP_CENTER_ENA = 0
                            PERSP_CENTROID_ENA = 0
                            PERSP_PULL_MODEL_ENA = 0
                            LINEAR_SAMPLE_ENA = 0
                            LINEAR_CENTER_ENA = 0
                            LINEAR_CENTROID_ENA = 0
                            LINE_STIPPLE_TEX_ENA = 0
                            POS_X_FLOAT_ENA = 0
                            POS_Y_FLOAT_ENA = 0
                            POS_Z_FLOAT_ENA = 0
                            POS_W_FLOAT_ENA = 0
                            FRONT_FACE_ENA = 0
                            ANCILLARY_ENA = 0
                            SAMPLE_COVERAGE_ENA = 0
                            POS_FIXED_PT_ENA = 0
        SPI_PS_INPUT_ADDR <- PERSP_SAMPLE_ENA = 1
                             PERSP_CENTER_ENA = 0
                             PERSP_CENTROID_ENA = 0
                             PERSP_PULL_MODEL_ENA = 0
                             LINEAR_SAMPLE_ENA = 0
                             LINEAR_CENTER_ENA = 0
                             LINEAR_CENTROID_ENA = 0
                             LINE_STIPPLE_TEX_ENA = 0
                             POS_X_FLOAT_ENA = 0
                             POS_Y_FLOAT_ENA = 0
                             POS_Z_FLOAT_ENA = 0
                             POS_W_FLOAT_ENA = 0
                             FRONT_FACE_ENA = 0
                             ANCILLARY_ENA = 0
                             SAMPLE_COVERAGE_ENA = 0
                             POS_FIXED_PT_ENA = 0
SET_CONTEXT_REG:
        SPI_PS_IN_CONTROL <- NUM_INTERP = 1
                             PARAM_GEN = 0
                             FOG_ADDR = 0
                             BC_OPTIMIZE_DISABLE = 1
                             PASS_FOG_THROUGH_PS = 0
SET_CONTEXT_REG:
        SPI_SHADER_Z_FORMAT <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
        SPI_SHADER_COL_FORMAT <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
SET_CONTEXT_REG:
        CB_SHADER_MASK <- OUTPUT0_ENABLE = 15
                          OUTPUT1_ENABLE = 0
                          OUTPUT2_ENABLE = 0
                          OUTPUT3_ENABLE = 0
                          OUTPUT4_ENABLE = 0
                          OUTPUT5_ENABLE = 0
                          OUTPUT6_ENABLE = 0
                          OUTPUT7_ENABLE = 0
SET_SH_REG:
        SPI_SHADER_PGM_LO_PS <- 0x0001af00
        SPI_SHADER_PGM_HI_PS <- MEM_BASE = 0
        SPI_SHADER_PGM_RSRC1_PS <- VGPRS = 0
                                   SGPRS = 9
                                   PRIORITY = 0
                                   FLOAT_MODE = 0
                                   PRIV = 0
                                   DX10_CLAMP = 1
                                   DEBUG_MODE = 0
                                   IEEE_MODE = 0
                                   CU_GROUP_DISABLE = 0
                                   CACHE_CTL = 0
                                   CDBG_USER = 0
        SPI_SHADER_PGM_RSRC2_PS <- SCRATCH_EN = 0
                                   USER_SGPR = 9
                                   TRAP_PRESENT = 0
                                   WAVE_CNT_EN = 0
                                   EXTRA_LDS_SIZE = 0
                                   EXCP_EN = 0
                                   EXCP_EN_CIK = 0
SET_CONTEXT_REG:
        SPI_PS_INPUT_CNTL_0 <- OFFSET = 0
                               DEFAULT_VAL = X_0_0F
                               FLAT_SHADE = 1
                               CYL_WRAP = 0
                               PT_SPRITE_TEX = 0
                               DUP = 0
                               FP16_INTERP_MODE = 0
                               USE_DEFAULT_ATTR1 = 0
                               DEFAULT_VAL_ATTR1 = 0
                               PT_SPRITE_TEX_ATTR1 = 0
                               ATTR0_VALID = 0
                               ATTR1_VALID = 0
SET_CONTEXT_REG:
        SPI_TMPRING_SIZE <- WAVES = 32
                            WAVESIZE = 0
DRAW_PREAMBLE:
        VGT_PRIMITIVE_TYPE <- PRIM_TYPE = DI_PT_RECTLIST
        IA_MULTI_VGT_PARAM <- PRIMGROUP_SIZE = 127
                              PARTIAL_VS_WAVE_ON = 0
                              SWITCH_ON_EOP = 0
                              PARTIAL_ES_WAVE_ON = 0
                              SWITCH_ON_EOI = 0
                              WD_SWITCH_ON_EOP = 0
                              MAX_PRIMGRP_IN_WAVE = 2
        VGT_LS_HS_CONFIG <- NUM_PATCHES = 0
                            HS_NUM_INPUT_CP = 0
                            HS_NUM_OUTPUT_CP = 0
SET_CONTEXT_REG:
        VGT_GS_OUT_PRIM_TYPE <- OUTPRIM_TYPE = OUTPRIM_TYPE_TRISTRIP
                                OUTPRIM_TYPE_1 = 0
                                OUTPRIM_TYPE_2 = 0
                                OUTPRIM_TYPE_3 = 0
                                UNIQUE_TYPE_PER_STREAM = 0
SET_CONTEXT_REG:
        VGT_MULTI_PRIM_IB_RESET_EN <- RESET_EN = 0
NUM_INSTANCES:
        VGT_NUM_INSTANCES <- 1
SET_SH_REG:
        SPI_SHADER_USER_DATA_VS_10 <- 0
        SPI_SHADER_USER_DATA_VS_11 <- 0
DRAW_INDEX_AUTO:
        VGT_NUM_INDICES <- 3
        VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX
                              MAJOR_MODE = DI_MAJOR_MODE_0
                              NOT_EOP = 0
                              USE_OPAQUE = 0
SET_CONTEXT_REG:
        DB_RENDER_CONTROL <- DEPTH_CLEAR_ENABLE = 0
                             STENCIL_CLEAR_ENABLE = 0
                             DEPTH_COPY = 0
                             STENCIL_COPY = 0
                             RESUMMARIZE_ENABLE = 0
                             STENCIL_COMPRESS_DISABLE = 0
                             DEPTH_COMPRESS_DISABLE = 0
                             COPY_CENTROID = 0
                             COPY_SAMPLE = 0
                             DECOMPRESS_ENABLE = 0
        DB_COUNT_CONTROL <- ZPASS_INCREMENT_DISABLE = 0
                            PERFECT_ZPASS_COUNTS = 0
                            SAMPLE_RATE = 0
                            ZPASS_ENABLE = 0
                            ZFAIL_ENABLE = 0
                            SFAIL_ENABLE = 0
                            DBFAIL_ENABLE = 0
                            SLICE_EVEN_ENABLE = 0
                            SLICE_ODD_ENABLE = 0
SET_CONTEXT_REG:
        DB_RENDER_OVERRIDE2 <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
                               DISABLE_COLOR_ON_VALIDATION = 0
                               DECOMPRESS_Z_ON_FLUSH = 0
                               DISABLE_REG_SNOOP = 0
                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
                               SEPARATE_HIZS_FUNC_ENABLE = 0
                               HIZ_ZFUNC = 0
                               HIS_SFUNC_FF = 0
                               HIS_SFUNC_BF = 0
                               PRESERVE_ZRANGE = 0
                               PRESERVE_SRESULTS = 0
                               DISABLE_FAST_PASS = 0
SET_CONTEXT_REG:
        DB_SHADER_CONTROL <- Z_EXPORT_ENABLE = 0
                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
                             Z_ORDER = EARLY_Z_THEN_LATE_Z
                             KILL_ENABLE = 0
                             COVERAGE_TO_MASK_ENABLE = 0
                             MASK_EXPORT_ENABLE = 0
                             EXEC_ON_HIER_FAIL = 0
                             EXEC_ON_NOOP = 0
                             ALPHA_TO_MASK_DISABLE = 0
                             DEPTH_BEFORE_SHADER = 0
                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
SET_CONTEXT_REG:
        PA_CL_VS_OUT_CNTL <- CLIP_DIST_ENA_0 = 0
                             CLIP_DIST_ENA_1 = 0
                             CLIP_DIST_ENA_2 = 0
                             CLIP_DIST_ENA_3 = 0
                             CLIP_DIST_ENA_4 = 0
                             CLIP_DIST_ENA_5 = 0
                             CLIP_DIST_ENA_6 = 0
                             CLIP_DIST_ENA_7 = 0
                             CULL_DIST_ENA_0 = 0
                             CULL_DIST_ENA_1 = 0
                             CULL_DIST_ENA_2 = 0
                             CULL_DIST_ENA_3 = 0
                             CULL_DIST_ENA_4 = 0
                             CULL_DIST_ENA_5 = 0
                             CULL_DIST_ENA_6 = 0
                             CULL_DIST_ENA_7 = 0
                             USE_VTX_POINT_SIZE = 0
                             USE_VTX_EDGE_FLAG = 0
                             USE_VTX_RENDER_TARGET_INDX = 0
                             USE_VTX_VIEWPORT_INDX = 0
                             USE_VTX_KILL_FLAG = 0
                             VS_OUT_MISC_VEC_ENA = 0
                             VS_OUT_CCDIST0_VEC_ENA = 0
                             VS_OUT_CCDIST1_VEC_ENA = 0
                             VS_OUT_MISC_SIDE_BUS_ENA = 1
                             USE_VTX_GS_CUT_FLAG = 0
                             USE_VTX_LINE_WIDTH = 0
SET_CONTEXT_REG:
        PA_CL_CLIP_CNTL <- UCP_ENA_0 = 0
                           UCP_ENA_1 = 0
                           UCP_ENA_2 = 0
                           UCP_ENA_3 = 0
                           UCP_ENA_4 = 0
                           UCP_ENA_5 = 0
                           PS_UCP_Y_SCALE_NEG = 0
                           PS_UCP_MODE = 3
                           CLIP_DISABLE = 0
                           UCP_CULL_ONLY_ENA = 0
                           BOUNDARY_EDGE_FLAG_ENA = 0
                           DX_CLIP_SPACE_DEF = 0
                           DIS_CLIP_ERR_DETECT = 0
                           VTX_KILL_OR = 0
                           DX_RASTERIZATION_KILL = 0
                           DX_LINEAR_ATTR_CLIP_ENA = 1
                           VTE_VPORT_PROVOKE_DISABLE = 0
                           ZCLIP_NEAR_DISABLE = 0
                           ZCLIP_FAR_DISABLE = 0
SET_SH_REG:
        SPI_SHADER_USER_DATA_VS_0 <- 0x019d7400
        SPI_SHADER_USER_DATA_VS_1 <- 0
SET_SH_REG:
        SPI_SHADER_USER_DATA_VS_2 <- 0x019d7200
        SPI_SHADER_USER_DATA_VS_3 <- 0
SET_SH_REG:
        SPI_SHADER_USER_DATA_VS_8 <- 0x019d7500
        SPI_SHADER_USER_DATA_VS_9 <- 0
SET_CONTEXT_REG:
        DB_ALPHA_TO_MASK <- ALPHA_TO_MASK_ENABLE = 0
                            ALPHA_TO_MASK_OFFSET0 = 2
                            ALPHA_TO_MASK_OFFSET1 = 2
                            ALPHA_TO_MASK_OFFSET2 = 2
                            ALPHA_TO_MASK_OFFSET3 = 2
                            OFFSET_ROUND = 0
SET_CONTEXT_REG:
        CB_BLEND0_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO
                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
                             COLOR_DESTBLEND = BLEND_ZERO
                             ALPHA_SRCBLEND = BLEND_ZERO
                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
                             ALPHA_DESTBLEND = BLEND_ZERO
                             SEPARATE_ALPHA_BLEND = 0
                             ENABLE = 0
                             DISABLE_ROP3 = 0
        CB_BLEND1_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO
                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
                             COLOR_DESTBLEND = BLEND_ZERO
                             ALPHA_SRCBLEND = BLEND_ZERO
                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
                             ALPHA_DESTBLEND = BLEND_ZERO
                             SEPARATE_ALPHA_BLEND = 0
                             ENABLE = 0
                             DISABLE_ROP3 = 0
        CB_BLEND2_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO
                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
                             COLOR_DESTBLEND = BLEND_ZERO
                             ALPHA_SRCBLEND = BLEND_ZERO
                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
                             ALPHA_DESTBLEND = BLEND_ZERO
                             SEPARATE_ALPHA_BLEND = 0
                             ENABLE = 0
                             DISABLE_ROP3 = 0
        CB_BLEND3_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO
                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
                             COLOR_DESTBLEND = BLEND_ZERO
                             ALPHA_SRCBLEND = BLEND_ZERO
                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
                             ALPHA_DESTBLEND = BLEND_ZERO
                             SEPARATE_ALPHA_BLEND = 0
                             ENABLE = 0
                             DISABLE_ROP3 = 0
        CB_BLEND4_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO
                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
                             COLOR_DESTBLEND = BLEND_ZERO
                             ALPHA_SRCBLEND = BLEND_ZERO
                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
                             ALPHA_DESTBLEND = BLEND_ZERO
                             SEPARATE_ALPHA_BLEND = 0
                             ENABLE = 0
                             DISABLE_ROP3 = 0
        CB_BLEND5_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO
                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
                             COLOR_DESTBLEND = BLEND_ZERO
                             ALPHA_SRCBLEND = BLEND_ZERO
                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
                             ALPHA_DESTBLEND = BLEND_ZERO
                             SEPARATE_ALPHA_BLEND = 0
                             ENABLE = 0
                             DISABLE_ROP3 = 0
        CB_BLEND6_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO
                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
                             COLOR_DESTBLEND = BLEND_ZERO
                             ALPHA_SRCBLEND = BLEND_ZERO
                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
                             ALPHA_DESTBLEND = BLEND_ZERO
                             SEPARATE_ALPHA_BLEND = 0
                             ENABLE = 0
                             DISABLE_ROP3 = 0
        CB_BLEND7_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO
                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
                             COLOR_DESTBLEND = BLEND_ZERO
                             ALPHA_SRCBLEND = BLEND_ZERO
                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
                             ALPHA_DESTBLEND = BLEND_ZERO
                             SEPARATE_ALPHA_BLEND = 0
                             ENABLE = 0
                             DISABLE_ROP3 = 0
SET_CONTEXT_REG:
        CB_COLOR_CONTROL <- DEGAMMA_ENABLE = 0
                            MODE = CB_NORMAL
                            ROP3 = X_0XCC
SET_CONTEXT_REG:
        PA_SC_AA_MASK_X0Y0_X1Y0 <- AA_MASK_X0Y0 = 0x0000ffff
                                   AA_MASK_X1Y0 = 0x0000ffff
        PA_SC_AA_MASK_X0Y1_X1Y1 <- AA_MASK_X0Y1 = 0x0000ffff
                                   AA_MASK_X1Y1 = 0x0000ffff
SET_CONTEXT_REG:
        PA_CL_VPORT_XSCALE <- 150.0f
        PA_CL_VPORT_XOFFSET <- 150.0f
        PA_CL_VPORT_YSCALE <- -150.0f
        PA_CL_VPORT_YOFFSET <- 150.0f
        PA_CL_VPORT_ZSCALE <- 0.5f
        PA_CL_VPORT_ZOFFSET <- 0.5f
SET_CONTEXT_REG:
        SPI_INTERP_CONTROL_0 <- FLAT_SHADE_ENA = 1
                                PNT_SPRITE_ENA = 1
                                PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
                                PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
                                PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
                                PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
                                PNT_SPRITE_TOP_1 = 0
SET_CONTEXT_REG:
        PA_SU_POINT_SIZE <- HEIGHT = 8
                            WIDTH = 8
        PA_SU_POINT_MINMAX <- MIN_SIZE = 8
                              MAX_SIZE = 8
        PA_SU_LINE_CNTL <- WIDTH = 8
SET_CONTEXT_REG:
        PA_SC_MODE_CNTL_0 <- MSAA_ENABLE = 0
                             VPORT_SCISSOR_ENABLE = 0
                             LINE_STIPPLE_ENABLE = 0
                             SEND_UNLIT_STILES_TO_PKR = 0
SET_CONTEXT_REG:
        PA_SU_VTX_CNTL <- PIX_CENTER = 1
                          ROUND_MODE = X_TRUNCATE
                          QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
SET_CONTEXT_REG:
        PA_SU_POLY_OFFSET_CLAMP <- 0
SET_CONTEXT_REG:
        PA_SU_SC_MODE_CNTL <- CULL_FRONT = 0
                              CULL_BACK = 1
                              FACE = 0
                              POLY_MODE = X_DISABLE_POLY_MODE
                              POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
                              POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
                              POLY_OFFSET_FRONT_ENABLE = 0
                              POLY_OFFSET_BACK_ENABLE = 0
                              POLY_OFFSET_PARA_ENABLE = 0
                              VTX_WINDOW_OFFSET_ENABLE = 0
                              PROVOKING_VTX_LAST = 1
                              PERSP_CORR_DIS = 0
                              MULTI_PRIM_IB_ENA = 0
SET_CONTEXT_REG:
        DB_DEPTH_CONTROL <- STENCIL_ENABLE = 0
                            Z_ENABLE = 1
                            Z_WRITE_ENABLE = 1
                            DEPTH_BOUNDS_ENABLE = 0
                            ZFUNC = FRAG_LESS
                            BACKFACE_ENABLE = 0
                            STENCILFUNC = REF_NEVER
                            STENCILFUNC_BF = REF_NEVER
                            ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0
                            DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0
SET_CONTEXT_REG:
        DB_STENCIL_CONTROL <- STENCILFAIL = STENCIL_KEEP
                              STENCILZPASS = STENCIL_KEEP
                              STENCILZFAIL = STENCIL_KEEP
                              STENCILFAIL_BF = STENCIL_KEEP
                              STENCILZPASS_BF = STENCIL_KEEP
                              STENCILZFAIL_BF = STENCIL_KEEP
SET_CONTEXT_REG:
        PA_SU_POLY_OFFSET_FRONT_SCALE <- 0
        PA_SU_POLY_OFFSET_FRONT_OFFSET <- 0
        PA_SU_POLY_OFFSET_BACK_SCALE <- 0
        PA_SU_POLY_OFFSET_BACK_OFFSET <- 0
SET_CONTEXT_REG:
        CB_TARGET_MASK <- TARGET0_ENABLE = 15
                          TARGET1_ENABLE = 0
                          TARGET2_ENABLE = 0
                          TARGET3_ENABLE = 0
                          TARGET4_ENABLE = 0
                          TARGET5_ENABLE = 0
                          TARGET6_ENABLE = 0
                          TARGET7_ENABLE = 0
SET_CONTEXT_REG:
        DB_STENCILREFMASK <- STENCILTESTVAL = 0
                             STENCILMASK = 0
                             STENCILWRITEMASK = 0
                             STENCILOPVAL = 1
        DB_STENCILREFMASK_BF <- STENCILTESTVAL_BF = 0
                                STENCILMASK_BF = 0
                                STENCILWRITEMASK_BF = 0
                                STENCILOPVAL_BF = 1
SET_CONTEXT_REG:
        VGT_GS_MODE <- MODE = GS_OFF
                       CUT_MODE = GS_CUT_1024
                       GS_C_PACK_EN = 0
                       ES_PASSTHRU = 0
                       COMPUTE_MODE = 0
                       FAST_COMPUTE_MODE = 0
                       ELEMENT_INFO_EN = 0
                       PARTIAL_THD_AT_EOI = 0
                       SUPPRESS_CUTS = 0
                       ES_WRITE_OPTIMIZE = 0
                       GS_WRITE_OPTIMIZE = 0
                       ONCHIP = X_0_OFFCHIP_GS
SET_CONTEXT_REG:
        VGT_PRIMITIVEID_EN <- PRIMITIVEID_EN = 0
                              DISABLE_RESET_ON_EOI = 0
SET_CONTEXT_REG:
        SPI_VS_OUT_CONFIG <- VS_EXPORT_COUNT = 0
                             VS_HALF_PACK = 0
                             VS_EXPORTS_FOG = 0
                             VS_OUT_FOG_VEC_ADDR = 0
SET_CONTEXT_REG:
        SPI_SHADER_POS_FORMAT <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
SET_SH_REG:
        SPI_SHADER_PGM_LO_VS <- 0x0001b000
        SPI_SHADER_PGM_HI_VS <- MEM_BASE = 0
        SPI_SHADER_PGM_RSRC1_VS <- VGPRS = 2
                                   SGPRS = 9
                                   PRIORITY = 0
                                   FLOAT_MODE = 0
                                   PRIV = 0
                                   DX10_CLAMP = 1
                                   DEBUG_MODE = 0
                                   IEEE_MODE = 0
                                   VGPR_COMP_CNT = 0
                                   CU_GROUP_ENABLE = 0
                                   CACHE_CTL = 0
                                   CDBG_USER = 0
        SPI_SHADER_PGM_RSRC2_VS <- SCRATCH_EN = 0
                                   USER_SGPR = 12
                                   TRAP_PRESENT = 0
                                   OC_LDS_EN = 0
                                   SO_BASE0_EN = 0
                                   SO_BASE1_EN = 0
                                   SO_BASE2_EN = 0
                                   SO_BASE3_EN = 0
                                   SO_EN = 0
                                   EXCP_EN = 0
                                   EXCP_EN_CIK = 0
                                   DISPATCH_DRAW_EN = 0
SET_CONTEXT_REG:
        PA_CL_VTE_CNTL <- VPORT_X_SCALE_ENA = 1
                          VPORT_X_OFFSET_ENA = 1
                          VPORT_Y_SCALE_ENA = 1
                          VPORT_Y_OFFSET_ENA = 1
                          VPORT_Z_SCALE_ENA = 1
                          VPORT_Z_OFFSET_ENA = 1
                          VTX_XY_FMT = 0
                          VTX_Z_FMT = 0
                          VTX_W0_FMT = 1
SET_CONTEXT_REG:
        SPI_BARYC_CNTL <- PERSP_CENTER_CNTL = 0
                          PERSP_CENTROID_CNTL = 0
                          LINEAR_CENTER_CNTL = 0
                          LINEAR_CENTROID_CNTL = 0
                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
                          POS_FLOAT_ULC = 0
                          FRONT_FACE_ALL_BITS = 0
SET_CONTEXT_REG:
        SPI_PS_INPUT_ENA <- PERSP_SAMPLE_ENA = 0
                            PERSP_CENTER_ENA = 1
                            PERSP_CENTROID_ENA = 0
                            PERSP_PULL_MODEL_ENA = 0
                            LINEAR_SAMPLE_ENA = 0
                            LINEAR_CENTER_ENA = 0
                            LINEAR_CENTROID_ENA = 0
                            LINE_STIPPLE_TEX_ENA = 0
                            POS_X_FLOAT_ENA = 0
                            POS_Y_FLOAT_ENA = 0
                            POS_Z_FLOAT_ENA = 0
                            POS_W_FLOAT_ENA = 0
                            FRONT_FACE_ENA = 0
                            ANCILLARY_ENA = 0
                            SAMPLE_COVERAGE_ENA = 0
                            POS_FIXED_PT_ENA = 0
        SPI_PS_INPUT_ADDR <- PERSP_SAMPLE_ENA = 0
                             PERSP_CENTER_ENA = 1
                             PERSP_CENTROID_ENA = 0
                             PERSP_PULL_MODEL_ENA = 0
                             LINEAR_SAMPLE_ENA = 0
                             LINEAR_CENTER_ENA = 0
                             LINEAR_CENTROID_ENA = 0
                             LINE_STIPPLE_TEX_ENA = 0
                             POS_X_FLOAT_ENA = 0
                             POS_Y_FLOAT_ENA = 0
                             POS_Z_FLOAT_ENA = 0
                             POS_W_FLOAT_ENA = 0
                             FRONT_FACE_ENA = 0
                             ANCILLARY_ENA = 0
                             SAMPLE_COVERAGE_ENA = 0
                             POS_FIXED_PT_ENA = 0
SET_CONTEXT_REG:
        SPI_PS_IN_CONTROL <- NUM_INTERP = 1
                             PARAM_GEN = 0
                             FOG_ADDR = 0
                             BC_OPTIMIZE_DISABLE = 1
                             PASS_FOG_THROUGH_PS = 0
SET_CONTEXT_REG:
        SPI_SHADER_Z_FORMAT <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
        SPI_SHADER_COL_FORMAT <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
SET_CONTEXT_REG:
        CB_SHADER_MASK <- OUTPUT0_ENABLE = 15
                          OUTPUT1_ENABLE = 0
                          OUTPUT2_ENABLE = 0
                          OUTPUT3_ENABLE = 0
                          OUTPUT4_ENABLE = 0
                          OUTPUT5_ENABLE = 0
                          OUTPUT6_ENABLE = 0
                          OUTPUT7_ENABLE = 0
SET_SH_REG:
        SPI_SHADER_PGM_LO_PS <- 0x0001b100
        SPI_SHADER_PGM_HI_PS <- MEM_BASE = 0
        SPI_SHADER_PGM_RSRC1_PS <- VGPRS = 1
                                   SGPRS = 9
                                   PRIORITY = 0
                                   FLOAT_MODE = 0
                                   PRIV = 0
                                   DX10_CLAMP = 1
                                   DEBUG_MODE = 0
                                   IEEE_MODE = 0
                                   CU_GROUP_DISABLE = 0
                                   CACHE_CTL = 0
                                   CDBG_USER = 0
        SPI_SHADER_PGM_RSRC2_PS <- SCRATCH_EN = 0
                                   USER_SGPR = 9
                                   TRAP_PRESENT = 0
                                   WAVE_CNT_EN = 0
                                   EXTRA_LDS_SIZE = 0
                                   EXCP_EN = 0
                                   EXCP_EN_CIK = 0
SET_CONTEXT_REG:
        SPI_PS_INPUT_CNTL_0 <- OFFSET = 0
                               DEFAULT_VAL = X_0_0F
                               FLAT_SHADE = 1
                               CYL_WRAP = 0
                               PT_SPRITE_TEX = 0
                               DUP = 0
                               FP16_INTERP_MODE = 0
                               USE_DEFAULT_ATTR1 = 0
                               DEFAULT_VAL_ATTR1 = 0
                               PT_SPRITE_TEX_ATTR1 = 0
                               ATTR0_VALID = 0
                               ATTR1_VALID = 0
DRAW_PREAMBLE:
        VGT_PRIMITIVE_TYPE <- PRIM_TYPE = DI_PT_QUADSTRIP
        IA_MULTI_VGT_PARAM <- PRIMGROUP_SIZE = 127
                              PARTIAL_VS_WAVE_ON = 0
                              SWITCH_ON_EOP = 0
                              PARTIAL_ES_WAVE_ON = 0
                              SWITCH_ON_EOI = 0
                              WD_SWITCH_ON_EOP = 0
                              MAX_PRIMGRP_IN_WAVE = 2
        VGT_LS_HS_CONFIG <- NUM_PATCHES = 0
                            HS_NUM_INPUT_CP = 0
                            HS_NUM_OUTPUT_CP = 0
NUM_INSTANCES:
        VGT_NUM_INSTANCES <- 1
DRAW_INDEX_AUTO:
        VGT_NUM_INDICES <- 82
        VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX
                              MAJOR_MODE = DI_MAJOR_MODE_0
                              NOT_EOP = 0
                              USE_OPAQUE = 0
DRAW_PREAMBLE:
        VGT_PRIMITIVE_TYPE <- PRIM_TYPE = DI_PT_QUADLIST
        IA_MULTI_VGT_PARAM <- PRIMGROUP_SIZE = 127
                              PARTIAL_VS_WAVE_ON = 0
                              SWITCH_ON_EOP = 0
                              PARTIAL_ES_WAVE_ON = 0
                              SWITCH_ON_EOI = 0
                              WD_SWITCH_ON_EOP = 0
                              MAX_PRIMGRP_IN_WAVE = 2
        VGT_LS_HS_CONFIG <- NUM_PATCHES = 0
                            HS_NUM_INPUT_CP = 0
                            HS_NUM_OUTPUT_CP = 0
NUM_INSTANCES:
        VGT_NUM_INSTANCES <- 1
SET_SH_REG:
        SPI_SHADER_USER_DATA_VS_10 <- 82
        SPI_SHADER_USER_DATA_VS_11 <- 0
DRAW_INDEX_AUTO:
        VGT_NUM_INDICES <- 80
        VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX
                              MAJOR_MODE = DI_MAJOR_MODE_0
                              NOT_EOP = 0
                              USE_OPAQUE = 0
SET_SH_REG:
        SPI_SHADER_USER_DATA_VS_2 <- 0x019d7700
        SPI_SHADER_USER_DATA_VS_3 <- 0
SET_SH_REG:
        SPI_SHADER_USER_DATA_VS_8 <- 0x019d7900
        SPI_SHADER_USER_DATA_VS_9 <- 0
DRAW_PREAMBLE:
        VGT_PRIMITIVE_TYPE <- PRIM_TYPE = DI_PT_QUADSTRIP
        IA_MULTI_VGT_PARAM <- PRIMGROUP_SIZE = 127
                              PARTIAL_VS_WAVE_ON = 0
                              SWITCH_ON_EOP = 0
                              PARTIAL_ES_WAVE_ON = 0
                              SWITCH_ON_EOI = 0
                              WD_SWITCH_ON_EOP = 0
                              MAX_PRIMGRP_IN_WAVE = 2
        VGT_LS_HS_CONFIG <- NUM_PATCHES = 0
                            HS_NUM_INPUT_CP = 0
                            HS_NUM_OUTPUT_CP = 0
NUM_INSTANCES:
        VGT_NUM_INSTANCES <- 1
SET_SH_REG:
        SPI_SHADER_USER_DATA_VS_10 <- 0
        SPI_SHADER_USER_DATA_VS_11 <- 0
DRAW_INDEX_AUTO:
        VGT_NUM_INDICES <- 82
        VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX
                              MAJOR_MODE = DI_MAJOR_MODE_0
                              NOT_EOP = 0
                              USE_OPAQUE = 0
DRAW_PREAMBLE:
        VGT_PRIMITIVE_TYPE <- PRIM_TYPE = DI_PT_QUADLIST
        IA_MULTI_VGT_PARAM <- PRIMGROUP_SIZE = 127
                              PARTIAL_VS_WAVE_ON = 0
                              SWITCH_ON_EOP = 0
                              PARTIAL_ES_WAVE_ON = 0
                              SWITCH_ON_EOI = 0
                              WD_SWITCH_ON_EOP = 0
                              MAX_PRIMGRP_IN_WAVE = 2
        VGT_LS_HS_CONFIG <- NUM_PATCHES = 0
                            HS_NUM_INPUT_CP = 0
                            HS_NUM_OUTPUT_CP = 0
NUM_INSTANCES:
        VGT_NUM_INSTANCES <- 1
SET_SH_REG:
        SPI_SHADER_USER_DATA_VS_10 <- 82
        SPI_SHADER_USER_DATA_VS_11 <- 0
DRAW_INDEX_AUTO:
        VGT_NUM_INDICES <- 80
        VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX
                              MAJOR_MODE = DI_MAJOR_MODE_0
                              NOT_EOP = 0
                              USE_OPAQUE = 0
SET_CONTEXT_REG:
        PA_CL_VS_OUT_CNTL <- CLIP_DIST_ENA_0 = 0
                             CLIP_DIST_ENA_1 = 0
                             CLIP_DIST_ENA_2 = 0
                             CLIP_DIST_ENA_3 = 0
                             CLIP_DIST_ENA_4 = 0
                             CLIP_DIST_ENA_5 = 0
                             CLIP_DIST_ENA_6 = 0
                             CLIP_DIST_ENA_7 = 0
                             CULL_DIST_ENA_0 = 0
                             CULL_DIST_ENA_1 = 0
                             CULL_DIST_ENA_2 = 0
                             CULL_DIST_ENA_3 = 0
                             CULL_DIST_ENA_4 = 0
                             CULL_DIST_ENA_5 = 0
                             CULL_DIST_ENA_6 = 0
                             CULL_DIST_ENA_7 = 0
                             USE_VTX_POINT_SIZE = 0
                             USE_VTX_EDGE_FLAG = 0
                             USE_VTX_RENDER_TARGET_INDX = 0
                             USE_VTX_VIEWPORT_INDX = 0
                             USE_VTX_KILL_FLAG = 0
                             VS_OUT_MISC_VEC_ENA = 0
                             VS_OUT_CCDIST0_VEC_ENA = 0
                             VS_OUT_CCDIST1_VEC_ENA = 0
                             VS_OUT_MISC_SIDE_BUS_ENA = 1
                             USE_VTX_GS_CUT_FLAG = 0
                             USE_VTX_LINE_WIDTH = 0
SET_CONTEXT_REG:
        PA_CL_CLIP_CNTL <- UCP_ENA_0 = 0
                           UCP_ENA_1 = 0
                           UCP_ENA_2 = 0
                           UCP_ENA_3 = 0
                           UCP_ENA_4 = 0
                           UCP_ENA_5 = 0
                           PS_UCP_Y_SCALE_NEG = 0
                           PS_UCP_MODE = 3
                           CLIP_DISABLE = 0
                           UCP_CULL_ONLY_ENA = 0
                           BOUNDARY_EDGE_FLAG_ENA = 0
                           DX_CLIP_SPACE_DEF = 0
                           DIS_CLIP_ERR_DETECT = 0
                           VTX_KILL_OR = 0
                           DX_RASTERIZATION_KILL = 0
                           DX_LINEAR_ATTR_CLIP_ENA = 1
                           VTE_VPORT_PROVOKE_DISABLE = 0
                           ZCLIP_NEAR_DISABLE = 0
                           ZCLIP_FAR_DISABLE = 0
SET_SH_REG:
        SPI_SHADER_USER_DATA_VS_2 <- 0x019d7b00
        SPI_SHADER_USER_DATA_VS_3 <- 0
SET_SH_REG:
        SPI_SHADER_USER_DATA_VS_8 <- 0x019d7d00
        SPI_SHADER_USER_DATA_VS_9 <- 0
SET_CONTEXT_REG:
        VGT_GS_MODE <- MODE = GS_OFF
                       CUT_MODE = GS_CUT_1024
                       GS_C_PACK_EN = 0
                       ES_PASSTHRU = 0
                       COMPUTE_MODE = 0
                       FAST_COMPUTE_MODE = 0
                       ELEMENT_INFO_EN = 0
                       PARTIAL_THD_AT_EOI = 0
                       SUPPRESS_CUTS = 0
                       ES_WRITE_OPTIMIZE = 0
                       GS_WRITE_OPTIMIZE = 0
                       ONCHIP = X_0_OFFCHIP_GS
SET_CONTEXT_REG:
        VGT_PRIMITIVEID_EN <- PRIMITIVEID_EN = 0
                              DISABLE_RESET_ON_EOI = 0
SET_CONTEXT_REG:
        SPI_VS_OUT_CONFIG <- VS_EXPORT_COUNT = 0
                             VS_HALF_PACK = 0
                             VS_EXPORTS_FOG = 0
                             VS_OUT_FOG_VEC_ADDR = 0
SET_CONTEXT_REG:
        SPI_SHADER_POS_FORMAT <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
SET_SH_REG:
        SPI_SHADER_PGM_LO_VS <- 0x0001b200
        SPI_SHADER_PGM_HI_VS <- MEM_BASE = 0
        SPI_SHADER_PGM_RSRC1_VS <- VGPRS = 2
                                   SGPRS = 9
                                   PRIORITY = 0
                                   FLOAT_MODE = 0
                                   PRIV = 0
                                   DX10_CLAMP = 1
                                   DEBUG_MODE = 0
                                   IEEE_MODE = 0
                                   VGPR_COMP_CNT = 0
                                   CU_GROUP_ENABLE = 0
                                   CACHE_CTL = 0
                                   CDBG_USER = 0
        SPI_SHADER_PGM_RSRC2_VS <- SCRATCH_EN = 0
                                   USER_SGPR = 12
                                   TRAP_PRESENT = 0
                                   OC_LDS_EN = 0
                                   SO_BASE0_EN = 0
                                   SO_BASE1_EN = 0
                                   SO_BASE2_EN = 0
                                   SO_BASE3_EN = 0
                                   SO_EN = 0
                                   EXCP_EN = 0
                                   EXCP_EN_CIK = 0
                                   DISPATCH_DRAW_EN = 0
SET_CONTEXT_REG:
        PA_CL_VTE_CNTL <- VPORT_X_SCALE_ENA = 1
                          VPORT_X_OFFSET_ENA = 1
                          VPORT_Y_SCALE_ENA = 1
                          VPORT_Y_OFFSET_ENA = 1
                          VPORT_Z_SCALE_ENA = 1
                          VPORT_Z_OFFSET_ENA = 1
                          VTX_XY_FMT = 0
                          VTX_Z_FMT = 0
                          VTX_W0_FMT = 1
SET_CONTEXT_REG:
        SPI_PS_INPUT_CNTL_0 <- OFFSET = 0
                               DEFAULT_VAL = X_0_0F
                               FLAT_SHADE = 1
                               CYL_WRAP = 0
                               PT_SPRITE_TEX = 0
                               DUP = 0
                               FP16_INTERP_MODE = 0
                               USE_DEFAULT_ATTR1 = 0
                               DEFAULT_VAL_ATTR1 = 0
                               PT_SPRITE_TEX_ATTR1 = 0
                               ATTR0_VALID = 0
                               ATTR1_VALID = 0
DRAW_PREAMBLE:
        VGT_PRIMITIVE_TYPE <- PRIM_TYPE = DI_PT_QUADSTRIP
        IA_MULTI_VGT_PARAM <- PRIMGROUP_SIZE = 127
                              PARTIAL_VS_WAVE_ON = 0
                              SWITCH_ON_EOP = 0
                              PARTIAL_ES_WAVE_ON = 0
                              SWITCH_ON_EOI = 0
                              WD_SWITCH_ON_EOP = 0
                              MAX_PRIMGRP_IN_WAVE = 2
        VGT_LS_HS_CONFIG <- NUM_PATCHES = 0
                            HS_NUM_INPUT_CP = 0
                            HS_NUM_OUTPUT_CP = 0
NUM_INSTANCES:
        VGT_NUM_INSTANCES <- 1
SET_SH_REG:
        SPI_SHADER_USER_DATA_VS_10 <- 0
        SPI_SHADER_USER_DATA_VS_11 <- 0
DRAW_INDEX_AUTO:
        VGT_NUM_INDICES <- 162
        VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX
                              MAJOR_MODE = DI_MAJOR_MODE_0
                              NOT_EOP = 0
                              USE_OPAQUE = 0
SET_CONTEXT_REG:
        PA_CL_VS_OUT_CNTL <- CLIP_DIST_ENA_0 = 0
                             CLIP_DIST_ENA_1 = 0
                             CLIP_DIST_ENA_2 = 0
                             CLIP_DIST_ENA_3 = 0
                             CLIP_DIST_ENA_4 = 0
                             CLIP_DIST_ENA_5 = 0
                             CLIP_DIST_ENA_6 = 0
                             CLIP_DIST_ENA_7 = 0
                             CULL_DIST_ENA_0 = 0
                             CULL_DIST_ENA_1 = 0
                             CULL_DIST_ENA_2 = 0
                             CULL_DIST_ENA_3 = 0
                             CULL_DIST_ENA_4 = 0
                             CULL_DIST_ENA_5 = 0
                             CULL_DIST_ENA_6 = 0
                             CULL_DIST_ENA_7 = 0
                             USE_VTX_POINT_SIZE = 0
                             USE_VTX_EDGE_FLAG = 0
                             USE_VTX_RENDER_TARGET_INDX = 0
                             USE_VTX_VIEWPORT_INDX = 0
                             USE_VTX_KILL_FLAG = 0
                             VS_OUT_MISC_VEC_ENA = 0
                             VS_OUT_CCDIST0_VEC_ENA = 0
                             VS_OUT_CCDIST1_VEC_ENA = 0
                             VS_OUT_MISC_SIDE_BUS_ENA = 1
                             USE_VTX_GS_CUT_FLAG = 0
                             USE_VTX_LINE_WIDTH = 0
SET_CONTEXT_REG:
        PA_CL_CLIP_CNTL <- UCP_ENA_0 = 0
                           UCP_ENA_1 = 0
                           UCP_ENA_2 = 0
                           UCP_ENA_3 = 0
                           UCP_ENA_4 = 0
                           UCP_ENA_5 = 0
                           PS_UCP_Y_SCALE_NEG = 0
                           PS_UCP_MODE = 3
                           CLIP_DISABLE = 0
                           UCP_CULL_ONLY_ENA = 0
                           BOUNDARY_EDGE_FLAG_ENA = 0
                           DX_CLIP_SPACE_DEF = 0
                           DIS_CLIP_ERR_DETECT = 0
                           VTX_KILL_OR = 0
                           DX_RASTERIZATION_KILL = 0
                           DX_LINEAR_ATTR_CLIP_ENA = 1
                           VTE_VPORT_PROVOKE_DISABLE = 0
                           ZCLIP_NEAR_DISABLE = 0
                           ZCLIP_FAR_DISABLE = 0
SET_SH_REG:
        SPI_SHADER_USER_DATA_VS_2 <- 0x019d7f00
        SPI_SHADER_USER_DATA_VS_3 <- 0
SET_SH_REG:
        SPI_SHADER_USER_DATA_VS_8 <- 0x019d8100
        SPI_SHADER_USER_DATA_VS_9 <- 0
SET_CONTEXT_REG:
        SPI_INTERP_CONTROL_0 <- FLAT_SHADE_ENA = 1
                                PNT_SPRITE_ENA = 1
                                PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
                                PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
                                PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
                                PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
                                PNT_SPRITE_TOP_1 = 0
SET_CONTEXT_REG:
        PA_SU_POINT_SIZE <- HEIGHT = 8
                            WIDTH = 8
        PA_SU_POINT_MINMAX <- MIN_SIZE = 8
                              MAX_SIZE = 8
        PA_SU_LINE_CNTL <- WIDTH = 8
SET_CONTEXT_REG:
        PA_SC_MODE_CNTL_0 <- MSAA_ENABLE = 0
                             VPORT_SCISSOR_ENABLE = 0
                             LINE_STIPPLE_ENABLE = 0
                             SEND_UNLIT_STILES_TO_PKR = 0
SET_CONTEXT_REG:
        PA_SU_VTX_CNTL <- PIX_CENTER = 1
                          ROUND_MODE = X_TRUNCATE
                          QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
SET_CONTEXT_REG:
        PA_SU_POLY_OFFSET_CLAMP <- 0
SET_CONTEXT_REG:
        PA_SU_SC_MODE_CNTL <- CULL_FRONT = 0
                              CULL_BACK = 1
                              FACE = 0
                              POLY_MODE = X_DISABLE_POLY_MODE
                              POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
                              POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
                              POLY_OFFSET_FRONT_ENABLE = 0
                              POLY_OFFSET_BACK_ENABLE = 0
                              POLY_OFFSET_PARA_ENABLE = 0
                              VTX_WINDOW_OFFSET_ENABLE = 0
                              PROVOKING_VTX_LAST = 1
                              PERSP_CORR_DIS = 0
                              MULTI_PRIM_IB_ENA = 0
SET_CONTEXT_REG:
        PA_SU_POLY_OFFSET_FRONT_SCALE <- 0
        PA_SU_POLY_OFFSET_FRONT_OFFSET <- 0
        PA_SU_POLY_OFFSET_BACK_SCALE <- 0
        PA_SU_POLY_OFFSET_BACK_OFFSET <- 0
SET_CONTEXT_REG:
        SPI_PS_INPUT_CNTL_0 <- OFFSET = 0
                               DEFAULT_VAL = X_0_0F
                               FLAT_SHADE = 0
                               CYL_WRAP = 0
                               PT_SPRITE_TEX = 0
                               DUP = 0
                               FP16_INTERP_MODE = 0
                               USE_DEFAULT_ATTR1 = 0
                               DEFAULT_VAL_ATTR1 = 0
                               PT_SPRITE_TEX_ATTR1 = 0
                               ATTR0_VALID = 0
                               ATTR1_VALID = 0
NUM_INSTANCES:
        VGT_NUM_INSTANCES <- 1
DRAW_INDEX_AUTO:
        VGT_NUM_INDICES <- 42
        VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX
                              MAJOR_MODE = DI_MAJOR_MODE_0
                              NOT_EOP = 0
                              USE_OPAQUE = 0
SET_CONTEXT_REG:
        PA_CL_VS_OUT_CNTL <- CLIP_DIST_ENA_0 = 0
                             CLIP_DIST_ENA_1 = 0
                             CLIP_DIST_ENA_2 = 0
                             CLIP_DIST_ENA_3 = 0
                             CLIP_DIST_ENA_4 = 0
                             CLIP_DIST_ENA_5 = 0
                             CLIP_DIST_ENA_6 = 0
                             CLIP_DIST_ENA_7 = 0
                             CULL_DIST_ENA_0 = 0
                             CULL_DIST_ENA_1 = 0
                             CULL_DIST_ENA_2 = 0
                             CULL_DIST_ENA_3 = 0
                             CULL_DIST_ENA_4 = 0
                             CULL_DIST_ENA_5 = 0
                             CULL_DIST_ENA_6 = 0
                             CULL_DIST_ENA_7 = 0
                             USE_VTX_POINT_SIZE = 0
                             USE_VTX_EDGE_FLAG = 0
                             USE_VTX_RENDER_TARGET_INDX = 0
                             USE_VTX_VIEWPORT_INDX = 0
                             USE_VTX_KILL_FLAG = 0
                             VS_OUT_MISC_VEC_ENA = 0
                             VS_OUT_CCDIST0_VEC_ENA = 0
                             VS_OUT_CCDIST1_VEC_ENA = 0
                             VS_OUT_MISC_SIDE_BUS_ENA = 1
                             USE_VTX_GS_CUT_FLAG = 0
                             USE_VTX_LINE_WIDTH = 0
SET_CONTEXT_REG:
        PA_CL_CLIP_CNTL <- UCP_ENA_0 = 0
                           UCP_ENA_1 = 0
                           UCP_ENA_2 = 0
                           UCP_ENA_3 = 0
                           UCP_ENA_4 = 0
                           UCP_ENA_5 = 0
                           PS_UCP_Y_SCALE_NEG = 0
                           PS_UCP_MODE = 3
                           CLIP_DISABLE = 0
                           UCP_CULL_ONLY_ENA = 0
                           BOUNDARY_EDGE_FLAG_ENA = 0
                           DX_CLIP_SPACE_DEF = 0
                           DIS_CLIP_ERR_DETECT = 0
                           VTX_KILL_OR = 0
                           DX_RASTERIZATION_KILL = 0
                           DX_LINEAR_ATTR_CLIP_ENA = 1
                           VTE_VPORT_PROVOKE_DISABLE = 0
                           ZCLIP_NEAR_DISABLE = 0
                           ZCLIP_FAR_DISABLE = 0
SET_SH_REG:
        SPI_SHADER_USER_DATA_VS_2 <- 0x019d8300
        SPI_SHADER_USER_DATA_VS_3 <- 0
SET_SH_REG:
        SPI_SHADER_USER_DATA_VS_8 <- 0x019d8500
        SPI_SHADER_USER_DATA_VS_9 <- 0
SET_CONTEXT_REG:
        SPI_INTERP_CONTROL_0 <- FLAT_SHADE_ENA = 1
                                PNT_SPRITE_ENA = 1
                                PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
                                PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
                                PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
                                PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
                                PNT_SPRITE_TOP_1 = 0
SET_CONTEXT_REG:
        PA_SU_POINT_SIZE <- HEIGHT = 8
                            WIDTH = 8
        PA_SU_POINT_MINMAX <- MIN_SIZE = 8
                              MAX_SIZE = 8
        PA_SU_LINE_CNTL <- WIDTH = 8
SET_CONTEXT_REG:
        PA_SC_MODE_CNTL_0 <- MSAA_ENABLE = 0
                             VPORT_SCISSOR_ENABLE = 0
                             LINE_STIPPLE_ENABLE = 0
                             SEND_UNLIT_STILES_TO_PKR = 0
SET_CONTEXT_REG:
        PA_SU_VTX_CNTL <- PIX_CENTER = 1
                          ROUND_MODE = X_TRUNCATE
                          QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
SET_CONTEXT_REG:
        PA_SU_POLY_OFFSET_CLAMP <- 0
SET_CONTEXT_REG:
        PA_SU_SC_MODE_CNTL <- CULL_FRONT = 0
                              CULL_BACK = 1
                              FACE = 0
                              POLY_MODE = X_DISABLE_POLY_MODE
                              POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
                              POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
                              POLY_OFFSET_FRONT_ENABLE = 0
                              POLY_OFFSET_BACK_ENABLE = 0
                              POLY_OFFSET_PARA_ENABLE = 0
                              VTX_WINDOW_OFFSET_ENABLE = 0
                              PROVOKING_VTX_LAST = 1
                              PERSP_CORR_DIS = 0
                              MULTI_PRIM_IB_ENA = 0
SET_CONTEXT_REG:
        PA_SU_POLY_OFFSET_FRONT_SCALE <- 0
        PA_SU_POLY_OFFSET_FRONT_OFFSET <- 0
        PA_SU_POLY_OFFSET_BACK_SCALE <- 0
        PA_SU_POLY_OFFSET_BACK_OFFSET <- 0
SET_CONTEXT_REG:
        VGT_GS_MODE <- MODE = GS_OFF
                       CUT_MODE = GS_CUT_1024
                       GS_C_PACK_EN = 0
                       ES_PASSTHRU = 0
                       COMPUTE_MODE = 0
                       FAST_COMPUTE_MODE = 0
                       ELEMENT_INFO_EN = 0
                       PARTIAL_THD_AT_EOI = 0
                       SUPPRESS_CUTS = 0
                       ES_WRITE_OPTIMIZE = 0
                       GS_WRITE_OPTIMIZE = 0
                       ONCHIP = X_0_OFFCHIP_GS
SET_CONTEXT_REG:
        VGT_PRIMITIVEID_EN <- PRIMITIVEID_EN = 0
                              DISABLE_RESET_ON_EOI = 0
SET_CONTEXT_REG:
        SPI_VS_OUT_CONFIG <- VS_EXPORT_COUNT = 0
                             VS_HALF_PACK = 0
                             VS_EXPORTS_FOG = 0
                             VS_OUT_FOG_VEC_ADDR = 0
SET_CONTEXT_REG:
        SPI_SHADER_POS_FORMAT <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
SET_SH_REG:
        SPI_SHADER_PGM_LO_VS <- 0x0001b000
        SPI_SHADER_PGM_HI_VS <- MEM_BASE = 0
        SPI_SHADER_PGM_RSRC1_VS <- VGPRS = 2
                                   SGPRS = 9
                                   PRIORITY = 0
                                   FLOAT_MODE = 0
                                   PRIV = 0
                                   DX10_CLAMP = 1
                                   DEBUG_MODE = 0
                                   IEEE_MODE = 0
                                   VGPR_COMP_CNT = 0
                                   CU_GROUP_ENABLE = 0
                                   CACHE_CTL = 0
                                   CDBG_USER = 0
        SPI_SHADER_PGM_RSRC2_VS <- SCRATCH_EN = 0
                                   USER_SGPR = 12
                                   TRAP_PRESENT = 0
                                   OC_LDS_EN = 0
                                   SO_BASE0_EN = 0
                                   SO_BASE1_EN = 0
                                   SO_BASE2_EN = 0
                                   SO_BASE3_EN = 0
                                   SO_EN = 0
                                   EXCP_EN = 0
                                   EXCP_EN_CIK = 0
                                   DISPATCH_DRAW_EN = 0
SET_CONTEXT_REG:
        PA_CL_VTE_CNTL <- VPORT_X_SCALE_ENA = 1
                          VPORT_X_OFFSET_ENA = 1
                          VPORT_Y_SCALE_ENA = 1
                          VPORT_Y_OFFSET_ENA = 1
                          VPORT_Z_SCALE_ENA = 1
                          VPORT_Z_OFFSET_ENA = 1
                          VTX_XY_FMT = 0
                          VTX_Z_FMT = 0
                          VTX_W0_FMT = 1
SET_CONTEXT_REG:
        SPI_PS_INPUT_CNTL_0 <- OFFSET = 0
                               DEFAULT_VAL = X_0_0F
                               FLAT_SHADE = 1
                               CYL_WRAP = 0
                               PT_SPRITE_TEX = 0
                               DUP = 0
                               FP16_INTERP_MODE = 0
                               USE_DEFAULT_ATTR1 = 0
                               DEFAULT_VAL_ATTR1 = 0
                               PT_SPRITE_TEX_ATTR1 = 0
                               ATTR0_VALID = 0
                               ATTR1_VALID = 0
NUM_INSTANCES:
        VGT_NUM_INSTANCES <- 1
DRAW_INDEX_AUTO:
        VGT_NUM_INDICES <- 42
        VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX
                              MAJOR_MODE = DI_MAJOR_MODE_0
                              NOT_EOP = 0
                              USE_OPAQUE = 0
DRAW_PREAMBLE:
        VGT_PRIMITIVE_TYPE <- PRIM_TYPE = DI_PT_QUADLIST
        IA_MULTI_VGT_PARAM <- PRIMGROUP_SIZE = 127
                              PARTIAL_VS_WAVE_ON = 0
                              SWITCH_ON_EOP = 0
                              PARTIAL_ES_WAVE_ON = 0
                              SWITCH_ON_EOI = 0
                              WD_SWITCH_ON_EOP = 0
                              MAX_PRIMGRP_IN_WAVE = 2
        VGT_LS_HS_CONFIG <- NUM_PATCHES = 0
                            HS_NUM_INPUT_CP = 0
                            HS_NUM_OUTPUT_CP = 0
NUM_INSTANCES:
        VGT_NUM_INSTANCES <- 1
SET_SH_REG:
        SPI_SHADER_USER_DATA_VS_10 <- 42
        SPI_SHADER_USER_DATA_VS_11 <- 0
DRAW_INDEX_AUTO:
        VGT_NUM_INDICES <- 40
        VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX
                              MAJOR_MODE = DI_MAJOR_MODE_0
                              NOT_EOP = 0
                              USE_OPAQUE = 0
SET_SH_REG:
        SPI_SHADER_USER_DATA_VS_2 <- 0x019d8700
        SPI_SHADER_USER_DATA_VS_3 <- 0
SET_SH_REG:
        SPI_SHADER_USER_DATA_VS_8 <- 0x019d8900
        SPI_SHADER_USER_DATA_VS_9 <- 0
DRAW_PREAMBLE:
        VGT_PRIMITIVE_TYPE <- PRIM_TYPE = DI_PT_QUADSTRIP
        IA_MULTI_VGT_PARAM <- PRIMGROUP_SIZE = 127
                              PARTIAL_VS_WAVE_ON = 0
                              SWITCH_ON_EOP = 0
                              PARTIAL_ES_WAVE_ON = 0
                              SWITCH_ON_EOI = 0
                              WD_SWITCH_ON_EOP = 0
                              MAX_PRIMGRP_IN_WAVE = 2
        VGT_LS_HS_CONFIG <- NUM_PATCHES = 0
                            HS_NUM_INPUT_CP = 0
                            HS_NUM_OUTPUT_CP = 0
NUM_INSTANCES:
        VGT_NUM_INSTANCES <- 1
SET_SH_REG:
        SPI_SHADER_USER_DATA_VS_10 <- 0
        SPI_SHADER_USER_DATA_VS_11 <- 0
DRAW_INDEX_AUTO:
        VGT_NUM_INDICES <- 42
        VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX
                              MAJOR_MODE = DI_MAJOR_MODE_0
                              NOT_EOP = 0
                              USE_OPAQUE = 0
DRAW_PREAMBLE:
        VGT_PRIMITIVE_TYPE <- PRIM_TYPE = DI_PT_QUADLIST
        IA_MULTI_VGT_PARAM <- PRIMGROUP_SIZE = 127
                              PARTIAL_VS_WAVE_ON = 0
                              SWITCH_ON_EOP = 0
                              PARTIAL_ES_WAVE_ON = 0
                              SWITCH_ON_EOI = 0
                              WD_SWITCH_ON_EOP = 0
                              MAX_PRIMGRP_IN_WAVE = 2
        VGT_LS_HS_CONFIG <- NUM_PATCHES = 0
                            HS_NUM_INPUT_CP = 0
                            HS_NUM_OUTPUT_CP = 0
NUM_INSTANCES:
        VGT_NUM_INSTANCES <- 1
SET_SH_REG:
        SPI_SHADER_USER_DATA_VS_10 <- 42
        SPI_SHADER_USER_DATA_VS_11 <- 0
DRAW_INDEX_AUTO:
        VGT_NUM_INDICES <- 40
        VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX
                              MAJOR_MODE = DI_MAJOR_MODE_0
                              NOT_EOP = 0
                              USE_OPAQUE = 0
SET_CONTEXT_REG:
        PA_CL_VS_OUT_CNTL <- CLIP_DIST_ENA_0 = 0
                             CLIP_DIST_ENA_1 = 0
                             CLIP_DIST_ENA_2 = 0
                             CLIP_DIST_ENA_3 = 0
                             CLIP_DIST_ENA_4 = 0
                             CLIP_DIST_ENA_5 = 0
                             CLIP_DIST_ENA_6 = 0
                             CLIP_DIST_ENA_7 = 0
                             CULL_DIST_ENA_0 = 0
                             CULL_DIST_ENA_1 = 0
                             CULL_DIST_ENA_2 = 0
                             CULL_DIST_ENA_3 = 0
                             CULL_DIST_ENA_4 = 0
                             CULL_DIST_ENA_5 = 0
                             CULL_DIST_ENA_6 = 0
                             CULL_DIST_ENA_7 = 0
                             USE_VTX_POINT_SIZE = 0
                             USE_VTX_EDGE_FLAG = 0
                             USE_VTX_RENDER_TARGET_INDX = 0
                             USE_VTX_VIEWPORT_INDX = 0
                             USE_VTX_KILL_FLAG = 0
                             VS_OUT_MISC_VEC_ENA = 0
                             VS_OUT_CCDIST0_VEC_ENA = 0
                             VS_OUT_CCDIST1_VEC_ENA = 0
                             VS_OUT_MISC_SIDE_BUS_ENA = 1
                             USE_VTX_GS_CUT_FLAG = 0
                             USE_VTX_LINE_WIDTH = 0
SET_CONTEXT_REG:
        PA_CL_CLIP_CNTL <- UCP_ENA_0 = 0
                           UCP_ENA_1 = 0
                           UCP_ENA_2 = 0
                           UCP_ENA_3 = 0
                           UCP_ENA_4 = 0
                           UCP_ENA_5 = 0
                           PS_UCP_Y_SCALE_NEG = 0
                           PS_UCP_MODE = 3
                           CLIP_DISABLE = 0
                           UCP_CULL_ONLY_ENA = 0
                           BOUNDARY_EDGE_FLAG_ENA = 0
                           DX_CLIP_SPACE_DEF = 0
                           DIS_CLIP_ERR_DETECT = 0
                           VTX_KILL_OR = 0
                           DX_RASTERIZATION_KILL = 0
                           DX_LINEAR_ATTR_CLIP_ENA = 1
                           VTE_VPORT_PROVOKE_DISABLE = 0
                           ZCLIP_NEAR_DISABLE = 0
                           ZCLIP_FAR_DISABLE = 0
SET_SH_REG:
        SPI_SHADER_USER_DATA_VS_2 <- 0x019d8b00
        SPI_SHADER_USER_DATA_VS_3 <- 0
SET_SH_REG:
        SPI_SHADER_USER_DATA_VS_8 <- 0x019d8d00
        SPI_SHADER_USER_DATA_VS_9 <- 0
SET_CONTEXT_REG:
        VGT_GS_MODE <- MODE = GS_OFF
                       CUT_MODE = GS_CUT_1024
                       GS_C_PACK_EN = 0
                       ES_PASSTHRU = 0
                       COMPUTE_MODE = 0
                       FAST_COMPUTE_MODE = 0
                       ELEMENT_INFO_EN = 0
                       PARTIAL_THD_AT_EOI = 0
                       SUPPRESS_CUTS = 0
                       ES_WRITE_OPTIMIZE = 0
                       GS_WRITE_OPTIMIZE = 0
                       ONCHIP = X_0_OFFCHIP_GS
SET_CONTEXT_REG:
        VGT_PRIMITIVEID_EN <- PRIMITIVEID_EN = 0
                              DISABLE_RESET_ON_EOI = 0
SET_CONTEXT_REG:
        SPI_VS_OUT_CONFIG <- VS_EXPORT_COUNT = 0
                             VS_HALF_PACK = 0
                             VS_EXPORTS_FOG = 0
                             VS_OUT_FOG_VEC_ADDR = 0
SET_CONTEXT_REG:
        SPI_SHADER_POS_FORMAT <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
SET_SH_REG:
        SPI_SHADER_PGM_LO_VS <- 0x0001b200
        SPI_SHADER_PGM_HI_VS <- MEM_BASE = 0
        SPI_SHADER_PGM_RSRC1_VS <- VGPRS = 2
                                   SGPRS = 9
                                   PRIORITY = 0
                                   FLOAT_MODE = 0
                                   PRIV = 0
                                   DX10_CLAMP = 1
                                   DEBUG_MODE = 0
                                   IEEE_MODE = 0
                                   VGPR_COMP_CNT = 0
                                   CU_GROUP_ENABLE = 0
                                   CACHE_CTL = 0
                                   CDBG_USER = 0
        SPI_SHADER_PGM_RSRC2_VS <- SCRATCH_EN = 0
                                   USER_SGPR = 12
                                   TRAP_PRESENT = 0
                                   OC_LDS_EN = 0
                                   SO_BASE0_EN = 0
                                   SO_BASE1_EN = 0
                                   SO_BASE2_EN = 0
                                   SO_BASE3_EN = 0
                                   SO_EN = 0
                                   EXCP_EN = 0
                                   EXCP_EN_CIK = 0
                                   DISPATCH_DRAW_EN = 0
SET_CONTEXT_REG:
        PA_CL_VTE_CNTL <- VPORT_X_SCALE_ENA = 1
                          VPORT_X_OFFSET_ENA = 1
                          VPORT_Y_SCALE_ENA = 1
                          VPORT_Y_OFFSET_ENA = 1
                          VPORT_Z_SCALE_ENA = 1
                          VPORT_Z_OFFSET_ENA = 1
                          VTX_XY_FMT = 0
                          VTX_Z_FMT = 0
                          VTX_W0_FMT = 1
SET_CONTEXT_REG:
        SPI_PS_INPUT_CNTL_0 <- OFFSET = 0
                               DEFAULT_VAL = X_0_0F
                               FLAT_SHADE = 1
                               CYL_WRAP = 0
                               PT_SPRITE_TEX = 0
                               DUP = 0
                               FP16_INTERP_MODE = 0
                               USE_DEFAULT_ATTR1 = 0
                               DEFAULT_VAL_ATTR1 = 0
                               PT_SPRITE_TEX_ATTR1 = 0
                               ATTR0_VALID = 0
                               ATTR1_VALID = 0
DRAW_PREAMBLE:
        VGT_PRIMITIVE_TYPE <- PRIM_TYPE = DI_PT_QUADSTRIP
        IA_MULTI_VGT_PARAM <- PRIMGROUP_SIZE = 127
                              PARTIAL_VS_WAVE_ON = 0
                              SWITCH_ON_EOP = 0
                              PARTIAL_ES_WAVE_ON = 0
                              SWITCH_ON_EOI = 0
                              WD_SWITCH_ON_EOP = 0
                              MAX_PRIMGRP_IN_WAVE = 2
        VGT_LS_HS_CONFIG <- NUM_PATCHES = 0
                            HS_NUM_INPUT_CP = 0
                            HS_NUM_OUTPUT_CP = 0
NUM_INSTANCES:
        VGT_NUM_INSTANCES <- 1
SET_SH_REG:
        SPI_SHADER_USER_DATA_VS_10 <- 0
        SPI_SHADER_USER_DATA_VS_11 <- 0
DRAW_INDEX_AUTO:
        VGT_NUM_INDICES <- 82
        VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX
                              MAJOR_MODE = DI_MAJOR_MODE_0
                              NOT_EOP = 0
                              USE_OPAQUE = 0
SET_CONTEXT_REG:
        PA_CL_VS_OUT_CNTL <- CLIP_DIST_ENA_0 = 0
                             CLIP_DIST_ENA_1 = 0
                             CLIP_DIST_ENA_2 = 0
                             CLIP_DIST_ENA_3 = 0
                             CLIP_DIST_ENA_4 = 0
                             CLIP_DIST_ENA_5 = 0
                             CLIP_DIST_ENA_6 = 0
                             CLIP_DIST_ENA_7 = 0
                             CULL_DIST_ENA_0 = 0
                             CULL_DIST_ENA_1 = 0
                             CULL_DIST_ENA_2 = 0
                             CULL_DIST_ENA_3 = 0
                             CULL_DIST_ENA_4 = 0
                             CULL_DIST_ENA_5 = 0
                             CULL_DIST_ENA_6 = 0
                             CULL_DIST_ENA_7 = 0
                             USE_VTX_POINT_SIZE = 0
                             USE_VTX_EDGE_FLAG = 0
                             USE_VTX_RENDER_TARGET_INDX = 0
                             USE_VTX_VIEWPORT_INDX = 0
                             USE_VTX_KILL_FLAG = 0
                             VS_OUT_MISC_VEC_ENA = 0
                             VS_OUT_CCDIST0_VEC_ENA = 0
                             VS_OUT_CCDIST1_VEC_ENA = 0
                             VS_OUT_MISC_SIDE_BUS_ENA = 1
                             USE_VTX_GS_CUT_FLAG = 0
                             USE_VTX_LINE_WIDTH = 0
SET_CONTEXT_REG:
        PA_CL_CLIP_CNTL <- UCP_ENA_0 = 0
                           UCP_ENA_1 = 0
                           UCP_ENA_2 = 0
                           UCP_ENA_3 = 0
                           UCP_ENA_4 = 0
                           UCP_ENA_5 = 0
                           PS_UCP_Y_SCALE_NEG = 0
                           PS_UCP_MODE = 3
                           CLIP_DISABLE = 0
                           UCP_CULL_ONLY_ENA = 0
                           BOUNDARY_EDGE_FLAG_ENA = 0
                           DX_CLIP_SPACE_DEF = 0
                           DIS_CLIP_ERR_DETECT = 0
                           VTX_KILL_OR = 0
                           DX_RASTERIZATION_KILL = 0
                           DX_LINEAR_ATTR_CLIP_ENA = 1
                           VTE_VPORT_PROVOKE_DISABLE = 0
                           ZCLIP_NEAR_DISABLE = 0
                           ZCLIP_FAR_DISABLE = 0
SET_SH_REG:
        SPI_SHADER_USER_DATA_VS_2 <- 0x019d8f00
        SPI_SHADER_USER_DATA_VS_3 <- 0
SET_SH_REG:
        SPI_SHADER_USER_DATA_VS_8 <- 0x019d9100
        SPI_SHADER_USER_DATA_VS_9 <- 0
SET_CONTEXT_REG:
        SPI_INTERP_CONTROL_0 <- FLAT_SHADE_ENA = 1
                                PNT_SPRITE_ENA = 1
                                PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
                                PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
                                PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
                                PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
                                PNT_SPRITE_TOP_1 = 0
SET_CONTEXT_REG:
        PA_SU_POINT_SIZE <- HEIGHT = 8
                            WIDTH = 8
        PA_SU_POINT_MINMAX <- MIN_SIZE = 8
                              MAX_SIZE = 8
        PA_SU_LINE_CNTL <- WIDTH = 8
SET_CONTEXT_REG:
        PA_SC_MODE_CNTL_0 <- MSAA_ENABLE = 0
                             VPORT_SCISSOR_ENABLE = 0
                             LINE_STIPPLE_ENABLE = 0
                             SEND_UNLIT_STILES_TO_PKR = 0
SET_CONTEXT_REG:
        PA_SU_VTX_CNTL <- PIX_CENTER = 1
                          ROUND_MODE = X_TRUNCATE
                          QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
SET_CONTEXT_REG:
        PA_SU_POLY_OFFSET_CLAMP <- 0
SET_CONTEXT_REG:
        PA_SU_SC_MODE_CNTL <- CULL_FRONT = 0
                              CULL_BACK = 1
                              FACE = 0
                              POLY_MODE = X_DISABLE_POLY_MODE
                              POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
                              POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
                              POLY_OFFSET_FRONT_ENABLE = 0
                              POLY_OFFSET_BACK_ENABLE = 0
                              POLY_OFFSET_PARA_ENABLE = 0
                              VTX_WINDOW_OFFSET_ENABLE = 0
                              PROVOKING_VTX_LAST = 1
                              PERSP_CORR_DIS = 0
                              MULTI_PRIM_IB_ENA = 0
SET_CONTEXT_REG:
        PA_SU_POLY_OFFSET_FRONT_SCALE <- 0
        PA_SU_POLY_OFFSET_FRONT_OFFSET <- 0
        PA_SU_POLY_OFFSET_BACK_SCALE <- 0
        PA_SU_POLY_OFFSET_BACK_OFFSET <- 0
SET_CONTEXT_REG:
        SPI_PS_INPUT_CNTL_0 <- OFFSET = 0
                               DEFAULT_VAL = X_0_0F
                               FLAT_SHADE = 0
                               CYL_WRAP = 0
                               PT_SPRITE_TEX = 0
                               DUP = 0
                               FP16_INTERP_MODE = 0
                               USE_DEFAULT_ATTR1 = 0
                               DEFAULT_VAL_ATTR1 = 0
                               PT_SPRITE_TEX_ATTR1 = 0
                               ATTR0_VALID = 0
                               ATTR1_VALID = 0
NUM_INSTANCES:
        VGT_NUM_INSTANCES <- 1
DRAW_INDEX_AUTO:
        VGT_NUM_INDICES <- 22
        VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX
                              MAJOR_MODE = DI_MAJOR_MODE_0
                              NOT_EOP = 0
                              USE_OPAQUE = 0
SET_CONTEXT_REG:
        PA_CL_VS_OUT_CNTL <- CLIP_DIST_ENA_0 = 0
                             CLIP_DIST_ENA_1 = 0
                             CLIP_DIST_ENA_2 = 0
                             CLIP_DIST_ENA_3 = 0
                             CLIP_DIST_ENA_4 = 0
                             CLIP_DIST_ENA_5 = 0
                             CLIP_DIST_ENA_6 = 0
                             CLIP_DIST_ENA_7 = 0
                             CULL_DIST_ENA_0 = 0
                             CULL_DIST_ENA_1 = 0
                             CULL_DIST_ENA_2 = 0
                             CULL_DIST_ENA_3 = 0
                             CULL_DIST_ENA_4 = 0
                             CULL_DIST_ENA_5 = 0
                             CULL_DIST_ENA_6 = 0
                             CULL_DIST_ENA_7 = 0
                             USE_VTX_POINT_SIZE = 0
                             USE_VTX_EDGE_FLAG = 0
                             USE_VTX_RENDER_TARGET_INDX = 0
                             USE_VTX_VIEWPORT_INDX = 0
                             USE_VTX_KILL_FLAG = 0
                             VS_OUT_MISC_VEC_ENA = 0
                             VS_OUT_CCDIST0_VEC_ENA = 0
                             VS_OUT_CCDIST1_VEC_ENA = 0
                             VS_OUT_MISC_SIDE_BUS_ENA = 1
                             USE_VTX_GS_CUT_FLAG = 0
                             USE_VTX_LINE_WIDTH = 0
SET_CONTEXT_REG:
        PA_CL_CLIP_CNTL <- UCP_ENA_0 = 0
                           UCP_ENA_1 = 0
                           UCP_ENA_2 = 0
                           UCP_ENA_3 = 0
                           UCP_ENA_4 = 0
                           UCP_ENA_5 = 0
                           PS_UCP_Y_SCALE_NEG = 0
                           PS_UCP_MODE = 3
                           CLIP_DISABLE = 0
                           UCP_CULL_ONLY_ENA = 0
                           BOUNDARY_EDGE_FLAG_ENA = 0
                           DX_CLIP_SPACE_DEF = 0
                           DIS_CLIP_ERR_DETECT = 0
                           VTX_KILL_OR = 0
                           DX_RASTERIZATION_KILL = 0
                           DX_LINEAR_ATTR_CLIP_ENA = 1
                           VTE_VPORT_PROVOKE_DISABLE = 0
                           ZCLIP_NEAR_DISABLE = 0
                           ZCLIP_FAR_DISABLE = 0
SET_SH_REG:
        SPI_SHADER_USER_DATA_VS_2 <- 0x019d9300
        SPI_SHADER_USER_DATA_VS_3 <- 0
SET_SH_REG:
        SPI_SHADER_USER_DATA_VS_8 <- 0x019d9500
        SPI_SHADER_USER_DATA_VS_9 <- 0
SET_CONTEXT_REG:
        SPI_INTERP_CONTROL_0 <- FLAT_SHADE_ENA = 1
                                PNT_SPRITE_ENA = 1
                                PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
                                PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
                                PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
                                PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
                                PNT_SPRITE_TOP_1 = 0
SET_CONTEXT_REG:
        PA_SU_POINT_SIZE <- HEIGHT = 8
                            WIDTH = 8
        PA_SU_POINT_MINMAX <- MIN_SIZE = 8
                              MAX_SIZE = 8
        PA_SU_LINE_CNTL <- WIDTH = 8
SET_CONTEXT_REG:
        PA_SC_MODE_CNTL_0 <- MSAA_ENABLE = 0
                             VPORT_SCISSOR_ENABLE = 0
                             LINE_STIPPLE_ENABLE = 0
                             SEND_UNLIT_STILES_TO_PKR = 0
SET_CONTEXT_REG:
        PA_SU_VTX_CNTL <- PIX_CENTER = 1
                          ROUND_MODE = X_TRUNCATE
                          QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
SET_CONTEXT_REG:
        PA_SU_POLY_OFFSET_CLAMP <- 0
SET_CONTEXT_REG:
        PA_SU_SC_MODE_CNTL <- CULL_FRONT = 0
                              CULL_BACK = 1
                              FACE = 0
                              POLY_MODE = X_DISABLE_POLY_MODE
                              POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
                              POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
                              POLY_OFFSET_FRONT_ENABLE = 0
                              POLY_OFFSET_BACK_ENABLE = 0
                              POLY_OFFSET_PARA_ENABLE = 0
                              VTX_WINDOW_OFFSET_ENABLE = 0
                              PROVOKING_VTX_LAST = 1
                              PERSP_CORR_DIS = 0
                              MULTI_PRIM_IB_ENA = 0
SET_CONTEXT_REG:
        PA_SU_POLY_OFFSET_FRONT_SCALE <- 0
        PA_SU_POLY_OFFSET_FRONT_OFFSET <- 0
        PA_SU_POLY_OFFSET_BACK_SCALE <- 0
        PA_SU_POLY_OFFSET_BACK_OFFSET <- 0
SET_CONTEXT_REG:
        VGT_GS_MODE <- MODE = GS_OFF
                       CUT_MODE = GS_CUT_1024
                       GS_C_PACK_EN = 0
                       ES_PASSTHRU = 0
                       COMPUTE_MODE = 0
                       FAST_COMPUTE_MODE = 0
                       ELEMENT_INFO_EN = 0
                       PARTIAL_THD_AT_EOI = 0
                       SUPPRESS_CUTS = 0
                       ES_WRITE_OPTIMIZE = 0
                       GS_WRITE_OPTIMIZE = 0
                       ONCHIP = X_0_OFFCHIP_GS
SET_CONTEXT_REG:
        VGT_PRIMITIVEID_EN <- PRIMITIVEID_EN = 0
                              DISABLE_RESET_ON_EOI = 0
SET_CONTEXT_REG:
        SPI_VS_OUT_CONFIG <- VS_EXPORT_COUNT = 0
                             VS_HALF_PACK = 0
                             VS_EXPORTS_FOG = 0
                             VS_OUT_FOG_VEC_ADDR = 0
SET_CONTEXT_REG:
        SPI_SHADER_POS_FORMAT <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
SET_SH_REG:
        SPI_SHADER_PGM_LO_VS <- 0x0001b000
        SPI_SHADER_PGM_HI_VS <- MEM_BASE = 0
        SPI_SHADER_PGM_RSRC1_VS <- VGPRS = 2
                                   SGPRS = 9
                                   PRIORITY = 0
                                   FLOAT_MODE = 0
                                   PRIV = 0
                                   DX10_CLAMP = 1
                                   DEBUG_MODE = 0
                                   IEEE_MODE = 0
                                   VGPR_COMP_CNT = 0
                                   CU_GROUP_ENABLE = 0
                                   CACHE_CTL = 0
                                   CDBG_USER = 0
        SPI_SHADER_PGM_RSRC2_VS <- SCRATCH_EN = 0
                                   USER_SGPR = 12
                                   TRAP_PRESENT = 0
                                   OC_LDS_EN = 0
                                   SO_BASE0_EN = 0
                                   SO_BASE1_EN = 0
                                   SO_BASE2_EN = 0
                                   SO_BASE3_EN = 0
                                   SO_EN = 0
                                   EXCP_EN = 0
                                   EXCP_EN_CIK = 0
                                   DISPATCH_DRAW_EN = 0
SET_CONTEXT_REG:
        PA_CL_VTE_CNTL <- VPORT_X_SCALE_ENA = 1
                          VPORT_X_OFFSET_ENA = 1
                          VPORT_Y_SCALE_ENA = 1
                          VPORT_Y_OFFSET_ENA = 1
                          VPORT_Z_SCALE_ENA = 1
                          VPORT_Z_OFFSET_ENA = 1
                          VTX_XY_FMT = 0
                          VTX_Z_FMT = 0
                          VTX_W0_FMT = 1
SET_CONTEXT_REG:
        SPI_PS_INPUT_CNTL_0 <- OFFSET = 0
                               DEFAULT_VAL = X_0_0F
                               FLAT_SHADE = 1
                               CYL_WRAP = 0
                               PT_SPRITE_TEX = 0
                               DUP = 0
                               FP16_INTERP_MODE = 0
                               USE_DEFAULT_ATTR1 = 0
                               DEFAULT_VAL_ATTR1 = 0
                               PT_SPRITE_TEX_ATTR1 = 0
                               ATTR0_VALID = 0
                               ATTR1_VALID = 0
NUM_INSTANCES:
        VGT_NUM_INSTANCES <- 1
DRAW_INDEX_AUTO:
        VGT_NUM_INDICES <- 42
        VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX
                              MAJOR_MODE = DI_MAJOR_MODE_0
                              NOT_EOP = 0
                              USE_OPAQUE = 0
DRAW_PREAMBLE:
        VGT_PRIMITIVE_TYPE <- PRIM_TYPE = DI_PT_QUADLIST
        IA_MULTI_VGT_PARAM <- PRIMGROUP_SIZE = 127
                              PARTIAL_VS_WAVE_ON = 0
                              SWITCH_ON_EOP = 0
                              PARTIAL_ES_WAVE_ON = 0
                              SWITCH_ON_EOI = 0
                              WD_SWITCH_ON_EOP = 0
                              MAX_PRIMGRP_IN_WAVE = 2
        VGT_LS_HS_CONFIG <- NUM_PATCHES = 0
                            HS_NUM_INPUT_CP = 0
                            HS_NUM_OUTPUT_CP = 0
NUM_INSTANCES:
        VGT_NUM_INSTANCES <- 1
SET_SH_REG:
        SPI_SHADER_USER_DATA_VS_10 <- 42
        SPI_SHADER_USER_DATA_VS_11 <- 0
DRAW_INDEX_AUTO:
        VGT_NUM_INDICES <- 40
        VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX
                              MAJOR_MODE = DI_MAJOR_MODE_0
                              NOT_EOP = 0
                              USE_OPAQUE = 0
SET_SH_REG:
        SPI_SHADER_USER_DATA_VS_2 <- 0x019d9700
        SPI_SHADER_USER_DATA_VS_3 <- 0
SET_SH_REG:
        SPI_SHADER_USER_DATA_VS_8 <- 0x019d9900
        SPI_SHADER_USER_DATA_VS_9 <- 0
DRAW_PREAMBLE:
        VGT_PRIMITIVE_TYPE <- PRIM_TYPE = DI_PT_QUADSTRIP
        IA_MULTI_VGT_PARAM <- PRIMGROUP_SIZE = 127
                              PARTIAL_VS_WAVE_ON = 0
                              SWITCH_ON_EOP = 0
                              PARTIAL_ES_WAVE_ON = 0
                              SWITCH_ON_EOI = 0
                              WD_SWITCH_ON_EOP = 0
                              MAX_PRIMGRP_IN_WAVE = 2
        VGT_LS_HS_CONFIG <- NUM_PATCHES = 0
                            HS_NUM_INPUT_CP = 0
                            HS_NUM_OUTPUT_CP = 0
NUM_INSTANCES:
        VGT_NUM_INSTANCES <- 1
SET_SH_REG:
        SPI_SHADER_USER_DATA_VS_10 <- 0
        SPI_SHADER_USER_DATA_VS_11 <- 0
DRAW_INDEX_AUTO:
        VGT_NUM_INDICES <- 42
        VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX
                              MAJOR_MODE = DI_MAJOR_MODE_0
                              NOT_EOP = 0
                              USE_OPAQUE = 0
DRAW_PREAMBLE:
        VGT_PRIMITIVE_TYPE <- PRIM_TYPE = DI_PT_QUADLIST
        IA_MULTI_VGT_PARAM <- PRIMGROUP_SIZE = 127
                              PARTIAL_VS_WAVE_ON = 0
                              SWITCH_ON_EOP = 0
                              PARTIAL_ES_WAVE_ON = 0
                              SWITCH_ON_EOI = 0
                              WD_SWITCH_ON_EOP = 0
                              MAX_PRIMGRP_IN_WAVE = 2
        VGT_LS_HS_CONFIG <- NUM_PATCHES = 0
                            HS_NUM_INPUT_CP = 0
                            HS_NUM_OUTPUT_CP = 0
NUM_INSTANCES:
        VGT_NUM_INSTANCES <- 1
SET_SH_REG:
        SPI_SHADER_USER_DATA_VS_10 <- 42
        SPI_SHADER_USER_DATA_VS_11 <- 0
DRAW_INDEX_AUTO:
        VGT_NUM_INDICES <- 40
        VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX
                              MAJOR_MODE = DI_MAJOR_MODE_0
                              NOT_EOP = 0
                              USE_OPAQUE = 0
SET_CONTEXT_REG:
        PA_CL_VS_OUT_CNTL <- CLIP_DIST_ENA_0 = 0
                             CLIP_DIST_ENA_1 = 0
                             CLIP_DIST_ENA_2 = 0
                             CLIP_DIST_ENA_3 = 0
                             CLIP_DIST_ENA_4 = 0
                             CLIP_DIST_ENA_5 = 0
                             CLIP_DIST_ENA_6 = 0
                             CLIP_DIST_ENA_7 = 0
                             CULL_DIST_ENA_0 = 0
                             CULL_DIST_ENA_1 = 0
                             CULL_DIST_ENA_2 = 0
                             CULL_DIST_ENA_3 = 0
                             CULL_DIST_ENA_4 = 0
                             CULL_DIST_ENA_5 = 0
                             CULL_DIST_ENA_6 = 0
                             CULL_DIST_ENA_7 = 0
                             USE_VTX_POINT_SIZE = 0
                             USE_VTX_EDGE_FLAG = 0
                             USE_VTX_RENDER_TARGET_INDX = 0
                             USE_VTX_VIEWPORT_INDX = 0
                             USE_VTX_KILL_FLAG = 0
                             VS_OUT_MISC_VEC_ENA = 0
                             VS_OUT_CCDIST0_VEC_ENA = 0
                             VS_OUT_CCDIST1_VEC_ENA = 0
                             VS_OUT_MISC_SIDE_BUS_ENA = 1
                             USE_VTX_GS_CUT_FLAG = 0
                             USE_VTX_LINE_WIDTH = 0
SET_CONTEXT_REG:
        PA_CL_CLIP_CNTL <- UCP_ENA_0 = 0
                           UCP_ENA_1 = 0
                           UCP_ENA_2 = 0
                           UCP_ENA_3 = 0
                           UCP_ENA_4 = 0
                           UCP_ENA_5 = 0
                           PS_UCP_Y_SCALE_NEG = 0
                           PS_UCP_MODE = 3
                           CLIP_DISABLE = 0
                           UCP_CULL_ONLY_ENA = 0
                           BOUNDARY_EDGE_FLAG_ENA = 0
                           DX_CLIP_SPACE_DEF = 0
                           DIS_CLIP_ERR_DETECT = 0
                           VTX_KILL_OR = 0
                           DX_RASTERIZATION_KILL = 0
                           DX_LINEAR_ATTR_CLIP_ENA = 1
                           VTE_VPORT_PROVOKE_DISABLE = 0
                           ZCLIP_NEAR_DISABLE = 0
                           ZCLIP_FAR_DISABLE = 0
SET_SH_REG:
        SPI_SHADER_USER_DATA_VS_2 <- 0x019d9b00
        SPI_SHADER_USER_DATA_VS_3 <- 0
SET_SH_REG:
        SPI_SHADER_USER_DATA_VS_8 <- 0x019d9d00
        SPI_SHADER_USER_DATA_VS_9 <- 0
SET_CONTEXT_REG:
        VGT_GS_MODE <- MODE = GS_OFF
                       CUT_MODE = GS_CUT_1024
                       GS_C_PACK_EN = 0
                       ES_PASSTHRU = 0
                       COMPUTE_MODE = 0
                       FAST_COMPUTE_MODE = 0
                       ELEMENT_INFO_EN = 0
                       PARTIAL_THD_AT_EOI = 0
                       SUPPRESS_CUTS = 0
                       ES_WRITE_OPTIMIZE = 0
                       GS_WRITE_OPTIMIZE = 0
                       ONCHIP = X_0_OFFCHIP_GS
SET_CONTEXT_REG:
        VGT_PRIMITIVEID_EN <- PRIMITIVEID_EN = 0
                              DISABLE_RESET_ON_EOI = 0
SET_CONTEXT_REG:
        SPI_VS_OUT_CONFIG <- VS_EXPORT_COUNT = 0
                             VS_HALF_PACK = 0
                             VS_EXPORTS_FOG = 0
                             VS_OUT_FOG_VEC_ADDR = 0
SET_CONTEXT_REG:
        SPI_SHADER_POS_FORMAT <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
SET_SH_REG:
        SPI_SHADER_PGM_LO_VS <- 0x0001b200
        SPI_SHADER_PGM_HI_VS <- MEM_BASE = 0
        SPI_SHADER_PGM_RSRC1_VS <- VGPRS = 2
                                   SGPRS = 9
                                   PRIORITY = 0
                                   FLOAT_MODE = 0
                                   PRIV = 0
                                   DX10_CLAMP = 1
                                   DEBUG_MODE = 0
                                   IEEE_MODE = 0
                                   VGPR_COMP_CNT = 0
                                   CU_GROUP_ENABLE = 0
                                   CACHE_CTL = 0
                                   CDBG_USER = 0
        SPI_SHADER_PGM_RSRC2_VS <- SCRATCH_EN = 0
                                   USER_SGPR = 12
                                   TRAP_PRESENT = 0
                                   OC_LDS_EN = 0
                                   SO_BASE0_EN = 0
                                   SO_BASE1_EN = 0
                                   SO_BASE2_EN = 0
                                   SO_BASE3_EN = 0
                                   SO_EN = 0
                                   EXCP_EN = 0
                                   EXCP_EN_CIK = 0
                                   DISPATCH_DRAW_EN = 0
SET_CONTEXT_REG:
        PA_CL_VTE_CNTL <- VPORT_X_SCALE_ENA = 1
                          VPORT_X_OFFSET_ENA = 1
                          VPORT_Y_SCALE_ENA = 1
                          VPORT_Y_OFFSET_ENA = 1
                          VPORT_Z_SCALE_ENA = 1
                          VPORT_Z_OFFSET_ENA = 1
                          VTX_XY_FMT = 0
                          VTX_Z_FMT = 0
                          VTX_W0_FMT = 1
SET_CONTEXT_REG:
        SPI_PS_INPUT_CNTL_0 <- OFFSET = 0
                               DEFAULT_VAL = X_0_0F
                               FLAT_SHADE = 1
                               CYL_WRAP = 0
                               PT_SPRITE_TEX = 0
                               DUP = 0
                               FP16_INTERP_MODE = 0
                               USE_DEFAULT_ATTR1 = 0
                               DEFAULT_VAL_ATTR1 = 0
                               PT_SPRITE_TEX_ATTR1 = 0
                               ATTR0_VALID = 0
                               ATTR1_VALID = 0
DRAW_PREAMBLE:
        VGT_PRIMITIVE_TYPE <- PRIM_TYPE = DI_PT_QUADSTRIP
        IA_MULTI_VGT_PARAM <- PRIMGROUP_SIZE = 127
                              PARTIAL_VS_WAVE_ON = 0
                              SWITCH_ON_EOP = 0
                              PARTIAL_ES_WAVE_ON = 0
                              SWITCH_ON_EOI = 0
                              WD_SWITCH_ON_EOP = 0
                              MAX_PRIMGRP_IN_WAVE = 2
        VGT_LS_HS_CONFIG <- NUM_PATCHES = 0
                            HS_NUM_INPUT_CP = 0
                            HS_NUM_OUTPUT_CP = 0
NUM_INSTANCES:
        VGT_NUM_INSTANCES <- 1
SET_SH_REG:
        SPI_SHADER_USER_DATA_VS_10 <- 0
        SPI_SHADER_USER_DATA_VS_11 <- 0
DRAW_INDEX_AUTO:
        VGT_NUM_INDICES <- 82
        VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX
                              MAJOR_MODE = DI_MAJOR_MODE_0
                              NOT_EOP = 0
                              USE_OPAQUE = 0
SET_CONTEXT_REG:
        PA_CL_VS_OUT_CNTL <- CLIP_DIST_ENA_0 = 0
                             CLIP_DIST_ENA_1 = 0
                             CLIP_DIST_ENA_2 = 0
                             CLIP_DIST_ENA_3 = 0
                             CLIP_DIST_ENA_4 = 0
                             CLIP_DIST_ENA_5 = 0
                             CLIP_DIST_ENA_6 = 0
                             CLIP_DIST_ENA_7 = 0
                             CULL_DIST_ENA_0 = 0
                             CULL_DIST_ENA_1 = 0
                             CULL_DIST_ENA_2 = 0
                             CULL_DIST_ENA_3 = 0
                             CULL_DIST_ENA_4 = 0
                             CULL_DIST_ENA_5 = 0
                             CULL_DIST_ENA_6 = 0
                             CULL_DIST_ENA_7 = 0
                             USE_VTX_POINT_SIZE = 0
                             USE_VTX_EDGE_FLAG = 0
                             USE_VTX_RENDER_TARGET_INDX = 0
                             USE_VTX_VIEWPORT_INDX = 0
                             USE_VTX_KILL_FLAG = 0
                             VS_OUT_MISC_VEC_ENA = 0
                             VS_OUT_CCDIST0_VEC_ENA = 0
                             VS_OUT_CCDIST1_VEC_ENA = 0
                             VS_OUT_MISC_SIDE_BUS_ENA = 1
                             USE_VTX_GS_CUT_FLAG = 0
                             USE_VTX_LINE_WIDTH = 0
SET_CONTEXT_REG:
        PA_CL_CLIP_CNTL <- UCP_ENA_0 = 0
                           UCP_ENA_1 = 0
                           UCP_ENA_2 = 0
                           UCP_ENA_3 = 0
                           UCP_ENA_4 = 0
                           UCP_ENA_5 = 0
                           PS_UCP_Y_SCALE_NEG = 0
                           PS_UCP_MODE = 3
                           CLIP_DISABLE = 0
                           UCP_CULL_ONLY_ENA = 0
                           BOUNDARY_EDGE_FLAG_ENA = 0
                           DX_CLIP_SPACE_DEF = 0
                           DIS_CLIP_ERR_DETECT = 0
                           VTX_KILL_OR = 0
                           DX_RASTERIZATION_KILL = 0
                           DX_LINEAR_ATTR_CLIP_ENA = 1
                           VTE_VPORT_PROVOKE_DISABLE = 0
                           ZCLIP_NEAR_DISABLE = 0
                           ZCLIP_FAR_DISABLE = 0
SET_SH_REG:
        SPI_SHADER_USER_DATA_VS_2 <- 0x019d9f00
        SPI_SHADER_USER_DATA_VS_3 <- 0
SET_SH_REG:
        SPI_SHADER_USER_DATA_VS_8 <- 0x019da100
        SPI_SHADER_USER_DATA_VS_9 <- 0
SET_CONTEXT_REG:
        SPI_INTERP_CONTROL_0 <- FLAT_SHADE_ENA = 1
                                PNT_SPRITE_ENA = 1
                                PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
                                PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
                                PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
                                PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
                                PNT_SPRITE_TOP_1 = 0
SET_CONTEXT_REG:
        PA_SU_POINT_SIZE <- HEIGHT = 8
                            WIDTH = 8
        PA_SU_POINT_MINMAX <- MIN_SIZE = 8
                              MAX_SIZE = 8
        PA_SU_LINE_CNTL <- WIDTH = 8
SET_CONTEXT_REG:
        PA_SC_MODE_CNTL_0 <- MSAA_ENABLE = 0
                             VPORT_SCISSOR_ENABLE = 0
                             LINE_STIPPLE_ENABLE = 0
                             SEND_UNLIT_STILES_TO_PKR = 0
SET_CONTEXT_REG:
        PA_SU_VTX_CNTL <- PIX_CENTER = 1
                          ROUND_MODE = X_TRUNCATE
                          QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
SET_CONTEXT_REG:
        PA_SU_POLY_OFFSET_CLAMP <- 0
SET_CONTEXT_REG:
        PA_SU_SC_MODE_CNTL <- CULL_FRONT = 0
                              CULL_BACK = 1
                              FACE = 0
                              POLY_MODE = X_DISABLE_POLY_MODE
                              POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
                              POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
                              POLY_OFFSET_FRONT_ENABLE = 0
                              POLY_OFFSET_BACK_ENABLE = 0
                              POLY_OFFSET_PARA_ENABLE = 0
                              VTX_WINDOW_OFFSET_ENABLE = 0
                              PROVOKING_VTX_LAST = 1
                              PERSP_CORR_DIS = 0
                              MULTI_PRIM_IB_ENA = 0
SET_CONTEXT_REG:
        PA_SU_POLY_OFFSET_FRONT_SCALE <- 0
        PA_SU_POLY_OFFSET_FRONT_OFFSET <- 0
        PA_SU_POLY_OFFSET_BACK_SCALE <- 0
        PA_SU_POLY_OFFSET_BACK_OFFSET <- 0
SET_CONTEXT_REG:
        SPI_PS_INPUT_CNTL_0 <- OFFSET = 0
                               DEFAULT_VAL = X_0_0F
                               FLAT_SHADE = 0
                               CYL_WRAP = 0
                               PT_SPRITE_TEX = 0
                               DUP = 0
                               FP16_INTERP_MODE = 0
                               USE_DEFAULT_ATTR1 = 0
                               DEFAULT_VAL_ATTR1 = 0
                               PT_SPRITE_TEX_ATTR1 = 0
                               ATTR0_VALID = 0
                               ATTR1_VALID = 0
NUM_INSTANCES:
        VGT_NUM_INSTANCES <- 1
DRAW_INDEX_AUTO:
        VGT_NUM_INDICES <- 22
        VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX
                              MAJOR_MODE = DI_MAJOR_MODE_0
                              NOT_EOP = 0
                              USE_OPAQUE = 0
EVENT_WRITE:
        VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_CB_META
        EVENT_INDEX <- 0
        INV_L2 <- 0
EVENT_WRITE:
        VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_DB_META
        EVENT_INDEX <- 0
        INV_L2 <- 0
ACQUIRE_MEM:
        CP_COHER_CNTL <- DEST_BASE_0_ENA = 0
                         DEST_BASE_1_ENA = 0
                         TC_SD_ACTION_ENA = 0
                         TC_NC_ACTION_ENA = 0
                         CB0_DEST_BASE_ENA = 1
                         CB1_DEST_BASE_ENA = 1
                         CB2_DEST_BASE_ENA = 1
                         CB3_DEST_BASE_ENA = 1
                         CB4_DEST_BASE_ENA = 1
                         CB5_DEST_BASE_ENA = 1
                         CB6_DEST_BASE_ENA = 1
                         CB7_DEST_BASE_ENA = 1
                         DB_DEST_BASE_ENA = 1
                         TCL1_VOL_ACTION_ENA = 0
                         TC_VOL_ACTION_ENA = 0
                         TC_WB_ACTION_ENA = 1
                         DEST_BASE_2_ENA = 0
                         DEST_BASE_3_ENA = 0
                         TCL1_ACTION_ENA = 1
                         TC_ACTION_ENA = 1
                         CB_ACTION_ENA = 1
                         DB_ACTION_ENA = 1
                         SH_KCACHE_ACTION_ENA = 0
                         SH_KCACHE_VOL_ACTION_ENA = 0
                         SH_ICACHE_ACTION_ENA = 0
                         SH_KCACHE_WB_ACTION_ENA = 0
                         SH_SD_ACTION_ENA = 0
        CP_COHER_SIZE <- 0xffffffff
        CP_COHER_SIZE_HI <- COHER_SIZE_HI_256B = 255
        CP_COHER_BASE <- 0
        CP_COHER_BASE_HI <- COHER_BASE_HI_256B = 0
        POLL_INTERVAL <- 10
SET_CONTEXT_REG:
        CB_COLOR0_BASE <- 0x00019000
        CB_COLOR0_PITCH <- TILE_MAX = 63
                           FMASK_TILE_MAX = 63
        CB_COLOR0_SLICE <- TILE_MAX = 3071
        CB_COLOR0_VIEW <- SLICE_START = 0
                          SLICE_MAX = 0
        CB_COLOR0_INFO <- ENDIAN = ENDIAN_NONE
                          FORMAT = COLOR_8_8_8_8
                          LINEAR_GENERAL = 0
                          NUMBER_TYPE = NUMBER_UNORM
                          COMP_SWAP = SWAP_ALT
                          FAST_CLEAR = 1
                          COMPRESSION = 0
                          BLEND_CLAMP = 1
                          BLEND_BYPASS = 0
                          SIMPLE_FLOAT = 0
                          ROUND_MODE = 0
                          CMASK_IS_LINEAR = 0
                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
                          FMASK_COMPRESSION_DISABLE = 0
                          FMASK_COMPRESS_1FRAG_ONLY = 0
                          DCC_ENABLE = 0
                          CMASK_ADDR_TYPE = 0
        CB_COLOR0_ATTRIB <- TILE_MODE_INDEX = 10
                            FMASK_TILE_MODE_INDEX = 10
                            FMASK_BANK_HEIGHT = 0
                            NUM_SAMPLES = 0
                            NUM_FRAGMENTS = 0
                            FORCE_DST_ALPHA_1 = 1
        CB_COLOR0_DCC_CONTROL <- OVERWRITE_COMBINER_DISABLE = 1
                                 KEY_CLEAR_ENABLE = 0
                                 MAX_UNCOMPRESSED_BLOCK_SIZE = 0
                                 MIN_COMPRESSED_BLOCK_SIZE = 0
                                 MAX_COMPRESSED_BLOCK_SIZE = 0
                                 COLOR_TRANSFORM = 0
                                 INDEPENDENT_64B_BLOCKS = 0
                                 LOSSY_RGB_PRECISION = 0
                                 LOSSY_ALPHA_PRECISION = 0
        CB_COLOR0_CMASK <- 0x0001ad00
        CB_COLOR0_CMASK_SLICE <- TILE_MAX = 15
        CB_COLOR0_FMASK <- 0x00019000
        CB_COLOR0_FMASK_SLICE <- TILE_MAX = 3071
        CB_COLOR0_CLEAR_WORD0 <- 0xff000000
        CB_COLOR0_CLEAR_WORD1 <- 0
        CB_COLOR0_DCC_BASE <- 0
SET_CONTEXT_REG:
        CB_COLOR1_INFO <- ENDIAN = ENDIAN_NONE
                          FORMAT = COLOR_8_8_8_8
                          LINEAR_GENERAL = 0
                          NUMBER_TYPE = NUMBER_UNORM
                          COMP_SWAP = SWAP_ALT
                          FAST_CLEAR = 1
                          COMPRESSION = 0
                          BLEND_CLAMP = 1
                          BLEND_BYPASS = 0
                          SIMPLE_FLOAT = 0
                          ROUND_MODE = 0
                          CMASK_IS_LINEAR = 0
                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
                          FMASK_COMPRESSION_DISABLE = 0
                          FMASK_COMPRESS_1FRAG_ONLY = 0
                          DCC_ENABLE = 0
                          CMASK_ADDR_TYPE = 0
SET_CONTEXT_REG:
        CB_COLOR2_INFO <- ENDIAN = ENDIAN_NONE
                          FORMAT = COLOR_INVALID
                          LINEAR_GENERAL = 0
                          NUMBER_TYPE = NUMBER_UNORM
                          COMP_SWAP = SWAP_STD
                          FAST_CLEAR = 0
                          COMPRESSION = 0
                          BLEND_CLAMP = 0
                          BLEND_BYPASS = 0
                          SIMPLE_FLOAT = 0
                          ROUND_MODE = 0
                          CMASK_IS_LINEAR = 0
                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
                          FMASK_COMPRESSION_DISABLE = 0
                          FMASK_COMPRESS_1FRAG_ONLY = 0
                          DCC_ENABLE = 0
                          CMASK_ADDR_TYPE = 0
SET_CONTEXT_REG:
        CB_COLOR3_INFO <- ENDIAN = ENDIAN_NONE
                          FORMAT = COLOR_INVALID
                          LINEAR_GENERAL = 0
                          NUMBER_TYPE = NUMBER_UNORM
                          COMP_SWAP = SWAP_STD
                          FAST_CLEAR = 0
                          COMPRESSION = 0
                          BLEND_CLAMP = 0
                          BLEND_BYPASS = 0
                          SIMPLE_FLOAT = 0
                          ROUND_MODE = 0
                          CMASK_IS_LINEAR = 0
                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
                          FMASK_COMPRESSION_DISABLE = 0
                          FMASK_COMPRESS_1FRAG_ONLY = 0
                          DCC_ENABLE = 0
                          CMASK_ADDR_TYPE = 0
SET_CONTEXT_REG:
        CB_COLOR4_INFO <- ENDIAN = ENDIAN_NONE
                          FORMAT = COLOR_INVALID
                          LINEAR_GENERAL = 0
                          NUMBER_TYPE = NUMBER_UNORM
                          COMP_SWAP = SWAP_STD
                          FAST_CLEAR = 0
                          COMPRESSION = 0
                          BLEND_CLAMP = 0
                          BLEND_BYPASS = 0
                          SIMPLE_FLOAT = 0
                          ROUND_MODE = 0
                          CMASK_IS_LINEAR = 0
                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
                          FMASK_COMPRESSION_DISABLE = 0
                          FMASK_COMPRESS_1FRAG_ONLY = 0
                          DCC_ENABLE = 0
                          CMASK_ADDR_TYPE = 0
SET_CONTEXT_REG:
        CB_COLOR5_INFO <- ENDIAN = ENDIAN_NONE
                          FORMAT = COLOR_INVALID
                          LINEAR_GENERAL = 0
                          NUMBER_TYPE = NUMBER_UNORM
                          COMP_SWAP = SWAP_STD
                          FAST_CLEAR = 0
                          COMPRESSION = 0
                          BLEND_CLAMP = 0
                          BLEND_BYPASS = 0
                          SIMPLE_FLOAT = 0
                          ROUND_MODE = 0
                          CMASK_IS_LINEAR = 0
                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
                          FMASK_COMPRESSION_DISABLE = 0
                          FMASK_COMPRESS_1FRAG_ONLY = 0
                          DCC_ENABLE = 0
                          CMASK_ADDR_TYPE = 0
SET_CONTEXT_REG:
        CB_COLOR6_INFO <- ENDIAN = ENDIAN_NONE
                          FORMAT = COLOR_INVALID
                          LINEAR_GENERAL = 0
                          NUMBER_TYPE = NUMBER_UNORM
                          COMP_SWAP = SWAP_STD
                          FAST_CLEAR = 0
                          COMPRESSION = 0
                          BLEND_CLAMP = 0
                          BLEND_BYPASS = 0
                          SIMPLE_FLOAT = 0
                          ROUND_MODE = 0
                          CMASK_IS_LINEAR = 0
                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
                          FMASK_COMPRESSION_DISABLE = 0
                          FMASK_COMPRESS_1FRAG_ONLY = 0
                          DCC_ENABLE = 0
                          CMASK_ADDR_TYPE = 0
SET_CONTEXT_REG:
        CB_COLOR7_INFO <- ENDIAN = ENDIAN_NONE
                          FORMAT = COLOR_INVALID
                          LINEAR_GENERAL = 0
                          NUMBER_TYPE = NUMBER_UNORM
                          COMP_SWAP = SWAP_STD
                          FAST_CLEAR = 0
                          COMPRESSION = 0
                          BLEND_CLAMP = 0
                          BLEND_BYPASS = 0
                          SIMPLE_FLOAT = 0
                          ROUND_MODE = 0
                          CMASK_IS_LINEAR = 0
                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
                          FMASK_COMPRESSION_DISABLE = 0
                          FMASK_COMPRESS_1FRAG_ONLY = 0
                          DCC_ENABLE = 0
                          CMASK_ADDR_TYPE = 0
SET_CONTEXT_REG:
        DB_Z_INFO <- FORMAT = Z_INVALID
                     NUM_SAMPLES = 0
                     TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
                     TILE_MODE_INDEX = 0
                     DECOMPRESS_ON_N_ZPLANES = 0
                     ALLOW_EXPCLEAR = 0
                     READ_SIZE = 0
                     TILE_SURFACE_ENABLE = 0
                     CLEAR_DISALLOWED = 0
                     ZRANGE_PRECISION = 0
        DB_STENCIL_INFO <- FORMAT = STENCIL_INVALID
                           TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
                           TILE_MODE_INDEX = 0
                           ALLOW_EXPCLEAR = 0
                           TILE_STENCIL_DISABLE = 0
                           CLEAR_DISALLOWED = 0
SET_CONTEXT_REG:
        PA_SC_WINDOW_SCISSOR_BR <- BR_X = 300
                                   BR_Y = 300
SET_CONTEXT_REG:
        PA_CL_VS_OUT_CNTL <- CLIP_DIST_ENA_0 = 0
                             CLIP_DIST_ENA_1 = 0
                             CLIP_DIST_ENA_2 = 0
                             CLIP_DIST_ENA_3 = 0
                             CLIP_DIST_ENA_4 = 0
                             CLIP_DIST_ENA_5 = 0
                             CLIP_DIST_ENA_6 = 0
                             CLIP_DIST_ENA_7 = 0
                             CULL_DIST_ENA_0 = 0
                             CULL_DIST_ENA_1 = 0
                             CULL_DIST_ENA_2 = 0
                             CULL_DIST_ENA_3 = 0
                             CULL_DIST_ENA_4 = 0
                             CULL_DIST_ENA_5 = 0
                             CULL_DIST_ENA_6 = 0
                             CULL_DIST_ENA_7 = 0
                             USE_VTX_POINT_SIZE = 0
                             USE_VTX_EDGE_FLAG = 0
                             USE_VTX_RENDER_TARGET_INDX = 0
                             USE_VTX_VIEWPORT_INDX = 0
                             USE_VTX_KILL_FLAG = 0
                             VS_OUT_MISC_VEC_ENA = 0
                             VS_OUT_CCDIST0_VEC_ENA = 0
                             VS_OUT_CCDIST1_VEC_ENA = 0
                             VS_OUT_MISC_SIDE_BUS_ENA = 1
                             USE_VTX_GS_CUT_FLAG = 0
                             USE_VTX_LINE_WIDTH = 0
SET_CONTEXT_REG:
        PA_CL_CLIP_CNTL <- UCP_ENA_0 = 0
                           UCP_ENA_1 = 0
                           UCP_ENA_2 = 0
                           UCP_ENA_3 = 0
                           UCP_ENA_4 = 0
                           UCP_ENA_5 = 0
                           PS_UCP_Y_SCALE_NEG = 0
                           PS_UCP_MODE = 3
                           CLIP_DISABLE = 0
                           UCP_CULL_ONLY_ENA = 0
                           BOUNDARY_EDGE_FLAG_ENA = 0
                           DX_CLIP_SPACE_DEF = 0
                           DIS_CLIP_ERR_DETECT = 0
                           VTX_KILL_OR = 0
                           DX_RASTERIZATION_KILL = 0
                           DX_LINEAR_ATTR_CLIP_ENA = 1
                           VTE_VPORT_PROVOKE_DISABLE = 0
                           ZCLIP_NEAR_DISABLE = 0
                           ZCLIP_FAR_DISABLE = 0
SET_SH_REG:
        SPI_SHADER_USER_DATA_VS_0 <- 0x019da300
        SPI_SHADER_USER_DATA_VS_1 <- 0
SET_SH_REG:
        SPI_SHADER_USER_DATA_VS_8 <- 0x019da400
        SPI_SHADER_USER_DATA_VS_9 <- 0
SET_CONTEXT_REG:
        DB_ALPHA_TO_MASK <- ALPHA_TO_MASK_ENABLE = 0
                            ALPHA_TO_MASK_OFFSET0 = 2
                            ALPHA_TO_MASK_OFFSET1 = 2
                            ALPHA_TO_MASK_OFFSET2 = 2
                            ALPHA_TO_MASK_OFFSET3 = 2
                            OFFSET_ROUND = 0
SET_CONTEXT_REG:
        CB_BLEND0_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO
                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
                             COLOR_DESTBLEND = BLEND_ZERO
                             ALPHA_SRCBLEND = BLEND_ZERO
                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
                             ALPHA_DESTBLEND = BLEND_ZERO
                             SEPARATE_ALPHA_BLEND = 0
                             ENABLE = 0
                             DISABLE_ROP3 = 0
        CB_BLEND1_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO
                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
                             COLOR_DESTBLEND = BLEND_ZERO
                             ALPHA_SRCBLEND = BLEND_ZERO
                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
                             ALPHA_DESTBLEND = BLEND_ZERO
                             SEPARATE_ALPHA_BLEND = 0
                             ENABLE = 0
                             DISABLE_ROP3 = 0
        CB_BLEND2_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO
                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
                             COLOR_DESTBLEND = BLEND_ZERO
                             ALPHA_SRCBLEND = BLEND_ZERO
                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
                             ALPHA_DESTBLEND = BLEND_ZERO
                             SEPARATE_ALPHA_BLEND = 0
                             ENABLE = 0
                             DISABLE_ROP3 = 0
        CB_BLEND3_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO
                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
                             COLOR_DESTBLEND = BLEND_ZERO
                             ALPHA_SRCBLEND = BLEND_ZERO
                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
                             ALPHA_DESTBLEND = BLEND_ZERO
                             SEPARATE_ALPHA_BLEND = 0
                             ENABLE = 0
                             DISABLE_ROP3 = 0
        CB_BLEND4_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO
                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
                             COLOR_DESTBLEND = BLEND_ZERO
                             ALPHA_SRCBLEND = BLEND_ZERO
                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
                             ALPHA_DESTBLEND = BLEND_ZERO
                             SEPARATE_ALPHA_BLEND = 0
                             ENABLE = 0
                             DISABLE_ROP3 = 0
        CB_BLEND5_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO
                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
                             COLOR_DESTBLEND = BLEND_ZERO
                             ALPHA_SRCBLEND = BLEND_ZERO
                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
                             ALPHA_DESTBLEND = BLEND_ZERO
                             SEPARATE_ALPHA_BLEND = 0
                             ENABLE = 0
                             DISABLE_ROP3 = 0
        CB_BLEND6_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO
                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
                             COLOR_DESTBLEND = BLEND_ZERO
                             ALPHA_SRCBLEND = BLEND_ZERO
                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
                             ALPHA_DESTBLEND = BLEND_ZERO
                             SEPARATE_ALPHA_BLEND = 0
                             ENABLE = 0
                             DISABLE_ROP3 = 0
        CB_BLEND7_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO
                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
                             COLOR_DESTBLEND = BLEND_ZERO
                             ALPHA_SRCBLEND = BLEND_ZERO
                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
                             ALPHA_DESTBLEND = BLEND_ZERO
                             SEPARATE_ALPHA_BLEND = 0
                             ENABLE = 0
                             DISABLE_ROP3 = 0
SET_CONTEXT_REG:
        CB_COLOR_CONTROL <- DEGAMMA_ENABLE = 0
                            MODE = CB_ELIMINATE_FAST_CLEAR
                            ROP3 = X_0XCC
SET_CONTEXT_REG:
        PA_SC_AA_MASK_X0Y0_X1Y0 <- AA_MASK_X0Y0 = 0x0000ffff
                                   AA_MASK_X1Y0 = 0x0000ffff
        PA_SC_AA_MASK_X0Y1_X1Y1 <- AA_MASK_X0Y1 = 0x0000ffff
                                   AA_MASK_X1Y1 = 0x0000ffff
SET_CONTEXT_REG:
        PA_CL_VPORT_XSCALE <- 1.0f
        PA_CL_VPORT_XOFFSET <- 0
        PA_CL_VPORT_YSCALE <- 1.0f
        PA_CL_VPORT_YOFFSET <- 0
        PA_CL_VPORT_ZSCALE <- 1.0f
        PA_CL_VPORT_ZOFFSET <- 0
SET_CONTEXT_REG:
        SPI_INTERP_CONTROL_0 <- FLAT_SHADE_ENA = 1
                                PNT_SPRITE_ENA = 1
                                PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
                                PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
                                PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
                                PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
                                PNT_SPRITE_TOP_1 = 0
SET_CONTEXT_REG:
        PA_SU_POINT_SIZE <- HEIGHT = 0
                            WIDTH = 0
        PA_SU_POINT_MINMAX <- MIN_SIZE = 0
                              MAX_SIZE = 0
        PA_SU_LINE_CNTL <- WIDTH = 0
SET_CONTEXT_REG:
        PA_SC_MODE_CNTL_0 <- MSAA_ENABLE = 0
                             VPORT_SCISSOR_ENABLE = 0
                             LINE_STIPPLE_ENABLE = 0
                             SEND_UNLIT_STILES_TO_PKR = 0
SET_CONTEXT_REG:
        PA_SU_VTX_CNTL <- PIX_CENTER = 1
                          ROUND_MODE = X_TRUNCATE
                          QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
SET_CONTEXT_REG:
        PA_SU_POLY_OFFSET_CLAMP <- 0
SET_CONTEXT_REG:
        PA_SU_SC_MODE_CNTL <- CULL_FRONT = 0
                              CULL_BACK = 0
                              FACE = 1
                              POLY_MODE = X_DISABLE_POLY_MODE
                              POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
                              POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
                              POLY_OFFSET_FRONT_ENABLE = 0
                              POLY_OFFSET_BACK_ENABLE = 0
                              POLY_OFFSET_PARA_ENABLE = 0
                              VTX_WINDOW_OFFSET_ENABLE = 0
                              PROVOKING_VTX_LAST = 1
                              PERSP_CORR_DIS = 0
                              MULTI_PRIM_IB_ENA = 0
SET_CONTEXT_REG:
        DB_DEPTH_CONTROL <- STENCIL_ENABLE = 0
                            Z_ENABLE = 0
                            Z_WRITE_ENABLE = 0
                            DEPTH_BOUNDS_ENABLE = 0
                            ZFUNC = FRAG_NEVER
                            BACKFACE_ENABLE = 0
                            STENCILFUNC = REF_NEVER
                            STENCILFUNC_BF = REF_NEVER
                            ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0
                            DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0
SET_CONTEXT_REG:
        DB_STENCIL_CONTROL <- STENCILFAIL = STENCIL_KEEP
                              STENCILZPASS = STENCIL_KEEP
                              STENCILZFAIL = STENCIL_KEEP
                              STENCILFAIL_BF = STENCIL_KEEP
                              STENCILZPASS_BF = STENCIL_KEEP
                              STENCILZFAIL_BF = STENCIL_KEEP
SET_CONTEXT_REG:
        CB_TARGET_MASK <- TARGET0_ENABLE = 15
                          TARGET1_ENABLE = 0
                          TARGET2_ENABLE = 0
                          TARGET3_ENABLE = 0
                          TARGET4_ENABLE = 0
                          TARGET5_ENABLE = 0
                          TARGET6_ENABLE = 0
                          TARGET7_ENABLE = 0
SET_CONTEXT_REG:
        DB_STENCILREFMASK <- STENCILTESTVAL = 0
                             STENCILMASK = 0
                             STENCILWRITEMASK = 0
                             STENCILOPVAL = 1
        DB_STENCILREFMASK_BF <- STENCILTESTVAL_BF = 0
                                STENCILMASK_BF = 0
                                STENCILWRITEMASK_BF = 0
                                STENCILOPVAL_BF = 1
SET_CONTEXT_REG:
        VGT_GS_MODE <- MODE = GS_OFF
                       CUT_MODE = GS_CUT_1024
                       GS_C_PACK_EN = 0
                       ES_PASSTHRU = 0
                       COMPUTE_MODE = 0
                       FAST_COMPUTE_MODE = 0
                       ELEMENT_INFO_EN = 0
                       PARTIAL_THD_AT_EOI = 0
                       SUPPRESS_CUTS = 0
                       ES_WRITE_OPTIMIZE = 0
                       GS_WRITE_OPTIMIZE = 0
                       ONCHIP = X_0_OFFCHIP_GS
SET_CONTEXT_REG:
        VGT_PRIMITIVEID_EN <- PRIMITIVEID_EN = 0
                              DISABLE_RESET_ON_EOI = 0
SET_CONTEXT_REG:
        SPI_VS_OUT_CONFIG <- VS_EXPORT_COUNT = 0
                             VS_HALF_PACK = 0
                             VS_EXPORTS_FOG = 0
                             VS_OUT_FOG_VEC_ADDR = 0
SET_CONTEXT_REG:
        SPI_SHADER_POS_FORMAT <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
SET_SH_REG:
        SPI_SHADER_PGM_LO_VS <- 0x0001ae00
        SPI_SHADER_PGM_HI_VS <- MEM_BASE = 0
        SPI_SHADER_PGM_RSRC1_VS <- VGPRS = 2
                                   SGPRS = 9
                                   PRIORITY = 0
                                   FLOAT_MODE = 0
                                   PRIV = 0
                                   DX10_CLAMP = 1
                                   DEBUG_MODE = 0
                                   IEEE_MODE = 0
                                   VGPR_COMP_CNT = 0
                                   CU_GROUP_ENABLE = 0
                                   CACHE_CTL = 0
                                   CDBG_USER = 0
        SPI_SHADER_PGM_RSRC2_VS <- SCRATCH_EN = 0
                                   USER_SGPR = 12
                                   TRAP_PRESENT = 0
                                   OC_LDS_EN = 0
                                   SO_BASE0_EN = 0
                                   SO_BASE1_EN = 0
                                   SO_BASE2_EN = 0
                                   SO_BASE3_EN = 0
                                   SO_EN = 0
                                   EXCP_EN = 0
                                   EXCP_EN_CIK = 0
                                   DISPATCH_DRAW_EN = 0
SET_CONTEXT_REG:
        PA_CL_VTE_CNTL <- VPORT_X_SCALE_ENA = 1
                          VPORT_X_OFFSET_ENA = 1
                          VPORT_Y_SCALE_ENA = 1
                          VPORT_Y_OFFSET_ENA = 1
                          VPORT_Z_SCALE_ENA = 1
                          VPORT_Z_OFFSET_ENA = 1
                          VTX_XY_FMT = 0
                          VTX_Z_FMT = 0
                          VTX_W0_FMT = 1
SET_CONTEXT_REG:
        SPI_BARYC_CNTL <- PERSP_CENTER_CNTL = 0
                          PERSP_CENTROID_CNTL = 0
                          LINEAR_CENTER_CNTL = 0
                          LINEAR_CENTROID_CNTL = 0
                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
                          POS_FLOAT_ULC = 0
                          FRONT_FACE_ALL_BITS = 0
SET_CONTEXT_REG:
        SPI_PS_INPUT_ENA <- PERSP_SAMPLE_ENA = 1
                            PERSP_CENTER_ENA = 0
                            PERSP_CENTROID_ENA = 0
                            PERSP_PULL_MODEL_ENA = 0
                            LINEAR_SAMPLE_ENA = 0
                            LINEAR_CENTER_ENA = 0
                            LINEAR_CENTROID_ENA = 0
                            LINE_STIPPLE_TEX_ENA = 0
                            POS_X_FLOAT_ENA = 0
                            POS_Y_FLOAT_ENA = 0
                            POS_Z_FLOAT_ENA = 0
                            POS_W_FLOAT_ENA = 0
                            FRONT_FACE_ENA = 0
                            ANCILLARY_ENA = 0
                            SAMPLE_COVERAGE_ENA = 0
                            POS_FIXED_PT_ENA = 0
        SPI_PS_INPUT_ADDR <- PERSP_SAMPLE_ENA = 1
                             PERSP_CENTER_ENA = 0
                             PERSP_CENTROID_ENA = 0
                             PERSP_PULL_MODEL_ENA = 0
                             LINEAR_SAMPLE_ENA = 0
                             LINEAR_CENTER_ENA = 0
                             LINEAR_CENTROID_ENA = 0
                             LINE_STIPPLE_TEX_ENA = 0
                             POS_X_FLOAT_ENA = 0
                             POS_Y_FLOAT_ENA = 0
                             POS_Z_FLOAT_ENA = 0
                             POS_W_FLOAT_ENA = 0
                             FRONT_FACE_ENA = 0
                             ANCILLARY_ENA = 0
                             SAMPLE_COVERAGE_ENA = 0
                             POS_FIXED_PT_ENA = 0
SET_CONTEXT_REG:
        SPI_PS_IN_CONTROL <- NUM_INTERP = 1
                             PARAM_GEN = 0
                             FOG_ADDR = 0
                             BC_OPTIMIZE_DISABLE = 1
                             PASS_FOG_THROUGH_PS = 0
SET_CONTEXT_REG:
        SPI_SHADER_Z_FORMAT <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
        SPI_SHADER_COL_FORMAT <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
SET_CONTEXT_REG:
        CB_SHADER_MASK <- OUTPUT0_ENABLE = 15
                          OUTPUT1_ENABLE = 0
                          OUTPUT2_ENABLE = 0
                          OUTPUT3_ENABLE = 0
                          OUTPUT4_ENABLE = 0
                          OUTPUT5_ENABLE = 0
                          OUTPUT6_ENABLE = 0
                          OUTPUT7_ENABLE = 0
SET_SH_REG:
        SPI_SHADER_PGM_LO_PS <- 0x0001b300
        SPI_SHADER_PGM_HI_PS <- MEM_BASE = 0
        SPI_SHADER_PGM_RSRC1_PS <- VGPRS = 0
                                   SGPRS = 9
                                   PRIORITY = 0
                                   FLOAT_MODE = 0
                                   PRIV = 0
                                   DX10_CLAMP = 1
                                   DEBUG_MODE = 0
                                   IEEE_MODE = 0
                                   CU_GROUP_DISABLE = 0
                                   CACHE_CTL = 0
                                   CDBG_USER = 0
        SPI_SHADER_PGM_RSRC2_PS <- SCRATCH_EN = 0
                                   USER_SGPR = 9
                                   TRAP_PRESENT = 0
                                   WAVE_CNT_EN = 0
                                   EXTRA_LDS_SIZE = 0
                                   EXCP_EN = 0
                                   EXCP_EN_CIK = 0
SET_CONTEXT_REG:
        SPI_PS_INPUT_CNTL_0 <- OFFSET = 0
                               DEFAULT_VAL = X_0_0F
                               FLAT_SHADE = 1
                               CYL_WRAP = 0
                               PT_SPRITE_TEX = 0
                               DUP = 0
                               FP16_INTERP_MODE = 0
                               USE_DEFAULT_ATTR1 = 0
                               DEFAULT_VAL_ATTR1 = 0
                               PT_SPRITE_TEX_ATTR1 = 0
                               ATTR0_VALID = 0
                               ATTR1_VALID = 0
DRAW_PREAMBLE:
        VGT_PRIMITIVE_TYPE <- PRIM_TYPE = DI_PT_RECTLIST
        IA_MULTI_VGT_PARAM <- PRIMGROUP_SIZE = 127
                              PARTIAL_VS_WAVE_ON = 0
                              SWITCH_ON_EOP = 0
                              PARTIAL_ES_WAVE_ON = 0
                              SWITCH_ON_EOI = 0
                              WD_SWITCH_ON_EOP = 0
                              MAX_PRIMGRP_IN_WAVE = 2
        VGT_LS_HS_CONFIG <- NUM_PATCHES = 0
                            HS_NUM_INPUT_CP = 0
                            HS_NUM_OUTPUT_CP = 0
NUM_INSTANCES:
        VGT_NUM_INSTANCES <- 1
DRAW_INDEX_AUTO:
        VGT_NUM_INDICES <- 3
        VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX
                              MAJOR_MODE = DI_MAJOR_MODE_0
                              NOT_EOP = 0
                              USE_OPAQUE = 0
EVENT_WRITE:
        VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_CB_META
        EVENT_INDEX <- 0
        INV_L2 <- 0
EVENT_WRITE:
        VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_DB_META
        EVENT_INDEX <- 0
        INV_L2 <- 0
EVENT_WRITE:
        VGT_EVENT_INITIATOR <- EVENT_TYPE = PS_PARTIAL_FLUSH
        EVENT_INDEX <- 4
        INV_L2 <- 0
ACQUIRE_MEM:
        CP_COHER_CNTL <- DEST_BASE_0_ENA = 0
                         DEST_BASE_1_ENA = 0
                         TC_SD_ACTION_ENA = 0
                         TC_NC_ACTION_ENA = 0
                         CB0_DEST_BASE_ENA = 1
                         CB1_DEST_BASE_ENA = 1
                         CB2_DEST_BASE_ENA = 1
                         CB3_DEST_BASE_ENA = 1
                         CB4_DEST_BASE_ENA = 1
                         CB5_DEST_BASE_ENA = 1
                         CB6_DEST_BASE_ENA = 1
                         CB7_DEST_BASE_ENA = 1
                         DB_DEST_BASE_ENA = 1
                         TCL1_VOL_ACTION_ENA = 0
                         TC_VOL_ACTION_ENA = 0
                         TC_WB_ACTION_ENA = 1
                         DEST_BASE_2_ENA = 0
                         DEST_BASE_3_ENA = 0
                         TCL1_ACTION_ENA = 1
                         TC_ACTION_ENA = 1
                         CB_ACTION_ENA = 1
                         DB_ACTION_ENA = 1
                         SH_KCACHE_ACTION_ENA = 0
                         SH_KCACHE_VOL_ACTION_ENA = 0
                         SH_ICACHE_ACTION_ENA = 0
                         SH_KCACHE_WB_ACTION_ENA = 0
                         SH_SD_ACTION_ENA = 0
        CP_COHER_SIZE <- 0xffffffff
        CP_COHER_SIZE_HI <- COHER_SIZE_HI_256B = 255
        CP_COHER_BASE <- 0
        CP_COHER_BASE_HI <- COHER_BASE_HI_256B = 0
        POLL_INTERVAL <- 10
------------------- IB end -------------------
Done.