Result: crash
Detail | Value |
---|---|
Returncode | -6 |
Time | 0:00:13.372362 |
Stdout | |
Stderr |
Overran sorted position: t129: i32 = srl t397, Constant:i32<8> t397: i32 = and t263, Constant:i32<65280> t263: i32 = or t262, t258 t262: i32 = and t288, Constant:i32<-256> t288: i32,ch = load<(load 4 from %stack.5, addrspace 5)> t291, t321, undef:i32 t321: i32 = DWORDADDR Constant:i32<10> t354: i32 = Constant<10> t49: i32 = undef t378: i32 = Constant<-256> t258: i32 = and t108, Constant:i32<255> t108: i32 = extract_vector_elt t39, Constant:i32<0> t39: v2i32,ch = CopyFromReg t0, Register:v2i32 %28 t38: v2i32 = Register %28 t87: i32 = Constant<0> t144: i32 = Constant<255> t396: i32 = Constant<65280> t128: i32 = Constant<8> Checking if this is due to cycles Detected cycle in SelectionDAG Offending node: t288: i32,ch = load<(load 4 from %stack.5, addrspace 5)> t291, t321, undef:i32 t321: i32 = DWORDADDR Constant:i32<10> t354: i32 = Constant<10> t49: i32 = undef |
Environment |
PIGLIT_SOURCE_DIR="/home/vesely/piglit" PIGLIT_PLATFORM="mixed_glx_egl" |
Command | /home/vesely/piglit/bin/cl-program-tester /home/vesely/piglit/generated_tests/cl/builtin/misc/builtin-shuffle-char-uchar.cl |
dmesg |