Result: crash
Detail | Value |
---|---|
Returncode | -6 |
Time | 0:00:07.634109 |
Stdout | |
Stderr |
Overran sorted position: t44: i32,ch = load<(load 2 from %ir.8, !tbaa !8, addrspace 1), zext from i16> t237, t21, undef:i32 t21: i32 = add nuw t82, Constant:i32<2> t82: i32 = CONST_ADDRESS Constant:i32<8228> t81: i32 = Constant<8228> t17: i32 = Constant<2> t1: i32 = undef Checking if this is due to cycles Detected cycle in SelectionDAG Offending node: t237: ch = store<(store 8 into %ir.storetmp, !tbaa !8, addrspace 1)> t66, t243, t236, undef:i32 t243: v2i32 = BUILD_VECTOR t326, t298 t326: i32,ch = load<(load 4 from %stack.1, align 8, addrspace 5)> t305, t325, undef:i32 t325: i32 = DWORDADDR Constant:i32<4> t14: i32 = Constant<4> t1: i32 = undef t298: i32 = or t297, t293 t297: i32 = and t306, Constant:i32<-65536> t306: i32,ch = load<(load 4 from %stack.1 + 4, addrspace 5)> t316, t304, undef:i32 t304: i32 = DWORDADDR Constant:i32<5> t374: i32 = Constant<5> t1: i32 = undef t376: i32 = Constant<-65536> t293: i32 = and t85, Constant:i32<65535> t85: i32,ch = load<(load 2 from %ir.arrayidx3.i, !tbaa !13, addrspace 1), anyext from i16> t0, t15, undef:i32 t15: i32 = add nuw t82, Constant:i32<4> t82: i32 = CONST_ADDRESS Constant:i32<8228> t81: i32 = Constant<8228> t14: i32 = Constant<4> t1: i32 = undef t176: i32 = Constant<65535> t236: i32 = DWORDADDR t235 t235: i32 = srl t69, Constant:i32<2> t69: i32 = CONST_ADDRESS Constant:i32<8232> t68: i32 = Constant<8232> t17: i32 = Constant<2> t1: i32 = undef |
Environment |
PIGLIT_SOURCE_DIR="/home/vesely/piglit" PIGLIT_PLATFORM="mixed_glx_egl" |
Command | /home/vesely/piglit/bin/cl-program-tester /home/vesely/piglit/generated_tests/cl/vload/vload-short-global.cl |
dmesg |