Result: crash
| Detail | Value |
|---|---|
| Returncode | -6 |
| Time | 0:00:12.958915 |
| Stdout | |
| Stderr |
Overran sorted position:
t128: i32 = srl t396, Constant:i32<8>
t396: i32 = and t262, Constant:i32<65280>
t262: i32 = or t261, t257
t261: i32 = and t287, Constant:i32<-256>
t287: i32,ch = load<(load 4 from `i32 addrspace(5)* undef`, addrspace 5)> t290, t320, undef:i32
t320: i32 = DWORDADDR Constant:i32<10>
t353: i32 = Constant<10>
t49: i32 = undef
t377: i32 = Constant<-256>
t257: i32 = and t107, Constant:i32<255>
t107: i32 = extract_vector_elt t39, Constant:i32<0>
t39: v2i32,ch = CopyFromReg t0, Register:v2i32 %32
t38: v2i32 = Register %32
t86: i32 = Constant<0>
t143: i32 = Constant<255>
t395: i32 = Constant<65280>
t127: i32 = Constant<8>
Checking if this is due to cycles
Detected cycle in SelectionDAG
Offending node:
t287: i32,ch = load<(load 4 from `i32 addrspace(5)* undef`, addrspace 5)> t290, t320, undef:i32
t320: i32 = DWORDADDR Constant:i32<10>
t353: i32 = Constant<10>
t49: i32 = undef
|
| Environment |
PIGLIT_SOURCE_DIR="/home/vesely/piglit" PIGLIT_PLATFORM="mixed_glx_egl" |
| Command | /home/vesely/piglit/bin/cl-program-tester /home/vesely/piglit/generated_tests/cl/builtin/misc/builtin-shuffle-uchar-uchar.cl |
| dmesg |