Reading fs-ssbo-with.rd... test: cmd: get_display:438: >>> eglInitialize(display, &egl_major, &egl_minor) cmd: eglInitialize(display, &egl_major, &egl_minor) gpu_id: 420 cmd: get_display:438: <<< eglInitialize(display, &egl_major, &egl_minor): succeeded cmd: get_display:440: Using display 0x1 with EGL version 1.4 cmd: get_display:443: EGL Version "1.4 Android META-EGL" cmd: get_display:444: EGL Vendor "Android" cmd: get_display:445: EGL Extensions "EGL_KHR_get_all_proc_addresses EGL_ANDROID_presentation_time EGL_KHR_image EGL_KHR_image_base EGL_KHR_lock_surface EGL_KHR_gl_texture_2D_image EGL_KHR_gl_texture_cubemap_image EGL_KHR_gl_renderbuffer_image EGL_KHR_reusable_sync EGL_KHR_fence_sync EGL_KHR_create_context EGL_EXT_create_context_robustness EGL_ANDROID_image_native_buffer EGL_KHR_wait_sync EGL_ANDROID_recordable " cmd: test_quad_flat:94: >>> eglChooseConfig(display, config_attribute_list, &config, 1, &num_config) cmd: eglChooseConfig(display, config_attribute_list, &config, 1, &num_config) cmd: test_quad_flat:94: <<< eglChooseConfig(display, config_attribute_list, &config, 1, &num_config): succeeded cmd: test_quad_flat:95: num_config: 1 cmd: test_quad_flat:98: >>> context = eglCreateContext(display, config, EGL_NO_CONTEXT, context_attribute_list) cmd: context = eglCreateContext(display, config, EGL_NO_CONTEXT, context_attribute_list) cmd: test_quad_flat:98: <<< context = eglCreateContext(display, config, EGL_NO_CONTEXT, context_attribute_list): succeeded cmd: make_window:460: >>> surface = eglCreatePbufferSurface(display, config, pbuffer_attribute_list) cmd: surface = eglCreatePbufferSurface(display, config, pbuffer_attribute_list) cmd: make_window:460: <<< surface = eglCreatePbufferSurface(display, config, pbuffer_attribute_list): succeeded cmd: test_quad_flat:102: >>> eglQuerySurface(display, surface, EGL_WIDTH, &width) cmd: eglQuerySurface(display, surface, EGL_WIDTH, &width) cmd: test_quad_flat:102: <<< eglQuerySurface(display, surface, EGL_WIDTH, &width): succeeded cmd: test_quad_flat:103: >>> eglQuerySurface(display, surface, EGL_HEIGHT, &height) cmd: eglQuerySurface(display, surface, EGL_HEIGHT, &height) cmd: test_quad_flat:103: <<< eglQuerySurface(display, surface, EGL_HEIGHT, &height): succeeded cmd: test_quad_flat:105: Buffer: 400x240 cmd: test_quad_flat:108: >>> eglMakeCurrent(display, surface, surface, context) cmd: eglMakeCurrent(display, surface, surface, context) cmd: test_quad_flat:108: <<< eglMakeCurrent(display, surface, surface, context): succeeded cmd: get_program:613: vertex shader: #version 310 es out vec4 aPosition; void main() { gl_Position = aPosition; } cmd: get_program:614: fragment shader: #version 310 es precision highp float; uniform vec4 uColor; out vec4 color; layout(binding = 0) buffer buffer_In { uvec3 In[]; }; layout(binding = 1) buffer buffer_Out { uvec3 Out[]; }; void main() { color = uColor; Out[0] = In[1]; } vertex shader: #version 310 es out vec4 aPosition; void main() { gl_Position = aPosition; } fragment shader: #version 310 es precision highp float; uniform vec4 uColor; out vec4 color; layout(binding = 0) buffer buffer_In { uvec3 In[]; }; layout(binding = 1) buffer buffer_Out { uvec3 Out[]; }; void main() { color = uColor; Out[0] = In[1]; } cmd: get_shader:581: vertex shader: #version 310 es out vec4 aPosition; void main() { gl_Position = aPosition; } cmd: get_shader:583: >>> shader = glCreateShader(stage) cmd: shader = glCreateShader(stage) cmd: get_shader:583: <<< shader = glCreateShader(stage): succeeded cmd: get_shader:585: >>> glShaderSource(shader, 1, &source, NULL) cmd: glShaderSource(shader, 1, &source, NULL) cmd: get_shader:585: <<< glShaderSource(shader, 1, &source, NULL): succeeded cmd: get_shader:586: >>> glCompileShader(shader) cmd: glCompileShader(shader) cmd: get_shader:586: <<< glCompileShader(shader): succeeded cmd: get_shader:588: >>> glGetShaderiv(shader, GL_COMPILE_STATUS, &ret) cmd: glGetShaderiv(shader, GL_COMPILE_STATUS, &ret) cmd: get_shader:588: <<< glGetShaderiv(shader, GL_COMPILE_STATUS, &ret): succeeded cmd: get_shader:603: vertex shader compilation succeeded! cmd: get_shader:581: fragment shader: #version 310 es precision highp float; uniform vec4 uColor; out vec4 color; layout(binding = 0) buffer buffer_In { uvec3 In[]; }; layout(binding = 1) buffer buffer_Out { uvec3 Out[]; }; void main() { color = uColor; Out[0] = In[1]; } cmd: get_shader:583: >>> shader = glCreateShader(stage) cmd: shader = glCreateShader(stage) cmd: get_shader:583: <<< shader = glCreateShader(stage): succeeded cmd: get_shader:585: >>> glShaderSource(shader, 1, &source, NULL) cmd: glShaderSource(shader, 1, &source, NULL) cmd: get_shader:585: <<< glShaderSource(shader, 1, &source, NULL): succeeded cmd: get_shader:586: >>> glCompileShader(shader) cmd: glCompileShader(shader) cmd: get_shader:586: <<< glCompileShader(shader): succeeded cmd: get_shader:588: >>> glGetShaderiv(shader, GL_COMPILE_STATUS, &ret) cmd: glGetShaderiv(shader, GL_COMPILE_STATUS, &ret) cmd: get_shader:588: <<< glGetShaderiv(shader, GL_COMPILE_STATUS, &ret): succeeded cmd: get_shader:603: fragment shader compilation succeeded! cmd: get_program:624: >>> program = glCreateProgram() cmd: program = glCreateProgram() cmd: get_program:624: <<< program = glCreateProgram(): succeeded cmd: get_program:626: >>> glAttachShader(program, vertex_shader) cmd: glAttachShader(program, vertex_shader) cmd: get_program:626: <<< glAttachShader(program, vertex_shader): succeeded cmd: get_program:627: >>> glAttachShader(program, fragment_shader) cmd: glAttachShader(program, fragment_shader) cmd: get_program:627: <<< glAttachShader(program, fragment_shader): succeeded cmd: test_quad_flat:112: >>> glBindAttribLocation(program, 0, "aPosition") cmd: glBindAttribLocation(program, 0, "aPosition") cmd: test_quad_flat:112: <<< glBindAttribLocation(program, 0, "aPosition"): succeeded cmd: link_program:719: >>> glLinkProgram(program) cmd: glLinkProgram(program) cmd: link_program:719: <<< glLinkProgram(program): succeeded cmd: link_program:721: >>> glGetProgramiv(program, GL_LINK_STATUS, &ret) cmd: glGetProgramiv(program, GL_LINK_STATUS, &ret) cmd: link_program:721: <<< glGetProgramiv(program, GL_LINK_STATUS, &ret): succeeded cmd: link_program:736: program linking succeeded! cmd: link_program:738: >>> glUseProgram(program) cmd: glUseProgram(program) cmd: link_program:738: <<< glUseProgram(program): succeeded cmd: link_program:744: >>> glGetProgramiv(program, GL_PROGRAM_BINARY_LENGTH_OES, &len) cmd: glGetProgramiv(program, GL_PROGRAM_BINARY_LENGTH_OES, &len) cmd: link_program:744: <<< glGetProgramiv(program, GL_PROGRAM_BINARY_LENGTH_OES, &len): succeeded cmd: link_program:746: >>> glGetProgramBinaryOES(program, len, &ret, &binary_format, binary) cmd: glGetProgramBinaryOES(program, len, &ret, &binary_format, binary) cmd: link_program:746: <<< glGetProgramBinaryOES(program, len, &ret, &binary_format, binary): succeeded cmd: link_program:747: program dump: len=8620, actual len=8620 cmd: test_quad_flat:125: >>> glViewport(0, 0, width, height) cmd: glViewport(0, 0, width, height) cmd: test_quad_flat:125: <<< glViewport(0, 0, width, height): succeeded cmd: test_quad_flat:133: >>> glVertexAttribPointer(0, 3, GL_FLOAT, GL_FALSE, 0, vertices) cmd: glVertexAttribPointer(0, 3, GL_FLOAT, GL_FALSE, 0, vertices) cmd: test_quad_flat:133: <<< glVertexAttribPointer(0, 3, GL_FLOAT, GL_FALSE, 0, vertices): succeeded cmd: test_quad_flat:134: >>> glEnableVertexAttribArray(0) cmd: glEnableVertexAttribArray(0) cmd: test_quad_flat:134: <<< glEnableVertexAttribArray(0): succeeded cmd: test_quad_flat:136: >>> glDepthRangef(0.2, 0.7) cmd: glDepthRangef(0.2, 0.7) cmd: test_quad_flat:136: <<< glDepthRangef(0.2, 0.7): succeeded cmd: test_quad_flat:139: >>> uniform_location = glGetUniformLocation(program, "uColor") cmd: uniform_location = glGetUniformLocation(program, "uColor") cmd: test_quad_flat:139: <<< uniform_location = glGetUniformLocation(program, "uColor"): succeeded cmd: test_quad_flat:141: >>> glUniform4fv(uniform_location, 1, quad_color) cmd: glUniform4fv(uniform_location, 1, quad_color) cmd: test_quad_flat:141: <<< glUniform4fv(uniform_location, 1, quad_color): succeeded cmd: test_quad_flat:142: >>> glDrawArrays(GL_TRIANGLE_STRIP, 0, 4) cmd: glDrawArrays(GL_TRIANGLE_STRIP, 0, 4) cmd: test_quad_flat:142: <<< glDrawArrays(GL_TRIANGLE_STRIP, 0, 4): succeeded cmd: test_quad_flat:144: >>> eglSwapBuffers(display, surface) cmd: eglSwapBuffers(display, surface) ############################################################ cmdstream: 83 dwords t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 0000: c0002600 00000000 t0 write UCHE_INVALIDATE0 (0e8a) UCHE_INVALIDATE0: 0 UCHE_INVALIDATE1: 0x12 0000: 00010e8a 00000000 00000012 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 0000: c0002600 00000000 t0 write RB_MODE_CONTROL (20a0) RB_MODE_CONTROL: { WIDTH = 0 | HEIGHT = 0 | 0xc00000 } 0000: 000020a0 00c00000 t0 write RB_FRAME_BUFFER_DIMENSION (0ce0) RB_FRAME_BUFFER_DIMENSION: { WIDTH = 400 | HEIGHT = 240 } 0000: 00000ce0 00f00190 t0 write 0xce1 (0ce1) 0xce1: 00000001 0000: 00000ce1 00000001 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 0000: c0002600 00000000 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0 0000: 00000cc6 00000000 t0 write GRAS_SC_WINDOW_SCISSOR_BR (209c) GRAS_SC_WINDOW_SCISSOR_BR: { X = 399 | Y = 239 } GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 0000: 0001209c 00ef018f 00000000 t0 write RB_BIN_OFFSET (210d) RB_BIN_OFFSET: { X = 0 | Y = 0 } 0000: 0000210d 00000000 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 0000: c0002600 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x1e 0000: 00000ec3 0000001e t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x38 0000: 00000f03 00000038 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 0000: c0002600 00000000 t0 write HLSQ_MODE_CONTROL (0e05) HLSQ_MODE_CONTROL: 0x1 0000: 00000e05 00000001 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } 0000: 000023c0 080004f0 t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x7 0000: 000023db 00000007 t0 write PC_RESTART_INDEX (21c6) PC_RESTART_INDEX: 0xffffffff 0000: 000021c6 ffffffff t0 write UNKNOWN_21E6 (21e6) UNKNOWN_21E6: 0x1 0000: 000021e6 00000001 t0 write UNKNOWN_21C3 (21c3) UNKNOWN_21C3: 0x1d 0000: 000021c3 0000001d t0 write TPL1_TP_TEX_OFFSET (2380) TPL1_TP_TEX_OFFSET: 0x808 0000: 00002380 00000808 t0 write GRAS_SU_POINT_MINMAX (2070) GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 4092.000000 } GRAS_SU_POINT_SIZE: 0.500000 0000: 00012070 ffc00010 00000008 t0 write UNKNOWN_2152 (2152) UNKNOWN_2152: 0 UNKNOWN_2153: 0 0000: 00012152 00000000 00000000 t0 write UNKNOWN_2154 (2154) UNKNOWN_2154: 0 0000: 00002154 00000000 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 0000: c0002600 00000000 t0 write UNKNOWN_0CC5 (0cc5) UNKNOWN_0CC5: 0x6 0000: 00000cc5 00000006 t0 write 0xcc4 (0cc4) 0xcc4: 00000000 0000: 00000cc4 00000000 t0 write 0xd03 (0d03) 0xd03: c0200000 0000: 00000d03 c0200000 t0 write UNKNOWN_0EC2 (0ec2) UNKNOWN_0EC2: 0x40000 0000: 00000ec2 00040000 t0 write UNKNOWN_0E42 (0e42) UNKNOWN_0E42: 0 0000: 00000e42 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x1e 0000: 00000ec3 0000001e t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x38 0000: 00000f03 00000038 t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:c00b3000 ibsize:000001a5 t0 write TPL1_TP_TEX_COUNT (2381) TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } 0000: 00002381 00000000 t0 write TPL1_TP_FS_TEX_COUNT (23a0) TPL1_TP_FS_TEX_COUNT: 0 0000: 000023a0 00000000 t0 write SP_GS_OBJ_OFFSET_REG (235b) SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } 0000: 0000235b 7e020000 t0 write 0x2072 (2072) 0x2072: 00000000 0000: 00002072 00000000 t0 write UNKNOWN_2155 (2155) UNKNOWN_2155: 0 0000: 00002155 00000000 t0 write SP_HS_OBJ_OFFSET_REG (230d) SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } 0000: 0000230d 7e020000 t0 write SP_DS_OBJ_OFFSET_REG (2334) SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } 0000: 00002334 7e020000 t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x7 0000: 000023db 00000007 t0 write HLSQ_FS_CONTROL_REG (23c6) HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 3 | CONSTOBJECTOFFSET = 2 | SSBO_ENABLE | ENABLED | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 } 0000: 000023c6 017f8203 t0 write HLSQ_CONTROL_1_REG (23c1) HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x1028 } 0000: 000023c1 fcfc1128 t0 write HLSQ_CONTROL_2_REG (23c2) HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 0000: 000023c2 fff3f3f0 t0 write HLSQ_CONTROL_3_REG (23c3) HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r63.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } 0000: 000023c3 fcfcfcfc t0 write HLSQ_CONTROL_4_REG (23c4) HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } 0000: 000023c4 00fcfcfc t0 write HLSQ_VS_CONTROL_REG (23c5) HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 2 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 1 } 0000: 000023c5 01010002 t0 write HLSQ_HS_CONTROL_REG (23c7) HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 0000: 000023c7 007e0200 t0 write HLSQ_DS_CONTROL_REG (23c8) HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 0000: 000023c8 007e0200 t0 write HLSQ_GS_CONTROL_REG (23c9) HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 0000: 000023c9 007e0200 t0 write HLSQ_CS_CONTROL_REG (23ca) HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 48 | CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } 0000: 000023ca 00000030 t0 write SP_VS_OBJ_START (22e1) SP_VS_OBJ_START: 0xc01ac000 0000: 00000000 30445300 00000000 03000000 00000000 00000000 00000000 00000000 * 0000[30445300x_00000000x] (sy)(ss)(rpt3)mov.f32f32 r0.x, (0.000000) 0001[03000000x_00000000x] end Register Stats: - used (half): (cnt=0, max=0) - used (full): 0-3 (cnt=4, max=3) - input (half): (cnt=0, max=0) - input (full): (cnt=0, max=0) - const (half): (cnt=0, max=0) - const (full): (cnt=0, max=0) - output (half): (cnt=0, max=0) (estimated) - output (full): 0-3 (cnt=4, max=3) (estimated) 0000: 000022e1 c01ac000 t0 write SP_HS_OBJ_START (230e) SP_HS_OBJ_START: 0 0000: 0000230e 00000000 t0 write SP_DS_OBJ_START (2335) SP_DS_OBJ_START: 0 0000: 00002335 00000000 t0 write SP_GS_OBJ_START (235c) SP_GS_OBJ_START: 0 0000: 0000235c 00000000 t0 write GRAS_CNTL (2003) GRAS_CNTL: { 0 } 0000: 00002003 00000000 t0 write VPC_VARYING_INTERP[0].MODE (2142) VPC_VARYING_INTERP[0].MODE: 0 VPC_VARYING_INTERP[0x1].MODE: 0 VPC_VARYING_INTERP[0x2].MODE: 0 VPC_VARYING_INTERP[0x3].MODE: 0 VPC_VARYING_INTERP[0x4].MODE: 0 VPC_VARYING_INTERP[0x5].MODE: 0 VPC_VARYING_INTERP[0x6].MODE: 0 VPC_VARYING_INTERP[0x7].MODE: 0 0000: 00072142 00000000 00000000 00000000 00000000 00000000 00000000 00000000 * t0 write SP_FS_CTRL_REG0 (22e8) SP_FS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE } SP_FS_CTRL_REG1: { CONSTLENGTH = 3 | 0x80000000 } SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } SP_FS_OBJ_START: 0xc01aa000 0000: 00000003 30555000 00000700 20354001 00000000 20554002 00000704 20354003 0020: 00000020 20244b04 00006619 c6ea0008 00000000 00000100 02002610 d7260203 0040: 00000000 03000000 00000000 00000000 00000000 00000000 00000000 00000000 * 0000[30555000x_00000003x] (sy)(ss)mov.s32s32 r0.x, 3 0001[20354001x_00000700x] mov.s32s32 r0.y, c0.x 0002[20554002x_00000000x] mov.s32s32 r0.z, 0 0003[20354003x_00000704x] mov.s32s32 r0.w, c1.x 0004[20244b04x_00000020x] (rpt3)mov.f32f32 r1.x, (r)c8.x 0005[c6ea0008x_00006619x] ldgb.untyped.4d.s32.3 r2.x, g[0], r0.y, r0.x 0006[00000100x_00000000x] (rpt1)nop 0007[d7260203x_02002610x] (sy)stgb.untyped.4d.u32.3 g[1], r2.x, r0.z, r0.w 0008[03000000x_00000000x] end Register Stats: - used (half): (cnt=0, max=0) - used (full): 0-8 (cnt=9, max=8) - input (half): (cnt=0, max=0) - input (full): 8 (cnt=1, max=8) - const (half): (cnt=0, max=0) - const (full): 32-35 1792 1796 (cnt=6, max=1796) - output (half): (cnt=0, max=0) (estimated) - output (full): 4-7 (cnt=4, max=7) (estimated) 0000: 000322e8 00340c00 80000003 7e020000 c01aa000 t0 write SP_FS_LENGTH_REG (22ef) SP_FS_LENGTH_REG: 1 0000: 000022ef 00000001 t0 write RB_RENDER_COMPONENTS (20fb) RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } 0000: 000020fb 0000000f t3 opcode: CP_LOAD_STATE4 (30) (3 dwords) { DST_OFF = 0 | STATE_SRC = SS4_INDIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 1 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0xc01aa000 } 0000[30555000x_00000003x] (sy)(ss)mov.s32s32 r0.x, 3 0001[20354001x_00000700x] mov.s32s32 r0.y, c0.x 0002[20554002x_00000000x] mov.s32s32 r0.z, 0 0003[20354003x_00000704x] mov.s32s32 r0.w, c1.x 0004[20244b04x_00000020x] (rpt3)mov.f32f32 r1.x, (r)c8.x 0005[c6ea0008x_00006619x] ldgb.untyped.4d.s32.3 r2.x, g[0], r0.y, r0.x 0006[00000100x_00000000x] (rpt1)nop 0007[d7260203x_02002610x] (sy)stgb.untyped.4d.u32.3 g[1], r2.x, r0.z, r0.w 0008[03000000x_00000000x] end Register Stats: - used (half): (cnt=0, max=0) - used (full): 0-8 (cnt=9, max=8) - input (half): (cnt=0, max=0) - input (full): 8 (cnt=1, max=8) - const (half): (cnt=0, max=0) - const (full): 32-35 1792 1796 (cnt=6, max=1796) - output (half): (cnt=0, max=0) (estimated) - output (full): 4-7 (cnt=4, max=7) (estimated) 0000: c0013000 00720000 c01aa000 t0 write SP_VS_LENGTH_REG (22e5) SP_VS_LENGTH_REG: 1 0000: 000022e5 00000001 t3 opcode: CP_LOAD_STATE4 (30) (3 dwords) { DST_OFF = 0 | STATE_SRC = SS4_INDIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 1 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0xc01ac000 } 0000[30445300x_00000000x] (sy)(ss)(rpt3)mov.f32f32 r0.x, (0.000000) 0001[03000000x_00000000x] end Register Stats: - used (half): (cnt=0, max=0) - used (full): 0-3 (cnt=4, max=3) - input (half): (cnt=0, max=0) - input (full): (cnt=0, max=0) - const (half): (cnt=0, max=0) - const (full): (cnt=0, max=0) - output (half): (cnt=0, max=0) (estimated) - output (full): 0-3 (cnt=4, max=3) (estimated) 0000: c0013000 00620000 c01ac000 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 13 | GROUP_ID = 1 } { ADDR_LO = 0xc0414080 } count: 13 addr: 00000000c0414080 0000: 00002200 041a0001 00002201 fcfc0081 00002203 0000fc00 0003220a 00000003 0020: c01f0000 00000010 00000001 0000228a 24000051 t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 1 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 1 | STRMFETCHINSTRCNT = 1 | 0xa0000 } 0000: 00002200 041a0001 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } 0000: 00002201 fcfc0081 t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } 0000: 00002203 0000fc00 t0 write VFD_FETCH[0].INSTR_0 (220a) VFD_FETCH[0].INSTR_0: { FETCHSIZE = 3 | BUFSTRIDE = 0 } VFD_FETCH[0].INSTR_1: 0xc01f0000 0.000000 0.000000 0.000000 0.000000 0000: 00000000 00000000 00000000 00000000 VFD_FETCH[0].INSTR_2: { SIZE = 0x10 } VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } 0000: 0003220a 00000003 c01f0000 00000010 00000001 t0 write VFD_DECODE[0].INSTR (228a) VFD_DECODE[0].INSTR: { WRITEMASK = 0x1 | CONSTFILL | FORMAT = VFMT4_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 4 | LASTCOMPVALID } 0000: 0000228a 24000051 0000: c0014300 0100000d c0414080 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 15 | GROUP_ID = 0 } { ADDR_LO = 0xc04140c0 } count: 15 addr: 00000000c04140c0 0000: 00002073 00000000 00002101 00000014 00002106 00000000 000021e5 00000000 0020: 0001210b 00000000 00000000 00002381 00000000 000023a0 00000000 t0 write GRAS_ALPHA_CONTROL (2073) GRAS_ALPHA_CONTROL: { 0 } 0000: 00002073 00000000 t0 write RB_DEPTH_CONTROL (2101) RB_DEPTH_CONTROL: { Z_WRITE_ENABLE | ZFUNC = FUNC_LESS } 0000: 00002101 00000014 t0 write RB_STENCIL_CONTROL (2106) RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } 0000: 00002106 00000000 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 0000: 000021e5 00000000 t0 write RB_STENCILREFMASK (210b) RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 0000: 0001210b 00000000 00000000 t0 write TPL1_TP_TEX_COUNT (2381) TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } 0000: 00002381 00000000 t0 write TPL1_TP_FS_TEX_COUNT (23a0) TPL1_TP_FS_TEX_COUNT: 0 0000: 000023a0 00000000 0000: c0014300 0000000f c04140c0 t0 write RB_MRT[0].BUF_INFO (20a5) RB_MRT[0].BUF_INFO: { COLOR_FORMAT = 0x1b | COLOR_TILE_MODE = TILE4_LINEAR | DITHER_MODE = DITHER_ALWAYS | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 2560 } RB_MRT[0].BASE: 0xc0114000 RB_MRT[0].CONTROL3: { STRIDE = 2400 } 0000: 000220a5 0028021b c0114000 00004b00 t0 write RB_MRT[0x1].BUF_INFO (20aa) RB_MRT[0x1].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE4_LINEAR | DITHER_MODE = DITHER_ALWAYS | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 0 } RB_MRT[0x1].BASE: 0 RB_MRT[0x1].CONTROL3: { STRIDE = 0 } 0000: 000220aa 00000200 00000000 00000000 t0 write RB_MRT[0x2].BUF_INFO (20af) RB_MRT[0x2].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE4_LINEAR | DITHER_MODE = DITHER_ALWAYS | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 0 } RB_MRT[0x2].BASE: 0 RB_MRT[0x2].CONTROL3: { STRIDE = 0 } 0000: 000220af 00000200 00000000 00000000 t0 write RB_MRT[0x3].BUF_INFO (20b4) RB_MRT[0x3].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE4_LINEAR | DITHER_MODE = DITHER_ALWAYS | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 0 } RB_MRT[0x3].BASE: 0 RB_MRT[0x3].CONTROL3: { STRIDE = 0 } 0000: 000220b4 00000200 00000000 00000000 t0 write RB_MRT[0x4].BUF_INFO (20b9) RB_MRT[0x4].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE4_LINEAR | DITHER_MODE = DITHER_ALWAYS | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 0 } RB_MRT[0x4].BASE: 0 RB_MRT[0x4].CONTROL3: { STRIDE = 0 } 0000: 000220b9 00000200 00000000 00000000 t0 write RB_MRT[0x5].BUF_INFO (20be) RB_MRT[0x5].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE4_LINEAR | DITHER_MODE = DITHER_ALWAYS | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 0 } RB_MRT[0x5].BASE: 0 RB_MRT[0x5].CONTROL3: { STRIDE = 0 } 0000: 000220be 00000200 00000000 00000000 t0 write RB_MRT[0x6].BUF_INFO (20c3) RB_MRT[0x6].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE4_LINEAR | DITHER_MODE = DITHER_ALWAYS | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 0 } RB_MRT[0x6].BASE: 0 RB_MRT[0x6].CONTROL3: { STRIDE = 0 } 0000: 000220c3 00000200 00000000 00000000 t0 write RB_MRT[0x7].BUF_INFO (20c8) RB_MRT[0x7].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE4_LINEAR | DITHER_MODE = DITHER_ALWAYS | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 0 } RB_MRT[0x7].BASE: 0 RB_MRT[0x7].CONTROL3: { STRIDE = 0 } 0000: 000220c8 00000200 00000000 00000000 t0 write RB_DEPTH_INFO (2103) RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTH4_16 | DEPTH_BASE = 0xc01b0000 } RB_DEPTH_PITCH: 896 RB_DEPTH_PITCH2: 217088 0000: 00022103 c01b0001 0000001c 00001a80 t0 write GRAS_DEPTH_CONTROL (2077) GRAS_DEPTH_CONTROL: { FORMAT = DEPTH4_16 } 0000: 00002077 00000001 t0 write RB_STENCIL_INFO (2108) RB_STENCIL_INFO: { STENCIL_BASE = 0 } RB_STENCIL_PITCH: 0 0x210a: 00000000 0000: 00022108 00000000 00000000 00000000 t0 write 0x2002 (2002) 0x2002: 00000000 0000: 00002002 00000000 t0 write RB_MRT[0].CONTROL (20a4) RB_MRT[0].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf } 0000: 000020a4 0f000c00 t0 write RB_MRT[0].BLEND_CONTROL (20a8) RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } 0000: 000020a8 00000000 t0 write RB_BLEND_RED (20f0) RB_BLEND_RED: { UINT = 0 | SINT = 0 | FLOAT = 0.000000 } RB_BLEND_RED_F32: 0.000000 RB_BLEND_GREEN: { UINT = 0 | SINT = 0 | FLOAT = 0.000000 } RB_BLEND_GREEN_F32: 0.000000 RB_BLEND_BLUE: { UINT = 0 | SINT = 0 | FLOAT = 0.000000 } RB_BLEND_BLUE_F32: 0.000000 RB_BLEND_ALPHA: { UINT = 0 | SINT = 0 | FLOAT = 0.000000 } RB_BLEND_ALPHA_F32: 0.000000 0000: 000720f0 00000000 00000000 00000000 00000000 00000000 00000000 00000000 * t0 write RB_ALPHA_CONTROL (20f8) RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } 0000: 000020f8 00000e00 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 0000: c0002600 00000000 t0 write PC_TESSFACTOR_ADDR (0d08) PC_TESSFACTOR_ADDR: 0 0000: 00000d08 00000000 t0 write VFD_INDEX_OFFSET (2208) VFD_INDEX_OFFSET: 0 0000: 00002208 00000000 t0 write UNKNOWN_2209 (2209) UNKNOWN_2209: 0 0000: 00002209 00000000 t0 write SP_SP_CTRL_REG (22c0) SP_SP_CTRL_REG: { 0x60010 } 0000: 000022c0 00060010 t0 write SP_INSTR_CACHE_CTRL (22c1) SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x7f } 0000: 000022c1 000005ff t0 write PC_PRIM_VTX_CNTL (21c4) PC_PRIM_VTX_CNTL: { VAROUT = 0 | PROVOKING_VTX_LAST } 0000: 000021c4 02000000 t0 write VPC_PACK (2141) VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 0 | NUMNONPOSVSVAR = 0 } 0000: 00002141 00000000 t0 write UNKNOWN_2001 (2001) UNKNOWN_2001: 0 0000: 00002001 00000000 t0 write SP_VS_CTRL_REG0 (22c4) SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 0000: 000022c4 00200400 t0 write SP_VS_CTRL_REG1 (22c5) SP_VS_CTRL_REG1: { CONSTLENGTH = 2 | INITIALOUTSTANDING = 0 } 0000: 000022c5 00000002 t0 write 0x230c (230c) 0x230c: 00000000 0000: 0000230c 00000000 t0 write 0x2318 (2318) 0x2318: 00000000 0000: 00002318 00000000 t0 write 0x2319 (2319) 0x2319: 00000000 0000: 00002319 00000000 t0 write 0x2340 (2340) 0x2340: 00000000 0000: 00002340 00000000 t0 write VFD_CONTROL_2 (2202) VFD_CONTROL_2: 0xfcfcfcfc 0000: 00002202 fcfcfcfc t0 write VFD_CONTROL_4 (2204) VFD_CONTROL_4: 0xfcfc 0000: 00002204 0000fcfc t0 write UNKNOWN_2154 (2154) UNKNOWN_2154: 0 0000: 00002154 00000000 t0 write PC_HS_PARAM (21e7) PC_HS_PARAM: { VERTICES_OUT = 0 | SPACING = EQUAL_SPACING } 0000: 000021e7 00000000 t0 write PC_PRIM_VTX_CNTL2 (21c5) PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 0000: 000021c5 00000012 t3 opcode: CP_LOAD_STATE4 (30) (11 dwords) { DST_OFF = 16 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = 0x6 | NUM_UNIT = 4 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } 0000: 00000000 00000000 00000000 00000000 0000: c0093000 01180010 00000001 00000000 00000000 00000000 00000000 00000000 0020: 00000000 00000000 00800000 t3 opcode: CP_LOAD_STATE4 (30) (11 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = 0x6 | NUM_UNIT = 4 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } 0000: 00000000 00000000 00000000 00000000 0000: c0093000 01180000 00000001 00000000 00000000 00000000 00000000 00000000 0020: 00000000 00000000 00800000 t3 opcode: CP_LOAD_STATE4 (30) (19 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 4 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -3.019531 0000: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 0020: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 c0414000 0000: c0113000 01300000 00000001 00000000 00000000 00000000 00000000 00000000 * 0040: 00000000 00000000 c0414000 t3 opcode: CP_LOAD_STATE4 (30) (19 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 4 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -3.019547 0000: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 0020: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 c0414040 0000: c0113000 01200000 00000001 00000000 00000000 00000000 00000000 00000000 * 0040: 00000000 00000000 c0414040 t3 opcode: CP_LOAD_STATE4 (30) (3 dwords) { DST_OFF = 8 | STATE_SRC = SS4_INDIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 4 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0xc0414000 } 1.000000 0.000000 0.000000 1.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0000: 3f800000 00000000 00000000 3f800000 00000000 00000000 00000000 00000000 * 0000: c0013000 01320008 c0414001 t0 write GRAS_CL_CLIP_CNTL (2000) GRAS_CL_CLIP_CNTL: { 0 } 0000: 00002000 00000000 t0 write GRAS_SU_POLY_OFFSET_SCALE (2074) GRAS_SU_POLY_OFFSET_SCALE: 0.000000 GRAS_SU_POLY_OFFSET_OFFSET: 0.000000 GRAS_SU_POLY_OFFSET_CLAMP: 0.000000 0000: 00022074 00000000 00000000 00000000 t0 write GRAS_SU_MODE_CONTROL (2078) GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.500000 | RENDERING_PASS } 0000: 00002078 00100010 t0 write GRAS_SC_SCREEN_SCISSOR_TL (207c) GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } GRAS_SC_SCREEN_SCISSOR_BR: { X = 399 | Y = 239 } 0000: 0001207c 00000000 00ef018f t0 write GRAS_CL_VPORT_XOFFSET_0 (2008) GRAS_CL_VPORT_XOFFSET_0: 200.000000 GRAS_CL_VPORT_XSCALE_0: 200.000000 GRAS_CL_VPORT_YOFFSET_0: 120.000000 GRAS_CL_VPORT_YSCALE_0: -120.000000 GRAS_CL_VPORT_ZOFFSET_0: 0.449992 GRAS_CL_VPORT_ZSCALE_0: 0.249996 0000: 00052008 43480000 43480000 42f00000 c2f00000 3ee66563 3e7ffee0 t0 write GRAS_CL_GB_CLIP_ADJ (2004) GRAS_CL_GB_CLIP_ADJ: { HORZ = 465 | VERT = 511 } 0000: 00002004 0007fdd1 t0 write GRAS_SC_CONTROL (207b) GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 0 | MSAA_DISABLE | RASTER_MODE = 0 } 0000: 0000207b 00000800 t0 write 0x2382 (2382) 0x2382: 00000000 0000: 00002382 00000000 t0 write RB_MSAA_CONTROL (20a2) RB_MSAA_CONTROL: { DISABLE | SAMPLES = 0 } 0000: 000020a2 00001000 t0 write RB_RENDER_CONTROL2 (20a3) RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 } 0000: 000020a3 00000000 t0 write SP_VS_PVT_MEM_PARAM (22e2) SP_VS_PVT_MEM_PARAM: 0 SP_VS_PVT_MEM_ADDR: 0 0x22e4: 00000000 0000: 000222e2 00000000 00000000 00000000 t0 write SP_FS_PVT_MEM_PARAM (22ec) SP_FS_PVT_MEM_PARAM: 0 SP_FS_PVT_MEM_ADDR: 0 0x22ee: 00000000 0000: 000222ec 00000000 00000000 00000000 t0 write SP_GS_PVT_MEM_PARAM (235d) SP_GS_PVT_MEM_PARAM: 0 SP_GS_PVT_MEM_ADDR: 0 0x235f: 00000000 0000: 0002235d 00000000 00000000 00000000 t0 write SP_HS_PVT_MEM_PARAM (230f) SP_HS_PVT_MEM_PARAM: 0 SP_HS_PVT_MEM_ADDR: 0 0x2311: 00000000 0000: 0002230f 00000000 00000000 00000000 t0 write SP_DS_PVT_MEM_PARAM (2336) SP_DS_PVT_MEM_PARAM: 0 SP_DS_PVT_MEM_ADDR: 0 0x2338: 00000000 0000: 00022336 00000000 00000000 00000000 t0 write RB_RENDER_CONTROL (20a1) RB_RENDER_CONTROL: { 0x8 } 0000: 000020a1 00000008 t0 write SP_FS_MRT[0].REG (22f1) SP_FS_MRT[0].REG: { REGID = r1.x | MRTFORMAT = 0x1b } SP_FS_MRT[0x1].REG: { REGID = r1.x | MRTFORMAT = 0 } SP_FS_MRT[0x2].REG: { REGID = r1.x | MRTFORMAT = 0 } SP_FS_MRT[0x3].REG: { REGID = r1.x | MRTFORMAT = 0 } SP_FS_MRT[0x4].REG: { REGID = r1.x | MRTFORMAT = 0 } SP_FS_MRT[0x5].REG: { REGID = r1.x | MRTFORMAT = 0 } SP_FS_MRT[0x6].REG: { REGID = r1.x | MRTFORMAT = 0 } SP_FS_MRT[0x7].REG: { REGID = r1.x | MRTFORMAT = 0 } 0000: 000722f1 0001b004 00000004 00000004 00000004 00000004 00000004 00000004 0020: 00000004 t0 write SP_FS_OUTPUT_REG (22f0) SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 0000: 000022f0 fc00fc01 t0 write RB_FS_OUTPUT_REG (2100) RB_FS_OUTPUT_REG: { MRT = 1 } 0000: 00002100 00000001 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 0000: 000021e5 00000000 t0 write RB_FS_OUTPUT (20f9) RB_FS_OUTPUT: { ENABLE_BLEND = 0 | INDEPENDENT_BLEND | SAMPLE_MASK = 0xffff } 0000: 000020f9 ffff0100 t0 write SP_DS_PARAM_REG (231a) SP_DS_PARAM_REG: { POSREGID = r0.x | TOTALGSOUTVAR = 0 } SP_DS_OUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_DS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_DS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_DS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_DS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_DS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_DS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_DS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_DS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_DS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_DS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_DS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_DS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_DS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_DS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_DS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } 0x232b: 00000000 SP_DS_VPC_DST[0].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_DS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_DS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_DS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_DS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_DS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_DS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_DS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 0000: 001a231a 00000000 00000000 00000000 00000000 00000000 00000000 00000000 * t0 write VPC_VARYING_PS_REPL[0].MODE (214a) VPC_VARYING_PS_REPL[0].MODE: 0 VPC_VARYING_PS_REPL[0x1].MODE: 0 VPC_VARYING_PS_REPL[0x2].MODE: 0 VPC_VARYING_PS_REPL[0x3].MODE: 0 VPC_VARYING_PS_REPL[0x4].MODE: 0 VPC_VARYING_PS_REPL[0x5].MODE: 0 VPC_VARYING_PS_REPL[0x6].MODE: 0 VPC_VARYING_PS_REPL[0x7].MODE: 0 0000: 0007214a 00000000 00000000 00000000 00000000 00000000 00000000 00000000 * t0 write VPC_ATTR (2140) VPC_ATTR: { TOTALATTR = 0 | THRDASSIGN = 1 | 0x40000000 } 0000: 00002140 40001000 t0 write SP_VS_PARAM_REG (22c6) SP_VS_PARAM_REG: { POSREGID = r0.x | PSIZEREGID = r63.x | TOTALVSOUTVAR = 0 } SP_VS_OUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } UNKNOWN_22D7: 0xfcfc00 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 0000: 001a22c6 0000fc00 00000000 00000000 00000000 00000000 00000000 00000000 * 0040: 00000000 00000000 00fcfc00 00000000 00000000 00000000 00000000 00000000 * t0 write 0x215c (215c) 0x215c: 00000000 0x215d: 00000000 0000: 0001215c 00000000 00000000 t0 write 0x215e (215e) 0x215e: 00000000 0000: 0000215e 00000000 t0 write 0x215f (215f) 0x215f: 00000000 0000: 0000215f 00000000 t0 write 0x2161 (2161) 0x2161: 00000000 0x2162: 00000000 0000: 00012161 00000000 00000000 t0 write 0x2163 (2163) 0x2163: 00000000 0000: 00002163 00000000 t0 write 0x2164 (2164) 0x2164: 00000000 0000: 00002164 00000000 t0 write 0x2166 (2166) 0x2166: 00000000 0x2167: 00000000 0000: 00012166 00000000 00000000 t0 write 0x2168 (2168) 0x2168: 00000000 0000: 00002168 00000000 t0 write 0x2169 (2169) 0x2169: 00000000 0000: 00002169 00000000 t0 write 0x216b (216b) 0x216b: 00000000 0x216c: 00000000 0000: 0001216b 00000000 00000000 t0 write 0x216d (216d) 0x216d: 00000000 0000: 0000216d 00000000 t0 write VPC_SO_FLUSH_WADDR_3 (216e) VPC_SO_FLUSH_WADDR_3: 0 0000: 0000216e 00000000 t0 write UNKNOWN_2156 (2156) UNKNOWN_2156: 0 0000: 00002156 00000000 t0 write 0x215b (215b) 0x215b: 00000000 0000: 0000215b 00000000 t0 write 0x2160 (2160) 0x2160: 00000000 0000: 00002160 00000000 t0 write 0x2165 (2165) 0x2165: 00000000 0000: 00002165 00000000 t0 write 0x216a (216a) 0x216a: 00000000 0000: 0000216a 00000000 t0 write 0x2158 (2158) 0x2158: 00010000 0x2159: 00000000 0000: 00012158 00010000 00000000 t0 write UNKNOWN_2157 (2157) UNKNOWN_2157: 0x1 0000: 00002157 00000001 t3 opcode: (null) (64) (2 dwords) 0000: c0006400 00000001 t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 1 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 1 | STRMFETCHINSTRCNT = 1 | 0xa0000 } 0000: 00002200 041a0001 0000: c0013f00 c00b3000 000001a5 t0 write UNKNOWN_2157 (2157) UNKNOWN_2157: 0x1 0000: 00002157 00000001 t3 opcode: (null) (64) (2 dwords) 0000: c0006400 00000001 t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:c009f000 ibsize:000001a0 t0 write SP_GS_OBJ_OFFSET_REG (235b) SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } 0000: 0000235b 7e020000 t0 write 0x2072 (2072) 0x2072: 00000000 0000: 00002072 00000000 t0 write UNKNOWN_2155 (2155) UNKNOWN_2155: 0 0000: 00002155 00000000 t0 write SP_HS_OBJ_OFFSET_REG (230d) SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } 0000: 0000230d 7e020000 t0 write SP_DS_OBJ_OFFSET_REG (2334) SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } 0000: 00002334 7e020000 t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x7 0000: 000023db 00000007 t0 write HLSQ_FS_CONTROL_REG (23c6) HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 3 | CONSTOBJECTOFFSET = 2 | SSBO_ENABLE | ENABLED | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 } 0000: 000023c6 017f8203 t0 write HLSQ_CONTROL_1_REG (23c1) HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x1028 } 0000: 000023c1 fcfc1128 t0 write HLSQ_CONTROL_2_REG (23c2) HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 0000: 000023c2 fff3f3f0 t0 write HLSQ_CONTROL_3_REG (23c3) HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r63.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } 0000: 000023c3 fcfcfcfc t0 write HLSQ_CONTROL_4_REG (23c4) HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } 0000: 000023c4 00fcfcfc t0 write HLSQ_VS_CONTROL_REG (23c5) HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 2 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 1 } 0000: 000023c5 01010002 t0 write HLSQ_HS_CONTROL_REG (23c7) HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 0000: 000023c7 007e0200 t0 write HLSQ_DS_CONTROL_REG (23c8) HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 0000: 000023c8 007e0200 t0 write HLSQ_GS_CONTROL_REG (23c9) HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 0000: 000023c9 007e0200 t0 write HLSQ_CS_CONTROL_REG (23ca) HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 48 | CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } 0000: 000023ca 00000030 t0 write SP_VS_OBJ_START (22e1) SP_VS_OBJ_START: 0xc01ac000 0000: 00000000 30445300 00000000 03000000 00000000 00000000 00000000 00000000 * 0000[30445300x_00000000x] (sy)(ss)(rpt3)mov.f32f32 r0.x, (0.000000) 0001[03000000x_00000000x] end Register Stats: - used (half): (cnt=0, max=0) - used (full): 0-3 (cnt=4, max=3) - input (half): (cnt=0, max=0) - input (full): (cnt=0, max=0) - const (half): (cnt=0, max=0) - const (full): (cnt=0, max=0) - output (half): (cnt=0, max=0) (estimated) - output (full): 0-3 (cnt=4, max=3) (estimated) 0000: 000022e1 c01ac000 t0 write SP_HS_OBJ_START (230e) SP_HS_OBJ_START: 0 0000: 0000230e 00000000 t0 write SP_DS_OBJ_START (2335) SP_DS_OBJ_START: 0 0000: 00002335 00000000 t0 write SP_GS_OBJ_START (235c) SP_GS_OBJ_START: 0 0000: 0000235c 00000000 t0 write GRAS_CNTL (2003) GRAS_CNTL: { 0 } 0000: 00002003 00000000 t0 write VPC_VARYING_INTERP[0].MODE (2142) VPC_VARYING_INTERP[0].MODE: 0 VPC_VARYING_INTERP[0x1].MODE: 0 VPC_VARYING_INTERP[0x2].MODE: 0 VPC_VARYING_INTERP[0x3].MODE: 0 VPC_VARYING_INTERP[0x4].MODE: 0 VPC_VARYING_INTERP[0x5].MODE: 0 VPC_VARYING_INTERP[0x6].MODE: 0 VPC_VARYING_INTERP[0x7].MODE: 0 0000: 00072142 00000000 00000000 00000000 00000000 00000000 00000000 00000000 * t0 write SP_FS_CTRL_REG0 (22e8) SP_FS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE } SP_FS_CTRL_REG1: { CONSTLENGTH = 3 | 0x80000000 } SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } SP_FS_OBJ_START: 0xc01aa000 0000: 00000003 30555000 00000700 20354001 00000000 20554002 00000704 20354003 0020: 00000020 20244b04 00006619 c6ea0008 00000000 00000100 02002610 d7260203 0040: 00000000 03000000 00000000 00000000 00000000 00000000 00000000 00000000 * 0000[30555000x_00000003x] (sy)(ss)mov.s32s32 r0.x, 3 0001[20354001x_00000700x] mov.s32s32 r0.y, c0.x 0002[20554002x_00000000x] mov.s32s32 r0.z, 0 0003[20354003x_00000704x] mov.s32s32 r0.w, c1.x 0004[20244b04x_00000020x] (rpt3)mov.f32f32 r1.x, (r)c8.x 0005[c6ea0008x_00006619x] ldgb.untyped.4d.s32.3 r2.x, g[0], r0.y, r0.x 0006[00000100x_00000000x] (rpt1)nop 0007[d7260203x_02002610x] (sy)stgb.untyped.4d.u32.3 g[1], r2.x, r0.z, r0.w 0008[03000000x_00000000x] end Register Stats: - used (half): (cnt=0, max=0) - used (full): 0-8 (cnt=9, max=8) - input (half): (cnt=0, max=0) - input (full): 8 (cnt=1, max=8) - const (half): (cnt=0, max=0) - const (full): 32-35 1792 1796 (cnt=6, max=1796) - output (half): (cnt=0, max=0) (estimated) - output (full): 4-7 (cnt=4, max=7) (estimated) 0000: 000322e8 00340c00 80000003 7e020000 c01aa000 t0 write SP_FS_LENGTH_REG (22ef) SP_FS_LENGTH_REG: 1 0000: 000022ef 00000001 t0 write RB_RENDER_COMPONENTS (20fb) RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } 0000: 000020fb 0000000f t3 opcode: CP_LOAD_STATE4 (30) (3 dwords) { DST_OFF = 0 | STATE_SRC = SS4_INDIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 1 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0xc01aa000 } 0000[30555000x_00000003x] (sy)(ss)mov.s32s32 r0.x, 3 0001[20354001x_00000700x] mov.s32s32 r0.y, c0.x 0002[20554002x_00000000x] mov.s32s32 r0.z, 0 0003[20354003x_00000704x] mov.s32s32 r0.w, c1.x 0004[20244b04x_00000020x] (rpt3)mov.f32f32 r1.x, (r)c8.x 0005[c6ea0008x_00006619x] ldgb.untyped.4d.s32.3 r2.x, g[0], r0.y, r0.x 0006[00000100x_00000000x] (rpt1)nop 0007[d7260203x_02002610x] (sy)stgb.untyped.4d.u32.3 g[1], r2.x, r0.z, r0.w 0008[03000000x_00000000x] end Register Stats: - used (half): (cnt=0, max=0) - used (full): 0-8 (cnt=9, max=8) - input (half): (cnt=0, max=0) - input (full): 8 (cnt=1, max=8) - const (half): (cnt=0, max=0) - const (full): 32-35 1792 1796 (cnt=6, max=1796) - output (half): (cnt=0, max=0) (estimated) - output (full): 4-7 (cnt=4, max=7) (estimated) 0000: c0013000 00720000 c01aa000 t0 write SP_VS_LENGTH_REG (22e5) SP_VS_LENGTH_REG: 1 0000: 000022e5 00000001 t3 opcode: CP_LOAD_STATE4 (30) (3 dwords) { DST_OFF = 0 | STATE_SRC = SS4_INDIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 1 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0xc01ac000 } 0000[30445300x_00000000x] (sy)(ss)(rpt3)mov.f32f32 r0.x, (0.000000) 0001[03000000x_00000000x] end Register Stats: - used (half): (cnt=0, max=0) - used (full): 0-3 (cnt=4, max=3) - input (half): (cnt=0, max=0) - input (full): (cnt=0, max=0) - const (half): (cnt=0, max=0) - const (full): (cnt=0, max=0) - output (half): (cnt=0, max=0) (estimated) - output (full): 0-3 (cnt=4, max=3) (estimated) 0000: c0013000 00620000 c01ac000 t0 write SP_SP_CTRL_REG (22c0) SP_SP_CTRL_REG: { 0x60010 } 0000: 000022c0 00060010 t0 write SP_INSTR_CACHE_CTRL (22c1) SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x7f } 0000: 000022c1 000005ff t0 write PC_PRIM_VTX_CNTL (21c4) PC_PRIM_VTX_CNTL: { VAROUT = 0 | PROVOKING_VTX_LAST } 0000: 000021c4 02000000 t0 write VPC_PACK (2141) VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 0 | NUMNONPOSVSVAR = 0 } 0000: 00002141 00000000 t0 write UNKNOWN_2001 (2001) UNKNOWN_2001: 0 0000: 00002001 00000000 t0 write SP_VS_CTRL_REG0 (22c4) SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 0000: 000022c4 00200400 t0 write SP_VS_CTRL_REG1 (22c5) SP_VS_CTRL_REG1: { CONSTLENGTH = 2 | INITIALOUTSTANDING = 0 } 0000: 000022c5 00000002 t0 write 0x230c (230c) 0x230c: 00000000 0000: 0000230c 00000000 t0 write 0x2318 (2318) 0x2318: 00000000 0000: 00002318 00000000 t0 write 0x2319 (2319) 0x2319: 00000000 0000: 00002319 00000000 t0 write 0x2340 (2340) 0x2340: 00000000 0000: 00002340 00000000 t0 write VFD_CONTROL_2 (2202) VFD_CONTROL_2: 0xfcfcfcfc 0000: 00002202 fcfcfcfc t0 write VFD_CONTROL_4 (2204) VFD_CONTROL_4: 0xfcfc 0000: 00002204 0000fcfc t0 write UNKNOWN_2154 (2154) UNKNOWN_2154: 0 0000: 00002154 00000000 t0 write PC_HS_PARAM (21e7) PC_HS_PARAM: { VERTICES_OUT = 0 | SPACING = EQUAL_SPACING } 0000: 000021e7 00000000 t0 write PC_PRIM_VTX_CNTL2 (21c5) PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 0000: 000021c5 00000012 t0 write SP_VS_PVT_MEM_PARAM (22e2) SP_VS_PVT_MEM_PARAM: 0 SP_VS_PVT_MEM_ADDR: 0 0x22e4: 00000000 0000: 000222e2 00000000 00000000 00000000 t0 write SP_FS_PVT_MEM_PARAM (22ec) SP_FS_PVT_MEM_PARAM: 0 SP_FS_PVT_MEM_ADDR: 0 0x22ee: 00000000 0000: 000222ec 00000000 00000000 00000000 t0 write SP_GS_PVT_MEM_PARAM (235d) SP_GS_PVT_MEM_PARAM: 0 SP_GS_PVT_MEM_ADDR: 0 0x235f: 00000000 0000: 0002235d 00000000 00000000 00000000 t0 write SP_HS_PVT_MEM_PARAM (230f) SP_HS_PVT_MEM_PARAM: 0 SP_HS_PVT_MEM_ADDR: 0 0x2311: 00000000 0000: 0002230f 00000000 00000000 00000000 t0 write SP_DS_PVT_MEM_PARAM (2336) SP_DS_PVT_MEM_PARAM: 0 SP_DS_PVT_MEM_ADDR: 0 0x2338: 00000000 0000: 00022336 00000000 00000000 00000000 t3 opcode: CP_LOAD_STATE4 (30) (11 dwords) { DST_OFF = 16 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = 0x6 | NUM_UNIT = 4 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } 0000: 00000000 00000000 00000000 00000000 0000: c0093000 01180010 00000001 00000000 00000000 00000000 00000000 00000000 0020: 00000000 00000000 00800000 t3 opcode: CP_LOAD_STATE4 (30) (11 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = 0x6 | NUM_UNIT = 4 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } 0000: 00000000 00000000 00000000 00000000 0000: c0093000 01180000 00000001 00000000 00000000 00000000 00000000 00000000 0020: 00000000 00000000 00800000 t3 opcode: CP_LOAD_STATE4 (30) (19 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 4 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -3.019531 0000: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 0020: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 c0414000 0000: c0113000 01300000 00000001 00000000 00000000 00000000 00000000 00000000 * 0040: 00000000 00000000 c0414000 t3 opcode: CP_LOAD_STATE4 (30) (19 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 4 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 -3.019547 0000: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 0020: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 c0414040 0000: c0113000 01200000 00000001 00000000 00000000 00000000 00000000 00000000 * 0040: 00000000 00000000 c0414040 t3 opcode: CP_LOAD_STATE4 (30) (3 dwords) { DST_OFF = 8 | STATE_SRC = SS4_INDIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 4 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0xc0414000 } 1.000000 0.000000 0.000000 1.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0000: 3f800000 00000000 00000000 3f800000 00000000 00000000 00000000 00000000 * 0000: c0013000 01320008 c0414001 t0 write RB_MRT[0].BUF_INFO (20a5) RB_MRT[0].BUF_INFO: { COLOR_FORMAT = 0x1b | COLOR_TILE_MODE = TILE4_LINEAR | DITHER_MODE = DITHER_ALWAYS | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 2560 } RB_MRT[0].BASE: 0xc0114000 RB_MRT[0].CONTROL3: { STRIDE = 2400 } 0000: 000220a5 0028021b c0114000 00004b00 t0 write RB_MRT[0x1].BUF_INFO (20aa) RB_MRT[0x1].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE4_LINEAR | DITHER_MODE = DITHER_ALWAYS | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 0 } RB_MRT[0x1].BASE: 0 RB_MRT[0x1].CONTROL3: { STRIDE = 0 } 0000: 000220aa 00000200 00000000 00000000 t0 write RB_MRT[0x2].BUF_INFO (20af) RB_MRT[0x2].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE4_LINEAR | DITHER_MODE = DITHER_ALWAYS | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 0 } RB_MRT[0x2].BASE: 0 RB_MRT[0x2].CONTROL3: { STRIDE = 0 } 0000: 000220af 00000200 00000000 00000000 t0 write RB_MRT[0x3].BUF_INFO (20b4) RB_MRT[0x3].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE4_LINEAR | DITHER_MODE = DITHER_ALWAYS | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 0 } RB_MRT[0x3].BASE: 0 RB_MRT[0x3].CONTROL3: { STRIDE = 0 } 0000: 000220b4 00000200 00000000 00000000 t0 write RB_MRT[0x4].BUF_INFO (20b9) RB_MRT[0x4].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE4_LINEAR | DITHER_MODE = DITHER_ALWAYS | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 0 } RB_MRT[0x4].BASE: 0 RB_MRT[0x4].CONTROL3: { STRIDE = 0 } 0000: 000220b9 00000200 00000000 00000000 t0 write RB_MRT[0x5].BUF_INFO (20be) RB_MRT[0x5].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE4_LINEAR | DITHER_MODE = DITHER_ALWAYS | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 0 } RB_MRT[0x5].BASE: 0 RB_MRT[0x5].CONTROL3: { STRIDE = 0 } 0000: 000220be 00000200 00000000 00000000 t0 write RB_MRT[0x6].BUF_INFO (20c3) RB_MRT[0x6].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE4_LINEAR | DITHER_MODE = DITHER_ALWAYS | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 0 } RB_MRT[0x6].BASE: 0 RB_MRT[0x6].CONTROL3: { STRIDE = 0 } 0000: 000220c3 00000200 00000000 00000000 t0 write RB_MRT[0x7].BUF_INFO (20c8) RB_MRT[0x7].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE4_LINEAR | DITHER_MODE = DITHER_ALWAYS | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 0 } RB_MRT[0x7].BASE: 0 RB_MRT[0x7].CONTROL3: { STRIDE = 0 } 0000: 000220c8 00000200 00000000 00000000 t0 write RB_DEPTH_INFO (2103) RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTH4_16 | DEPTH_BASE = 0xc01b0000 } RB_DEPTH_PITCH: 896 RB_DEPTH_PITCH2: 217088 0000: 00022103 c01b0001 0000001c 00001a80 t0 write GRAS_DEPTH_CONTROL (2077) GRAS_DEPTH_CONTROL: { FORMAT = DEPTH4_16 } 0000: 00002077 00000001 t0 write RB_STENCIL_INFO (2108) RB_STENCIL_INFO: { STENCIL_BASE = 0 } RB_STENCIL_PITCH: 0 0x210a: 00000000 0000: 00022108 00000000 00000000 00000000 t0 write 0x2002 (2002) 0x2002: 00000000 0000: 00002002 00000000 t0 write RB_ALPHA_CONTROL (20f8) RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } 0000: 000020f8 00000e00 t0 write RB_MRT[0].CONTROL (20a4) RB_MRT[0].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf } 0000: 000020a4 0f000c00 t0 write RB_MRT[0].BLEND_CONTROL (20a8) RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } 0000: 000020a8 00000000 t0 write GRAS_CL_CLIP_CNTL (2000) GRAS_CL_CLIP_CNTL: { 0 } 0000: 00002000 00000000 t0 write GRAS_SU_POLY_OFFSET_SCALE (2074) GRAS_SU_POLY_OFFSET_SCALE: 0.000000 GRAS_SU_POLY_OFFSET_OFFSET: 0.000000 GRAS_SU_POLY_OFFSET_CLAMP: 0.000000 0000: 00022074 00000000 00000000 00000000 t0 write GRAS_SU_MODE_CONTROL (2078) GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.500000 | RENDERING_PASS } 0000: 00002078 00100010 t0 write GRAS_SC_SCREEN_SCISSOR_TL (207c) GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } GRAS_SC_SCREEN_SCISSOR_BR: { X = 399 | Y = 239 } 0000: 0001207c 00000000 00ef018f t0 write GRAS_CL_VPORT_XOFFSET_0 (2008) GRAS_CL_VPORT_XOFFSET_0: 200.000000 GRAS_CL_VPORT_XSCALE_0: 200.000000 GRAS_CL_VPORT_YOFFSET_0: 120.000000 GRAS_CL_VPORT_YSCALE_0: -120.000000 GRAS_CL_VPORT_ZOFFSET_0: 0.449992 GRAS_CL_VPORT_ZSCALE_0: 0.249996 0000: 00052008 43480000 43480000 42f00000 c2f00000 3ee66563 3e7ffee0 t0 write GRAS_CL_GB_CLIP_ADJ (2004) GRAS_CL_GB_CLIP_ADJ: { HORZ = 465 | VERT = 511 } 0000: 00002004 0007fdd1 t0 write GRAS_SC_CONTROL (207b) GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 0 | MSAA_DISABLE | RASTER_MODE = 0 } 0000: 0000207b 00000800 t0 write 0x2382 (2382) 0x2382: 00000000 0000: 00002382 00000000 t0 write RB_MSAA_CONTROL (20a2) RB_MSAA_CONTROL: { DISABLE | SAMPLES = 0 } 0000: 000020a2 00001000 t0 write RB_RENDER_CONTROL2 (20a3) RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 } 0000: 000020a3 00000000 t3 opcode: CP_LOAD_STATE4 (30) (11 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_SSBO | NUM_UNIT = 2 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } { BASE = 0xc0210000 } { PITCH = 0 } { ARRAY_PITCH = 0 } { CPP = 0 } 0000: c0210000 00000000 00000000 00000000 { BASE = 0xc0312000 } { PITCH = 0 } { ARRAY_PITCH = 0 } { CPP = 0 } 0000: c0312000 00000000 00000000 00000000 0000: c0093000 00b80000 00000000 c0210000 00000000 00000000 00000000 c0312000 * t3 opcode: CP_LOAD_STATE4 (30) (7 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_SSBO | NUM_UNIT = 2 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } { CPP = 0 | FMT = 0 | WIDTH = 5 } { HEIGHT = 4 | DEPTH = 0 } 0000: 00050000 00000004 { CPP = 0 | FMT = 0 | WIDTH = 8 } { HEIGHT = 4 | DEPTH = 0 } 0000: 00080000 00000004 0000: c0053000 00b80000 00000001 00050000 00000004 00080000 00000004 t0 write RB_RENDER_CONTROL (20a1) RB_RENDER_CONTROL: { 0x8 } 0000: 000020a1 00000008 t0 write SP_FS_MRT[0].REG (22f1) SP_FS_MRT[0].REG: { REGID = r1.x | MRTFORMAT = 0x1b } SP_FS_MRT[0x1].REG: { REGID = r1.x | MRTFORMAT = 0 } SP_FS_MRT[0x2].REG: { REGID = r1.x | MRTFORMAT = 0 } SP_FS_MRT[0x3].REG: { REGID = r1.x | MRTFORMAT = 0 } SP_FS_MRT[0x4].REG: { REGID = r1.x | MRTFORMAT = 0 } SP_FS_MRT[0x5].REG: { REGID = r1.x | MRTFORMAT = 0 } SP_FS_MRT[0x6].REG: { REGID = r1.x | MRTFORMAT = 0 } SP_FS_MRT[0x7].REG: { REGID = r1.x | MRTFORMAT = 0 } 0000: 000722f1 0001b004 00000004 00000004 00000004 00000004 00000004 00000004 0020: 00000004 t0 write SP_FS_OUTPUT_REG (22f0) SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 0000: 000022f0 fc00fc01 t0 write RB_FS_OUTPUT_REG (2100) RB_FS_OUTPUT_REG: { MRT = 1 } 0000: 00002100 00000001 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 0000: 000021e5 00000000 t0 write RB_FS_OUTPUT (20f9) RB_FS_OUTPUT: { ENABLE_BLEND = 0 | INDEPENDENT_BLEND | SAMPLE_MASK = 0xffff } 0000: 000020f9 ffff0100 t0 write SP_DS_PARAM_REG (231a) SP_DS_PARAM_REG: { POSREGID = r0.x | TOTALGSOUTVAR = 0 } SP_DS_OUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_DS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_DS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_DS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_DS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_DS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_DS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_DS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_DS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_DS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_DS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_DS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_DS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_DS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_DS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_DS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } 0x232b: 00000000 SP_DS_VPC_DST[0].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_DS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_DS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_DS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_DS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_DS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_DS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_DS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 0000: 001a231a 00000000 00000000 00000000 00000000 00000000 00000000 00000000 * t0 write VPC_VARYING_PS_REPL[0].MODE (214a) VPC_VARYING_PS_REPL[0].MODE: 0 VPC_VARYING_PS_REPL[0x1].MODE: 0 VPC_VARYING_PS_REPL[0x2].MODE: 0 VPC_VARYING_PS_REPL[0x3].MODE: 0 VPC_VARYING_PS_REPL[0x4].MODE: 0 VPC_VARYING_PS_REPL[0x5].MODE: 0 VPC_VARYING_PS_REPL[0x6].MODE: 0 VPC_VARYING_PS_REPL[0x7].MODE: 0 0000: 0007214a 00000000 00000000 00000000 00000000 00000000 00000000 00000000 * t0 write VPC_ATTR (2140) VPC_ATTR: { TOTALATTR = 0 | THRDASSIGN = 1 | 0x40000000 } 0000: 00002140 40001000 t0 write SP_VS_PARAM_REG (22c6) SP_VS_PARAM_REG: { POSREGID = r0.x | PSIZEREGID = r63.x | TOTALVSOUTVAR = 0 } SP_VS_OUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } UNKNOWN_22D7: 0xfcfc00 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 0000: 001a22c6 0000fc00 00000000 00000000 00000000 00000000 00000000 00000000 * 0040: 00000000 00000000 00fcfc00 00000000 00000000 00000000 00000000 00000000 * t0 write 0x215c (215c) 0x215c: 00000000 0x215d: 00000000 0000: 0001215c 00000000 00000000 t0 write 0x215e (215e) 0x215e: 00000000 0000: 0000215e 00000000 t0 write 0x215f (215f) 0x215f: 00000000 0000: 0000215f 00000000 t0 write 0x2161 (2161) 0x2161: 00000000 0x2162: 00000000 0000: 00012161 00000000 00000000 t0 write 0x2163 (2163) 0x2163: 00000000 0000: 00002163 00000000 t0 write 0x2164 (2164) 0x2164: 00000000 0000: 00002164 00000000 t0 write 0x2166 (2166) 0x2166: 00000000 0x2167: 00000000 0000: 00012166 00000000 00000000 t0 write 0x2168 (2168) 0x2168: 00000000 0000: 00002168 00000000 t0 write 0x2169 (2169) 0x2169: 00000000 0000: 00002169 00000000 t0 write 0x216b (216b) 0x216b: 00000000 0x216c: 00000000 0000: 0001216b 00000000 00000000 t0 write 0x216d (216d) 0x216d: 00000000 0000: 0000216d 00000000 t0 write VPC_SO_FLUSH_WADDR_3 (216e) VPC_SO_FLUSH_WADDR_3: 0 0000: 0000216e 00000000 t0 write UNKNOWN_2156 (2156) UNKNOWN_2156: 0 0000: 00002156 00000000 t0 write 0x215b (215b) 0x215b: 00000000 0000: 0000215b 00000000 t0 write 0x2160 (2160) 0x2160: 00000000 0000: 00002160 00000000 t0 write 0x2165 (2165) 0x2165: 00000000 0000: 00002165 00000000 t0 write 0x216a (216a) 0x216a: 00000000 0000: 0000216a 00000000 t0 write 0x2158 (2158) 0x2158: 00010000 0x2159: 00000000 0000: 00012158 00010000 00000000 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 13 | GROUP_ID = 1 } { ADDR_LO = 0xc0414080 } count: 13 addr: 00000000c0414080 0000: 00002200 041a0001 00002201 fcfc0081 00002203 0000fc00 0003220a 00000003 0020: c01f0000 00000010 00000001 0000228a 24000051 t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 1 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 1 | STRMFETCHINSTRCNT = 1 | 0xa0000 } 0000: 00002200 041a0001 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } 0000: 00002201 fcfc0081 t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } 0000: 00002203 0000fc00 t0 write VFD_FETCH[0].INSTR_0 (220a) VFD_FETCH[0].INSTR_0: { FETCHSIZE = 3 | BUFSTRIDE = 0 } VFD_FETCH[0].INSTR_1: 0xc01f0000 0.000000 0.000000 0.000000 0.000000 0000: 00000000 00000000 00000000 00000000 VFD_FETCH[0].INSTR_2: { SIZE = 0x10 } VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } 0000: 0003220a 00000003 c01f0000 00000010 00000001 t0 write VFD_DECODE[0].INSTR (228a) VFD_DECODE[0].INSTR: { WRITEMASK = 0x1 | CONSTFILL | FORMAT = VFMT4_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 4 | LASTCOMPVALID } 0000: 0000228a 24000051 0000: c0014300 0100000d c0414080 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 15 | GROUP_ID = 0 } { ADDR_LO = 0xc04140c0 } count: 15 addr: 00000000c04140c0 0000: 00002073 00000000 00002101 00000014 00002106 00000000 000021e5 00000000 0020: 0001210b 00000000 00000000 00002381 00000000 000023a0 00000000 t0 write GRAS_ALPHA_CONTROL (2073) GRAS_ALPHA_CONTROL: { 0 } 0000: 00002073 00000000 t0 write RB_DEPTH_CONTROL (2101) RB_DEPTH_CONTROL: { Z_WRITE_ENABLE | ZFUNC = FUNC_LESS } 0000: 00002101 00000014 t0 write RB_STENCIL_CONTROL (2106) RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } 0000: 00002106 00000000 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 0000: 000021e5 00000000 t0 write RB_STENCILREFMASK (210b) RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 0000: 0001210b 00000000 00000000 t0 write TPL1_TP_TEX_COUNT (2381) TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } 0000: 00002381 00000000 t0 write TPL1_TP_FS_TEX_COUNT (23a0) TPL1_TP_FS_TEX_COUNT: 0 0000: 000023a0 00000000 0000: c0014300 0000000f c04140c0 t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = USE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x200000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 4 } draw[0] register values + 00000000 0xcc4: 00000000 !+ 00000006 UNKNOWN_0CC5: 0x6 + 00000000 UNKNOWN_0CC6: 0 !+ 00f00190 RB_FRAME_BUFFER_DIMENSION: { WIDTH = 400 | HEIGHT = 240 } !+ 00000001 0xce1: 00000001 !+ c0200000 0xd03: c0200000 + 00000000 PC_TESSFACTOR_ADDR: 0 !+ 00000001 HLSQ_MODE_CONTROL: 0x1 + 00000000 UNKNOWN_0E42: 0 + 00000000 UCHE_INVALIDATE0: 0 !+ 00000012 UCHE_INVALIDATE1: 0x12 !+ 00040000 UNKNOWN_0EC2: 0x40000 !+ 0000001e SP_MODE_CONTROL: 0x1e !+ 00000038 TPL1_TP_MODE_CONTROL: 0x38 + 00000000 GRAS_CL_CLIP_CNTL: { 0 } + 00000000 UNKNOWN_2001: 0 + 00000000 0x2002: 00000000 + 00000000 GRAS_CNTL: { 0 } !+ 0007fdd1 GRAS_CL_GB_CLIP_ADJ: { HORZ = 465 | VERT = 511 } !+ 43480000 GRAS_CL_VPORT_XOFFSET_0: 200.000000 !+ 43480000 GRAS_CL_VPORT_XSCALE_0: 200.000000 !+ 42f00000 GRAS_CL_VPORT_YOFFSET_0: 120.000000 !+ c2f00000 GRAS_CL_VPORT_YSCALE_0: -120.000000 !+ 3ee66563 GRAS_CL_VPORT_ZOFFSET_0: 0.449992 !+ 3e7ffee0 GRAS_CL_VPORT_ZSCALE_0: 0.249996 !+ ffc00010 GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 4092.000000 } !+ 00000008 GRAS_SU_POINT_SIZE: 0.500000 + 00000000 0x2072: 00000000 + 00000000 GRAS_ALPHA_CONTROL: { 0 } + 00000000 GRAS_SU_POLY_OFFSET_SCALE: 0.000000 + 00000000 GRAS_SU_POLY_OFFSET_OFFSET: 0.000000 + 00000000 GRAS_SU_POLY_OFFSET_CLAMP: 0.000000 !+ 00000001 GRAS_DEPTH_CONTROL: { FORMAT = DEPTH4_16 } !+ 00100010 GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.500000 | RENDERING_PASS } !+ 00000800 GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 0 | MSAA_DISABLE | RASTER_MODE = 0 } + 00000000 GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } !+ 00ef018f GRAS_SC_SCREEN_SCISSOR_BR: { X = 399 | Y = 239 } !+ 00ef018f GRAS_SC_WINDOW_SCISSOR_BR: { X = 399 | Y = 239 } + 00000000 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } !+ 00c00000 RB_MODE_CONTROL: { WIDTH = 0 | HEIGHT = 0 | 0xc00000 } !+ 00000008 RB_RENDER_CONTROL: { 0x8 } !+ 00001000 RB_MSAA_CONTROL: { DISABLE | SAMPLES = 0 } + 00000000 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 } !+ 0f000c00 RB_MRT[0].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf } !+ 0028021b RB_MRT[0].BUF_INFO: { COLOR_FORMAT = 0x1b | COLOR_TILE_MODE = TILE4_LINEAR | DITHER_MODE = DITHER_ALWAYS | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 2560 } !+ c0114000 RB_MRT[0].BASE: 0xc0114000 !+ 00004b00 RB_MRT[0].CONTROL3: { STRIDE = 2400 } + 00000000 RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } !+ 00000200 RB_MRT[0x1].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE4_LINEAR | DITHER_MODE = DITHER_ALWAYS | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 0 } + 00000000 RB_MRT[0x1].BASE: 0 + 00000000 RB_MRT[0x1].CONTROL3: { STRIDE = 0 } !+ 00000200 RB_MRT[0x2].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE4_LINEAR | DITHER_MODE = DITHER_ALWAYS | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 0 } + 00000000 RB_MRT[0x2].BASE: 0 + 00000000 RB_MRT[0x2].CONTROL3: { STRIDE = 0 } !+ 00000200 RB_MRT[0x3].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE4_LINEAR | DITHER_MODE = DITHER_ALWAYS | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 0 } + 00000000 RB_MRT[0x3].BASE: 0 + 00000000 RB_MRT[0x3].CONTROL3: { STRIDE = 0 } !+ 00000200 RB_MRT[0x4].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE4_LINEAR | DITHER_MODE = DITHER_ALWAYS | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 0 } + 00000000 RB_MRT[0x4].BASE: 0 + 00000000 RB_MRT[0x4].CONTROL3: { STRIDE = 0 } !+ 00000200 RB_MRT[0x5].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE4_LINEAR | DITHER_MODE = DITHER_ALWAYS | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 0 } + 00000000 RB_MRT[0x5].BASE: 0 + 00000000 RB_MRT[0x5].CONTROL3: { STRIDE = 0 } !+ 00000200 RB_MRT[0x6].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE4_LINEAR | DITHER_MODE = DITHER_ALWAYS | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 0 } + 00000000 RB_MRT[0x6].BASE: 0 + 00000000 RB_MRT[0x6].CONTROL3: { STRIDE = 0 } !+ 00000200 RB_MRT[0x7].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE4_LINEAR | DITHER_MODE = DITHER_ALWAYS | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 0 } + 00000000 RB_MRT[0x7].BASE: 0 + 00000000 RB_MRT[0x7].CONTROL3: { STRIDE = 0 } + 00000000 RB_BLEND_RED: { UINT = 0 | SINT = 0 | FLOAT = 0.000000 } + 00000000 RB_BLEND_RED_F32: 0.000000 + 00000000 RB_BLEND_GREEN: { UINT = 0 | SINT = 0 | FLOAT = 0.000000 } + 00000000 RB_BLEND_GREEN_F32: 0.000000 + 00000000 RB_BLEND_BLUE: { UINT = 0 | SINT = 0 | FLOAT = 0.000000 } + 00000000 RB_BLEND_BLUE_F32: 0.000000 + 00000000 RB_BLEND_ALPHA: { UINT = 0 | SINT = 0 | FLOAT = 0.000000 } + 00000000 RB_BLEND_ALPHA_F32: 0.000000 !+ 00000e00 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } !+ ffff0100 RB_FS_OUTPUT: { ENABLE_BLEND = 0 | INDEPENDENT_BLEND | SAMPLE_MASK = 0xffff } !+ 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } !+ 00000001 RB_FS_OUTPUT_REG: { MRT = 1 } !+ 00000014 RB_DEPTH_CONTROL: { Z_WRITE_ENABLE | ZFUNC = FUNC_LESS } !+ c01b0001 RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTH4_16 | DEPTH_BASE = 0xc01b0000 } !+ 0000001c RB_DEPTH_PITCH: 896 !+ 00001a80 RB_DEPTH_PITCH2: 217088 + 00000000 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } + 00000000 RB_STENCIL_INFO: { STENCIL_BASE = 0 } + 00000000 RB_STENCIL_PITCH: 0 + 00000000 0x210a: 00000000 + 00000000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } + 00000000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } + 00000000 RB_BIN_OFFSET: { X = 0 | Y = 0 } !+ 40001000 VPC_ATTR: { TOTALATTR = 0 | THRDASSIGN = 1 | 0x40000000 } + 00000000 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 0 | NUMNONPOSVSVAR = 0 } + 00000000 VPC_VARYING_INTERP[0].MODE: 0 + 00000000 VPC_VARYING_INTERP[0x1].MODE: 0 + 00000000 VPC_VARYING_INTERP[0x2].MODE: 0 + 00000000 VPC_VARYING_INTERP[0x3].MODE: 0 + 00000000 VPC_VARYING_INTERP[0x4].MODE: 0 + 00000000 VPC_VARYING_INTERP[0x5].MODE: 0 + 00000000 VPC_VARYING_INTERP[0x6].MODE: 0 + 00000000 VPC_VARYING_INTERP[0x7].MODE: 0 + 00000000 VPC_VARYING_PS_REPL[0].MODE: 0 + 00000000 VPC_VARYING_PS_REPL[0x1].MODE: 0 + 00000000 VPC_VARYING_PS_REPL[0x2].MODE: 0 + 00000000 VPC_VARYING_PS_REPL[0x3].MODE: 0 + 00000000 VPC_VARYING_PS_REPL[0x4].MODE: 0 + 00000000 VPC_VARYING_PS_REPL[0x5].MODE: 0 + 00000000 VPC_VARYING_PS_REPL[0x6].MODE: 0 + 00000000 VPC_VARYING_PS_REPL[0x7].MODE: 0 + 00000000 UNKNOWN_2152: 0 + 00000000 UNKNOWN_2153: 0 + 00000000 UNKNOWN_2154: 0 + 00000000 UNKNOWN_2155: 0 + 00000000 UNKNOWN_2156: 0 !+ 00000001 UNKNOWN_2157: 0x1 !+ 00010000 0x2158: 00010000 + 00000000 0x2159: 00000000 + 00000000 0x215b: 00000000 + 00000000 0x215c: 00000000 + 00000000 0x215d: 00000000 + 00000000 0x215e: 00000000 + 00000000 0x215f: 00000000 + 00000000 0x2160: 00000000 + 00000000 0x2161: 00000000 + 00000000 0x2162: 00000000 + 00000000 0x2163: 00000000 + 00000000 0x2164: 00000000 + 00000000 0x2165: 00000000 + 00000000 0x2166: 00000000 + 00000000 0x2167: 00000000 + 00000000 0x2168: 00000000 + 00000000 0x2169: 00000000 + 00000000 0x216a: 00000000 + 00000000 0x216b: 00000000 + 00000000 0x216c: 00000000 + 00000000 0x216d: 00000000 + 00000000 VPC_SO_FLUSH_WADDR_3: 0 !+ 0000001d UNKNOWN_21C3: 0x1d !+ 02000000 PC_PRIM_VTX_CNTL: { VAROUT = 0 | PROVOKING_VTX_LAST } !+ 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } !+ ffffffff PC_RESTART_INDEX: 0xffffffff + 00000000 PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } !+ 00000001 UNKNOWN_21E6: 0x1 + 00000000 PC_HS_PARAM: { VERTICES_OUT = 0 | SPACING = EQUAL_SPACING } !+ 041a0001 VFD_CONTROL_0: { TOTALATTRTOVS = 1 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 1 | STRMFETCHINSTRCNT = 1 | 0xa0000 } !+ fcfc0081 VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } !+ fcfcfcfc VFD_CONTROL_2: 0xfcfcfcfc !+ 0000fc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } !+ 0000fcfc VFD_CONTROL_4: 0xfcfc + 00000000 VFD_INDEX_OFFSET: 0 + 00000000 UNKNOWN_2209: 0 !+ 00000003 VFD_FETCH[0].INSTR_0: { FETCHSIZE = 3 | BUFSTRIDE = 0 } !+ c01f0000 VFD_FETCH[0].INSTR_1: 0xc01f0000 0.000000 0.000000 0.000000 0.000000 0000: 00000000 00000000 00000000 00000000 !+ 00000010 VFD_FETCH[0].INSTR_2: { SIZE = 0x10 } !+ 00000001 VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } !+ 24000051 VFD_DECODE[0].INSTR: { WRITEMASK = 0x1 | CONSTFILL | FORMAT = VFMT4_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 4 | LASTCOMPVALID } !+ 00060010 SP_SP_CTRL_REG: { 0x60010 } !+ 000005ff SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x7f } !+ 00200400 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } !+ 00000002 SP_VS_CTRL_REG1: { CONSTLENGTH = 2 | INITIALOUTSTANDING = 0 } !+ 0000fc00 SP_VS_PARAM_REG: { POSREGID = r0.x | PSIZEREGID = r63.x | TOTALVSOUTVAR = 0 } + 00000000 SP_VS_OUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } !+ 00fcfc00 UNKNOWN_22D7: 0xfcfc00 + 00000000 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } !+ c01ac000 SP_VS_OBJ_START: 0xc01ac000 0000: 00000000 30445300 00000000 03000000 00000000 00000000 00000000 00000000 * 0000[30445300x_00000000x] (sy)(ss)(rpt3)mov.f32f32 r0.x, (0.000000) 0001[03000000x_00000000x] end Register Stats: - used (half): (cnt=0, max=0) - used (full): 0-3 (cnt=4, max=3) - input (half): (cnt=0, max=0) - input (full): (cnt=0, max=0) - const (half): (cnt=0, max=0) - const (full): (cnt=0, max=0) - output (half): (cnt=0, max=0) (estimated) - output (full): 0-3 (cnt=4, max=3) (estimated) + 00000000 SP_VS_PVT_MEM_PARAM: 0 + 00000000 SP_VS_PVT_MEM_ADDR: 0 + 00000000 0x22e4: 00000000 !+ 00000001 SP_VS_LENGTH_REG: 1 !+ 00340c00 SP_FS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE } !+ 80000003 SP_FS_CTRL_REG1: { CONSTLENGTH = 3 | 0x80000000 } !+ 7e020000 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } !+ c01aa000 SP_FS_OBJ_START: 0xc01aa000 0000: 00000003 30555000 00000700 20354001 00000000 20554002 00000704 20354003 0020: 00000020 20244b04 00006619 c6ea0008 00000000 00000100 02002610 d7260203 0040: 00000000 03000000 00000000 00000000 00000000 00000000 00000000 00000000 * 0000[30555000x_00000003x] (sy)(ss)mov.s32s32 r0.x, 3 0001[20354001x_00000700x] mov.s32s32 r0.y, c0.x 0002[20554002x_00000000x] mov.s32s32 r0.z, 0 0003[20354003x_00000704x] mov.s32s32 r0.w, c1.x 0004[20244b04x_00000020x] (rpt3)mov.f32f32 r1.x, (r)c8.x 0005[c6ea0008x_00006619x] ldgb.untyped.4d.s32.3 r2.x, g[0], r0.y, r0.x 0006[00000100x_00000000x] (rpt1)nop 0007[d7260203x_02002610x] (sy)stgb.untyped.4d.u32.3 g[1], r2.x, r0.z, r0.w 0008[03000000x_00000000x] end Register Stats: - used (half): (cnt=0, max=0) - used (full): 0-8 (cnt=9, max=8) - input (half): (cnt=0, max=0) - input (full): 8 (cnt=1, max=8) - const (half): (cnt=0, max=0) - const (full): 32-35 1792 1796 (cnt=6, max=1796) - output (half): (cnt=0, max=0) (estimated) - output (full): 4-7 (cnt=4, max=7) (estimated) + 00000000 SP_FS_PVT_MEM_PARAM: 0 + 00000000 SP_FS_PVT_MEM_ADDR: 0 + 00000000 0x22ee: 00000000 !+ 00000001 SP_FS_LENGTH_REG: 1 !+ fc00fc01 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r63.x } !+ 0001b004 SP_FS_MRT[0].REG: { REGID = r1.x | MRTFORMAT = 0x1b } !+ 00000004 SP_FS_MRT[0x1].REG: { REGID = r1.x | MRTFORMAT = 0 } !+ 00000004 SP_FS_MRT[0x2].REG: { REGID = r1.x | MRTFORMAT = 0 } !+ 00000004 SP_FS_MRT[0x3].REG: { REGID = r1.x | MRTFORMAT = 0 } !+ 00000004 SP_FS_MRT[0x4].REG: { REGID = r1.x | MRTFORMAT = 0 } !+ 00000004 SP_FS_MRT[0x5].REG: { REGID = r1.x | MRTFORMAT = 0 } !+ 00000004 SP_FS_MRT[0x6].REG: { REGID = r1.x | MRTFORMAT = 0 } !+ 00000004 SP_FS_MRT[0x7].REG: { REGID = r1.x | MRTFORMAT = 0 } + 00000000 0x230c: 00000000 !+ 7e020000 SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } + 00000000 SP_HS_OBJ_START: 0 + 00000000 SP_HS_PVT_MEM_PARAM: 0 + 00000000 SP_HS_PVT_MEM_ADDR: 0 + 00000000 0x2311: 00000000 + 00000000 0x2318: 00000000 + 00000000 0x2319: 00000000 + 00000000 SP_DS_PARAM_REG: { POSREGID = r0.x | TOTALGSOUTVAR = 0 } + 00000000 SP_DS_OUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_DS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_DS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_DS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_DS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_DS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_DS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_DS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_DS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_DS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_DS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_DS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_DS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_DS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_DS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_DS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 0x232b: 00000000 + 00000000 SP_DS_VPC_DST[0].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_DS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_DS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_DS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_DS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_DS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_DS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_DS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } + 00000000 SP_DS_OBJ_START: 0 + 00000000 SP_DS_PVT_MEM_PARAM: 0 + 00000000 SP_DS_PVT_MEM_ADDR: 0 + 00000000 0x2338: 00000000 + 00000000 0x2340: 00000000 !+ 7e020000 SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } + 00000000 SP_GS_OBJ_START: 0 + 00000000 SP_GS_PVT_MEM_PARAM: 0 + 00000000 SP_GS_PVT_MEM_ADDR: 0 + 00000000 0x235f: 00000000 !+ 00000808 TPL1_TP_TEX_OFFSET: 0x808 + 00000000 TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } + 00000000 0x2382: 00000000 + 00000000 TPL1_TP_FS_TEX_COUNT: 0 !+ 080004f0 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } !+ fcfc1128 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x1028 } !+ fff3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } !+ fcfcfcfc HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r63.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } !+ 00fcfcfc HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } !+ 01010002 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 2 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 1 } !+ 017f8203 HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 3 | CONSTOBJECTOFFSET = 2 | SSBO_ENABLE | ENABLED | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 } !+ 007e0200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } !+ 007e0200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } !+ 007e0200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } !+ 00000030 HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 48 | CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } !+ 00000007 HLSQ_UPDATE_CONTROL: 0x7 0000: c0023800 00200986 00000001 00000004 0000: c0013f00 c009f000 000001a0 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } count: 0 addr: 0000000000000000 0000: c0014300 00040000 00000000 ############################################################ vertices: 0 cmd: test_quad_flat:144: <<< eglSwapBuffers(display, surface): succeeded cmd: test_quad_flat:145: >>> glFlush() cmd: glFlush() cmd: test_quad_flat:145: <<< glFlush(): succeeded