MESA-INTEL: warning: Performance support disabled, consider sysctl dev.i915.perf_stream_paranoid=0 MESA-INTEL: warning: Performance support disabled, consider sysctl dev.i915.perf_stream_paranoid=0 MESA-INTEL: warning: Performance support disabled, consider sysctl dev.i915.perf_stream_paranoid=0 MESA-INTEL: warning: Performance support disabled, consider sysctl dev.i915.perf_stream_paranoid=0 NIR (from SPIR-V) for MESA_SHADER_COMPUTE shader: NIR (from SPIR-V) for MESA_SHADER_COMPUTE shader: shader: MESA_SHADER_COMPUTE shader: MESA_SHADER_COMPUTE local-size: 1, 1, 1 local-size: 1, 1, 1 shared-size: 0 shared-size: 0 inputs: 0 inputs: 0 outputs: 0 outputs: 0 uniforms: 0 uniforms: 0 shared: 0 shared: 0 decl_var system INTERP_MODE_NONE uvec3 @0 decl_var system INTERP_MODE_NONE uvec3 @0 decl_var system INTERP_MODE_NONE uvec3 @1 decl_var system INTERP_MODE_NONE uvec3 @1 decl_var system INTERP_MODE_NONE uint @2 decl_var system INTERP_MODE_NONE uint @2 decl_var ssbo INTERP_MODE_NONE restrict block @3 (~0, 0, 0) decl_var ssbo INTERP_MODE_NONE restrict block @3 (~0, 0, 0) decl_function main (0 params) decl_function main (0 params) impl main { impl main { decl_var INTERP_MODE_NONE uvec3 @4 decl_var INTERP_MODE_NONE uvec3 @4 decl_var INTERP_MODE_NONE uint @5 decl_var INTERP_MODE_NONE uint @5 decl_var INTERP_MODE_NONE uvec4 @6 decl_var INTERP_MODE_NONE uvec4 @6 decl_var INTERP_MODE_NONE uvec4 @7 decl_var INTERP_MODE_NONE uvec4 @7 decl_var INTERP_MODE_NONE uint @8 decl_var INTERP_MODE_NONE uint @8 decl_var INTERP_MODE_NONE uint @9 decl_var INTERP_MODE_NONE uint @9 decl_var INTERP_MODE_NONE uint @10 decl_var INTERP_MODE_NONE uint @10 decl_var INTERP_MODE_NONE uint @11 decl_var INTERP_MODE_NONE uint @11 decl_var INTERP_MODE_NONE uvec4 @12 decl_var INTERP_MODE_NONE uvec4 @12 decl_var INTERP_MODE_NONE int @13 decl_var INTERP_MODE_NONE int @13 decl_var INTERP_MODE_NONE int @14 decl_var INTERP_MODE_NONE int @14 decl_var INTERP_MODE_NONE uint @15 decl_var INTERP_MODE_NONE uint @15 decl_var INTERP_MODE_NONE int @16 decl_var INTERP_MODE_NONE int @16 decl_var INTERP_MODE_NONE uint @17 decl_var INTERP_MODE_NONE uint @17 decl_var INTERP_MODE_NONE int @18 decl_var INTERP_MODE_NONE int @18 decl_var INTERP_MODE_NONE uint @19 decl_var INTERP_MODE_NONE uint @19 decl_var INTERP_MODE_NONE uint @20 decl_var INTERP_MODE_NONE uint @20 decl_var INTERP_MODE_NONE bool cont decl_var INTERP_MODE_NONE bool cont block block_0: block block_0: /* preds: */ /* preds: */ vec1 32 ssa_217 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_217 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_208 = load_const (0xfffffff7 /* -nan */) vec1 32 ssa_208 = load_const (0xfffffff7 /* -nan */) vec1 32 ssa_189 = load_const (0xffffffff /* -nan */) vec1 32 ssa_189 = load_const (0xffffffff /* -nan */) vec1 32 ssa_184 = load_const (0x00000060 /* 0.000000 */) vec1 32 ssa_184 = load_const (0x00000060 /* 0.000000 */) vec1 32 ssa_180 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_180 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_178 = load_const (0x00000060 /* 0.000000 */) vec1 32 ssa_178 = load_const (0x00000060 /* 0.000000 */) vec1 32 ssa_174 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_174 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_172 = load_const (0x00000080 /* 0.000000 */) vec1 32 ssa_172 = load_const (0x00000080 /* 0.000000 */) vec1 32 ssa_164 = load_const (0xffffffff /* -nan */) vec1 32 ssa_164 = load_const (0xffffffff /* -nan */) vec1 32 ssa_159 = load_const (0x00000040 /* 0.000000 */) vec1 32 ssa_159 = load_const (0x00000040 /* 0.000000 */) vec1 32 ssa_155 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_155 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_153 = load_const (0x00000040 /* 0.000000 */) vec1 32 ssa_153 = load_const (0x00000040 /* 0.000000 */) vec1 32 ssa_149 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_149 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_147 = load_const (0x00000060 /* 0.000000 */) vec1 32 ssa_147 = load_const (0x00000060 /* 0.000000 */) vec1 32 ssa_139 = load_const (0xffffffff /* -nan */) vec1 32 ssa_139 = load_const (0xffffffff /* -nan */) vec1 32 ssa_134 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_134 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_130 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_130 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_128 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_128 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_124 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_124 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_122 = load_const (0x00000040 /* 0.000000 */) vec1 32 ssa_122 = load_const (0x00000040 /* 0.000000 */) vec1 32 ssa_114 = load_const (0xffffffff /* -nan */) vec1 32 ssa_114 = load_const (0xffffffff /* -nan */) vec1 32 ssa_110 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_110 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_108 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_108 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_95 = load_const (0x00000080 /* 0.000000 */) vec1 32 ssa_95 = load_const (0x00000080 /* 0.000000 */) vec1 32 ssa_91 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_91 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_88 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_88 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_79 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_79 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_78 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_78 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_76 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_76 = load_const (0x00000000 /* 0.000000 */) vec1 1 ssa_73 = load_const (true) vec1 1 ssa_73 = load_const (true) vec1 32 ssa_66 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_66 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_65 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_65 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_63 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_63 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_53 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_53 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_52 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_52 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_43 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_43 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_39 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_39 = load_const (0x00000000 /* 0.000000 */) vec4 32 ssa_37 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, vec4 32 ssa_37 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, vec4 32 ssa_35 = load_const (0xffffffff /* -nan */, 0xffffffff /* -nan */, 0xffffffff /* -nan */, 0xffffffff vec4 32 ssa_35 = load_const (0xffffffff /* -nan */, 0xffffffff /* -nan */, 0xffffffff /* -nan */, 0xffffffff vec3 32 ssa_2 = load_const (0x00000001 /* 0.000000 */, 0x00000001 /* 0.000000 */, 0x00000001 /* 0.000000 */) vec3 32 ssa_2 = load_const (0x00000001 /* 0.000000 */, 0x00000001 /* 0.000000 */, 0x00000001 /* 0.000000 */) vec1 32 ssa_0 = deref_var &@0 (system uvec3) vec1 32 ssa_0 = deref_var &@0 (system uvec3) vec3 32 ssa_1 = intrinsic load_deref (ssa_0) (0) /* access=0 */ vec3 32 ssa_1 = intrinsic load_deref (ssa_0) (0) /* access=0 */ vec3 32 ssa_3 = imul ssa_1, ssa_2 vec3 32 ssa_3 = imul ssa_1, ssa_2 vec1 32 ssa_4 = deref_var &@4 (function_temp uvec3) vec1 32 ssa_4 = deref_var &@4 (function_temp uvec3) intrinsic store_deref (ssa_4, ssa_3) (7, 0) /* wrmask=xyz */ /* access=0 */ intrinsic store_deref (ssa_4, ssa_3) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_5 = deref_var &@4 (function_temp uvec3) vec1 32 ssa_5 = deref_var &@4 (function_temp uvec3) vec3 32 ssa_8 = intrinsic load_deref (ssa_5) (0) /* access=0 */ vec3 32 ssa_8 = intrinsic load_deref (ssa_5) (0) /* access=0 */ vec1 32 ssa_9 = mov ssa_8.x vec1 32 ssa_9 = mov ssa_8.x vec1 32 ssa_10 = deref_var &@4 (function_temp uvec3) vec1 32 ssa_10 = deref_var &@4 (function_temp uvec3) vec3 32 ssa_13 = intrinsic load_deref (ssa_10) (0) /* access=0 */ vec3 32 ssa_13 = intrinsic load_deref (ssa_10) (0) /* access=0 */ vec1 32 ssa_14 = mov ssa_13.y vec1 32 ssa_14 = mov ssa_13.y vec1 32 ssa_15 = deref_var &@1 (system uvec3) vec1 32 ssa_15 = deref_var &@1 (system uvec3) vec3 32 ssa_18 = intrinsic load_deref (ssa_15) (0) /* access=0 */ vec3 32 ssa_18 = intrinsic load_deref (ssa_15) (0) /* access=0 */ vec1 32 ssa_19 = mov ssa_18.z vec1 32 ssa_19 = mov ssa_18.z vec1 32 ssa_20 = imul ssa_14, ssa_19 vec1 32 ssa_20 = imul ssa_14, ssa_19 vec1 32 ssa_21 = deref_var &@1 (system uvec3) vec1 32 ssa_21 = deref_var &@1 (system uvec3) vec3 32 ssa_24 = intrinsic load_deref (ssa_21) (0) /* access=0 */ vec3 32 ssa_24 = intrinsic load_deref (ssa_21) (0) /* access=0 */ vec1 32 ssa_25 = mov ssa_24.y vec1 32 ssa_25 = mov ssa_24.y vec1 32 ssa_26 = iadd ssa_20, ssa_25 vec1 32 ssa_26 = iadd ssa_20, ssa_25 vec1 32 ssa_27 = imul ssa_9, ssa_26 vec1 32 ssa_27 = imul ssa_9, ssa_26 vec1 32 ssa_28 = deref_var &@1 (system uvec3) vec1 32 ssa_28 = deref_var &@1 (system uvec3) vec3 32 ssa_31 = intrinsic load_deref (ssa_28) (0) /* access=0 */ vec3 32 ssa_31 = intrinsic load_deref (ssa_28) (0) /* access=0 */ vec1 32 ssa_32 = mov ssa_31.x vec1 32 ssa_32 = mov ssa_31.x vec1 32 ssa_33 = iadd ssa_27, ssa_32 vec1 32 ssa_33 = iadd ssa_27, ssa_32 vec1 32 ssa_34 = deref_var &@5 (function_temp uint) vec1 32 ssa_34 = deref_var &@5 (function_temp uint) intrinsic store_deref (ssa_34, ssa_33) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_34, ssa_33) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_36 = deref_var &@6 (function_temp uvec4) vec1 32 ssa_36 = deref_var &@6 (function_temp uvec4) intrinsic store_deref (ssa_36, ssa_35) (15, 0) /* wrmask=xyzw */ /* access=0 */ intrinsic store_deref (ssa_36, ssa_35) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_38 = deref_var &@7 (function_temp uvec4) vec1 32 ssa_38 = deref_var &@7 (function_temp uvec4) intrinsic store_deref (ssa_38, ssa_37) (15, 0) /* wrmask=xyzw */ /* access=0 */ intrinsic store_deref (ssa_38, ssa_37) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_40 = deref_var &@8 (function_temp uint) vec1 32 ssa_40 = deref_var &@8 (function_temp uint) intrinsic store_deref (ssa_40, ssa_39) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_40, ssa_39) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_41 = deref_var &@2 (system uint) vec1 32 ssa_41 = deref_var &@2 (system uint) vec1 32 ssa_42 = intrinsic load_deref (ssa_41) (0) /* access=0 */ vec1 32 ssa_42 = intrinsic load_deref (ssa_41) (0) /* access=0 */ vec1 32 ssa_44 = iadd ssa_42, ssa_43 vec1 32 ssa_44 = iadd ssa_42, ssa_43 vec1 32 ssa_45 = deref_var &@9 (function_temp uint) vec1 32 ssa_45 = deref_var &@9 (function_temp uint) intrinsic store_deref (ssa_45, ssa_44) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_45, ssa_44) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_46 = deref_var &@9 (function_temp uint) vec1 32 ssa_46 = deref_var &@9 (function_temp uint) vec1 32 ssa_47 = intrinsic load_deref (ssa_46) (0) /* access=0 */ vec1 32 ssa_47 = intrinsic load_deref (ssa_46) (0) /* access=0 */ vec1 32 ssa_48 = deref_var &@6 (function_temp uvec4) vec1 32 ssa_48 = deref_var &@6 (function_temp uvec4) vec4 32 ssa_49 = intrinsic load_deref (ssa_48) (0) /* access=0 */ vec4 32 ssa_49 = intrinsic load_deref (ssa_48) (0) /* access=0 */ vec1 32 ssa_50 = intrinsic ballot_bit_count_inclusive (ssa_49) () vec1 32 ssa_50 = intrinsic ballot_bit_count_inclusive (ssa_49) () vec1 1 ssa_51 = ieq ssa_47, ssa_50 vec1 1 ssa_51 = ieq ssa_47, ssa_50 vec1 32 ssa_54 = bcsel ssa_51, ssa_53, ssa_52 vec1 32 ssa_54 = bcsel ssa_51, ssa_53, ssa_52 vec1 32 ssa_55 = mov ssa_54 vec1 32 ssa_55 = mov ssa_54 vec1 32 ssa_56 = deref_var &@8 (function_temp uint) vec1 32 ssa_56 = deref_var &@8 (function_temp uint) vec1 32 ssa_57 = intrinsic load_deref (ssa_56) (0) /* access=0 */ vec1 32 ssa_57 = intrinsic load_deref (ssa_56) (0) /* access=0 */ vec1 32 ssa_58 = ior ssa_57, ssa_55 vec1 32 ssa_58 = ior ssa_57, ssa_55 vec1 32 ssa_59 = deref_var &@8 (function_temp uint) vec1 32 ssa_59 = deref_var &@8 (function_temp uint) intrinsic store_deref (ssa_59, ssa_58) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_59, ssa_58) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_60 = deref_var &@7 (function_temp uvec4) vec1 32 ssa_60 = deref_var &@7 (function_temp uvec4) vec4 32 ssa_61 = intrinsic load_deref (ssa_60) (0) /* access=0 */ vec4 32 ssa_61 = intrinsic load_deref (ssa_60) (0) /* access=0 */ vec1 32 ssa_62 = intrinsic ballot_bit_count_inclusive (ssa_61) () vec1 32 ssa_62 = intrinsic ballot_bit_count_inclusive (ssa_61) () vec1 1 ssa_64 = ieq ssa_63, ssa_62 vec1 1 ssa_64 = ieq ssa_63, ssa_62 vec1 32 ssa_67 = bcsel ssa_64, ssa_66, ssa_65 vec1 32 ssa_67 = bcsel ssa_64, ssa_66, ssa_65 vec1 32 ssa_68 = mov ssa_67 vec1 32 ssa_68 = mov ssa_67 vec1 32 ssa_69 = deref_var &@8 (function_temp uint) vec1 32 ssa_69 = deref_var &@8 (function_temp uint) vec1 32 ssa_70 = intrinsic load_deref (ssa_69) (0) /* access=0 */ vec1 32 ssa_70 = intrinsic load_deref (ssa_69) (0) /* access=0 */ vec1 32 ssa_71 = ior ssa_70, ssa_68 vec1 32 ssa_71 = ior ssa_70, ssa_68 vec1 32 ssa_72 = deref_var &@8 (function_temp uint) vec1 32 ssa_72 = deref_var &@8 (function_temp uint) intrinsic store_deref (ssa_72, ssa_71) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_72, ssa_71) (1, 0) /* wrmask=x */ /* access=0 */ vec4 32 ssa_74 = intrinsic ballot (ssa_73) () vec4 32 ssa_74 = intrinsic ballot (ssa_73) () vec1 32 ssa_75 = intrinsic ballot_bit_count_inclusive (ssa_74) () vec1 32 ssa_75 = intrinsic ballot_bit_count_inclusive (ssa_74) () vec1 1 ssa_77 = ult ssa_76, ssa_75 vec1 1 ssa_77 = ult ssa_76, ssa_75 vec1 32 ssa_80 = bcsel ssa_77, ssa_79, ssa_78 vec1 32 ssa_80 = bcsel ssa_77, ssa_79, ssa_78 vec1 32 ssa_81 = mov ssa_80 vec1 32 ssa_81 = mov ssa_80 vec1 32 ssa_82 = deref_var &@8 (function_temp uint) vec1 32 ssa_82 = deref_var &@8 (function_temp uint) vec1 32 ssa_83 = intrinsic load_deref (ssa_82) (0) /* access=0 */ vec1 32 ssa_83 = intrinsic load_deref (ssa_82) (0) /* access=0 */ vec1 32 ssa_84 = ior ssa_83, ssa_81 vec1 32 ssa_84 = ior ssa_83, ssa_81 vec1 32 ssa_85 = deref_var &@8 (function_temp uint) vec1 32 ssa_85 = deref_var &@8 (function_temp uint) intrinsic store_deref (ssa_85, ssa_84) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_85, ssa_84) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_86 = deref_var &@8 (function_temp uint) vec1 32 ssa_86 = deref_var &@8 (function_temp uint) vec1 32 ssa_87 = intrinsic load_deref (ssa_86) (0) /* access=0 */ vec1 32 ssa_87 = intrinsic load_deref (ssa_86) (0) /* access=0 */ vec1 32 ssa_89 = ior ssa_87, ssa_88 vec1 32 ssa_89 = ior ssa_87, ssa_88 vec1 32 ssa_90 = deref_var &@8 (function_temp uint) vec1 32 ssa_90 = deref_var &@8 (function_temp uint) intrinsic store_deref (ssa_90, ssa_89) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_90, ssa_89) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_92 = deref_var &@10 (function_temp uint) vec1 32 ssa_92 = deref_var &@10 (function_temp uint) intrinsic store_deref (ssa_92, ssa_91) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_92, ssa_91) (1, 0) /* wrmask=x */ /* access=0 */ vec1 1 ssa_211 = load_const (false) vec1 1 ssa_211 = load_const (false) vec1 32 ssa_212 = deref_var &cont (function_temp bool) vec1 32 ssa_212 = deref_var &cont (function_temp bool) intrinsic store_deref (ssa_212, ssa_211) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_212, ssa_211) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_1 */ /* succs: block_1 */ loop { loop { block block_1: block block_1: /* preds: block_0 block_29 block_31 */ /* preds: block_0 block_29 block_31 */ vec1 32 ssa_213 = deref_var &cont (function_temp bool) vec1 32 ssa_213 = deref_var &cont (function_temp bool) vec1 1 ssa_214 = intrinsic load_deref (ssa_213) (0) /* access=0 */ vec1 1 ssa_214 = intrinsic load_deref (ssa_213) (0) /* access=0 */ /* succs: block_2 block_3 */ /* succs: block_2 block_3 */ if ssa_214 { if ssa_214 { block block_2: block block_2: /* preds: block_1 */ /* preds: block_1 */ vec1 32 ssa_215 = deref_var &@10 (function_temp uint) vec1 32 ssa_215 = deref_var &@10 (function_temp uint) vec1 32 ssa_216 = intrinsic load_deref (ssa_215) (0) /* access=0 */ vec1 32 ssa_216 = intrinsic load_deref (ssa_215) (0) /* access=0 */ vec1 32 ssa_218 = iadd ssa_216, ssa_217 vec1 32 ssa_218 = iadd ssa_216, ssa_217 vec1 32 ssa_219 = deref_var &@10 (function_temp uint) vec1 32 ssa_219 = deref_var &@10 (function_temp uint) intrinsic store_deref (ssa_219, ssa_218) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_219, ssa_218) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_4 */ /* succs: block_4 */ } else { } else { block block_3: block block_3: /* preds: block_1 */ /* preds: block_1 */ /* succs: block_4 */ /* succs: block_4 */ } } block block_4: block block_4: /* preds: block_2 block_3 */ /* preds: block_2 block_3 */ vec1 1 ssa_220 = load_const (true) vec1 1 ssa_220 = load_const (true) vec1 32 ssa_221 = deref_var &cont (function_temp bool) vec1 32 ssa_221 = deref_var &cont (function_temp bool) intrinsic store_deref (ssa_221, ssa_220) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_221, ssa_220) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_93 = deref_var &@10 (function_temp uint) vec1 32 ssa_93 = deref_var &@10 (function_temp uint) vec1 32 ssa_94 = intrinsic load_deref (ssa_93) (0) /* access=0 */ vec1 32 ssa_94 = intrinsic load_deref (ssa_93) (0) /* access=0 */ vec1 1 ssa_96 = ult ssa_94, ssa_95 vec1 1 ssa_96 = ult ssa_94, ssa_95 /* succs: block_5 block_30 */ /* succs: block_5 block_30 */ if ssa_96 { if ssa_96 { block block_5: block block_5: /* preds: block_4 */ /* preds: block_4 */ vec1 32 ssa_97 = deref_var &@9 (function_temp uint) vec1 32 ssa_97 = deref_var &@9 (function_temp uint) vec1 32 ssa_98 = intrinsic load_deref (ssa_97) (0) /* access=0 */ vec1 32 ssa_98 = intrinsic load_deref (ssa_97) (0) /* access=0 */ vec1 32 ssa_99 = deref_var &@9 (function_temp uint) vec1 32 ssa_99 = deref_var &@9 (function_temp uint) vec1 32 ssa_100 = intrinsic load_deref (ssa_99) (0) /* access=0 */ vec1 32 ssa_100 = intrinsic load_deref (ssa_99) (0) /* access=0 */ vec1 32 ssa_101 = deref_var &@10 (function_temp uint) vec1 32 ssa_101 = deref_var &@10 (function_temp uint) vec1 32 ssa_102 = intrinsic load_deref (ssa_101) (0) /* access=0 */ vec1 32 ssa_102 = intrinsic load_deref (ssa_101) (0) /* access=0 */ vec1 32 ssa_103 = umin ssa_100, ssa_102 vec1 32 ssa_103 = umin ssa_100, ssa_102 vec1 32 ssa_104 = isub ssa_98, ssa_103 vec1 32 ssa_104 = isub ssa_98, ssa_103 vec1 32 ssa_105 = deref_var &@11 (function_temp uint) vec1 32 ssa_105 = deref_var &@11 (function_temp uint) intrinsic store_deref (ssa_105, ssa_104) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_105, ssa_104) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_106 = deref_var &@10 (function_temp uint) vec1 32 ssa_106 = deref_var &@10 (function_temp uint) vec1 32 ssa_107 = intrinsic load_deref (ssa_106) (0) /* access=0 */ vec1 32 ssa_107 = intrinsic load_deref (ssa_106) (0) /* access=0 */ vec1 1 ssa_109 = uge ssa_107, ssa_108 vec1 1 ssa_109 = uge ssa_107, ssa_108 /* succs: block_6 block_7 */ /* succs: block_6 block_7 */ if ssa_109 { if ssa_109 { block block_6: block block_6: /* preds: block_5 */ /* preds: block_5 */ vec1 32 ssa_111 = deref_var &@13 (function_temp int) vec1 32 ssa_111 = deref_var &@13 (function_temp int) intrinsic store_deref (ssa_111, ssa_110) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_111, ssa_110) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_8 */ /* succs: block_8 */ } else { } else { block block_7: block block_7: /* preds: block_5 */ /* preds: block_5 */ vec1 32 ssa_112 = deref_var &@10 (function_temp uint) vec1 32 ssa_112 = deref_var &@10 (function_temp uint) vec1 32 ssa_113 = intrinsic load_deref (ssa_112) (0) /* access=0 */ vec1 32 ssa_113 = intrinsic load_deref (ssa_112) (0) /* access=0 */ vec1 32 ssa_115 = ishl ssa_114, ssa_113 vec1 32 ssa_115 = ishl ssa_114, ssa_113 vec1 32 ssa_116 = deref_var &@13 (function_temp int) vec1 32 ssa_116 = deref_var &@13 (function_temp int) intrinsic store_deref (ssa_116, ssa_115) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_116, ssa_115) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_8 */ /* succs: block_8 */ } } block block_8: block block_8: /* preds: block_6 block_7 */ /* preds: block_6 block_7 */ vec1 32 ssa_117 = deref_var &@13 (function_temp int) vec1 32 ssa_117 = deref_var &@13 (function_temp int) vec1 32 ssa_118 = intrinsic load_deref (ssa_117) (0) /* access=0 */ vec1 32 ssa_118 = intrinsic load_deref (ssa_117) (0) /* access=0 */ vec1 32 ssa_119 = mov ssa_118 vec1 32 ssa_119 = mov ssa_118 vec1 32 ssa_120 = deref_var &@10 (function_temp uint) vec1 32 ssa_120 = deref_var &@10 (function_temp uint) vec1 32 ssa_121 = intrinsic load_deref (ssa_120) (0) /* access=0 */ vec1 32 ssa_121 = intrinsic load_deref (ssa_120) (0) /* access=0 */ vec1 1 ssa_123 = uge ssa_121, ssa_122 vec1 1 ssa_123 = uge ssa_121, ssa_122 /* succs: block_9 block_10 */ /* succs: block_9 block_10 */ if ssa_123 { if ssa_123 { block block_9: block block_9: /* preds: block_8 */ /* preds: block_8 */ vec1 32 ssa_125 = deref_var &@14 (function_temp int) vec1 32 ssa_125 = deref_var &@14 (function_temp int) intrinsic store_deref (ssa_125, ssa_124) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_125, ssa_124) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_14 */ /* succs: block_14 */ } else { } else { block block_10: block block_10: /* preds: block_8 */ /* preds: block_8 */ vec1 32 ssa_126 = deref_var &@10 (function_temp uint) vec1 32 ssa_126 = deref_var &@10 (function_temp uint) vec1 32 ssa_127 = intrinsic load_deref (ssa_126) (0) /* access=0 */ vec1 32 ssa_127 = intrinsic load_deref (ssa_126) (0) /* access=0 */ vec1 1 ssa_129 = ult ssa_127, ssa_128 vec1 1 ssa_129 = ult ssa_127, ssa_128 /* succs: block_11 block_12 */ /* succs: block_11 block_12 */ if ssa_129 { if ssa_129 { block block_11: block block_11: /* preds: block_10 */ /* preds: block_10 */ vec1 32 ssa_131 = deref_var &@15 (function_temp uint) vec1 32 ssa_131 = deref_var &@15 (function_temp uint) intrinsic store_deref (ssa_131, ssa_130) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_131, ssa_130) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_13 */ /* succs: block_13 */ } else { } else { block block_12: block block_12: /* preds: block_10 */ /* preds: block_10 */ vec1 32 ssa_132 = deref_var &@10 (function_temp uint) vec1 32 ssa_132 = deref_var &@10 (function_temp uint) vec1 32 ssa_133 = intrinsic load_deref (ssa_132) (0) /* access=0 */ vec1 32 ssa_133 = intrinsic load_deref (ssa_132) (0) /* access=0 */ vec1 32 ssa_135 = isub ssa_133, ssa_134 vec1 32 ssa_135 = isub ssa_133, ssa_134 vec1 32 ssa_136 = deref_var &@15 (function_temp uint) vec1 32 ssa_136 = deref_var &@15 (function_temp uint) intrinsic store_deref (ssa_136, ssa_135) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_136, ssa_135) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_13 */ /* succs: block_13 */ } } block block_13: block block_13: /* preds: block_11 block_12 */ /* preds: block_11 block_12 */ vec1 32 ssa_137 = deref_var &@15 (function_temp uint) vec1 32 ssa_137 = deref_var &@15 (function_temp uint) vec1 32 ssa_138 = intrinsic load_deref (ssa_137) (0) /* access=0 */ vec1 32 ssa_138 = intrinsic load_deref (ssa_137) (0) /* access=0 */ vec1 32 ssa_140 = ishl ssa_139, ssa_138 vec1 32 ssa_140 = ishl ssa_139, ssa_138 vec1 32 ssa_141 = deref_var &@14 (function_temp int) vec1 32 ssa_141 = deref_var &@14 (function_temp int) intrinsic store_deref (ssa_141, ssa_140) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_141, ssa_140) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_14 */ /* succs: block_14 */ } } block block_14: block block_14: /* preds: block_9 block_13 */ /* preds: block_9 block_13 */ vec1 32 ssa_142 = deref_var &@14 (function_temp int) vec1 32 ssa_142 = deref_var &@14 (function_temp int) vec1 32 ssa_143 = intrinsic load_deref (ssa_142) (0) /* access=0 */ vec1 32 ssa_143 = intrinsic load_deref (ssa_142) (0) /* access=0 */ vec1 32 ssa_144 = mov ssa_143 vec1 32 ssa_144 = mov ssa_143 vec1 32 ssa_145 = deref_var &@10 (function_temp uint) vec1 32 ssa_145 = deref_var &@10 (function_temp uint) vec1 32 ssa_146 = intrinsic load_deref (ssa_145) (0) /* access=0 */ vec1 32 ssa_146 = intrinsic load_deref (ssa_145) (0) /* access=0 */ vec1 1 ssa_148 = uge ssa_146, ssa_147 vec1 1 ssa_148 = uge ssa_146, ssa_147 /* succs: block_15 block_16 */ /* succs: block_15 block_16 */ if ssa_148 { if ssa_148 { block block_15: block block_15: /* preds: block_14 */ /* preds: block_14 */ vec1 32 ssa_150 = deref_var &@16 (function_temp int) vec1 32 ssa_150 = deref_var &@16 (function_temp int) intrinsic store_deref (ssa_150, ssa_149) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_150, ssa_149) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_20 */ /* succs: block_20 */ } else { } else { block block_16: block block_16: /* preds: block_14 */ /* preds: block_14 */ vec1 32 ssa_151 = deref_var &@10 (function_temp uint) vec1 32 ssa_151 = deref_var &@10 (function_temp uint) vec1 32 ssa_152 = intrinsic load_deref (ssa_151) (0) /* access=0 */ vec1 32 ssa_152 = intrinsic load_deref (ssa_151) (0) /* access=0 */ vec1 1 ssa_154 = ult ssa_152, ssa_153 vec1 1 ssa_154 = ult ssa_152, ssa_153 /* succs: block_17 block_18 */ /* succs: block_17 block_18 */ if ssa_154 { if ssa_154 { block block_17: block block_17: /* preds: block_16 */ /* preds: block_16 */ vec1 32 ssa_156 = deref_var &@17 (function_temp uint) vec1 32 ssa_156 = deref_var &@17 (function_temp uint) intrinsic store_deref (ssa_156, ssa_155) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_156, ssa_155) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_19 */ /* succs: block_19 */ } else { } else { block block_18: block block_18: /* preds: block_16 */ /* preds: block_16 */ vec1 32 ssa_157 = deref_var &@10 (function_temp uint) vec1 32 ssa_157 = deref_var &@10 (function_temp uint) vec1 32 ssa_158 = intrinsic load_deref (ssa_157) (0) /* access=0 */ vec1 32 ssa_158 = intrinsic load_deref (ssa_157) (0) /* access=0 */ vec1 32 ssa_160 = isub ssa_158, ssa_159 vec1 32 ssa_160 = isub ssa_158, ssa_159 vec1 32 ssa_161 = deref_var &@17 (function_temp uint) vec1 32 ssa_161 = deref_var &@17 (function_temp uint) intrinsic store_deref (ssa_161, ssa_160) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_161, ssa_160) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_19 */ /* succs: block_19 */ } } block block_19: block block_19: /* preds: block_17 block_18 */ /* preds: block_17 block_18 */ vec1 32 ssa_162 = deref_var &@17 (function_temp uint) vec1 32 ssa_162 = deref_var &@17 (function_temp uint) vec1 32 ssa_163 = intrinsic load_deref (ssa_162) (0) /* access=0 */ vec1 32 ssa_163 = intrinsic load_deref (ssa_162) (0) /* access=0 */ vec1 32 ssa_165 = ishl ssa_164, ssa_163 vec1 32 ssa_165 = ishl ssa_164, ssa_163 vec1 32 ssa_166 = deref_var &@16 (function_temp int) vec1 32 ssa_166 = deref_var &@16 (function_temp int) intrinsic store_deref (ssa_166, ssa_165) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_166, ssa_165) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_20 */ /* succs: block_20 */ } } block block_20: block block_20: /* preds: block_15 block_19 */ /* preds: block_15 block_19 */ vec1 32 ssa_167 = deref_var &@16 (function_temp int) vec1 32 ssa_167 = deref_var &@16 (function_temp int) vec1 32 ssa_168 = intrinsic load_deref (ssa_167) (0) /* access=0 */ vec1 32 ssa_168 = intrinsic load_deref (ssa_167) (0) /* access=0 */ vec1 32 ssa_169 = mov ssa_168 vec1 32 ssa_169 = mov ssa_168 vec1 32 ssa_170 = deref_var &@10 (function_temp uint) vec1 32 ssa_170 = deref_var &@10 (function_temp uint) vec1 32 ssa_171 = intrinsic load_deref (ssa_170) (0) /* access=0 */ vec1 32 ssa_171 = intrinsic load_deref (ssa_170) (0) /* access=0 */ vec1 1 ssa_173 = uge ssa_171, ssa_172 vec1 1 ssa_173 = uge ssa_171, ssa_172 /* succs: block_21 block_22 */ /* succs: block_21 block_22 */ if ssa_173 { if ssa_173 { block block_21: block block_21: /* preds: block_20 */ /* preds: block_20 */ vec1 32 ssa_175 = deref_var &@18 (function_temp int) vec1 32 ssa_175 = deref_var &@18 (function_temp int) intrinsic store_deref (ssa_175, ssa_174) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_175, ssa_174) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_26 */ /* succs: block_26 */ } else { } else { block block_22: block block_22: /* preds: block_20 */ /* preds: block_20 */ vec1 32 ssa_176 = deref_var &@10 (function_temp uint) vec1 32 ssa_176 = deref_var &@10 (function_temp uint) vec1 32 ssa_177 = intrinsic load_deref (ssa_176) (0) /* access=0 */ vec1 32 ssa_177 = intrinsic load_deref (ssa_176) (0) /* access=0 */ vec1 1 ssa_179 = ult ssa_177, ssa_178 vec1 1 ssa_179 = ult ssa_177, ssa_178 /* succs: block_23 block_24 */ /* succs: block_23 block_24 */ if ssa_179 { if ssa_179 { block block_23: block block_23: /* preds: block_22 */ /* preds: block_22 */ vec1 32 ssa_181 = deref_var &@19 (function_temp uint) vec1 32 ssa_181 = deref_var &@19 (function_temp uint) intrinsic store_deref (ssa_181, ssa_180) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_181, ssa_180) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_25 */ /* succs: block_25 */ } else { } else { block block_24: block block_24: /* preds: block_22 */ /* preds: block_22 */ vec1 32 ssa_182 = deref_var &@10 (function_temp uint) vec1 32 ssa_182 = deref_var &@10 (function_temp uint) vec1 32 ssa_183 = intrinsic load_deref (ssa_182) (0) /* access=0 */ vec1 32 ssa_183 = intrinsic load_deref (ssa_182) (0) /* access=0 */ vec1 32 ssa_185 = isub ssa_183, ssa_184 vec1 32 ssa_185 = isub ssa_183, ssa_184 vec1 32 ssa_186 = deref_var &@19 (function_temp uint) vec1 32 ssa_186 = deref_var &@19 (function_temp uint) intrinsic store_deref (ssa_186, ssa_185) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_186, ssa_185) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_25 */ /* succs: block_25 */ } } block block_25: block block_25: /* preds: block_23 block_24 */ /* preds: block_23 block_24 */ vec1 32 ssa_187 = deref_var &@19 (function_temp uint) vec1 32 ssa_187 = deref_var &@19 (function_temp uint) vec1 32 ssa_188 = intrinsic load_deref (ssa_187) (0) /* access=0 */ vec1 32 ssa_188 = intrinsic load_deref (ssa_187) (0) /* access=0 */ vec1 32 ssa_190 = ishl ssa_189, ssa_188 vec1 32 ssa_190 = ishl ssa_189, ssa_188 vec1 32 ssa_191 = deref_var &@18 (function_temp int) vec1 32 ssa_191 = deref_var &@18 (function_temp int) intrinsic store_deref (ssa_191, ssa_190) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_191, ssa_190) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_26 */ /* succs: block_26 */ } } block block_26: block block_26: /* preds: block_21 block_25 */ /* preds: block_21 block_25 */ vec1 32 ssa_192 = deref_var &@18 (function_temp int) vec1 32 ssa_192 = deref_var &@18 (function_temp int) vec1 32 ssa_193 = intrinsic load_deref (ssa_192) (0) /* access=0 */ vec1 32 ssa_193 = intrinsic load_deref (ssa_192) (0) /* access=0 */ vec1 32 ssa_194 = mov ssa_193 vec1 32 ssa_194 = mov ssa_193 vec4 32 ssa_195 = vec4 ssa_119, ssa_144, ssa_169, ssa_194 vec4 32 ssa_195 = vec4 ssa_119, ssa_144, ssa_169, ssa_194 vec1 32 ssa_196 = deref_var &@12 (function_temp uvec4) vec1 32 ssa_196 = deref_var &@12 (function_temp uvec4) intrinsic store_deref (ssa_196, ssa_195) (15, 0) /* wrmask=xyzw */ /* access=0 */ intrinsic store_deref (ssa_196, ssa_195) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_197 = deref_var &@12 (function_temp uvec4) vec1 32 ssa_197 = deref_var &@12 (function_temp uvec4) vec4 32 ssa_198 = intrinsic load_deref (ssa_197) (0) /* access=0 */ vec4 32 ssa_198 = intrinsic load_deref (ssa_197) (0) /* access=0 */ vec1 32 ssa_199 = intrinsic ballot_bit_count_inclusive (ssa_198) () vec1 32 ssa_199 = intrinsic ballot_bit_count_inclusive (ssa_198) () vec1 32 ssa_200 = deref_var &@20 (function_temp uint) vec1 32 ssa_200 = deref_var &@20 (function_temp uint) intrinsic store_deref (ssa_200, ssa_199) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_200, ssa_199) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_201 = deref_var &@20 (function_temp uint) vec1 32 ssa_201 = deref_var &@20 (function_temp uint) vec1 32 ssa_202 = intrinsic load_deref (ssa_201) (0) /* access=0 */ vec1 32 ssa_202 = intrinsic load_deref (ssa_201) (0) /* access=0 */ vec1 32 ssa_203 = deref_var &@11 (function_temp uint) vec1 32 ssa_203 = deref_var &@11 (function_temp uint) vec1 32 ssa_204 = intrinsic load_deref (ssa_203) (0) /* access=0 */ vec1 32 ssa_204 = intrinsic load_deref (ssa_203) (0) /* access=0 */ vec1 1 ssa_205 = ine ssa_202, ssa_204 vec1 1 ssa_205 = ine ssa_202, ssa_204 /* succs: block_27 block_28 */ /* succs: block_27 block_28 */ if ssa_205 { if ssa_205 { block block_27: block block_27: /* preds: block_26 */ /* preds: block_26 */ vec1 32 ssa_206 = deref_var &@8 (function_temp uint) vec1 32 ssa_206 = deref_var &@8 (function_temp uint) vec1 32 ssa_207 = intrinsic load_deref (ssa_206) (0) /* access=0 */ vec1 32 ssa_207 = intrinsic load_deref (ssa_206) (0) /* access=0 */ vec1 32 ssa_209 = iand ssa_207, ssa_208 vec1 32 ssa_209 = iand ssa_207, ssa_208 vec1 32 ssa_210 = deref_var &@8 (function_temp uint) vec1 32 ssa_210 = deref_var &@8 (function_temp uint) intrinsic store_deref (ssa_210, ssa_209) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_210, ssa_209) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_29 */ /* succs: block_29 */ } else { } else { block block_28: block block_28: /* preds: block_26 */ /* preds: block_26 */ /* succs: block_29 */ /* succs: block_29 */ } } block block_29: block block_29: /* preds: block_27 block_28 */ /* preds: block_27 block_28 */ continue continue /* succs: block_1 */ /* succs: block_1 */ } else { } else { block block_30: block block_30: /* preds: block_4 */ /* preds: block_4 */ break break /* succs: block_32 */ /* succs: block_32 */ } } block block_31: block block_31: /* preds: */ /* preds: */ /* succs: block_1 */ /* succs: block_1 */ } } block block_32: block block_32: /* preds: block_30 */ /* preds: block_30 */ vec1 32 ssa_222 = deref_var &@5 (function_temp uint) vec1 32 ssa_222 = deref_var &@5 (function_temp uint) vec1 32 ssa_223 = intrinsic load_deref (ssa_222) (0) /* access=0 */ vec1 32 ssa_223 = intrinsic load_deref (ssa_222) (0) /* access=0 */ vec1 32 ssa_224 = deref_var &@8 (function_temp uint) vec1 32 ssa_224 = deref_var &@8 (function_temp uint) vec1 32 ssa_225 = intrinsic load_deref (ssa_224) (0) /* access=0 */ vec1 32 ssa_225 = intrinsic load_deref (ssa_224) (0) /* access=0 */ vec1 32 ssa_226 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_226 = load_const (0x00000000 /* 0.000000 */) vec1 64 ssa_227 = intrinsic vulkan_resource_index (ssa_226) (0, 0, 7) /* desc-set=0 */ /* binding=0 */ /* des vec1 64 ssa_227 = intrinsic vulkan_resource_index (ssa_226) (0, 0, 7) /* desc-set=0 */ /* binding=0 */ /* des vec1 64 ssa_228 = intrinsic load_vulkan_descriptor (ssa_227) (7) /* desc_type=SSBO */ vec1 64 ssa_228 = intrinsic load_vulkan_descriptor (ssa_227) (7) /* desc_type=SSBO */ vec1 64 ssa_229 = deref_cast (block *)ssa_228 (ssbo block) /* ptr_stride=0, align_mul=0, align_offset=0 */ vec1 64 ssa_229 = deref_cast (block *)ssa_228 (ssbo block) /* ptr_stride=0, align_mul=0, align_offset=0 */ vec1 64 ssa_230 = deref_struct &ssa_229->field0 (ssbo uint[]) /* &((block *)ssa_228)->field0 */ vec1 64 ssa_230 = deref_struct &ssa_229->field0 (ssbo uint[]) /* &((block *)ssa_228)->field0 */ vec1 64 ssa_231 = i2i64 ssa_223 vec1 64 ssa_231 = i2i64 ssa_223 vec1 64 ssa_232 = deref_array &(*ssa_230)[ssa_231] (ssbo uint) /* &((block *)ssa_228)->field0[ssa_231] */ vec1 64 ssa_232 = deref_array &(*ssa_230)[ssa_231] (ssbo uint) /* &((block *)ssa_228)->field0[ssa_231] */ intrinsic store_deref (ssa_232, ssa_225) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_232, ssa_225) (1, 0) /* wrmask=x */ /* access=0 */ return return /* succs: block_33 */ /* succs: block_33 */ block block_33: block block_33: } } NIR (SSA form) for compute shader: NIR (SSA form) for compute shader: shader: MESA_SHADER_COMPUTE shader: MESA_SHADER_COMPUTE local-size: 1, 1, 1 local-size: 1, 1, 1 shared-size: 0 shared-size: 0 inputs: 0 inputs: 0 outputs: 0 outputs: 0 uniforms: 36 uniforms: 36 shared: 0 shared: 0 decl_var ssbo INTERP_MODE_NONE restrict block @0 (~0, 0, 0) decl_var ssbo INTERP_MODE_NONE restrict block @0 (~0, 0, 0) decl_function main (0 params) decl_function main (0 params) impl main { impl main { block block_0: block block_0: /* preds: */ /* preds: */ vec1 32 ssa_0 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_0 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_1 = load_const (0xfffffff7 /* -nan */) vec1 32 ssa_1 = load_const (0xfffffff7 /* -nan */) vec1 32 ssa_2 = load_const (0xffffffff /* -nan */) vec1 32 ssa_2 = load_const (0xffffffff /* -nan */) vec1 32 ssa_3 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_4 = load_const (0x00000080 /* 0.000000 */) vec1 32 ssa_4 = load_const (0x00000080 /* 0.000000 */) vec1 32 ssa_5 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_5 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_6 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_6 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_7 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_7 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_8 = load_const (0xffffffff /* -nan */) vec1 32 ssa_8 = load_const (0xffffffff /* -nan */) vec3 32 ssa_9 = intrinsic load_num_work_groups () () vec3 32 ssa_9 = intrinsic load_num_work_groups () () vec3 32 ssa_10 = intrinsic load_work_group_id () () vec3 32 ssa_10 = intrinsic load_work_group_id () () vec3 32 ssa_11 = intrinsic load_uniform (ssa_3) (24, 12, 0) /* base=24 */ /* range=12 */ /* dest_type=invalid vec3 32 ssa_11 = intrinsic load_uniform (ssa_3) (24, 12, 0) /* base=24 */ /* range=12 */ /* dest_type=invalid vec1 32 ssa_12 = iadd ssa_10.x, ssa_11.x vec1 32 ssa_12 = iadd ssa_10.x, ssa_11.x vec1 32 ssa_13 = iadd ssa_10.y, ssa_11.y vec1 32 ssa_13 = iadd ssa_10.y, ssa_11.y vec1 32 ssa_14 = iadd ssa_10.z, ssa_11.z vec1 32 ssa_14 = iadd ssa_10.z, ssa_11.z vec1 32 ssa_15 = intrinsic load_subgroup_invocation () () vec1 32 ssa_15 = intrinsic load_subgroup_invocation () () vec1 32 ssa_16 = iadd ssa_14, ssa_15 vec1 32 ssa_16 = iadd ssa_14, ssa_15 vec1 32 ssa_17 = imul ssa_9.y, ssa_16 vec1 32 ssa_17 = imul ssa_9.y, ssa_16 vec1 32 ssa_18 = iadd ssa_17, ssa_13 vec1 32 ssa_18 = iadd ssa_17, ssa_13 vec1 32 ssa_19 = imul ssa_9.x, ssa_18 vec1 32 ssa_19 = imul ssa_9.x, ssa_18 vec1 32 ssa_20 = iadd ssa_19, ssa_12 vec1 32 ssa_20 = iadd ssa_19, ssa_12 vec1 32 ssa_21 = iadd ssa_15, ssa_0 vec1 32 ssa_21 = iadd ssa_15, ssa_0 vec1 32 ssa_22 = load_const (0x0000001f /* 0.000000 */) vec1 32 ssa_22 = load_const (0x0000001f /* 0.000000 */) vec1 32 ssa_23 = ineg ssa_15 vec1 32 ssa_23 = ineg ssa_15 vec1 32 ssa_24 = iadd ssa_22, ssa_23 vec1 32 ssa_24 = iadd ssa_22, ssa_23 vec1 32 ssa_25 = ushr ssa_2, ssa_24 vec1 32 ssa_25 = ushr ssa_2, ssa_24 vec1 32 ssa_26 = bit_count ssa_25 vec1 32 ssa_26 = bit_count ssa_25 vec1 32 ssa_27 = ieq32 ssa_21, ssa_26 vec1 32 ssa_27 = ieq32 ssa_21, ssa_26 vec1 32 ssa_28 = b2i32 ssa_27 vec1 32 ssa_28 = b2i32 ssa_27 vec1 32 ssa_29 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_29 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_30 = ior ssa_28, ssa_29 vec1 32 ssa_30 = ior ssa_28, ssa_29 vec1 32 ssa_31 = intrinsic ballot (ssa_8) () vec1 32 ssa_31 = intrinsic ballot (ssa_8) () vec1 32 ssa_32 = iand ssa_31, ssa_25 vec1 32 ssa_32 = iand ssa_31, ssa_25 vec1 32 ssa_33 = bit_count ssa_32 vec1 32 ssa_33 = bit_count ssa_32 vec1 32 ssa_34 = ult32 ssa_3, ssa_33 vec1 32 ssa_34 = ult32 ssa_3, ssa_33 vec1 32 ssa_35 = b32csel ssa_34, ssa_7, ssa_3 vec1 32 ssa_35 = b32csel ssa_34, ssa_7, ssa_3 vec1 32 ssa_36 = ior ssa_30, ssa_35 vec1 32 ssa_36 = ior ssa_30, ssa_35 vec1 32 ssa_37 = ior ssa_36, ssa_6 vec1 32 ssa_37 = ior ssa_36, ssa_6 /* succs: block_1 */ /* succs: block_1 */ loop { loop { block block_1: block block_1: /* preds: block_0 block_4 */ /* preds: block_0 block_4 */ vec1 32 ssa_38 = phi block_0: ssa_37, block_4: ssa_51 vec1 32 ssa_38 = phi block_0: ssa_37, block_4: ssa_51 vec1 32 ssa_39 = phi block_0: ssa_3, block_4: ssa_52 vec1 32 ssa_39 = phi block_0: ssa_3, block_4: ssa_52 vec1 32 ssa_40 = uge32 ssa_39, ssa_4 vec1 32 ssa_40 = uge32 ssa_39, ssa_4 /* succs: block_2 block_3 */ /* succs: block_2 block_3 */ if ssa_40 { if ssa_40 { block block_2: block block_2: /* preds: block_1 */ /* preds: block_1 */ break break /* succs: block_5 */ /* succs: block_5 */ } else { } else { block block_3: block block_3: /* preds: block_1 */ /* preds: block_1 */ /* succs: block_4 */ /* succs: block_4 */ } } block block_4: block block_4: /* preds: block_3 */ /* preds: block_3 */ vec1 32 ssa_41 = umin ssa_21, ssa_39 vec1 32 ssa_41 = umin ssa_21, ssa_39 vec1 32 ssa_42 = ineg ssa_41 vec1 32 ssa_42 = ineg ssa_41 vec1 32 ssa_43 = iadd ssa_21, ssa_42 vec1 32 ssa_43 = iadd ssa_21, ssa_42 vec1 32 ssa_44 = ishl ssa_2, ssa_39 vec1 32 ssa_44 = ishl ssa_2, ssa_39 vec1 32 ssa_45 = uge32 ssa_39, ssa_5 vec1 32 ssa_45 = uge32 ssa_39, ssa_5 vec1 32 ssa_46 = b32csel ssa_45, ssa_3, ssa_44 vec1 32 ssa_46 = b32csel ssa_45, ssa_3, ssa_44 vec1 32 ssa_47 = iand ssa_46, ssa_25 vec1 32 ssa_47 = iand ssa_46, ssa_25 vec1 32 ssa_48 = bit_count ssa_47 vec1 32 ssa_48 = bit_count ssa_47 vec1 32 ssa_49 = iand ssa_38, ssa_1 vec1 32 ssa_49 = iand ssa_38, ssa_1 vec1 32 ssa_50 = ine32 ssa_48, ssa_43 vec1 32 ssa_50 = ine32 ssa_48, ssa_43 vec1 32 ssa_51 = b32csel ssa_50, ssa_49, ssa_38 vec1 32 ssa_51 = b32csel ssa_50, ssa_49, ssa_38 vec1 32 ssa_52 = iadd ssa_39, ssa_0 vec1 32 ssa_52 = iadd ssa_39, ssa_0 /* succs: block_1 */ /* succs: block_1 */ } } block block_5: block block_5: /* preds: block_2 */ /* preds: block_2 */ vec1 32 ssa_53 = ishl ssa_20, ssa_29 vec1 32 ssa_53 = ishl ssa_20, ssa_29 intrinsic store_ssbo (ssa_38, ssa_29, ssa_53) (1, 0, 4, 0) /* wrmask=x */ /* access=0 */ /* align_mul=4 */ /* intrinsic store_ssbo (ssa_38, ssa_29, ssa_53) (1, 0, 4, 0) /* wrmask=x */ /* access=0 */ /* align_mul=4 */ /* /* succs: block_6 */ /* succs: block_6 */ block block_6: block block_6: } } NIR (final form) for compute shader: NIR (final form) for compute shader: shader: MESA_SHADER_COMPUTE shader: MESA_SHADER_COMPUTE local-size: 1, 1, 1 local-size: 1, 1, 1 shared-size: 0 shared-size: 0 inputs: 0 inputs: 0 outputs: 0 outputs: 0 uniforms: 36 uniforms: 36 shared: 0 shared: 0 decl_var ssbo INTERP_MODE_NONE restrict block @0 (~0, 0, 0) decl_var ssbo INTERP_MODE_NONE restrict block @0 (~0, 0, 0) decl_function main (0 params) decl_function main (0 params) impl main { impl main { decl_reg vec1 32 r3 decl_reg vec1 32 r3 decl_reg vec1 32 r4 decl_reg vec1 32 r4 block block_0: block block_0: /* preds: */ /* preds: */ vec1 32 ssa_0 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_0 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_1 = load_const (0xfffffff7 /* -nan */) vec1 32 ssa_1 = load_const (0xfffffff7 /* -nan */) vec1 32 ssa_2 = load_const (0xffffffff /* -nan */) vec1 32 ssa_2 = load_const (0xffffffff /* -nan */) vec1 32 ssa_3 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_4 = load_const (0x00000080 /* 0.000000 */) vec1 32 ssa_4 = load_const (0x00000080 /* 0.000000 */) vec1 32 ssa_5 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_5 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_6 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_6 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_7 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_7 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_8 = load_const (0xffffffff /* -nan */) vec1 32 ssa_8 = load_const (0xffffffff /* -nan */) vec3 32 ssa_9 = intrinsic load_num_work_groups () () vec3 32 ssa_9 = intrinsic load_num_work_groups () () vec3 32 ssa_10 = intrinsic load_work_group_id () () vec3 32 ssa_10 = intrinsic load_work_group_id () () vec3 32 ssa_11 = intrinsic load_uniform (ssa_3) (24, 12, 0) /* base=24 */ /* range=12 */ /* dest_type=invalid vec3 32 ssa_11 = intrinsic load_uniform (ssa_3) (24, 12, 0) /* base=24 */ /* range=12 */ /* dest_type=invalid vec1 32 ssa_12 = iadd ssa_10.x, ssa_11.x vec1 32 ssa_12 = iadd ssa_10.x, ssa_11.x vec1 32 ssa_13 = iadd ssa_10.y, ssa_11.y vec1 32 ssa_13 = iadd ssa_10.y, ssa_11.y vec1 32 ssa_14 = iadd ssa_10.z, ssa_11.z vec1 32 ssa_14 = iadd ssa_10.z, ssa_11.z vec1 32 ssa_15 = intrinsic load_subgroup_invocation () () vec1 32 ssa_15 = intrinsic load_subgroup_invocation () () vec1 32 ssa_16 = iadd ssa_14, ssa_15 vec1 32 ssa_16 = iadd ssa_14, ssa_15 vec1 32 ssa_17 = imul ssa_9.y, ssa_16 vec1 32 ssa_17 = imul ssa_9.y, ssa_16 vec1 32 ssa_18 = iadd ssa_17, ssa_13 vec1 32 ssa_18 = iadd ssa_17, ssa_13 vec1 32 ssa_19 = imul ssa_9.x, ssa_18 vec1 32 ssa_19 = imul ssa_9.x, ssa_18 vec1 32 ssa_20 = iadd ssa_19, ssa_12 vec1 32 ssa_20 = iadd ssa_19, ssa_12 vec1 32 ssa_21 = iadd ssa_15, ssa_0 vec1 32 ssa_21 = iadd ssa_15, ssa_0 vec1 32 ssa_22 = load_const (0x0000001f /* 0.000000 */) vec1 32 ssa_22 = load_const (0x0000001f /* 0.000000 */) vec1 32 ssa_23 = ineg ssa_15 vec1 32 ssa_23 = ineg ssa_15 vec1 32 ssa_24 = iadd ssa_22, ssa_23 vec1 32 ssa_24 = iadd ssa_22, ssa_23 vec1 32 ssa_25 = ushr ssa_2, ssa_24 vec1 32 ssa_25 = ushr ssa_2, ssa_24 vec1 32 ssa_26 = bit_count ssa_25 vec1 32 ssa_26 = bit_count ssa_25 vec1 32 ssa_27 = ieq32 ssa_21, ssa_26 vec1 32 ssa_27 = ieq32 ssa_21, ssa_26 vec1 32 ssa_28 = b2i32 ssa_27 vec1 32 ssa_28 = b2i32 ssa_27 vec1 32 ssa_29 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_29 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_30 = ior ssa_28, ssa_29 vec1 32 ssa_30 = ior ssa_28, ssa_29 vec1 32 ssa_31 = intrinsic ballot (ssa_8) () vec1 32 ssa_31 = intrinsic ballot (ssa_8) () vec1 32 ssa_32 = iand ssa_31, ssa_25 vec1 32 ssa_32 = iand ssa_31, ssa_25 vec1 32 ssa_33 = bit_count ssa_32 vec1 32 ssa_33 = bit_count ssa_32 vec1 32 ssa_34 = ult32 ssa_3, ssa_33 vec1 32 ssa_34 = ult32 ssa_3, ssa_33 vec1 32 ssa_35 = b32csel ssa_34, ssa_7, ssa_3 vec1 32 ssa_35 = b32csel ssa_34, ssa_7, ssa_3 vec1 32 ssa_36 = ior ssa_30, ssa_35 vec1 32 ssa_36 = ior ssa_30, ssa_35 r3 = ior ssa_36, ssa_6 r3 = ior ssa_36, ssa_6 r4 = mov ssa_3 r4 = mov ssa_3 /* succs: block_1 */ /* succs: block_1 */ loop { loop { block block_1: block block_1: /* preds: block_0 block_4 */ /* preds: block_0 block_4 */ vec1 32 ssa_40 = uge32 r4, ssa_4 vec1 32 ssa_40 = uge32 r4, ssa_4 /* succs: block_2 block_3 */ /* succs: block_2 block_3 */ if ssa_40 { if ssa_40 { block block_2: block block_2: /* preds: block_1 */ /* preds: block_1 */ break break /* succs: block_5 */ /* succs: block_5 */ } else { } else { block block_3: block block_3: /* preds: block_1 */ /* preds: block_1 */ /* succs: block_4 */ /* succs: block_4 */ } } block block_4: block block_4: /* preds: block_3 */ /* preds: block_3 */ vec1 32 ssa_41 = umin ssa_21, r4 vec1 32 ssa_41 = umin ssa_21, r4 vec1 32 ssa_42 = ineg ssa_41 vec1 32 ssa_42 = ineg ssa_41 vec1 32 ssa_43 = iadd ssa_21, ssa_42 vec1 32 ssa_43 = iadd ssa_21, ssa_42 vec1 32 ssa_44 = ishl ssa_2, r4 vec1 32 ssa_44 = ishl ssa_2, r4 vec1 32 ssa_45 = uge32 r4, ssa_5 vec1 32 ssa_45 = uge32 r4, ssa_5 vec1 32 ssa_46 = b32csel ssa_45, ssa_3, ssa_44 vec1 32 ssa_46 = b32csel ssa_45, ssa_3, ssa_44 vec1 32 ssa_47 = iand ssa_46, ssa_25 vec1 32 ssa_47 = iand ssa_46, ssa_25 vec1 32 ssa_48 = bit_count ssa_47 vec1 32 ssa_48 = bit_count ssa_47 vec1 32 ssa_49 = iand r3, ssa_1 vec1 32 ssa_49 = iand r3, ssa_1 vec1 32 ssa_50 = ine32 ssa_48, ssa_43 vec1 32 ssa_50 = ine32 ssa_48, ssa_43 r3 = b32csel ssa_50, ssa_49, r3 r3 = b32csel ssa_50, ssa_49, r3 r4 = iadd r4, ssa_0 r4 = iadd r4, ssa_0 /* succs: block_1 */ /* succs: block_1 */ } } block block_5: block block_5: /* preds: block_2 */ /* preds: block_2 */ vec1 32 ssa_53 = ishl ssa_20, ssa_29 vec1 32 ssa_53 = ishl ssa_20, ssa_29 intrinsic store_ssbo (r3, ssa_29, ssa_53) (1, 0, 4, 0) /* wrmask=x */ /* access=0 */ /* align_mul=4 */ /* ali intrinsic store_ssbo (r3, ssa_29, ssa_53) (1, 0, 4, 0) /* wrmask=x */ /* access=0 */ /* align_mul=4 */ /* ali /* succs: block_6 */ /* succs: block_6 */ block block_6: block block_6: } } NIR (SSA form) for compute shader: NIR (SSA form) for compute shader: shader: MESA_SHADER_COMPUTE shader: MESA_SHADER_COMPUTE local-size: 1, 1, 1 local-size: 1, 1, 1 shared-size: 0 shared-size: 0 inputs: 0 inputs: 0 outputs: 0 outputs: 0 uniforms: 36 uniforms: 36 shared: 0 shared: 0 decl_var ssbo INTERP_MODE_NONE restrict block @0 (~0, 0, 0) decl_var ssbo INTERP_MODE_NONE restrict block @0 (~0, 0, 0) decl_function main (0 params) decl_function main (0 params) impl main { impl main { block block_0: block block_0: /* preds: */ /* preds: */ vec1 32 ssa_0 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_0 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_1 = load_const (0xfffffff7 /* -nan */) vec1 32 ssa_1 = load_const (0xfffffff7 /* -nan */) vec1 32 ssa_2 = load_const (0xffffffff /* -nan */) vec1 32 ssa_2 = load_const (0xffffffff /* -nan */) vec1 32 ssa_3 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_4 = load_const (0x00000080 /* 0.000000 */) vec1 32 ssa_4 = load_const (0x00000080 /* 0.000000 */) vec1 32 ssa_5 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_5 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_6 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_6 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_7 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_7 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_8 = load_const (0xffffffff /* -nan */) vec1 32 ssa_8 = load_const (0xffffffff /* -nan */) vec3 32 ssa_9 = intrinsic load_num_work_groups () () vec3 32 ssa_9 = intrinsic load_num_work_groups () () vec3 32 ssa_10 = intrinsic load_work_group_id () () vec3 32 ssa_10 = intrinsic load_work_group_id () () vec3 32 ssa_11 = intrinsic load_uniform (ssa_3) (24, 12, 0) /* base=24 */ /* range=12 */ /* dest_type=invalid vec3 32 ssa_11 = intrinsic load_uniform (ssa_3) (24, 12, 0) /* base=24 */ /* range=12 */ /* dest_type=invalid vec1 32 ssa_12 = iadd ssa_10.x, ssa_11.x vec1 32 ssa_12 = iadd ssa_10.x, ssa_11.x vec1 32 ssa_13 = iadd ssa_10.y, ssa_11.y vec1 32 ssa_13 = iadd ssa_10.y, ssa_11.y vec1 32 ssa_14 = iadd ssa_10.z, ssa_11.z vec1 32 ssa_14 = iadd ssa_10.z, ssa_11.z vec1 32 ssa_15 = intrinsic load_subgroup_invocation () () vec1 32 ssa_15 = intrinsic load_subgroup_invocation () () vec1 32 ssa_16 = iadd ssa_14, ssa_15 vec1 32 ssa_16 = iadd ssa_14, ssa_15 vec1 32 ssa_17 = imul ssa_9.y, ssa_16 vec1 32 ssa_17 = imul ssa_9.y, ssa_16 vec1 32 ssa_18 = iadd ssa_17, ssa_13 vec1 32 ssa_18 = iadd ssa_17, ssa_13 vec1 32 ssa_19 = imul ssa_9.x, ssa_18 vec1 32 ssa_19 = imul ssa_9.x, ssa_18 vec1 32 ssa_20 = iadd ssa_19, ssa_12 vec1 32 ssa_20 = iadd ssa_19, ssa_12 vec1 32 ssa_21 = iadd ssa_15, ssa_0 vec1 32 ssa_21 = iadd ssa_15, ssa_0 vec1 32 ssa_22 = load_const (0x0000001f /* 0.000000 */) vec1 32 ssa_22 = load_const (0x0000001f /* 0.000000 */) vec1 32 ssa_23 = ineg ssa_15 vec1 32 ssa_23 = ineg ssa_15 vec1 32 ssa_24 = iadd ssa_22, ssa_23 vec1 32 ssa_24 = iadd ssa_22, ssa_23 vec1 32 ssa_25 = ushr ssa_2, ssa_24 vec1 32 ssa_25 = ushr ssa_2, ssa_24 vec1 32 ssa_26 = bit_count ssa_25 vec1 32 ssa_26 = bit_count ssa_25 vec1 32 ssa_27 = ieq32 ssa_21, ssa_26 vec1 32 ssa_27 = ieq32 ssa_21, ssa_26 vec1 32 ssa_28 = b2i32 ssa_27 vec1 32 ssa_28 = b2i32 ssa_27 vec1 32 ssa_29 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_29 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_30 = ior ssa_28, ssa_29 vec1 32 ssa_30 = ior ssa_28, ssa_29 vec1 32 ssa_31 = intrinsic ballot (ssa_8) () vec1 32 ssa_31 = intrinsic ballot (ssa_8) () vec1 32 ssa_32 = iand ssa_31, ssa_25 vec1 32 ssa_32 = iand ssa_31, ssa_25 vec1 32 ssa_33 = bit_count ssa_32 vec1 32 ssa_33 = bit_count ssa_32 vec1 32 ssa_34 = ult32 ssa_3, ssa_33 vec1 32 ssa_34 = ult32 ssa_3, ssa_33 vec1 32 ssa_35 = b32csel ssa_34, ssa_7, ssa_3 vec1 32 ssa_35 = b32csel ssa_34, ssa_7, ssa_3 vec1 32 ssa_36 = ior ssa_30, ssa_35 vec1 32 ssa_36 = ior ssa_30, ssa_35 vec1 32 ssa_37 = ior ssa_36, ssa_6 vec1 32 ssa_37 = ior ssa_36, ssa_6 /* succs: block_1 */ /* succs: block_1 */ loop { loop { block block_1: block block_1: /* preds: block_0 block_4 */ /* preds: block_0 block_4 */ vec1 32 ssa_38 = phi block_0: ssa_37, block_4: ssa_51 vec1 32 ssa_38 = phi block_0: ssa_37, block_4: ssa_51 vec1 32 ssa_39 = phi block_0: ssa_3, block_4: ssa_52 vec1 32 ssa_39 = phi block_0: ssa_3, block_4: ssa_52 vec1 32 ssa_40 = uge32 ssa_39, ssa_4 vec1 32 ssa_40 = uge32 ssa_39, ssa_4 /* succs: block_2 block_3 */ /* succs: block_2 block_3 */ if ssa_40 { if ssa_40 { block block_2: block block_2: /* preds: block_1 */ /* preds: block_1 */ break break /* succs: block_5 */ /* succs: block_5 */ } else { } else { block block_3: block block_3: /* preds: block_1 */ /* preds: block_1 */ /* succs: block_4 */ /* succs: block_4 */ } } block block_4: block block_4: /* preds: block_3 */ /* preds: block_3 */ vec1 32 ssa_41 = umin ssa_21, ssa_39 vec1 32 ssa_41 = umin ssa_21, ssa_39 vec1 32 ssa_42 = ineg ssa_41 vec1 32 ssa_42 = ineg ssa_41 vec1 32 ssa_43 = iadd ssa_21, ssa_42 vec1 32 ssa_43 = iadd ssa_21, ssa_42 vec1 32 ssa_44 = ishl ssa_2, ssa_39 vec1 32 ssa_44 = ishl ssa_2, ssa_39 vec1 32 ssa_45 = uge32 ssa_39, ssa_5 vec1 32 ssa_45 = uge32 ssa_39, ssa_5 vec1 32 ssa_46 = b32csel ssa_45, ssa_3, ssa_44 vec1 32 ssa_46 = b32csel ssa_45, ssa_3, ssa_44 vec1 32 ssa_47 = iand ssa_46, ssa_25 vec1 32 ssa_47 = iand ssa_46, ssa_25 vec1 32 ssa_48 = bit_count ssa_47 vec1 32 ssa_48 = bit_count ssa_47 vec1 32 ssa_49 = iand ssa_38, ssa_1 vec1 32 ssa_49 = iand ssa_38, ssa_1 vec1 32 ssa_50 = ine32 ssa_48, ssa_43 vec1 32 ssa_50 = ine32 ssa_48, ssa_43 vec1 32 ssa_51 = b32csel ssa_50, ssa_49, ssa_38 vec1 32 ssa_51 = b32csel ssa_50, ssa_49, ssa_38 vec1 32 ssa_52 = iadd ssa_39, ssa_0 vec1 32 ssa_52 = iadd ssa_39, ssa_0 /* succs: block_1 */ /* succs: block_1 */ } } block block_5: block block_5: /* preds: block_2 */ /* preds: block_2 */ vec1 32 ssa_53 = ishl ssa_20, ssa_29 vec1 32 ssa_53 = ishl ssa_20, ssa_29 intrinsic store_ssbo (ssa_38, ssa_29, ssa_53) (1, 0, 4, 0) /* wrmask=x */ /* access=0 */ /* align_mul=4 */ /* intrinsic store_ssbo (ssa_38, ssa_29, ssa_53) (1, 0, 4, 0) /* wrmask=x */ /* access=0 */ /* align_mul=4 */ /* /* succs: block_6 */ /* succs: block_6 */ block block_6: block block_6: } } NIR (final form) for compute shader: NIR (final form) for compute shader: shader: MESA_SHADER_COMPUTE shader: MESA_SHADER_COMPUTE local-size: 1, 1, 1 local-size: 1, 1, 1 shared-size: 0 shared-size: 0 inputs: 0 inputs: 0 outputs: 0 outputs: 0 uniforms: 36 uniforms: 36 shared: 0 shared: 0 decl_var ssbo INTERP_MODE_NONE restrict block @0 (~0, 0, 0) decl_var ssbo INTERP_MODE_NONE restrict block @0 (~0, 0, 0) decl_function main (0 params) decl_function main (0 params) impl main { impl main { decl_reg vec1 32 r3 decl_reg vec1 32 r3 decl_reg vec1 32 r4 decl_reg vec1 32 r4 block block_0: block block_0: /* preds: */ /* preds: */ vec1 32 ssa_0 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_0 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_1 = load_const (0xfffffff7 /* -nan */) vec1 32 ssa_1 = load_const (0xfffffff7 /* -nan */) vec1 32 ssa_2 = load_const (0xffffffff /* -nan */) vec1 32 ssa_2 = load_const (0xffffffff /* -nan */) vec1 32 ssa_3 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_4 = load_const (0x00000080 /* 0.000000 */) vec1 32 ssa_4 = load_const (0x00000080 /* 0.000000 */) vec1 32 ssa_5 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_5 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_6 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_6 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_7 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_7 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_8 = load_const (0xffffffff /* -nan */) vec1 32 ssa_8 = load_const (0xffffffff /* -nan */) vec3 32 ssa_9 = intrinsic load_num_work_groups () () vec3 32 ssa_9 = intrinsic load_num_work_groups () () vec3 32 ssa_10 = intrinsic load_work_group_id () () vec3 32 ssa_10 = intrinsic load_work_group_id () () vec3 32 ssa_11 = intrinsic load_uniform (ssa_3) (24, 12, 0) /* base=24 */ /* range=12 */ /* dest_type=invalid vec3 32 ssa_11 = intrinsic load_uniform (ssa_3) (24, 12, 0) /* base=24 */ /* range=12 */ /* dest_type=invalid vec1 32 ssa_12 = iadd ssa_10.x, ssa_11.x vec1 32 ssa_12 = iadd ssa_10.x, ssa_11.x vec1 32 ssa_13 = iadd ssa_10.y, ssa_11.y vec1 32 ssa_13 = iadd ssa_10.y, ssa_11.y vec1 32 ssa_14 = iadd ssa_10.z, ssa_11.z vec1 32 ssa_14 = iadd ssa_10.z, ssa_11.z vec1 32 ssa_15 = intrinsic load_subgroup_invocation () () vec1 32 ssa_15 = intrinsic load_subgroup_invocation () () vec1 32 ssa_16 = iadd ssa_14, ssa_15 vec1 32 ssa_16 = iadd ssa_14, ssa_15 vec1 32 ssa_17 = imul ssa_9.y, ssa_16 vec1 32 ssa_17 = imul ssa_9.y, ssa_16 vec1 32 ssa_18 = iadd ssa_17, ssa_13 vec1 32 ssa_18 = iadd ssa_17, ssa_13 vec1 32 ssa_19 = imul ssa_9.x, ssa_18 vec1 32 ssa_19 = imul ssa_9.x, ssa_18 vec1 32 ssa_20 = iadd ssa_19, ssa_12 vec1 32 ssa_20 = iadd ssa_19, ssa_12 vec1 32 ssa_21 = iadd ssa_15, ssa_0 vec1 32 ssa_21 = iadd ssa_15, ssa_0 vec1 32 ssa_22 = load_const (0x0000001f /* 0.000000 */) vec1 32 ssa_22 = load_const (0x0000001f /* 0.000000 */) vec1 32 ssa_23 = ineg ssa_15 vec1 32 ssa_23 = ineg ssa_15 vec1 32 ssa_24 = iadd ssa_22, ssa_23 vec1 32 ssa_24 = iadd ssa_22, ssa_23 vec1 32 ssa_25 = ushr ssa_2, ssa_24 vec1 32 ssa_25 = ushr ssa_2, ssa_24 vec1 32 ssa_26 = bit_count ssa_25 vec1 32 ssa_26 = bit_count ssa_25 vec1 32 ssa_27 = ieq32 ssa_21, ssa_26 vec1 32 ssa_27 = ieq32 ssa_21, ssa_26 vec1 32 ssa_28 = b2i32 ssa_27 vec1 32 ssa_28 = b2i32 ssa_27 vec1 32 ssa_29 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_29 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_30 = ior ssa_28, ssa_29 vec1 32 ssa_30 = ior ssa_28, ssa_29 vec1 32 ssa_31 = intrinsic ballot (ssa_8) () vec1 32 ssa_31 = intrinsic ballot (ssa_8) () vec1 32 ssa_32 = iand ssa_31, ssa_25 vec1 32 ssa_32 = iand ssa_31, ssa_25 vec1 32 ssa_33 = bit_count ssa_32 vec1 32 ssa_33 = bit_count ssa_32 vec1 32 ssa_34 = ult32 ssa_3, ssa_33 vec1 32 ssa_34 = ult32 ssa_3, ssa_33 vec1 32 ssa_35 = b32csel ssa_34, ssa_7, ssa_3 vec1 32 ssa_35 = b32csel ssa_34, ssa_7, ssa_3 vec1 32 ssa_36 = ior ssa_30, ssa_35 vec1 32 ssa_36 = ior ssa_30, ssa_35 r3 = ior ssa_36, ssa_6 r3 = ior ssa_36, ssa_6 r4 = mov ssa_3 r4 = mov ssa_3 /* succs: block_1 */ /* succs: block_1 */ loop { loop { block block_1: block block_1: /* preds: block_0 block_4 */ /* preds: block_0 block_4 */ vec1 32 ssa_40 = uge32 r4, ssa_4 vec1 32 ssa_40 = uge32 r4, ssa_4 /* succs: block_2 block_3 */ /* succs: block_2 block_3 */ if ssa_40 { if ssa_40 { block block_2: block block_2: /* preds: block_1 */ /* preds: block_1 */ break break /* succs: block_5 */ /* succs: block_5 */ } else { } else { block block_3: block block_3: /* preds: block_1 */ /* preds: block_1 */ /* succs: block_4 */ /* succs: block_4 */ } } block block_4: block block_4: /* preds: block_3 */ /* preds: block_3 */ vec1 32 ssa_41 = umin ssa_21, r4 vec1 32 ssa_41 = umin ssa_21, r4 vec1 32 ssa_42 = ineg ssa_41 vec1 32 ssa_42 = ineg ssa_41 vec1 32 ssa_43 = iadd ssa_21, ssa_42 vec1 32 ssa_43 = iadd ssa_21, ssa_42 vec1 32 ssa_44 = ishl ssa_2, r4 vec1 32 ssa_44 = ishl ssa_2, r4 vec1 32 ssa_45 = uge32 r4, ssa_5 vec1 32 ssa_45 = uge32 r4, ssa_5 vec1 32 ssa_46 = b32csel ssa_45, ssa_3, ssa_44 vec1 32 ssa_46 = b32csel ssa_45, ssa_3, ssa_44 vec1 32 ssa_47 = iand ssa_46, ssa_25 vec1 32 ssa_47 = iand ssa_46, ssa_25 vec1 32 ssa_48 = bit_count ssa_47 vec1 32 ssa_48 = bit_count ssa_47 vec1 32 ssa_49 = iand r3, ssa_1 vec1 32 ssa_49 = iand r3, ssa_1 vec1 32 ssa_50 = ine32 ssa_48, ssa_43 vec1 32 ssa_50 = ine32 ssa_48, ssa_43 r3 = b32csel ssa_50, ssa_49, r3 r3 = b32csel ssa_50, ssa_49, r3 r4 = iadd r4, ssa_0 r4 = iadd r4, ssa_0 /* succs: block_1 */ /* succs: block_1 */ } } block block_5: block block_5: /* preds: block_2 */ /* preds: block_2 */ vec1 32 ssa_53 = ishl ssa_20, ssa_29 vec1 32 ssa_53 = ishl ssa_20, ssa_29 intrinsic store_ssbo (r3, ssa_29, ssa_53) (1, 0, 4, 0) /* wrmask=x */ /* access=0 */ /* align_mul=4 */ /* ali intrinsic store_ssbo (r3, ssa_29, ssa_53) (1, 0, 4, 0) /* wrmask=x */ /* access=0 */ /* align_mul=4 */ /* ali /* succs: block_6 */ /* succs: block_6 */ block block_6: block block_6: } } Native code for unnamed compute shader (null) (sha1 ca8721f44592afe487bd4f9601372203d9588d6a) | Native code for unnamed compute shader (null) (sha1 4dc08f08f4cbe7686e33eef89da3edbe92e8c0cd) SIMD16 shader: 60 instructions. 1 loops. 1706 cycles. 0:0 spills:fills, 3 sends, scheduled with mode top-down. Promot | SIMD16 shader: 59 instructions. 1 loops. 1622 cycles. 0:0 spills:fills, 3 sends, scheduled with mode top-down. Promot START B0 (356 cycles) | START B0 (352 cycles) mov(8) g3<1>UW 0x76543210V { align1 WE_all 1Q }; mov(8) g3<1>UW 0x76543210V { align1 WE_all 1Q }; mov(16) g69<1>UD g0.1<0,1,0>UD { align1 1H compacted }; | mov(16) g67<1>UD g0.1<0,1,0>UD { align1 1H compacted }; mov(16) g71<1>UD g0.6<0,1,0>UD { align1 1H }; | mov(16) g69<1>UD g0.6<0,1,0>UD { align1 1H }; mov(16) g4<1>UD g0.7<0,1,0>UD { align1 1H }; mov(16) g4<1>UD g0.7<0,1,0>UD { align1 1H }; mov(16) g6<1>UD 0xffffffffUD { align1 1H compacted }; mov(16) g6<1>UD 0xffffffffUD { align1 1H compacted }; mov(16) g8<1>UD 0xffffffffUD { align1 1H compacted }; | mov(16) g71<1>UD 0x00000000UD { align1 1H compacted }; mov(16) g73<1>UD 0x00000000UD { align1 1H compacted }; < add(8) g3.8<1>UW g3<8,8,1>UW 0x0008UW { align1 WE_all 1Q }; add(8) g3.8<1>UW g3<8,8,1>UW 0x0008UW { align1 WE_all 1Q }; send(16) g10<1>UW g73<0,1,0>UD 0x04605800 | send(16) g8<1>UW g71<0,1,0>UD 0x04605800 dp data 1 MsgDesc: ( untyped surface read, Surface = 0, SIMD16, Mask = 0x8) mlen 2 rlen 6 dp data 1 MsgDesc: ( untyped surface read, Surface = 0, SIMD16, Mask = 0x8) mlen 2 rlen 6 add(16) g16<1>D g69<8,8,1>D g1.6<0,1,0>D { align1 1H compacted }; | add(16) g14<1>D g67<8,8,1>D g1.6<0,1,0>D { align1 1H compacted }; add(16) g18<1>D g71<8,8,1>D g1.7<0,1,0>D { align1 1H compacted }; | add(16) g16<1>D g69<8,8,1>D g1.7<0,1,0>D { align1 1H compacted }; add(16) g20<1>D g4<8,8,1>D g2<0,1,0>D { align1 1H compacted }; | add(16) g18<1>D g4<8,8,1>D g2<0,1,0>D { align1 1H compacted }; mov(16) g22<1>D g3<8,8,1>UW { align1 1H }; | mov(16) g20<1>D g3<8,8,1>UW { align1 1H }; add(16) g24<1>D g20<8,8,1>D g22<8,8,1>D { align1 1H compacted }; | mov(1) g1.1<1>D 1D { align1 WE_all 1N }; add(16) g34<1>D g22<8,8,1>D 1D { align1 1H compacted }; | add(16) g22<1>D g18<8,8,1>D g20<8,8,1>D { align1 1H compacted }; add(16) g36<1>D -g22<8,8,1>D 31D { align1 1H compacted }; | add(16) g32<1>D g20<8,8,1>D 1D { align1 1H compacted }; mov(1) g4<2>UW 0x00000000UD { align1 WE_all 1N }; | add(16) g34<1>D -g20<8,8,1>D 31D { align1 1H compacted }; shr(16) g38<1>UD g6<8,8,1>UD g36<8,8,1>UD { align1 1H compacted }; | mov(1) g5<2>UW 0x00000000UD { align1 WE_all 1N }; cbit(16) g40<1>UD g38<8,8,1>UD { align1 1H compacted }; | shr(16) g36<1>D -g1.1<0,1,0>D g34<8,8,1>D { align1 1H compacted }; cmp.z.f0.0(16) g42<1>D g34<8,8,1>D g40<8,8,1>D { align1 1H compacted }; | cbit(16) g38<1>UD g36<8,8,1>UD { align1 1H compacted }; mov(16) g44<1>D -g42<8,8,1>D { align1 1H compacted }; | cmp.z.f0.0(16) g40<1>D g32<8,8,1>D g38<8,8,1>D { align1 1H compacted }; or(16) g46<1>UD g44<8,8,1>UD 0x00000002UD { align1 1H compacted }; | mov(16) g42<1>D -g40<8,8,1>D { align1 1H compacted }; mul(16) g26<1>D g12<8,8,1>D g24<16,8,2>UW { align1 1H }; | or(16) g44<1>UD g42<8,8,1>UD 0x00000002UD { align1 1H compacted }; mul(16) g1<1>D g12<8,8,1>D g24.1<16,8,2>UW { align1 1H }; | mul(16) g24<1>D g10<8,8,1>D g22<16,8,2>UW { align1 1H }; add(16) g26.1<2>UW g26.1<16,8,2>UW g1<16,8,2>UW { align1 1H }; | mul(16) g2<1>D g10<8,8,1>D g22.1<16,8,2>UW { align1 1H }; add(16) g28<1>D g26<8,8,1>D g18<8,8,1>D { align1 1H compacted }; | add(16) g24.1<2>UW g24.1<16,8,2>UW g2<16,8,2>UW { align1 1H }; mul(16) g30<1>D g10<8,8,1>D g28<16,8,2>UW { align1 1H }; | add(16) g26<1>D g24<8,8,1>D g16<8,8,1>D { align1 1H compacted }; mul(16) g2<1>D g10<8,8,1>D g28.1<16,8,2>UW { align1 1H }; | mul(16) g28<1>D g8<8,8,1>D g26<16,8,2>UW { align1 1H }; add(16) g30.1<2>UW g30.1<16,8,2>UW g2<16,8,2>UW { align1 1H }; | mul(16) g3<1>D g8<8,8,1>D g26.1<16,8,2>UW { align1 1H }; add(16) g32<1>D g30<8,8,1>D g16<8,8,1>D { align1 1H compacted }; | add(16) g28.1<2>UW g28.1<16,8,2>UW g3<16,8,2>UW { align1 1H }; mov(1) f0<1>UW g4<0,1,0>UW { align1 WE_all 1N }; | add(16) g30<1>D g28<8,8,1>D g14<8,8,1>D { align1 1H compacted }; cmp.nz.f0.0(16) null<1>UD g8<8,8,1>UD 0x00000000UD { align1 1H compacted }; | mov(1) f0<1>UW g5<0,1,0>UW { align1 WE_all 1N }; mov(16) g48<1>UD f0<0,1,0>UW { align1 1H }; | cmp.nz.f0.0(16) null<1>UD g6<8,8,1>UD 0x00000000UD { align1 1H compacted }; > mov(16) g46<1>UD f0<0,1,0>UW { align1 1H }; mov(1) g1<1>UD 0x00000000UD { align1 WE_all 1N compacted }; mov(1) g1<1>UD 0x00000000UD { align1 WE_all 1N compacted }; mov(16) g5<1>UD 0x00000000UD { align1 1H compacted }; mov(16) g5<1>UD 0x00000000UD { align1 1H compacted }; and(16) g50<1>UD g48<8,8,1>UD g38<8,8,1>UD { align1 1H compacted }; | and(16) g48<1>UD g46<8,8,1>UD g36<8,8,1>UD { align1 1H compacted }; cbit(16) g52<1>UD g50<8,8,1>UD { align1 1H compacted }; | cbit(16) g50<1>UD g48<8,8,1>UD { align1 1H compacted }; cmp.g.f0.0(16) null<1>UD g52<8,8,1>UD 0x00000000UD { align1 1H compacted }; | cmp.g.f0.0(16) null<1>UD g50<8,8,1>UD 0x00000000UD { align1 1H compacted }; (-f0.0) sel(16) g53<1>UD g1<0,1,0>UD 0x00000004UD { align1 1H }; | (-f0.0) sel(16) g51<1>UD g1<0,1,0>UD 0x00000004UD { align1 1H }; or(16) g55<1>UD g46<8,8,1>UD g53<8,8,1>UD { align1 1H compacted }; | or(16) g53<1>UD g44<8,8,1>UD g51<8,8,1>UD { align1 1H compacted }; or(16) g76<1>UD g55<8,8,1>UD 0x00000008UD { align1 1H compacted }; | or(16) g74<1>UD g53<8,8,1>UD 0x00000008UD { align1 1H compacted }; END B0 ->B1 END B0 ->B1 START B2 <-B1 <-B3 (260 cycles) START B2 <-B1 <-B3 (260 cycles) LABEL1: LABEL1: cmp.ge.f0.0(16) null<1>UD g5<8,8,1>UD 0x00000080UD { align1 1H compacted }; cmp.ge.f0.0(16) null<1>UD g5<8,8,1>UD 0x00000080UD { align1 1H compacted }; END B1 ->B2 ->B4 END B1 ->B2 ->B4 (+f0.0) break(16) JIP: LABEL0 UIP: LABEL0 { align1 1H }; (+f0.0) break(16) JIP: LABEL0 UIP: LABEL0 { align1 1H }; END B2 ->B1 ->B4 ->B3 END B2 ->B1 ->B4 ->B3 START B3 <-B2 (1060 cycles) | START B3 <-B2 (980 cycles) sel.l(16) g56<1>UD g34<8,8,1>UD g5<8,8,1>UD { align1 1H compacted }; | sel.l(16) g54<1>UD g32<8,8,1>UD g5<8,8,1>UD { align1 1H compacted }; mov(1) g1.1<1>D 1D { align1 WE_all 1N }; | shl(16) g58<1>D -g1.1<0,1,0>D g5<8,8,1>UD { align1 1H }; cmp.ge.f0.0(16) null<1>UD g5<8,8,1>UD 0x00000020UD { align1 1H compacted }; cmp.ge.f0.0(16) null<1>UD g5<8,8,1>UD 0x00000020UD { align1 1H compacted }; and(16) g68<1>UD g76<8,8,1>UD 0xfffffff7UD { align1 1H compacted }; | and(16) g66<1>UD g74<8,8,1>UD 0xfffffff7UD { align1 1H compacted }; add(16) g58<1>D g34<8,8,1>D -g56<8,8,1>D { align1 1H compacted }; < shl(16) g60<1>D -g1.1<0,1,0>D g5<8,8,1>UD { align1 1H }; < add(16) g5<1>D g5<8,8,1>D 1D { align1 1H compacted }; add(16) g5<1>D g5<8,8,1>D 1D { align1 1H compacted }; (-f0.0) sel(16) g62<1>UD g60<8,8,1>UD 0x00000000UD { align1 1H }; | add(16) g56<1>D g32<8,8,1>D -g54<8,8,1>D { align1 1H compacted }; and(16) g64<1>UD g62<8,8,1>UD g38<8,8,1>UD { align1 1H compacted }; | (-f0.0) sel(16) g60<1>UD g58<8,8,1>UD 0x00000000UD { align1 1H }; cbit(16) g66<1>UD g64<8,8,1>UD { align1 1H compacted }; | and(16) g62<1>UD g60<8,8,1>UD g36<8,8,1>UD { align1 1H compacted }; cmp.nz.f0.0(16) null<1>D g66<8,8,1>D g58<8,8,1>D { align1 1H compacted }; | cbit(16) g64<1>UD g62<8,8,1>UD { align1 1H compacted }; (+f0.0) sel(16) g76<1>UD g68<8,8,1>UD g76<8,8,1>UD { align1 1H compacted }; | cmp.nz.f0.0(16) null<1>D g64<8,8,1>D g56<8,8,1>D { align1 1H compacted }; > (+f0.0) sel(16) g74<1>UD g66<8,8,1>UD g74<8,8,1>UD { align1 1H compacted }; LABEL0: LABEL0: while(16) JIP: LABEL1 { align1 1H }; while(16) JIP: LABEL1 { align1 1H }; END B3 ->B2 END B3 ->B2 START B4 <-B1 <-B2 (30 cycles) START B4 <-B1 <-B2 (30 cycles) shl(16) g74<1>D g32<8,8,1>D 0x00000002UD { align1 1H }; | shl(16) g72<1>D g30<8,8,1>D 0x00000002UD { align1 1H }; sends(16) nullUD g74UD g76UD 0x04025e02 0x00000080 | sends(16) nullUD g72UD g74UD 0x04025e02 0x00000080 dp data 1 MsgDesc: ( DC untyped surface write, Surface = 2, SIMD16, Mask = 0xe) mlen 2 ex dp data 1 MsgDesc: ( DC untyped surface write, Surface = 2, SIMD16, Mask = 0xe) mlen 2 ex mov(8) g126<1>UD g0<8,8,1>UD { align1 WE_all 1Q compacted }; mov(8) g126<1>UD g0<8,8,1>UD { align1 WE_all 1Q compacted }; send(16) null<1>UW g126<8,8,1>UW 0x82000000 send(16) null<1>UW g126<8,8,1>UW 0x82000000 thread_spawner MsgDesc: mlen 1 rlen 0 { align1 WE_all 1H EOT }; thread_spawner MsgDesc: mlen 1 rlen 0 { align1 WE_all 1H EOT }; END B4 END B4 NIR (from SPIR-V) for MESA_SHADER_COMPUTE shader: NIR (from SPIR-V) for MESA_SHADER_COMPUTE shader: shader: MESA_SHADER_COMPUTE shader: MESA_SHADER_COMPUTE local-size: 32, 1, 1 local-size: 32, 1, 1 shared-size: 0 shared-size: 0 inputs: 0 inputs: 0 outputs: 0 outputs: 0 uniforms: 0 uniforms: 0 shared: 0 shared: 0 decl_var system INTERP_MODE_NONE uvec3 @0 decl_var system INTERP_MODE_NONE uvec3 @0 decl_var system INTERP_MODE_NONE uvec3 @1 decl_var system INTERP_MODE_NONE uvec3 @1 decl_var system INTERP_MODE_NONE uint @2 decl_var system INTERP_MODE_NONE uint @2 decl_var ssbo INTERP_MODE_NONE restrict block @3 (~0, 0, 0) decl_var ssbo INTERP_MODE_NONE restrict block @3 (~0, 0, 0) decl_function main (0 params) decl_function main (0 params) impl main { impl main { decl_var INTERP_MODE_NONE uvec3 @4 decl_var INTERP_MODE_NONE uvec3 @4 decl_var INTERP_MODE_NONE uint @5 decl_var INTERP_MODE_NONE uint @5 decl_var INTERP_MODE_NONE uvec4 @6 decl_var INTERP_MODE_NONE uvec4 @6 decl_var INTERP_MODE_NONE uvec4 @7 decl_var INTERP_MODE_NONE uvec4 @7 decl_var INTERP_MODE_NONE uint @8 decl_var INTERP_MODE_NONE uint @8 decl_var INTERP_MODE_NONE uint @9 decl_var INTERP_MODE_NONE uint @9 decl_var INTERP_MODE_NONE uint @10 decl_var INTERP_MODE_NONE uint @10 decl_var INTERP_MODE_NONE uint @11 decl_var INTERP_MODE_NONE uint @11 decl_var INTERP_MODE_NONE uvec4 @12 decl_var INTERP_MODE_NONE uvec4 @12 decl_var INTERP_MODE_NONE int @13 decl_var INTERP_MODE_NONE int @13 decl_var INTERP_MODE_NONE int @14 decl_var INTERP_MODE_NONE int @14 decl_var INTERP_MODE_NONE uint @15 decl_var INTERP_MODE_NONE uint @15 decl_var INTERP_MODE_NONE int @16 decl_var INTERP_MODE_NONE int @16 decl_var INTERP_MODE_NONE uint @17 decl_var INTERP_MODE_NONE uint @17 decl_var INTERP_MODE_NONE int @18 decl_var INTERP_MODE_NONE int @18 decl_var INTERP_MODE_NONE uint @19 decl_var INTERP_MODE_NONE uint @19 decl_var INTERP_MODE_NONE uint @20 decl_var INTERP_MODE_NONE uint @20 decl_var INTERP_MODE_NONE bool cont decl_var INTERP_MODE_NONE bool cont block block_0: block block_0: /* preds: */ /* preds: */ vec1 32 ssa_217 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_217 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_208 = load_const (0xfffffff7 /* -nan */) vec1 32 ssa_208 = load_const (0xfffffff7 /* -nan */) vec1 32 ssa_189 = load_const (0xffffffff /* -nan */) vec1 32 ssa_189 = load_const (0xffffffff /* -nan */) vec1 32 ssa_184 = load_const (0x00000060 /* 0.000000 */) vec1 32 ssa_184 = load_const (0x00000060 /* 0.000000 */) vec1 32 ssa_180 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_180 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_178 = load_const (0x00000060 /* 0.000000 */) vec1 32 ssa_178 = load_const (0x00000060 /* 0.000000 */) vec1 32 ssa_174 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_174 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_172 = load_const (0x00000080 /* 0.000000 */) vec1 32 ssa_172 = load_const (0x00000080 /* 0.000000 */) vec1 32 ssa_164 = load_const (0xffffffff /* -nan */) vec1 32 ssa_164 = load_const (0xffffffff /* -nan */) vec1 32 ssa_159 = load_const (0x00000040 /* 0.000000 */) vec1 32 ssa_159 = load_const (0x00000040 /* 0.000000 */) vec1 32 ssa_155 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_155 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_153 = load_const (0x00000040 /* 0.000000 */) vec1 32 ssa_153 = load_const (0x00000040 /* 0.000000 */) vec1 32 ssa_149 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_149 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_147 = load_const (0x00000060 /* 0.000000 */) vec1 32 ssa_147 = load_const (0x00000060 /* 0.000000 */) vec1 32 ssa_139 = load_const (0xffffffff /* -nan */) vec1 32 ssa_139 = load_const (0xffffffff /* -nan */) vec1 32 ssa_134 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_134 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_130 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_130 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_128 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_128 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_124 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_124 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_122 = load_const (0x00000040 /* 0.000000 */) vec1 32 ssa_122 = load_const (0x00000040 /* 0.000000 */) vec1 32 ssa_114 = load_const (0xffffffff /* -nan */) vec1 32 ssa_114 = load_const (0xffffffff /* -nan */) vec1 32 ssa_110 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_110 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_108 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_108 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_95 = load_const (0x00000080 /* 0.000000 */) vec1 32 ssa_95 = load_const (0x00000080 /* 0.000000 */) vec1 32 ssa_91 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_91 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_88 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_88 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_79 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_79 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_78 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_78 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_76 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_76 = load_const (0x00000000 /* 0.000000 */) vec1 1 ssa_73 = load_const (true) vec1 1 ssa_73 = load_const (true) vec1 32 ssa_66 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_66 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_65 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_65 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_63 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_63 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_53 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_53 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_52 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_52 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_43 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_43 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_39 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_39 = load_const (0x00000000 /* 0.000000 */) vec4 32 ssa_37 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, vec4 32 ssa_37 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, vec4 32 ssa_35 = load_const (0xffffffff /* -nan */, 0xffffffff /* -nan */, 0xffffffff /* -nan */, 0xffffffff vec4 32 ssa_35 = load_const (0xffffffff /* -nan */, 0xffffffff /* -nan */, 0xffffffff /* -nan */, 0xffffffff vec3 32 ssa_2 = load_const (0x00000020 /* 0.000000 */, 0x00000001 /* 0.000000 */, 0x00000001 /* 0.000000 */) vec3 32 ssa_2 = load_const (0x00000020 /* 0.000000 */, 0x00000001 /* 0.000000 */, 0x00000001 /* 0.000000 */) vec1 32 ssa_0 = deref_var &@0 (system uvec3) vec1 32 ssa_0 = deref_var &@0 (system uvec3) vec3 32 ssa_1 = intrinsic load_deref (ssa_0) (0) /* access=0 */ vec3 32 ssa_1 = intrinsic load_deref (ssa_0) (0) /* access=0 */ vec3 32 ssa_3 = imul ssa_1, ssa_2 vec3 32 ssa_3 = imul ssa_1, ssa_2 vec1 32 ssa_4 = deref_var &@4 (function_temp uvec3) vec1 32 ssa_4 = deref_var &@4 (function_temp uvec3) intrinsic store_deref (ssa_4, ssa_3) (7, 0) /* wrmask=xyz */ /* access=0 */ intrinsic store_deref (ssa_4, ssa_3) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_5 = deref_var &@4 (function_temp uvec3) vec1 32 ssa_5 = deref_var &@4 (function_temp uvec3) vec3 32 ssa_8 = intrinsic load_deref (ssa_5) (0) /* access=0 */ vec3 32 ssa_8 = intrinsic load_deref (ssa_5) (0) /* access=0 */ vec1 32 ssa_9 = mov ssa_8.x vec1 32 ssa_9 = mov ssa_8.x vec1 32 ssa_10 = deref_var &@4 (function_temp uvec3) vec1 32 ssa_10 = deref_var &@4 (function_temp uvec3) vec3 32 ssa_13 = intrinsic load_deref (ssa_10) (0) /* access=0 */ vec3 32 ssa_13 = intrinsic load_deref (ssa_10) (0) /* access=0 */ vec1 32 ssa_14 = mov ssa_13.y vec1 32 ssa_14 = mov ssa_13.y vec1 32 ssa_15 = deref_var &@1 (system uvec3) vec1 32 ssa_15 = deref_var &@1 (system uvec3) vec3 32 ssa_18 = intrinsic load_deref (ssa_15) (0) /* access=0 */ vec3 32 ssa_18 = intrinsic load_deref (ssa_15) (0) /* access=0 */ vec1 32 ssa_19 = mov ssa_18.z vec1 32 ssa_19 = mov ssa_18.z vec1 32 ssa_20 = imul ssa_14, ssa_19 vec1 32 ssa_20 = imul ssa_14, ssa_19 vec1 32 ssa_21 = deref_var &@1 (system uvec3) vec1 32 ssa_21 = deref_var &@1 (system uvec3) vec3 32 ssa_24 = intrinsic load_deref (ssa_21) (0) /* access=0 */ vec3 32 ssa_24 = intrinsic load_deref (ssa_21) (0) /* access=0 */ vec1 32 ssa_25 = mov ssa_24.y vec1 32 ssa_25 = mov ssa_24.y vec1 32 ssa_26 = iadd ssa_20, ssa_25 vec1 32 ssa_26 = iadd ssa_20, ssa_25 vec1 32 ssa_27 = imul ssa_9, ssa_26 vec1 32 ssa_27 = imul ssa_9, ssa_26 vec1 32 ssa_28 = deref_var &@1 (system uvec3) vec1 32 ssa_28 = deref_var &@1 (system uvec3) vec3 32 ssa_31 = intrinsic load_deref (ssa_28) (0) /* access=0 */ vec3 32 ssa_31 = intrinsic load_deref (ssa_28) (0) /* access=0 */ vec1 32 ssa_32 = mov ssa_31.x vec1 32 ssa_32 = mov ssa_31.x vec1 32 ssa_33 = iadd ssa_27, ssa_32 vec1 32 ssa_33 = iadd ssa_27, ssa_32 vec1 32 ssa_34 = deref_var &@5 (function_temp uint) vec1 32 ssa_34 = deref_var &@5 (function_temp uint) intrinsic store_deref (ssa_34, ssa_33) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_34, ssa_33) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_36 = deref_var &@6 (function_temp uvec4) vec1 32 ssa_36 = deref_var &@6 (function_temp uvec4) intrinsic store_deref (ssa_36, ssa_35) (15, 0) /* wrmask=xyzw */ /* access=0 */ intrinsic store_deref (ssa_36, ssa_35) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_38 = deref_var &@7 (function_temp uvec4) vec1 32 ssa_38 = deref_var &@7 (function_temp uvec4) intrinsic store_deref (ssa_38, ssa_37) (15, 0) /* wrmask=xyzw */ /* access=0 */ intrinsic store_deref (ssa_38, ssa_37) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_40 = deref_var &@8 (function_temp uint) vec1 32 ssa_40 = deref_var &@8 (function_temp uint) intrinsic store_deref (ssa_40, ssa_39) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_40, ssa_39) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_41 = deref_var &@2 (system uint) vec1 32 ssa_41 = deref_var &@2 (system uint) vec1 32 ssa_42 = intrinsic load_deref (ssa_41) (0) /* access=0 */ vec1 32 ssa_42 = intrinsic load_deref (ssa_41) (0) /* access=0 */ vec1 32 ssa_44 = iadd ssa_42, ssa_43 vec1 32 ssa_44 = iadd ssa_42, ssa_43 vec1 32 ssa_45 = deref_var &@9 (function_temp uint) vec1 32 ssa_45 = deref_var &@9 (function_temp uint) intrinsic store_deref (ssa_45, ssa_44) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_45, ssa_44) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_46 = deref_var &@9 (function_temp uint) vec1 32 ssa_46 = deref_var &@9 (function_temp uint) vec1 32 ssa_47 = intrinsic load_deref (ssa_46) (0) /* access=0 */ vec1 32 ssa_47 = intrinsic load_deref (ssa_46) (0) /* access=0 */ vec1 32 ssa_48 = deref_var &@6 (function_temp uvec4) vec1 32 ssa_48 = deref_var &@6 (function_temp uvec4) vec4 32 ssa_49 = intrinsic load_deref (ssa_48) (0) /* access=0 */ vec4 32 ssa_49 = intrinsic load_deref (ssa_48) (0) /* access=0 */ vec1 32 ssa_50 = intrinsic ballot_bit_count_inclusive (ssa_49) () vec1 32 ssa_50 = intrinsic ballot_bit_count_inclusive (ssa_49) () vec1 1 ssa_51 = ieq ssa_47, ssa_50 vec1 1 ssa_51 = ieq ssa_47, ssa_50 vec1 32 ssa_54 = bcsel ssa_51, ssa_53, ssa_52 vec1 32 ssa_54 = bcsel ssa_51, ssa_53, ssa_52 vec1 32 ssa_55 = mov ssa_54 vec1 32 ssa_55 = mov ssa_54 vec1 32 ssa_56 = deref_var &@8 (function_temp uint) vec1 32 ssa_56 = deref_var &@8 (function_temp uint) vec1 32 ssa_57 = intrinsic load_deref (ssa_56) (0) /* access=0 */ vec1 32 ssa_57 = intrinsic load_deref (ssa_56) (0) /* access=0 */ vec1 32 ssa_58 = ior ssa_57, ssa_55 vec1 32 ssa_58 = ior ssa_57, ssa_55 vec1 32 ssa_59 = deref_var &@8 (function_temp uint) vec1 32 ssa_59 = deref_var &@8 (function_temp uint) intrinsic store_deref (ssa_59, ssa_58) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_59, ssa_58) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_60 = deref_var &@7 (function_temp uvec4) vec1 32 ssa_60 = deref_var &@7 (function_temp uvec4) vec4 32 ssa_61 = intrinsic load_deref (ssa_60) (0) /* access=0 */ vec4 32 ssa_61 = intrinsic load_deref (ssa_60) (0) /* access=0 */ vec1 32 ssa_62 = intrinsic ballot_bit_count_inclusive (ssa_61) () vec1 32 ssa_62 = intrinsic ballot_bit_count_inclusive (ssa_61) () vec1 1 ssa_64 = ieq ssa_63, ssa_62 vec1 1 ssa_64 = ieq ssa_63, ssa_62 vec1 32 ssa_67 = bcsel ssa_64, ssa_66, ssa_65 vec1 32 ssa_67 = bcsel ssa_64, ssa_66, ssa_65 vec1 32 ssa_68 = mov ssa_67 vec1 32 ssa_68 = mov ssa_67 vec1 32 ssa_69 = deref_var &@8 (function_temp uint) vec1 32 ssa_69 = deref_var &@8 (function_temp uint) vec1 32 ssa_70 = intrinsic load_deref (ssa_69) (0) /* access=0 */ vec1 32 ssa_70 = intrinsic load_deref (ssa_69) (0) /* access=0 */ vec1 32 ssa_71 = ior ssa_70, ssa_68 vec1 32 ssa_71 = ior ssa_70, ssa_68 vec1 32 ssa_72 = deref_var &@8 (function_temp uint) vec1 32 ssa_72 = deref_var &@8 (function_temp uint) intrinsic store_deref (ssa_72, ssa_71) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_72, ssa_71) (1, 0) /* wrmask=x */ /* access=0 */ vec4 32 ssa_74 = intrinsic ballot (ssa_73) () vec4 32 ssa_74 = intrinsic ballot (ssa_73) () vec1 32 ssa_75 = intrinsic ballot_bit_count_inclusive (ssa_74) () vec1 32 ssa_75 = intrinsic ballot_bit_count_inclusive (ssa_74) () vec1 1 ssa_77 = ult ssa_76, ssa_75 vec1 1 ssa_77 = ult ssa_76, ssa_75 vec1 32 ssa_80 = bcsel ssa_77, ssa_79, ssa_78 vec1 32 ssa_80 = bcsel ssa_77, ssa_79, ssa_78 vec1 32 ssa_81 = mov ssa_80 vec1 32 ssa_81 = mov ssa_80 vec1 32 ssa_82 = deref_var &@8 (function_temp uint) vec1 32 ssa_82 = deref_var &@8 (function_temp uint) vec1 32 ssa_83 = intrinsic load_deref (ssa_82) (0) /* access=0 */ vec1 32 ssa_83 = intrinsic load_deref (ssa_82) (0) /* access=0 */ vec1 32 ssa_84 = ior ssa_83, ssa_81 vec1 32 ssa_84 = ior ssa_83, ssa_81 vec1 32 ssa_85 = deref_var &@8 (function_temp uint) vec1 32 ssa_85 = deref_var &@8 (function_temp uint) intrinsic store_deref (ssa_85, ssa_84) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_85, ssa_84) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_86 = deref_var &@8 (function_temp uint) vec1 32 ssa_86 = deref_var &@8 (function_temp uint) vec1 32 ssa_87 = intrinsic load_deref (ssa_86) (0) /* access=0 */ vec1 32 ssa_87 = intrinsic load_deref (ssa_86) (0) /* access=0 */ vec1 32 ssa_89 = ior ssa_87, ssa_88 vec1 32 ssa_89 = ior ssa_87, ssa_88 vec1 32 ssa_90 = deref_var &@8 (function_temp uint) vec1 32 ssa_90 = deref_var &@8 (function_temp uint) intrinsic store_deref (ssa_90, ssa_89) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_90, ssa_89) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_92 = deref_var &@10 (function_temp uint) vec1 32 ssa_92 = deref_var &@10 (function_temp uint) intrinsic store_deref (ssa_92, ssa_91) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_92, ssa_91) (1, 0) /* wrmask=x */ /* access=0 */ vec1 1 ssa_211 = load_const (false) vec1 1 ssa_211 = load_const (false) vec1 32 ssa_212 = deref_var &cont (function_temp bool) vec1 32 ssa_212 = deref_var &cont (function_temp bool) intrinsic store_deref (ssa_212, ssa_211) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_212, ssa_211) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_1 */ /* succs: block_1 */ loop { loop { block block_1: block block_1: /* preds: block_0 block_29 block_31 */ /* preds: block_0 block_29 block_31 */ vec1 32 ssa_213 = deref_var &cont (function_temp bool) vec1 32 ssa_213 = deref_var &cont (function_temp bool) vec1 1 ssa_214 = intrinsic load_deref (ssa_213) (0) /* access=0 */ vec1 1 ssa_214 = intrinsic load_deref (ssa_213) (0) /* access=0 */ /* succs: block_2 block_3 */ /* succs: block_2 block_3 */ if ssa_214 { if ssa_214 { block block_2: block block_2: /* preds: block_1 */ /* preds: block_1 */ vec1 32 ssa_215 = deref_var &@10 (function_temp uint) vec1 32 ssa_215 = deref_var &@10 (function_temp uint) vec1 32 ssa_216 = intrinsic load_deref (ssa_215) (0) /* access=0 */ vec1 32 ssa_216 = intrinsic load_deref (ssa_215) (0) /* access=0 */ vec1 32 ssa_218 = iadd ssa_216, ssa_217 vec1 32 ssa_218 = iadd ssa_216, ssa_217 vec1 32 ssa_219 = deref_var &@10 (function_temp uint) vec1 32 ssa_219 = deref_var &@10 (function_temp uint) intrinsic store_deref (ssa_219, ssa_218) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_219, ssa_218) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_4 */ /* succs: block_4 */ } else { } else { block block_3: block block_3: /* preds: block_1 */ /* preds: block_1 */ /* succs: block_4 */ /* succs: block_4 */ } } block block_4: block block_4: /* preds: block_2 block_3 */ /* preds: block_2 block_3 */ vec1 1 ssa_220 = load_const (true) vec1 1 ssa_220 = load_const (true) vec1 32 ssa_221 = deref_var &cont (function_temp bool) vec1 32 ssa_221 = deref_var &cont (function_temp bool) intrinsic store_deref (ssa_221, ssa_220) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_221, ssa_220) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_93 = deref_var &@10 (function_temp uint) vec1 32 ssa_93 = deref_var &@10 (function_temp uint) vec1 32 ssa_94 = intrinsic load_deref (ssa_93) (0) /* access=0 */ vec1 32 ssa_94 = intrinsic load_deref (ssa_93) (0) /* access=0 */ vec1 1 ssa_96 = ult ssa_94, ssa_95 vec1 1 ssa_96 = ult ssa_94, ssa_95 /* succs: block_5 block_30 */ /* succs: block_5 block_30 */ if ssa_96 { if ssa_96 { block block_5: block block_5: /* preds: block_4 */ /* preds: block_4 */ vec1 32 ssa_97 = deref_var &@9 (function_temp uint) vec1 32 ssa_97 = deref_var &@9 (function_temp uint) vec1 32 ssa_98 = intrinsic load_deref (ssa_97) (0) /* access=0 */ vec1 32 ssa_98 = intrinsic load_deref (ssa_97) (0) /* access=0 */ vec1 32 ssa_99 = deref_var &@9 (function_temp uint) vec1 32 ssa_99 = deref_var &@9 (function_temp uint) vec1 32 ssa_100 = intrinsic load_deref (ssa_99) (0) /* access=0 */ vec1 32 ssa_100 = intrinsic load_deref (ssa_99) (0) /* access=0 */ vec1 32 ssa_101 = deref_var &@10 (function_temp uint) vec1 32 ssa_101 = deref_var &@10 (function_temp uint) vec1 32 ssa_102 = intrinsic load_deref (ssa_101) (0) /* access=0 */ vec1 32 ssa_102 = intrinsic load_deref (ssa_101) (0) /* access=0 */ vec1 32 ssa_103 = umin ssa_100, ssa_102 vec1 32 ssa_103 = umin ssa_100, ssa_102 vec1 32 ssa_104 = isub ssa_98, ssa_103 vec1 32 ssa_104 = isub ssa_98, ssa_103 vec1 32 ssa_105 = deref_var &@11 (function_temp uint) vec1 32 ssa_105 = deref_var &@11 (function_temp uint) intrinsic store_deref (ssa_105, ssa_104) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_105, ssa_104) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_106 = deref_var &@10 (function_temp uint) vec1 32 ssa_106 = deref_var &@10 (function_temp uint) vec1 32 ssa_107 = intrinsic load_deref (ssa_106) (0) /* access=0 */ vec1 32 ssa_107 = intrinsic load_deref (ssa_106) (0) /* access=0 */ vec1 1 ssa_109 = uge ssa_107, ssa_108 vec1 1 ssa_109 = uge ssa_107, ssa_108 /* succs: block_6 block_7 */ /* succs: block_6 block_7 */ if ssa_109 { if ssa_109 { block block_6: block block_6: /* preds: block_5 */ /* preds: block_5 */ vec1 32 ssa_111 = deref_var &@13 (function_temp int) vec1 32 ssa_111 = deref_var &@13 (function_temp int) intrinsic store_deref (ssa_111, ssa_110) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_111, ssa_110) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_8 */ /* succs: block_8 */ } else { } else { block block_7: block block_7: /* preds: block_5 */ /* preds: block_5 */ vec1 32 ssa_112 = deref_var &@10 (function_temp uint) vec1 32 ssa_112 = deref_var &@10 (function_temp uint) vec1 32 ssa_113 = intrinsic load_deref (ssa_112) (0) /* access=0 */ vec1 32 ssa_113 = intrinsic load_deref (ssa_112) (0) /* access=0 */ vec1 32 ssa_115 = ishl ssa_114, ssa_113 vec1 32 ssa_115 = ishl ssa_114, ssa_113 vec1 32 ssa_116 = deref_var &@13 (function_temp int) vec1 32 ssa_116 = deref_var &@13 (function_temp int) intrinsic store_deref (ssa_116, ssa_115) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_116, ssa_115) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_8 */ /* succs: block_8 */ } } block block_8: block block_8: /* preds: block_6 block_7 */ /* preds: block_6 block_7 */ vec1 32 ssa_117 = deref_var &@13 (function_temp int) vec1 32 ssa_117 = deref_var &@13 (function_temp int) vec1 32 ssa_118 = intrinsic load_deref (ssa_117) (0) /* access=0 */ vec1 32 ssa_118 = intrinsic load_deref (ssa_117) (0) /* access=0 */ vec1 32 ssa_119 = mov ssa_118 vec1 32 ssa_119 = mov ssa_118 vec1 32 ssa_120 = deref_var &@10 (function_temp uint) vec1 32 ssa_120 = deref_var &@10 (function_temp uint) vec1 32 ssa_121 = intrinsic load_deref (ssa_120) (0) /* access=0 */ vec1 32 ssa_121 = intrinsic load_deref (ssa_120) (0) /* access=0 */ vec1 1 ssa_123 = uge ssa_121, ssa_122 vec1 1 ssa_123 = uge ssa_121, ssa_122 /* succs: block_9 block_10 */ /* succs: block_9 block_10 */ if ssa_123 { if ssa_123 { block block_9: block block_9: /* preds: block_8 */ /* preds: block_8 */ vec1 32 ssa_125 = deref_var &@14 (function_temp int) vec1 32 ssa_125 = deref_var &@14 (function_temp int) intrinsic store_deref (ssa_125, ssa_124) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_125, ssa_124) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_14 */ /* succs: block_14 */ } else { } else { block block_10: block block_10: /* preds: block_8 */ /* preds: block_8 */ vec1 32 ssa_126 = deref_var &@10 (function_temp uint) vec1 32 ssa_126 = deref_var &@10 (function_temp uint) vec1 32 ssa_127 = intrinsic load_deref (ssa_126) (0) /* access=0 */ vec1 32 ssa_127 = intrinsic load_deref (ssa_126) (0) /* access=0 */ vec1 1 ssa_129 = ult ssa_127, ssa_128 vec1 1 ssa_129 = ult ssa_127, ssa_128 /* succs: block_11 block_12 */ /* succs: block_11 block_12 */ if ssa_129 { if ssa_129 { block block_11: block block_11: /* preds: block_10 */ /* preds: block_10 */ vec1 32 ssa_131 = deref_var &@15 (function_temp uint) vec1 32 ssa_131 = deref_var &@15 (function_temp uint) intrinsic store_deref (ssa_131, ssa_130) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_131, ssa_130) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_13 */ /* succs: block_13 */ } else { } else { block block_12: block block_12: /* preds: block_10 */ /* preds: block_10 */ vec1 32 ssa_132 = deref_var &@10 (function_temp uint) vec1 32 ssa_132 = deref_var &@10 (function_temp uint) vec1 32 ssa_133 = intrinsic load_deref (ssa_132) (0) /* access=0 */ vec1 32 ssa_133 = intrinsic load_deref (ssa_132) (0) /* access=0 */ vec1 32 ssa_135 = isub ssa_133, ssa_134 vec1 32 ssa_135 = isub ssa_133, ssa_134 vec1 32 ssa_136 = deref_var &@15 (function_temp uint) vec1 32 ssa_136 = deref_var &@15 (function_temp uint) intrinsic store_deref (ssa_136, ssa_135) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_136, ssa_135) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_13 */ /* succs: block_13 */ } } block block_13: block block_13: /* preds: block_11 block_12 */ /* preds: block_11 block_12 */ vec1 32 ssa_137 = deref_var &@15 (function_temp uint) vec1 32 ssa_137 = deref_var &@15 (function_temp uint) vec1 32 ssa_138 = intrinsic load_deref (ssa_137) (0) /* access=0 */ vec1 32 ssa_138 = intrinsic load_deref (ssa_137) (0) /* access=0 */ vec1 32 ssa_140 = ishl ssa_139, ssa_138 vec1 32 ssa_140 = ishl ssa_139, ssa_138 vec1 32 ssa_141 = deref_var &@14 (function_temp int) vec1 32 ssa_141 = deref_var &@14 (function_temp int) intrinsic store_deref (ssa_141, ssa_140) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_141, ssa_140) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_14 */ /* succs: block_14 */ } } block block_14: block block_14: /* preds: block_9 block_13 */ /* preds: block_9 block_13 */ vec1 32 ssa_142 = deref_var &@14 (function_temp int) vec1 32 ssa_142 = deref_var &@14 (function_temp int) vec1 32 ssa_143 = intrinsic load_deref (ssa_142) (0) /* access=0 */ vec1 32 ssa_143 = intrinsic load_deref (ssa_142) (0) /* access=0 */ vec1 32 ssa_144 = mov ssa_143 vec1 32 ssa_144 = mov ssa_143 vec1 32 ssa_145 = deref_var &@10 (function_temp uint) vec1 32 ssa_145 = deref_var &@10 (function_temp uint) vec1 32 ssa_146 = intrinsic load_deref (ssa_145) (0) /* access=0 */ vec1 32 ssa_146 = intrinsic load_deref (ssa_145) (0) /* access=0 */ vec1 1 ssa_148 = uge ssa_146, ssa_147 vec1 1 ssa_148 = uge ssa_146, ssa_147 /* succs: block_15 block_16 */ /* succs: block_15 block_16 */ if ssa_148 { if ssa_148 { block block_15: block block_15: /* preds: block_14 */ /* preds: block_14 */ vec1 32 ssa_150 = deref_var &@16 (function_temp int) vec1 32 ssa_150 = deref_var &@16 (function_temp int) intrinsic store_deref (ssa_150, ssa_149) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_150, ssa_149) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_20 */ /* succs: block_20 */ } else { } else { block block_16: block block_16: /* preds: block_14 */ /* preds: block_14 */ vec1 32 ssa_151 = deref_var &@10 (function_temp uint) vec1 32 ssa_151 = deref_var &@10 (function_temp uint) vec1 32 ssa_152 = intrinsic load_deref (ssa_151) (0) /* access=0 */ vec1 32 ssa_152 = intrinsic load_deref (ssa_151) (0) /* access=0 */ vec1 1 ssa_154 = ult ssa_152, ssa_153 vec1 1 ssa_154 = ult ssa_152, ssa_153 /* succs: block_17 block_18 */ /* succs: block_17 block_18 */ if ssa_154 { if ssa_154 { block block_17: block block_17: /* preds: block_16 */ /* preds: block_16 */ vec1 32 ssa_156 = deref_var &@17 (function_temp uint) vec1 32 ssa_156 = deref_var &@17 (function_temp uint) intrinsic store_deref (ssa_156, ssa_155) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_156, ssa_155) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_19 */ /* succs: block_19 */ } else { } else { block block_18: block block_18: /* preds: block_16 */ /* preds: block_16 */ vec1 32 ssa_157 = deref_var &@10 (function_temp uint) vec1 32 ssa_157 = deref_var &@10 (function_temp uint) vec1 32 ssa_158 = intrinsic load_deref (ssa_157) (0) /* access=0 */ vec1 32 ssa_158 = intrinsic load_deref (ssa_157) (0) /* access=0 */ vec1 32 ssa_160 = isub ssa_158, ssa_159 vec1 32 ssa_160 = isub ssa_158, ssa_159 vec1 32 ssa_161 = deref_var &@17 (function_temp uint) vec1 32 ssa_161 = deref_var &@17 (function_temp uint) intrinsic store_deref (ssa_161, ssa_160) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_161, ssa_160) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_19 */ /* succs: block_19 */ } } block block_19: block block_19: /* preds: block_17 block_18 */ /* preds: block_17 block_18 */ vec1 32 ssa_162 = deref_var &@17 (function_temp uint) vec1 32 ssa_162 = deref_var &@17 (function_temp uint) vec1 32 ssa_163 = intrinsic load_deref (ssa_162) (0) /* access=0 */ vec1 32 ssa_163 = intrinsic load_deref (ssa_162) (0) /* access=0 */ vec1 32 ssa_165 = ishl ssa_164, ssa_163 vec1 32 ssa_165 = ishl ssa_164, ssa_163 vec1 32 ssa_166 = deref_var &@16 (function_temp int) vec1 32 ssa_166 = deref_var &@16 (function_temp int) intrinsic store_deref (ssa_166, ssa_165) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_166, ssa_165) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_20 */ /* succs: block_20 */ } } block block_20: block block_20: /* preds: block_15 block_19 */ /* preds: block_15 block_19 */ vec1 32 ssa_167 = deref_var &@16 (function_temp int) vec1 32 ssa_167 = deref_var &@16 (function_temp int) vec1 32 ssa_168 = intrinsic load_deref (ssa_167) (0) /* access=0 */ vec1 32 ssa_168 = intrinsic load_deref (ssa_167) (0) /* access=0 */ vec1 32 ssa_169 = mov ssa_168 vec1 32 ssa_169 = mov ssa_168 vec1 32 ssa_170 = deref_var &@10 (function_temp uint) vec1 32 ssa_170 = deref_var &@10 (function_temp uint) vec1 32 ssa_171 = intrinsic load_deref (ssa_170) (0) /* access=0 */ vec1 32 ssa_171 = intrinsic load_deref (ssa_170) (0) /* access=0 */ vec1 1 ssa_173 = uge ssa_171, ssa_172 vec1 1 ssa_173 = uge ssa_171, ssa_172 /* succs: block_21 block_22 */ /* succs: block_21 block_22 */ if ssa_173 { if ssa_173 { block block_21: block block_21: /* preds: block_20 */ /* preds: block_20 */ vec1 32 ssa_175 = deref_var &@18 (function_temp int) vec1 32 ssa_175 = deref_var &@18 (function_temp int) intrinsic store_deref (ssa_175, ssa_174) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_175, ssa_174) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_26 */ /* succs: block_26 */ } else { } else { block block_22: block block_22: /* preds: block_20 */ /* preds: block_20 */ vec1 32 ssa_176 = deref_var &@10 (function_temp uint) vec1 32 ssa_176 = deref_var &@10 (function_temp uint) vec1 32 ssa_177 = intrinsic load_deref (ssa_176) (0) /* access=0 */ vec1 32 ssa_177 = intrinsic load_deref (ssa_176) (0) /* access=0 */ vec1 1 ssa_179 = ult ssa_177, ssa_178 vec1 1 ssa_179 = ult ssa_177, ssa_178 /* succs: block_23 block_24 */ /* succs: block_23 block_24 */ if ssa_179 { if ssa_179 { block block_23: block block_23: /* preds: block_22 */ /* preds: block_22 */ vec1 32 ssa_181 = deref_var &@19 (function_temp uint) vec1 32 ssa_181 = deref_var &@19 (function_temp uint) intrinsic store_deref (ssa_181, ssa_180) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_181, ssa_180) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_25 */ /* succs: block_25 */ } else { } else { block block_24: block block_24: /* preds: block_22 */ /* preds: block_22 */ vec1 32 ssa_182 = deref_var &@10 (function_temp uint) vec1 32 ssa_182 = deref_var &@10 (function_temp uint) vec1 32 ssa_183 = intrinsic load_deref (ssa_182) (0) /* access=0 */ vec1 32 ssa_183 = intrinsic load_deref (ssa_182) (0) /* access=0 */ vec1 32 ssa_185 = isub ssa_183, ssa_184 vec1 32 ssa_185 = isub ssa_183, ssa_184 vec1 32 ssa_186 = deref_var &@19 (function_temp uint) vec1 32 ssa_186 = deref_var &@19 (function_temp uint) intrinsic store_deref (ssa_186, ssa_185) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_186, ssa_185) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_25 */ /* succs: block_25 */ } } block block_25: block block_25: /* preds: block_23 block_24 */ /* preds: block_23 block_24 */ vec1 32 ssa_187 = deref_var &@19 (function_temp uint) vec1 32 ssa_187 = deref_var &@19 (function_temp uint) vec1 32 ssa_188 = intrinsic load_deref (ssa_187) (0) /* access=0 */ vec1 32 ssa_188 = intrinsic load_deref (ssa_187) (0) /* access=0 */ vec1 32 ssa_190 = ishl ssa_189, ssa_188 vec1 32 ssa_190 = ishl ssa_189, ssa_188 vec1 32 ssa_191 = deref_var &@18 (function_temp int) vec1 32 ssa_191 = deref_var &@18 (function_temp int) intrinsic store_deref (ssa_191, ssa_190) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_191, ssa_190) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_26 */ /* succs: block_26 */ } } block block_26: block block_26: /* preds: block_21 block_25 */ /* preds: block_21 block_25 */ vec1 32 ssa_192 = deref_var &@18 (function_temp int) vec1 32 ssa_192 = deref_var &@18 (function_temp int) vec1 32 ssa_193 = intrinsic load_deref (ssa_192) (0) /* access=0 */ vec1 32 ssa_193 = intrinsic load_deref (ssa_192) (0) /* access=0 */ vec1 32 ssa_194 = mov ssa_193 vec1 32 ssa_194 = mov ssa_193 vec4 32 ssa_195 = vec4 ssa_119, ssa_144, ssa_169, ssa_194 vec4 32 ssa_195 = vec4 ssa_119, ssa_144, ssa_169, ssa_194 vec1 32 ssa_196 = deref_var &@12 (function_temp uvec4) vec1 32 ssa_196 = deref_var &@12 (function_temp uvec4) intrinsic store_deref (ssa_196, ssa_195) (15, 0) /* wrmask=xyzw */ /* access=0 */ intrinsic store_deref (ssa_196, ssa_195) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_197 = deref_var &@12 (function_temp uvec4) vec1 32 ssa_197 = deref_var &@12 (function_temp uvec4) vec4 32 ssa_198 = intrinsic load_deref (ssa_197) (0) /* access=0 */ vec4 32 ssa_198 = intrinsic load_deref (ssa_197) (0) /* access=0 */ vec1 32 ssa_199 = intrinsic ballot_bit_count_inclusive (ssa_198) () vec1 32 ssa_199 = intrinsic ballot_bit_count_inclusive (ssa_198) () vec1 32 ssa_200 = deref_var &@20 (function_temp uint) vec1 32 ssa_200 = deref_var &@20 (function_temp uint) intrinsic store_deref (ssa_200, ssa_199) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_200, ssa_199) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_201 = deref_var &@20 (function_temp uint) vec1 32 ssa_201 = deref_var &@20 (function_temp uint) vec1 32 ssa_202 = intrinsic load_deref (ssa_201) (0) /* access=0 */ vec1 32 ssa_202 = intrinsic load_deref (ssa_201) (0) /* access=0 */ vec1 32 ssa_203 = deref_var &@11 (function_temp uint) vec1 32 ssa_203 = deref_var &@11 (function_temp uint) vec1 32 ssa_204 = intrinsic load_deref (ssa_203) (0) /* access=0 */ vec1 32 ssa_204 = intrinsic load_deref (ssa_203) (0) /* access=0 */ vec1 1 ssa_205 = ine ssa_202, ssa_204 vec1 1 ssa_205 = ine ssa_202, ssa_204 /* succs: block_27 block_28 */ /* succs: block_27 block_28 */ if ssa_205 { if ssa_205 { block block_27: block block_27: /* preds: block_26 */ /* preds: block_26 */ vec1 32 ssa_206 = deref_var &@8 (function_temp uint) vec1 32 ssa_206 = deref_var &@8 (function_temp uint) vec1 32 ssa_207 = intrinsic load_deref (ssa_206) (0) /* access=0 */ vec1 32 ssa_207 = intrinsic load_deref (ssa_206) (0) /* access=0 */ vec1 32 ssa_209 = iand ssa_207, ssa_208 vec1 32 ssa_209 = iand ssa_207, ssa_208 vec1 32 ssa_210 = deref_var &@8 (function_temp uint) vec1 32 ssa_210 = deref_var &@8 (function_temp uint) intrinsic store_deref (ssa_210, ssa_209) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_210, ssa_209) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_29 */ /* succs: block_29 */ } else { } else { block block_28: block block_28: /* preds: block_26 */ /* preds: block_26 */ /* succs: block_29 */ /* succs: block_29 */ } } block block_29: block block_29: /* preds: block_27 block_28 */ /* preds: block_27 block_28 */ continue continue /* succs: block_1 */ /* succs: block_1 */ } else { } else { block block_30: block block_30: /* preds: block_4 */ /* preds: block_4 */ break break /* succs: block_32 */ /* succs: block_32 */ } } block block_31: block block_31: /* preds: */ /* preds: */ /* succs: block_1 */ /* succs: block_1 */ } } block block_32: block block_32: /* preds: block_30 */ /* preds: block_30 */ vec1 32 ssa_222 = deref_var &@5 (function_temp uint) vec1 32 ssa_222 = deref_var &@5 (function_temp uint) vec1 32 ssa_223 = intrinsic load_deref (ssa_222) (0) /* access=0 */ vec1 32 ssa_223 = intrinsic load_deref (ssa_222) (0) /* access=0 */ vec1 32 ssa_224 = deref_var &@8 (function_temp uint) vec1 32 ssa_224 = deref_var &@8 (function_temp uint) vec1 32 ssa_225 = intrinsic load_deref (ssa_224) (0) /* access=0 */ vec1 32 ssa_225 = intrinsic load_deref (ssa_224) (0) /* access=0 */ vec1 32 ssa_226 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_226 = load_const (0x00000000 /* 0.000000 */) vec1 64 ssa_227 = intrinsic vulkan_resource_index (ssa_226) (0, 0, 7) /* desc-set=0 */ /* binding=0 */ /* des vec1 64 ssa_227 = intrinsic vulkan_resource_index (ssa_226) (0, 0, 7) /* desc-set=0 */ /* binding=0 */ /* des vec1 64 ssa_228 = intrinsic load_vulkan_descriptor (ssa_227) (7) /* desc_type=SSBO */ vec1 64 ssa_228 = intrinsic load_vulkan_descriptor (ssa_227) (7) /* desc_type=SSBO */ vec1 64 ssa_229 = deref_cast (block *)ssa_228 (ssbo block) /* ptr_stride=0, align_mul=0, align_offset=0 */ vec1 64 ssa_229 = deref_cast (block *)ssa_228 (ssbo block) /* ptr_stride=0, align_mul=0, align_offset=0 */ vec1 64 ssa_230 = deref_struct &ssa_229->field0 (ssbo uint[]) /* &((block *)ssa_228)->field0 */ vec1 64 ssa_230 = deref_struct &ssa_229->field0 (ssbo uint[]) /* &((block *)ssa_228)->field0 */ vec1 64 ssa_231 = i2i64 ssa_223 vec1 64 ssa_231 = i2i64 ssa_223 vec1 64 ssa_232 = deref_array &(*ssa_230)[ssa_231] (ssbo uint) /* &((block *)ssa_228)->field0[ssa_231] */ vec1 64 ssa_232 = deref_array &(*ssa_230)[ssa_231] (ssbo uint) /* &((block *)ssa_228)->field0[ssa_231] */ intrinsic store_deref (ssa_232, ssa_225) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_232, ssa_225) (1, 0) /* wrmask=x */ /* access=0 */ return return /* succs: block_33 */ /* succs: block_33 */ block block_33: block block_33: } } NIR (SSA form) for compute shader: NIR (SSA form) for compute shader: shader: MESA_SHADER_COMPUTE shader: MESA_SHADER_COMPUTE local-size: 32, 1, 1 local-size: 32, 1, 1 shared-size: 0 shared-size: 0 inputs: 0 inputs: 0 outputs: 0 outputs: 0 uniforms: 36 uniforms: 36 shared: 0 shared: 0 decl_var ssbo INTERP_MODE_NONE restrict block @0 (~0, 0, 0) decl_var ssbo INTERP_MODE_NONE restrict block @0 (~0, 0, 0) decl_function main (0 params) decl_function main (0 params) impl main { impl main { block block_0: block block_0: /* preds: */ /* preds: */ vec1 32 ssa_0 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_0 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_1 = load_const (0xfffffff7 /* -nan */) vec1 32 ssa_1 = load_const (0xfffffff7 /* -nan */) vec1 32 ssa_2 = load_const (0xffffffff /* -nan */) vec1 32 ssa_2 = load_const (0xffffffff /* -nan */) vec1 32 ssa_3 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_4 = load_const (0x00000080 /* 0.000000 */) vec1 32 ssa_4 = load_const (0x00000080 /* 0.000000 */) vec1 32 ssa_5 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_5 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_6 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_6 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_7 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_7 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_8 = load_const (0xffffffff /* -nan */) vec1 32 ssa_8 = load_const (0xffffffff /* -nan */) vec3 32 ssa_9 = intrinsic load_num_work_groups () () vec3 32 ssa_9 = intrinsic load_num_work_groups () () vec1 32 ssa_10 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_10 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_11 = ishl ssa_9.x, ssa_10 vec1 32 ssa_11 = ishl ssa_9.x, ssa_10 vec3 32 ssa_12 = intrinsic load_work_group_id () () vec3 32 ssa_12 = intrinsic load_work_group_id () () vec3 32 ssa_13 = intrinsic load_uniform (ssa_3) (24, 12, 0) /* base=24 */ /* range=12 */ /* dest_type=invalid vec3 32 ssa_13 = intrinsic load_uniform (ssa_3) (24, 12, 0) /* base=24 */ /* range=12 */ /* dest_type=invalid vec1 32 ssa_14 = iadd ssa_12.x, ssa_13.x vec1 32 ssa_14 = iadd ssa_12.x, ssa_13.x vec1 32 ssa_15 = iadd ssa_12.y, ssa_13.y vec1 32 ssa_15 = iadd ssa_12.y, ssa_13.y vec1 32 ssa_16 = iadd ssa_12.z, ssa_13.z vec1 32 ssa_16 = iadd ssa_12.z, ssa_13.z vec1 32 ssa_17 = intrinsic load_subgroup_id () () vec1 32 ssa_17 = intrinsic load_subgroup_id () () vec1 32 ssa_18 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_18 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_19 = ishl ssa_17, ssa_18 vec1 32 ssa_19 = ishl ssa_17, ssa_18 vec1 32 ssa_20 = intrinsic load_subgroup_invocation () () vec1 32 ssa_20 = intrinsic load_subgroup_invocation () () vec1 32 ssa_21 = iadd ssa_20, ssa_19 vec1 32 ssa_21 = iadd ssa_20, ssa_19 vec1 32 ssa_22 = load_const (0x0000001f /* 0.000000 */) vec1 32 ssa_22 = load_const (0x0000001f /* 0.000000 */) vec1 32 ssa_23 = iand ssa_21, ssa_22 vec1 32 ssa_23 = iand ssa_21, ssa_22 vec1 32 ssa_24 = ushr ssa_21, ssa_10 vec1 32 ssa_24 = ushr ssa_21, ssa_10 vec1 32 ssa_25 = ishl ssa_14, ssa_10 vec1 32 ssa_25 = ishl ssa_14, ssa_10 vec1 32 ssa_26 = iadd ssa_25, ssa_23 vec1 32 ssa_26 = iadd ssa_25, ssa_23 vec1 32 ssa_27 = iadd ssa_16, ssa_24 vec1 32 ssa_27 = iadd ssa_16, ssa_24 vec1 32 ssa_28 = imul ssa_9.y, ssa_27 vec1 32 ssa_28 = imul ssa_9.y, ssa_27 vec1 32 ssa_29 = iadd ssa_28, ssa_15 vec1 32 ssa_29 = iadd ssa_28, ssa_15 vec1 32 ssa_30 = imul ssa_11, ssa_29 vec1 32 ssa_30 = imul ssa_11, ssa_29 vec1 32 ssa_31 = iadd ssa_30, ssa_26 vec1 32 ssa_31 = iadd ssa_30, ssa_26 vec1 32 ssa_32 = iadd ssa_20, ssa_0 vec1 32 ssa_32 = iadd ssa_20, ssa_0 vec1 32 ssa_33 = ineg ssa_20 vec1 32 ssa_33 = ineg ssa_20 vec1 32 ssa_34 = iadd ssa_22, ssa_33 vec1 32 ssa_34 = iadd ssa_22, ssa_33 vec1 32 ssa_35 = ushr ssa_2, ssa_34 vec1 32 ssa_35 = ushr ssa_2, ssa_34 vec1 32 ssa_36 = bit_count ssa_35 vec1 32 ssa_36 = bit_count ssa_35 vec1 32 ssa_37 = ieq32 ssa_32, ssa_36 vec1 32 ssa_37 = ieq32 ssa_32, ssa_36 vec1 32 ssa_38 = b2i32 ssa_37 vec1 32 ssa_38 = b2i32 ssa_37 vec1 32 ssa_39 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_39 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_40 = ior ssa_38, ssa_39 vec1 32 ssa_40 = ior ssa_38, ssa_39 vec1 32 ssa_41 = intrinsic ballot (ssa_8) () vec1 32 ssa_41 = intrinsic ballot (ssa_8) () vec1 32 ssa_42 = iand ssa_41, ssa_35 vec1 32 ssa_42 = iand ssa_41, ssa_35 vec1 32 ssa_43 = bit_count ssa_42 vec1 32 ssa_43 = bit_count ssa_42 vec1 32 ssa_44 = ult32 ssa_3, ssa_43 vec1 32 ssa_44 = ult32 ssa_3, ssa_43 vec1 32 ssa_45 = b32csel ssa_44, ssa_7, ssa_3 vec1 32 ssa_45 = b32csel ssa_44, ssa_7, ssa_3 vec1 32 ssa_46 = ior ssa_40, ssa_45 vec1 32 ssa_46 = ior ssa_40, ssa_45 vec1 32 ssa_47 = ior ssa_46, ssa_6 vec1 32 ssa_47 = ior ssa_46, ssa_6 /* succs: block_1 */ /* succs: block_1 */ loop { loop { block block_1: block block_1: /* preds: block_0 block_4 */ /* preds: block_0 block_4 */ vec1 32 ssa_48 = phi block_0: ssa_47, block_4: ssa_61 vec1 32 ssa_48 = phi block_0: ssa_47, block_4: ssa_61 vec1 32 ssa_49 = phi block_0: ssa_3, block_4: ssa_62 vec1 32 ssa_49 = phi block_0: ssa_3, block_4: ssa_62 vec1 32 ssa_50 = uge32 ssa_49, ssa_4 vec1 32 ssa_50 = uge32 ssa_49, ssa_4 /* succs: block_2 block_3 */ /* succs: block_2 block_3 */ if ssa_50 { if ssa_50 { block block_2: block block_2: /* preds: block_1 */ /* preds: block_1 */ break break /* succs: block_5 */ /* succs: block_5 */ } else { } else { block block_3: block block_3: /* preds: block_1 */ /* preds: block_1 */ /* succs: block_4 */ /* succs: block_4 */ } } block block_4: block block_4: /* preds: block_3 */ /* preds: block_3 */ vec1 32 ssa_51 = umin ssa_32, ssa_49 vec1 32 ssa_51 = umin ssa_32, ssa_49 vec1 32 ssa_52 = ineg ssa_51 vec1 32 ssa_52 = ineg ssa_51 vec1 32 ssa_53 = iadd ssa_32, ssa_52 vec1 32 ssa_53 = iadd ssa_32, ssa_52 vec1 32 ssa_54 = ishl ssa_2, ssa_49 vec1 32 ssa_54 = ishl ssa_2, ssa_49 vec1 32 ssa_55 = uge32 ssa_49, ssa_5 vec1 32 ssa_55 = uge32 ssa_49, ssa_5 vec1 32 ssa_56 = b32csel ssa_55, ssa_3, ssa_54 vec1 32 ssa_56 = b32csel ssa_55, ssa_3, ssa_54 vec1 32 ssa_57 = iand ssa_56, ssa_35 vec1 32 ssa_57 = iand ssa_56, ssa_35 vec1 32 ssa_58 = bit_count ssa_57 vec1 32 ssa_58 = bit_count ssa_57 vec1 32 ssa_59 = iand ssa_48, ssa_1 vec1 32 ssa_59 = iand ssa_48, ssa_1 vec1 32 ssa_60 = ine32 ssa_58, ssa_53 vec1 32 ssa_60 = ine32 ssa_58, ssa_53 vec1 32 ssa_61 = b32csel ssa_60, ssa_59, ssa_48 vec1 32 ssa_61 = b32csel ssa_60, ssa_59, ssa_48 vec1 32 ssa_62 = iadd ssa_49, ssa_0 vec1 32 ssa_62 = iadd ssa_49, ssa_0 /* succs: block_1 */ /* succs: block_1 */ } } block block_5: block block_5: /* preds: block_2 */ /* preds: block_2 */ vec1 32 ssa_63 = ishl ssa_31, ssa_39 vec1 32 ssa_63 = ishl ssa_31, ssa_39 intrinsic store_ssbo (ssa_48, ssa_39, ssa_63) (1, 0, 4, 0) /* wrmask=x */ /* access=0 */ /* align_mul=4 */ /* intrinsic store_ssbo (ssa_48, ssa_39, ssa_63) (1, 0, 4, 0) /* wrmask=x */ /* access=0 */ /* align_mul=4 */ /* /* succs: block_6 */ /* succs: block_6 */ block block_6: block block_6: } } NIR (final form) for compute shader: NIR (final form) for compute shader: shader: MESA_SHADER_COMPUTE shader: MESA_SHADER_COMPUTE local-size: 32, 1, 1 local-size: 32, 1, 1 shared-size: 0 shared-size: 0 inputs: 0 inputs: 0 outputs: 0 outputs: 0 uniforms: 36 uniforms: 36 shared: 0 shared: 0 decl_var ssbo INTERP_MODE_NONE restrict block @0 (~0, 0, 0) decl_var ssbo INTERP_MODE_NONE restrict block @0 (~0, 0, 0) decl_function main (0 params) decl_function main (0 params) impl main { impl main { decl_reg vec1 32 r3 decl_reg vec1 32 r3 decl_reg vec1 32 r4 decl_reg vec1 32 r4 block block_0: block block_0: /* preds: */ /* preds: */ vec1 32 ssa_0 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_0 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_1 = load_const (0xfffffff7 /* -nan */) vec1 32 ssa_1 = load_const (0xfffffff7 /* -nan */) vec1 32 ssa_2 = load_const (0xffffffff /* -nan */) vec1 32 ssa_2 = load_const (0xffffffff /* -nan */) vec1 32 ssa_3 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_4 = load_const (0x00000080 /* 0.000000 */) vec1 32 ssa_4 = load_const (0x00000080 /* 0.000000 */) vec1 32 ssa_5 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_5 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_6 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_6 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_7 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_7 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_8 = load_const (0xffffffff /* -nan */) vec1 32 ssa_8 = load_const (0xffffffff /* -nan */) vec3 32 ssa_9 = intrinsic load_num_work_groups () () vec3 32 ssa_9 = intrinsic load_num_work_groups () () vec1 32 ssa_10 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_10 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_11 = ishl ssa_9.x, ssa_10 vec1 32 ssa_11 = ishl ssa_9.x, ssa_10 vec3 32 ssa_12 = intrinsic load_work_group_id () () vec3 32 ssa_12 = intrinsic load_work_group_id () () vec3 32 ssa_13 = intrinsic load_uniform (ssa_3) (24, 12, 0) /* base=24 */ /* range=12 */ /* dest_type=invalid vec3 32 ssa_13 = intrinsic load_uniform (ssa_3) (24, 12, 0) /* base=24 */ /* range=12 */ /* dest_type=invalid vec1 32 ssa_14 = iadd ssa_12.x, ssa_13.x vec1 32 ssa_14 = iadd ssa_12.x, ssa_13.x vec1 32 ssa_15 = iadd ssa_12.y, ssa_13.y vec1 32 ssa_15 = iadd ssa_12.y, ssa_13.y vec1 32 ssa_16 = iadd ssa_12.z, ssa_13.z vec1 32 ssa_16 = iadd ssa_12.z, ssa_13.z vec1 32 ssa_17 = intrinsic load_subgroup_id () () vec1 32 ssa_17 = intrinsic load_subgroup_id () () vec1 32 ssa_18 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_18 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_19 = ishl ssa_17, ssa_18 vec1 32 ssa_19 = ishl ssa_17, ssa_18 vec1 32 ssa_20 = intrinsic load_subgroup_invocation () () vec1 32 ssa_20 = intrinsic load_subgroup_invocation () () vec1 32 ssa_21 = iadd ssa_20, ssa_19 vec1 32 ssa_21 = iadd ssa_20, ssa_19 vec1 32 ssa_22 = load_const (0x0000001f /* 0.000000 */) vec1 32 ssa_22 = load_const (0x0000001f /* 0.000000 */) vec1 32 ssa_23 = iand ssa_21, ssa_22 vec1 32 ssa_23 = iand ssa_21, ssa_22 vec1 32 ssa_24 = ushr ssa_21, ssa_10 vec1 32 ssa_24 = ushr ssa_21, ssa_10 vec1 32 ssa_25 = ishl ssa_14, ssa_10 vec1 32 ssa_25 = ishl ssa_14, ssa_10 vec1 32 ssa_26 = iadd ssa_25, ssa_23 vec1 32 ssa_26 = iadd ssa_25, ssa_23 vec1 32 ssa_27 = iadd ssa_16, ssa_24 vec1 32 ssa_27 = iadd ssa_16, ssa_24 vec1 32 ssa_28 = imul ssa_9.y, ssa_27 vec1 32 ssa_28 = imul ssa_9.y, ssa_27 vec1 32 ssa_29 = iadd ssa_28, ssa_15 vec1 32 ssa_29 = iadd ssa_28, ssa_15 vec1 32 ssa_30 = imul ssa_11, ssa_29 vec1 32 ssa_30 = imul ssa_11, ssa_29 vec1 32 ssa_31 = iadd ssa_30, ssa_26 vec1 32 ssa_31 = iadd ssa_30, ssa_26 vec1 32 ssa_32 = iadd ssa_20, ssa_0 vec1 32 ssa_32 = iadd ssa_20, ssa_0 vec1 32 ssa_33 = ineg ssa_20 vec1 32 ssa_33 = ineg ssa_20 vec1 32 ssa_34 = iadd ssa_22, ssa_33 vec1 32 ssa_34 = iadd ssa_22, ssa_33 vec1 32 ssa_35 = ushr ssa_2, ssa_34 vec1 32 ssa_35 = ushr ssa_2, ssa_34 vec1 32 ssa_36 = bit_count ssa_35 vec1 32 ssa_36 = bit_count ssa_35 vec1 32 ssa_37 = ieq32 ssa_32, ssa_36 vec1 32 ssa_37 = ieq32 ssa_32, ssa_36 vec1 32 ssa_38 = b2i32 ssa_37 vec1 32 ssa_38 = b2i32 ssa_37 vec1 32 ssa_39 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_39 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_40 = ior ssa_38, ssa_39 vec1 32 ssa_40 = ior ssa_38, ssa_39 vec1 32 ssa_41 = intrinsic ballot (ssa_8) () vec1 32 ssa_41 = intrinsic ballot (ssa_8) () vec1 32 ssa_42 = iand ssa_41, ssa_35 vec1 32 ssa_42 = iand ssa_41, ssa_35 vec1 32 ssa_43 = bit_count ssa_42 vec1 32 ssa_43 = bit_count ssa_42 vec1 32 ssa_44 = ult32 ssa_3, ssa_43 vec1 32 ssa_44 = ult32 ssa_3, ssa_43 vec1 32 ssa_45 = b32csel ssa_44, ssa_7, ssa_3 vec1 32 ssa_45 = b32csel ssa_44, ssa_7, ssa_3 vec1 32 ssa_46 = ior ssa_40, ssa_45 vec1 32 ssa_46 = ior ssa_40, ssa_45 r3 = ior ssa_46, ssa_6 r3 = ior ssa_46, ssa_6 r4 = mov ssa_3 r4 = mov ssa_3 /* succs: block_1 */ /* succs: block_1 */ loop { loop { block block_1: block block_1: /* preds: block_0 block_4 */ /* preds: block_0 block_4 */ vec1 32 ssa_50 = uge32 r4, ssa_4 vec1 32 ssa_50 = uge32 r4, ssa_4 /* succs: block_2 block_3 */ /* succs: block_2 block_3 */ if ssa_50 { if ssa_50 { block block_2: block block_2: /* preds: block_1 */ /* preds: block_1 */ break break /* succs: block_5 */ /* succs: block_5 */ } else { } else { block block_3: block block_3: /* preds: block_1 */ /* preds: block_1 */ /* succs: block_4 */ /* succs: block_4 */ } } block block_4: block block_4: /* preds: block_3 */ /* preds: block_3 */ vec1 32 ssa_51 = umin ssa_32, r4 vec1 32 ssa_51 = umin ssa_32, r4 vec1 32 ssa_52 = ineg ssa_51 vec1 32 ssa_52 = ineg ssa_51 vec1 32 ssa_53 = iadd ssa_32, ssa_52 vec1 32 ssa_53 = iadd ssa_32, ssa_52 vec1 32 ssa_54 = ishl ssa_2, r4 vec1 32 ssa_54 = ishl ssa_2, r4 vec1 32 ssa_55 = uge32 r4, ssa_5 vec1 32 ssa_55 = uge32 r4, ssa_5 vec1 32 ssa_56 = b32csel ssa_55, ssa_3, ssa_54 vec1 32 ssa_56 = b32csel ssa_55, ssa_3, ssa_54 vec1 32 ssa_57 = iand ssa_56, ssa_35 vec1 32 ssa_57 = iand ssa_56, ssa_35 vec1 32 ssa_58 = bit_count ssa_57 vec1 32 ssa_58 = bit_count ssa_57 vec1 32 ssa_59 = iand r3, ssa_1 vec1 32 ssa_59 = iand r3, ssa_1 vec1 32 ssa_60 = ine32 ssa_58, ssa_53 vec1 32 ssa_60 = ine32 ssa_58, ssa_53 r3 = b32csel ssa_60, ssa_59, r3 r3 = b32csel ssa_60, ssa_59, r3 r4 = iadd r4, ssa_0 r4 = iadd r4, ssa_0 /* succs: block_1 */ /* succs: block_1 */ } } block block_5: block block_5: /* preds: block_2 */ /* preds: block_2 */ vec1 32 ssa_63 = ishl ssa_31, ssa_39 vec1 32 ssa_63 = ishl ssa_31, ssa_39 intrinsic store_ssbo (r3, ssa_39, ssa_63) (1, 0, 4, 0) /* wrmask=x */ /* access=0 */ /* align_mul=4 */ /* ali intrinsic store_ssbo (r3, ssa_39, ssa_63) (1, 0, 4, 0) /* wrmask=x */ /* access=0 */ /* align_mul=4 */ /* ali /* succs: block_6 */ /* succs: block_6 */ block block_6: block block_6: } } NIR (SSA form) for compute shader: NIR (SSA form) for compute shader: shader: MESA_SHADER_COMPUTE shader: MESA_SHADER_COMPUTE local-size: 32, 1, 1 local-size: 32, 1, 1 shared-size: 0 shared-size: 0 inputs: 0 inputs: 0 outputs: 0 outputs: 0 uniforms: 36 uniforms: 36 shared: 0 shared: 0 decl_var ssbo INTERP_MODE_NONE restrict block @0 (~0, 0, 0) decl_var ssbo INTERP_MODE_NONE restrict block @0 (~0, 0, 0) decl_function main (0 params) decl_function main (0 params) impl main { impl main { block block_0: block block_0: /* preds: */ /* preds: */ vec1 32 ssa_0 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_0 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_1 = load_const (0xfffffff7 /* -nan */) vec1 32 ssa_1 = load_const (0xfffffff7 /* -nan */) vec1 32 ssa_2 = load_const (0xffffffff /* -nan */) vec1 32 ssa_2 = load_const (0xffffffff /* -nan */) vec1 32 ssa_3 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_4 = load_const (0x00000080 /* 0.000000 */) vec1 32 ssa_4 = load_const (0x00000080 /* 0.000000 */) vec1 32 ssa_5 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_5 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_6 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_6 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_7 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_7 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_8 = load_const (0xffffffff /* -nan */) vec1 32 ssa_8 = load_const (0xffffffff /* -nan */) vec3 32 ssa_9 = intrinsic load_num_work_groups () () vec3 32 ssa_9 = intrinsic load_num_work_groups () () vec1 32 ssa_10 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_10 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_11 = ishl ssa_9.x, ssa_10 vec1 32 ssa_11 = ishl ssa_9.x, ssa_10 vec3 32 ssa_12 = intrinsic load_work_group_id () () vec3 32 ssa_12 = intrinsic load_work_group_id () () vec3 32 ssa_13 = intrinsic load_uniform (ssa_3) (24, 12, 0) /* base=24 */ /* range=12 */ /* dest_type=invalid vec3 32 ssa_13 = intrinsic load_uniform (ssa_3) (24, 12, 0) /* base=24 */ /* range=12 */ /* dest_type=invalid vec1 32 ssa_14 = iadd ssa_12.x, ssa_13.x vec1 32 ssa_14 = iadd ssa_12.x, ssa_13.x vec1 32 ssa_15 = iadd ssa_12.y, ssa_13.y vec1 32 ssa_15 = iadd ssa_12.y, ssa_13.y vec1 32 ssa_16 = iadd ssa_12.z, ssa_13.z vec1 32 ssa_16 = iadd ssa_12.z, ssa_13.z vec1 32 ssa_17 = intrinsic load_subgroup_id () () vec1 32 ssa_17 = intrinsic load_subgroup_id () () vec1 32 ssa_18 = ishl ssa_17, ssa_7 vec1 32 ssa_18 = ishl ssa_17, ssa_7 vec1 32 ssa_19 = intrinsic load_subgroup_invocation () () vec1 32 ssa_19 = intrinsic load_subgroup_invocation () () vec1 32 ssa_20 = iadd ssa_19, ssa_18 vec1 32 ssa_20 = iadd ssa_19, ssa_18 vec1 32 ssa_21 = load_const (0x0000001f /* 0.000000 */) vec1 32 ssa_21 = load_const (0x0000001f /* 0.000000 */) vec1 32 ssa_22 = iand ssa_20, ssa_21 vec1 32 ssa_22 = iand ssa_20, ssa_21 vec1 32 ssa_23 = ushr ssa_20, ssa_10 vec1 32 ssa_23 = ushr ssa_20, ssa_10 vec1 32 ssa_24 = ishl ssa_14, ssa_10 vec1 32 ssa_24 = ishl ssa_14, ssa_10 vec1 32 ssa_25 = iadd ssa_24, ssa_22 vec1 32 ssa_25 = iadd ssa_24, ssa_22 vec1 32 ssa_26 = iadd ssa_16, ssa_23 vec1 32 ssa_26 = iadd ssa_16, ssa_23 vec1 32 ssa_27 = imul ssa_9.y, ssa_26 vec1 32 ssa_27 = imul ssa_9.y, ssa_26 vec1 32 ssa_28 = iadd ssa_27, ssa_15 vec1 32 ssa_28 = iadd ssa_27, ssa_15 vec1 32 ssa_29 = imul ssa_11, ssa_28 vec1 32 ssa_29 = imul ssa_11, ssa_28 vec1 32 ssa_30 = iadd ssa_29, ssa_25 vec1 32 ssa_30 = iadd ssa_29, ssa_25 vec1 32 ssa_31 = iadd ssa_19, ssa_0 vec1 32 ssa_31 = iadd ssa_19, ssa_0 vec1 32 ssa_32 = ineg ssa_19 vec1 32 ssa_32 = ineg ssa_19 vec1 32 ssa_33 = iadd ssa_21, ssa_32 vec1 32 ssa_33 = iadd ssa_21, ssa_32 vec1 32 ssa_34 = ushr ssa_2, ssa_33 vec1 32 ssa_34 = ushr ssa_2, ssa_33 vec1 32 ssa_35 = bit_count ssa_34 vec1 32 ssa_35 = bit_count ssa_34 vec1 32 ssa_36 = ieq32 ssa_31, ssa_35 vec1 32 ssa_36 = ieq32 ssa_31, ssa_35 vec1 32 ssa_37 = b2i32 ssa_36 vec1 32 ssa_37 = b2i32 ssa_36 vec1 32 ssa_38 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_38 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_39 = ior ssa_37, ssa_38 vec1 32 ssa_39 = ior ssa_37, ssa_38 vec1 32 ssa_40 = intrinsic ballot (ssa_8) () vec1 32 ssa_40 = intrinsic ballot (ssa_8) () vec1 32 ssa_41 = iand ssa_40, ssa_34 vec1 32 ssa_41 = iand ssa_40, ssa_34 vec1 32 ssa_42 = bit_count ssa_41 vec1 32 ssa_42 = bit_count ssa_41 vec1 32 ssa_43 = ult32 ssa_3, ssa_42 vec1 32 ssa_43 = ult32 ssa_3, ssa_42 vec1 32 ssa_44 = b32csel ssa_43, ssa_7, ssa_3 vec1 32 ssa_44 = b32csel ssa_43, ssa_7, ssa_3 vec1 32 ssa_45 = ior ssa_39, ssa_44 vec1 32 ssa_45 = ior ssa_39, ssa_44 vec1 32 ssa_46 = ior ssa_45, ssa_6 vec1 32 ssa_46 = ior ssa_45, ssa_6 /* succs: block_1 */ /* succs: block_1 */ loop { loop { block block_1: block block_1: /* preds: block_0 block_4 */ /* preds: block_0 block_4 */ vec1 32 ssa_47 = phi block_0: ssa_46, block_4: ssa_60 vec1 32 ssa_47 = phi block_0: ssa_46, block_4: ssa_60 vec1 32 ssa_48 = phi block_0: ssa_3, block_4: ssa_61 vec1 32 ssa_48 = phi block_0: ssa_3, block_4: ssa_61 vec1 32 ssa_49 = uge32 ssa_48, ssa_4 vec1 32 ssa_49 = uge32 ssa_48, ssa_4 /* succs: block_2 block_3 */ /* succs: block_2 block_3 */ if ssa_49 { if ssa_49 { block block_2: block block_2: /* preds: block_1 */ /* preds: block_1 */ break break /* succs: block_5 */ /* succs: block_5 */ } else { } else { block block_3: block block_3: /* preds: block_1 */ /* preds: block_1 */ /* succs: block_4 */ /* succs: block_4 */ } } block block_4: block block_4: /* preds: block_3 */ /* preds: block_3 */ vec1 32 ssa_50 = umin ssa_31, ssa_48 vec1 32 ssa_50 = umin ssa_31, ssa_48 vec1 32 ssa_51 = ineg ssa_50 vec1 32 ssa_51 = ineg ssa_50 vec1 32 ssa_52 = iadd ssa_31, ssa_51 vec1 32 ssa_52 = iadd ssa_31, ssa_51 vec1 32 ssa_53 = ishl ssa_2, ssa_48 vec1 32 ssa_53 = ishl ssa_2, ssa_48 vec1 32 ssa_54 = uge32 ssa_48, ssa_5 vec1 32 ssa_54 = uge32 ssa_48, ssa_5 vec1 32 ssa_55 = b32csel ssa_54, ssa_3, ssa_53 vec1 32 ssa_55 = b32csel ssa_54, ssa_3, ssa_53 vec1 32 ssa_56 = iand ssa_55, ssa_34 vec1 32 ssa_56 = iand ssa_55, ssa_34 vec1 32 ssa_57 = bit_count ssa_56 vec1 32 ssa_57 = bit_count ssa_56 vec1 32 ssa_58 = iand ssa_47, ssa_1 vec1 32 ssa_58 = iand ssa_47, ssa_1 vec1 32 ssa_59 = ine32 ssa_57, ssa_52 vec1 32 ssa_59 = ine32 ssa_57, ssa_52 vec1 32 ssa_60 = b32csel ssa_59, ssa_58, ssa_47 vec1 32 ssa_60 = b32csel ssa_59, ssa_58, ssa_47 vec1 32 ssa_61 = iadd ssa_48, ssa_0 vec1 32 ssa_61 = iadd ssa_48, ssa_0 /* succs: block_1 */ /* succs: block_1 */ } } block block_5: block block_5: /* preds: block_2 */ /* preds: block_2 */ vec1 32 ssa_62 = ishl ssa_30, ssa_38 vec1 32 ssa_62 = ishl ssa_30, ssa_38 intrinsic store_ssbo (ssa_47, ssa_38, ssa_62) (1, 0, 4, 0) /* wrmask=x */ /* access=0 */ /* align_mul=4 */ /* intrinsic store_ssbo (ssa_47, ssa_38, ssa_62) (1, 0, 4, 0) /* wrmask=x */ /* access=0 */ /* align_mul=4 */ /* /* succs: block_6 */ /* succs: block_6 */ block block_6: block block_6: } } NIR (final form) for compute shader: NIR (final form) for compute shader: shader: MESA_SHADER_COMPUTE shader: MESA_SHADER_COMPUTE local-size: 32, 1, 1 local-size: 32, 1, 1 shared-size: 0 shared-size: 0 inputs: 0 inputs: 0 outputs: 0 outputs: 0 uniforms: 36 uniforms: 36 shared: 0 shared: 0 decl_var ssbo INTERP_MODE_NONE restrict block @0 (~0, 0, 0) decl_var ssbo INTERP_MODE_NONE restrict block @0 (~0, 0, 0) decl_function main (0 params) decl_function main (0 params) impl main { impl main { decl_reg vec1 32 r3 decl_reg vec1 32 r3 decl_reg vec1 32 r4 decl_reg vec1 32 r4 block block_0: block block_0: /* preds: */ /* preds: */ vec1 32 ssa_0 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_0 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_1 = load_const (0xfffffff7 /* -nan */) vec1 32 ssa_1 = load_const (0xfffffff7 /* -nan */) vec1 32 ssa_2 = load_const (0xffffffff /* -nan */) vec1 32 ssa_2 = load_const (0xffffffff /* -nan */) vec1 32 ssa_3 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_4 = load_const (0x00000080 /* 0.000000 */) vec1 32 ssa_4 = load_const (0x00000080 /* 0.000000 */) vec1 32 ssa_5 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_5 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_6 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_6 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_7 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_7 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_8 = load_const (0xffffffff /* -nan */) vec1 32 ssa_8 = load_const (0xffffffff /* -nan */) vec3 32 ssa_9 = intrinsic load_num_work_groups () () vec3 32 ssa_9 = intrinsic load_num_work_groups () () vec1 32 ssa_10 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_10 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_11 = ishl ssa_9.x, ssa_10 vec1 32 ssa_11 = ishl ssa_9.x, ssa_10 vec3 32 ssa_12 = intrinsic load_work_group_id () () vec3 32 ssa_12 = intrinsic load_work_group_id () () vec3 32 ssa_13 = intrinsic load_uniform (ssa_3) (24, 12, 0) /* base=24 */ /* range=12 */ /* dest_type=invalid vec3 32 ssa_13 = intrinsic load_uniform (ssa_3) (24, 12, 0) /* base=24 */ /* range=12 */ /* dest_type=invalid vec1 32 ssa_14 = iadd ssa_12.x, ssa_13.x vec1 32 ssa_14 = iadd ssa_12.x, ssa_13.x vec1 32 ssa_15 = iadd ssa_12.y, ssa_13.y vec1 32 ssa_15 = iadd ssa_12.y, ssa_13.y vec1 32 ssa_16 = iadd ssa_12.z, ssa_13.z vec1 32 ssa_16 = iadd ssa_12.z, ssa_13.z vec1 32 ssa_17 = intrinsic load_subgroup_id () () vec1 32 ssa_17 = intrinsic load_subgroup_id () () vec1 32 ssa_18 = ishl ssa_17, ssa_7 vec1 32 ssa_18 = ishl ssa_17, ssa_7 vec1 32 ssa_19 = intrinsic load_subgroup_invocation () () vec1 32 ssa_19 = intrinsic load_subgroup_invocation () () vec1 32 ssa_20 = iadd ssa_19, ssa_18 vec1 32 ssa_20 = iadd ssa_19, ssa_18 vec1 32 ssa_21 = load_const (0x0000001f /* 0.000000 */) vec1 32 ssa_21 = load_const (0x0000001f /* 0.000000 */) vec1 32 ssa_22 = iand ssa_20, ssa_21 vec1 32 ssa_22 = iand ssa_20, ssa_21 vec1 32 ssa_23 = ushr ssa_20, ssa_10 vec1 32 ssa_23 = ushr ssa_20, ssa_10 vec1 32 ssa_24 = ishl ssa_14, ssa_10 vec1 32 ssa_24 = ishl ssa_14, ssa_10 vec1 32 ssa_25 = iadd ssa_24, ssa_22 vec1 32 ssa_25 = iadd ssa_24, ssa_22 vec1 32 ssa_26 = iadd ssa_16, ssa_23 vec1 32 ssa_26 = iadd ssa_16, ssa_23 vec1 32 ssa_27 = imul ssa_9.y, ssa_26 vec1 32 ssa_27 = imul ssa_9.y, ssa_26 vec1 32 ssa_28 = iadd ssa_27, ssa_15 vec1 32 ssa_28 = iadd ssa_27, ssa_15 vec1 32 ssa_29 = imul ssa_11, ssa_28 vec1 32 ssa_29 = imul ssa_11, ssa_28 vec1 32 ssa_30 = iadd ssa_29, ssa_25 vec1 32 ssa_30 = iadd ssa_29, ssa_25 vec1 32 ssa_31 = iadd ssa_19, ssa_0 vec1 32 ssa_31 = iadd ssa_19, ssa_0 vec1 32 ssa_32 = ineg ssa_19 vec1 32 ssa_32 = ineg ssa_19 vec1 32 ssa_33 = iadd ssa_21, ssa_32 vec1 32 ssa_33 = iadd ssa_21, ssa_32 vec1 32 ssa_34 = ushr ssa_2, ssa_33 vec1 32 ssa_34 = ushr ssa_2, ssa_33 vec1 32 ssa_35 = bit_count ssa_34 vec1 32 ssa_35 = bit_count ssa_34 vec1 32 ssa_36 = ieq32 ssa_31, ssa_35 vec1 32 ssa_36 = ieq32 ssa_31, ssa_35 vec1 32 ssa_37 = b2i32 ssa_36 vec1 32 ssa_37 = b2i32 ssa_36 vec1 32 ssa_38 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_38 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_39 = ior ssa_37, ssa_38 vec1 32 ssa_39 = ior ssa_37, ssa_38 vec1 32 ssa_40 = intrinsic ballot (ssa_8) () vec1 32 ssa_40 = intrinsic ballot (ssa_8) () vec1 32 ssa_41 = iand ssa_40, ssa_34 vec1 32 ssa_41 = iand ssa_40, ssa_34 vec1 32 ssa_42 = bit_count ssa_41 vec1 32 ssa_42 = bit_count ssa_41 vec1 32 ssa_43 = ult32 ssa_3, ssa_42 vec1 32 ssa_43 = ult32 ssa_3, ssa_42 vec1 32 ssa_44 = b32csel ssa_43, ssa_7, ssa_3 vec1 32 ssa_44 = b32csel ssa_43, ssa_7, ssa_3 vec1 32 ssa_45 = ior ssa_39, ssa_44 vec1 32 ssa_45 = ior ssa_39, ssa_44 r3 = ior ssa_45, ssa_6 r3 = ior ssa_45, ssa_6 r4 = mov ssa_3 r4 = mov ssa_3 /* succs: block_1 */ /* succs: block_1 */ loop { loop { block block_1: block block_1: /* preds: block_0 block_4 */ /* preds: block_0 block_4 */ vec1 32 ssa_49 = uge32 r4, ssa_4 vec1 32 ssa_49 = uge32 r4, ssa_4 /* succs: block_2 block_3 */ /* succs: block_2 block_3 */ if ssa_49 { if ssa_49 { block block_2: block block_2: /* preds: block_1 */ /* preds: block_1 */ break break /* succs: block_5 */ /* succs: block_5 */ } else { } else { block block_3: block block_3: /* preds: block_1 */ /* preds: block_1 */ /* succs: block_4 */ /* succs: block_4 */ } } block block_4: block block_4: /* preds: block_3 */ /* preds: block_3 */ vec1 32 ssa_50 = umin ssa_31, r4 vec1 32 ssa_50 = umin ssa_31, r4 vec1 32 ssa_51 = ineg ssa_50 vec1 32 ssa_51 = ineg ssa_50 vec1 32 ssa_52 = iadd ssa_31, ssa_51 vec1 32 ssa_52 = iadd ssa_31, ssa_51 vec1 32 ssa_53 = ishl ssa_2, r4 vec1 32 ssa_53 = ishl ssa_2, r4 vec1 32 ssa_54 = uge32 r4, ssa_5 vec1 32 ssa_54 = uge32 r4, ssa_5 vec1 32 ssa_55 = b32csel ssa_54, ssa_3, ssa_53 vec1 32 ssa_55 = b32csel ssa_54, ssa_3, ssa_53 vec1 32 ssa_56 = iand ssa_55, ssa_34 vec1 32 ssa_56 = iand ssa_55, ssa_34 vec1 32 ssa_57 = bit_count ssa_56 vec1 32 ssa_57 = bit_count ssa_56 vec1 32 ssa_58 = iand r3, ssa_1 vec1 32 ssa_58 = iand r3, ssa_1 vec1 32 ssa_59 = ine32 ssa_57, ssa_52 vec1 32 ssa_59 = ine32 ssa_57, ssa_52 r3 = b32csel ssa_59, ssa_58, r3 r3 = b32csel ssa_59, ssa_58, r3 r4 = iadd r4, ssa_0 r4 = iadd r4, ssa_0 /* succs: block_1 */ /* succs: block_1 */ } } block block_5: block block_5: /* preds: block_2 */ /* preds: block_2 */ vec1 32 ssa_62 = ishl ssa_30, ssa_38 vec1 32 ssa_62 = ishl ssa_30, ssa_38 intrinsic store_ssbo (r3, ssa_38, ssa_62) (1, 0, 4, 0) /* wrmask=x */ /* access=0 */ /* align_mul=4 */ /* ali intrinsic store_ssbo (r3, ssa_38, ssa_62) (1, 0, 4, 0) /* wrmask=x */ /* access=0 */ /* align_mul=4 */ /* ali /* succs: block_6 */ /* succs: block_6 */ block block_6: block block_6: } } Native code for unnamed compute shader (null) (sha1 07da95c142020d3392479134d736275363ed6e1d) | Native code for unnamed compute shader (null) (sha1 b329ad70195e3ccda813299efe395f7365bf0b29) SIMD16 shader: 67 instructions. 1 loops. 1712 cycles. 0:0 spills:fills, 3 sends, scheduled with mode top-down. Promot | SIMD16 shader: 66 instructions. 1 loops. 1628 cycles. 0:0 spills:fills, 3 sends, scheduled with mode top-down. Promot START B0 (362 cycles) | START B0 (358 cycles) mov(8) g3<1>UW 0x76543210V { align1 WE_all 1Q }; mov(8) g3<1>UW 0x76543210V { align1 WE_all 1Q }; mov(16) g81<1>UD g0.1<0,1,0>UD { align1 1H compacted }; | mov(16) g79<1>UD g0.1<0,1,0>UD { align1 1H compacted }; mov(16) g83<1>UD g0.6<0,1,0>UD { align1 1H }; | mov(16) g81<1>UD g0.6<0,1,0>UD { align1 1H }; mov(16) g4<1>UD g0.7<0,1,0>UD { align1 1H }; mov(16) g4<1>UD g0.7<0,1,0>UD { align1 1H }; mov(16) g6<1>UD 0xffffffffUD { align1 1H compacted }; mov(16) g6<1>UD 0xffffffffUD { align1 1H compacted }; mov(16) g8<1>UD 0xffffffffUD { align1 1H compacted }; | mov(16) g83<1>UD 0x00000000UD { align1 1H compacted }; mov(16) g85<1>UD 0x00000000UD { align1 1H compacted }; < add(8) g3.8<1>UW g3<8,8,1>UW 0x0008UW { align1 WE_all 1Q }; add(8) g3.8<1>UW g3<8,8,1>UW 0x0008UW { align1 WE_all 1Q }; send(16) g10<1>UW g85<0,1,0>UD 0x04605800 | send(16) g8<1>UW g83<0,1,0>UD 0x04605800 dp data 1 MsgDesc: ( untyped surface read, Surface = 0, SIMD16, Mask = 0x8) mlen 2 rlen 6 dp data 1 MsgDesc: ( untyped surface read, Surface = 0, SIMD16, Mask = 0x8) mlen 2 rlen 6 add(16) g16<1>D g81<8,8,1>D g1.6<0,1,0>D { align1 1H compacted }; | add(16) g14<1>D g79<8,8,1>D g1.6<0,1,0>D { align1 1H compacted }; add(16) g18<1>D g83<8,8,1>D g1.7<0,1,0>D { align1 1H compacted }; | add(16) g16<1>D g81<8,8,1>D g1.7<0,1,0>D { align1 1H compacted }; add(16) g20<1>D g4<8,8,1>D g2<0,1,0>D { align1 1H compacted }; | add(16) g18<1>D g4<8,8,1>D g2<0,1,0>D { align1 1H compacted }; shl(16) g22<1>D g2.1<0,1,0>D 0x00000004UD { align1 1H }; | shl(16) g20<1>D g2.1<0,1,0>D 0x00000004UD { align1 1H }; mov(16) g24<1>D g3<8,8,1>UW { align1 1H }; | mov(16) g22<1>D g3<8,8,1>UW { align1 1H }; shl(16) g32<1>D g16<8,8,1>D 0x00000005UD { align1 1H }; | shl(16) g30<1>D g14<8,8,1>D 0x00000005UD { align1 1H }; add(16) g26<1>D g24<8,8,1>D g22<8,8,1>D { align1 1H compacted }; | mov(1) g3.1<1>D 1D { align1 WE_all 1N }; add(16) g46<1>D g24<8,8,1>D 1D { align1 1H compacted }; | add(16) g24<1>D g22<8,8,1>D g20<8,8,1>D { align1 1H compacted }; add(16) g48<1>D -g24<8,8,1>D 31D { align1 1H compacted }; | add(16) g44<1>D g22<8,8,1>D 1D { align1 1H compacted }; mov(1) g60<2>UW 0x00000000UD { align1 WE_all 1N }; | add(16) g46<1>D -g22<8,8,1>D 31D { align1 1H compacted }; and(16) g28<1>UD g26<8,8,1>UD 0x0000001fUD { align1 1H compacted }; | mov(1) g58<2>UW 0x00000000UD { align1 WE_all 1N }; shr(16) g30<1>UD g26<8,8,1>UD 0x00000005UD { align1 1H compacted }; | and(16) g26<1>UD g24<8,8,1>UD 0x0000001fUD { align1 1H compacted }; shr(16) g50<1>UD g6<8,8,1>UD g48<8,8,1>UD { align1 1H compacted }; | shr(16) g28<1>UD g24<8,8,1>UD 0x00000005UD { align1 1H compacted }; add(16) g34<1>D g32<8,8,1>D g28<8,8,1>D { align1 1H compacted }; | shr(16) g48<1>D -g3.1<0,1,0>D g46<8,8,1>D { align1 1H compacted }; add(16) g36<1>D g20<8,8,1>D g30<8,8,1>D { align1 1H compacted }; | add(16) g32<1>D g30<8,8,1>D g26<8,8,1>D { align1 1H compacted }; cbit(16) g52<1>UD g50<8,8,1>UD { align1 1H compacted }; | add(16) g34<1>D g18<8,8,1>D g28<8,8,1>D { align1 1H compacted }; cmp.z.f0.0(16) g54<1>D g46<8,8,1>D g52<8,8,1>D { align1 1H compacted }; | cbit(16) g50<1>UD g48<8,8,1>UD { align1 1H compacted }; mov(16) g56<1>D -g54<8,8,1>D { align1 1H compacted }; | cmp.z.f0.0(16) g52<1>D g44<8,8,1>D g50<8,8,1>D { align1 1H compacted }; or(16) g58<1>UD g56<8,8,1>UD 0x00000002UD { align1 1H compacted }; | mov(16) g54<1>D -g52<8,8,1>D { align1 1H compacted }; mul(16) g38<1>D g12<8,8,1>D g36<16,8,2>UW { align1 1H }; | or(16) g56<1>UD g54<8,8,1>UD 0x00000002UD { align1 1H compacted }; mul(16) g3<1>D g12<8,8,1>D g36.1<16,8,2>UW { align1 1H }; | mul(16) g36<1>D g10<8,8,1>D g34<16,8,2>UW { align1 1H }; shl(16) g1<1>D g10<8,8,1>D 0x00000005UD { align1 1H }; | mul(16) g4<1>D g10<8,8,1>D g34.1<16,8,2>UW { align1 1H }; add(16) g38.1<2>UW g38.1<16,8,2>UW g3<16,8,2>UW { align1 1H }; | shl(16) g1<1>D g8<8,8,1>D 0x00000005UD { align1 1H }; add(16) g40<1>D g38<8,8,1>D g18<8,8,1>D { align1 1H compacted }; | add(16) g36.1<2>UW g36.1<16,8,2>UW g4<16,8,2>UW { align1 1H }; mul(16) g42<1>D g1<8,8,1>D g40<16,8,2>UW { align1 1H }; | add(16) g38<1>D g36<8,8,1>D g16<8,8,1>D { align1 1H compacted }; mul(16) g4<1>D g1<8,8,1>D g40.1<16,8,2>UW { align1 1H }; | mul(16) g40<1>D g1<8,8,1>D g38<16,8,2>UW { align1 1H }; add(16) g42.1<2>UW g42.1<16,8,2>UW g4<16,8,2>UW { align1 1H }; | mul(16) g8<1>D g1<8,8,1>D g38.1<16,8,2>UW { align1 1H }; add(16) g44<1>D g42<8,8,1>D g34<8,8,1>D { align1 1H compacted }; | add(16) g40.1<2>UW g40.1<16,8,2>UW g8<16,8,2>UW { align1 1H }; mov(1) f0<1>UW g60<0,1,0>UW { align1 WE_all 1N }; | add(16) g42<1>D g40<8,8,1>D g32<8,8,1>D { align1 1H compacted }; cmp.nz.f0.0(16) null<1>UD g8<8,8,1>UD 0x00000000UD { align1 1H compacted }; | mov(1) f0<1>UW g58<0,1,0>UW { align1 WE_all 1N }; mov(16) g60<1>UD f0<0,1,0>UW { align1 1H }; | cmp.nz.f0.0(16) null<1>UD g6<8,8,1>UD 0x00000000UD { align1 1H compacted }; mov(1) g1<1>UD 0x00000000UD { align1 WE_all 1N compacted }; | mov(16) g58<1>UD f0<0,1,0>UW { align1 1H }; > mov(1) g3<1>UD 0x00000000UD { align1 WE_all 1N compacted }; mov(16) g5<1>UD 0x00000000UD { align1 1H compacted }; mov(16) g5<1>UD 0x00000000UD { align1 1H compacted }; and(16) g62<1>UD g60<8,8,1>UD g50<8,8,1>UD { align1 1H compacted }; | and(16) g60<1>UD g58<8,8,1>UD g48<8,8,1>UD { align1 1H compacted }; cbit(16) g64<1>UD g62<8,8,1>UD { align1 1H compacted }; | cbit(16) g62<1>UD g60<8,8,1>UD { align1 1H compacted }; cmp.g.f0.0(16) null<1>UD g64<8,8,1>UD 0x00000000UD { align1 1H compacted }; | cmp.g.f0.0(16) null<1>UD g62<8,8,1>UD 0x00000000UD { align1 1H compacted }; (-f0.0) sel(16) g65<1>UD g1<0,1,0>UD 0x00000004UD { align1 1H }; | (-f0.0) sel(16) g63<1>UD g3<0,1,0>UD 0x00000004UD { align1 1H }; or(16) g67<1>UD g58<8,8,1>UD g65<8,8,1>UD { align1 1H compacted }; | or(16) g65<1>UD g56<8,8,1>UD g63<8,8,1>UD { align1 1H compacted }; or(16) g88<1>UD g67<8,8,1>UD 0x00000008UD { align1 1H compacted }; | or(16) g86<1>UD g65<8,8,1>UD 0x00000008UD { align1 1H compacted }; END B0 ->B1 END B0 ->B1 START B2 <-B1 <-B3 (260 cycles) START B2 <-B1 <-B3 (260 cycles) LABEL1: LABEL1: cmp.ge.f0.0(16) null<1>UD g5<8,8,1>UD 0x00000080UD { align1 1H compacted }; cmp.ge.f0.0(16) null<1>UD g5<8,8,1>UD 0x00000080UD { align1 1H compacted }; END B1 ->B2 ->B4 END B1 ->B2 ->B4 (+f0.0) break(16) JIP: LABEL0 UIP: LABEL0 { align1 1H }; (+f0.0) break(16) JIP: LABEL0 UIP: LABEL0 { align1 1H }; END B2 ->B1 ->B4 ->B3 END B2 ->B1 ->B4 ->B3 START B3 <-B2 (1060 cycles) | START B3 <-B2 (980 cycles) sel.l(16) g68<1>UD g46<8,8,1>UD g5<8,8,1>UD { align1 1H compacted }; | sel.l(16) g66<1>UD g44<8,8,1>UD g5<8,8,1>UD { align1 1H compacted }; mov(1) g1.1<1>D 1D { align1 WE_all 1N }; | shl(16) g70<1>D -g3.1<0,1,0>D g5<8,8,1>UD { align1 1H }; cmp.ge.f0.0(16) null<1>UD g5<8,8,1>UD 0x00000020UD { align1 1H compacted }; cmp.ge.f0.0(16) null<1>UD g5<8,8,1>UD 0x00000020UD { align1 1H compacted }; and(16) g80<1>UD g88<8,8,1>UD 0xfffffff7UD { align1 1H compacted }; | and(16) g78<1>UD g86<8,8,1>UD 0xfffffff7UD { align1 1H compacted }; add(16) g70<1>D g46<8,8,1>D -g68<8,8,1>D { align1 1H compacted }; < shl(16) g72<1>D -g1.1<0,1,0>D g5<8,8,1>UD { align1 1H }; < add(16) g5<1>D g5<8,8,1>D 1D { align1 1H compacted }; add(16) g5<1>D g5<8,8,1>D 1D { align1 1H compacted }; (-f0.0) sel(16) g74<1>UD g72<8,8,1>UD 0x00000000UD { align1 1H }; | add(16) g68<1>D g44<8,8,1>D -g66<8,8,1>D { align1 1H compacted }; and(16) g76<1>UD g74<8,8,1>UD g50<8,8,1>UD { align1 1H compacted }; | (-f0.0) sel(16) g72<1>UD g70<8,8,1>UD 0x00000000UD { align1 1H }; cbit(16) g78<1>UD g76<8,8,1>UD { align1 1H compacted }; | and(16) g74<1>UD g72<8,8,1>UD g48<8,8,1>UD { align1 1H compacted }; cmp.nz.f0.0(16) null<1>D g78<8,8,1>D g70<8,8,1>D { align1 1H compacted }; | cbit(16) g76<1>UD g74<8,8,1>UD { align1 1H compacted }; (+f0.0) sel(16) g88<1>UD g80<8,8,1>UD g88<8,8,1>UD { align1 1H compacted }; | cmp.nz.f0.0(16) null<1>D g76<8,8,1>D g68<8,8,1>D { align1 1H compacted }; > (+f0.0) sel(16) g86<1>UD g78<8,8,1>UD g86<8,8,1>UD { align1 1H compacted }; LABEL0: LABEL0: while(16) JIP: LABEL1 { align1 1H }; while(16) JIP: LABEL1 { align1 1H }; END B3 ->B2 END B3 ->B2 START B4 <-B1 <-B2 (30 cycles) START B4 <-B1 <-B2 (30 cycles) shl(16) g86<1>D g44<8,8,1>D 0x00000002UD { align1 1H }; | shl(16) g84<1>D g42<8,8,1>D 0x00000002UD { align1 1H }; sends(16) nullUD g86UD g88UD 0x04025e02 0x00000080 | sends(16) nullUD g84UD g86UD 0x04025e02 0x00000080 dp data 1 MsgDesc: ( DC untyped surface write, Surface = 2, SIMD16, Mask = 0xe) mlen 2 ex dp data 1 MsgDesc: ( DC untyped surface write, Surface = 2, SIMD16, Mask = 0xe) mlen 2 ex mov(8) g126<1>UD g0<8,8,1>UD { align1 WE_all 1Q compacted }; mov(8) g126<1>UD g0<8,8,1>UD { align1 WE_all 1Q compacted }; send(16) null<1>UW g126<8,8,1>UW 0x82000000 send(16) null<1>UW g126<8,8,1>UW 0x82000000 thread_spawner MsgDesc: mlen 1 rlen 0 { align1 WE_all 1H EOT }; thread_spawner MsgDesc: mlen 1 rlen 0 { align1 WE_all 1H EOT }; END B4 END B4 NIR (from SPIR-V) for MESA_SHADER_COMPUTE shader: NIR (from SPIR-V) for MESA_SHADER_COMPUTE shader: shader: MESA_SHADER_COMPUTE shader: MESA_SHADER_COMPUTE local-size: 1, 32, 1 local-size: 1, 32, 1 shared-size: 0 shared-size: 0 inputs: 0 inputs: 0 outputs: 0 outputs: 0 uniforms: 0 uniforms: 0 shared: 0 shared: 0 decl_var system INTERP_MODE_NONE uvec3 @0 decl_var system INTERP_MODE_NONE uvec3 @0 decl_var system INTERP_MODE_NONE uvec3 @1 decl_var system INTERP_MODE_NONE uvec3 @1 decl_var system INTERP_MODE_NONE uint @2 decl_var system INTERP_MODE_NONE uint @2 decl_var ssbo INTERP_MODE_NONE restrict block @3 (~0, 0, 0) decl_var ssbo INTERP_MODE_NONE restrict block @3 (~0, 0, 0) decl_function main (0 params) decl_function main (0 params) impl main { impl main { decl_var INTERP_MODE_NONE uvec3 @4 decl_var INTERP_MODE_NONE uvec3 @4 decl_var INTERP_MODE_NONE uint @5 decl_var INTERP_MODE_NONE uint @5 decl_var INTERP_MODE_NONE uvec4 @6 decl_var INTERP_MODE_NONE uvec4 @6 decl_var INTERP_MODE_NONE uvec4 @7 decl_var INTERP_MODE_NONE uvec4 @7 decl_var INTERP_MODE_NONE uint @8 decl_var INTERP_MODE_NONE uint @8 decl_var INTERP_MODE_NONE uint @9 decl_var INTERP_MODE_NONE uint @9 decl_var INTERP_MODE_NONE uint @10 decl_var INTERP_MODE_NONE uint @10 decl_var INTERP_MODE_NONE uint @11 decl_var INTERP_MODE_NONE uint @11 decl_var INTERP_MODE_NONE uvec4 @12 decl_var INTERP_MODE_NONE uvec4 @12 decl_var INTERP_MODE_NONE int @13 decl_var INTERP_MODE_NONE int @13 decl_var INTERP_MODE_NONE int @14 decl_var INTERP_MODE_NONE int @14 decl_var INTERP_MODE_NONE uint @15 decl_var INTERP_MODE_NONE uint @15 decl_var INTERP_MODE_NONE int @16 decl_var INTERP_MODE_NONE int @16 decl_var INTERP_MODE_NONE uint @17 decl_var INTERP_MODE_NONE uint @17 decl_var INTERP_MODE_NONE int @18 decl_var INTERP_MODE_NONE int @18 decl_var INTERP_MODE_NONE uint @19 decl_var INTERP_MODE_NONE uint @19 decl_var INTERP_MODE_NONE uint @20 decl_var INTERP_MODE_NONE uint @20 decl_var INTERP_MODE_NONE bool cont decl_var INTERP_MODE_NONE bool cont block block_0: block block_0: /* preds: */ /* preds: */ vec1 32 ssa_217 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_217 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_208 = load_const (0xfffffff7 /* -nan */) vec1 32 ssa_208 = load_const (0xfffffff7 /* -nan */) vec1 32 ssa_189 = load_const (0xffffffff /* -nan */) vec1 32 ssa_189 = load_const (0xffffffff /* -nan */) vec1 32 ssa_184 = load_const (0x00000060 /* 0.000000 */) vec1 32 ssa_184 = load_const (0x00000060 /* 0.000000 */) vec1 32 ssa_180 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_180 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_178 = load_const (0x00000060 /* 0.000000 */) vec1 32 ssa_178 = load_const (0x00000060 /* 0.000000 */) vec1 32 ssa_174 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_174 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_172 = load_const (0x00000080 /* 0.000000 */) vec1 32 ssa_172 = load_const (0x00000080 /* 0.000000 */) vec1 32 ssa_164 = load_const (0xffffffff /* -nan */) vec1 32 ssa_164 = load_const (0xffffffff /* -nan */) vec1 32 ssa_159 = load_const (0x00000040 /* 0.000000 */) vec1 32 ssa_159 = load_const (0x00000040 /* 0.000000 */) vec1 32 ssa_155 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_155 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_153 = load_const (0x00000040 /* 0.000000 */) vec1 32 ssa_153 = load_const (0x00000040 /* 0.000000 */) vec1 32 ssa_149 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_149 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_147 = load_const (0x00000060 /* 0.000000 */) vec1 32 ssa_147 = load_const (0x00000060 /* 0.000000 */) vec1 32 ssa_139 = load_const (0xffffffff /* -nan */) vec1 32 ssa_139 = load_const (0xffffffff /* -nan */) vec1 32 ssa_134 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_134 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_130 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_130 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_128 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_128 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_124 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_124 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_122 = load_const (0x00000040 /* 0.000000 */) vec1 32 ssa_122 = load_const (0x00000040 /* 0.000000 */) vec1 32 ssa_114 = load_const (0xffffffff /* -nan */) vec1 32 ssa_114 = load_const (0xffffffff /* -nan */) vec1 32 ssa_110 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_110 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_108 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_108 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_95 = load_const (0x00000080 /* 0.000000 */) vec1 32 ssa_95 = load_const (0x00000080 /* 0.000000 */) vec1 32 ssa_91 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_91 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_88 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_88 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_79 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_79 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_78 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_78 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_76 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_76 = load_const (0x00000000 /* 0.000000 */) vec1 1 ssa_73 = load_const (true) vec1 1 ssa_73 = load_const (true) vec1 32 ssa_66 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_66 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_65 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_65 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_63 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_63 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_53 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_53 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_52 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_52 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_43 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_43 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_39 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_39 = load_const (0x00000000 /* 0.000000 */) vec4 32 ssa_37 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, vec4 32 ssa_37 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, vec4 32 ssa_35 = load_const (0xffffffff /* -nan */, 0xffffffff /* -nan */, 0xffffffff /* -nan */, 0xffffffff vec4 32 ssa_35 = load_const (0xffffffff /* -nan */, 0xffffffff /* -nan */, 0xffffffff /* -nan */, 0xffffffff vec3 32 ssa_2 = load_const (0x00000001 /* 0.000000 */, 0x00000020 /* 0.000000 */, 0x00000001 /* 0.000000 */) vec3 32 ssa_2 = load_const (0x00000001 /* 0.000000 */, 0x00000020 /* 0.000000 */, 0x00000001 /* 0.000000 */) vec1 32 ssa_0 = deref_var &@0 (system uvec3) vec1 32 ssa_0 = deref_var &@0 (system uvec3) vec3 32 ssa_1 = intrinsic load_deref (ssa_0) (0) /* access=0 */ vec3 32 ssa_1 = intrinsic load_deref (ssa_0) (0) /* access=0 */ vec3 32 ssa_3 = imul ssa_1, ssa_2 vec3 32 ssa_3 = imul ssa_1, ssa_2 vec1 32 ssa_4 = deref_var &@4 (function_temp uvec3) vec1 32 ssa_4 = deref_var &@4 (function_temp uvec3) intrinsic store_deref (ssa_4, ssa_3) (7, 0) /* wrmask=xyz */ /* access=0 */ intrinsic store_deref (ssa_4, ssa_3) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_5 = deref_var &@4 (function_temp uvec3) vec1 32 ssa_5 = deref_var &@4 (function_temp uvec3) vec3 32 ssa_8 = intrinsic load_deref (ssa_5) (0) /* access=0 */ vec3 32 ssa_8 = intrinsic load_deref (ssa_5) (0) /* access=0 */ vec1 32 ssa_9 = mov ssa_8.x vec1 32 ssa_9 = mov ssa_8.x vec1 32 ssa_10 = deref_var &@4 (function_temp uvec3) vec1 32 ssa_10 = deref_var &@4 (function_temp uvec3) vec3 32 ssa_13 = intrinsic load_deref (ssa_10) (0) /* access=0 */ vec3 32 ssa_13 = intrinsic load_deref (ssa_10) (0) /* access=0 */ vec1 32 ssa_14 = mov ssa_13.y vec1 32 ssa_14 = mov ssa_13.y vec1 32 ssa_15 = deref_var &@1 (system uvec3) vec1 32 ssa_15 = deref_var &@1 (system uvec3) vec3 32 ssa_18 = intrinsic load_deref (ssa_15) (0) /* access=0 */ vec3 32 ssa_18 = intrinsic load_deref (ssa_15) (0) /* access=0 */ vec1 32 ssa_19 = mov ssa_18.z vec1 32 ssa_19 = mov ssa_18.z vec1 32 ssa_20 = imul ssa_14, ssa_19 vec1 32 ssa_20 = imul ssa_14, ssa_19 vec1 32 ssa_21 = deref_var &@1 (system uvec3) vec1 32 ssa_21 = deref_var &@1 (system uvec3) vec3 32 ssa_24 = intrinsic load_deref (ssa_21) (0) /* access=0 */ vec3 32 ssa_24 = intrinsic load_deref (ssa_21) (0) /* access=0 */ vec1 32 ssa_25 = mov ssa_24.y vec1 32 ssa_25 = mov ssa_24.y vec1 32 ssa_26 = iadd ssa_20, ssa_25 vec1 32 ssa_26 = iadd ssa_20, ssa_25 vec1 32 ssa_27 = imul ssa_9, ssa_26 vec1 32 ssa_27 = imul ssa_9, ssa_26 vec1 32 ssa_28 = deref_var &@1 (system uvec3) vec1 32 ssa_28 = deref_var &@1 (system uvec3) vec3 32 ssa_31 = intrinsic load_deref (ssa_28) (0) /* access=0 */ vec3 32 ssa_31 = intrinsic load_deref (ssa_28) (0) /* access=0 */ vec1 32 ssa_32 = mov ssa_31.x vec1 32 ssa_32 = mov ssa_31.x vec1 32 ssa_33 = iadd ssa_27, ssa_32 vec1 32 ssa_33 = iadd ssa_27, ssa_32 vec1 32 ssa_34 = deref_var &@5 (function_temp uint) vec1 32 ssa_34 = deref_var &@5 (function_temp uint) intrinsic store_deref (ssa_34, ssa_33) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_34, ssa_33) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_36 = deref_var &@6 (function_temp uvec4) vec1 32 ssa_36 = deref_var &@6 (function_temp uvec4) intrinsic store_deref (ssa_36, ssa_35) (15, 0) /* wrmask=xyzw */ /* access=0 */ intrinsic store_deref (ssa_36, ssa_35) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_38 = deref_var &@7 (function_temp uvec4) vec1 32 ssa_38 = deref_var &@7 (function_temp uvec4) intrinsic store_deref (ssa_38, ssa_37) (15, 0) /* wrmask=xyzw */ /* access=0 */ intrinsic store_deref (ssa_38, ssa_37) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_40 = deref_var &@8 (function_temp uint) vec1 32 ssa_40 = deref_var &@8 (function_temp uint) intrinsic store_deref (ssa_40, ssa_39) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_40, ssa_39) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_41 = deref_var &@2 (system uint) vec1 32 ssa_41 = deref_var &@2 (system uint) vec1 32 ssa_42 = intrinsic load_deref (ssa_41) (0) /* access=0 */ vec1 32 ssa_42 = intrinsic load_deref (ssa_41) (0) /* access=0 */ vec1 32 ssa_44 = iadd ssa_42, ssa_43 vec1 32 ssa_44 = iadd ssa_42, ssa_43 vec1 32 ssa_45 = deref_var &@9 (function_temp uint) vec1 32 ssa_45 = deref_var &@9 (function_temp uint) intrinsic store_deref (ssa_45, ssa_44) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_45, ssa_44) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_46 = deref_var &@9 (function_temp uint) vec1 32 ssa_46 = deref_var &@9 (function_temp uint) vec1 32 ssa_47 = intrinsic load_deref (ssa_46) (0) /* access=0 */ vec1 32 ssa_47 = intrinsic load_deref (ssa_46) (0) /* access=0 */ vec1 32 ssa_48 = deref_var &@6 (function_temp uvec4) vec1 32 ssa_48 = deref_var &@6 (function_temp uvec4) vec4 32 ssa_49 = intrinsic load_deref (ssa_48) (0) /* access=0 */ vec4 32 ssa_49 = intrinsic load_deref (ssa_48) (0) /* access=0 */ vec1 32 ssa_50 = intrinsic ballot_bit_count_inclusive (ssa_49) () vec1 32 ssa_50 = intrinsic ballot_bit_count_inclusive (ssa_49) () vec1 1 ssa_51 = ieq ssa_47, ssa_50 vec1 1 ssa_51 = ieq ssa_47, ssa_50 vec1 32 ssa_54 = bcsel ssa_51, ssa_53, ssa_52 vec1 32 ssa_54 = bcsel ssa_51, ssa_53, ssa_52 vec1 32 ssa_55 = mov ssa_54 vec1 32 ssa_55 = mov ssa_54 vec1 32 ssa_56 = deref_var &@8 (function_temp uint) vec1 32 ssa_56 = deref_var &@8 (function_temp uint) vec1 32 ssa_57 = intrinsic load_deref (ssa_56) (0) /* access=0 */ vec1 32 ssa_57 = intrinsic load_deref (ssa_56) (0) /* access=0 */ vec1 32 ssa_58 = ior ssa_57, ssa_55 vec1 32 ssa_58 = ior ssa_57, ssa_55 vec1 32 ssa_59 = deref_var &@8 (function_temp uint) vec1 32 ssa_59 = deref_var &@8 (function_temp uint) intrinsic store_deref (ssa_59, ssa_58) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_59, ssa_58) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_60 = deref_var &@7 (function_temp uvec4) vec1 32 ssa_60 = deref_var &@7 (function_temp uvec4) vec4 32 ssa_61 = intrinsic load_deref (ssa_60) (0) /* access=0 */ vec4 32 ssa_61 = intrinsic load_deref (ssa_60) (0) /* access=0 */ vec1 32 ssa_62 = intrinsic ballot_bit_count_inclusive (ssa_61) () vec1 32 ssa_62 = intrinsic ballot_bit_count_inclusive (ssa_61) () vec1 1 ssa_64 = ieq ssa_63, ssa_62 vec1 1 ssa_64 = ieq ssa_63, ssa_62 vec1 32 ssa_67 = bcsel ssa_64, ssa_66, ssa_65 vec1 32 ssa_67 = bcsel ssa_64, ssa_66, ssa_65 vec1 32 ssa_68 = mov ssa_67 vec1 32 ssa_68 = mov ssa_67 vec1 32 ssa_69 = deref_var &@8 (function_temp uint) vec1 32 ssa_69 = deref_var &@8 (function_temp uint) vec1 32 ssa_70 = intrinsic load_deref (ssa_69) (0) /* access=0 */ vec1 32 ssa_70 = intrinsic load_deref (ssa_69) (0) /* access=0 */ vec1 32 ssa_71 = ior ssa_70, ssa_68 vec1 32 ssa_71 = ior ssa_70, ssa_68 vec1 32 ssa_72 = deref_var &@8 (function_temp uint) vec1 32 ssa_72 = deref_var &@8 (function_temp uint) intrinsic store_deref (ssa_72, ssa_71) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_72, ssa_71) (1, 0) /* wrmask=x */ /* access=0 */ vec4 32 ssa_74 = intrinsic ballot (ssa_73) () vec4 32 ssa_74 = intrinsic ballot (ssa_73) () vec1 32 ssa_75 = intrinsic ballot_bit_count_inclusive (ssa_74) () vec1 32 ssa_75 = intrinsic ballot_bit_count_inclusive (ssa_74) () vec1 1 ssa_77 = ult ssa_76, ssa_75 vec1 1 ssa_77 = ult ssa_76, ssa_75 vec1 32 ssa_80 = bcsel ssa_77, ssa_79, ssa_78 vec1 32 ssa_80 = bcsel ssa_77, ssa_79, ssa_78 vec1 32 ssa_81 = mov ssa_80 vec1 32 ssa_81 = mov ssa_80 vec1 32 ssa_82 = deref_var &@8 (function_temp uint) vec1 32 ssa_82 = deref_var &@8 (function_temp uint) vec1 32 ssa_83 = intrinsic load_deref (ssa_82) (0) /* access=0 */ vec1 32 ssa_83 = intrinsic load_deref (ssa_82) (0) /* access=0 */ vec1 32 ssa_84 = ior ssa_83, ssa_81 vec1 32 ssa_84 = ior ssa_83, ssa_81 vec1 32 ssa_85 = deref_var &@8 (function_temp uint) vec1 32 ssa_85 = deref_var &@8 (function_temp uint) intrinsic store_deref (ssa_85, ssa_84) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_85, ssa_84) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_86 = deref_var &@8 (function_temp uint) vec1 32 ssa_86 = deref_var &@8 (function_temp uint) vec1 32 ssa_87 = intrinsic load_deref (ssa_86) (0) /* access=0 */ vec1 32 ssa_87 = intrinsic load_deref (ssa_86) (0) /* access=0 */ vec1 32 ssa_89 = ior ssa_87, ssa_88 vec1 32 ssa_89 = ior ssa_87, ssa_88 vec1 32 ssa_90 = deref_var &@8 (function_temp uint) vec1 32 ssa_90 = deref_var &@8 (function_temp uint) intrinsic store_deref (ssa_90, ssa_89) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_90, ssa_89) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_92 = deref_var &@10 (function_temp uint) vec1 32 ssa_92 = deref_var &@10 (function_temp uint) intrinsic store_deref (ssa_92, ssa_91) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_92, ssa_91) (1, 0) /* wrmask=x */ /* access=0 */ vec1 1 ssa_211 = load_const (false) vec1 1 ssa_211 = load_const (false) vec1 32 ssa_212 = deref_var &cont (function_temp bool) vec1 32 ssa_212 = deref_var &cont (function_temp bool) intrinsic store_deref (ssa_212, ssa_211) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_212, ssa_211) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_1 */ /* succs: block_1 */ loop { loop { block block_1: block block_1: /* preds: block_0 block_29 block_31 */ /* preds: block_0 block_29 block_31 */ vec1 32 ssa_213 = deref_var &cont (function_temp bool) vec1 32 ssa_213 = deref_var &cont (function_temp bool) vec1 1 ssa_214 = intrinsic load_deref (ssa_213) (0) /* access=0 */ vec1 1 ssa_214 = intrinsic load_deref (ssa_213) (0) /* access=0 */ /* succs: block_2 block_3 */ /* succs: block_2 block_3 */ if ssa_214 { if ssa_214 { block block_2: block block_2: /* preds: block_1 */ /* preds: block_1 */ vec1 32 ssa_215 = deref_var &@10 (function_temp uint) vec1 32 ssa_215 = deref_var &@10 (function_temp uint) vec1 32 ssa_216 = intrinsic load_deref (ssa_215) (0) /* access=0 */ vec1 32 ssa_216 = intrinsic load_deref (ssa_215) (0) /* access=0 */ vec1 32 ssa_218 = iadd ssa_216, ssa_217 vec1 32 ssa_218 = iadd ssa_216, ssa_217 vec1 32 ssa_219 = deref_var &@10 (function_temp uint) vec1 32 ssa_219 = deref_var &@10 (function_temp uint) intrinsic store_deref (ssa_219, ssa_218) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_219, ssa_218) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_4 */ /* succs: block_4 */ } else { } else { block block_3: block block_3: /* preds: block_1 */ /* preds: block_1 */ /* succs: block_4 */ /* succs: block_4 */ } } block block_4: block block_4: /* preds: block_2 block_3 */ /* preds: block_2 block_3 */ vec1 1 ssa_220 = load_const (true) vec1 1 ssa_220 = load_const (true) vec1 32 ssa_221 = deref_var &cont (function_temp bool) vec1 32 ssa_221 = deref_var &cont (function_temp bool) intrinsic store_deref (ssa_221, ssa_220) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_221, ssa_220) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_93 = deref_var &@10 (function_temp uint) vec1 32 ssa_93 = deref_var &@10 (function_temp uint) vec1 32 ssa_94 = intrinsic load_deref (ssa_93) (0) /* access=0 */ vec1 32 ssa_94 = intrinsic load_deref (ssa_93) (0) /* access=0 */ vec1 1 ssa_96 = ult ssa_94, ssa_95 vec1 1 ssa_96 = ult ssa_94, ssa_95 /* succs: block_5 block_30 */ /* succs: block_5 block_30 */ if ssa_96 { if ssa_96 { block block_5: block block_5: /* preds: block_4 */ /* preds: block_4 */ vec1 32 ssa_97 = deref_var &@9 (function_temp uint) vec1 32 ssa_97 = deref_var &@9 (function_temp uint) vec1 32 ssa_98 = intrinsic load_deref (ssa_97) (0) /* access=0 */ vec1 32 ssa_98 = intrinsic load_deref (ssa_97) (0) /* access=0 */ vec1 32 ssa_99 = deref_var &@9 (function_temp uint) vec1 32 ssa_99 = deref_var &@9 (function_temp uint) vec1 32 ssa_100 = intrinsic load_deref (ssa_99) (0) /* access=0 */ vec1 32 ssa_100 = intrinsic load_deref (ssa_99) (0) /* access=0 */ vec1 32 ssa_101 = deref_var &@10 (function_temp uint) vec1 32 ssa_101 = deref_var &@10 (function_temp uint) vec1 32 ssa_102 = intrinsic load_deref (ssa_101) (0) /* access=0 */ vec1 32 ssa_102 = intrinsic load_deref (ssa_101) (0) /* access=0 */ vec1 32 ssa_103 = umin ssa_100, ssa_102 vec1 32 ssa_103 = umin ssa_100, ssa_102 vec1 32 ssa_104 = isub ssa_98, ssa_103 vec1 32 ssa_104 = isub ssa_98, ssa_103 vec1 32 ssa_105 = deref_var &@11 (function_temp uint) vec1 32 ssa_105 = deref_var &@11 (function_temp uint) intrinsic store_deref (ssa_105, ssa_104) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_105, ssa_104) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_106 = deref_var &@10 (function_temp uint) vec1 32 ssa_106 = deref_var &@10 (function_temp uint) vec1 32 ssa_107 = intrinsic load_deref (ssa_106) (0) /* access=0 */ vec1 32 ssa_107 = intrinsic load_deref (ssa_106) (0) /* access=0 */ vec1 1 ssa_109 = uge ssa_107, ssa_108 vec1 1 ssa_109 = uge ssa_107, ssa_108 /* succs: block_6 block_7 */ /* succs: block_6 block_7 */ if ssa_109 { if ssa_109 { block block_6: block block_6: /* preds: block_5 */ /* preds: block_5 */ vec1 32 ssa_111 = deref_var &@13 (function_temp int) vec1 32 ssa_111 = deref_var &@13 (function_temp int) intrinsic store_deref (ssa_111, ssa_110) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_111, ssa_110) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_8 */ /* succs: block_8 */ } else { } else { block block_7: block block_7: /* preds: block_5 */ /* preds: block_5 */ vec1 32 ssa_112 = deref_var &@10 (function_temp uint) vec1 32 ssa_112 = deref_var &@10 (function_temp uint) vec1 32 ssa_113 = intrinsic load_deref (ssa_112) (0) /* access=0 */ vec1 32 ssa_113 = intrinsic load_deref (ssa_112) (0) /* access=0 */ vec1 32 ssa_115 = ishl ssa_114, ssa_113 vec1 32 ssa_115 = ishl ssa_114, ssa_113 vec1 32 ssa_116 = deref_var &@13 (function_temp int) vec1 32 ssa_116 = deref_var &@13 (function_temp int) intrinsic store_deref (ssa_116, ssa_115) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_116, ssa_115) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_8 */ /* succs: block_8 */ } } block block_8: block block_8: /* preds: block_6 block_7 */ /* preds: block_6 block_7 */ vec1 32 ssa_117 = deref_var &@13 (function_temp int) vec1 32 ssa_117 = deref_var &@13 (function_temp int) vec1 32 ssa_118 = intrinsic load_deref (ssa_117) (0) /* access=0 */ vec1 32 ssa_118 = intrinsic load_deref (ssa_117) (0) /* access=0 */ vec1 32 ssa_119 = mov ssa_118 vec1 32 ssa_119 = mov ssa_118 vec1 32 ssa_120 = deref_var &@10 (function_temp uint) vec1 32 ssa_120 = deref_var &@10 (function_temp uint) vec1 32 ssa_121 = intrinsic load_deref (ssa_120) (0) /* access=0 */ vec1 32 ssa_121 = intrinsic load_deref (ssa_120) (0) /* access=0 */ vec1 1 ssa_123 = uge ssa_121, ssa_122 vec1 1 ssa_123 = uge ssa_121, ssa_122 /* succs: block_9 block_10 */ /* succs: block_9 block_10 */ if ssa_123 { if ssa_123 { block block_9: block block_9: /* preds: block_8 */ /* preds: block_8 */ vec1 32 ssa_125 = deref_var &@14 (function_temp int) vec1 32 ssa_125 = deref_var &@14 (function_temp int) intrinsic store_deref (ssa_125, ssa_124) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_125, ssa_124) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_14 */ /* succs: block_14 */ } else { } else { block block_10: block block_10: /* preds: block_8 */ /* preds: block_8 */ vec1 32 ssa_126 = deref_var &@10 (function_temp uint) vec1 32 ssa_126 = deref_var &@10 (function_temp uint) vec1 32 ssa_127 = intrinsic load_deref (ssa_126) (0) /* access=0 */ vec1 32 ssa_127 = intrinsic load_deref (ssa_126) (0) /* access=0 */ vec1 1 ssa_129 = ult ssa_127, ssa_128 vec1 1 ssa_129 = ult ssa_127, ssa_128 /* succs: block_11 block_12 */ /* succs: block_11 block_12 */ if ssa_129 { if ssa_129 { block block_11: block block_11: /* preds: block_10 */ /* preds: block_10 */ vec1 32 ssa_131 = deref_var &@15 (function_temp uint) vec1 32 ssa_131 = deref_var &@15 (function_temp uint) intrinsic store_deref (ssa_131, ssa_130) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_131, ssa_130) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_13 */ /* succs: block_13 */ } else { } else { block block_12: block block_12: /* preds: block_10 */ /* preds: block_10 */ vec1 32 ssa_132 = deref_var &@10 (function_temp uint) vec1 32 ssa_132 = deref_var &@10 (function_temp uint) vec1 32 ssa_133 = intrinsic load_deref (ssa_132) (0) /* access=0 */ vec1 32 ssa_133 = intrinsic load_deref (ssa_132) (0) /* access=0 */ vec1 32 ssa_135 = isub ssa_133, ssa_134 vec1 32 ssa_135 = isub ssa_133, ssa_134 vec1 32 ssa_136 = deref_var &@15 (function_temp uint) vec1 32 ssa_136 = deref_var &@15 (function_temp uint) intrinsic store_deref (ssa_136, ssa_135) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_136, ssa_135) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_13 */ /* succs: block_13 */ } } block block_13: block block_13: /* preds: block_11 block_12 */ /* preds: block_11 block_12 */ vec1 32 ssa_137 = deref_var &@15 (function_temp uint) vec1 32 ssa_137 = deref_var &@15 (function_temp uint) vec1 32 ssa_138 = intrinsic load_deref (ssa_137) (0) /* access=0 */ vec1 32 ssa_138 = intrinsic load_deref (ssa_137) (0) /* access=0 */ vec1 32 ssa_140 = ishl ssa_139, ssa_138 vec1 32 ssa_140 = ishl ssa_139, ssa_138 vec1 32 ssa_141 = deref_var &@14 (function_temp int) vec1 32 ssa_141 = deref_var &@14 (function_temp int) intrinsic store_deref (ssa_141, ssa_140) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_141, ssa_140) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_14 */ /* succs: block_14 */ } } block block_14: block block_14: /* preds: block_9 block_13 */ /* preds: block_9 block_13 */ vec1 32 ssa_142 = deref_var &@14 (function_temp int) vec1 32 ssa_142 = deref_var &@14 (function_temp int) vec1 32 ssa_143 = intrinsic load_deref (ssa_142) (0) /* access=0 */ vec1 32 ssa_143 = intrinsic load_deref (ssa_142) (0) /* access=0 */ vec1 32 ssa_144 = mov ssa_143 vec1 32 ssa_144 = mov ssa_143 vec1 32 ssa_145 = deref_var &@10 (function_temp uint) vec1 32 ssa_145 = deref_var &@10 (function_temp uint) vec1 32 ssa_146 = intrinsic load_deref (ssa_145) (0) /* access=0 */ vec1 32 ssa_146 = intrinsic load_deref (ssa_145) (0) /* access=0 */ vec1 1 ssa_148 = uge ssa_146, ssa_147 vec1 1 ssa_148 = uge ssa_146, ssa_147 /* succs: block_15 block_16 */ /* succs: block_15 block_16 */ if ssa_148 { if ssa_148 { block block_15: block block_15: /* preds: block_14 */ /* preds: block_14 */ vec1 32 ssa_150 = deref_var &@16 (function_temp int) vec1 32 ssa_150 = deref_var &@16 (function_temp int) intrinsic store_deref (ssa_150, ssa_149) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_150, ssa_149) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_20 */ /* succs: block_20 */ } else { } else { block block_16: block block_16: /* preds: block_14 */ /* preds: block_14 */ vec1 32 ssa_151 = deref_var &@10 (function_temp uint) vec1 32 ssa_151 = deref_var &@10 (function_temp uint) vec1 32 ssa_152 = intrinsic load_deref (ssa_151) (0) /* access=0 */ vec1 32 ssa_152 = intrinsic load_deref (ssa_151) (0) /* access=0 */ vec1 1 ssa_154 = ult ssa_152, ssa_153 vec1 1 ssa_154 = ult ssa_152, ssa_153 /* succs: block_17 block_18 */ /* succs: block_17 block_18 */ if ssa_154 { if ssa_154 { block block_17: block block_17: /* preds: block_16 */ /* preds: block_16 */ vec1 32 ssa_156 = deref_var &@17 (function_temp uint) vec1 32 ssa_156 = deref_var &@17 (function_temp uint) intrinsic store_deref (ssa_156, ssa_155) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_156, ssa_155) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_19 */ /* succs: block_19 */ } else { } else { block block_18: block block_18: /* preds: block_16 */ /* preds: block_16 */ vec1 32 ssa_157 = deref_var &@10 (function_temp uint) vec1 32 ssa_157 = deref_var &@10 (function_temp uint) vec1 32 ssa_158 = intrinsic load_deref (ssa_157) (0) /* access=0 */ vec1 32 ssa_158 = intrinsic load_deref (ssa_157) (0) /* access=0 */ vec1 32 ssa_160 = isub ssa_158, ssa_159 vec1 32 ssa_160 = isub ssa_158, ssa_159 vec1 32 ssa_161 = deref_var &@17 (function_temp uint) vec1 32 ssa_161 = deref_var &@17 (function_temp uint) intrinsic store_deref (ssa_161, ssa_160) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_161, ssa_160) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_19 */ /* succs: block_19 */ } } block block_19: block block_19: /* preds: block_17 block_18 */ /* preds: block_17 block_18 */ vec1 32 ssa_162 = deref_var &@17 (function_temp uint) vec1 32 ssa_162 = deref_var &@17 (function_temp uint) vec1 32 ssa_163 = intrinsic load_deref (ssa_162) (0) /* access=0 */ vec1 32 ssa_163 = intrinsic load_deref (ssa_162) (0) /* access=0 */ vec1 32 ssa_165 = ishl ssa_164, ssa_163 vec1 32 ssa_165 = ishl ssa_164, ssa_163 vec1 32 ssa_166 = deref_var &@16 (function_temp int) vec1 32 ssa_166 = deref_var &@16 (function_temp int) intrinsic store_deref (ssa_166, ssa_165) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_166, ssa_165) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_20 */ /* succs: block_20 */ } } block block_20: block block_20: /* preds: block_15 block_19 */ /* preds: block_15 block_19 */ vec1 32 ssa_167 = deref_var &@16 (function_temp int) vec1 32 ssa_167 = deref_var &@16 (function_temp int) vec1 32 ssa_168 = intrinsic load_deref (ssa_167) (0) /* access=0 */ vec1 32 ssa_168 = intrinsic load_deref (ssa_167) (0) /* access=0 */ vec1 32 ssa_169 = mov ssa_168 vec1 32 ssa_169 = mov ssa_168 vec1 32 ssa_170 = deref_var &@10 (function_temp uint) vec1 32 ssa_170 = deref_var &@10 (function_temp uint) vec1 32 ssa_171 = intrinsic load_deref (ssa_170) (0) /* access=0 */ vec1 32 ssa_171 = intrinsic load_deref (ssa_170) (0) /* access=0 */ vec1 1 ssa_173 = uge ssa_171, ssa_172 vec1 1 ssa_173 = uge ssa_171, ssa_172 /* succs: block_21 block_22 */ /* succs: block_21 block_22 */ if ssa_173 { if ssa_173 { block block_21: block block_21: /* preds: block_20 */ /* preds: block_20 */ vec1 32 ssa_175 = deref_var &@18 (function_temp int) vec1 32 ssa_175 = deref_var &@18 (function_temp int) intrinsic store_deref (ssa_175, ssa_174) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_175, ssa_174) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_26 */ /* succs: block_26 */ } else { } else { block block_22: block block_22: /* preds: block_20 */ /* preds: block_20 */ vec1 32 ssa_176 = deref_var &@10 (function_temp uint) vec1 32 ssa_176 = deref_var &@10 (function_temp uint) vec1 32 ssa_177 = intrinsic load_deref (ssa_176) (0) /* access=0 */ vec1 32 ssa_177 = intrinsic load_deref (ssa_176) (0) /* access=0 */ vec1 1 ssa_179 = ult ssa_177, ssa_178 vec1 1 ssa_179 = ult ssa_177, ssa_178 /* succs: block_23 block_24 */ /* succs: block_23 block_24 */ if ssa_179 { if ssa_179 { block block_23: block block_23: /* preds: block_22 */ /* preds: block_22 */ vec1 32 ssa_181 = deref_var &@19 (function_temp uint) vec1 32 ssa_181 = deref_var &@19 (function_temp uint) intrinsic store_deref (ssa_181, ssa_180) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_181, ssa_180) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_25 */ /* succs: block_25 */ } else { } else { block block_24: block block_24: /* preds: block_22 */ /* preds: block_22 */ vec1 32 ssa_182 = deref_var &@10 (function_temp uint) vec1 32 ssa_182 = deref_var &@10 (function_temp uint) vec1 32 ssa_183 = intrinsic load_deref (ssa_182) (0) /* access=0 */ vec1 32 ssa_183 = intrinsic load_deref (ssa_182) (0) /* access=0 */ vec1 32 ssa_185 = isub ssa_183, ssa_184 vec1 32 ssa_185 = isub ssa_183, ssa_184 vec1 32 ssa_186 = deref_var &@19 (function_temp uint) vec1 32 ssa_186 = deref_var &@19 (function_temp uint) intrinsic store_deref (ssa_186, ssa_185) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_186, ssa_185) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_25 */ /* succs: block_25 */ } } block block_25: block block_25: /* preds: block_23 block_24 */ /* preds: block_23 block_24 */ vec1 32 ssa_187 = deref_var &@19 (function_temp uint) vec1 32 ssa_187 = deref_var &@19 (function_temp uint) vec1 32 ssa_188 = intrinsic load_deref (ssa_187) (0) /* access=0 */ vec1 32 ssa_188 = intrinsic load_deref (ssa_187) (0) /* access=0 */ vec1 32 ssa_190 = ishl ssa_189, ssa_188 vec1 32 ssa_190 = ishl ssa_189, ssa_188 vec1 32 ssa_191 = deref_var &@18 (function_temp int) vec1 32 ssa_191 = deref_var &@18 (function_temp int) intrinsic store_deref (ssa_191, ssa_190) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_191, ssa_190) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_26 */ /* succs: block_26 */ } } block block_26: block block_26: /* preds: block_21 block_25 */ /* preds: block_21 block_25 */ vec1 32 ssa_192 = deref_var &@18 (function_temp int) vec1 32 ssa_192 = deref_var &@18 (function_temp int) vec1 32 ssa_193 = intrinsic load_deref (ssa_192) (0) /* access=0 */ vec1 32 ssa_193 = intrinsic load_deref (ssa_192) (0) /* access=0 */ vec1 32 ssa_194 = mov ssa_193 vec1 32 ssa_194 = mov ssa_193 vec4 32 ssa_195 = vec4 ssa_119, ssa_144, ssa_169, ssa_194 vec4 32 ssa_195 = vec4 ssa_119, ssa_144, ssa_169, ssa_194 vec1 32 ssa_196 = deref_var &@12 (function_temp uvec4) vec1 32 ssa_196 = deref_var &@12 (function_temp uvec4) intrinsic store_deref (ssa_196, ssa_195) (15, 0) /* wrmask=xyzw */ /* access=0 */ intrinsic store_deref (ssa_196, ssa_195) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_197 = deref_var &@12 (function_temp uvec4) vec1 32 ssa_197 = deref_var &@12 (function_temp uvec4) vec4 32 ssa_198 = intrinsic load_deref (ssa_197) (0) /* access=0 */ vec4 32 ssa_198 = intrinsic load_deref (ssa_197) (0) /* access=0 */ vec1 32 ssa_199 = intrinsic ballot_bit_count_inclusive (ssa_198) () vec1 32 ssa_199 = intrinsic ballot_bit_count_inclusive (ssa_198) () vec1 32 ssa_200 = deref_var &@20 (function_temp uint) vec1 32 ssa_200 = deref_var &@20 (function_temp uint) intrinsic store_deref (ssa_200, ssa_199) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_200, ssa_199) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_201 = deref_var &@20 (function_temp uint) vec1 32 ssa_201 = deref_var &@20 (function_temp uint) vec1 32 ssa_202 = intrinsic load_deref (ssa_201) (0) /* access=0 */ vec1 32 ssa_202 = intrinsic load_deref (ssa_201) (0) /* access=0 */ vec1 32 ssa_203 = deref_var &@11 (function_temp uint) vec1 32 ssa_203 = deref_var &@11 (function_temp uint) vec1 32 ssa_204 = intrinsic load_deref (ssa_203) (0) /* access=0 */ vec1 32 ssa_204 = intrinsic load_deref (ssa_203) (0) /* access=0 */ vec1 1 ssa_205 = ine ssa_202, ssa_204 vec1 1 ssa_205 = ine ssa_202, ssa_204 /* succs: block_27 block_28 */ /* succs: block_27 block_28 */ if ssa_205 { if ssa_205 { block block_27: block block_27: /* preds: block_26 */ /* preds: block_26 */ vec1 32 ssa_206 = deref_var &@8 (function_temp uint) vec1 32 ssa_206 = deref_var &@8 (function_temp uint) vec1 32 ssa_207 = intrinsic load_deref (ssa_206) (0) /* access=0 */ vec1 32 ssa_207 = intrinsic load_deref (ssa_206) (0) /* access=0 */ vec1 32 ssa_209 = iand ssa_207, ssa_208 vec1 32 ssa_209 = iand ssa_207, ssa_208 vec1 32 ssa_210 = deref_var &@8 (function_temp uint) vec1 32 ssa_210 = deref_var &@8 (function_temp uint) intrinsic store_deref (ssa_210, ssa_209) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_210, ssa_209) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_29 */ /* succs: block_29 */ } else { } else { block block_28: block block_28: /* preds: block_26 */ /* preds: block_26 */ /* succs: block_29 */ /* succs: block_29 */ } } block block_29: block block_29: /* preds: block_27 block_28 */ /* preds: block_27 block_28 */ continue continue /* succs: block_1 */ /* succs: block_1 */ } else { } else { block block_30: block block_30: /* preds: block_4 */ /* preds: block_4 */ break break /* succs: block_32 */ /* succs: block_32 */ } } block block_31: block block_31: /* preds: */ /* preds: */ /* succs: block_1 */ /* succs: block_1 */ } } block block_32: block block_32: /* preds: block_30 */ /* preds: block_30 */ vec1 32 ssa_222 = deref_var &@5 (function_temp uint) vec1 32 ssa_222 = deref_var &@5 (function_temp uint) vec1 32 ssa_223 = intrinsic load_deref (ssa_222) (0) /* access=0 */ vec1 32 ssa_223 = intrinsic load_deref (ssa_222) (0) /* access=0 */ vec1 32 ssa_224 = deref_var &@8 (function_temp uint) vec1 32 ssa_224 = deref_var &@8 (function_temp uint) vec1 32 ssa_225 = intrinsic load_deref (ssa_224) (0) /* access=0 */ vec1 32 ssa_225 = intrinsic load_deref (ssa_224) (0) /* access=0 */ vec1 32 ssa_226 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_226 = load_const (0x00000000 /* 0.000000 */) vec1 64 ssa_227 = intrinsic vulkan_resource_index (ssa_226) (0, 0, 7) /* desc-set=0 */ /* binding=0 */ /* des vec1 64 ssa_227 = intrinsic vulkan_resource_index (ssa_226) (0, 0, 7) /* desc-set=0 */ /* binding=0 */ /* des vec1 64 ssa_228 = intrinsic load_vulkan_descriptor (ssa_227) (7) /* desc_type=SSBO */ vec1 64 ssa_228 = intrinsic load_vulkan_descriptor (ssa_227) (7) /* desc_type=SSBO */ vec1 64 ssa_229 = deref_cast (block *)ssa_228 (ssbo block) /* ptr_stride=0, align_mul=0, align_offset=0 */ vec1 64 ssa_229 = deref_cast (block *)ssa_228 (ssbo block) /* ptr_stride=0, align_mul=0, align_offset=0 */ vec1 64 ssa_230 = deref_struct &ssa_229->field0 (ssbo uint[]) /* &((block *)ssa_228)->field0 */ vec1 64 ssa_230 = deref_struct &ssa_229->field0 (ssbo uint[]) /* &((block *)ssa_228)->field0 */ vec1 64 ssa_231 = i2i64 ssa_223 vec1 64 ssa_231 = i2i64 ssa_223 vec1 64 ssa_232 = deref_array &(*ssa_230)[ssa_231] (ssbo uint) /* &((block *)ssa_228)->field0[ssa_231] */ vec1 64 ssa_232 = deref_array &(*ssa_230)[ssa_231] (ssbo uint) /* &((block *)ssa_228)->field0[ssa_231] */ intrinsic store_deref (ssa_232, ssa_225) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_232, ssa_225) (1, 0) /* wrmask=x */ /* access=0 */ return return /* succs: block_33 */ /* succs: block_33 */ block block_33: block block_33: } } NIR (SSA form) for compute shader: NIR (SSA form) for compute shader: shader: MESA_SHADER_COMPUTE shader: MESA_SHADER_COMPUTE local-size: 1, 32, 1 local-size: 1, 32, 1 shared-size: 0 shared-size: 0 inputs: 0 inputs: 0 outputs: 0 outputs: 0 uniforms: 36 uniforms: 36 shared: 0 shared: 0 decl_var ssbo INTERP_MODE_NONE restrict block @0 (~0, 0, 0) decl_var ssbo INTERP_MODE_NONE restrict block @0 (~0, 0, 0) decl_function main (0 params) decl_function main (0 params) impl main { impl main { block block_0: block block_0: /* preds: */ /* preds: */ vec1 32 ssa_0 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_0 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_1 = load_const (0xfffffff7 /* -nan */) vec1 32 ssa_1 = load_const (0xfffffff7 /* -nan */) vec1 32 ssa_2 = load_const (0xffffffff /* -nan */) vec1 32 ssa_2 = load_const (0xffffffff /* -nan */) vec1 32 ssa_3 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_4 = load_const (0x00000080 /* 0.000000 */) vec1 32 ssa_4 = load_const (0x00000080 /* 0.000000 */) vec1 32 ssa_5 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_5 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_6 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_6 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_7 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_7 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_8 = load_const (0xffffffff /* -nan */) vec1 32 ssa_8 = load_const (0xffffffff /* -nan */) vec3 32 ssa_9 = intrinsic load_num_work_groups () () vec3 32 ssa_9 = intrinsic load_num_work_groups () () vec1 32 ssa_10 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_10 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_11 = ishl ssa_9.y, ssa_10 vec1 32 ssa_11 = ishl ssa_9.y, ssa_10 vec3 32 ssa_12 = intrinsic load_work_group_id () () vec3 32 ssa_12 = intrinsic load_work_group_id () () vec3 32 ssa_13 = intrinsic load_uniform (ssa_3) (24, 12, 0) /* base=24 */ /* range=12 */ /* dest_type=invalid vec3 32 ssa_13 = intrinsic load_uniform (ssa_3) (24, 12, 0) /* base=24 */ /* range=12 */ /* dest_type=invalid vec1 32 ssa_14 = iadd ssa_12.x, ssa_13.x vec1 32 ssa_14 = iadd ssa_12.x, ssa_13.x vec1 32 ssa_15 = iadd ssa_12.y, ssa_13.y vec1 32 ssa_15 = iadd ssa_12.y, ssa_13.y vec1 32 ssa_16 = iadd ssa_12.z, ssa_13.z vec1 32 ssa_16 = iadd ssa_12.z, ssa_13.z vec1 32 ssa_17 = intrinsic load_subgroup_id () () vec1 32 ssa_17 = intrinsic load_subgroup_id () () vec1 32 ssa_18 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_18 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_19 = ishl ssa_17, ssa_18 vec1 32 ssa_19 = ishl ssa_17, ssa_18 vec1 32 ssa_20 = intrinsic load_subgroup_invocation () () vec1 32 ssa_20 = intrinsic load_subgroup_invocation () () vec1 32 ssa_21 = iadd ssa_20, ssa_19 vec1 32 ssa_21 = iadd ssa_20, ssa_19 vec1 32 ssa_22 = load_const (0x0000001f /* 0.000000 */) vec1 32 ssa_22 = load_const (0x0000001f /* 0.000000 */) vec1 32 ssa_23 = iand ssa_21, ssa_22 vec1 32 ssa_23 = iand ssa_21, ssa_22 vec1 32 ssa_24 = ushr ssa_21, ssa_10 vec1 32 ssa_24 = ushr ssa_21, ssa_10 vec1 32 ssa_25 = ishl ssa_15, ssa_10 vec1 32 ssa_25 = ishl ssa_15, ssa_10 vec1 32 ssa_26 = iadd ssa_25, ssa_23 vec1 32 ssa_26 = iadd ssa_25, ssa_23 vec1 32 ssa_27 = iadd ssa_16, ssa_24 vec1 32 ssa_27 = iadd ssa_16, ssa_24 vec1 32 ssa_28 = imul ssa_11, ssa_27 vec1 32 ssa_28 = imul ssa_11, ssa_27 vec1 32 ssa_29 = iadd ssa_28, ssa_26 vec1 32 ssa_29 = iadd ssa_28, ssa_26 vec1 32 ssa_30 = imul ssa_9.x, ssa_29 vec1 32 ssa_30 = imul ssa_9.x, ssa_29 vec1 32 ssa_31 = iadd ssa_30, ssa_14 vec1 32 ssa_31 = iadd ssa_30, ssa_14 vec1 32 ssa_32 = iadd ssa_20, ssa_0 vec1 32 ssa_32 = iadd ssa_20, ssa_0 vec1 32 ssa_33 = ineg ssa_20 vec1 32 ssa_33 = ineg ssa_20 vec1 32 ssa_34 = iadd ssa_22, ssa_33 vec1 32 ssa_34 = iadd ssa_22, ssa_33 vec1 32 ssa_35 = ushr ssa_2, ssa_34 vec1 32 ssa_35 = ushr ssa_2, ssa_34 vec1 32 ssa_36 = bit_count ssa_35 vec1 32 ssa_36 = bit_count ssa_35 vec1 32 ssa_37 = ieq32 ssa_32, ssa_36 vec1 32 ssa_37 = ieq32 ssa_32, ssa_36 vec1 32 ssa_38 = b2i32 ssa_37 vec1 32 ssa_38 = b2i32 ssa_37 vec1 32 ssa_39 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_39 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_40 = ior ssa_38, ssa_39 vec1 32 ssa_40 = ior ssa_38, ssa_39 vec1 32 ssa_41 = intrinsic ballot (ssa_8) () vec1 32 ssa_41 = intrinsic ballot (ssa_8) () vec1 32 ssa_42 = iand ssa_41, ssa_35 vec1 32 ssa_42 = iand ssa_41, ssa_35 vec1 32 ssa_43 = bit_count ssa_42 vec1 32 ssa_43 = bit_count ssa_42 vec1 32 ssa_44 = ult32 ssa_3, ssa_43 vec1 32 ssa_44 = ult32 ssa_3, ssa_43 vec1 32 ssa_45 = b32csel ssa_44, ssa_7, ssa_3 vec1 32 ssa_45 = b32csel ssa_44, ssa_7, ssa_3 vec1 32 ssa_46 = ior ssa_40, ssa_45 vec1 32 ssa_46 = ior ssa_40, ssa_45 vec1 32 ssa_47 = ior ssa_46, ssa_6 vec1 32 ssa_47 = ior ssa_46, ssa_6 /* succs: block_1 */ /* succs: block_1 */ loop { loop { block block_1: block block_1: /* preds: block_0 block_4 */ /* preds: block_0 block_4 */ vec1 32 ssa_48 = phi block_0: ssa_47, block_4: ssa_61 vec1 32 ssa_48 = phi block_0: ssa_47, block_4: ssa_61 vec1 32 ssa_49 = phi block_0: ssa_3, block_4: ssa_62 vec1 32 ssa_49 = phi block_0: ssa_3, block_4: ssa_62 vec1 32 ssa_50 = uge32 ssa_49, ssa_4 vec1 32 ssa_50 = uge32 ssa_49, ssa_4 /* succs: block_2 block_3 */ /* succs: block_2 block_3 */ if ssa_50 { if ssa_50 { block block_2: block block_2: /* preds: block_1 */ /* preds: block_1 */ break break /* succs: block_5 */ /* succs: block_5 */ } else { } else { block block_3: block block_3: /* preds: block_1 */ /* preds: block_1 */ /* succs: block_4 */ /* succs: block_4 */ } } block block_4: block block_4: /* preds: block_3 */ /* preds: block_3 */ vec1 32 ssa_51 = umin ssa_32, ssa_49 vec1 32 ssa_51 = umin ssa_32, ssa_49 vec1 32 ssa_52 = ineg ssa_51 vec1 32 ssa_52 = ineg ssa_51 vec1 32 ssa_53 = iadd ssa_32, ssa_52 vec1 32 ssa_53 = iadd ssa_32, ssa_52 vec1 32 ssa_54 = ishl ssa_2, ssa_49 vec1 32 ssa_54 = ishl ssa_2, ssa_49 vec1 32 ssa_55 = uge32 ssa_49, ssa_5 vec1 32 ssa_55 = uge32 ssa_49, ssa_5 vec1 32 ssa_56 = b32csel ssa_55, ssa_3, ssa_54 vec1 32 ssa_56 = b32csel ssa_55, ssa_3, ssa_54 vec1 32 ssa_57 = iand ssa_56, ssa_35 vec1 32 ssa_57 = iand ssa_56, ssa_35 vec1 32 ssa_58 = bit_count ssa_57 vec1 32 ssa_58 = bit_count ssa_57 vec1 32 ssa_59 = iand ssa_48, ssa_1 vec1 32 ssa_59 = iand ssa_48, ssa_1 vec1 32 ssa_60 = ine32 ssa_58, ssa_53 vec1 32 ssa_60 = ine32 ssa_58, ssa_53 vec1 32 ssa_61 = b32csel ssa_60, ssa_59, ssa_48 vec1 32 ssa_61 = b32csel ssa_60, ssa_59, ssa_48 vec1 32 ssa_62 = iadd ssa_49, ssa_0 vec1 32 ssa_62 = iadd ssa_49, ssa_0 /* succs: block_1 */ /* succs: block_1 */ } } block block_5: block block_5: /* preds: block_2 */ /* preds: block_2 */ vec1 32 ssa_63 = ishl ssa_31, ssa_39 vec1 32 ssa_63 = ishl ssa_31, ssa_39 intrinsic store_ssbo (ssa_48, ssa_39, ssa_63) (1, 0, 4, 0) /* wrmask=x */ /* access=0 */ /* align_mul=4 */ /* intrinsic store_ssbo (ssa_48, ssa_39, ssa_63) (1, 0, 4, 0) /* wrmask=x */ /* access=0 */ /* align_mul=4 */ /* /* succs: block_6 */ /* succs: block_6 */ block block_6: block block_6: } } NIR (final form) for compute shader: NIR (final form) for compute shader: shader: MESA_SHADER_COMPUTE shader: MESA_SHADER_COMPUTE local-size: 1, 32, 1 local-size: 1, 32, 1 shared-size: 0 shared-size: 0 inputs: 0 inputs: 0 outputs: 0 outputs: 0 uniforms: 36 uniforms: 36 shared: 0 shared: 0 decl_var ssbo INTERP_MODE_NONE restrict block @0 (~0, 0, 0) decl_var ssbo INTERP_MODE_NONE restrict block @0 (~0, 0, 0) decl_function main (0 params) decl_function main (0 params) impl main { impl main { decl_reg vec1 32 r3 decl_reg vec1 32 r3 decl_reg vec1 32 r4 decl_reg vec1 32 r4 block block_0: block block_0: /* preds: */ /* preds: */ vec1 32 ssa_0 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_0 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_1 = load_const (0xfffffff7 /* -nan */) vec1 32 ssa_1 = load_const (0xfffffff7 /* -nan */) vec1 32 ssa_2 = load_const (0xffffffff /* -nan */) vec1 32 ssa_2 = load_const (0xffffffff /* -nan */) vec1 32 ssa_3 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_4 = load_const (0x00000080 /* 0.000000 */) vec1 32 ssa_4 = load_const (0x00000080 /* 0.000000 */) vec1 32 ssa_5 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_5 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_6 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_6 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_7 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_7 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_8 = load_const (0xffffffff /* -nan */) vec1 32 ssa_8 = load_const (0xffffffff /* -nan */) vec3 32 ssa_9 = intrinsic load_num_work_groups () () vec3 32 ssa_9 = intrinsic load_num_work_groups () () vec1 32 ssa_10 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_10 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_11 = ishl ssa_9.y, ssa_10 vec1 32 ssa_11 = ishl ssa_9.y, ssa_10 vec3 32 ssa_12 = intrinsic load_work_group_id () () vec3 32 ssa_12 = intrinsic load_work_group_id () () vec3 32 ssa_13 = intrinsic load_uniform (ssa_3) (24, 12, 0) /* base=24 */ /* range=12 */ /* dest_type=invalid vec3 32 ssa_13 = intrinsic load_uniform (ssa_3) (24, 12, 0) /* base=24 */ /* range=12 */ /* dest_type=invalid vec1 32 ssa_14 = iadd ssa_12.x, ssa_13.x vec1 32 ssa_14 = iadd ssa_12.x, ssa_13.x vec1 32 ssa_15 = iadd ssa_12.y, ssa_13.y vec1 32 ssa_15 = iadd ssa_12.y, ssa_13.y vec1 32 ssa_16 = iadd ssa_12.z, ssa_13.z vec1 32 ssa_16 = iadd ssa_12.z, ssa_13.z vec1 32 ssa_17 = intrinsic load_subgroup_id () () vec1 32 ssa_17 = intrinsic load_subgroup_id () () vec1 32 ssa_18 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_18 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_19 = ishl ssa_17, ssa_18 vec1 32 ssa_19 = ishl ssa_17, ssa_18 vec1 32 ssa_20 = intrinsic load_subgroup_invocation () () vec1 32 ssa_20 = intrinsic load_subgroup_invocation () () vec1 32 ssa_21 = iadd ssa_20, ssa_19 vec1 32 ssa_21 = iadd ssa_20, ssa_19 vec1 32 ssa_22 = load_const (0x0000001f /* 0.000000 */) vec1 32 ssa_22 = load_const (0x0000001f /* 0.000000 */) vec1 32 ssa_23 = iand ssa_21, ssa_22 vec1 32 ssa_23 = iand ssa_21, ssa_22 vec1 32 ssa_24 = ushr ssa_21, ssa_10 vec1 32 ssa_24 = ushr ssa_21, ssa_10 vec1 32 ssa_25 = ishl ssa_15, ssa_10 vec1 32 ssa_25 = ishl ssa_15, ssa_10 vec1 32 ssa_26 = iadd ssa_25, ssa_23 vec1 32 ssa_26 = iadd ssa_25, ssa_23 vec1 32 ssa_27 = iadd ssa_16, ssa_24 vec1 32 ssa_27 = iadd ssa_16, ssa_24 vec1 32 ssa_28 = imul ssa_11, ssa_27 vec1 32 ssa_28 = imul ssa_11, ssa_27 vec1 32 ssa_29 = iadd ssa_28, ssa_26 vec1 32 ssa_29 = iadd ssa_28, ssa_26 vec1 32 ssa_30 = imul ssa_9.x, ssa_29 vec1 32 ssa_30 = imul ssa_9.x, ssa_29 vec1 32 ssa_31 = iadd ssa_30, ssa_14 vec1 32 ssa_31 = iadd ssa_30, ssa_14 vec1 32 ssa_32 = iadd ssa_20, ssa_0 vec1 32 ssa_32 = iadd ssa_20, ssa_0 vec1 32 ssa_33 = ineg ssa_20 vec1 32 ssa_33 = ineg ssa_20 vec1 32 ssa_34 = iadd ssa_22, ssa_33 vec1 32 ssa_34 = iadd ssa_22, ssa_33 vec1 32 ssa_35 = ushr ssa_2, ssa_34 vec1 32 ssa_35 = ushr ssa_2, ssa_34 vec1 32 ssa_36 = bit_count ssa_35 vec1 32 ssa_36 = bit_count ssa_35 vec1 32 ssa_37 = ieq32 ssa_32, ssa_36 vec1 32 ssa_37 = ieq32 ssa_32, ssa_36 vec1 32 ssa_38 = b2i32 ssa_37 vec1 32 ssa_38 = b2i32 ssa_37 vec1 32 ssa_39 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_39 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_40 = ior ssa_38, ssa_39 vec1 32 ssa_40 = ior ssa_38, ssa_39 vec1 32 ssa_41 = intrinsic ballot (ssa_8) () vec1 32 ssa_41 = intrinsic ballot (ssa_8) () vec1 32 ssa_42 = iand ssa_41, ssa_35 vec1 32 ssa_42 = iand ssa_41, ssa_35 vec1 32 ssa_43 = bit_count ssa_42 vec1 32 ssa_43 = bit_count ssa_42 vec1 32 ssa_44 = ult32 ssa_3, ssa_43 vec1 32 ssa_44 = ult32 ssa_3, ssa_43 vec1 32 ssa_45 = b32csel ssa_44, ssa_7, ssa_3 vec1 32 ssa_45 = b32csel ssa_44, ssa_7, ssa_3 vec1 32 ssa_46 = ior ssa_40, ssa_45 vec1 32 ssa_46 = ior ssa_40, ssa_45 r3 = ior ssa_46, ssa_6 r3 = ior ssa_46, ssa_6 r4 = mov ssa_3 r4 = mov ssa_3 /* succs: block_1 */ /* succs: block_1 */ loop { loop { block block_1: block block_1: /* preds: block_0 block_4 */ /* preds: block_0 block_4 */ vec1 32 ssa_50 = uge32 r4, ssa_4 vec1 32 ssa_50 = uge32 r4, ssa_4 /* succs: block_2 block_3 */ /* succs: block_2 block_3 */ if ssa_50 { if ssa_50 { block block_2: block block_2: /* preds: block_1 */ /* preds: block_1 */ break break /* succs: block_5 */ /* succs: block_5 */ } else { } else { block block_3: block block_3: /* preds: block_1 */ /* preds: block_1 */ /* succs: block_4 */ /* succs: block_4 */ } } block block_4: block block_4: /* preds: block_3 */ /* preds: block_3 */ vec1 32 ssa_51 = umin ssa_32, r4 vec1 32 ssa_51 = umin ssa_32, r4 vec1 32 ssa_52 = ineg ssa_51 vec1 32 ssa_52 = ineg ssa_51 vec1 32 ssa_53 = iadd ssa_32, ssa_52 vec1 32 ssa_53 = iadd ssa_32, ssa_52 vec1 32 ssa_54 = ishl ssa_2, r4 vec1 32 ssa_54 = ishl ssa_2, r4 vec1 32 ssa_55 = uge32 r4, ssa_5 vec1 32 ssa_55 = uge32 r4, ssa_5 vec1 32 ssa_56 = b32csel ssa_55, ssa_3, ssa_54 vec1 32 ssa_56 = b32csel ssa_55, ssa_3, ssa_54 vec1 32 ssa_57 = iand ssa_56, ssa_35 vec1 32 ssa_57 = iand ssa_56, ssa_35 vec1 32 ssa_58 = bit_count ssa_57 vec1 32 ssa_58 = bit_count ssa_57 vec1 32 ssa_59 = iand r3, ssa_1 vec1 32 ssa_59 = iand r3, ssa_1 vec1 32 ssa_60 = ine32 ssa_58, ssa_53 vec1 32 ssa_60 = ine32 ssa_58, ssa_53 r3 = b32csel ssa_60, ssa_59, r3 r3 = b32csel ssa_60, ssa_59, r3 r4 = iadd r4, ssa_0 r4 = iadd r4, ssa_0 /* succs: block_1 */ /* succs: block_1 */ } } block block_5: block block_5: /* preds: block_2 */ /* preds: block_2 */ vec1 32 ssa_63 = ishl ssa_31, ssa_39 vec1 32 ssa_63 = ishl ssa_31, ssa_39 intrinsic store_ssbo (r3, ssa_39, ssa_63) (1, 0, 4, 0) /* wrmask=x */ /* access=0 */ /* align_mul=4 */ /* ali intrinsic store_ssbo (r3, ssa_39, ssa_63) (1, 0, 4, 0) /* wrmask=x */ /* access=0 */ /* align_mul=4 */ /* ali /* succs: block_6 */ /* succs: block_6 */ block block_6: block block_6: } } NIR (SSA form) for compute shader: NIR (SSA form) for compute shader: shader: MESA_SHADER_COMPUTE shader: MESA_SHADER_COMPUTE local-size: 1, 32, 1 local-size: 1, 32, 1 shared-size: 0 shared-size: 0 inputs: 0 inputs: 0 outputs: 0 outputs: 0 uniforms: 36 uniforms: 36 shared: 0 shared: 0 decl_var ssbo INTERP_MODE_NONE restrict block @0 (~0, 0, 0) decl_var ssbo INTERP_MODE_NONE restrict block @0 (~0, 0, 0) decl_function main (0 params) decl_function main (0 params) impl main { impl main { block block_0: block block_0: /* preds: */ /* preds: */ vec1 32 ssa_0 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_0 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_1 = load_const (0xfffffff7 /* -nan */) vec1 32 ssa_1 = load_const (0xfffffff7 /* -nan */) vec1 32 ssa_2 = load_const (0xffffffff /* -nan */) vec1 32 ssa_2 = load_const (0xffffffff /* -nan */) vec1 32 ssa_3 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_4 = load_const (0x00000080 /* 0.000000 */) vec1 32 ssa_4 = load_const (0x00000080 /* 0.000000 */) vec1 32 ssa_5 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_5 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_6 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_6 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_7 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_7 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_8 = load_const (0xffffffff /* -nan */) vec1 32 ssa_8 = load_const (0xffffffff /* -nan */) vec3 32 ssa_9 = intrinsic load_num_work_groups () () vec3 32 ssa_9 = intrinsic load_num_work_groups () () vec1 32 ssa_10 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_10 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_11 = ishl ssa_9.y, ssa_10 vec1 32 ssa_11 = ishl ssa_9.y, ssa_10 vec3 32 ssa_12 = intrinsic load_work_group_id () () vec3 32 ssa_12 = intrinsic load_work_group_id () () vec3 32 ssa_13 = intrinsic load_uniform (ssa_3) (24, 12, 0) /* base=24 */ /* range=12 */ /* dest_type=invalid vec3 32 ssa_13 = intrinsic load_uniform (ssa_3) (24, 12, 0) /* base=24 */ /* range=12 */ /* dest_type=invalid vec1 32 ssa_14 = iadd ssa_12.x, ssa_13.x vec1 32 ssa_14 = iadd ssa_12.x, ssa_13.x vec1 32 ssa_15 = iadd ssa_12.y, ssa_13.y vec1 32 ssa_15 = iadd ssa_12.y, ssa_13.y vec1 32 ssa_16 = iadd ssa_12.z, ssa_13.z vec1 32 ssa_16 = iadd ssa_12.z, ssa_13.z vec1 32 ssa_17 = intrinsic load_subgroup_id () () vec1 32 ssa_17 = intrinsic load_subgroup_id () () vec1 32 ssa_18 = ishl ssa_17, ssa_7 vec1 32 ssa_18 = ishl ssa_17, ssa_7 vec1 32 ssa_19 = intrinsic load_subgroup_invocation () () vec1 32 ssa_19 = intrinsic load_subgroup_invocation () () vec1 32 ssa_20 = iadd ssa_19, ssa_18 vec1 32 ssa_20 = iadd ssa_19, ssa_18 vec1 32 ssa_21 = load_const (0x0000001f /* 0.000000 */) vec1 32 ssa_21 = load_const (0x0000001f /* 0.000000 */) vec1 32 ssa_22 = iand ssa_20, ssa_21 vec1 32 ssa_22 = iand ssa_20, ssa_21 vec1 32 ssa_23 = ushr ssa_20, ssa_10 vec1 32 ssa_23 = ushr ssa_20, ssa_10 vec1 32 ssa_24 = ishl ssa_15, ssa_10 vec1 32 ssa_24 = ishl ssa_15, ssa_10 vec1 32 ssa_25 = iadd ssa_24, ssa_22 vec1 32 ssa_25 = iadd ssa_24, ssa_22 vec1 32 ssa_26 = iadd ssa_16, ssa_23 vec1 32 ssa_26 = iadd ssa_16, ssa_23 vec1 32 ssa_27 = imul ssa_11, ssa_26 vec1 32 ssa_27 = imul ssa_11, ssa_26 vec1 32 ssa_28 = iadd ssa_27, ssa_25 vec1 32 ssa_28 = iadd ssa_27, ssa_25 vec1 32 ssa_29 = imul ssa_9.x, ssa_28 vec1 32 ssa_29 = imul ssa_9.x, ssa_28 vec1 32 ssa_30 = iadd ssa_29, ssa_14 vec1 32 ssa_30 = iadd ssa_29, ssa_14 vec1 32 ssa_31 = iadd ssa_19, ssa_0 vec1 32 ssa_31 = iadd ssa_19, ssa_0 vec1 32 ssa_32 = ineg ssa_19 vec1 32 ssa_32 = ineg ssa_19 vec1 32 ssa_33 = iadd ssa_21, ssa_32 vec1 32 ssa_33 = iadd ssa_21, ssa_32 vec1 32 ssa_34 = ushr ssa_2, ssa_33 vec1 32 ssa_34 = ushr ssa_2, ssa_33 vec1 32 ssa_35 = bit_count ssa_34 vec1 32 ssa_35 = bit_count ssa_34 vec1 32 ssa_36 = ieq32 ssa_31, ssa_35 vec1 32 ssa_36 = ieq32 ssa_31, ssa_35 vec1 32 ssa_37 = b2i32 ssa_36 vec1 32 ssa_37 = b2i32 ssa_36 vec1 32 ssa_38 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_38 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_39 = ior ssa_37, ssa_38 vec1 32 ssa_39 = ior ssa_37, ssa_38 vec1 32 ssa_40 = intrinsic ballot (ssa_8) () vec1 32 ssa_40 = intrinsic ballot (ssa_8) () vec1 32 ssa_41 = iand ssa_40, ssa_34 vec1 32 ssa_41 = iand ssa_40, ssa_34 vec1 32 ssa_42 = bit_count ssa_41 vec1 32 ssa_42 = bit_count ssa_41 vec1 32 ssa_43 = ult32 ssa_3, ssa_42 vec1 32 ssa_43 = ult32 ssa_3, ssa_42 vec1 32 ssa_44 = b32csel ssa_43, ssa_7, ssa_3 vec1 32 ssa_44 = b32csel ssa_43, ssa_7, ssa_3 vec1 32 ssa_45 = ior ssa_39, ssa_44 vec1 32 ssa_45 = ior ssa_39, ssa_44 vec1 32 ssa_46 = ior ssa_45, ssa_6 vec1 32 ssa_46 = ior ssa_45, ssa_6 /* succs: block_1 */ /* succs: block_1 */ loop { loop { block block_1: block block_1: /* preds: block_0 block_4 */ /* preds: block_0 block_4 */ vec1 32 ssa_47 = phi block_0: ssa_46, block_4: ssa_60 vec1 32 ssa_47 = phi block_0: ssa_46, block_4: ssa_60 vec1 32 ssa_48 = phi block_0: ssa_3, block_4: ssa_61 vec1 32 ssa_48 = phi block_0: ssa_3, block_4: ssa_61 vec1 32 ssa_49 = uge32 ssa_48, ssa_4 vec1 32 ssa_49 = uge32 ssa_48, ssa_4 /* succs: block_2 block_3 */ /* succs: block_2 block_3 */ if ssa_49 { if ssa_49 { block block_2: block block_2: /* preds: block_1 */ /* preds: block_1 */ break break /* succs: block_5 */ /* succs: block_5 */ } else { } else { block block_3: block block_3: /* preds: block_1 */ /* preds: block_1 */ /* succs: block_4 */ /* succs: block_4 */ } } block block_4: block block_4: /* preds: block_3 */ /* preds: block_3 */ vec1 32 ssa_50 = umin ssa_31, ssa_48 vec1 32 ssa_50 = umin ssa_31, ssa_48 vec1 32 ssa_51 = ineg ssa_50 vec1 32 ssa_51 = ineg ssa_50 vec1 32 ssa_52 = iadd ssa_31, ssa_51 vec1 32 ssa_52 = iadd ssa_31, ssa_51 vec1 32 ssa_53 = ishl ssa_2, ssa_48 vec1 32 ssa_53 = ishl ssa_2, ssa_48 vec1 32 ssa_54 = uge32 ssa_48, ssa_5 vec1 32 ssa_54 = uge32 ssa_48, ssa_5 vec1 32 ssa_55 = b32csel ssa_54, ssa_3, ssa_53 vec1 32 ssa_55 = b32csel ssa_54, ssa_3, ssa_53 vec1 32 ssa_56 = iand ssa_55, ssa_34 vec1 32 ssa_56 = iand ssa_55, ssa_34 vec1 32 ssa_57 = bit_count ssa_56 vec1 32 ssa_57 = bit_count ssa_56 vec1 32 ssa_58 = iand ssa_47, ssa_1 vec1 32 ssa_58 = iand ssa_47, ssa_1 vec1 32 ssa_59 = ine32 ssa_57, ssa_52 vec1 32 ssa_59 = ine32 ssa_57, ssa_52 vec1 32 ssa_60 = b32csel ssa_59, ssa_58, ssa_47 vec1 32 ssa_60 = b32csel ssa_59, ssa_58, ssa_47 vec1 32 ssa_61 = iadd ssa_48, ssa_0 vec1 32 ssa_61 = iadd ssa_48, ssa_0 /* succs: block_1 */ /* succs: block_1 */ } } block block_5: block block_5: /* preds: block_2 */ /* preds: block_2 */ vec1 32 ssa_62 = ishl ssa_30, ssa_38 vec1 32 ssa_62 = ishl ssa_30, ssa_38 intrinsic store_ssbo (ssa_47, ssa_38, ssa_62) (1, 0, 4, 0) /* wrmask=x */ /* access=0 */ /* align_mul=4 */ /* intrinsic store_ssbo (ssa_47, ssa_38, ssa_62) (1, 0, 4, 0) /* wrmask=x */ /* access=0 */ /* align_mul=4 */ /* /* succs: block_6 */ /* succs: block_6 */ block block_6: block block_6: } } NIR (final form) for compute shader: NIR (final form) for compute shader: shader: MESA_SHADER_COMPUTE shader: MESA_SHADER_COMPUTE local-size: 1, 32, 1 local-size: 1, 32, 1 shared-size: 0 shared-size: 0 inputs: 0 inputs: 0 outputs: 0 outputs: 0 uniforms: 36 uniforms: 36 shared: 0 shared: 0 decl_var ssbo INTERP_MODE_NONE restrict block @0 (~0, 0, 0) decl_var ssbo INTERP_MODE_NONE restrict block @0 (~0, 0, 0) decl_function main (0 params) decl_function main (0 params) impl main { impl main { decl_reg vec1 32 r3 decl_reg vec1 32 r3 decl_reg vec1 32 r4 decl_reg vec1 32 r4 block block_0: block block_0: /* preds: */ /* preds: */ vec1 32 ssa_0 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_0 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_1 = load_const (0xfffffff7 /* -nan */) vec1 32 ssa_1 = load_const (0xfffffff7 /* -nan */) vec1 32 ssa_2 = load_const (0xffffffff /* -nan */) vec1 32 ssa_2 = load_const (0xffffffff /* -nan */) vec1 32 ssa_3 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_4 = load_const (0x00000080 /* 0.000000 */) vec1 32 ssa_4 = load_const (0x00000080 /* 0.000000 */) vec1 32 ssa_5 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_5 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_6 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_6 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_7 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_7 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_8 = load_const (0xffffffff /* -nan */) vec1 32 ssa_8 = load_const (0xffffffff /* -nan */) vec3 32 ssa_9 = intrinsic load_num_work_groups () () vec3 32 ssa_9 = intrinsic load_num_work_groups () () vec1 32 ssa_10 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_10 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_11 = ishl ssa_9.y, ssa_10 vec1 32 ssa_11 = ishl ssa_9.y, ssa_10 vec3 32 ssa_12 = intrinsic load_work_group_id () () vec3 32 ssa_12 = intrinsic load_work_group_id () () vec3 32 ssa_13 = intrinsic load_uniform (ssa_3) (24, 12, 0) /* base=24 */ /* range=12 */ /* dest_type=invalid vec3 32 ssa_13 = intrinsic load_uniform (ssa_3) (24, 12, 0) /* base=24 */ /* range=12 */ /* dest_type=invalid vec1 32 ssa_14 = iadd ssa_12.x, ssa_13.x vec1 32 ssa_14 = iadd ssa_12.x, ssa_13.x vec1 32 ssa_15 = iadd ssa_12.y, ssa_13.y vec1 32 ssa_15 = iadd ssa_12.y, ssa_13.y vec1 32 ssa_16 = iadd ssa_12.z, ssa_13.z vec1 32 ssa_16 = iadd ssa_12.z, ssa_13.z vec1 32 ssa_17 = intrinsic load_subgroup_id () () vec1 32 ssa_17 = intrinsic load_subgroup_id () () vec1 32 ssa_18 = ishl ssa_17, ssa_7 vec1 32 ssa_18 = ishl ssa_17, ssa_7 vec1 32 ssa_19 = intrinsic load_subgroup_invocation () () vec1 32 ssa_19 = intrinsic load_subgroup_invocation () () vec1 32 ssa_20 = iadd ssa_19, ssa_18 vec1 32 ssa_20 = iadd ssa_19, ssa_18 vec1 32 ssa_21 = load_const (0x0000001f /* 0.000000 */) vec1 32 ssa_21 = load_const (0x0000001f /* 0.000000 */) vec1 32 ssa_22 = iand ssa_20, ssa_21 vec1 32 ssa_22 = iand ssa_20, ssa_21 vec1 32 ssa_23 = ushr ssa_20, ssa_10 vec1 32 ssa_23 = ushr ssa_20, ssa_10 vec1 32 ssa_24 = ishl ssa_15, ssa_10 vec1 32 ssa_24 = ishl ssa_15, ssa_10 vec1 32 ssa_25 = iadd ssa_24, ssa_22 vec1 32 ssa_25 = iadd ssa_24, ssa_22 vec1 32 ssa_26 = iadd ssa_16, ssa_23 vec1 32 ssa_26 = iadd ssa_16, ssa_23 vec1 32 ssa_27 = imul ssa_11, ssa_26 vec1 32 ssa_27 = imul ssa_11, ssa_26 vec1 32 ssa_28 = iadd ssa_27, ssa_25 vec1 32 ssa_28 = iadd ssa_27, ssa_25 vec1 32 ssa_29 = imul ssa_9.x, ssa_28 vec1 32 ssa_29 = imul ssa_9.x, ssa_28 vec1 32 ssa_30 = iadd ssa_29, ssa_14 vec1 32 ssa_30 = iadd ssa_29, ssa_14 vec1 32 ssa_31 = iadd ssa_19, ssa_0 vec1 32 ssa_31 = iadd ssa_19, ssa_0 vec1 32 ssa_32 = ineg ssa_19 vec1 32 ssa_32 = ineg ssa_19 vec1 32 ssa_33 = iadd ssa_21, ssa_32 vec1 32 ssa_33 = iadd ssa_21, ssa_32 vec1 32 ssa_34 = ushr ssa_2, ssa_33 vec1 32 ssa_34 = ushr ssa_2, ssa_33 vec1 32 ssa_35 = bit_count ssa_34 vec1 32 ssa_35 = bit_count ssa_34 vec1 32 ssa_36 = ieq32 ssa_31, ssa_35 vec1 32 ssa_36 = ieq32 ssa_31, ssa_35 vec1 32 ssa_37 = b2i32 ssa_36 vec1 32 ssa_37 = b2i32 ssa_36 vec1 32 ssa_38 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_38 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_39 = ior ssa_37, ssa_38 vec1 32 ssa_39 = ior ssa_37, ssa_38 vec1 32 ssa_40 = intrinsic ballot (ssa_8) () vec1 32 ssa_40 = intrinsic ballot (ssa_8) () vec1 32 ssa_41 = iand ssa_40, ssa_34 vec1 32 ssa_41 = iand ssa_40, ssa_34 vec1 32 ssa_42 = bit_count ssa_41 vec1 32 ssa_42 = bit_count ssa_41 vec1 32 ssa_43 = ult32 ssa_3, ssa_42 vec1 32 ssa_43 = ult32 ssa_3, ssa_42 vec1 32 ssa_44 = b32csel ssa_43, ssa_7, ssa_3 vec1 32 ssa_44 = b32csel ssa_43, ssa_7, ssa_3 vec1 32 ssa_45 = ior ssa_39, ssa_44 vec1 32 ssa_45 = ior ssa_39, ssa_44 r3 = ior ssa_45, ssa_6 r3 = ior ssa_45, ssa_6 r4 = mov ssa_3 r4 = mov ssa_3 /* succs: block_1 */ /* succs: block_1 */ loop { loop { block block_1: block block_1: /* preds: block_0 block_4 */ /* preds: block_0 block_4 */ vec1 32 ssa_49 = uge32 r4, ssa_4 vec1 32 ssa_49 = uge32 r4, ssa_4 /* succs: block_2 block_3 */ /* succs: block_2 block_3 */ if ssa_49 { if ssa_49 { block block_2: block block_2: /* preds: block_1 */ /* preds: block_1 */ break break /* succs: block_5 */ /* succs: block_5 */ } else { } else { block block_3: block block_3: /* preds: block_1 */ /* preds: block_1 */ /* succs: block_4 */ /* succs: block_4 */ } } block block_4: block block_4: /* preds: block_3 */ /* preds: block_3 */ vec1 32 ssa_50 = umin ssa_31, r4 vec1 32 ssa_50 = umin ssa_31, r4 vec1 32 ssa_51 = ineg ssa_50 vec1 32 ssa_51 = ineg ssa_50 vec1 32 ssa_52 = iadd ssa_31, ssa_51 vec1 32 ssa_52 = iadd ssa_31, ssa_51 vec1 32 ssa_53 = ishl ssa_2, r4 vec1 32 ssa_53 = ishl ssa_2, r4 vec1 32 ssa_54 = uge32 r4, ssa_5 vec1 32 ssa_54 = uge32 r4, ssa_5 vec1 32 ssa_55 = b32csel ssa_54, ssa_3, ssa_53 vec1 32 ssa_55 = b32csel ssa_54, ssa_3, ssa_53 vec1 32 ssa_56 = iand ssa_55, ssa_34 vec1 32 ssa_56 = iand ssa_55, ssa_34 vec1 32 ssa_57 = bit_count ssa_56 vec1 32 ssa_57 = bit_count ssa_56 vec1 32 ssa_58 = iand r3, ssa_1 vec1 32 ssa_58 = iand r3, ssa_1 vec1 32 ssa_59 = ine32 ssa_57, ssa_52 vec1 32 ssa_59 = ine32 ssa_57, ssa_52 r3 = b32csel ssa_59, ssa_58, r3 r3 = b32csel ssa_59, ssa_58, r3 r4 = iadd r4, ssa_0 r4 = iadd r4, ssa_0 /* succs: block_1 */ /* succs: block_1 */ } } block block_5: block block_5: /* preds: block_2 */ /* preds: block_2 */ vec1 32 ssa_62 = ishl ssa_30, ssa_38 vec1 32 ssa_62 = ishl ssa_30, ssa_38 intrinsic store_ssbo (r3, ssa_38, ssa_62) (1, 0, 4, 0) /* wrmask=x */ /* access=0 */ /* align_mul=4 */ /* ali intrinsic store_ssbo (r3, ssa_38, ssa_62) (1, 0, 4, 0) /* wrmask=x */ /* access=0 */ /* align_mul=4 */ /* ali /* succs: block_6 */ /* succs: block_6 */ block block_6: block block_6: } } Native code for unnamed compute shader (null) (sha1 7edc7c47371767c44667807927397441efb76681) | Native code for unnamed compute shader (null) (sha1 dde7a2dd0d57b8983f9514cdf89a36b046ee0d5b) SIMD16 shader: 67 instructions. 1 loops. 1726 cycles. 0:0 spills:fills, 3 sends, scheduled with mode top-down. Promot | SIMD16 shader: 66 instructions. 1 loops. 1642 cycles. 0:0 spills:fills, 3 sends, scheduled with mode top-down. Promot START B0 (376 cycles) | START B0 (372 cycles) mov(8) g3<1>UW 0x76543210V { align1 WE_all 1Q }; mov(8) g3<1>UW 0x76543210V { align1 WE_all 1Q }; mov(16) g81<1>UD g0.1<0,1,0>UD { align1 1H compacted }; | mov(16) g79<1>UD g0.1<0,1,0>UD { align1 1H compacted }; mov(16) g83<1>UD g0.6<0,1,0>UD { align1 1H }; | mov(16) g81<1>UD g0.6<0,1,0>UD { align1 1H }; mov(16) g4<1>UD g0.7<0,1,0>UD { align1 1H }; mov(16) g4<1>UD g0.7<0,1,0>UD { align1 1H }; mov(16) g6<1>UD 0xffffffffUD { align1 1H compacted }; mov(16) g6<1>UD 0xffffffffUD { align1 1H compacted }; mov(16) g8<1>UD 0xffffffffUD { align1 1H compacted }; | mov(16) g83<1>UD 0x00000000UD { align1 1H compacted }; mov(16) g85<1>UD 0x00000000UD { align1 1H compacted }; < add(8) g3.8<1>UW g3<8,8,1>UW 0x0008UW { align1 WE_all 1Q }; add(8) g3.8<1>UW g3<8,8,1>UW 0x0008UW { align1 WE_all 1Q }; send(16) g10<1>UW g85<0,1,0>UD 0x04605800 | send(16) g8<1>UW g83<0,1,0>UD 0x04605800 dp data 1 MsgDesc: ( untyped surface read, Surface = 0, SIMD16, Mask = 0x8) mlen 2 rlen 6 dp data 1 MsgDesc: ( untyped surface read, Surface = 0, SIMD16, Mask = 0x8) mlen 2 rlen 6 add(16) g16<1>D g81<8,8,1>D g1.6<0,1,0>D { align1 1H compacted }; | add(16) g14<1>D g79<8,8,1>D g1.6<0,1,0>D { align1 1H compacted }; add(16) g18<1>D g83<8,8,1>D g1.7<0,1,0>D { align1 1H compacted }; | add(16) g16<1>D g81<8,8,1>D g1.7<0,1,0>D { align1 1H compacted }; add(16) g20<1>D g4<8,8,1>D g2<0,1,0>D { align1 1H compacted }; | add(16) g18<1>D g4<8,8,1>D g2<0,1,0>D { align1 1H compacted }; shl(16) g22<1>D g2.1<0,1,0>D 0x00000004UD { align1 1H }; | shl(16) g20<1>D g2.1<0,1,0>D 0x00000004UD { align1 1H }; mov(16) g24<1>D g3<8,8,1>UW { align1 1H }; | mov(16) g22<1>D g3<8,8,1>UW { align1 1H }; shl(16) g32<1>D g18<8,8,1>D 0x00000005UD { align1 1H }; | mov(1) g3.1<1>D 1D { align1 WE_all 1N }; add(16) g26<1>D g24<8,8,1>D g22<8,8,1>D { align1 1H compacted }; | shl(16) g30<1>D g16<8,8,1>D 0x00000005UD { align1 1H }; add(16) g46<1>D g24<8,8,1>D 1D { align1 1H compacted }; | add(16) g24<1>D g22<8,8,1>D g20<8,8,1>D { align1 1H compacted }; add(16) g48<1>D -g24<8,8,1>D 31D { align1 1H compacted }; | add(16) g44<1>D g22<8,8,1>D 1D { align1 1H compacted }; mov(1) g60<2>UW 0x00000000UD { align1 WE_all 1N }; | add(16) g46<1>D -g22<8,8,1>D 31D { align1 1H compacted }; and(16) g28<1>UD g26<8,8,1>UD 0x0000001fUD { align1 1H compacted }; | mov(1) g58<2>UW 0x00000000UD { align1 WE_all 1N }; shr(16) g30<1>UD g26<8,8,1>UD 0x00000005UD { align1 1H compacted }; | and(16) g26<1>UD g24<8,8,1>UD 0x0000001fUD { align1 1H compacted }; shr(16) g50<1>UD g6<8,8,1>UD g48<8,8,1>UD { align1 1H compacted }; | shr(16) g28<1>UD g24<8,8,1>UD 0x00000005UD { align1 1H compacted }; add(16) g34<1>D g32<8,8,1>D g28<8,8,1>D { align1 1H compacted }; | shr(16) g48<1>D -g3.1<0,1,0>D g46<8,8,1>D { align1 1H compacted }; add(16) g36<1>D g20<8,8,1>D g30<8,8,1>D { align1 1H compacted }; | add(16) g32<1>D g30<8,8,1>D g26<8,8,1>D { align1 1H compacted }; cbit(16) g52<1>UD g50<8,8,1>UD { align1 1H compacted }; | add(16) g34<1>D g18<8,8,1>D g28<8,8,1>D { align1 1H compacted }; cmp.z.f0.0(16) g54<1>D g46<8,8,1>D g52<8,8,1>D { align1 1H compacted }; | cbit(16) g50<1>UD g48<8,8,1>UD { align1 1H compacted }; mov(16) g56<1>D -g54<8,8,1>D { align1 1H compacted }; | cmp.z.f0.0(16) g52<1>D g44<8,8,1>D g50<8,8,1>D { align1 1H compacted }; or(16) g58<1>UD g56<8,8,1>UD 0x00000002UD { align1 1H compacted }; | mov(16) g54<1>D -g52<8,8,1>D { align1 1H compacted }; shl(16) g1<1>D g12<8,8,1>D 0x00000005UD { align1 1H }; | or(16) g56<1>UD g54<8,8,1>UD 0x00000002UD { align1 1H compacted }; mul(16) g38<1>D g1<8,8,1>D g36<16,8,2>UW { align1 1H }; | shl(16) g1<1>D g10<8,8,1>D 0x00000005UD { align1 1H }; mul(16) g3<1>D g1<8,8,1>D g36.1<16,8,2>UW { align1 1H }; | mul(16) g36<1>D g1<8,8,1>D g34<16,8,2>UW { align1 1H }; add(16) g38.1<2>UW g38.1<16,8,2>UW g3<16,8,2>UW { align1 1H }; | mul(16) g4<1>D g1<8,8,1>D g34.1<16,8,2>UW { align1 1H }; add(16) g40<1>D g38<8,8,1>D g34<8,8,1>D { align1 1H compacted }; | add(16) g36.1<2>UW g36.1<16,8,2>UW g4<16,8,2>UW { align1 1H }; mul(16) g42<1>D g10<8,8,1>D g40<16,8,2>UW { align1 1H }; | add(16) g38<1>D g36<8,8,1>D g32<8,8,1>D { align1 1H compacted }; mul(16) g4<1>D g10<8,8,1>D g40.1<16,8,2>UW { align1 1H }; | mul(16) g40<1>D g8<8,8,1>D g38<16,8,2>UW { align1 1H }; add(16) g42.1<2>UW g42.1<16,8,2>UW g4<16,8,2>UW { align1 1H }; | mul(16) g16<1>D g8<8,8,1>D g38.1<16,8,2>UW { align1 1H }; add(16) g44<1>D g42<8,8,1>D g16<8,8,1>D { align1 1H compacted }; | add(16) g40.1<2>UW g40.1<16,8,2>UW g16<16,8,2>UW { align1 1H }; mov(1) f0<1>UW g60<0,1,0>UW { align1 WE_all 1N }; | add(16) g42<1>D g40<8,8,1>D g14<8,8,1>D { align1 1H compacted }; cmp.nz.f0.0(16) null<1>UD g8<8,8,1>UD 0x00000000UD { align1 1H compacted }; | mov(1) f0<1>UW g58<0,1,0>UW { align1 WE_all 1N }; mov(16) g60<1>UD f0<0,1,0>UW { align1 1H }; | cmp.nz.f0.0(16) null<1>UD g6<8,8,1>UD 0x00000000UD { align1 1H compacted }; mov(1) g1<1>UD 0x00000000UD { align1 WE_all 1N compacted }; | mov(16) g58<1>UD f0<0,1,0>UW { align1 1H }; > mov(1) g3<1>UD 0x00000000UD { align1 WE_all 1N compacted }; mov(16) g5<1>UD 0x00000000UD { align1 1H compacted }; mov(16) g5<1>UD 0x00000000UD { align1 1H compacted }; and(16) g62<1>UD g60<8,8,1>UD g50<8,8,1>UD { align1 1H compacted }; | and(16) g60<1>UD g58<8,8,1>UD g48<8,8,1>UD { align1 1H compacted }; cbit(16) g64<1>UD g62<8,8,1>UD { align1 1H compacted }; | cbit(16) g62<1>UD g60<8,8,1>UD { align1 1H compacted }; cmp.g.f0.0(16) null<1>UD g64<8,8,1>UD 0x00000000UD { align1 1H compacted }; | cmp.g.f0.0(16) null<1>UD g62<8,8,1>UD 0x00000000UD { align1 1H compacted }; (-f0.0) sel(16) g65<1>UD g1<0,1,0>UD 0x00000004UD { align1 1H }; | (-f0.0) sel(16) g63<1>UD g3<0,1,0>UD 0x00000004UD { align1 1H }; or(16) g67<1>UD g58<8,8,1>UD g65<8,8,1>UD { align1 1H compacted }; | or(16) g65<1>UD g56<8,8,1>UD g63<8,8,1>UD { align1 1H compacted }; or(16) g88<1>UD g67<8,8,1>UD 0x00000008UD { align1 1H compacted }; | or(16) g86<1>UD g65<8,8,1>UD 0x00000008UD { align1 1H compacted }; END B0 ->B1 END B0 ->B1 START B2 <-B1 <-B3 (260 cycles) START B2 <-B1 <-B3 (260 cycles) LABEL1: LABEL1: cmp.ge.f0.0(16) null<1>UD g5<8,8,1>UD 0x00000080UD { align1 1H compacted }; cmp.ge.f0.0(16) null<1>UD g5<8,8,1>UD 0x00000080UD { align1 1H compacted }; END B1 ->B2 ->B4 END B1 ->B2 ->B4 (+f0.0) break(16) JIP: LABEL0 UIP: LABEL0 { align1 1H }; (+f0.0) break(16) JIP: LABEL0 UIP: LABEL0 { align1 1H }; END B2 ->B1 ->B4 ->B3 END B2 ->B1 ->B4 ->B3 START B3 <-B2 (1060 cycles) | START B3 <-B2 (980 cycles) sel.l(16) g68<1>UD g46<8,8,1>UD g5<8,8,1>UD { align1 1H compacted }; | sel.l(16) g66<1>UD g44<8,8,1>UD g5<8,8,1>UD { align1 1H compacted }; mov(1) g1.1<1>D 1D { align1 WE_all 1N }; | shl(16) g70<1>D -g3.1<0,1,0>D g5<8,8,1>UD { align1 1H }; cmp.ge.f0.0(16) null<1>UD g5<8,8,1>UD 0x00000020UD { align1 1H compacted }; cmp.ge.f0.0(16) null<1>UD g5<8,8,1>UD 0x00000020UD { align1 1H compacted }; and(16) g80<1>UD g88<8,8,1>UD 0xfffffff7UD { align1 1H compacted }; | and(16) g78<1>UD g86<8,8,1>UD 0xfffffff7UD { align1 1H compacted }; add(16) g70<1>D g46<8,8,1>D -g68<8,8,1>D { align1 1H compacted }; < shl(16) g72<1>D -g1.1<0,1,0>D g5<8,8,1>UD { align1 1H }; < add(16) g5<1>D g5<8,8,1>D 1D { align1 1H compacted }; add(16) g5<1>D g5<8,8,1>D 1D { align1 1H compacted }; (-f0.0) sel(16) g74<1>UD g72<8,8,1>UD 0x00000000UD { align1 1H }; | add(16) g68<1>D g44<8,8,1>D -g66<8,8,1>D { align1 1H compacted }; and(16) g76<1>UD g74<8,8,1>UD g50<8,8,1>UD { align1 1H compacted }; | (-f0.0) sel(16) g72<1>UD g70<8,8,1>UD 0x00000000UD { align1 1H }; cbit(16) g78<1>UD g76<8,8,1>UD { align1 1H compacted }; | and(16) g74<1>UD g72<8,8,1>UD g48<8,8,1>UD { align1 1H compacted }; cmp.nz.f0.0(16) null<1>D g78<8,8,1>D g70<8,8,1>D { align1 1H compacted }; | cbit(16) g76<1>UD g74<8,8,1>UD { align1 1H compacted }; (+f0.0) sel(16) g88<1>UD g80<8,8,1>UD g88<8,8,1>UD { align1 1H compacted }; | cmp.nz.f0.0(16) null<1>D g76<8,8,1>D g68<8,8,1>D { align1 1H compacted }; > (+f0.0) sel(16) g86<1>UD g78<8,8,1>UD g86<8,8,1>UD { align1 1H compacted }; LABEL0: LABEL0: while(16) JIP: LABEL1 { align1 1H }; while(16) JIP: LABEL1 { align1 1H }; END B3 ->B2 END B3 ->B2 START B4 <-B1 <-B2 (30 cycles) START B4 <-B1 <-B2 (30 cycles) shl(16) g86<1>D g44<8,8,1>D 0x00000002UD { align1 1H }; | shl(16) g84<1>D g42<8,8,1>D 0x00000002UD { align1 1H }; sends(16) nullUD g86UD g88UD 0x04025e02 0x00000080 | sends(16) nullUD g84UD g86UD 0x04025e02 0x00000080 dp data 1 MsgDesc: ( DC untyped surface write, Surface = 2, SIMD16, Mask = 0xe) mlen 2 ex dp data 1 MsgDesc: ( DC untyped surface write, Surface = 2, SIMD16, Mask = 0xe) mlen 2 ex mov(8) g126<1>UD g0<8,8,1>UD { align1 WE_all 1Q compacted }; mov(8) g126<1>UD g0<8,8,1>UD { align1 WE_all 1Q compacted }; send(16) null<1>UW g126<8,8,1>UW 0x82000000 send(16) null<1>UW g126<8,8,1>UW 0x82000000 thread_spawner MsgDesc: mlen 1 rlen 0 { align1 WE_all 1H EOT }; thread_spawner MsgDesc: mlen 1 rlen 0 { align1 WE_all 1H EOT }; END B4 END B4 NIR (from SPIR-V) for MESA_SHADER_COMPUTE shader: NIR (from SPIR-V) for MESA_SHADER_COMPUTE shader: shader: MESA_SHADER_COMPUTE shader: MESA_SHADER_COMPUTE local-size: 1, 1, 32 local-size: 1, 1, 32 shared-size: 0 shared-size: 0 inputs: 0 inputs: 0 outputs: 0 outputs: 0 uniforms: 0 uniforms: 0 shared: 0 shared: 0 decl_var system INTERP_MODE_NONE uvec3 @0 decl_var system INTERP_MODE_NONE uvec3 @0 decl_var system INTERP_MODE_NONE uvec3 @1 decl_var system INTERP_MODE_NONE uvec3 @1 decl_var system INTERP_MODE_NONE uint @2 decl_var system INTERP_MODE_NONE uint @2 decl_var ssbo INTERP_MODE_NONE restrict block @3 (~0, 0, 0) decl_var ssbo INTERP_MODE_NONE restrict block @3 (~0, 0, 0) decl_function main (0 params) decl_function main (0 params) impl main { impl main { decl_var INTERP_MODE_NONE uvec3 @4 decl_var INTERP_MODE_NONE uvec3 @4 decl_var INTERP_MODE_NONE uint @5 decl_var INTERP_MODE_NONE uint @5 decl_var INTERP_MODE_NONE uvec4 @6 decl_var INTERP_MODE_NONE uvec4 @6 decl_var INTERP_MODE_NONE uvec4 @7 decl_var INTERP_MODE_NONE uvec4 @7 decl_var INTERP_MODE_NONE uint @8 decl_var INTERP_MODE_NONE uint @8 decl_var INTERP_MODE_NONE uint @9 decl_var INTERP_MODE_NONE uint @9 decl_var INTERP_MODE_NONE uint @10 decl_var INTERP_MODE_NONE uint @10 decl_var INTERP_MODE_NONE uint @11 decl_var INTERP_MODE_NONE uint @11 decl_var INTERP_MODE_NONE uvec4 @12 decl_var INTERP_MODE_NONE uvec4 @12 decl_var INTERP_MODE_NONE int @13 decl_var INTERP_MODE_NONE int @13 decl_var INTERP_MODE_NONE int @14 decl_var INTERP_MODE_NONE int @14 decl_var INTERP_MODE_NONE uint @15 decl_var INTERP_MODE_NONE uint @15 decl_var INTERP_MODE_NONE int @16 decl_var INTERP_MODE_NONE int @16 decl_var INTERP_MODE_NONE uint @17 decl_var INTERP_MODE_NONE uint @17 decl_var INTERP_MODE_NONE int @18 decl_var INTERP_MODE_NONE int @18 decl_var INTERP_MODE_NONE uint @19 decl_var INTERP_MODE_NONE uint @19 decl_var INTERP_MODE_NONE uint @20 decl_var INTERP_MODE_NONE uint @20 decl_var INTERP_MODE_NONE bool cont decl_var INTERP_MODE_NONE bool cont block block_0: block block_0: /* preds: */ /* preds: */ vec1 32 ssa_217 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_217 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_208 = load_const (0xfffffff7 /* -nan */) vec1 32 ssa_208 = load_const (0xfffffff7 /* -nan */) vec1 32 ssa_189 = load_const (0xffffffff /* -nan */) vec1 32 ssa_189 = load_const (0xffffffff /* -nan */) vec1 32 ssa_184 = load_const (0x00000060 /* 0.000000 */) vec1 32 ssa_184 = load_const (0x00000060 /* 0.000000 */) vec1 32 ssa_180 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_180 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_178 = load_const (0x00000060 /* 0.000000 */) vec1 32 ssa_178 = load_const (0x00000060 /* 0.000000 */) vec1 32 ssa_174 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_174 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_172 = load_const (0x00000080 /* 0.000000 */) vec1 32 ssa_172 = load_const (0x00000080 /* 0.000000 */) vec1 32 ssa_164 = load_const (0xffffffff /* -nan */) vec1 32 ssa_164 = load_const (0xffffffff /* -nan */) vec1 32 ssa_159 = load_const (0x00000040 /* 0.000000 */) vec1 32 ssa_159 = load_const (0x00000040 /* 0.000000 */) vec1 32 ssa_155 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_155 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_153 = load_const (0x00000040 /* 0.000000 */) vec1 32 ssa_153 = load_const (0x00000040 /* 0.000000 */) vec1 32 ssa_149 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_149 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_147 = load_const (0x00000060 /* 0.000000 */) vec1 32 ssa_147 = load_const (0x00000060 /* 0.000000 */) vec1 32 ssa_139 = load_const (0xffffffff /* -nan */) vec1 32 ssa_139 = load_const (0xffffffff /* -nan */) vec1 32 ssa_134 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_134 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_130 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_130 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_128 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_128 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_124 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_124 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_122 = load_const (0x00000040 /* 0.000000 */) vec1 32 ssa_122 = load_const (0x00000040 /* 0.000000 */) vec1 32 ssa_114 = load_const (0xffffffff /* -nan */) vec1 32 ssa_114 = load_const (0xffffffff /* -nan */) vec1 32 ssa_110 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_110 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_108 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_108 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_95 = load_const (0x00000080 /* 0.000000 */) vec1 32 ssa_95 = load_const (0x00000080 /* 0.000000 */) vec1 32 ssa_91 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_91 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_88 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_88 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_79 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_79 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_78 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_78 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_76 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_76 = load_const (0x00000000 /* 0.000000 */) vec1 1 ssa_73 = load_const (true) vec1 1 ssa_73 = load_const (true) vec1 32 ssa_66 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_66 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_65 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_65 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_63 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_63 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_53 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_53 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_52 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_52 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_43 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_43 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_39 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_39 = load_const (0x00000000 /* 0.000000 */) vec4 32 ssa_37 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, vec4 32 ssa_37 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, vec4 32 ssa_35 = load_const (0xffffffff /* -nan */, 0xffffffff /* -nan */, 0xffffffff /* -nan */, 0xffffffff vec4 32 ssa_35 = load_const (0xffffffff /* -nan */, 0xffffffff /* -nan */, 0xffffffff /* -nan */, 0xffffffff vec3 32 ssa_2 = load_const (0x00000001 /* 0.000000 */, 0x00000001 /* 0.000000 */, 0x00000020 /* 0.000000 */) vec3 32 ssa_2 = load_const (0x00000001 /* 0.000000 */, 0x00000001 /* 0.000000 */, 0x00000020 /* 0.000000 */) vec1 32 ssa_0 = deref_var &@0 (system uvec3) vec1 32 ssa_0 = deref_var &@0 (system uvec3) vec3 32 ssa_1 = intrinsic load_deref (ssa_0) (0) /* access=0 */ vec3 32 ssa_1 = intrinsic load_deref (ssa_0) (0) /* access=0 */ vec3 32 ssa_3 = imul ssa_1, ssa_2 vec3 32 ssa_3 = imul ssa_1, ssa_2 vec1 32 ssa_4 = deref_var &@4 (function_temp uvec3) vec1 32 ssa_4 = deref_var &@4 (function_temp uvec3) intrinsic store_deref (ssa_4, ssa_3) (7, 0) /* wrmask=xyz */ /* access=0 */ intrinsic store_deref (ssa_4, ssa_3) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_5 = deref_var &@4 (function_temp uvec3) vec1 32 ssa_5 = deref_var &@4 (function_temp uvec3) vec3 32 ssa_8 = intrinsic load_deref (ssa_5) (0) /* access=0 */ vec3 32 ssa_8 = intrinsic load_deref (ssa_5) (0) /* access=0 */ vec1 32 ssa_9 = mov ssa_8.x vec1 32 ssa_9 = mov ssa_8.x vec1 32 ssa_10 = deref_var &@4 (function_temp uvec3) vec1 32 ssa_10 = deref_var &@4 (function_temp uvec3) vec3 32 ssa_13 = intrinsic load_deref (ssa_10) (0) /* access=0 */ vec3 32 ssa_13 = intrinsic load_deref (ssa_10) (0) /* access=0 */ vec1 32 ssa_14 = mov ssa_13.y vec1 32 ssa_14 = mov ssa_13.y vec1 32 ssa_15 = deref_var &@1 (system uvec3) vec1 32 ssa_15 = deref_var &@1 (system uvec3) vec3 32 ssa_18 = intrinsic load_deref (ssa_15) (0) /* access=0 */ vec3 32 ssa_18 = intrinsic load_deref (ssa_15) (0) /* access=0 */ vec1 32 ssa_19 = mov ssa_18.z vec1 32 ssa_19 = mov ssa_18.z vec1 32 ssa_20 = imul ssa_14, ssa_19 vec1 32 ssa_20 = imul ssa_14, ssa_19 vec1 32 ssa_21 = deref_var &@1 (system uvec3) vec1 32 ssa_21 = deref_var &@1 (system uvec3) vec3 32 ssa_24 = intrinsic load_deref (ssa_21) (0) /* access=0 */ vec3 32 ssa_24 = intrinsic load_deref (ssa_21) (0) /* access=0 */ vec1 32 ssa_25 = mov ssa_24.y vec1 32 ssa_25 = mov ssa_24.y vec1 32 ssa_26 = iadd ssa_20, ssa_25 vec1 32 ssa_26 = iadd ssa_20, ssa_25 vec1 32 ssa_27 = imul ssa_9, ssa_26 vec1 32 ssa_27 = imul ssa_9, ssa_26 vec1 32 ssa_28 = deref_var &@1 (system uvec3) vec1 32 ssa_28 = deref_var &@1 (system uvec3) vec3 32 ssa_31 = intrinsic load_deref (ssa_28) (0) /* access=0 */ vec3 32 ssa_31 = intrinsic load_deref (ssa_28) (0) /* access=0 */ vec1 32 ssa_32 = mov ssa_31.x vec1 32 ssa_32 = mov ssa_31.x vec1 32 ssa_33 = iadd ssa_27, ssa_32 vec1 32 ssa_33 = iadd ssa_27, ssa_32 vec1 32 ssa_34 = deref_var &@5 (function_temp uint) vec1 32 ssa_34 = deref_var &@5 (function_temp uint) intrinsic store_deref (ssa_34, ssa_33) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_34, ssa_33) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_36 = deref_var &@6 (function_temp uvec4) vec1 32 ssa_36 = deref_var &@6 (function_temp uvec4) intrinsic store_deref (ssa_36, ssa_35) (15, 0) /* wrmask=xyzw */ /* access=0 */ intrinsic store_deref (ssa_36, ssa_35) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_38 = deref_var &@7 (function_temp uvec4) vec1 32 ssa_38 = deref_var &@7 (function_temp uvec4) intrinsic store_deref (ssa_38, ssa_37) (15, 0) /* wrmask=xyzw */ /* access=0 */ intrinsic store_deref (ssa_38, ssa_37) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_40 = deref_var &@8 (function_temp uint) vec1 32 ssa_40 = deref_var &@8 (function_temp uint) intrinsic store_deref (ssa_40, ssa_39) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_40, ssa_39) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_41 = deref_var &@2 (system uint) vec1 32 ssa_41 = deref_var &@2 (system uint) vec1 32 ssa_42 = intrinsic load_deref (ssa_41) (0) /* access=0 */ vec1 32 ssa_42 = intrinsic load_deref (ssa_41) (0) /* access=0 */ vec1 32 ssa_44 = iadd ssa_42, ssa_43 vec1 32 ssa_44 = iadd ssa_42, ssa_43 vec1 32 ssa_45 = deref_var &@9 (function_temp uint) vec1 32 ssa_45 = deref_var &@9 (function_temp uint) intrinsic store_deref (ssa_45, ssa_44) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_45, ssa_44) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_46 = deref_var &@9 (function_temp uint) vec1 32 ssa_46 = deref_var &@9 (function_temp uint) vec1 32 ssa_47 = intrinsic load_deref (ssa_46) (0) /* access=0 */ vec1 32 ssa_47 = intrinsic load_deref (ssa_46) (0) /* access=0 */ vec1 32 ssa_48 = deref_var &@6 (function_temp uvec4) vec1 32 ssa_48 = deref_var &@6 (function_temp uvec4) vec4 32 ssa_49 = intrinsic load_deref (ssa_48) (0) /* access=0 */ vec4 32 ssa_49 = intrinsic load_deref (ssa_48) (0) /* access=0 */ vec1 32 ssa_50 = intrinsic ballot_bit_count_inclusive (ssa_49) () vec1 32 ssa_50 = intrinsic ballot_bit_count_inclusive (ssa_49) () vec1 1 ssa_51 = ieq ssa_47, ssa_50 vec1 1 ssa_51 = ieq ssa_47, ssa_50 vec1 32 ssa_54 = bcsel ssa_51, ssa_53, ssa_52 vec1 32 ssa_54 = bcsel ssa_51, ssa_53, ssa_52 vec1 32 ssa_55 = mov ssa_54 vec1 32 ssa_55 = mov ssa_54 vec1 32 ssa_56 = deref_var &@8 (function_temp uint) vec1 32 ssa_56 = deref_var &@8 (function_temp uint) vec1 32 ssa_57 = intrinsic load_deref (ssa_56) (0) /* access=0 */ vec1 32 ssa_57 = intrinsic load_deref (ssa_56) (0) /* access=0 */ vec1 32 ssa_58 = ior ssa_57, ssa_55 vec1 32 ssa_58 = ior ssa_57, ssa_55 vec1 32 ssa_59 = deref_var &@8 (function_temp uint) vec1 32 ssa_59 = deref_var &@8 (function_temp uint) intrinsic store_deref (ssa_59, ssa_58) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_59, ssa_58) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_60 = deref_var &@7 (function_temp uvec4) vec1 32 ssa_60 = deref_var &@7 (function_temp uvec4) vec4 32 ssa_61 = intrinsic load_deref (ssa_60) (0) /* access=0 */ vec4 32 ssa_61 = intrinsic load_deref (ssa_60) (0) /* access=0 */ vec1 32 ssa_62 = intrinsic ballot_bit_count_inclusive (ssa_61) () vec1 32 ssa_62 = intrinsic ballot_bit_count_inclusive (ssa_61) () vec1 1 ssa_64 = ieq ssa_63, ssa_62 vec1 1 ssa_64 = ieq ssa_63, ssa_62 vec1 32 ssa_67 = bcsel ssa_64, ssa_66, ssa_65 vec1 32 ssa_67 = bcsel ssa_64, ssa_66, ssa_65 vec1 32 ssa_68 = mov ssa_67 vec1 32 ssa_68 = mov ssa_67 vec1 32 ssa_69 = deref_var &@8 (function_temp uint) vec1 32 ssa_69 = deref_var &@8 (function_temp uint) vec1 32 ssa_70 = intrinsic load_deref (ssa_69) (0) /* access=0 */ vec1 32 ssa_70 = intrinsic load_deref (ssa_69) (0) /* access=0 */ vec1 32 ssa_71 = ior ssa_70, ssa_68 vec1 32 ssa_71 = ior ssa_70, ssa_68 vec1 32 ssa_72 = deref_var &@8 (function_temp uint) vec1 32 ssa_72 = deref_var &@8 (function_temp uint) intrinsic store_deref (ssa_72, ssa_71) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_72, ssa_71) (1, 0) /* wrmask=x */ /* access=0 */ vec4 32 ssa_74 = intrinsic ballot (ssa_73) () vec4 32 ssa_74 = intrinsic ballot (ssa_73) () vec1 32 ssa_75 = intrinsic ballot_bit_count_inclusive (ssa_74) () vec1 32 ssa_75 = intrinsic ballot_bit_count_inclusive (ssa_74) () vec1 1 ssa_77 = ult ssa_76, ssa_75 vec1 1 ssa_77 = ult ssa_76, ssa_75 vec1 32 ssa_80 = bcsel ssa_77, ssa_79, ssa_78 vec1 32 ssa_80 = bcsel ssa_77, ssa_79, ssa_78 vec1 32 ssa_81 = mov ssa_80 vec1 32 ssa_81 = mov ssa_80 vec1 32 ssa_82 = deref_var &@8 (function_temp uint) vec1 32 ssa_82 = deref_var &@8 (function_temp uint) vec1 32 ssa_83 = intrinsic load_deref (ssa_82) (0) /* access=0 */ vec1 32 ssa_83 = intrinsic load_deref (ssa_82) (0) /* access=0 */ vec1 32 ssa_84 = ior ssa_83, ssa_81 vec1 32 ssa_84 = ior ssa_83, ssa_81 vec1 32 ssa_85 = deref_var &@8 (function_temp uint) vec1 32 ssa_85 = deref_var &@8 (function_temp uint) intrinsic store_deref (ssa_85, ssa_84) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_85, ssa_84) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_86 = deref_var &@8 (function_temp uint) vec1 32 ssa_86 = deref_var &@8 (function_temp uint) vec1 32 ssa_87 = intrinsic load_deref (ssa_86) (0) /* access=0 */ vec1 32 ssa_87 = intrinsic load_deref (ssa_86) (0) /* access=0 */ vec1 32 ssa_89 = ior ssa_87, ssa_88 vec1 32 ssa_89 = ior ssa_87, ssa_88 vec1 32 ssa_90 = deref_var &@8 (function_temp uint) vec1 32 ssa_90 = deref_var &@8 (function_temp uint) intrinsic store_deref (ssa_90, ssa_89) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_90, ssa_89) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_92 = deref_var &@10 (function_temp uint) vec1 32 ssa_92 = deref_var &@10 (function_temp uint) intrinsic store_deref (ssa_92, ssa_91) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_92, ssa_91) (1, 0) /* wrmask=x */ /* access=0 */ vec1 1 ssa_211 = load_const (false) vec1 1 ssa_211 = load_const (false) vec1 32 ssa_212 = deref_var &cont (function_temp bool) vec1 32 ssa_212 = deref_var &cont (function_temp bool) intrinsic store_deref (ssa_212, ssa_211) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_212, ssa_211) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_1 */ /* succs: block_1 */ loop { loop { block block_1: block block_1: /* preds: block_0 block_29 block_31 */ /* preds: block_0 block_29 block_31 */ vec1 32 ssa_213 = deref_var &cont (function_temp bool) vec1 32 ssa_213 = deref_var &cont (function_temp bool) vec1 1 ssa_214 = intrinsic load_deref (ssa_213) (0) /* access=0 */ vec1 1 ssa_214 = intrinsic load_deref (ssa_213) (0) /* access=0 */ /* succs: block_2 block_3 */ /* succs: block_2 block_3 */ if ssa_214 { if ssa_214 { block block_2: block block_2: /* preds: block_1 */ /* preds: block_1 */ vec1 32 ssa_215 = deref_var &@10 (function_temp uint) vec1 32 ssa_215 = deref_var &@10 (function_temp uint) vec1 32 ssa_216 = intrinsic load_deref (ssa_215) (0) /* access=0 */ vec1 32 ssa_216 = intrinsic load_deref (ssa_215) (0) /* access=0 */ vec1 32 ssa_218 = iadd ssa_216, ssa_217 vec1 32 ssa_218 = iadd ssa_216, ssa_217 vec1 32 ssa_219 = deref_var &@10 (function_temp uint) vec1 32 ssa_219 = deref_var &@10 (function_temp uint) intrinsic store_deref (ssa_219, ssa_218) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_219, ssa_218) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_4 */ /* succs: block_4 */ } else { } else { block block_3: block block_3: /* preds: block_1 */ /* preds: block_1 */ /* succs: block_4 */ /* succs: block_4 */ } } block block_4: block block_4: /* preds: block_2 block_3 */ /* preds: block_2 block_3 */ vec1 1 ssa_220 = load_const (true) vec1 1 ssa_220 = load_const (true) vec1 32 ssa_221 = deref_var &cont (function_temp bool) vec1 32 ssa_221 = deref_var &cont (function_temp bool) intrinsic store_deref (ssa_221, ssa_220) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_221, ssa_220) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_93 = deref_var &@10 (function_temp uint) vec1 32 ssa_93 = deref_var &@10 (function_temp uint) vec1 32 ssa_94 = intrinsic load_deref (ssa_93) (0) /* access=0 */ vec1 32 ssa_94 = intrinsic load_deref (ssa_93) (0) /* access=0 */ vec1 1 ssa_96 = ult ssa_94, ssa_95 vec1 1 ssa_96 = ult ssa_94, ssa_95 /* succs: block_5 block_30 */ /* succs: block_5 block_30 */ if ssa_96 { if ssa_96 { block block_5: block block_5: /* preds: block_4 */ /* preds: block_4 */ vec1 32 ssa_97 = deref_var &@9 (function_temp uint) vec1 32 ssa_97 = deref_var &@9 (function_temp uint) vec1 32 ssa_98 = intrinsic load_deref (ssa_97) (0) /* access=0 */ vec1 32 ssa_98 = intrinsic load_deref (ssa_97) (0) /* access=0 */ vec1 32 ssa_99 = deref_var &@9 (function_temp uint) vec1 32 ssa_99 = deref_var &@9 (function_temp uint) vec1 32 ssa_100 = intrinsic load_deref (ssa_99) (0) /* access=0 */ vec1 32 ssa_100 = intrinsic load_deref (ssa_99) (0) /* access=0 */ vec1 32 ssa_101 = deref_var &@10 (function_temp uint) vec1 32 ssa_101 = deref_var &@10 (function_temp uint) vec1 32 ssa_102 = intrinsic load_deref (ssa_101) (0) /* access=0 */ vec1 32 ssa_102 = intrinsic load_deref (ssa_101) (0) /* access=0 */ vec1 32 ssa_103 = umin ssa_100, ssa_102 vec1 32 ssa_103 = umin ssa_100, ssa_102 vec1 32 ssa_104 = isub ssa_98, ssa_103 vec1 32 ssa_104 = isub ssa_98, ssa_103 vec1 32 ssa_105 = deref_var &@11 (function_temp uint) vec1 32 ssa_105 = deref_var &@11 (function_temp uint) intrinsic store_deref (ssa_105, ssa_104) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_105, ssa_104) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_106 = deref_var &@10 (function_temp uint) vec1 32 ssa_106 = deref_var &@10 (function_temp uint) vec1 32 ssa_107 = intrinsic load_deref (ssa_106) (0) /* access=0 */ vec1 32 ssa_107 = intrinsic load_deref (ssa_106) (0) /* access=0 */ vec1 1 ssa_109 = uge ssa_107, ssa_108 vec1 1 ssa_109 = uge ssa_107, ssa_108 /* succs: block_6 block_7 */ /* succs: block_6 block_7 */ if ssa_109 { if ssa_109 { block block_6: block block_6: /* preds: block_5 */ /* preds: block_5 */ vec1 32 ssa_111 = deref_var &@13 (function_temp int) vec1 32 ssa_111 = deref_var &@13 (function_temp int) intrinsic store_deref (ssa_111, ssa_110) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_111, ssa_110) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_8 */ /* succs: block_8 */ } else { } else { block block_7: block block_7: /* preds: block_5 */ /* preds: block_5 */ vec1 32 ssa_112 = deref_var &@10 (function_temp uint) vec1 32 ssa_112 = deref_var &@10 (function_temp uint) vec1 32 ssa_113 = intrinsic load_deref (ssa_112) (0) /* access=0 */ vec1 32 ssa_113 = intrinsic load_deref (ssa_112) (0) /* access=0 */ vec1 32 ssa_115 = ishl ssa_114, ssa_113 vec1 32 ssa_115 = ishl ssa_114, ssa_113 vec1 32 ssa_116 = deref_var &@13 (function_temp int) vec1 32 ssa_116 = deref_var &@13 (function_temp int) intrinsic store_deref (ssa_116, ssa_115) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_116, ssa_115) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_8 */ /* succs: block_8 */ } } block block_8: block block_8: /* preds: block_6 block_7 */ /* preds: block_6 block_7 */ vec1 32 ssa_117 = deref_var &@13 (function_temp int) vec1 32 ssa_117 = deref_var &@13 (function_temp int) vec1 32 ssa_118 = intrinsic load_deref (ssa_117) (0) /* access=0 */ vec1 32 ssa_118 = intrinsic load_deref (ssa_117) (0) /* access=0 */ vec1 32 ssa_119 = mov ssa_118 vec1 32 ssa_119 = mov ssa_118 vec1 32 ssa_120 = deref_var &@10 (function_temp uint) vec1 32 ssa_120 = deref_var &@10 (function_temp uint) vec1 32 ssa_121 = intrinsic load_deref (ssa_120) (0) /* access=0 */ vec1 32 ssa_121 = intrinsic load_deref (ssa_120) (0) /* access=0 */ vec1 1 ssa_123 = uge ssa_121, ssa_122 vec1 1 ssa_123 = uge ssa_121, ssa_122 /* succs: block_9 block_10 */ /* succs: block_9 block_10 */ if ssa_123 { if ssa_123 { block block_9: block block_9: /* preds: block_8 */ /* preds: block_8 */ vec1 32 ssa_125 = deref_var &@14 (function_temp int) vec1 32 ssa_125 = deref_var &@14 (function_temp int) intrinsic store_deref (ssa_125, ssa_124) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_125, ssa_124) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_14 */ /* succs: block_14 */ } else { } else { block block_10: block block_10: /* preds: block_8 */ /* preds: block_8 */ vec1 32 ssa_126 = deref_var &@10 (function_temp uint) vec1 32 ssa_126 = deref_var &@10 (function_temp uint) vec1 32 ssa_127 = intrinsic load_deref (ssa_126) (0) /* access=0 */ vec1 32 ssa_127 = intrinsic load_deref (ssa_126) (0) /* access=0 */ vec1 1 ssa_129 = ult ssa_127, ssa_128 vec1 1 ssa_129 = ult ssa_127, ssa_128 /* succs: block_11 block_12 */ /* succs: block_11 block_12 */ if ssa_129 { if ssa_129 { block block_11: block block_11: /* preds: block_10 */ /* preds: block_10 */ vec1 32 ssa_131 = deref_var &@15 (function_temp uint) vec1 32 ssa_131 = deref_var &@15 (function_temp uint) intrinsic store_deref (ssa_131, ssa_130) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_131, ssa_130) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_13 */ /* succs: block_13 */ } else { } else { block block_12: block block_12: /* preds: block_10 */ /* preds: block_10 */ vec1 32 ssa_132 = deref_var &@10 (function_temp uint) vec1 32 ssa_132 = deref_var &@10 (function_temp uint) vec1 32 ssa_133 = intrinsic load_deref (ssa_132) (0) /* access=0 */ vec1 32 ssa_133 = intrinsic load_deref (ssa_132) (0) /* access=0 */ vec1 32 ssa_135 = isub ssa_133, ssa_134 vec1 32 ssa_135 = isub ssa_133, ssa_134 vec1 32 ssa_136 = deref_var &@15 (function_temp uint) vec1 32 ssa_136 = deref_var &@15 (function_temp uint) intrinsic store_deref (ssa_136, ssa_135) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_136, ssa_135) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_13 */ /* succs: block_13 */ } } block block_13: block block_13: /* preds: block_11 block_12 */ /* preds: block_11 block_12 */ vec1 32 ssa_137 = deref_var &@15 (function_temp uint) vec1 32 ssa_137 = deref_var &@15 (function_temp uint) vec1 32 ssa_138 = intrinsic load_deref (ssa_137) (0) /* access=0 */ vec1 32 ssa_138 = intrinsic load_deref (ssa_137) (0) /* access=0 */ vec1 32 ssa_140 = ishl ssa_139, ssa_138 vec1 32 ssa_140 = ishl ssa_139, ssa_138 vec1 32 ssa_141 = deref_var &@14 (function_temp int) vec1 32 ssa_141 = deref_var &@14 (function_temp int) intrinsic store_deref (ssa_141, ssa_140) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_141, ssa_140) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_14 */ /* succs: block_14 */ } } block block_14: block block_14: /* preds: block_9 block_13 */ /* preds: block_9 block_13 */ vec1 32 ssa_142 = deref_var &@14 (function_temp int) vec1 32 ssa_142 = deref_var &@14 (function_temp int) vec1 32 ssa_143 = intrinsic load_deref (ssa_142) (0) /* access=0 */ vec1 32 ssa_143 = intrinsic load_deref (ssa_142) (0) /* access=0 */ vec1 32 ssa_144 = mov ssa_143 vec1 32 ssa_144 = mov ssa_143 vec1 32 ssa_145 = deref_var &@10 (function_temp uint) vec1 32 ssa_145 = deref_var &@10 (function_temp uint) vec1 32 ssa_146 = intrinsic load_deref (ssa_145) (0) /* access=0 */ vec1 32 ssa_146 = intrinsic load_deref (ssa_145) (0) /* access=0 */ vec1 1 ssa_148 = uge ssa_146, ssa_147 vec1 1 ssa_148 = uge ssa_146, ssa_147 /* succs: block_15 block_16 */ /* succs: block_15 block_16 */ if ssa_148 { if ssa_148 { block block_15: block block_15: /* preds: block_14 */ /* preds: block_14 */ vec1 32 ssa_150 = deref_var &@16 (function_temp int) vec1 32 ssa_150 = deref_var &@16 (function_temp int) intrinsic store_deref (ssa_150, ssa_149) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_150, ssa_149) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_20 */ /* succs: block_20 */ } else { } else { block block_16: block block_16: /* preds: block_14 */ /* preds: block_14 */ vec1 32 ssa_151 = deref_var &@10 (function_temp uint) vec1 32 ssa_151 = deref_var &@10 (function_temp uint) vec1 32 ssa_152 = intrinsic load_deref (ssa_151) (0) /* access=0 */ vec1 32 ssa_152 = intrinsic load_deref (ssa_151) (0) /* access=0 */ vec1 1 ssa_154 = ult ssa_152, ssa_153 vec1 1 ssa_154 = ult ssa_152, ssa_153 /* succs: block_17 block_18 */ /* succs: block_17 block_18 */ if ssa_154 { if ssa_154 { block block_17: block block_17: /* preds: block_16 */ /* preds: block_16 */ vec1 32 ssa_156 = deref_var &@17 (function_temp uint) vec1 32 ssa_156 = deref_var &@17 (function_temp uint) intrinsic store_deref (ssa_156, ssa_155) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_156, ssa_155) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_19 */ /* succs: block_19 */ } else { } else { block block_18: block block_18: /* preds: block_16 */ /* preds: block_16 */ vec1 32 ssa_157 = deref_var &@10 (function_temp uint) vec1 32 ssa_157 = deref_var &@10 (function_temp uint) vec1 32 ssa_158 = intrinsic load_deref (ssa_157) (0) /* access=0 */ vec1 32 ssa_158 = intrinsic load_deref (ssa_157) (0) /* access=0 */ vec1 32 ssa_160 = isub ssa_158, ssa_159 vec1 32 ssa_160 = isub ssa_158, ssa_159 vec1 32 ssa_161 = deref_var &@17 (function_temp uint) vec1 32 ssa_161 = deref_var &@17 (function_temp uint) intrinsic store_deref (ssa_161, ssa_160) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_161, ssa_160) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_19 */ /* succs: block_19 */ } } block block_19: block block_19: /* preds: block_17 block_18 */ /* preds: block_17 block_18 */ vec1 32 ssa_162 = deref_var &@17 (function_temp uint) vec1 32 ssa_162 = deref_var &@17 (function_temp uint) vec1 32 ssa_163 = intrinsic load_deref (ssa_162) (0) /* access=0 */ vec1 32 ssa_163 = intrinsic load_deref (ssa_162) (0) /* access=0 */ vec1 32 ssa_165 = ishl ssa_164, ssa_163 vec1 32 ssa_165 = ishl ssa_164, ssa_163 vec1 32 ssa_166 = deref_var &@16 (function_temp int) vec1 32 ssa_166 = deref_var &@16 (function_temp int) intrinsic store_deref (ssa_166, ssa_165) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_166, ssa_165) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_20 */ /* succs: block_20 */ } } block block_20: block block_20: /* preds: block_15 block_19 */ /* preds: block_15 block_19 */ vec1 32 ssa_167 = deref_var &@16 (function_temp int) vec1 32 ssa_167 = deref_var &@16 (function_temp int) vec1 32 ssa_168 = intrinsic load_deref (ssa_167) (0) /* access=0 */ vec1 32 ssa_168 = intrinsic load_deref (ssa_167) (0) /* access=0 */ vec1 32 ssa_169 = mov ssa_168 vec1 32 ssa_169 = mov ssa_168 vec1 32 ssa_170 = deref_var &@10 (function_temp uint) vec1 32 ssa_170 = deref_var &@10 (function_temp uint) vec1 32 ssa_171 = intrinsic load_deref (ssa_170) (0) /* access=0 */ vec1 32 ssa_171 = intrinsic load_deref (ssa_170) (0) /* access=0 */ vec1 1 ssa_173 = uge ssa_171, ssa_172 vec1 1 ssa_173 = uge ssa_171, ssa_172 /* succs: block_21 block_22 */ /* succs: block_21 block_22 */ if ssa_173 { if ssa_173 { block block_21: block block_21: /* preds: block_20 */ /* preds: block_20 */ vec1 32 ssa_175 = deref_var &@18 (function_temp int) vec1 32 ssa_175 = deref_var &@18 (function_temp int) intrinsic store_deref (ssa_175, ssa_174) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_175, ssa_174) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_26 */ /* succs: block_26 */ } else { } else { block block_22: block block_22: /* preds: block_20 */ /* preds: block_20 */ vec1 32 ssa_176 = deref_var &@10 (function_temp uint) vec1 32 ssa_176 = deref_var &@10 (function_temp uint) vec1 32 ssa_177 = intrinsic load_deref (ssa_176) (0) /* access=0 */ vec1 32 ssa_177 = intrinsic load_deref (ssa_176) (0) /* access=0 */ vec1 1 ssa_179 = ult ssa_177, ssa_178 vec1 1 ssa_179 = ult ssa_177, ssa_178 /* succs: block_23 block_24 */ /* succs: block_23 block_24 */ if ssa_179 { if ssa_179 { block block_23: block block_23: /* preds: block_22 */ /* preds: block_22 */ vec1 32 ssa_181 = deref_var &@19 (function_temp uint) vec1 32 ssa_181 = deref_var &@19 (function_temp uint) intrinsic store_deref (ssa_181, ssa_180) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_181, ssa_180) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_25 */ /* succs: block_25 */ } else { } else { block block_24: block block_24: /* preds: block_22 */ /* preds: block_22 */ vec1 32 ssa_182 = deref_var &@10 (function_temp uint) vec1 32 ssa_182 = deref_var &@10 (function_temp uint) vec1 32 ssa_183 = intrinsic load_deref (ssa_182) (0) /* access=0 */ vec1 32 ssa_183 = intrinsic load_deref (ssa_182) (0) /* access=0 */ vec1 32 ssa_185 = isub ssa_183, ssa_184 vec1 32 ssa_185 = isub ssa_183, ssa_184 vec1 32 ssa_186 = deref_var &@19 (function_temp uint) vec1 32 ssa_186 = deref_var &@19 (function_temp uint) intrinsic store_deref (ssa_186, ssa_185) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_186, ssa_185) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_25 */ /* succs: block_25 */ } } block block_25: block block_25: /* preds: block_23 block_24 */ /* preds: block_23 block_24 */ vec1 32 ssa_187 = deref_var &@19 (function_temp uint) vec1 32 ssa_187 = deref_var &@19 (function_temp uint) vec1 32 ssa_188 = intrinsic load_deref (ssa_187) (0) /* access=0 */ vec1 32 ssa_188 = intrinsic load_deref (ssa_187) (0) /* access=0 */ vec1 32 ssa_190 = ishl ssa_189, ssa_188 vec1 32 ssa_190 = ishl ssa_189, ssa_188 vec1 32 ssa_191 = deref_var &@18 (function_temp int) vec1 32 ssa_191 = deref_var &@18 (function_temp int) intrinsic store_deref (ssa_191, ssa_190) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_191, ssa_190) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_26 */ /* succs: block_26 */ } } block block_26: block block_26: /* preds: block_21 block_25 */ /* preds: block_21 block_25 */ vec1 32 ssa_192 = deref_var &@18 (function_temp int) vec1 32 ssa_192 = deref_var &@18 (function_temp int) vec1 32 ssa_193 = intrinsic load_deref (ssa_192) (0) /* access=0 */ vec1 32 ssa_193 = intrinsic load_deref (ssa_192) (0) /* access=0 */ vec1 32 ssa_194 = mov ssa_193 vec1 32 ssa_194 = mov ssa_193 vec4 32 ssa_195 = vec4 ssa_119, ssa_144, ssa_169, ssa_194 vec4 32 ssa_195 = vec4 ssa_119, ssa_144, ssa_169, ssa_194 vec1 32 ssa_196 = deref_var &@12 (function_temp uvec4) vec1 32 ssa_196 = deref_var &@12 (function_temp uvec4) intrinsic store_deref (ssa_196, ssa_195) (15, 0) /* wrmask=xyzw */ /* access=0 */ intrinsic store_deref (ssa_196, ssa_195) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_197 = deref_var &@12 (function_temp uvec4) vec1 32 ssa_197 = deref_var &@12 (function_temp uvec4) vec4 32 ssa_198 = intrinsic load_deref (ssa_197) (0) /* access=0 */ vec4 32 ssa_198 = intrinsic load_deref (ssa_197) (0) /* access=0 */ vec1 32 ssa_199 = intrinsic ballot_bit_count_inclusive (ssa_198) () vec1 32 ssa_199 = intrinsic ballot_bit_count_inclusive (ssa_198) () vec1 32 ssa_200 = deref_var &@20 (function_temp uint) vec1 32 ssa_200 = deref_var &@20 (function_temp uint) intrinsic store_deref (ssa_200, ssa_199) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_200, ssa_199) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_201 = deref_var &@20 (function_temp uint) vec1 32 ssa_201 = deref_var &@20 (function_temp uint) vec1 32 ssa_202 = intrinsic load_deref (ssa_201) (0) /* access=0 */ vec1 32 ssa_202 = intrinsic load_deref (ssa_201) (0) /* access=0 */ vec1 32 ssa_203 = deref_var &@11 (function_temp uint) vec1 32 ssa_203 = deref_var &@11 (function_temp uint) vec1 32 ssa_204 = intrinsic load_deref (ssa_203) (0) /* access=0 */ vec1 32 ssa_204 = intrinsic load_deref (ssa_203) (0) /* access=0 */ vec1 1 ssa_205 = ine ssa_202, ssa_204 vec1 1 ssa_205 = ine ssa_202, ssa_204 /* succs: block_27 block_28 */ /* succs: block_27 block_28 */ if ssa_205 { if ssa_205 { block block_27: block block_27: /* preds: block_26 */ /* preds: block_26 */ vec1 32 ssa_206 = deref_var &@8 (function_temp uint) vec1 32 ssa_206 = deref_var &@8 (function_temp uint) vec1 32 ssa_207 = intrinsic load_deref (ssa_206) (0) /* access=0 */ vec1 32 ssa_207 = intrinsic load_deref (ssa_206) (0) /* access=0 */ vec1 32 ssa_209 = iand ssa_207, ssa_208 vec1 32 ssa_209 = iand ssa_207, ssa_208 vec1 32 ssa_210 = deref_var &@8 (function_temp uint) vec1 32 ssa_210 = deref_var &@8 (function_temp uint) intrinsic store_deref (ssa_210, ssa_209) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_210, ssa_209) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_29 */ /* succs: block_29 */ } else { } else { block block_28: block block_28: /* preds: block_26 */ /* preds: block_26 */ /* succs: block_29 */ /* succs: block_29 */ } } block block_29: block block_29: /* preds: block_27 block_28 */ /* preds: block_27 block_28 */ continue continue /* succs: block_1 */ /* succs: block_1 */ } else { } else { block block_30: block block_30: /* preds: block_4 */ /* preds: block_4 */ break break /* succs: block_32 */ /* succs: block_32 */ } } block block_31: block block_31: /* preds: */ /* preds: */ /* succs: block_1 */ /* succs: block_1 */ } } block block_32: block block_32: /* preds: block_30 */ /* preds: block_30 */ vec1 32 ssa_222 = deref_var &@5 (function_temp uint) vec1 32 ssa_222 = deref_var &@5 (function_temp uint) vec1 32 ssa_223 = intrinsic load_deref (ssa_222) (0) /* access=0 */ vec1 32 ssa_223 = intrinsic load_deref (ssa_222) (0) /* access=0 */ vec1 32 ssa_224 = deref_var &@8 (function_temp uint) vec1 32 ssa_224 = deref_var &@8 (function_temp uint) vec1 32 ssa_225 = intrinsic load_deref (ssa_224) (0) /* access=0 */ vec1 32 ssa_225 = intrinsic load_deref (ssa_224) (0) /* access=0 */ vec1 32 ssa_226 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_226 = load_const (0x00000000 /* 0.000000 */) vec1 64 ssa_227 = intrinsic vulkan_resource_index (ssa_226) (0, 0, 7) /* desc-set=0 */ /* binding=0 */ /* des vec1 64 ssa_227 = intrinsic vulkan_resource_index (ssa_226) (0, 0, 7) /* desc-set=0 */ /* binding=0 */ /* des vec1 64 ssa_228 = intrinsic load_vulkan_descriptor (ssa_227) (7) /* desc_type=SSBO */ vec1 64 ssa_228 = intrinsic load_vulkan_descriptor (ssa_227) (7) /* desc_type=SSBO */ vec1 64 ssa_229 = deref_cast (block *)ssa_228 (ssbo block) /* ptr_stride=0, align_mul=0, align_offset=0 */ vec1 64 ssa_229 = deref_cast (block *)ssa_228 (ssbo block) /* ptr_stride=0, align_mul=0, align_offset=0 */ vec1 64 ssa_230 = deref_struct &ssa_229->field0 (ssbo uint[]) /* &((block *)ssa_228)->field0 */ vec1 64 ssa_230 = deref_struct &ssa_229->field0 (ssbo uint[]) /* &((block *)ssa_228)->field0 */ vec1 64 ssa_231 = i2i64 ssa_223 vec1 64 ssa_231 = i2i64 ssa_223 vec1 64 ssa_232 = deref_array &(*ssa_230)[ssa_231] (ssbo uint) /* &((block *)ssa_228)->field0[ssa_231] */ vec1 64 ssa_232 = deref_array &(*ssa_230)[ssa_231] (ssbo uint) /* &((block *)ssa_228)->field0[ssa_231] */ intrinsic store_deref (ssa_232, ssa_225) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_232, ssa_225) (1, 0) /* wrmask=x */ /* access=0 */ return return /* succs: block_33 */ /* succs: block_33 */ block block_33: block block_33: } } NIR (SSA form) for compute shader: NIR (SSA form) for compute shader: shader: MESA_SHADER_COMPUTE shader: MESA_SHADER_COMPUTE local-size: 1, 1, 32 local-size: 1, 1, 32 shared-size: 0 shared-size: 0 inputs: 0 inputs: 0 outputs: 0 outputs: 0 uniforms: 36 uniforms: 36 shared: 0 shared: 0 decl_var ssbo INTERP_MODE_NONE restrict block @0 (~0, 0, 0) decl_var ssbo INTERP_MODE_NONE restrict block @0 (~0, 0, 0) decl_function main (0 params) decl_function main (0 params) impl main { impl main { block block_0: block block_0: /* preds: */ /* preds: */ vec1 32 ssa_0 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_0 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_1 = load_const (0xfffffff7 /* -nan */) vec1 32 ssa_1 = load_const (0xfffffff7 /* -nan */) vec1 32 ssa_2 = load_const (0xffffffff /* -nan */) vec1 32 ssa_2 = load_const (0xffffffff /* -nan */) vec1 32 ssa_3 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_4 = load_const (0x00000080 /* 0.000000 */) vec1 32 ssa_4 = load_const (0x00000080 /* 0.000000 */) vec1 32 ssa_5 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_5 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_6 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_6 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_7 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_7 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_8 = load_const (0xffffffff /* -nan */) vec1 32 ssa_8 = load_const (0xffffffff /* -nan */) vec3 32 ssa_9 = intrinsic load_num_work_groups () () vec3 32 ssa_9 = intrinsic load_num_work_groups () () vec3 32 ssa_10 = intrinsic load_work_group_id () () vec3 32 ssa_10 = intrinsic load_work_group_id () () vec3 32 ssa_11 = intrinsic load_uniform (ssa_3) (24, 12, 0) /* base=24 */ /* range=12 */ /* dest_type=invalid vec3 32 ssa_11 = intrinsic load_uniform (ssa_3) (24, 12, 0) /* base=24 */ /* range=12 */ /* dest_type=invalid vec1 32 ssa_12 = iadd ssa_10.x, ssa_11.x vec1 32 ssa_12 = iadd ssa_10.x, ssa_11.x vec1 32 ssa_13 = iadd ssa_10.y, ssa_11.y vec1 32 ssa_13 = iadd ssa_10.y, ssa_11.y vec1 32 ssa_14 = iadd ssa_10.z, ssa_11.z vec1 32 ssa_14 = iadd ssa_10.z, ssa_11.z vec1 32 ssa_15 = intrinsic load_subgroup_id () () vec1 32 ssa_15 = intrinsic load_subgroup_id () () vec1 32 ssa_16 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_16 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_17 = ishl ssa_15, ssa_16 vec1 32 ssa_17 = ishl ssa_15, ssa_16 vec1 32 ssa_18 = intrinsic load_subgroup_invocation () () vec1 32 ssa_18 = intrinsic load_subgroup_invocation () () vec1 32 ssa_19 = iadd ssa_18, ssa_17 vec1 32 ssa_19 = iadd ssa_18, ssa_17 vec1 32 ssa_20 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_20 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_21 = ishl ssa_14, ssa_20 vec1 32 ssa_21 = ishl ssa_14, ssa_20 vec1 32 ssa_22 = iadd ssa_21, ssa_19 vec1 32 ssa_22 = iadd ssa_21, ssa_19 vec1 32 ssa_23 = imul ssa_9.y, ssa_22 vec1 32 ssa_23 = imul ssa_9.y, ssa_22 vec1 32 ssa_24 = iadd ssa_23, ssa_13 vec1 32 ssa_24 = iadd ssa_23, ssa_13 vec1 32 ssa_25 = imul ssa_9.x, ssa_24 vec1 32 ssa_25 = imul ssa_9.x, ssa_24 vec1 32 ssa_26 = iadd ssa_25, ssa_12 vec1 32 ssa_26 = iadd ssa_25, ssa_12 vec1 32 ssa_27 = iadd ssa_18, ssa_0 vec1 32 ssa_27 = iadd ssa_18, ssa_0 vec1 32 ssa_28 = load_const (0x0000001f /* 0.000000 */) vec1 32 ssa_28 = load_const (0x0000001f /* 0.000000 */) vec1 32 ssa_29 = ineg ssa_18 vec1 32 ssa_29 = ineg ssa_18 vec1 32 ssa_30 = iadd ssa_28, ssa_29 vec1 32 ssa_30 = iadd ssa_28, ssa_29 vec1 32 ssa_31 = ushr ssa_2, ssa_30 vec1 32 ssa_31 = ushr ssa_2, ssa_30 vec1 32 ssa_32 = bit_count ssa_31 vec1 32 ssa_32 = bit_count ssa_31 vec1 32 ssa_33 = ieq32 ssa_27, ssa_32 vec1 32 ssa_33 = ieq32 ssa_27, ssa_32 vec1 32 ssa_34 = b2i32 ssa_33 vec1 32 ssa_34 = b2i32 ssa_33 vec1 32 ssa_35 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_35 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_36 = ior ssa_34, ssa_35 vec1 32 ssa_36 = ior ssa_34, ssa_35 vec1 32 ssa_37 = intrinsic ballot (ssa_8) () vec1 32 ssa_37 = intrinsic ballot (ssa_8) () vec1 32 ssa_38 = iand ssa_37, ssa_31 vec1 32 ssa_38 = iand ssa_37, ssa_31 vec1 32 ssa_39 = bit_count ssa_38 vec1 32 ssa_39 = bit_count ssa_38 vec1 32 ssa_40 = ult32 ssa_3, ssa_39 vec1 32 ssa_40 = ult32 ssa_3, ssa_39 vec1 32 ssa_41 = b32csel ssa_40, ssa_7, ssa_3 vec1 32 ssa_41 = b32csel ssa_40, ssa_7, ssa_3 vec1 32 ssa_42 = ior ssa_36, ssa_41 vec1 32 ssa_42 = ior ssa_36, ssa_41 vec1 32 ssa_43 = ior ssa_42, ssa_6 vec1 32 ssa_43 = ior ssa_42, ssa_6 /* succs: block_1 */ /* succs: block_1 */ loop { loop { block block_1: block block_1: /* preds: block_0 block_4 */ /* preds: block_0 block_4 */ vec1 32 ssa_44 = phi block_0: ssa_43, block_4: ssa_57 vec1 32 ssa_44 = phi block_0: ssa_43, block_4: ssa_57 vec1 32 ssa_45 = phi block_0: ssa_3, block_4: ssa_58 vec1 32 ssa_45 = phi block_0: ssa_3, block_4: ssa_58 vec1 32 ssa_46 = uge32 ssa_45, ssa_4 vec1 32 ssa_46 = uge32 ssa_45, ssa_4 /* succs: block_2 block_3 */ /* succs: block_2 block_3 */ if ssa_46 { if ssa_46 { block block_2: block block_2: /* preds: block_1 */ /* preds: block_1 */ break break /* succs: block_5 */ /* succs: block_5 */ } else { } else { block block_3: block block_3: /* preds: block_1 */ /* preds: block_1 */ /* succs: block_4 */ /* succs: block_4 */ } } block block_4: block block_4: /* preds: block_3 */ /* preds: block_3 */ vec1 32 ssa_47 = umin ssa_27, ssa_45 vec1 32 ssa_47 = umin ssa_27, ssa_45 vec1 32 ssa_48 = ineg ssa_47 vec1 32 ssa_48 = ineg ssa_47 vec1 32 ssa_49 = iadd ssa_27, ssa_48 vec1 32 ssa_49 = iadd ssa_27, ssa_48 vec1 32 ssa_50 = ishl ssa_2, ssa_45 vec1 32 ssa_50 = ishl ssa_2, ssa_45 vec1 32 ssa_51 = uge32 ssa_45, ssa_5 vec1 32 ssa_51 = uge32 ssa_45, ssa_5 vec1 32 ssa_52 = b32csel ssa_51, ssa_3, ssa_50 vec1 32 ssa_52 = b32csel ssa_51, ssa_3, ssa_50 vec1 32 ssa_53 = iand ssa_52, ssa_31 vec1 32 ssa_53 = iand ssa_52, ssa_31 vec1 32 ssa_54 = bit_count ssa_53 vec1 32 ssa_54 = bit_count ssa_53 vec1 32 ssa_55 = iand ssa_44, ssa_1 vec1 32 ssa_55 = iand ssa_44, ssa_1 vec1 32 ssa_56 = ine32 ssa_54, ssa_49 vec1 32 ssa_56 = ine32 ssa_54, ssa_49 vec1 32 ssa_57 = b32csel ssa_56, ssa_55, ssa_44 vec1 32 ssa_57 = b32csel ssa_56, ssa_55, ssa_44 vec1 32 ssa_58 = iadd ssa_45, ssa_0 vec1 32 ssa_58 = iadd ssa_45, ssa_0 /* succs: block_1 */ /* succs: block_1 */ } } block block_5: block block_5: /* preds: block_2 */ /* preds: block_2 */ vec1 32 ssa_59 = ishl ssa_26, ssa_35 vec1 32 ssa_59 = ishl ssa_26, ssa_35 intrinsic store_ssbo (ssa_44, ssa_35, ssa_59) (1, 0, 4, 0) /* wrmask=x */ /* access=0 */ /* align_mul=4 */ /* intrinsic store_ssbo (ssa_44, ssa_35, ssa_59) (1, 0, 4, 0) /* wrmask=x */ /* access=0 */ /* align_mul=4 */ /* /* succs: block_6 */ /* succs: block_6 */ block block_6: block block_6: } } NIR (final form) for compute shader: NIR (final form) for compute shader: shader: MESA_SHADER_COMPUTE shader: MESA_SHADER_COMPUTE local-size: 1, 1, 32 local-size: 1, 1, 32 shared-size: 0 shared-size: 0 inputs: 0 inputs: 0 outputs: 0 outputs: 0 uniforms: 36 uniforms: 36 shared: 0 shared: 0 decl_var ssbo INTERP_MODE_NONE restrict block @0 (~0, 0, 0) decl_var ssbo INTERP_MODE_NONE restrict block @0 (~0, 0, 0) decl_function main (0 params) decl_function main (0 params) impl main { impl main { decl_reg vec1 32 r3 decl_reg vec1 32 r3 decl_reg vec1 32 r4 decl_reg vec1 32 r4 block block_0: block block_0: /* preds: */ /* preds: */ vec1 32 ssa_0 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_0 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_1 = load_const (0xfffffff7 /* -nan */) vec1 32 ssa_1 = load_const (0xfffffff7 /* -nan */) vec1 32 ssa_2 = load_const (0xffffffff /* -nan */) vec1 32 ssa_2 = load_const (0xffffffff /* -nan */) vec1 32 ssa_3 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_4 = load_const (0x00000080 /* 0.000000 */) vec1 32 ssa_4 = load_const (0x00000080 /* 0.000000 */) vec1 32 ssa_5 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_5 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_6 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_6 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_7 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_7 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_8 = load_const (0xffffffff /* -nan */) vec1 32 ssa_8 = load_const (0xffffffff /* -nan */) vec3 32 ssa_9 = intrinsic load_num_work_groups () () vec3 32 ssa_9 = intrinsic load_num_work_groups () () vec3 32 ssa_10 = intrinsic load_work_group_id () () vec3 32 ssa_10 = intrinsic load_work_group_id () () vec3 32 ssa_11 = intrinsic load_uniform (ssa_3) (24, 12, 0) /* base=24 */ /* range=12 */ /* dest_type=invalid vec3 32 ssa_11 = intrinsic load_uniform (ssa_3) (24, 12, 0) /* base=24 */ /* range=12 */ /* dest_type=invalid vec1 32 ssa_12 = iadd ssa_10.x, ssa_11.x vec1 32 ssa_12 = iadd ssa_10.x, ssa_11.x vec1 32 ssa_13 = iadd ssa_10.y, ssa_11.y vec1 32 ssa_13 = iadd ssa_10.y, ssa_11.y vec1 32 ssa_14 = iadd ssa_10.z, ssa_11.z vec1 32 ssa_14 = iadd ssa_10.z, ssa_11.z vec1 32 ssa_15 = intrinsic load_subgroup_id () () vec1 32 ssa_15 = intrinsic load_subgroup_id () () vec1 32 ssa_16 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_16 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_17 = ishl ssa_15, ssa_16 vec1 32 ssa_17 = ishl ssa_15, ssa_16 vec1 32 ssa_18 = intrinsic load_subgroup_invocation () () vec1 32 ssa_18 = intrinsic load_subgroup_invocation () () vec1 32 ssa_19 = iadd ssa_18, ssa_17 vec1 32 ssa_19 = iadd ssa_18, ssa_17 vec1 32 ssa_20 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_20 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_21 = ishl ssa_14, ssa_20 vec1 32 ssa_21 = ishl ssa_14, ssa_20 vec1 32 ssa_22 = iadd ssa_21, ssa_19 vec1 32 ssa_22 = iadd ssa_21, ssa_19 vec1 32 ssa_23 = imul ssa_9.y, ssa_22 vec1 32 ssa_23 = imul ssa_9.y, ssa_22 vec1 32 ssa_24 = iadd ssa_23, ssa_13 vec1 32 ssa_24 = iadd ssa_23, ssa_13 vec1 32 ssa_25 = imul ssa_9.x, ssa_24 vec1 32 ssa_25 = imul ssa_9.x, ssa_24 vec1 32 ssa_26 = iadd ssa_25, ssa_12 vec1 32 ssa_26 = iadd ssa_25, ssa_12 vec1 32 ssa_27 = iadd ssa_18, ssa_0 vec1 32 ssa_27 = iadd ssa_18, ssa_0 vec1 32 ssa_28 = load_const (0x0000001f /* 0.000000 */) vec1 32 ssa_28 = load_const (0x0000001f /* 0.000000 */) vec1 32 ssa_29 = ineg ssa_18 vec1 32 ssa_29 = ineg ssa_18 vec1 32 ssa_30 = iadd ssa_28, ssa_29 vec1 32 ssa_30 = iadd ssa_28, ssa_29 vec1 32 ssa_31 = ushr ssa_2, ssa_30 vec1 32 ssa_31 = ushr ssa_2, ssa_30 vec1 32 ssa_32 = bit_count ssa_31 vec1 32 ssa_32 = bit_count ssa_31 vec1 32 ssa_33 = ieq32 ssa_27, ssa_32 vec1 32 ssa_33 = ieq32 ssa_27, ssa_32 vec1 32 ssa_34 = b2i32 ssa_33 vec1 32 ssa_34 = b2i32 ssa_33 vec1 32 ssa_35 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_35 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_36 = ior ssa_34, ssa_35 vec1 32 ssa_36 = ior ssa_34, ssa_35 vec1 32 ssa_37 = intrinsic ballot (ssa_8) () vec1 32 ssa_37 = intrinsic ballot (ssa_8) () vec1 32 ssa_38 = iand ssa_37, ssa_31 vec1 32 ssa_38 = iand ssa_37, ssa_31 vec1 32 ssa_39 = bit_count ssa_38 vec1 32 ssa_39 = bit_count ssa_38 vec1 32 ssa_40 = ult32 ssa_3, ssa_39 vec1 32 ssa_40 = ult32 ssa_3, ssa_39 vec1 32 ssa_41 = b32csel ssa_40, ssa_7, ssa_3 vec1 32 ssa_41 = b32csel ssa_40, ssa_7, ssa_3 vec1 32 ssa_42 = ior ssa_36, ssa_41 vec1 32 ssa_42 = ior ssa_36, ssa_41 r3 = ior ssa_42, ssa_6 r3 = ior ssa_42, ssa_6 r4 = mov ssa_3 r4 = mov ssa_3 /* succs: block_1 */ /* succs: block_1 */ loop { loop { block block_1: block block_1: /* preds: block_0 block_4 */ /* preds: block_0 block_4 */ vec1 32 ssa_46 = uge32 r4, ssa_4 vec1 32 ssa_46 = uge32 r4, ssa_4 /* succs: block_2 block_3 */ /* succs: block_2 block_3 */ if ssa_46 { if ssa_46 { block block_2: block block_2: /* preds: block_1 */ /* preds: block_1 */ break break /* succs: block_5 */ /* succs: block_5 */ } else { } else { block block_3: block block_3: /* preds: block_1 */ /* preds: block_1 */ /* succs: block_4 */ /* succs: block_4 */ } } block block_4: block block_4: /* preds: block_3 */ /* preds: block_3 */ vec1 32 ssa_47 = umin ssa_27, r4 vec1 32 ssa_47 = umin ssa_27, r4 vec1 32 ssa_48 = ineg ssa_47 vec1 32 ssa_48 = ineg ssa_47 vec1 32 ssa_49 = iadd ssa_27, ssa_48 vec1 32 ssa_49 = iadd ssa_27, ssa_48 vec1 32 ssa_50 = ishl ssa_2, r4 vec1 32 ssa_50 = ishl ssa_2, r4 vec1 32 ssa_51 = uge32 r4, ssa_5 vec1 32 ssa_51 = uge32 r4, ssa_5 vec1 32 ssa_52 = b32csel ssa_51, ssa_3, ssa_50 vec1 32 ssa_52 = b32csel ssa_51, ssa_3, ssa_50 vec1 32 ssa_53 = iand ssa_52, ssa_31 vec1 32 ssa_53 = iand ssa_52, ssa_31 vec1 32 ssa_54 = bit_count ssa_53 vec1 32 ssa_54 = bit_count ssa_53 vec1 32 ssa_55 = iand r3, ssa_1 vec1 32 ssa_55 = iand r3, ssa_1 vec1 32 ssa_56 = ine32 ssa_54, ssa_49 vec1 32 ssa_56 = ine32 ssa_54, ssa_49 r3 = b32csel ssa_56, ssa_55, r3 r3 = b32csel ssa_56, ssa_55, r3 r4 = iadd r4, ssa_0 r4 = iadd r4, ssa_0 /* succs: block_1 */ /* succs: block_1 */ } } block block_5: block block_5: /* preds: block_2 */ /* preds: block_2 */ vec1 32 ssa_59 = ishl ssa_26, ssa_35 vec1 32 ssa_59 = ishl ssa_26, ssa_35 intrinsic store_ssbo (r3, ssa_35, ssa_59) (1, 0, 4, 0) /* wrmask=x */ /* access=0 */ /* align_mul=4 */ /* ali intrinsic store_ssbo (r3, ssa_35, ssa_59) (1, 0, 4, 0) /* wrmask=x */ /* access=0 */ /* align_mul=4 */ /* ali /* succs: block_6 */ /* succs: block_6 */ block block_6: block block_6: } } NIR (SSA form) for compute shader: NIR (SSA form) for compute shader: shader: MESA_SHADER_COMPUTE shader: MESA_SHADER_COMPUTE local-size: 1, 1, 32 local-size: 1, 1, 32 shared-size: 0 shared-size: 0 inputs: 0 inputs: 0 outputs: 0 outputs: 0 uniforms: 36 uniforms: 36 shared: 0 shared: 0 decl_var ssbo INTERP_MODE_NONE restrict block @0 (~0, 0, 0) decl_var ssbo INTERP_MODE_NONE restrict block @0 (~0, 0, 0) decl_function main (0 params) decl_function main (0 params) impl main { impl main { block block_0: block block_0: /* preds: */ /* preds: */ vec1 32 ssa_0 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_0 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_1 = load_const (0xfffffff7 /* -nan */) vec1 32 ssa_1 = load_const (0xfffffff7 /* -nan */) vec1 32 ssa_2 = load_const (0xffffffff /* -nan */) vec1 32 ssa_2 = load_const (0xffffffff /* -nan */) vec1 32 ssa_3 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_4 = load_const (0x00000080 /* 0.000000 */) vec1 32 ssa_4 = load_const (0x00000080 /* 0.000000 */) vec1 32 ssa_5 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_5 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_6 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_6 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_7 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_7 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_8 = load_const (0xffffffff /* -nan */) vec1 32 ssa_8 = load_const (0xffffffff /* -nan */) vec3 32 ssa_9 = intrinsic load_num_work_groups () () vec3 32 ssa_9 = intrinsic load_num_work_groups () () vec3 32 ssa_10 = intrinsic load_work_group_id () () vec3 32 ssa_10 = intrinsic load_work_group_id () () vec3 32 ssa_11 = intrinsic load_uniform (ssa_3) (24, 12, 0) /* base=24 */ /* range=12 */ /* dest_type=invalid vec3 32 ssa_11 = intrinsic load_uniform (ssa_3) (24, 12, 0) /* base=24 */ /* range=12 */ /* dest_type=invalid vec1 32 ssa_12 = iadd ssa_10.x, ssa_11.x vec1 32 ssa_12 = iadd ssa_10.x, ssa_11.x vec1 32 ssa_13 = iadd ssa_10.y, ssa_11.y vec1 32 ssa_13 = iadd ssa_10.y, ssa_11.y vec1 32 ssa_14 = iadd ssa_10.z, ssa_11.z vec1 32 ssa_14 = iadd ssa_10.z, ssa_11.z vec1 32 ssa_15 = intrinsic load_subgroup_id () () vec1 32 ssa_15 = intrinsic load_subgroup_id () () vec1 32 ssa_16 = ishl ssa_15, ssa_7 vec1 32 ssa_16 = ishl ssa_15, ssa_7 vec1 32 ssa_17 = intrinsic load_subgroup_invocation () () vec1 32 ssa_17 = intrinsic load_subgroup_invocation () () vec1 32 ssa_18 = iadd ssa_17, ssa_16 vec1 32 ssa_18 = iadd ssa_17, ssa_16 vec1 32 ssa_19 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_19 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_20 = ishl ssa_14, ssa_19 vec1 32 ssa_20 = ishl ssa_14, ssa_19 vec1 32 ssa_21 = iadd ssa_20, ssa_18 vec1 32 ssa_21 = iadd ssa_20, ssa_18 vec1 32 ssa_22 = imul ssa_9.y, ssa_21 vec1 32 ssa_22 = imul ssa_9.y, ssa_21 vec1 32 ssa_23 = iadd ssa_22, ssa_13 vec1 32 ssa_23 = iadd ssa_22, ssa_13 vec1 32 ssa_24 = imul ssa_9.x, ssa_23 vec1 32 ssa_24 = imul ssa_9.x, ssa_23 vec1 32 ssa_25 = iadd ssa_24, ssa_12 vec1 32 ssa_25 = iadd ssa_24, ssa_12 vec1 32 ssa_26 = iadd ssa_17, ssa_0 vec1 32 ssa_26 = iadd ssa_17, ssa_0 vec1 32 ssa_27 = load_const (0x0000001f /* 0.000000 */) vec1 32 ssa_27 = load_const (0x0000001f /* 0.000000 */) vec1 32 ssa_28 = ineg ssa_17 vec1 32 ssa_28 = ineg ssa_17 vec1 32 ssa_29 = iadd ssa_27, ssa_28 vec1 32 ssa_29 = iadd ssa_27, ssa_28 vec1 32 ssa_30 = ushr ssa_2, ssa_29 vec1 32 ssa_30 = ushr ssa_2, ssa_29 vec1 32 ssa_31 = bit_count ssa_30 vec1 32 ssa_31 = bit_count ssa_30 vec1 32 ssa_32 = ieq32 ssa_26, ssa_31 vec1 32 ssa_32 = ieq32 ssa_26, ssa_31 vec1 32 ssa_33 = b2i32 ssa_32 vec1 32 ssa_33 = b2i32 ssa_32 vec1 32 ssa_34 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_34 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_35 = ior ssa_33, ssa_34 vec1 32 ssa_35 = ior ssa_33, ssa_34 vec1 32 ssa_36 = intrinsic ballot (ssa_8) () vec1 32 ssa_36 = intrinsic ballot (ssa_8) () vec1 32 ssa_37 = iand ssa_36, ssa_30 vec1 32 ssa_37 = iand ssa_36, ssa_30 vec1 32 ssa_38 = bit_count ssa_37 vec1 32 ssa_38 = bit_count ssa_37 vec1 32 ssa_39 = ult32 ssa_3, ssa_38 vec1 32 ssa_39 = ult32 ssa_3, ssa_38 vec1 32 ssa_40 = b32csel ssa_39, ssa_7, ssa_3 vec1 32 ssa_40 = b32csel ssa_39, ssa_7, ssa_3 vec1 32 ssa_41 = ior ssa_35, ssa_40 vec1 32 ssa_41 = ior ssa_35, ssa_40 vec1 32 ssa_42 = ior ssa_41, ssa_6 vec1 32 ssa_42 = ior ssa_41, ssa_6 /* succs: block_1 */ /* succs: block_1 */ loop { loop { block block_1: block block_1: /* preds: block_0 block_4 */ /* preds: block_0 block_4 */ vec1 32 ssa_43 = phi block_0: ssa_42, block_4: ssa_56 vec1 32 ssa_43 = phi block_0: ssa_42, block_4: ssa_56 vec1 32 ssa_44 = phi block_0: ssa_3, block_4: ssa_57 vec1 32 ssa_44 = phi block_0: ssa_3, block_4: ssa_57 vec1 32 ssa_45 = uge32 ssa_44, ssa_4 vec1 32 ssa_45 = uge32 ssa_44, ssa_4 /* succs: block_2 block_3 */ /* succs: block_2 block_3 */ if ssa_45 { if ssa_45 { block block_2: block block_2: /* preds: block_1 */ /* preds: block_1 */ break break /* succs: block_5 */ /* succs: block_5 */ } else { } else { block block_3: block block_3: /* preds: block_1 */ /* preds: block_1 */ /* succs: block_4 */ /* succs: block_4 */ } } block block_4: block block_4: /* preds: block_3 */ /* preds: block_3 */ vec1 32 ssa_46 = umin ssa_26, ssa_44 vec1 32 ssa_46 = umin ssa_26, ssa_44 vec1 32 ssa_47 = ineg ssa_46 vec1 32 ssa_47 = ineg ssa_46 vec1 32 ssa_48 = iadd ssa_26, ssa_47 vec1 32 ssa_48 = iadd ssa_26, ssa_47 vec1 32 ssa_49 = ishl ssa_2, ssa_44 vec1 32 ssa_49 = ishl ssa_2, ssa_44 vec1 32 ssa_50 = uge32 ssa_44, ssa_5 vec1 32 ssa_50 = uge32 ssa_44, ssa_5 vec1 32 ssa_51 = b32csel ssa_50, ssa_3, ssa_49 vec1 32 ssa_51 = b32csel ssa_50, ssa_3, ssa_49 vec1 32 ssa_52 = iand ssa_51, ssa_30 vec1 32 ssa_52 = iand ssa_51, ssa_30 vec1 32 ssa_53 = bit_count ssa_52 vec1 32 ssa_53 = bit_count ssa_52 vec1 32 ssa_54 = iand ssa_43, ssa_1 vec1 32 ssa_54 = iand ssa_43, ssa_1 vec1 32 ssa_55 = ine32 ssa_53, ssa_48 vec1 32 ssa_55 = ine32 ssa_53, ssa_48 vec1 32 ssa_56 = b32csel ssa_55, ssa_54, ssa_43 vec1 32 ssa_56 = b32csel ssa_55, ssa_54, ssa_43 vec1 32 ssa_57 = iadd ssa_44, ssa_0 vec1 32 ssa_57 = iadd ssa_44, ssa_0 /* succs: block_1 */ /* succs: block_1 */ } } block block_5: block block_5: /* preds: block_2 */ /* preds: block_2 */ vec1 32 ssa_58 = ishl ssa_25, ssa_34 vec1 32 ssa_58 = ishl ssa_25, ssa_34 intrinsic store_ssbo (ssa_43, ssa_34, ssa_58) (1, 0, 4, 0) /* wrmask=x */ /* access=0 */ /* align_mul=4 */ /* intrinsic store_ssbo (ssa_43, ssa_34, ssa_58) (1, 0, 4, 0) /* wrmask=x */ /* access=0 */ /* align_mul=4 */ /* /* succs: block_6 */ /* succs: block_6 */ block block_6: block block_6: } } NIR (final form) for compute shader: NIR (final form) for compute shader: shader: MESA_SHADER_COMPUTE shader: MESA_SHADER_COMPUTE local-size: 1, 1, 32 local-size: 1, 1, 32 shared-size: 0 shared-size: 0 inputs: 0 inputs: 0 outputs: 0 outputs: 0 uniforms: 36 uniforms: 36 shared: 0 shared: 0 decl_var ssbo INTERP_MODE_NONE restrict block @0 (~0, 0, 0) decl_var ssbo INTERP_MODE_NONE restrict block @0 (~0, 0, 0) decl_function main (0 params) decl_function main (0 params) impl main { impl main { decl_reg vec1 32 r3 decl_reg vec1 32 r3 decl_reg vec1 32 r4 decl_reg vec1 32 r4 block block_0: block block_0: /* preds: */ /* preds: */ vec1 32 ssa_0 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_0 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_1 = load_const (0xfffffff7 /* -nan */) vec1 32 ssa_1 = load_const (0xfffffff7 /* -nan */) vec1 32 ssa_2 = load_const (0xffffffff /* -nan */) vec1 32 ssa_2 = load_const (0xffffffff /* -nan */) vec1 32 ssa_3 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_4 = load_const (0x00000080 /* 0.000000 */) vec1 32 ssa_4 = load_const (0x00000080 /* 0.000000 */) vec1 32 ssa_5 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_5 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_6 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_6 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_7 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_7 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_8 = load_const (0xffffffff /* -nan */) vec1 32 ssa_8 = load_const (0xffffffff /* -nan */) vec3 32 ssa_9 = intrinsic load_num_work_groups () () vec3 32 ssa_9 = intrinsic load_num_work_groups () () vec3 32 ssa_10 = intrinsic load_work_group_id () () vec3 32 ssa_10 = intrinsic load_work_group_id () () vec3 32 ssa_11 = intrinsic load_uniform (ssa_3) (24, 12, 0) /* base=24 */ /* range=12 */ /* dest_type=invalid vec3 32 ssa_11 = intrinsic load_uniform (ssa_3) (24, 12, 0) /* base=24 */ /* range=12 */ /* dest_type=invalid vec1 32 ssa_12 = iadd ssa_10.x, ssa_11.x vec1 32 ssa_12 = iadd ssa_10.x, ssa_11.x vec1 32 ssa_13 = iadd ssa_10.y, ssa_11.y vec1 32 ssa_13 = iadd ssa_10.y, ssa_11.y vec1 32 ssa_14 = iadd ssa_10.z, ssa_11.z vec1 32 ssa_14 = iadd ssa_10.z, ssa_11.z vec1 32 ssa_15 = intrinsic load_subgroup_id () () vec1 32 ssa_15 = intrinsic load_subgroup_id () () vec1 32 ssa_16 = ishl ssa_15, ssa_7 vec1 32 ssa_16 = ishl ssa_15, ssa_7 vec1 32 ssa_17 = intrinsic load_subgroup_invocation () () vec1 32 ssa_17 = intrinsic load_subgroup_invocation () () vec1 32 ssa_18 = iadd ssa_17, ssa_16 vec1 32 ssa_18 = iadd ssa_17, ssa_16 vec1 32 ssa_19 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_19 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_20 = ishl ssa_14, ssa_19 vec1 32 ssa_20 = ishl ssa_14, ssa_19 vec1 32 ssa_21 = iadd ssa_20, ssa_18 vec1 32 ssa_21 = iadd ssa_20, ssa_18 vec1 32 ssa_22 = imul ssa_9.y, ssa_21 vec1 32 ssa_22 = imul ssa_9.y, ssa_21 vec1 32 ssa_23 = iadd ssa_22, ssa_13 vec1 32 ssa_23 = iadd ssa_22, ssa_13 vec1 32 ssa_24 = imul ssa_9.x, ssa_23 vec1 32 ssa_24 = imul ssa_9.x, ssa_23 vec1 32 ssa_25 = iadd ssa_24, ssa_12 vec1 32 ssa_25 = iadd ssa_24, ssa_12 vec1 32 ssa_26 = iadd ssa_17, ssa_0 vec1 32 ssa_26 = iadd ssa_17, ssa_0 vec1 32 ssa_27 = load_const (0x0000001f /* 0.000000 */) vec1 32 ssa_27 = load_const (0x0000001f /* 0.000000 */) vec1 32 ssa_28 = ineg ssa_17 vec1 32 ssa_28 = ineg ssa_17 vec1 32 ssa_29 = iadd ssa_27, ssa_28 vec1 32 ssa_29 = iadd ssa_27, ssa_28 vec1 32 ssa_30 = ushr ssa_2, ssa_29 vec1 32 ssa_30 = ushr ssa_2, ssa_29 vec1 32 ssa_31 = bit_count ssa_30 vec1 32 ssa_31 = bit_count ssa_30 vec1 32 ssa_32 = ieq32 ssa_26, ssa_31 vec1 32 ssa_32 = ieq32 ssa_26, ssa_31 vec1 32 ssa_33 = b2i32 ssa_32 vec1 32 ssa_33 = b2i32 ssa_32 vec1 32 ssa_34 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_34 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_35 = ior ssa_33, ssa_34 vec1 32 ssa_35 = ior ssa_33, ssa_34 vec1 32 ssa_36 = intrinsic ballot (ssa_8) () vec1 32 ssa_36 = intrinsic ballot (ssa_8) () vec1 32 ssa_37 = iand ssa_36, ssa_30 vec1 32 ssa_37 = iand ssa_36, ssa_30 vec1 32 ssa_38 = bit_count ssa_37 vec1 32 ssa_38 = bit_count ssa_37 vec1 32 ssa_39 = ult32 ssa_3, ssa_38 vec1 32 ssa_39 = ult32 ssa_3, ssa_38 vec1 32 ssa_40 = b32csel ssa_39, ssa_7, ssa_3 vec1 32 ssa_40 = b32csel ssa_39, ssa_7, ssa_3 vec1 32 ssa_41 = ior ssa_35, ssa_40 vec1 32 ssa_41 = ior ssa_35, ssa_40 r3 = ior ssa_41, ssa_6 r3 = ior ssa_41, ssa_6 r4 = mov ssa_3 r4 = mov ssa_3 /* succs: block_1 */ /* succs: block_1 */ loop { loop { block block_1: block block_1: /* preds: block_0 block_4 */ /* preds: block_0 block_4 */ vec1 32 ssa_45 = uge32 r4, ssa_4 vec1 32 ssa_45 = uge32 r4, ssa_4 /* succs: block_2 block_3 */ /* succs: block_2 block_3 */ if ssa_45 { if ssa_45 { block block_2: block block_2: /* preds: block_1 */ /* preds: block_1 */ break break /* succs: block_5 */ /* succs: block_5 */ } else { } else { block block_3: block block_3: /* preds: block_1 */ /* preds: block_1 */ /* succs: block_4 */ /* succs: block_4 */ } } block block_4: block block_4: /* preds: block_3 */ /* preds: block_3 */ vec1 32 ssa_46 = umin ssa_26, r4 vec1 32 ssa_46 = umin ssa_26, r4 vec1 32 ssa_47 = ineg ssa_46 vec1 32 ssa_47 = ineg ssa_46 vec1 32 ssa_48 = iadd ssa_26, ssa_47 vec1 32 ssa_48 = iadd ssa_26, ssa_47 vec1 32 ssa_49 = ishl ssa_2, r4 vec1 32 ssa_49 = ishl ssa_2, r4 vec1 32 ssa_50 = uge32 r4, ssa_5 vec1 32 ssa_50 = uge32 r4, ssa_5 vec1 32 ssa_51 = b32csel ssa_50, ssa_3, ssa_49 vec1 32 ssa_51 = b32csel ssa_50, ssa_3, ssa_49 vec1 32 ssa_52 = iand ssa_51, ssa_30 vec1 32 ssa_52 = iand ssa_51, ssa_30 vec1 32 ssa_53 = bit_count ssa_52 vec1 32 ssa_53 = bit_count ssa_52 vec1 32 ssa_54 = iand r3, ssa_1 vec1 32 ssa_54 = iand r3, ssa_1 vec1 32 ssa_55 = ine32 ssa_53, ssa_48 vec1 32 ssa_55 = ine32 ssa_53, ssa_48 r3 = b32csel ssa_55, ssa_54, r3 r3 = b32csel ssa_55, ssa_54, r3 r4 = iadd r4, ssa_0 r4 = iadd r4, ssa_0 /* succs: block_1 */ /* succs: block_1 */ } } block block_5: block block_5: /* preds: block_2 */ /* preds: block_2 */ vec1 32 ssa_58 = ishl ssa_25, ssa_34 vec1 32 ssa_58 = ishl ssa_25, ssa_34 intrinsic store_ssbo (r3, ssa_34, ssa_58) (1, 0, 4, 0) /* wrmask=x */ /* access=0 */ /* align_mul=4 */ /* ali intrinsic store_ssbo (r3, ssa_34, ssa_58) (1, 0, 4, 0) /* wrmask=x */ /* access=0 */ /* align_mul=4 */ /* ali /* succs: block_6 */ /* succs: block_6 */ block block_6: block block_6: } } Native code for unnamed compute shader (null) (sha1 1b13225cb26be68593265c352ac49dee0b53fe73) | Native code for unnamed compute shader (null) (sha1 49554d8dc0ca499c219db9739eb3201947e38bff) SIMD16 shader: 63 instructions. 1 loops. 1710 cycles. 0:0 spills:fills, 3 sends, scheduled with mode top-down. Promot | SIMD16 shader: 62 instructions. 1 loops. 1626 cycles. 0:0 spills:fills, 3 sends, scheduled with mode top-down. Promot START B0 (360 cycles) | START B0 (356 cycles) mov(8) g3<1>UW 0x76543210V { align1 WE_all 1Q }; mov(8) g3<1>UW 0x76543210V { align1 WE_all 1Q }; mov(16) g75<1>UD g0.1<0,1,0>UD { align1 1H compacted }; | mov(16) g73<1>UD g0.1<0,1,0>UD { align1 1H compacted }; mov(16) g77<1>UD g0.6<0,1,0>UD { align1 1H }; | mov(16) g75<1>UD g0.6<0,1,0>UD { align1 1H }; mov(16) g4<1>UD g0.7<0,1,0>UD { align1 1H }; mov(16) g4<1>UD g0.7<0,1,0>UD { align1 1H }; mov(16) g6<1>UD 0xffffffffUD { align1 1H compacted }; mov(16) g6<1>UD 0xffffffffUD { align1 1H compacted }; mov(16) g8<1>UD 0xffffffffUD { align1 1H compacted }; | mov(16) g77<1>UD 0x00000000UD { align1 1H compacted }; mov(16) g79<1>UD 0x00000000UD { align1 1H compacted }; < add(8) g3.8<1>UW g3<8,8,1>UW 0x0008UW { align1 WE_all 1Q }; add(8) g3.8<1>UW g3<8,8,1>UW 0x0008UW { align1 WE_all 1Q }; send(16) g10<1>UW g79<0,1,0>UD 0x04605800 | send(16) g8<1>UW g77<0,1,0>UD 0x04605800 dp data 1 MsgDesc: ( untyped surface read, Surface = 0, SIMD16, Mask = 0x8) mlen 2 rlen 6 dp data 1 MsgDesc: ( untyped surface read, Surface = 0, SIMD16, Mask = 0x8) mlen 2 rlen 6 add(16) g16<1>D g75<8,8,1>D g1.6<0,1,0>D { align1 1H compacted }; | add(16) g14<1>D g73<8,8,1>D g1.6<0,1,0>D { align1 1H compacted }; add(16) g18<1>D g77<8,8,1>D g1.7<0,1,0>D { align1 1H compacted }; | add(16) g16<1>D g75<8,8,1>D g1.7<0,1,0>D { align1 1H compacted }; add(16) g20<1>D g4<8,8,1>D g2<0,1,0>D { align1 1H compacted }; | add(16) g18<1>D g4<8,8,1>D g2<0,1,0>D { align1 1H compacted }; shl(16) g22<1>D g2.1<0,1,0>D 0x00000004UD { align1 1H }; | shl(16) g20<1>D g2.1<0,1,0>D 0x00000004UD { align1 1H }; mov(16) g24<1>D g3<8,8,1>UW { align1 1H }; | mov(16) g22<1>D g3<8,8,1>UW { align1 1H }; shl(16) g28<1>D g20<8,8,1>D 0x00000005UD { align1 1H }; | mov(1) g1.1<1>D 1D { align1 WE_all 1N }; add(16) g26<1>D g24<8,8,1>D g22<8,8,1>D { align1 1H compacted }; | shl(16) g26<1>D g18<8,8,1>D 0x00000005UD { align1 1H }; add(16) g40<1>D g24<8,8,1>D 1D { align1 1H compacted }; | add(16) g24<1>D g22<8,8,1>D g20<8,8,1>D { align1 1H compacted }; add(16) g42<1>D -g24<8,8,1>D 31D { align1 1H compacted }; | add(16) g38<1>D g22<8,8,1>D 1D { align1 1H compacted }; mov(1) g4<2>UW 0x00000000UD { align1 WE_all 1N }; | add(16) g40<1>D -g22<8,8,1>D 31D { align1 1H compacted }; add(16) g30<1>D g28<8,8,1>D g26<8,8,1>D { align1 1H compacted }; | mov(1) g5<2>UW 0x00000000UD { align1 WE_all 1N }; shr(16) g44<1>UD g6<8,8,1>UD g42<8,8,1>UD { align1 1H compacted }; | add(16) g28<1>D g26<8,8,1>D g24<8,8,1>D { align1 1H compacted }; cbit(16) g46<1>UD g44<8,8,1>UD { align1 1H compacted }; | shr(16) g42<1>D -g1.1<0,1,0>D g40<8,8,1>D { align1 1H compacted }; cmp.z.f0.0(16) g48<1>D g40<8,8,1>D g46<8,8,1>D { align1 1H compacted }; | cbit(16) g44<1>UD g42<8,8,1>UD { align1 1H compacted }; mov(16) g50<1>D -g48<8,8,1>D { align1 1H compacted }; | cmp.z.f0.0(16) g46<1>D g38<8,8,1>D g44<8,8,1>D { align1 1H compacted }; or(16) g52<1>UD g50<8,8,1>UD 0x00000002UD { align1 1H compacted }; | mov(16) g48<1>D -g46<8,8,1>D { align1 1H compacted }; mul(16) g32<1>D g12<8,8,1>D g30<16,8,2>UW { align1 1H }; | or(16) g50<1>UD g48<8,8,1>UD 0x00000002UD { align1 1H compacted }; mul(16) g1<1>D g12<8,8,1>D g30.1<16,8,2>UW { align1 1H }; | mul(16) g30<1>D g10<8,8,1>D g28<16,8,2>UW { align1 1H }; add(16) g32.1<2>UW g32.1<16,8,2>UW g1<16,8,2>UW { align1 1H }; | mul(16) g2<1>D g10<8,8,1>D g28.1<16,8,2>UW { align1 1H }; add(16) g34<1>D g32<8,8,1>D g18<8,8,1>D { align1 1H compacted }; | add(16) g30.1<2>UW g30.1<16,8,2>UW g2<16,8,2>UW { align1 1H }; mul(16) g36<1>D g10<8,8,1>D g34<16,8,2>UW { align1 1H }; | add(16) g32<1>D g30<8,8,1>D g16<8,8,1>D { align1 1H compacted }; mul(16) g2<1>D g10<8,8,1>D g34.1<16,8,2>UW { align1 1H }; | mul(16) g34<1>D g8<8,8,1>D g32<16,8,2>UW { align1 1H }; add(16) g36.1<2>UW g36.1<16,8,2>UW g2<16,8,2>UW { align1 1H }; | mul(16) g3<1>D g8<8,8,1>D g32.1<16,8,2>UW { align1 1H }; add(16) g38<1>D g36<8,8,1>D g16<8,8,1>D { align1 1H compacted }; | add(16) g34.1<2>UW g34.1<16,8,2>UW g3<16,8,2>UW { align1 1H }; mov(1) f0<1>UW g4<0,1,0>UW { align1 WE_all 1N }; | add(16) g36<1>D g34<8,8,1>D g14<8,8,1>D { align1 1H compacted }; cmp.nz.f0.0(16) null<1>UD g8<8,8,1>UD 0x00000000UD { align1 1H compacted }; | mov(1) f0<1>UW g5<0,1,0>UW { align1 WE_all 1N }; mov(16) g54<1>UD f0<0,1,0>UW { align1 1H }; | cmp.nz.f0.0(16) null<1>UD g6<8,8,1>UD 0x00000000UD { align1 1H compacted }; > mov(16) g52<1>UD f0<0,1,0>UW { align1 1H }; mov(1) g1<1>UD 0x00000000UD { align1 WE_all 1N compacted }; mov(1) g1<1>UD 0x00000000UD { align1 WE_all 1N compacted }; mov(16) g5<1>UD 0x00000000UD { align1 1H compacted }; mov(16) g5<1>UD 0x00000000UD { align1 1H compacted }; and(16) g56<1>UD g54<8,8,1>UD g44<8,8,1>UD { align1 1H compacted }; | and(16) g54<1>UD g52<8,8,1>UD g42<8,8,1>UD { align1 1H compacted }; cbit(16) g58<1>UD g56<8,8,1>UD { align1 1H compacted }; | cbit(16) g56<1>UD g54<8,8,1>UD { align1 1H compacted }; cmp.g.f0.0(16) null<1>UD g58<8,8,1>UD 0x00000000UD { align1 1H compacted }; | cmp.g.f0.0(16) null<1>UD g56<8,8,1>UD 0x00000000UD { align1 1H compacted }; (-f0.0) sel(16) g59<1>UD g1<0,1,0>UD 0x00000004UD { align1 1H }; | (-f0.0) sel(16) g57<1>UD g1<0,1,0>UD 0x00000004UD { align1 1H }; or(16) g61<1>UD g52<8,8,1>UD g59<8,8,1>UD { align1 1H compacted }; | or(16) g59<1>UD g50<8,8,1>UD g57<8,8,1>UD { align1 1H compacted }; or(16) g82<1>UD g61<8,8,1>UD 0x00000008UD { align1 1H compacted }; | or(16) g80<1>UD g59<8,8,1>UD 0x00000008UD { align1 1H compacted }; END B0 ->B1 END B0 ->B1 START B2 <-B1 <-B3 (260 cycles) START B2 <-B1 <-B3 (260 cycles) LABEL1: LABEL1: cmp.ge.f0.0(16) null<1>UD g5<8,8,1>UD 0x00000080UD { align1 1H compacted }; cmp.ge.f0.0(16) null<1>UD g5<8,8,1>UD 0x00000080UD { align1 1H compacted }; END B1 ->B2 ->B4 END B1 ->B2 ->B4 (+f0.0) break(16) JIP: LABEL0 UIP: LABEL0 { align1 1H }; (+f0.0) break(16) JIP: LABEL0 UIP: LABEL0 { align1 1H }; END B2 ->B1 ->B4 ->B3 END B2 ->B1 ->B4 ->B3 START B3 <-B2 (1060 cycles) | START B3 <-B2 (980 cycles) sel.l(16) g62<1>UD g40<8,8,1>UD g5<8,8,1>UD { align1 1H compacted }; | sel.l(16) g60<1>UD g38<8,8,1>UD g5<8,8,1>UD { align1 1H compacted }; mov(1) g1.1<1>D 1D { align1 WE_all 1N }; | shl(16) g64<1>D -g1.1<0,1,0>D g5<8,8,1>UD { align1 1H }; cmp.ge.f0.0(16) null<1>UD g5<8,8,1>UD 0x00000020UD { align1 1H compacted }; cmp.ge.f0.0(16) null<1>UD g5<8,8,1>UD 0x00000020UD { align1 1H compacted }; and(16) g74<1>UD g82<8,8,1>UD 0xfffffff7UD { align1 1H compacted }; | and(16) g72<1>UD g80<8,8,1>UD 0xfffffff7UD { align1 1H compacted }; add(16) g64<1>D g40<8,8,1>D -g62<8,8,1>D { align1 1H compacted }; < shl(16) g66<1>D -g1.1<0,1,0>D g5<8,8,1>UD { align1 1H }; < add(16) g5<1>D g5<8,8,1>D 1D { align1 1H compacted }; add(16) g5<1>D g5<8,8,1>D 1D { align1 1H compacted }; (-f0.0) sel(16) g68<1>UD g66<8,8,1>UD 0x00000000UD { align1 1H }; | add(16) g62<1>D g38<8,8,1>D -g60<8,8,1>D { align1 1H compacted }; and(16) g70<1>UD g68<8,8,1>UD g44<8,8,1>UD { align1 1H compacted }; | (-f0.0) sel(16) g66<1>UD g64<8,8,1>UD 0x00000000UD { align1 1H }; cbit(16) g72<1>UD g70<8,8,1>UD { align1 1H compacted }; | and(16) g68<1>UD g66<8,8,1>UD g42<8,8,1>UD { align1 1H compacted }; cmp.nz.f0.0(16) null<1>D g72<8,8,1>D g64<8,8,1>D { align1 1H compacted }; | cbit(16) g70<1>UD g68<8,8,1>UD { align1 1H compacted }; (+f0.0) sel(16) g82<1>UD g74<8,8,1>UD g82<8,8,1>UD { align1 1H compacted }; | cmp.nz.f0.0(16) null<1>D g70<8,8,1>D g62<8,8,1>D { align1 1H compacted }; > (+f0.0) sel(16) g80<1>UD g72<8,8,1>UD g80<8,8,1>UD { align1 1H compacted }; LABEL0: LABEL0: while(16) JIP: LABEL1 { align1 1H }; while(16) JIP: LABEL1 { align1 1H }; END B3 ->B2 END B3 ->B2 START B4 <-B1 <-B2 (30 cycles) START B4 <-B1 <-B2 (30 cycles) shl(16) g80<1>D g38<8,8,1>D 0x00000002UD { align1 1H }; | shl(16) g78<1>D g36<8,8,1>D 0x00000002UD { align1 1H }; sends(16) nullUD g80UD g82UD 0x04025e02 0x00000080 | sends(16) nullUD g78UD g80UD 0x04025e02 0x00000080 dp data 1 MsgDesc: ( DC untyped surface write, Surface = 2, SIMD16, Mask = 0xe) mlen 2 ex dp data 1 MsgDesc: ( DC untyped surface write, Surface = 2, SIMD16, Mask = 0xe) mlen 2 ex mov(8) g126<1>UD g0<8,8,1>UD { align1 WE_all 1Q compacted }; mov(8) g126<1>UD g0<8,8,1>UD { align1 WE_all 1Q compacted }; send(16) null<1>UW g126<8,8,1>UW 0x82000000 send(16) null<1>UW g126<8,8,1>UW 0x82000000 thread_spawner MsgDesc: mlen 1 rlen 0 { align1 WE_all 1H EOT }; thread_spawner MsgDesc: mlen 1 rlen 0 { align1 WE_all 1H EOT }; END B4 END B4 NIR (from SPIR-V) for MESA_SHADER_COMPUTE shader: NIR (from SPIR-V) for MESA_SHADER_COMPUTE shader: shader: MESA_SHADER_COMPUTE shader: MESA_SHADER_COMPUTE local-size: 32, 4, 1 local-size: 32, 4, 1 shared-size: 0 shared-size: 0 inputs: 0 inputs: 0 outputs: 0 outputs: 0 uniforms: 0 uniforms: 0 shared: 0 shared: 0 decl_var system INTERP_MODE_NONE uvec3 @0 decl_var system INTERP_MODE_NONE uvec3 @0 decl_var system INTERP_MODE_NONE uvec3 @1 decl_var system INTERP_MODE_NONE uvec3 @1 decl_var system INTERP_MODE_NONE uint @2 decl_var system INTERP_MODE_NONE uint @2 decl_var ssbo INTERP_MODE_NONE restrict block @3 (~0, 0, 0) decl_var ssbo INTERP_MODE_NONE restrict block @3 (~0, 0, 0) decl_function main (0 params) decl_function main (0 params) impl main { impl main { decl_var INTERP_MODE_NONE uvec3 @4 decl_var INTERP_MODE_NONE uvec3 @4 decl_var INTERP_MODE_NONE uint @5 decl_var INTERP_MODE_NONE uint @5 decl_var INTERP_MODE_NONE uvec4 @6 decl_var INTERP_MODE_NONE uvec4 @6 decl_var INTERP_MODE_NONE uvec4 @7 decl_var INTERP_MODE_NONE uvec4 @7 decl_var INTERP_MODE_NONE uint @8 decl_var INTERP_MODE_NONE uint @8 decl_var INTERP_MODE_NONE uint @9 decl_var INTERP_MODE_NONE uint @9 decl_var INTERP_MODE_NONE uint @10 decl_var INTERP_MODE_NONE uint @10 decl_var INTERP_MODE_NONE uint @11 decl_var INTERP_MODE_NONE uint @11 decl_var INTERP_MODE_NONE uvec4 @12 decl_var INTERP_MODE_NONE uvec4 @12 decl_var INTERP_MODE_NONE int @13 decl_var INTERP_MODE_NONE int @13 decl_var INTERP_MODE_NONE int @14 decl_var INTERP_MODE_NONE int @14 decl_var INTERP_MODE_NONE uint @15 decl_var INTERP_MODE_NONE uint @15 decl_var INTERP_MODE_NONE int @16 decl_var INTERP_MODE_NONE int @16 decl_var INTERP_MODE_NONE uint @17 decl_var INTERP_MODE_NONE uint @17 decl_var INTERP_MODE_NONE int @18 decl_var INTERP_MODE_NONE int @18 decl_var INTERP_MODE_NONE uint @19 decl_var INTERP_MODE_NONE uint @19 decl_var INTERP_MODE_NONE uint @20 decl_var INTERP_MODE_NONE uint @20 decl_var INTERP_MODE_NONE bool cont decl_var INTERP_MODE_NONE bool cont block block_0: block block_0: /* preds: */ /* preds: */ vec1 32 ssa_217 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_217 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_208 = load_const (0xfffffff7 /* -nan */) vec1 32 ssa_208 = load_const (0xfffffff7 /* -nan */) vec1 32 ssa_189 = load_const (0xffffffff /* -nan */) vec1 32 ssa_189 = load_const (0xffffffff /* -nan */) vec1 32 ssa_184 = load_const (0x00000060 /* 0.000000 */) vec1 32 ssa_184 = load_const (0x00000060 /* 0.000000 */) vec1 32 ssa_180 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_180 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_178 = load_const (0x00000060 /* 0.000000 */) vec1 32 ssa_178 = load_const (0x00000060 /* 0.000000 */) vec1 32 ssa_174 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_174 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_172 = load_const (0x00000080 /* 0.000000 */) vec1 32 ssa_172 = load_const (0x00000080 /* 0.000000 */) vec1 32 ssa_164 = load_const (0xffffffff /* -nan */) vec1 32 ssa_164 = load_const (0xffffffff /* -nan */) vec1 32 ssa_159 = load_const (0x00000040 /* 0.000000 */) vec1 32 ssa_159 = load_const (0x00000040 /* 0.000000 */) vec1 32 ssa_155 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_155 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_153 = load_const (0x00000040 /* 0.000000 */) vec1 32 ssa_153 = load_const (0x00000040 /* 0.000000 */) vec1 32 ssa_149 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_149 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_147 = load_const (0x00000060 /* 0.000000 */) vec1 32 ssa_147 = load_const (0x00000060 /* 0.000000 */) vec1 32 ssa_139 = load_const (0xffffffff /* -nan */) vec1 32 ssa_139 = load_const (0xffffffff /* -nan */) vec1 32 ssa_134 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_134 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_130 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_130 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_128 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_128 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_124 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_124 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_122 = load_const (0x00000040 /* 0.000000 */) vec1 32 ssa_122 = load_const (0x00000040 /* 0.000000 */) vec1 32 ssa_114 = load_const (0xffffffff /* -nan */) vec1 32 ssa_114 = load_const (0xffffffff /* -nan */) vec1 32 ssa_110 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_110 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_108 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_108 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_95 = load_const (0x00000080 /* 0.000000 */) vec1 32 ssa_95 = load_const (0x00000080 /* 0.000000 */) vec1 32 ssa_91 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_91 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_88 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_88 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_79 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_79 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_78 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_78 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_76 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_76 = load_const (0x00000000 /* 0.000000 */) vec1 1 ssa_73 = load_const (true) vec1 1 ssa_73 = load_const (true) vec1 32 ssa_66 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_66 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_65 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_65 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_63 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_63 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_53 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_53 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_52 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_52 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_43 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_43 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_39 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_39 = load_const (0x00000000 /* 0.000000 */) vec4 32 ssa_37 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, vec4 32 ssa_37 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, vec4 32 ssa_35 = load_const (0xffffffff /* -nan */, 0xffffffff /* -nan */, 0xffffffff /* -nan */, 0xffffffff vec4 32 ssa_35 = load_const (0xffffffff /* -nan */, 0xffffffff /* -nan */, 0xffffffff /* -nan */, 0xffffffff vec3 32 ssa_2 = load_const (0x00000020 /* 0.000000 */, 0x00000004 /* 0.000000 */, 0x00000001 /* 0.000000 */) vec3 32 ssa_2 = load_const (0x00000020 /* 0.000000 */, 0x00000004 /* 0.000000 */, 0x00000001 /* 0.000000 */) vec1 32 ssa_0 = deref_var &@0 (system uvec3) vec1 32 ssa_0 = deref_var &@0 (system uvec3) vec3 32 ssa_1 = intrinsic load_deref (ssa_0) (0) /* access=0 */ vec3 32 ssa_1 = intrinsic load_deref (ssa_0) (0) /* access=0 */ vec3 32 ssa_3 = imul ssa_1, ssa_2 vec3 32 ssa_3 = imul ssa_1, ssa_2 vec1 32 ssa_4 = deref_var &@4 (function_temp uvec3) vec1 32 ssa_4 = deref_var &@4 (function_temp uvec3) intrinsic store_deref (ssa_4, ssa_3) (7, 0) /* wrmask=xyz */ /* access=0 */ intrinsic store_deref (ssa_4, ssa_3) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_5 = deref_var &@4 (function_temp uvec3) vec1 32 ssa_5 = deref_var &@4 (function_temp uvec3) vec3 32 ssa_8 = intrinsic load_deref (ssa_5) (0) /* access=0 */ vec3 32 ssa_8 = intrinsic load_deref (ssa_5) (0) /* access=0 */ vec1 32 ssa_9 = mov ssa_8.x vec1 32 ssa_9 = mov ssa_8.x vec1 32 ssa_10 = deref_var &@4 (function_temp uvec3) vec1 32 ssa_10 = deref_var &@4 (function_temp uvec3) vec3 32 ssa_13 = intrinsic load_deref (ssa_10) (0) /* access=0 */ vec3 32 ssa_13 = intrinsic load_deref (ssa_10) (0) /* access=0 */ vec1 32 ssa_14 = mov ssa_13.y vec1 32 ssa_14 = mov ssa_13.y vec1 32 ssa_15 = deref_var &@1 (system uvec3) vec1 32 ssa_15 = deref_var &@1 (system uvec3) vec3 32 ssa_18 = intrinsic load_deref (ssa_15) (0) /* access=0 */ vec3 32 ssa_18 = intrinsic load_deref (ssa_15) (0) /* access=0 */ vec1 32 ssa_19 = mov ssa_18.z vec1 32 ssa_19 = mov ssa_18.z vec1 32 ssa_20 = imul ssa_14, ssa_19 vec1 32 ssa_20 = imul ssa_14, ssa_19 vec1 32 ssa_21 = deref_var &@1 (system uvec3) vec1 32 ssa_21 = deref_var &@1 (system uvec3) vec3 32 ssa_24 = intrinsic load_deref (ssa_21) (0) /* access=0 */ vec3 32 ssa_24 = intrinsic load_deref (ssa_21) (0) /* access=0 */ vec1 32 ssa_25 = mov ssa_24.y vec1 32 ssa_25 = mov ssa_24.y vec1 32 ssa_26 = iadd ssa_20, ssa_25 vec1 32 ssa_26 = iadd ssa_20, ssa_25 vec1 32 ssa_27 = imul ssa_9, ssa_26 vec1 32 ssa_27 = imul ssa_9, ssa_26 vec1 32 ssa_28 = deref_var &@1 (system uvec3) vec1 32 ssa_28 = deref_var &@1 (system uvec3) vec3 32 ssa_31 = intrinsic load_deref (ssa_28) (0) /* access=0 */ vec3 32 ssa_31 = intrinsic load_deref (ssa_28) (0) /* access=0 */ vec1 32 ssa_32 = mov ssa_31.x vec1 32 ssa_32 = mov ssa_31.x vec1 32 ssa_33 = iadd ssa_27, ssa_32 vec1 32 ssa_33 = iadd ssa_27, ssa_32 vec1 32 ssa_34 = deref_var &@5 (function_temp uint) vec1 32 ssa_34 = deref_var &@5 (function_temp uint) intrinsic store_deref (ssa_34, ssa_33) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_34, ssa_33) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_36 = deref_var &@6 (function_temp uvec4) vec1 32 ssa_36 = deref_var &@6 (function_temp uvec4) intrinsic store_deref (ssa_36, ssa_35) (15, 0) /* wrmask=xyzw */ /* access=0 */ intrinsic store_deref (ssa_36, ssa_35) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_38 = deref_var &@7 (function_temp uvec4) vec1 32 ssa_38 = deref_var &@7 (function_temp uvec4) intrinsic store_deref (ssa_38, ssa_37) (15, 0) /* wrmask=xyzw */ /* access=0 */ intrinsic store_deref (ssa_38, ssa_37) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_40 = deref_var &@8 (function_temp uint) vec1 32 ssa_40 = deref_var &@8 (function_temp uint) intrinsic store_deref (ssa_40, ssa_39) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_40, ssa_39) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_41 = deref_var &@2 (system uint) vec1 32 ssa_41 = deref_var &@2 (system uint) vec1 32 ssa_42 = intrinsic load_deref (ssa_41) (0) /* access=0 */ vec1 32 ssa_42 = intrinsic load_deref (ssa_41) (0) /* access=0 */ vec1 32 ssa_44 = iadd ssa_42, ssa_43 vec1 32 ssa_44 = iadd ssa_42, ssa_43 vec1 32 ssa_45 = deref_var &@9 (function_temp uint) vec1 32 ssa_45 = deref_var &@9 (function_temp uint) intrinsic store_deref (ssa_45, ssa_44) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_45, ssa_44) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_46 = deref_var &@9 (function_temp uint) vec1 32 ssa_46 = deref_var &@9 (function_temp uint) vec1 32 ssa_47 = intrinsic load_deref (ssa_46) (0) /* access=0 */ vec1 32 ssa_47 = intrinsic load_deref (ssa_46) (0) /* access=0 */ vec1 32 ssa_48 = deref_var &@6 (function_temp uvec4) vec1 32 ssa_48 = deref_var &@6 (function_temp uvec4) vec4 32 ssa_49 = intrinsic load_deref (ssa_48) (0) /* access=0 */ vec4 32 ssa_49 = intrinsic load_deref (ssa_48) (0) /* access=0 */ vec1 32 ssa_50 = intrinsic ballot_bit_count_inclusive (ssa_49) () vec1 32 ssa_50 = intrinsic ballot_bit_count_inclusive (ssa_49) () vec1 1 ssa_51 = ieq ssa_47, ssa_50 vec1 1 ssa_51 = ieq ssa_47, ssa_50 vec1 32 ssa_54 = bcsel ssa_51, ssa_53, ssa_52 vec1 32 ssa_54 = bcsel ssa_51, ssa_53, ssa_52 vec1 32 ssa_55 = mov ssa_54 vec1 32 ssa_55 = mov ssa_54 vec1 32 ssa_56 = deref_var &@8 (function_temp uint) vec1 32 ssa_56 = deref_var &@8 (function_temp uint) vec1 32 ssa_57 = intrinsic load_deref (ssa_56) (0) /* access=0 */ vec1 32 ssa_57 = intrinsic load_deref (ssa_56) (0) /* access=0 */ vec1 32 ssa_58 = ior ssa_57, ssa_55 vec1 32 ssa_58 = ior ssa_57, ssa_55 vec1 32 ssa_59 = deref_var &@8 (function_temp uint) vec1 32 ssa_59 = deref_var &@8 (function_temp uint) intrinsic store_deref (ssa_59, ssa_58) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_59, ssa_58) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_60 = deref_var &@7 (function_temp uvec4) vec1 32 ssa_60 = deref_var &@7 (function_temp uvec4) vec4 32 ssa_61 = intrinsic load_deref (ssa_60) (0) /* access=0 */ vec4 32 ssa_61 = intrinsic load_deref (ssa_60) (0) /* access=0 */ vec1 32 ssa_62 = intrinsic ballot_bit_count_inclusive (ssa_61) () vec1 32 ssa_62 = intrinsic ballot_bit_count_inclusive (ssa_61) () vec1 1 ssa_64 = ieq ssa_63, ssa_62 vec1 1 ssa_64 = ieq ssa_63, ssa_62 vec1 32 ssa_67 = bcsel ssa_64, ssa_66, ssa_65 vec1 32 ssa_67 = bcsel ssa_64, ssa_66, ssa_65 vec1 32 ssa_68 = mov ssa_67 vec1 32 ssa_68 = mov ssa_67 vec1 32 ssa_69 = deref_var &@8 (function_temp uint) vec1 32 ssa_69 = deref_var &@8 (function_temp uint) vec1 32 ssa_70 = intrinsic load_deref (ssa_69) (0) /* access=0 */ vec1 32 ssa_70 = intrinsic load_deref (ssa_69) (0) /* access=0 */ vec1 32 ssa_71 = ior ssa_70, ssa_68 vec1 32 ssa_71 = ior ssa_70, ssa_68 vec1 32 ssa_72 = deref_var &@8 (function_temp uint) vec1 32 ssa_72 = deref_var &@8 (function_temp uint) intrinsic store_deref (ssa_72, ssa_71) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_72, ssa_71) (1, 0) /* wrmask=x */ /* access=0 */ vec4 32 ssa_74 = intrinsic ballot (ssa_73) () vec4 32 ssa_74 = intrinsic ballot (ssa_73) () vec1 32 ssa_75 = intrinsic ballot_bit_count_inclusive (ssa_74) () vec1 32 ssa_75 = intrinsic ballot_bit_count_inclusive (ssa_74) () vec1 1 ssa_77 = ult ssa_76, ssa_75 vec1 1 ssa_77 = ult ssa_76, ssa_75 vec1 32 ssa_80 = bcsel ssa_77, ssa_79, ssa_78 vec1 32 ssa_80 = bcsel ssa_77, ssa_79, ssa_78 vec1 32 ssa_81 = mov ssa_80 vec1 32 ssa_81 = mov ssa_80 vec1 32 ssa_82 = deref_var &@8 (function_temp uint) vec1 32 ssa_82 = deref_var &@8 (function_temp uint) vec1 32 ssa_83 = intrinsic load_deref (ssa_82) (0) /* access=0 */ vec1 32 ssa_83 = intrinsic load_deref (ssa_82) (0) /* access=0 */ vec1 32 ssa_84 = ior ssa_83, ssa_81 vec1 32 ssa_84 = ior ssa_83, ssa_81 vec1 32 ssa_85 = deref_var &@8 (function_temp uint) vec1 32 ssa_85 = deref_var &@8 (function_temp uint) intrinsic store_deref (ssa_85, ssa_84) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_85, ssa_84) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_86 = deref_var &@8 (function_temp uint) vec1 32 ssa_86 = deref_var &@8 (function_temp uint) vec1 32 ssa_87 = intrinsic load_deref (ssa_86) (0) /* access=0 */ vec1 32 ssa_87 = intrinsic load_deref (ssa_86) (0) /* access=0 */ vec1 32 ssa_89 = ior ssa_87, ssa_88 vec1 32 ssa_89 = ior ssa_87, ssa_88 vec1 32 ssa_90 = deref_var &@8 (function_temp uint) vec1 32 ssa_90 = deref_var &@8 (function_temp uint) intrinsic store_deref (ssa_90, ssa_89) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_90, ssa_89) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_92 = deref_var &@10 (function_temp uint) vec1 32 ssa_92 = deref_var &@10 (function_temp uint) intrinsic store_deref (ssa_92, ssa_91) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_92, ssa_91) (1, 0) /* wrmask=x */ /* access=0 */ vec1 1 ssa_211 = load_const (false) vec1 1 ssa_211 = load_const (false) vec1 32 ssa_212 = deref_var &cont (function_temp bool) vec1 32 ssa_212 = deref_var &cont (function_temp bool) intrinsic store_deref (ssa_212, ssa_211) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_212, ssa_211) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_1 */ /* succs: block_1 */ loop { loop { block block_1: block block_1: /* preds: block_0 block_29 block_31 */ /* preds: block_0 block_29 block_31 */ vec1 32 ssa_213 = deref_var &cont (function_temp bool) vec1 32 ssa_213 = deref_var &cont (function_temp bool) vec1 1 ssa_214 = intrinsic load_deref (ssa_213) (0) /* access=0 */ vec1 1 ssa_214 = intrinsic load_deref (ssa_213) (0) /* access=0 */ /* succs: block_2 block_3 */ /* succs: block_2 block_3 */ if ssa_214 { if ssa_214 { block block_2: block block_2: /* preds: block_1 */ /* preds: block_1 */ vec1 32 ssa_215 = deref_var &@10 (function_temp uint) vec1 32 ssa_215 = deref_var &@10 (function_temp uint) vec1 32 ssa_216 = intrinsic load_deref (ssa_215) (0) /* access=0 */ vec1 32 ssa_216 = intrinsic load_deref (ssa_215) (0) /* access=0 */ vec1 32 ssa_218 = iadd ssa_216, ssa_217 vec1 32 ssa_218 = iadd ssa_216, ssa_217 vec1 32 ssa_219 = deref_var &@10 (function_temp uint) vec1 32 ssa_219 = deref_var &@10 (function_temp uint) intrinsic store_deref (ssa_219, ssa_218) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_219, ssa_218) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_4 */ /* succs: block_4 */ } else { } else { block block_3: block block_3: /* preds: block_1 */ /* preds: block_1 */ /* succs: block_4 */ /* succs: block_4 */ } } block block_4: block block_4: /* preds: block_2 block_3 */ /* preds: block_2 block_3 */ vec1 1 ssa_220 = load_const (true) vec1 1 ssa_220 = load_const (true) vec1 32 ssa_221 = deref_var &cont (function_temp bool) vec1 32 ssa_221 = deref_var &cont (function_temp bool) intrinsic store_deref (ssa_221, ssa_220) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_221, ssa_220) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_93 = deref_var &@10 (function_temp uint) vec1 32 ssa_93 = deref_var &@10 (function_temp uint) vec1 32 ssa_94 = intrinsic load_deref (ssa_93) (0) /* access=0 */ vec1 32 ssa_94 = intrinsic load_deref (ssa_93) (0) /* access=0 */ vec1 1 ssa_96 = ult ssa_94, ssa_95 vec1 1 ssa_96 = ult ssa_94, ssa_95 /* succs: block_5 block_30 */ /* succs: block_5 block_30 */ if ssa_96 { if ssa_96 { block block_5: block block_5: /* preds: block_4 */ /* preds: block_4 */ vec1 32 ssa_97 = deref_var &@9 (function_temp uint) vec1 32 ssa_97 = deref_var &@9 (function_temp uint) vec1 32 ssa_98 = intrinsic load_deref (ssa_97) (0) /* access=0 */ vec1 32 ssa_98 = intrinsic load_deref (ssa_97) (0) /* access=0 */ vec1 32 ssa_99 = deref_var &@9 (function_temp uint) vec1 32 ssa_99 = deref_var &@9 (function_temp uint) vec1 32 ssa_100 = intrinsic load_deref (ssa_99) (0) /* access=0 */ vec1 32 ssa_100 = intrinsic load_deref (ssa_99) (0) /* access=0 */ vec1 32 ssa_101 = deref_var &@10 (function_temp uint) vec1 32 ssa_101 = deref_var &@10 (function_temp uint) vec1 32 ssa_102 = intrinsic load_deref (ssa_101) (0) /* access=0 */ vec1 32 ssa_102 = intrinsic load_deref (ssa_101) (0) /* access=0 */ vec1 32 ssa_103 = umin ssa_100, ssa_102 vec1 32 ssa_103 = umin ssa_100, ssa_102 vec1 32 ssa_104 = isub ssa_98, ssa_103 vec1 32 ssa_104 = isub ssa_98, ssa_103 vec1 32 ssa_105 = deref_var &@11 (function_temp uint) vec1 32 ssa_105 = deref_var &@11 (function_temp uint) intrinsic store_deref (ssa_105, ssa_104) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_105, ssa_104) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_106 = deref_var &@10 (function_temp uint) vec1 32 ssa_106 = deref_var &@10 (function_temp uint) vec1 32 ssa_107 = intrinsic load_deref (ssa_106) (0) /* access=0 */ vec1 32 ssa_107 = intrinsic load_deref (ssa_106) (0) /* access=0 */ vec1 1 ssa_109 = uge ssa_107, ssa_108 vec1 1 ssa_109 = uge ssa_107, ssa_108 /* succs: block_6 block_7 */ /* succs: block_6 block_7 */ if ssa_109 { if ssa_109 { block block_6: block block_6: /* preds: block_5 */ /* preds: block_5 */ vec1 32 ssa_111 = deref_var &@13 (function_temp int) vec1 32 ssa_111 = deref_var &@13 (function_temp int) intrinsic store_deref (ssa_111, ssa_110) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_111, ssa_110) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_8 */ /* succs: block_8 */ } else { } else { block block_7: block block_7: /* preds: block_5 */ /* preds: block_5 */ vec1 32 ssa_112 = deref_var &@10 (function_temp uint) vec1 32 ssa_112 = deref_var &@10 (function_temp uint) vec1 32 ssa_113 = intrinsic load_deref (ssa_112) (0) /* access=0 */ vec1 32 ssa_113 = intrinsic load_deref (ssa_112) (0) /* access=0 */ vec1 32 ssa_115 = ishl ssa_114, ssa_113 vec1 32 ssa_115 = ishl ssa_114, ssa_113 vec1 32 ssa_116 = deref_var &@13 (function_temp int) vec1 32 ssa_116 = deref_var &@13 (function_temp int) intrinsic store_deref (ssa_116, ssa_115) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_116, ssa_115) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_8 */ /* succs: block_8 */ } } block block_8: block block_8: /* preds: block_6 block_7 */ /* preds: block_6 block_7 */ vec1 32 ssa_117 = deref_var &@13 (function_temp int) vec1 32 ssa_117 = deref_var &@13 (function_temp int) vec1 32 ssa_118 = intrinsic load_deref (ssa_117) (0) /* access=0 */ vec1 32 ssa_118 = intrinsic load_deref (ssa_117) (0) /* access=0 */ vec1 32 ssa_119 = mov ssa_118 vec1 32 ssa_119 = mov ssa_118 vec1 32 ssa_120 = deref_var &@10 (function_temp uint) vec1 32 ssa_120 = deref_var &@10 (function_temp uint) vec1 32 ssa_121 = intrinsic load_deref (ssa_120) (0) /* access=0 */ vec1 32 ssa_121 = intrinsic load_deref (ssa_120) (0) /* access=0 */ vec1 1 ssa_123 = uge ssa_121, ssa_122 vec1 1 ssa_123 = uge ssa_121, ssa_122 /* succs: block_9 block_10 */ /* succs: block_9 block_10 */ if ssa_123 { if ssa_123 { block block_9: block block_9: /* preds: block_8 */ /* preds: block_8 */ vec1 32 ssa_125 = deref_var &@14 (function_temp int) vec1 32 ssa_125 = deref_var &@14 (function_temp int) intrinsic store_deref (ssa_125, ssa_124) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_125, ssa_124) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_14 */ /* succs: block_14 */ } else { } else { block block_10: block block_10: /* preds: block_8 */ /* preds: block_8 */ vec1 32 ssa_126 = deref_var &@10 (function_temp uint) vec1 32 ssa_126 = deref_var &@10 (function_temp uint) vec1 32 ssa_127 = intrinsic load_deref (ssa_126) (0) /* access=0 */ vec1 32 ssa_127 = intrinsic load_deref (ssa_126) (0) /* access=0 */ vec1 1 ssa_129 = ult ssa_127, ssa_128 vec1 1 ssa_129 = ult ssa_127, ssa_128 /* succs: block_11 block_12 */ /* succs: block_11 block_12 */ if ssa_129 { if ssa_129 { block block_11: block block_11: /* preds: block_10 */ /* preds: block_10 */ vec1 32 ssa_131 = deref_var &@15 (function_temp uint) vec1 32 ssa_131 = deref_var &@15 (function_temp uint) intrinsic store_deref (ssa_131, ssa_130) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_131, ssa_130) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_13 */ /* succs: block_13 */ } else { } else { block block_12: block block_12: /* preds: block_10 */ /* preds: block_10 */ vec1 32 ssa_132 = deref_var &@10 (function_temp uint) vec1 32 ssa_132 = deref_var &@10 (function_temp uint) vec1 32 ssa_133 = intrinsic load_deref (ssa_132) (0) /* access=0 */ vec1 32 ssa_133 = intrinsic load_deref (ssa_132) (0) /* access=0 */ vec1 32 ssa_135 = isub ssa_133, ssa_134 vec1 32 ssa_135 = isub ssa_133, ssa_134 vec1 32 ssa_136 = deref_var &@15 (function_temp uint) vec1 32 ssa_136 = deref_var &@15 (function_temp uint) intrinsic store_deref (ssa_136, ssa_135) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_136, ssa_135) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_13 */ /* succs: block_13 */ } } block block_13: block block_13: /* preds: block_11 block_12 */ /* preds: block_11 block_12 */ vec1 32 ssa_137 = deref_var &@15 (function_temp uint) vec1 32 ssa_137 = deref_var &@15 (function_temp uint) vec1 32 ssa_138 = intrinsic load_deref (ssa_137) (0) /* access=0 */ vec1 32 ssa_138 = intrinsic load_deref (ssa_137) (0) /* access=0 */ vec1 32 ssa_140 = ishl ssa_139, ssa_138 vec1 32 ssa_140 = ishl ssa_139, ssa_138 vec1 32 ssa_141 = deref_var &@14 (function_temp int) vec1 32 ssa_141 = deref_var &@14 (function_temp int) intrinsic store_deref (ssa_141, ssa_140) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_141, ssa_140) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_14 */ /* succs: block_14 */ } } block block_14: block block_14: /* preds: block_9 block_13 */ /* preds: block_9 block_13 */ vec1 32 ssa_142 = deref_var &@14 (function_temp int) vec1 32 ssa_142 = deref_var &@14 (function_temp int) vec1 32 ssa_143 = intrinsic load_deref (ssa_142) (0) /* access=0 */ vec1 32 ssa_143 = intrinsic load_deref (ssa_142) (0) /* access=0 */ vec1 32 ssa_144 = mov ssa_143 vec1 32 ssa_144 = mov ssa_143 vec1 32 ssa_145 = deref_var &@10 (function_temp uint) vec1 32 ssa_145 = deref_var &@10 (function_temp uint) vec1 32 ssa_146 = intrinsic load_deref (ssa_145) (0) /* access=0 */ vec1 32 ssa_146 = intrinsic load_deref (ssa_145) (0) /* access=0 */ vec1 1 ssa_148 = uge ssa_146, ssa_147 vec1 1 ssa_148 = uge ssa_146, ssa_147 /* succs: block_15 block_16 */ /* succs: block_15 block_16 */ if ssa_148 { if ssa_148 { block block_15: block block_15: /* preds: block_14 */ /* preds: block_14 */ vec1 32 ssa_150 = deref_var &@16 (function_temp int) vec1 32 ssa_150 = deref_var &@16 (function_temp int) intrinsic store_deref (ssa_150, ssa_149) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_150, ssa_149) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_20 */ /* succs: block_20 */ } else { } else { block block_16: block block_16: /* preds: block_14 */ /* preds: block_14 */ vec1 32 ssa_151 = deref_var &@10 (function_temp uint) vec1 32 ssa_151 = deref_var &@10 (function_temp uint) vec1 32 ssa_152 = intrinsic load_deref (ssa_151) (0) /* access=0 */ vec1 32 ssa_152 = intrinsic load_deref (ssa_151) (0) /* access=0 */ vec1 1 ssa_154 = ult ssa_152, ssa_153 vec1 1 ssa_154 = ult ssa_152, ssa_153 /* succs: block_17 block_18 */ /* succs: block_17 block_18 */ if ssa_154 { if ssa_154 { block block_17: block block_17: /* preds: block_16 */ /* preds: block_16 */ vec1 32 ssa_156 = deref_var &@17 (function_temp uint) vec1 32 ssa_156 = deref_var &@17 (function_temp uint) intrinsic store_deref (ssa_156, ssa_155) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_156, ssa_155) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_19 */ /* succs: block_19 */ } else { } else { block block_18: block block_18: /* preds: block_16 */ /* preds: block_16 */ vec1 32 ssa_157 = deref_var &@10 (function_temp uint) vec1 32 ssa_157 = deref_var &@10 (function_temp uint) vec1 32 ssa_158 = intrinsic load_deref (ssa_157) (0) /* access=0 */ vec1 32 ssa_158 = intrinsic load_deref (ssa_157) (0) /* access=0 */ vec1 32 ssa_160 = isub ssa_158, ssa_159 vec1 32 ssa_160 = isub ssa_158, ssa_159 vec1 32 ssa_161 = deref_var &@17 (function_temp uint) vec1 32 ssa_161 = deref_var &@17 (function_temp uint) intrinsic store_deref (ssa_161, ssa_160) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_161, ssa_160) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_19 */ /* succs: block_19 */ } } block block_19: block block_19: /* preds: block_17 block_18 */ /* preds: block_17 block_18 */ vec1 32 ssa_162 = deref_var &@17 (function_temp uint) vec1 32 ssa_162 = deref_var &@17 (function_temp uint) vec1 32 ssa_163 = intrinsic load_deref (ssa_162) (0) /* access=0 */ vec1 32 ssa_163 = intrinsic load_deref (ssa_162) (0) /* access=0 */ vec1 32 ssa_165 = ishl ssa_164, ssa_163 vec1 32 ssa_165 = ishl ssa_164, ssa_163 vec1 32 ssa_166 = deref_var &@16 (function_temp int) vec1 32 ssa_166 = deref_var &@16 (function_temp int) intrinsic store_deref (ssa_166, ssa_165) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_166, ssa_165) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_20 */ /* succs: block_20 */ } } block block_20: block block_20: /* preds: block_15 block_19 */ /* preds: block_15 block_19 */ vec1 32 ssa_167 = deref_var &@16 (function_temp int) vec1 32 ssa_167 = deref_var &@16 (function_temp int) vec1 32 ssa_168 = intrinsic load_deref (ssa_167) (0) /* access=0 */ vec1 32 ssa_168 = intrinsic load_deref (ssa_167) (0) /* access=0 */ vec1 32 ssa_169 = mov ssa_168 vec1 32 ssa_169 = mov ssa_168 vec1 32 ssa_170 = deref_var &@10 (function_temp uint) vec1 32 ssa_170 = deref_var &@10 (function_temp uint) vec1 32 ssa_171 = intrinsic load_deref (ssa_170) (0) /* access=0 */ vec1 32 ssa_171 = intrinsic load_deref (ssa_170) (0) /* access=0 */ vec1 1 ssa_173 = uge ssa_171, ssa_172 vec1 1 ssa_173 = uge ssa_171, ssa_172 /* succs: block_21 block_22 */ /* succs: block_21 block_22 */ if ssa_173 { if ssa_173 { block block_21: block block_21: /* preds: block_20 */ /* preds: block_20 */ vec1 32 ssa_175 = deref_var &@18 (function_temp int) vec1 32 ssa_175 = deref_var &@18 (function_temp int) intrinsic store_deref (ssa_175, ssa_174) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_175, ssa_174) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_26 */ /* succs: block_26 */ } else { } else { block block_22: block block_22: /* preds: block_20 */ /* preds: block_20 */ vec1 32 ssa_176 = deref_var &@10 (function_temp uint) vec1 32 ssa_176 = deref_var &@10 (function_temp uint) vec1 32 ssa_177 = intrinsic load_deref (ssa_176) (0) /* access=0 */ vec1 32 ssa_177 = intrinsic load_deref (ssa_176) (0) /* access=0 */ vec1 1 ssa_179 = ult ssa_177, ssa_178 vec1 1 ssa_179 = ult ssa_177, ssa_178 /* succs: block_23 block_24 */ /* succs: block_23 block_24 */ if ssa_179 { if ssa_179 { block block_23: block block_23: /* preds: block_22 */ /* preds: block_22 */ vec1 32 ssa_181 = deref_var &@19 (function_temp uint) vec1 32 ssa_181 = deref_var &@19 (function_temp uint) intrinsic store_deref (ssa_181, ssa_180) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_181, ssa_180) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_25 */ /* succs: block_25 */ } else { } else { block block_24: block block_24: /* preds: block_22 */ /* preds: block_22 */ vec1 32 ssa_182 = deref_var &@10 (function_temp uint) vec1 32 ssa_182 = deref_var &@10 (function_temp uint) vec1 32 ssa_183 = intrinsic load_deref (ssa_182) (0) /* access=0 */ vec1 32 ssa_183 = intrinsic load_deref (ssa_182) (0) /* access=0 */ vec1 32 ssa_185 = isub ssa_183, ssa_184 vec1 32 ssa_185 = isub ssa_183, ssa_184 vec1 32 ssa_186 = deref_var &@19 (function_temp uint) vec1 32 ssa_186 = deref_var &@19 (function_temp uint) intrinsic store_deref (ssa_186, ssa_185) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_186, ssa_185) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_25 */ /* succs: block_25 */ } } block block_25: block block_25: /* preds: block_23 block_24 */ /* preds: block_23 block_24 */ vec1 32 ssa_187 = deref_var &@19 (function_temp uint) vec1 32 ssa_187 = deref_var &@19 (function_temp uint) vec1 32 ssa_188 = intrinsic load_deref (ssa_187) (0) /* access=0 */ vec1 32 ssa_188 = intrinsic load_deref (ssa_187) (0) /* access=0 */ vec1 32 ssa_190 = ishl ssa_189, ssa_188 vec1 32 ssa_190 = ishl ssa_189, ssa_188 vec1 32 ssa_191 = deref_var &@18 (function_temp int) vec1 32 ssa_191 = deref_var &@18 (function_temp int) intrinsic store_deref (ssa_191, ssa_190) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_191, ssa_190) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_26 */ /* succs: block_26 */ } } block block_26: block block_26: /* preds: block_21 block_25 */ /* preds: block_21 block_25 */ vec1 32 ssa_192 = deref_var &@18 (function_temp int) vec1 32 ssa_192 = deref_var &@18 (function_temp int) vec1 32 ssa_193 = intrinsic load_deref (ssa_192) (0) /* access=0 */ vec1 32 ssa_193 = intrinsic load_deref (ssa_192) (0) /* access=0 */ vec1 32 ssa_194 = mov ssa_193 vec1 32 ssa_194 = mov ssa_193 vec4 32 ssa_195 = vec4 ssa_119, ssa_144, ssa_169, ssa_194 vec4 32 ssa_195 = vec4 ssa_119, ssa_144, ssa_169, ssa_194 vec1 32 ssa_196 = deref_var &@12 (function_temp uvec4) vec1 32 ssa_196 = deref_var &@12 (function_temp uvec4) intrinsic store_deref (ssa_196, ssa_195) (15, 0) /* wrmask=xyzw */ /* access=0 */ intrinsic store_deref (ssa_196, ssa_195) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_197 = deref_var &@12 (function_temp uvec4) vec1 32 ssa_197 = deref_var &@12 (function_temp uvec4) vec4 32 ssa_198 = intrinsic load_deref (ssa_197) (0) /* access=0 */ vec4 32 ssa_198 = intrinsic load_deref (ssa_197) (0) /* access=0 */ vec1 32 ssa_199 = intrinsic ballot_bit_count_inclusive (ssa_198) () vec1 32 ssa_199 = intrinsic ballot_bit_count_inclusive (ssa_198) () vec1 32 ssa_200 = deref_var &@20 (function_temp uint) vec1 32 ssa_200 = deref_var &@20 (function_temp uint) intrinsic store_deref (ssa_200, ssa_199) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_200, ssa_199) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_201 = deref_var &@20 (function_temp uint) vec1 32 ssa_201 = deref_var &@20 (function_temp uint) vec1 32 ssa_202 = intrinsic load_deref (ssa_201) (0) /* access=0 */ vec1 32 ssa_202 = intrinsic load_deref (ssa_201) (0) /* access=0 */ vec1 32 ssa_203 = deref_var &@11 (function_temp uint) vec1 32 ssa_203 = deref_var &@11 (function_temp uint) vec1 32 ssa_204 = intrinsic load_deref (ssa_203) (0) /* access=0 */ vec1 32 ssa_204 = intrinsic load_deref (ssa_203) (0) /* access=0 */ vec1 1 ssa_205 = ine ssa_202, ssa_204 vec1 1 ssa_205 = ine ssa_202, ssa_204 /* succs: block_27 block_28 */ /* succs: block_27 block_28 */ if ssa_205 { if ssa_205 { block block_27: block block_27: /* preds: block_26 */ /* preds: block_26 */ vec1 32 ssa_206 = deref_var &@8 (function_temp uint) vec1 32 ssa_206 = deref_var &@8 (function_temp uint) vec1 32 ssa_207 = intrinsic load_deref (ssa_206) (0) /* access=0 */ vec1 32 ssa_207 = intrinsic load_deref (ssa_206) (0) /* access=0 */ vec1 32 ssa_209 = iand ssa_207, ssa_208 vec1 32 ssa_209 = iand ssa_207, ssa_208 vec1 32 ssa_210 = deref_var &@8 (function_temp uint) vec1 32 ssa_210 = deref_var &@8 (function_temp uint) intrinsic store_deref (ssa_210, ssa_209) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_210, ssa_209) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_29 */ /* succs: block_29 */ } else { } else { block block_28: block block_28: /* preds: block_26 */ /* preds: block_26 */ /* succs: block_29 */ /* succs: block_29 */ } } block block_29: block block_29: /* preds: block_27 block_28 */ /* preds: block_27 block_28 */ continue continue /* succs: block_1 */ /* succs: block_1 */ } else { } else { block block_30: block block_30: /* preds: block_4 */ /* preds: block_4 */ break break /* succs: block_32 */ /* succs: block_32 */ } } block block_31: block block_31: /* preds: */ /* preds: */ /* succs: block_1 */ /* succs: block_1 */ } } block block_32: block block_32: /* preds: block_30 */ /* preds: block_30 */ vec1 32 ssa_222 = deref_var &@5 (function_temp uint) vec1 32 ssa_222 = deref_var &@5 (function_temp uint) vec1 32 ssa_223 = intrinsic load_deref (ssa_222) (0) /* access=0 */ vec1 32 ssa_223 = intrinsic load_deref (ssa_222) (0) /* access=0 */ vec1 32 ssa_224 = deref_var &@8 (function_temp uint) vec1 32 ssa_224 = deref_var &@8 (function_temp uint) vec1 32 ssa_225 = intrinsic load_deref (ssa_224) (0) /* access=0 */ vec1 32 ssa_225 = intrinsic load_deref (ssa_224) (0) /* access=0 */ vec1 32 ssa_226 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_226 = load_const (0x00000000 /* 0.000000 */) vec1 64 ssa_227 = intrinsic vulkan_resource_index (ssa_226) (0, 0, 7) /* desc-set=0 */ /* binding=0 */ /* des vec1 64 ssa_227 = intrinsic vulkan_resource_index (ssa_226) (0, 0, 7) /* desc-set=0 */ /* binding=0 */ /* des vec1 64 ssa_228 = intrinsic load_vulkan_descriptor (ssa_227) (7) /* desc_type=SSBO */ vec1 64 ssa_228 = intrinsic load_vulkan_descriptor (ssa_227) (7) /* desc_type=SSBO */ vec1 64 ssa_229 = deref_cast (block *)ssa_228 (ssbo block) /* ptr_stride=0, align_mul=0, align_offset=0 */ vec1 64 ssa_229 = deref_cast (block *)ssa_228 (ssbo block) /* ptr_stride=0, align_mul=0, align_offset=0 */ vec1 64 ssa_230 = deref_struct &ssa_229->field0 (ssbo uint[]) /* &((block *)ssa_228)->field0 */ vec1 64 ssa_230 = deref_struct &ssa_229->field0 (ssbo uint[]) /* &((block *)ssa_228)->field0 */ vec1 64 ssa_231 = i2i64 ssa_223 vec1 64 ssa_231 = i2i64 ssa_223 vec1 64 ssa_232 = deref_array &(*ssa_230)[ssa_231] (ssbo uint) /* &((block *)ssa_228)->field0[ssa_231] */ vec1 64 ssa_232 = deref_array &(*ssa_230)[ssa_231] (ssbo uint) /* &((block *)ssa_228)->field0[ssa_231] */ intrinsic store_deref (ssa_232, ssa_225) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_232, ssa_225) (1, 0) /* wrmask=x */ /* access=0 */ return return /* succs: block_33 */ /* succs: block_33 */ block block_33: block block_33: } } NIR (SSA form) for compute shader: NIR (SSA form) for compute shader: shader: MESA_SHADER_COMPUTE shader: MESA_SHADER_COMPUTE local-size: 32, 4, 1 local-size: 32, 4, 1 shared-size: 0 shared-size: 0 inputs: 0 inputs: 0 outputs: 0 outputs: 0 uniforms: 36 uniforms: 36 shared: 0 shared: 0 decl_var ssbo INTERP_MODE_NONE restrict block @0 (~0, 0, 0) decl_var ssbo INTERP_MODE_NONE restrict block @0 (~0, 0, 0) decl_function main (0 params) decl_function main (0 params) impl main { impl main { block block_0: block block_0: /* preds: */ /* preds: */ vec1 32 ssa_0 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_0 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_1 = load_const (0xfffffff7 /* -nan */) vec1 32 ssa_1 = load_const (0xfffffff7 /* -nan */) vec1 32 ssa_2 = load_const (0xffffffff /* -nan */) vec1 32 ssa_2 = load_const (0xffffffff /* -nan */) vec1 32 ssa_3 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_4 = load_const (0x00000080 /* 0.000000 */) vec1 32 ssa_4 = load_const (0x00000080 /* 0.000000 */) vec1 32 ssa_5 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_5 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_6 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_6 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_7 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_7 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_8 = load_const (0xffffffff /* -nan */) vec1 32 ssa_8 = load_const (0xffffffff /* -nan */) vec1 32 ssa_9 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_9 = load_const (0x00000002 /* 0.000000 */) vec3 32 ssa_10 = intrinsic load_num_work_groups () () vec3 32 ssa_10 = intrinsic load_num_work_groups () () vec1 32 ssa_11 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_11 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_12 = ishl ssa_10.x, ssa_11 vec1 32 ssa_12 = ishl ssa_10.x, ssa_11 vec1 32 ssa_13 = ishl ssa_10.y, ssa_9 vec1 32 ssa_13 = ishl ssa_10.y, ssa_9 vec3 32 ssa_14 = intrinsic load_work_group_id () () vec3 32 ssa_14 = intrinsic load_work_group_id () () vec3 32 ssa_15 = intrinsic load_uniform (ssa_3) (24, 12, 0) /* base=24 */ /* range=12 */ /* dest_type=invalid vec3 32 ssa_15 = intrinsic load_uniform (ssa_3) (24, 12, 0) /* base=24 */ /* range=12 */ /* dest_type=invalid vec1 32 ssa_16 = iadd ssa_14.x, ssa_15.x vec1 32 ssa_16 = iadd ssa_14.x, ssa_15.x vec1 32 ssa_17 = iadd ssa_14.y, ssa_15.y vec1 32 ssa_17 = iadd ssa_14.y, ssa_15.y vec1 32 ssa_18 = iadd ssa_14.z, ssa_15.z vec1 32 ssa_18 = iadd ssa_14.z, ssa_15.z vec1 32 ssa_19 = intrinsic load_subgroup_id () () vec1 32 ssa_19 = intrinsic load_subgroup_id () () vec1 32 ssa_20 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_20 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_21 = ishl ssa_19, ssa_20 vec1 32 ssa_21 = ishl ssa_19, ssa_20 vec1 32 ssa_22 = intrinsic load_subgroup_invocation () () vec1 32 ssa_22 = intrinsic load_subgroup_invocation () () vec1 32 ssa_23 = iadd ssa_22, ssa_21 vec1 32 ssa_23 = iadd ssa_22, ssa_21 vec1 32 ssa_24 = load_const (0x0000001f /* 0.000000 */) vec1 32 ssa_24 = load_const (0x0000001f /* 0.000000 */) vec1 32 ssa_25 = iand ssa_23, ssa_24 vec1 32 ssa_25 = iand ssa_23, ssa_24 vec1 32 ssa_26 = ushr ssa_23, ssa_11 vec1 32 ssa_26 = ushr ssa_23, ssa_11 vec1 32 ssa_27 = iand ssa_26, ssa_20 vec1 32 ssa_27 = iand ssa_26, ssa_20 vec1 32 ssa_28 = load_const (0x00000007 /* 0.000000 */) vec1 32 ssa_28 = load_const (0x00000007 /* 0.000000 */) vec1 32 ssa_29 = ushr ssa_23, ssa_28 vec1 32 ssa_29 = ushr ssa_23, ssa_28 vec1 32 ssa_30 = ishl ssa_16, ssa_11 vec1 32 ssa_30 = ishl ssa_16, ssa_11 vec1 32 ssa_31 = ishl ssa_17, ssa_9 vec1 32 ssa_31 = ishl ssa_17, ssa_9 vec1 32 ssa_32 = iadd ssa_30, ssa_25 vec1 32 ssa_32 = iadd ssa_30, ssa_25 vec1 32 ssa_33 = iadd ssa_31, ssa_27 vec1 32 ssa_33 = iadd ssa_31, ssa_27 vec1 32 ssa_34 = iadd ssa_18, ssa_29 vec1 32 ssa_34 = iadd ssa_18, ssa_29 vec1 32 ssa_35 = imul ssa_13, ssa_34 vec1 32 ssa_35 = imul ssa_13, ssa_34 vec1 32 ssa_36 = iadd ssa_35, ssa_33 vec1 32 ssa_36 = iadd ssa_35, ssa_33 vec1 32 ssa_37 = imul ssa_12, ssa_36 vec1 32 ssa_37 = imul ssa_12, ssa_36 vec1 32 ssa_38 = iadd ssa_37, ssa_32 vec1 32 ssa_38 = iadd ssa_37, ssa_32 vec1 32 ssa_39 = iadd ssa_22, ssa_0 vec1 32 ssa_39 = iadd ssa_22, ssa_0 vec1 32 ssa_40 = ineg ssa_22 vec1 32 ssa_40 = ineg ssa_22 vec1 32 ssa_41 = iadd ssa_24, ssa_40 vec1 32 ssa_41 = iadd ssa_24, ssa_40 vec1 32 ssa_42 = ushr ssa_2, ssa_41 vec1 32 ssa_42 = ushr ssa_2, ssa_41 vec1 32 ssa_43 = bit_count ssa_42 vec1 32 ssa_43 = bit_count ssa_42 vec1 32 ssa_44 = ieq32 ssa_39, ssa_43 vec1 32 ssa_44 = ieq32 ssa_39, ssa_43 vec1 32 ssa_45 = b2i32 ssa_44 vec1 32 ssa_45 = b2i32 ssa_44 vec1 32 ssa_46 = ior ssa_45, ssa_9 vec1 32 ssa_46 = ior ssa_45, ssa_9 vec1 32 ssa_47 = intrinsic ballot (ssa_8) () vec1 32 ssa_47 = intrinsic ballot (ssa_8) () vec1 32 ssa_48 = iand ssa_47, ssa_42 vec1 32 ssa_48 = iand ssa_47, ssa_42 vec1 32 ssa_49 = bit_count ssa_48 vec1 32 ssa_49 = bit_count ssa_48 vec1 32 ssa_50 = ult32 ssa_3, ssa_49 vec1 32 ssa_50 = ult32 ssa_3, ssa_49 vec1 32 ssa_51 = b32csel ssa_50, ssa_7, ssa_3 vec1 32 ssa_51 = b32csel ssa_50, ssa_7, ssa_3 vec1 32 ssa_52 = ior ssa_46, ssa_51 vec1 32 ssa_52 = ior ssa_46, ssa_51 vec1 32 ssa_53 = ior ssa_52, ssa_6 vec1 32 ssa_53 = ior ssa_52, ssa_6 /* succs: block_1 */ /* succs: block_1 */ loop { loop { block block_1: block block_1: /* preds: block_0 block_4 */ /* preds: block_0 block_4 */ vec1 32 ssa_54 = phi block_0: ssa_53, block_4: ssa_67 vec1 32 ssa_54 = phi block_0: ssa_53, block_4: ssa_67 vec1 32 ssa_55 = phi block_0: ssa_3, block_4: ssa_68 vec1 32 ssa_55 = phi block_0: ssa_3, block_4: ssa_68 vec1 32 ssa_56 = uge32 ssa_55, ssa_4 vec1 32 ssa_56 = uge32 ssa_55, ssa_4 /* succs: block_2 block_3 */ /* succs: block_2 block_3 */ if ssa_56 { if ssa_56 { block block_2: block block_2: /* preds: block_1 */ /* preds: block_1 */ break break /* succs: block_5 */ /* succs: block_5 */ } else { } else { block block_3: block block_3: /* preds: block_1 */ /* preds: block_1 */ /* succs: block_4 */ /* succs: block_4 */ } } block block_4: block block_4: /* preds: block_3 */ /* preds: block_3 */ vec1 32 ssa_57 = umin ssa_39, ssa_55 vec1 32 ssa_57 = umin ssa_39, ssa_55 vec1 32 ssa_58 = ineg ssa_57 vec1 32 ssa_58 = ineg ssa_57 vec1 32 ssa_59 = iadd ssa_39, ssa_58 vec1 32 ssa_59 = iadd ssa_39, ssa_58 vec1 32 ssa_60 = ishl ssa_2, ssa_55 vec1 32 ssa_60 = ishl ssa_2, ssa_55 vec1 32 ssa_61 = uge32 ssa_55, ssa_5 vec1 32 ssa_61 = uge32 ssa_55, ssa_5 vec1 32 ssa_62 = b32csel ssa_61, ssa_3, ssa_60 vec1 32 ssa_62 = b32csel ssa_61, ssa_3, ssa_60 vec1 32 ssa_63 = iand ssa_62, ssa_42 vec1 32 ssa_63 = iand ssa_62, ssa_42 vec1 32 ssa_64 = bit_count ssa_63 vec1 32 ssa_64 = bit_count ssa_63 vec1 32 ssa_65 = iand ssa_54, ssa_1 vec1 32 ssa_65 = iand ssa_54, ssa_1 vec1 32 ssa_66 = ine32 ssa_64, ssa_59 vec1 32 ssa_66 = ine32 ssa_64, ssa_59 vec1 32 ssa_67 = b32csel ssa_66, ssa_65, ssa_54 vec1 32 ssa_67 = b32csel ssa_66, ssa_65, ssa_54 vec1 32 ssa_68 = iadd ssa_55, ssa_0 vec1 32 ssa_68 = iadd ssa_55, ssa_0 /* succs: block_1 */ /* succs: block_1 */ } } block block_5: block block_5: /* preds: block_2 */ /* preds: block_2 */ vec1 32 ssa_69 = ishl ssa_38, ssa_9 vec1 32 ssa_69 = ishl ssa_38, ssa_9 intrinsic store_ssbo (ssa_54, ssa_9, ssa_69) (1, 0, 4, 0) /* wrmask=x */ /* access=0 */ /* align_mul=4 */ /* intrinsic store_ssbo (ssa_54, ssa_9, ssa_69) (1, 0, 4, 0) /* wrmask=x */ /* access=0 */ /* align_mul=4 */ /* /* succs: block_6 */ /* succs: block_6 */ block block_6: block block_6: } } NIR (final form) for compute shader: NIR (final form) for compute shader: shader: MESA_SHADER_COMPUTE shader: MESA_SHADER_COMPUTE local-size: 32, 4, 1 local-size: 32, 4, 1 shared-size: 0 shared-size: 0 inputs: 0 inputs: 0 outputs: 0 outputs: 0 uniforms: 36 uniforms: 36 shared: 0 shared: 0 decl_var ssbo INTERP_MODE_NONE restrict block @0 (~0, 0, 0) decl_var ssbo INTERP_MODE_NONE restrict block @0 (~0, 0, 0) decl_function main (0 params) decl_function main (0 params) impl main { impl main { decl_reg vec1 32 r3 decl_reg vec1 32 r3 decl_reg vec1 32 r4 decl_reg vec1 32 r4 block block_0: block block_0: /* preds: */ /* preds: */ vec1 32 ssa_0 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_0 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_1 = load_const (0xfffffff7 /* -nan */) vec1 32 ssa_1 = load_const (0xfffffff7 /* -nan */) vec1 32 ssa_2 = load_const (0xffffffff /* -nan */) vec1 32 ssa_2 = load_const (0xffffffff /* -nan */) vec1 32 ssa_3 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_4 = load_const (0x00000080 /* 0.000000 */) vec1 32 ssa_4 = load_const (0x00000080 /* 0.000000 */) vec1 32 ssa_5 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_5 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_6 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_6 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_7 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_7 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_8 = load_const (0xffffffff /* -nan */) vec1 32 ssa_8 = load_const (0xffffffff /* -nan */) vec1 32 ssa_9 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_9 = load_const (0x00000002 /* 0.000000 */) vec3 32 ssa_10 = intrinsic load_num_work_groups () () vec3 32 ssa_10 = intrinsic load_num_work_groups () () vec1 32 ssa_11 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_11 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_12 = ishl ssa_10.x, ssa_11 vec1 32 ssa_12 = ishl ssa_10.x, ssa_11 vec1 32 ssa_13 = ishl ssa_10.y, ssa_9 vec1 32 ssa_13 = ishl ssa_10.y, ssa_9 vec3 32 ssa_14 = intrinsic load_work_group_id () () vec3 32 ssa_14 = intrinsic load_work_group_id () () vec3 32 ssa_15 = intrinsic load_uniform (ssa_3) (24, 12, 0) /* base=24 */ /* range=12 */ /* dest_type=invalid vec3 32 ssa_15 = intrinsic load_uniform (ssa_3) (24, 12, 0) /* base=24 */ /* range=12 */ /* dest_type=invalid vec1 32 ssa_16 = iadd ssa_14.x, ssa_15.x vec1 32 ssa_16 = iadd ssa_14.x, ssa_15.x vec1 32 ssa_17 = iadd ssa_14.y, ssa_15.y vec1 32 ssa_17 = iadd ssa_14.y, ssa_15.y vec1 32 ssa_18 = iadd ssa_14.z, ssa_15.z vec1 32 ssa_18 = iadd ssa_14.z, ssa_15.z vec1 32 ssa_19 = intrinsic load_subgroup_id () () vec1 32 ssa_19 = intrinsic load_subgroup_id () () vec1 32 ssa_20 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_20 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_21 = ishl ssa_19, ssa_20 vec1 32 ssa_21 = ishl ssa_19, ssa_20 vec1 32 ssa_22 = intrinsic load_subgroup_invocation () () vec1 32 ssa_22 = intrinsic load_subgroup_invocation () () vec1 32 ssa_23 = iadd ssa_22, ssa_21 vec1 32 ssa_23 = iadd ssa_22, ssa_21 vec1 32 ssa_24 = load_const (0x0000001f /* 0.000000 */) vec1 32 ssa_24 = load_const (0x0000001f /* 0.000000 */) vec1 32 ssa_25 = iand ssa_23, ssa_24 vec1 32 ssa_25 = iand ssa_23, ssa_24 vec1 32 ssa_26 = ushr ssa_23, ssa_11 vec1 32 ssa_26 = ushr ssa_23, ssa_11 vec1 32 ssa_27 = iand ssa_26, ssa_20 vec1 32 ssa_27 = iand ssa_26, ssa_20 vec1 32 ssa_28 = load_const (0x00000007 /* 0.000000 */) vec1 32 ssa_28 = load_const (0x00000007 /* 0.000000 */) vec1 32 ssa_29 = ushr ssa_23, ssa_28 vec1 32 ssa_29 = ushr ssa_23, ssa_28 vec1 32 ssa_30 = ishl ssa_16, ssa_11 vec1 32 ssa_30 = ishl ssa_16, ssa_11 vec1 32 ssa_31 = ishl ssa_17, ssa_9 vec1 32 ssa_31 = ishl ssa_17, ssa_9 vec1 32 ssa_32 = iadd ssa_30, ssa_25 vec1 32 ssa_32 = iadd ssa_30, ssa_25 vec1 32 ssa_33 = iadd ssa_31, ssa_27 vec1 32 ssa_33 = iadd ssa_31, ssa_27 vec1 32 ssa_34 = iadd ssa_18, ssa_29 vec1 32 ssa_34 = iadd ssa_18, ssa_29 vec1 32 ssa_35 = imul ssa_13, ssa_34 vec1 32 ssa_35 = imul ssa_13, ssa_34 vec1 32 ssa_36 = iadd ssa_35, ssa_33 vec1 32 ssa_36 = iadd ssa_35, ssa_33 vec1 32 ssa_37 = imul ssa_12, ssa_36 vec1 32 ssa_37 = imul ssa_12, ssa_36 vec1 32 ssa_38 = iadd ssa_37, ssa_32 vec1 32 ssa_38 = iadd ssa_37, ssa_32 vec1 32 ssa_39 = iadd ssa_22, ssa_0 vec1 32 ssa_39 = iadd ssa_22, ssa_0 vec1 32 ssa_40 = ineg ssa_22 vec1 32 ssa_40 = ineg ssa_22 vec1 32 ssa_41 = iadd ssa_24, ssa_40 vec1 32 ssa_41 = iadd ssa_24, ssa_40 vec1 32 ssa_42 = ushr ssa_2, ssa_41 vec1 32 ssa_42 = ushr ssa_2, ssa_41 vec1 32 ssa_43 = bit_count ssa_42 vec1 32 ssa_43 = bit_count ssa_42 vec1 32 ssa_44 = ieq32 ssa_39, ssa_43 vec1 32 ssa_44 = ieq32 ssa_39, ssa_43 vec1 32 ssa_45 = b2i32 ssa_44 vec1 32 ssa_45 = b2i32 ssa_44 vec1 32 ssa_46 = ior ssa_45, ssa_9 vec1 32 ssa_46 = ior ssa_45, ssa_9 vec1 32 ssa_47 = intrinsic ballot (ssa_8) () vec1 32 ssa_47 = intrinsic ballot (ssa_8) () vec1 32 ssa_48 = iand ssa_47, ssa_42 vec1 32 ssa_48 = iand ssa_47, ssa_42 vec1 32 ssa_49 = bit_count ssa_48 vec1 32 ssa_49 = bit_count ssa_48 vec1 32 ssa_50 = ult32 ssa_3, ssa_49 vec1 32 ssa_50 = ult32 ssa_3, ssa_49 vec1 32 ssa_51 = b32csel ssa_50, ssa_7, ssa_3 vec1 32 ssa_51 = b32csel ssa_50, ssa_7, ssa_3 vec1 32 ssa_52 = ior ssa_46, ssa_51 vec1 32 ssa_52 = ior ssa_46, ssa_51 r3 = ior ssa_52, ssa_6 r3 = ior ssa_52, ssa_6 r4 = mov ssa_3 r4 = mov ssa_3 /* succs: block_1 */ /* succs: block_1 */ loop { loop { block block_1: block block_1: /* preds: block_0 block_4 */ /* preds: block_0 block_4 */ vec1 32 ssa_56 = uge32 r4, ssa_4 vec1 32 ssa_56 = uge32 r4, ssa_4 /* succs: block_2 block_3 */ /* succs: block_2 block_3 */ if ssa_56 { if ssa_56 { block block_2: block block_2: /* preds: block_1 */ /* preds: block_1 */ break break /* succs: block_5 */ /* succs: block_5 */ } else { } else { block block_3: block block_3: /* preds: block_1 */ /* preds: block_1 */ /* succs: block_4 */ /* succs: block_4 */ } } block block_4: block block_4: /* preds: block_3 */ /* preds: block_3 */ vec1 32 ssa_57 = umin ssa_39, r4 vec1 32 ssa_57 = umin ssa_39, r4 vec1 32 ssa_58 = ineg ssa_57 vec1 32 ssa_58 = ineg ssa_57 vec1 32 ssa_59 = iadd ssa_39, ssa_58 vec1 32 ssa_59 = iadd ssa_39, ssa_58 vec1 32 ssa_60 = ishl ssa_2, r4 vec1 32 ssa_60 = ishl ssa_2, r4 vec1 32 ssa_61 = uge32 r4, ssa_5 vec1 32 ssa_61 = uge32 r4, ssa_5 vec1 32 ssa_62 = b32csel ssa_61, ssa_3, ssa_60 vec1 32 ssa_62 = b32csel ssa_61, ssa_3, ssa_60 vec1 32 ssa_63 = iand ssa_62, ssa_42 vec1 32 ssa_63 = iand ssa_62, ssa_42 vec1 32 ssa_64 = bit_count ssa_63 vec1 32 ssa_64 = bit_count ssa_63 vec1 32 ssa_65 = iand r3, ssa_1 vec1 32 ssa_65 = iand r3, ssa_1 vec1 32 ssa_66 = ine32 ssa_64, ssa_59 vec1 32 ssa_66 = ine32 ssa_64, ssa_59 r3 = b32csel ssa_66, ssa_65, r3 r3 = b32csel ssa_66, ssa_65, r3 r4 = iadd r4, ssa_0 r4 = iadd r4, ssa_0 /* succs: block_1 */ /* succs: block_1 */ } } block block_5: block block_5: /* preds: block_2 */ /* preds: block_2 */ vec1 32 ssa_69 = ishl ssa_38, ssa_9 vec1 32 ssa_69 = ishl ssa_38, ssa_9 intrinsic store_ssbo (r3, ssa_9, ssa_69) (1, 0, 4, 0) /* wrmask=x */ /* access=0 */ /* align_mul=4 */ /* alig intrinsic store_ssbo (r3, ssa_9, ssa_69) (1, 0, 4, 0) /* wrmask=x */ /* access=0 */ /* align_mul=4 */ /* alig /* succs: block_6 */ /* succs: block_6 */ block block_6: block block_6: } } NIR (SSA form) for compute shader: NIR (SSA form) for compute shader: shader: MESA_SHADER_COMPUTE shader: MESA_SHADER_COMPUTE local-size: 32, 4, 1 local-size: 32, 4, 1 shared-size: 0 shared-size: 0 inputs: 0 inputs: 0 outputs: 0 outputs: 0 uniforms: 36 uniforms: 36 shared: 0 shared: 0 decl_var ssbo INTERP_MODE_NONE restrict block @0 (~0, 0, 0) decl_var ssbo INTERP_MODE_NONE restrict block @0 (~0, 0, 0) decl_function main (0 params) decl_function main (0 params) impl main { impl main { block block_0: block block_0: /* preds: */ /* preds: */ vec1 32 ssa_0 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_0 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_1 = load_const (0xfffffff7 /* -nan */) vec1 32 ssa_1 = load_const (0xfffffff7 /* -nan */) vec1 32 ssa_2 = load_const (0xffffffff /* -nan */) vec1 32 ssa_2 = load_const (0xffffffff /* -nan */) vec1 32 ssa_3 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_4 = load_const (0x00000080 /* 0.000000 */) vec1 32 ssa_4 = load_const (0x00000080 /* 0.000000 */) vec1 32 ssa_5 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_5 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_6 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_6 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_7 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_7 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_8 = load_const (0xffffffff /* -nan */) vec1 32 ssa_8 = load_const (0xffffffff /* -nan */) vec1 32 ssa_9 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_9 = load_const (0x00000002 /* 0.000000 */) vec3 32 ssa_10 = intrinsic load_num_work_groups () () vec3 32 ssa_10 = intrinsic load_num_work_groups () () vec1 32 ssa_11 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_11 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_12 = ishl ssa_10.x, ssa_11 vec1 32 ssa_12 = ishl ssa_10.x, ssa_11 vec1 32 ssa_13 = ishl ssa_10.y, ssa_9 vec1 32 ssa_13 = ishl ssa_10.y, ssa_9 vec3 32 ssa_14 = intrinsic load_work_group_id () () vec3 32 ssa_14 = intrinsic load_work_group_id () () vec3 32 ssa_15 = intrinsic load_uniform (ssa_3) (24, 12, 0) /* base=24 */ /* range=12 */ /* dest_type=invalid vec3 32 ssa_15 = intrinsic load_uniform (ssa_3) (24, 12, 0) /* base=24 */ /* range=12 */ /* dest_type=invalid vec1 32 ssa_16 = iadd ssa_14.x, ssa_15.x vec1 32 ssa_16 = iadd ssa_14.x, ssa_15.x vec1 32 ssa_17 = iadd ssa_14.y, ssa_15.y vec1 32 ssa_17 = iadd ssa_14.y, ssa_15.y vec1 32 ssa_18 = iadd ssa_14.z, ssa_15.z vec1 32 ssa_18 = iadd ssa_14.z, ssa_15.z vec1 32 ssa_19 = intrinsic load_subgroup_id () () vec1 32 ssa_19 = intrinsic load_subgroup_id () () vec1 32 ssa_20 = ishl ssa_19, ssa_7 vec1 32 ssa_20 = ishl ssa_19, ssa_7 vec1 32 ssa_21 = intrinsic load_subgroup_invocation () () vec1 32 ssa_21 = intrinsic load_subgroup_invocation () () vec1 32 ssa_22 = iadd ssa_21, ssa_20 vec1 32 ssa_22 = iadd ssa_21, ssa_20 vec1 32 ssa_23 = load_const (0x0000001f /* 0.000000 */) vec1 32 ssa_23 = load_const (0x0000001f /* 0.000000 */) vec1 32 ssa_24 = iand ssa_22, ssa_23 vec1 32 ssa_24 = iand ssa_22, ssa_23 vec1 32 ssa_25 = ushr ssa_22, ssa_11 vec1 32 ssa_25 = ushr ssa_22, ssa_11 vec1 32 ssa_26 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_26 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_27 = iand ssa_25, ssa_26 vec1 32 ssa_27 = iand ssa_25, ssa_26 vec1 32 ssa_28 = load_const (0x00000007 /* 0.000000 */) vec1 32 ssa_28 = load_const (0x00000007 /* 0.000000 */) vec1 32 ssa_29 = ushr ssa_22, ssa_28 vec1 32 ssa_29 = ushr ssa_22, ssa_28 vec1 32 ssa_30 = ishl ssa_16, ssa_11 vec1 32 ssa_30 = ishl ssa_16, ssa_11 vec1 32 ssa_31 = ishl ssa_17, ssa_9 vec1 32 ssa_31 = ishl ssa_17, ssa_9 vec1 32 ssa_32 = iadd ssa_30, ssa_24 vec1 32 ssa_32 = iadd ssa_30, ssa_24 vec1 32 ssa_33 = iadd ssa_31, ssa_27 vec1 32 ssa_33 = iadd ssa_31, ssa_27 vec1 32 ssa_34 = iadd ssa_18, ssa_29 vec1 32 ssa_34 = iadd ssa_18, ssa_29 vec1 32 ssa_35 = imul ssa_13, ssa_34 vec1 32 ssa_35 = imul ssa_13, ssa_34 vec1 32 ssa_36 = iadd ssa_35, ssa_33 vec1 32 ssa_36 = iadd ssa_35, ssa_33 vec1 32 ssa_37 = imul ssa_12, ssa_36 vec1 32 ssa_37 = imul ssa_12, ssa_36 vec1 32 ssa_38 = iadd ssa_37, ssa_32 vec1 32 ssa_38 = iadd ssa_37, ssa_32 vec1 32 ssa_39 = iadd ssa_21, ssa_0 vec1 32 ssa_39 = iadd ssa_21, ssa_0 vec1 32 ssa_40 = ineg ssa_21 vec1 32 ssa_40 = ineg ssa_21 vec1 32 ssa_41 = iadd ssa_23, ssa_40 vec1 32 ssa_41 = iadd ssa_23, ssa_40 vec1 32 ssa_42 = ushr ssa_2, ssa_41 vec1 32 ssa_42 = ushr ssa_2, ssa_41 vec1 32 ssa_43 = bit_count ssa_42 vec1 32 ssa_43 = bit_count ssa_42 vec1 32 ssa_44 = ieq32 ssa_39, ssa_43 vec1 32 ssa_44 = ieq32 ssa_39, ssa_43 vec1 32 ssa_45 = b2i32 ssa_44 vec1 32 ssa_45 = b2i32 ssa_44 vec1 32 ssa_46 = ior ssa_45, ssa_9 vec1 32 ssa_46 = ior ssa_45, ssa_9 vec1 32 ssa_47 = intrinsic ballot (ssa_8) () vec1 32 ssa_47 = intrinsic ballot (ssa_8) () vec1 32 ssa_48 = iand ssa_47, ssa_42 vec1 32 ssa_48 = iand ssa_47, ssa_42 vec1 32 ssa_49 = bit_count ssa_48 vec1 32 ssa_49 = bit_count ssa_48 vec1 32 ssa_50 = ult32 ssa_3, ssa_49 vec1 32 ssa_50 = ult32 ssa_3, ssa_49 vec1 32 ssa_51 = b32csel ssa_50, ssa_7, ssa_3 vec1 32 ssa_51 = b32csel ssa_50, ssa_7, ssa_3 vec1 32 ssa_52 = ior ssa_46, ssa_51 vec1 32 ssa_52 = ior ssa_46, ssa_51 vec1 32 ssa_53 = ior ssa_52, ssa_6 vec1 32 ssa_53 = ior ssa_52, ssa_6 /* succs: block_1 */ /* succs: block_1 */ loop { loop { block block_1: block block_1: /* preds: block_0 block_4 */ /* preds: block_0 block_4 */ vec1 32 ssa_54 = phi block_0: ssa_53, block_4: ssa_67 vec1 32 ssa_54 = phi block_0: ssa_53, block_4: ssa_67 vec1 32 ssa_55 = phi block_0: ssa_3, block_4: ssa_68 vec1 32 ssa_55 = phi block_0: ssa_3, block_4: ssa_68 vec1 32 ssa_56 = uge32 ssa_55, ssa_4 vec1 32 ssa_56 = uge32 ssa_55, ssa_4 /* succs: block_2 block_3 */ /* succs: block_2 block_3 */ if ssa_56 { if ssa_56 { block block_2: block block_2: /* preds: block_1 */ /* preds: block_1 */ break break /* succs: block_5 */ /* succs: block_5 */ } else { } else { block block_3: block block_3: /* preds: block_1 */ /* preds: block_1 */ /* succs: block_4 */ /* succs: block_4 */ } } block block_4: block block_4: /* preds: block_3 */ /* preds: block_3 */ vec1 32 ssa_57 = umin ssa_39, ssa_55 vec1 32 ssa_57 = umin ssa_39, ssa_55 vec1 32 ssa_58 = ineg ssa_57 vec1 32 ssa_58 = ineg ssa_57 vec1 32 ssa_59 = iadd ssa_39, ssa_58 vec1 32 ssa_59 = iadd ssa_39, ssa_58 vec1 32 ssa_60 = ishl ssa_2, ssa_55 vec1 32 ssa_60 = ishl ssa_2, ssa_55 vec1 32 ssa_61 = uge32 ssa_55, ssa_5 vec1 32 ssa_61 = uge32 ssa_55, ssa_5 vec1 32 ssa_62 = b32csel ssa_61, ssa_3, ssa_60 vec1 32 ssa_62 = b32csel ssa_61, ssa_3, ssa_60 vec1 32 ssa_63 = iand ssa_62, ssa_42 vec1 32 ssa_63 = iand ssa_62, ssa_42 vec1 32 ssa_64 = bit_count ssa_63 vec1 32 ssa_64 = bit_count ssa_63 vec1 32 ssa_65 = iand ssa_54, ssa_1 vec1 32 ssa_65 = iand ssa_54, ssa_1 vec1 32 ssa_66 = ine32 ssa_64, ssa_59 vec1 32 ssa_66 = ine32 ssa_64, ssa_59 vec1 32 ssa_67 = b32csel ssa_66, ssa_65, ssa_54 vec1 32 ssa_67 = b32csel ssa_66, ssa_65, ssa_54 vec1 32 ssa_68 = iadd ssa_55, ssa_0 vec1 32 ssa_68 = iadd ssa_55, ssa_0 /* succs: block_1 */ /* succs: block_1 */ } } block block_5: block block_5: /* preds: block_2 */ /* preds: block_2 */ vec1 32 ssa_69 = ishl ssa_38, ssa_9 vec1 32 ssa_69 = ishl ssa_38, ssa_9 intrinsic store_ssbo (ssa_54, ssa_9, ssa_69) (1, 0, 4, 0) /* wrmask=x */ /* access=0 */ /* align_mul=4 */ /* intrinsic store_ssbo (ssa_54, ssa_9, ssa_69) (1, 0, 4, 0) /* wrmask=x */ /* access=0 */ /* align_mul=4 */ /* /* succs: block_6 */ /* succs: block_6 */ block block_6: block block_6: } } NIR (final form) for compute shader: NIR (final form) for compute shader: shader: MESA_SHADER_COMPUTE shader: MESA_SHADER_COMPUTE local-size: 32, 4, 1 local-size: 32, 4, 1 shared-size: 0 shared-size: 0 inputs: 0 inputs: 0 outputs: 0 outputs: 0 uniforms: 36 uniforms: 36 shared: 0 shared: 0 decl_var ssbo INTERP_MODE_NONE restrict block @0 (~0, 0, 0) decl_var ssbo INTERP_MODE_NONE restrict block @0 (~0, 0, 0) decl_function main (0 params) decl_function main (0 params) impl main { impl main { decl_reg vec1 32 r3 decl_reg vec1 32 r3 decl_reg vec1 32 r4 decl_reg vec1 32 r4 block block_0: block block_0: /* preds: */ /* preds: */ vec1 32 ssa_0 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_0 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_1 = load_const (0xfffffff7 /* -nan */) vec1 32 ssa_1 = load_const (0xfffffff7 /* -nan */) vec1 32 ssa_2 = load_const (0xffffffff /* -nan */) vec1 32 ssa_2 = load_const (0xffffffff /* -nan */) vec1 32 ssa_3 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_4 = load_const (0x00000080 /* 0.000000 */) vec1 32 ssa_4 = load_const (0x00000080 /* 0.000000 */) vec1 32 ssa_5 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_5 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_6 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_6 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_7 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_7 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_8 = load_const (0xffffffff /* -nan */) vec1 32 ssa_8 = load_const (0xffffffff /* -nan */) vec1 32 ssa_9 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_9 = load_const (0x00000002 /* 0.000000 */) vec3 32 ssa_10 = intrinsic load_num_work_groups () () vec3 32 ssa_10 = intrinsic load_num_work_groups () () vec1 32 ssa_11 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_11 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_12 = ishl ssa_10.x, ssa_11 vec1 32 ssa_12 = ishl ssa_10.x, ssa_11 vec1 32 ssa_13 = ishl ssa_10.y, ssa_9 vec1 32 ssa_13 = ishl ssa_10.y, ssa_9 vec3 32 ssa_14 = intrinsic load_work_group_id () () vec3 32 ssa_14 = intrinsic load_work_group_id () () vec3 32 ssa_15 = intrinsic load_uniform (ssa_3) (24, 12, 0) /* base=24 */ /* range=12 */ /* dest_type=invalid vec3 32 ssa_15 = intrinsic load_uniform (ssa_3) (24, 12, 0) /* base=24 */ /* range=12 */ /* dest_type=invalid vec1 32 ssa_16 = iadd ssa_14.x, ssa_15.x vec1 32 ssa_16 = iadd ssa_14.x, ssa_15.x vec1 32 ssa_17 = iadd ssa_14.y, ssa_15.y vec1 32 ssa_17 = iadd ssa_14.y, ssa_15.y vec1 32 ssa_18 = iadd ssa_14.z, ssa_15.z vec1 32 ssa_18 = iadd ssa_14.z, ssa_15.z vec1 32 ssa_19 = intrinsic load_subgroup_id () () vec1 32 ssa_19 = intrinsic load_subgroup_id () () vec1 32 ssa_20 = ishl ssa_19, ssa_7 vec1 32 ssa_20 = ishl ssa_19, ssa_7 vec1 32 ssa_21 = intrinsic load_subgroup_invocation () () vec1 32 ssa_21 = intrinsic load_subgroup_invocation () () vec1 32 ssa_22 = iadd ssa_21, ssa_20 vec1 32 ssa_22 = iadd ssa_21, ssa_20 vec1 32 ssa_23 = load_const (0x0000001f /* 0.000000 */) vec1 32 ssa_23 = load_const (0x0000001f /* 0.000000 */) vec1 32 ssa_24 = iand ssa_22, ssa_23 vec1 32 ssa_24 = iand ssa_22, ssa_23 vec1 32 ssa_25 = ushr ssa_22, ssa_11 vec1 32 ssa_25 = ushr ssa_22, ssa_11 vec1 32 ssa_26 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_26 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_27 = iand ssa_25, ssa_26 vec1 32 ssa_27 = iand ssa_25, ssa_26 vec1 32 ssa_28 = load_const (0x00000007 /* 0.000000 */) vec1 32 ssa_28 = load_const (0x00000007 /* 0.000000 */) vec1 32 ssa_29 = ushr ssa_22, ssa_28 vec1 32 ssa_29 = ushr ssa_22, ssa_28 vec1 32 ssa_30 = ishl ssa_16, ssa_11 vec1 32 ssa_30 = ishl ssa_16, ssa_11 vec1 32 ssa_31 = ishl ssa_17, ssa_9 vec1 32 ssa_31 = ishl ssa_17, ssa_9 vec1 32 ssa_32 = iadd ssa_30, ssa_24 vec1 32 ssa_32 = iadd ssa_30, ssa_24 vec1 32 ssa_33 = iadd ssa_31, ssa_27 vec1 32 ssa_33 = iadd ssa_31, ssa_27 vec1 32 ssa_34 = iadd ssa_18, ssa_29 vec1 32 ssa_34 = iadd ssa_18, ssa_29 vec1 32 ssa_35 = imul ssa_13, ssa_34 vec1 32 ssa_35 = imul ssa_13, ssa_34 vec1 32 ssa_36 = iadd ssa_35, ssa_33 vec1 32 ssa_36 = iadd ssa_35, ssa_33 vec1 32 ssa_37 = imul ssa_12, ssa_36 vec1 32 ssa_37 = imul ssa_12, ssa_36 vec1 32 ssa_38 = iadd ssa_37, ssa_32 vec1 32 ssa_38 = iadd ssa_37, ssa_32 vec1 32 ssa_39 = iadd ssa_21, ssa_0 vec1 32 ssa_39 = iadd ssa_21, ssa_0 vec1 32 ssa_40 = ineg ssa_21 vec1 32 ssa_40 = ineg ssa_21 vec1 32 ssa_41 = iadd ssa_23, ssa_40 vec1 32 ssa_41 = iadd ssa_23, ssa_40 vec1 32 ssa_42 = ushr ssa_2, ssa_41 vec1 32 ssa_42 = ushr ssa_2, ssa_41 vec1 32 ssa_43 = bit_count ssa_42 vec1 32 ssa_43 = bit_count ssa_42 vec1 32 ssa_44 = ieq32 ssa_39, ssa_43 vec1 32 ssa_44 = ieq32 ssa_39, ssa_43 vec1 32 ssa_45 = b2i32 ssa_44 vec1 32 ssa_45 = b2i32 ssa_44 vec1 32 ssa_46 = ior ssa_45, ssa_9 vec1 32 ssa_46 = ior ssa_45, ssa_9 vec1 32 ssa_47 = intrinsic ballot (ssa_8) () vec1 32 ssa_47 = intrinsic ballot (ssa_8) () vec1 32 ssa_48 = iand ssa_47, ssa_42 vec1 32 ssa_48 = iand ssa_47, ssa_42 vec1 32 ssa_49 = bit_count ssa_48 vec1 32 ssa_49 = bit_count ssa_48 vec1 32 ssa_50 = ult32 ssa_3, ssa_49 vec1 32 ssa_50 = ult32 ssa_3, ssa_49 vec1 32 ssa_51 = b32csel ssa_50, ssa_7, ssa_3 vec1 32 ssa_51 = b32csel ssa_50, ssa_7, ssa_3 vec1 32 ssa_52 = ior ssa_46, ssa_51 vec1 32 ssa_52 = ior ssa_46, ssa_51 r3 = ior ssa_52, ssa_6 r3 = ior ssa_52, ssa_6 r4 = mov ssa_3 r4 = mov ssa_3 /* succs: block_1 */ /* succs: block_1 */ loop { loop { block block_1: block block_1: /* preds: block_0 block_4 */ /* preds: block_0 block_4 */ vec1 32 ssa_56 = uge32 r4, ssa_4 vec1 32 ssa_56 = uge32 r4, ssa_4 /* succs: block_2 block_3 */ /* succs: block_2 block_3 */ if ssa_56 { if ssa_56 { block block_2: block block_2: /* preds: block_1 */ /* preds: block_1 */ break break /* succs: block_5 */ /* succs: block_5 */ } else { } else { block block_3: block block_3: /* preds: block_1 */ /* preds: block_1 */ /* succs: block_4 */ /* succs: block_4 */ } } block block_4: block block_4: /* preds: block_3 */ /* preds: block_3 */ vec1 32 ssa_57 = umin ssa_39, r4 vec1 32 ssa_57 = umin ssa_39, r4 vec1 32 ssa_58 = ineg ssa_57 vec1 32 ssa_58 = ineg ssa_57 vec1 32 ssa_59 = iadd ssa_39, ssa_58 vec1 32 ssa_59 = iadd ssa_39, ssa_58 vec1 32 ssa_60 = ishl ssa_2, r4 vec1 32 ssa_60 = ishl ssa_2, r4 vec1 32 ssa_61 = uge32 r4, ssa_5 vec1 32 ssa_61 = uge32 r4, ssa_5 vec1 32 ssa_62 = b32csel ssa_61, ssa_3, ssa_60 vec1 32 ssa_62 = b32csel ssa_61, ssa_3, ssa_60 vec1 32 ssa_63 = iand ssa_62, ssa_42 vec1 32 ssa_63 = iand ssa_62, ssa_42 vec1 32 ssa_64 = bit_count ssa_63 vec1 32 ssa_64 = bit_count ssa_63 vec1 32 ssa_65 = iand r3, ssa_1 vec1 32 ssa_65 = iand r3, ssa_1 vec1 32 ssa_66 = ine32 ssa_64, ssa_59 vec1 32 ssa_66 = ine32 ssa_64, ssa_59 r3 = b32csel ssa_66, ssa_65, r3 r3 = b32csel ssa_66, ssa_65, r3 r4 = iadd r4, ssa_0 r4 = iadd r4, ssa_0 /* succs: block_1 */ /* succs: block_1 */ } } block block_5: block block_5: /* preds: block_2 */ /* preds: block_2 */ vec1 32 ssa_69 = ishl ssa_38, ssa_9 vec1 32 ssa_69 = ishl ssa_38, ssa_9 intrinsic store_ssbo (r3, ssa_9, ssa_69) (1, 0, 4, 0) /* wrmask=x */ /* access=0 */ /* align_mul=4 */ /* alig intrinsic store_ssbo (r3, ssa_9, ssa_69) (1, 0, 4, 0) /* wrmask=x */ /* access=0 */ /* align_mul=4 */ /* alig /* succs: block_6 */ /* succs: block_6 */ block block_6: block block_6: } } Native code for unnamed compute shader (null) (sha1 c2f6b206737c1044b0ecfb551105957da5416dc7) | Native code for unnamed compute shader (null) (sha1 07f23b018d1e9473bbcacb94c2c25b0921a463d1) SIMD16 shader: 72 instructions. 1 loops. 1732 cycles. 0:0 spills:fills, 3 sends, scheduled with mode top-down. Promot | SIMD16 shader: 71 instructions. 1 loops. 1648 cycles. 0:0 spills:fills, 3 sends, scheduled with mode top-down. Promot START B0 (382 cycles) | START B0 (378 cycles) mov(8) g3<1>UW 0x76543210V { align1 WE_all 1Q }; mov(8) g3<1>UW 0x76543210V { align1 WE_all 1Q }; mov(16) g89<1>UD g0.1<0,1,0>UD { align1 1H compacted }; | mov(16) g87<1>UD g0.1<0,1,0>UD { align1 1H compacted }; mov(16) g91<1>UD g0.6<0,1,0>UD { align1 1H }; | mov(16) g89<1>UD g0.6<0,1,0>UD { align1 1H }; mov(16) g4<1>UD g0.7<0,1,0>UD { align1 1H }; mov(16) g4<1>UD g0.7<0,1,0>UD { align1 1H }; mov(16) g6<1>UD 0xffffffffUD { align1 1H compacted }; mov(16) g6<1>UD 0xffffffffUD { align1 1H compacted }; mov(16) g8<1>UD 0xffffffffUD { align1 1H compacted }; | mov(16) g91<1>UD 0x00000000UD { align1 1H compacted }; mov(16) g93<1>UD 0x00000000UD { align1 1H compacted }; < add(8) g3.8<1>UW g3<8,8,1>UW 0x0008UW { align1 WE_all 1Q }; add(8) g3.8<1>UW g3<8,8,1>UW 0x0008UW { align1 WE_all 1Q }; send(16) g10<1>UW g93<0,1,0>UD 0x04605800 | send(16) g8<1>UW g91<0,1,0>UD 0x04605800 dp data 1 MsgDesc: ( untyped surface read, Surface = 0, SIMD16, Mask = 0x8) mlen 2 rlen 6 dp data 1 MsgDesc: ( untyped surface read, Surface = 0, SIMD16, Mask = 0x8) mlen 2 rlen 6 add(16) g16<1>D g89<8,8,1>D g1.6<0,1,0>D { align1 1H compacted }; | add(16) g14<1>D g87<8,8,1>D g1.6<0,1,0>D { align1 1H compacted }; add(16) g18<1>D g91<8,8,1>D g1.7<0,1,0>D { align1 1H compacted }; | add(16) g16<1>D g89<8,8,1>D g1.7<0,1,0>D { align1 1H compacted }; add(16) g20<1>D g4<8,8,1>D g2<0,1,0>D { align1 1H compacted }; | add(16) g18<1>D g4<8,8,1>D g2<0,1,0>D { align1 1H compacted }; shl(16) g22<1>D g2.1<0,1,0>D 0x00000004UD { align1 1H }; | shl(16) g20<1>D g2.1<0,1,0>D 0x00000004UD { align1 1H }; mov(16) g24<1>D g3<8,8,1>UW { align1 1H }; | mov(16) g22<1>D g3<8,8,1>UW { align1 1H }; shl(16) g36<1>D g16<8,8,1>D 0x00000005UD { align1 1H }; | mov(1) g88.1<1>D 1D { align1 WE_all 1N }; shl(16) g38<1>D g18<8,8,1>D 0x00000002UD { align1 1H }; | shl(16) g34<1>D g14<8,8,1>D 0x00000005UD { align1 1H }; add(16) g26<1>D g24<8,8,1>D g22<8,8,1>D { align1 1H compacted }; | shl(16) g36<1>D g16<8,8,1>D 0x00000002UD { align1 1H }; add(16) g54<1>D g24<8,8,1>D 1D { align1 1H compacted }; | add(16) g24<1>D g22<8,8,1>D g20<8,8,1>D { align1 1H compacted }; add(16) g56<1>D -g24<8,8,1>D 31D { align1 1H compacted }; | add(16) g52<1>D g22<8,8,1>D 1D { align1 1H compacted }; mov(1) g68<2>UW 0x00000000UD { align1 WE_all 1N }; | add(16) g54<1>D -g22<8,8,1>D 31D { align1 1H compacted }; and(16) g28<1>UD g26<8,8,1>UD 0x0000001fUD { align1 1H compacted }; | mov(1) g5<2>UW 0x00000000UD { align1 WE_all 1N }; shr(16) g30<1>UD g26<8,8,1>UD 0x00000005UD { align1 1H compacted }; | and(16) g26<1>UD g24<8,8,1>UD 0x0000001fUD { align1 1H compacted }; shr(16) g34<1>UD g26<8,8,1>UD 0x00000007UD { align1 1H compacted }; | shr(16) g28<1>UD g24<8,8,1>UD 0x00000005UD { align1 1H compacted }; shr(16) g58<1>UD g6<8,8,1>UD g56<8,8,1>UD { align1 1H compacted }; | shr(16) g32<1>UD g24<8,8,1>UD 0x00000007UD { align1 1H compacted }; add(16) g40<1>D g36<8,8,1>D g28<8,8,1>D { align1 1H compacted }; | shr(16) g56<1>D -g88.1<0,1,0>D g54<8,8,1>D { align1 1H compacted }; and(16) g32<1>UD g30<8,8,1>UD 0x00000003UD { align1 1H compacted }; | add(16) g38<1>D g34<8,8,1>D g26<8,8,1>D { align1 1H compacted }; add(16) g44<1>D g20<8,8,1>D g34<8,8,1>D { align1 1H compacted }; | and(16) g30<1>UD g28<8,8,1>UD 0x00000003UD { align1 1H compacted }; cbit(16) g60<1>UD g58<8,8,1>UD { align1 1H compacted }; | add(16) g42<1>D g18<8,8,1>D g32<8,8,1>D { align1 1H compacted }; add(16) g42<1>D g38<8,8,1>D g32<8,8,1>D { align1 1H compacted }; | cbit(16) g58<1>UD g56<8,8,1>UD { align1 1H compacted }; cmp.z.f0.0(16) g62<1>D g54<8,8,1>D g60<8,8,1>D { align1 1H compacted }; | add(16) g40<1>D g36<8,8,1>D g30<8,8,1>D { align1 1H compacted }; mov(16) g64<1>D -g62<8,8,1>D { align1 1H compacted }; | cmp.z.f0.0(16) g60<1>D g52<8,8,1>D g58<8,8,1>D { align1 1H compacted }; or(16) g66<1>UD g64<8,8,1>UD 0x00000002UD { align1 1H compacted }; | mov(16) g62<1>D -g60<8,8,1>D { align1 1H compacted }; shl(16) g3<1>D g12<8,8,1>D 0x00000002UD { align1 1H }; | or(16) g64<1>UD g62<8,8,1>UD 0x00000002UD { align1 1H compacted }; shl(16) g1<1>D g10<8,8,1>D 0x00000005UD { align1 1H }; | shl(16) g3<1>D g10<8,8,1>D 0x00000002UD { align1 1H }; mul(16) g46<1>D g3<8,8,1>D g44<16,8,2>UW { align1 1H }; | shl(16) g1<1>D g8<8,8,1>D 0x00000005UD { align1 1H }; mul(16) g5<1>D g3<8,8,1>D g44.1<16,8,2>UW { align1 1H }; | mul(16) g8<1>D g3<8,8,1>D g42.1<16,8,2>UW { align1 1H }; add(16) g46.1<2>UW g46.1<16,8,2>UW g5<16,8,2>UW { align1 1H }; | mul(16) g44<1>D g3<8,8,1>D g42<16,8,2>UW { align1 1H }; add(16) g48<1>D g46<8,8,1>D g42<8,8,1>D { align1 1H compacted }; | add(16) g44.1<2>UW g44.1<16,8,2>UW g8<16,8,2>UW { align1 1H }; mul(16) g50<1>D g1<8,8,1>D g48<16,8,2>UW { align1 1H }; | add(16) g46<1>D g44<8,8,1>D g40<8,8,1>D { align1 1H compacted }; mul(16) g6<1>D g1<8,8,1>D g48.1<16,8,2>UW { align1 1H }; | mul(16) g48<1>D g1<8,8,1>D g46<16,8,2>UW { align1 1H }; add(16) g50.1<2>UW g50.1<16,8,2>UW g6<16,8,2>UW { align1 1H }; | mul(16) g9<1>D g1<8,8,1>D g46.1<16,8,2>UW { align1 1H }; add(16) g52<1>D g50<8,8,1>D g40<8,8,1>D { align1 1H compacted }; | add(16) g48.1<2>UW g48.1<16,8,2>UW g9<16,8,2>UW { align1 1H }; mov(1) f0<1>UW g68<0,1,0>UW { align1 WE_all 1N }; | add(16) g50<1>D g48<8,8,1>D g38<8,8,1>D { align1 1H compacted }; cmp.nz.f0.0(16) null<1>UD g8<8,8,1>UD 0x00000000UD { align1 1H compacted }; | mov(1) f0<1>UW g5<0,1,0>UW { align1 WE_all 1N }; mov(16) g68<1>UD f0<0,1,0>UW { align1 1H }; | cmp.nz.f0.0(16) null<1>UD g6<8,8,1>UD 0x00000000UD { align1 1H compacted }; mov(1) g1<1>UD 0x00000000UD { align1 WE_all 1N compacted }; | mov(16) g66<1>UD f0<0,1,0>UW { align1 1H }; > mov(1) g88<1>UD 0x00000000UD { align1 WE_all 1N compacted }; mov(16) g5<1>UD 0x00000000UD { align1 1H compacted }; mov(16) g5<1>UD 0x00000000UD { align1 1H compacted }; and(16) g70<1>UD g68<8,8,1>UD g58<8,8,1>UD { align1 1H compacted }; | and(16) g68<1>UD g66<8,8,1>UD g56<8,8,1>UD { align1 1H compacted }; cbit(16) g72<1>UD g70<8,8,1>UD { align1 1H compacted }; | cbit(16) g70<1>UD g68<8,8,1>UD { align1 1H compacted }; cmp.g.f0.0(16) null<1>UD g72<8,8,1>UD 0x00000000UD { align1 1H compacted }; | cmp.g.f0.0(16) null<1>UD g70<8,8,1>UD 0x00000000UD { align1 1H compacted }; (-f0.0) sel(16) g73<1>UD g1<0,1,0>UD 0x00000004UD { align1 1H }; | (-f0.0) sel(16) g71<1>UD g88<0,1,0>UD 0x00000004UD { align1 1H }; or(16) g75<1>UD g66<8,8,1>UD g73<8,8,1>UD { align1 1H compacted }; | or(16) g73<1>UD g64<8,8,1>UD g71<8,8,1>UD { align1 1H compacted }; or(16) g96<1>UD g75<8,8,1>UD 0x00000008UD { align1 1H compacted }; | or(16) g94<1>UD g73<8,8,1>UD 0x00000008UD { align1 1H compacted }; END B0 ->B1 END B0 ->B1 START B2 <-B1 <-B3 (260 cycles) START B2 <-B1 <-B3 (260 cycles) LABEL1: LABEL1: cmp.ge.f0.0(16) null<1>UD g5<8,8,1>UD 0x00000080UD { align1 1H compacted }; cmp.ge.f0.0(16) null<1>UD g5<8,8,1>UD 0x00000080UD { align1 1H compacted }; END B1 ->B2 ->B4 END B1 ->B2 ->B4 (+f0.0) break(16) JIP: LABEL0 UIP: LABEL0 { align1 1H }; (+f0.0) break(16) JIP: LABEL0 UIP: LABEL0 { align1 1H }; END B2 ->B1 ->B4 ->B3 END B2 ->B1 ->B4 ->B3 START B3 <-B2 (1060 cycles) | START B3 <-B2 (980 cycles) sel.l(16) g76<1>UD g54<8,8,1>UD g5<8,8,1>UD { align1 1H compacted }; | sel.l(16) g74<1>UD g52<8,8,1>UD g5<8,8,1>UD { align1 1H compacted }; mov(1) g1.1<1>D 1D { align1 WE_all 1N }; | shl(16) g78<1>D -g88.1<0,1,0>D g5<8,8,1>UD { align1 1H }; cmp.ge.f0.0(16) null<1>UD g5<8,8,1>UD 0x00000020UD { align1 1H compacted }; cmp.ge.f0.0(16) null<1>UD g5<8,8,1>UD 0x00000020UD { align1 1H compacted }; and(16) g88<1>UD g96<8,8,1>UD 0xfffffff7UD { align1 1H compacted }; | and(16) g86<1>UD g94<8,8,1>UD 0xfffffff7UD { align1 1H compacted }; add(16) g78<1>D g54<8,8,1>D -g76<8,8,1>D { align1 1H compacted }; < shl(16) g80<1>D -g1.1<0,1,0>D g5<8,8,1>UD { align1 1H }; < add(16) g5<1>D g5<8,8,1>D 1D { align1 1H compacted }; add(16) g5<1>D g5<8,8,1>D 1D { align1 1H compacted }; (-f0.0) sel(16) g82<1>UD g80<8,8,1>UD 0x00000000UD { align1 1H }; | add(16) g76<1>D g52<8,8,1>D -g74<8,8,1>D { align1 1H compacted }; and(16) g84<1>UD g82<8,8,1>UD g58<8,8,1>UD { align1 1H compacted }; | (-f0.0) sel(16) g80<1>UD g78<8,8,1>UD 0x00000000UD { align1 1H }; cbit(16) g86<1>UD g84<8,8,1>UD { align1 1H compacted }; | and(16) g82<1>UD g80<8,8,1>UD g56<8,8,1>UD { align1 1H compacted }; cmp.nz.f0.0(16) null<1>D g86<8,8,1>D g78<8,8,1>D { align1 1H compacted }; | cbit(16) g84<1>UD g82<8,8,1>UD { align1 1H compacted }; (+f0.0) sel(16) g96<1>UD g88<8,8,1>UD g96<8,8,1>UD { align1 1H compacted }; | cmp.nz.f0.0(16) null<1>D g84<8,8,1>D g76<8,8,1>D { align1 1H compacted }; > (+f0.0) sel(16) g94<1>UD g86<8,8,1>UD g94<8,8,1>UD { align1 1H compacted }; LABEL0: LABEL0: while(16) JIP: LABEL1 { align1 1H }; while(16) JIP: LABEL1 { align1 1H }; END B3 ->B2 END B3 ->B2 START B4 <-B1 <-B2 (30 cycles) START B4 <-B1 <-B2 (30 cycles) shl(16) g94<1>D g52<8,8,1>D 0x00000002UD { align1 1H }; | shl(16) g92<1>D g50<8,8,1>D 0x00000002UD { align1 1H }; sends(16) nullUD g94UD g96UD 0x04025e02 0x00000080 | sends(16) nullUD g92UD g94UD 0x04025e02 0x00000080 dp data 1 MsgDesc: ( DC untyped surface write, Surface = 2, SIMD16, Mask = 0xe) mlen 2 ex dp data 1 MsgDesc: ( DC untyped surface write, Surface = 2, SIMD16, Mask = 0xe) mlen 2 ex mov(8) g126<1>UD g0<8,8,1>UD { align1 WE_all 1Q compacted }; mov(8) g126<1>UD g0<8,8,1>UD { align1 WE_all 1Q compacted }; send(16) null<1>UW g126<8,8,1>UW 0x82000000 send(16) null<1>UW g126<8,8,1>UW 0x82000000 thread_spawner MsgDesc: mlen 1 rlen 0 { align1 WE_all 1H EOT }; thread_spawner MsgDesc: mlen 1 rlen 0 { align1 WE_all 1H EOT }; END B4 END B4 NIR (from SPIR-V) for MESA_SHADER_COMPUTE shader: NIR (from SPIR-V) for MESA_SHADER_COMPUTE shader: shader: MESA_SHADER_COMPUTE shader: MESA_SHADER_COMPUTE local-size: 1, 4, 32 local-size: 1, 4, 32 shared-size: 0 shared-size: 0 inputs: 0 inputs: 0 outputs: 0 outputs: 0 uniforms: 0 uniforms: 0 shared: 0 shared: 0 decl_var system INTERP_MODE_NONE uvec3 @0 decl_var system INTERP_MODE_NONE uvec3 @0 decl_var system INTERP_MODE_NONE uvec3 @1 decl_var system INTERP_MODE_NONE uvec3 @1 decl_var system INTERP_MODE_NONE uint @2 decl_var system INTERP_MODE_NONE uint @2 decl_var ssbo INTERP_MODE_NONE restrict block @3 (~0, 0, 0) decl_var ssbo INTERP_MODE_NONE restrict block @3 (~0, 0, 0) decl_function main (0 params) decl_function main (0 params) impl main { impl main { decl_var INTERP_MODE_NONE uvec3 @4 decl_var INTERP_MODE_NONE uvec3 @4 decl_var INTERP_MODE_NONE uint @5 decl_var INTERP_MODE_NONE uint @5 decl_var INTERP_MODE_NONE uvec4 @6 decl_var INTERP_MODE_NONE uvec4 @6 decl_var INTERP_MODE_NONE uvec4 @7 decl_var INTERP_MODE_NONE uvec4 @7 decl_var INTERP_MODE_NONE uint @8 decl_var INTERP_MODE_NONE uint @8 decl_var INTERP_MODE_NONE uint @9 decl_var INTERP_MODE_NONE uint @9 decl_var INTERP_MODE_NONE uint @10 decl_var INTERP_MODE_NONE uint @10 decl_var INTERP_MODE_NONE uint @11 decl_var INTERP_MODE_NONE uint @11 decl_var INTERP_MODE_NONE uvec4 @12 decl_var INTERP_MODE_NONE uvec4 @12 decl_var INTERP_MODE_NONE int @13 decl_var INTERP_MODE_NONE int @13 decl_var INTERP_MODE_NONE int @14 decl_var INTERP_MODE_NONE int @14 decl_var INTERP_MODE_NONE uint @15 decl_var INTERP_MODE_NONE uint @15 decl_var INTERP_MODE_NONE int @16 decl_var INTERP_MODE_NONE int @16 decl_var INTERP_MODE_NONE uint @17 decl_var INTERP_MODE_NONE uint @17 decl_var INTERP_MODE_NONE int @18 decl_var INTERP_MODE_NONE int @18 decl_var INTERP_MODE_NONE uint @19 decl_var INTERP_MODE_NONE uint @19 decl_var INTERP_MODE_NONE uint @20 decl_var INTERP_MODE_NONE uint @20 decl_var INTERP_MODE_NONE bool cont decl_var INTERP_MODE_NONE bool cont block block_0: block block_0: /* preds: */ /* preds: */ vec1 32 ssa_217 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_217 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_208 = load_const (0xfffffff7 /* -nan */) vec1 32 ssa_208 = load_const (0xfffffff7 /* -nan */) vec1 32 ssa_189 = load_const (0xffffffff /* -nan */) vec1 32 ssa_189 = load_const (0xffffffff /* -nan */) vec1 32 ssa_184 = load_const (0x00000060 /* 0.000000 */) vec1 32 ssa_184 = load_const (0x00000060 /* 0.000000 */) vec1 32 ssa_180 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_180 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_178 = load_const (0x00000060 /* 0.000000 */) vec1 32 ssa_178 = load_const (0x00000060 /* 0.000000 */) vec1 32 ssa_174 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_174 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_172 = load_const (0x00000080 /* 0.000000 */) vec1 32 ssa_172 = load_const (0x00000080 /* 0.000000 */) vec1 32 ssa_164 = load_const (0xffffffff /* -nan */) vec1 32 ssa_164 = load_const (0xffffffff /* -nan */) vec1 32 ssa_159 = load_const (0x00000040 /* 0.000000 */) vec1 32 ssa_159 = load_const (0x00000040 /* 0.000000 */) vec1 32 ssa_155 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_155 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_153 = load_const (0x00000040 /* 0.000000 */) vec1 32 ssa_153 = load_const (0x00000040 /* 0.000000 */) vec1 32 ssa_149 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_149 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_147 = load_const (0x00000060 /* 0.000000 */) vec1 32 ssa_147 = load_const (0x00000060 /* 0.000000 */) vec1 32 ssa_139 = load_const (0xffffffff /* -nan */) vec1 32 ssa_139 = load_const (0xffffffff /* -nan */) vec1 32 ssa_134 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_134 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_130 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_130 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_128 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_128 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_124 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_124 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_122 = load_const (0x00000040 /* 0.000000 */) vec1 32 ssa_122 = load_const (0x00000040 /* 0.000000 */) vec1 32 ssa_114 = load_const (0xffffffff /* -nan */) vec1 32 ssa_114 = load_const (0xffffffff /* -nan */) vec1 32 ssa_110 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_110 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_108 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_108 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_95 = load_const (0x00000080 /* 0.000000 */) vec1 32 ssa_95 = load_const (0x00000080 /* 0.000000 */) vec1 32 ssa_91 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_91 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_88 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_88 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_79 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_79 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_78 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_78 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_76 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_76 = load_const (0x00000000 /* 0.000000 */) vec1 1 ssa_73 = load_const (true) vec1 1 ssa_73 = load_const (true) vec1 32 ssa_66 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_66 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_65 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_65 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_63 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_63 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_53 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_53 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_52 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_52 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_43 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_43 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_39 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_39 = load_const (0x00000000 /* 0.000000 */) vec4 32 ssa_37 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, vec4 32 ssa_37 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, vec4 32 ssa_35 = load_const (0xffffffff /* -nan */, 0xffffffff /* -nan */, 0xffffffff /* -nan */, 0xffffffff vec4 32 ssa_35 = load_const (0xffffffff /* -nan */, 0xffffffff /* -nan */, 0xffffffff /* -nan */, 0xffffffff vec3 32 ssa_2 = load_const (0x00000001 /* 0.000000 */, 0x00000004 /* 0.000000 */, 0x00000020 /* 0.000000 */) vec3 32 ssa_2 = load_const (0x00000001 /* 0.000000 */, 0x00000004 /* 0.000000 */, 0x00000020 /* 0.000000 */) vec1 32 ssa_0 = deref_var &@0 (system uvec3) vec1 32 ssa_0 = deref_var &@0 (system uvec3) vec3 32 ssa_1 = intrinsic load_deref (ssa_0) (0) /* access=0 */ vec3 32 ssa_1 = intrinsic load_deref (ssa_0) (0) /* access=0 */ vec3 32 ssa_3 = imul ssa_1, ssa_2 vec3 32 ssa_3 = imul ssa_1, ssa_2 vec1 32 ssa_4 = deref_var &@4 (function_temp uvec3) vec1 32 ssa_4 = deref_var &@4 (function_temp uvec3) intrinsic store_deref (ssa_4, ssa_3) (7, 0) /* wrmask=xyz */ /* access=0 */ intrinsic store_deref (ssa_4, ssa_3) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_5 = deref_var &@4 (function_temp uvec3) vec1 32 ssa_5 = deref_var &@4 (function_temp uvec3) vec3 32 ssa_8 = intrinsic load_deref (ssa_5) (0) /* access=0 */ vec3 32 ssa_8 = intrinsic load_deref (ssa_5) (0) /* access=0 */ vec1 32 ssa_9 = mov ssa_8.x vec1 32 ssa_9 = mov ssa_8.x vec1 32 ssa_10 = deref_var &@4 (function_temp uvec3) vec1 32 ssa_10 = deref_var &@4 (function_temp uvec3) vec3 32 ssa_13 = intrinsic load_deref (ssa_10) (0) /* access=0 */ vec3 32 ssa_13 = intrinsic load_deref (ssa_10) (0) /* access=0 */ vec1 32 ssa_14 = mov ssa_13.y vec1 32 ssa_14 = mov ssa_13.y vec1 32 ssa_15 = deref_var &@1 (system uvec3) vec1 32 ssa_15 = deref_var &@1 (system uvec3) vec3 32 ssa_18 = intrinsic load_deref (ssa_15) (0) /* access=0 */ vec3 32 ssa_18 = intrinsic load_deref (ssa_15) (0) /* access=0 */ vec1 32 ssa_19 = mov ssa_18.z vec1 32 ssa_19 = mov ssa_18.z vec1 32 ssa_20 = imul ssa_14, ssa_19 vec1 32 ssa_20 = imul ssa_14, ssa_19 vec1 32 ssa_21 = deref_var &@1 (system uvec3) vec1 32 ssa_21 = deref_var &@1 (system uvec3) vec3 32 ssa_24 = intrinsic load_deref (ssa_21) (0) /* access=0 */ vec3 32 ssa_24 = intrinsic load_deref (ssa_21) (0) /* access=0 */ vec1 32 ssa_25 = mov ssa_24.y vec1 32 ssa_25 = mov ssa_24.y vec1 32 ssa_26 = iadd ssa_20, ssa_25 vec1 32 ssa_26 = iadd ssa_20, ssa_25 vec1 32 ssa_27 = imul ssa_9, ssa_26 vec1 32 ssa_27 = imul ssa_9, ssa_26 vec1 32 ssa_28 = deref_var &@1 (system uvec3) vec1 32 ssa_28 = deref_var &@1 (system uvec3) vec3 32 ssa_31 = intrinsic load_deref (ssa_28) (0) /* access=0 */ vec3 32 ssa_31 = intrinsic load_deref (ssa_28) (0) /* access=0 */ vec1 32 ssa_32 = mov ssa_31.x vec1 32 ssa_32 = mov ssa_31.x vec1 32 ssa_33 = iadd ssa_27, ssa_32 vec1 32 ssa_33 = iadd ssa_27, ssa_32 vec1 32 ssa_34 = deref_var &@5 (function_temp uint) vec1 32 ssa_34 = deref_var &@5 (function_temp uint) intrinsic store_deref (ssa_34, ssa_33) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_34, ssa_33) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_36 = deref_var &@6 (function_temp uvec4) vec1 32 ssa_36 = deref_var &@6 (function_temp uvec4) intrinsic store_deref (ssa_36, ssa_35) (15, 0) /* wrmask=xyzw */ /* access=0 */ intrinsic store_deref (ssa_36, ssa_35) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_38 = deref_var &@7 (function_temp uvec4) vec1 32 ssa_38 = deref_var &@7 (function_temp uvec4) intrinsic store_deref (ssa_38, ssa_37) (15, 0) /* wrmask=xyzw */ /* access=0 */ intrinsic store_deref (ssa_38, ssa_37) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_40 = deref_var &@8 (function_temp uint) vec1 32 ssa_40 = deref_var &@8 (function_temp uint) intrinsic store_deref (ssa_40, ssa_39) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_40, ssa_39) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_41 = deref_var &@2 (system uint) vec1 32 ssa_41 = deref_var &@2 (system uint) vec1 32 ssa_42 = intrinsic load_deref (ssa_41) (0) /* access=0 */ vec1 32 ssa_42 = intrinsic load_deref (ssa_41) (0) /* access=0 */ vec1 32 ssa_44 = iadd ssa_42, ssa_43 vec1 32 ssa_44 = iadd ssa_42, ssa_43 vec1 32 ssa_45 = deref_var &@9 (function_temp uint) vec1 32 ssa_45 = deref_var &@9 (function_temp uint) intrinsic store_deref (ssa_45, ssa_44) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_45, ssa_44) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_46 = deref_var &@9 (function_temp uint) vec1 32 ssa_46 = deref_var &@9 (function_temp uint) vec1 32 ssa_47 = intrinsic load_deref (ssa_46) (0) /* access=0 */ vec1 32 ssa_47 = intrinsic load_deref (ssa_46) (0) /* access=0 */ vec1 32 ssa_48 = deref_var &@6 (function_temp uvec4) vec1 32 ssa_48 = deref_var &@6 (function_temp uvec4) vec4 32 ssa_49 = intrinsic load_deref (ssa_48) (0) /* access=0 */ vec4 32 ssa_49 = intrinsic load_deref (ssa_48) (0) /* access=0 */ vec1 32 ssa_50 = intrinsic ballot_bit_count_inclusive (ssa_49) () vec1 32 ssa_50 = intrinsic ballot_bit_count_inclusive (ssa_49) () vec1 1 ssa_51 = ieq ssa_47, ssa_50 vec1 1 ssa_51 = ieq ssa_47, ssa_50 vec1 32 ssa_54 = bcsel ssa_51, ssa_53, ssa_52 vec1 32 ssa_54 = bcsel ssa_51, ssa_53, ssa_52 vec1 32 ssa_55 = mov ssa_54 vec1 32 ssa_55 = mov ssa_54 vec1 32 ssa_56 = deref_var &@8 (function_temp uint) vec1 32 ssa_56 = deref_var &@8 (function_temp uint) vec1 32 ssa_57 = intrinsic load_deref (ssa_56) (0) /* access=0 */ vec1 32 ssa_57 = intrinsic load_deref (ssa_56) (0) /* access=0 */ vec1 32 ssa_58 = ior ssa_57, ssa_55 vec1 32 ssa_58 = ior ssa_57, ssa_55 vec1 32 ssa_59 = deref_var &@8 (function_temp uint) vec1 32 ssa_59 = deref_var &@8 (function_temp uint) intrinsic store_deref (ssa_59, ssa_58) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_59, ssa_58) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_60 = deref_var &@7 (function_temp uvec4) vec1 32 ssa_60 = deref_var &@7 (function_temp uvec4) vec4 32 ssa_61 = intrinsic load_deref (ssa_60) (0) /* access=0 */ vec4 32 ssa_61 = intrinsic load_deref (ssa_60) (0) /* access=0 */ vec1 32 ssa_62 = intrinsic ballot_bit_count_inclusive (ssa_61) () vec1 32 ssa_62 = intrinsic ballot_bit_count_inclusive (ssa_61) () vec1 1 ssa_64 = ieq ssa_63, ssa_62 vec1 1 ssa_64 = ieq ssa_63, ssa_62 vec1 32 ssa_67 = bcsel ssa_64, ssa_66, ssa_65 vec1 32 ssa_67 = bcsel ssa_64, ssa_66, ssa_65 vec1 32 ssa_68 = mov ssa_67 vec1 32 ssa_68 = mov ssa_67 vec1 32 ssa_69 = deref_var &@8 (function_temp uint) vec1 32 ssa_69 = deref_var &@8 (function_temp uint) vec1 32 ssa_70 = intrinsic load_deref (ssa_69) (0) /* access=0 */ vec1 32 ssa_70 = intrinsic load_deref (ssa_69) (0) /* access=0 */ vec1 32 ssa_71 = ior ssa_70, ssa_68 vec1 32 ssa_71 = ior ssa_70, ssa_68 vec1 32 ssa_72 = deref_var &@8 (function_temp uint) vec1 32 ssa_72 = deref_var &@8 (function_temp uint) intrinsic store_deref (ssa_72, ssa_71) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_72, ssa_71) (1, 0) /* wrmask=x */ /* access=0 */ vec4 32 ssa_74 = intrinsic ballot (ssa_73) () vec4 32 ssa_74 = intrinsic ballot (ssa_73) () vec1 32 ssa_75 = intrinsic ballot_bit_count_inclusive (ssa_74) () vec1 32 ssa_75 = intrinsic ballot_bit_count_inclusive (ssa_74) () vec1 1 ssa_77 = ult ssa_76, ssa_75 vec1 1 ssa_77 = ult ssa_76, ssa_75 vec1 32 ssa_80 = bcsel ssa_77, ssa_79, ssa_78 vec1 32 ssa_80 = bcsel ssa_77, ssa_79, ssa_78 vec1 32 ssa_81 = mov ssa_80 vec1 32 ssa_81 = mov ssa_80 vec1 32 ssa_82 = deref_var &@8 (function_temp uint) vec1 32 ssa_82 = deref_var &@8 (function_temp uint) vec1 32 ssa_83 = intrinsic load_deref (ssa_82) (0) /* access=0 */ vec1 32 ssa_83 = intrinsic load_deref (ssa_82) (0) /* access=0 */ vec1 32 ssa_84 = ior ssa_83, ssa_81 vec1 32 ssa_84 = ior ssa_83, ssa_81 vec1 32 ssa_85 = deref_var &@8 (function_temp uint) vec1 32 ssa_85 = deref_var &@8 (function_temp uint) intrinsic store_deref (ssa_85, ssa_84) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_85, ssa_84) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_86 = deref_var &@8 (function_temp uint) vec1 32 ssa_86 = deref_var &@8 (function_temp uint) vec1 32 ssa_87 = intrinsic load_deref (ssa_86) (0) /* access=0 */ vec1 32 ssa_87 = intrinsic load_deref (ssa_86) (0) /* access=0 */ vec1 32 ssa_89 = ior ssa_87, ssa_88 vec1 32 ssa_89 = ior ssa_87, ssa_88 vec1 32 ssa_90 = deref_var &@8 (function_temp uint) vec1 32 ssa_90 = deref_var &@8 (function_temp uint) intrinsic store_deref (ssa_90, ssa_89) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_90, ssa_89) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_92 = deref_var &@10 (function_temp uint) vec1 32 ssa_92 = deref_var &@10 (function_temp uint) intrinsic store_deref (ssa_92, ssa_91) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_92, ssa_91) (1, 0) /* wrmask=x */ /* access=0 */ vec1 1 ssa_211 = load_const (false) vec1 1 ssa_211 = load_const (false) vec1 32 ssa_212 = deref_var &cont (function_temp bool) vec1 32 ssa_212 = deref_var &cont (function_temp bool) intrinsic store_deref (ssa_212, ssa_211) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_212, ssa_211) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_1 */ /* succs: block_1 */ loop { loop { block block_1: block block_1: /* preds: block_0 block_29 block_31 */ /* preds: block_0 block_29 block_31 */ vec1 32 ssa_213 = deref_var &cont (function_temp bool) vec1 32 ssa_213 = deref_var &cont (function_temp bool) vec1 1 ssa_214 = intrinsic load_deref (ssa_213) (0) /* access=0 */ vec1 1 ssa_214 = intrinsic load_deref (ssa_213) (0) /* access=0 */ /* succs: block_2 block_3 */ /* succs: block_2 block_3 */ if ssa_214 { if ssa_214 { block block_2: block block_2: /* preds: block_1 */ /* preds: block_1 */ vec1 32 ssa_215 = deref_var &@10 (function_temp uint) vec1 32 ssa_215 = deref_var &@10 (function_temp uint) vec1 32 ssa_216 = intrinsic load_deref (ssa_215) (0) /* access=0 */ vec1 32 ssa_216 = intrinsic load_deref (ssa_215) (0) /* access=0 */ vec1 32 ssa_218 = iadd ssa_216, ssa_217 vec1 32 ssa_218 = iadd ssa_216, ssa_217 vec1 32 ssa_219 = deref_var &@10 (function_temp uint) vec1 32 ssa_219 = deref_var &@10 (function_temp uint) intrinsic store_deref (ssa_219, ssa_218) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_219, ssa_218) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_4 */ /* succs: block_4 */ } else { } else { block block_3: block block_3: /* preds: block_1 */ /* preds: block_1 */ /* succs: block_4 */ /* succs: block_4 */ } } block block_4: block block_4: /* preds: block_2 block_3 */ /* preds: block_2 block_3 */ vec1 1 ssa_220 = load_const (true) vec1 1 ssa_220 = load_const (true) vec1 32 ssa_221 = deref_var &cont (function_temp bool) vec1 32 ssa_221 = deref_var &cont (function_temp bool) intrinsic store_deref (ssa_221, ssa_220) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_221, ssa_220) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_93 = deref_var &@10 (function_temp uint) vec1 32 ssa_93 = deref_var &@10 (function_temp uint) vec1 32 ssa_94 = intrinsic load_deref (ssa_93) (0) /* access=0 */ vec1 32 ssa_94 = intrinsic load_deref (ssa_93) (0) /* access=0 */ vec1 1 ssa_96 = ult ssa_94, ssa_95 vec1 1 ssa_96 = ult ssa_94, ssa_95 /* succs: block_5 block_30 */ /* succs: block_5 block_30 */ if ssa_96 { if ssa_96 { block block_5: block block_5: /* preds: block_4 */ /* preds: block_4 */ vec1 32 ssa_97 = deref_var &@9 (function_temp uint) vec1 32 ssa_97 = deref_var &@9 (function_temp uint) vec1 32 ssa_98 = intrinsic load_deref (ssa_97) (0) /* access=0 */ vec1 32 ssa_98 = intrinsic load_deref (ssa_97) (0) /* access=0 */ vec1 32 ssa_99 = deref_var &@9 (function_temp uint) vec1 32 ssa_99 = deref_var &@9 (function_temp uint) vec1 32 ssa_100 = intrinsic load_deref (ssa_99) (0) /* access=0 */ vec1 32 ssa_100 = intrinsic load_deref (ssa_99) (0) /* access=0 */ vec1 32 ssa_101 = deref_var &@10 (function_temp uint) vec1 32 ssa_101 = deref_var &@10 (function_temp uint) vec1 32 ssa_102 = intrinsic load_deref (ssa_101) (0) /* access=0 */ vec1 32 ssa_102 = intrinsic load_deref (ssa_101) (0) /* access=0 */ vec1 32 ssa_103 = umin ssa_100, ssa_102 vec1 32 ssa_103 = umin ssa_100, ssa_102 vec1 32 ssa_104 = isub ssa_98, ssa_103 vec1 32 ssa_104 = isub ssa_98, ssa_103 vec1 32 ssa_105 = deref_var &@11 (function_temp uint) vec1 32 ssa_105 = deref_var &@11 (function_temp uint) intrinsic store_deref (ssa_105, ssa_104) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_105, ssa_104) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_106 = deref_var &@10 (function_temp uint) vec1 32 ssa_106 = deref_var &@10 (function_temp uint) vec1 32 ssa_107 = intrinsic load_deref (ssa_106) (0) /* access=0 */ vec1 32 ssa_107 = intrinsic load_deref (ssa_106) (0) /* access=0 */ vec1 1 ssa_109 = uge ssa_107, ssa_108 vec1 1 ssa_109 = uge ssa_107, ssa_108 /* succs: block_6 block_7 */ /* succs: block_6 block_7 */ if ssa_109 { if ssa_109 { block block_6: block block_6: /* preds: block_5 */ /* preds: block_5 */ vec1 32 ssa_111 = deref_var &@13 (function_temp int) vec1 32 ssa_111 = deref_var &@13 (function_temp int) intrinsic store_deref (ssa_111, ssa_110) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_111, ssa_110) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_8 */ /* succs: block_8 */ } else { } else { block block_7: block block_7: /* preds: block_5 */ /* preds: block_5 */ vec1 32 ssa_112 = deref_var &@10 (function_temp uint) vec1 32 ssa_112 = deref_var &@10 (function_temp uint) vec1 32 ssa_113 = intrinsic load_deref (ssa_112) (0) /* access=0 */ vec1 32 ssa_113 = intrinsic load_deref (ssa_112) (0) /* access=0 */ vec1 32 ssa_115 = ishl ssa_114, ssa_113 vec1 32 ssa_115 = ishl ssa_114, ssa_113 vec1 32 ssa_116 = deref_var &@13 (function_temp int) vec1 32 ssa_116 = deref_var &@13 (function_temp int) intrinsic store_deref (ssa_116, ssa_115) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_116, ssa_115) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_8 */ /* succs: block_8 */ } } block block_8: block block_8: /* preds: block_6 block_7 */ /* preds: block_6 block_7 */ vec1 32 ssa_117 = deref_var &@13 (function_temp int) vec1 32 ssa_117 = deref_var &@13 (function_temp int) vec1 32 ssa_118 = intrinsic load_deref (ssa_117) (0) /* access=0 */ vec1 32 ssa_118 = intrinsic load_deref (ssa_117) (0) /* access=0 */ vec1 32 ssa_119 = mov ssa_118 vec1 32 ssa_119 = mov ssa_118 vec1 32 ssa_120 = deref_var &@10 (function_temp uint) vec1 32 ssa_120 = deref_var &@10 (function_temp uint) vec1 32 ssa_121 = intrinsic load_deref (ssa_120) (0) /* access=0 */ vec1 32 ssa_121 = intrinsic load_deref (ssa_120) (0) /* access=0 */ vec1 1 ssa_123 = uge ssa_121, ssa_122 vec1 1 ssa_123 = uge ssa_121, ssa_122 /* succs: block_9 block_10 */ /* succs: block_9 block_10 */ if ssa_123 { if ssa_123 { block block_9: block block_9: /* preds: block_8 */ /* preds: block_8 */ vec1 32 ssa_125 = deref_var &@14 (function_temp int) vec1 32 ssa_125 = deref_var &@14 (function_temp int) intrinsic store_deref (ssa_125, ssa_124) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_125, ssa_124) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_14 */ /* succs: block_14 */ } else { } else { block block_10: block block_10: /* preds: block_8 */ /* preds: block_8 */ vec1 32 ssa_126 = deref_var &@10 (function_temp uint) vec1 32 ssa_126 = deref_var &@10 (function_temp uint) vec1 32 ssa_127 = intrinsic load_deref (ssa_126) (0) /* access=0 */ vec1 32 ssa_127 = intrinsic load_deref (ssa_126) (0) /* access=0 */ vec1 1 ssa_129 = ult ssa_127, ssa_128 vec1 1 ssa_129 = ult ssa_127, ssa_128 /* succs: block_11 block_12 */ /* succs: block_11 block_12 */ if ssa_129 { if ssa_129 { block block_11: block block_11: /* preds: block_10 */ /* preds: block_10 */ vec1 32 ssa_131 = deref_var &@15 (function_temp uint) vec1 32 ssa_131 = deref_var &@15 (function_temp uint) intrinsic store_deref (ssa_131, ssa_130) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_131, ssa_130) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_13 */ /* succs: block_13 */ } else { } else { block block_12: block block_12: /* preds: block_10 */ /* preds: block_10 */ vec1 32 ssa_132 = deref_var &@10 (function_temp uint) vec1 32 ssa_132 = deref_var &@10 (function_temp uint) vec1 32 ssa_133 = intrinsic load_deref (ssa_132) (0) /* access=0 */ vec1 32 ssa_133 = intrinsic load_deref (ssa_132) (0) /* access=0 */ vec1 32 ssa_135 = isub ssa_133, ssa_134 vec1 32 ssa_135 = isub ssa_133, ssa_134 vec1 32 ssa_136 = deref_var &@15 (function_temp uint) vec1 32 ssa_136 = deref_var &@15 (function_temp uint) intrinsic store_deref (ssa_136, ssa_135) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_136, ssa_135) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_13 */ /* succs: block_13 */ } } block block_13: block block_13: /* preds: block_11 block_12 */ /* preds: block_11 block_12 */ vec1 32 ssa_137 = deref_var &@15 (function_temp uint) vec1 32 ssa_137 = deref_var &@15 (function_temp uint) vec1 32 ssa_138 = intrinsic load_deref (ssa_137) (0) /* access=0 */ vec1 32 ssa_138 = intrinsic load_deref (ssa_137) (0) /* access=0 */ vec1 32 ssa_140 = ishl ssa_139, ssa_138 vec1 32 ssa_140 = ishl ssa_139, ssa_138 vec1 32 ssa_141 = deref_var &@14 (function_temp int) vec1 32 ssa_141 = deref_var &@14 (function_temp int) intrinsic store_deref (ssa_141, ssa_140) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_141, ssa_140) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_14 */ /* succs: block_14 */ } } block block_14: block block_14: /* preds: block_9 block_13 */ /* preds: block_9 block_13 */ vec1 32 ssa_142 = deref_var &@14 (function_temp int) vec1 32 ssa_142 = deref_var &@14 (function_temp int) vec1 32 ssa_143 = intrinsic load_deref (ssa_142) (0) /* access=0 */ vec1 32 ssa_143 = intrinsic load_deref (ssa_142) (0) /* access=0 */ vec1 32 ssa_144 = mov ssa_143 vec1 32 ssa_144 = mov ssa_143 vec1 32 ssa_145 = deref_var &@10 (function_temp uint) vec1 32 ssa_145 = deref_var &@10 (function_temp uint) vec1 32 ssa_146 = intrinsic load_deref (ssa_145) (0) /* access=0 */ vec1 32 ssa_146 = intrinsic load_deref (ssa_145) (0) /* access=0 */ vec1 1 ssa_148 = uge ssa_146, ssa_147 vec1 1 ssa_148 = uge ssa_146, ssa_147 /* succs: block_15 block_16 */ /* succs: block_15 block_16 */ if ssa_148 { if ssa_148 { block block_15: block block_15: /* preds: block_14 */ /* preds: block_14 */ vec1 32 ssa_150 = deref_var &@16 (function_temp int) vec1 32 ssa_150 = deref_var &@16 (function_temp int) intrinsic store_deref (ssa_150, ssa_149) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_150, ssa_149) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_20 */ /* succs: block_20 */ } else { } else { block block_16: block block_16: /* preds: block_14 */ /* preds: block_14 */ vec1 32 ssa_151 = deref_var &@10 (function_temp uint) vec1 32 ssa_151 = deref_var &@10 (function_temp uint) vec1 32 ssa_152 = intrinsic load_deref (ssa_151) (0) /* access=0 */ vec1 32 ssa_152 = intrinsic load_deref (ssa_151) (0) /* access=0 */ vec1 1 ssa_154 = ult ssa_152, ssa_153 vec1 1 ssa_154 = ult ssa_152, ssa_153 /* succs: block_17 block_18 */ /* succs: block_17 block_18 */ if ssa_154 { if ssa_154 { block block_17: block block_17: /* preds: block_16 */ /* preds: block_16 */ vec1 32 ssa_156 = deref_var &@17 (function_temp uint) vec1 32 ssa_156 = deref_var &@17 (function_temp uint) intrinsic store_deref (ssa_156, ssa_155) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_156, ssa_155) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_19 */ /* succs: block_19 */ } else { } else { block block_18: block block_18: /* preds: block_16 */ /* preds: block_16 */ vec1 32 ssa_157 = deref_var &@10 (function_temp uint) vec1 32 ssa_157 = deref_var &@10 (function_temp uint) vec1 32 ssa_158 = intrinsic load_deref (ssa_157) (0) /* access=0 */ vec1 32 ssa_158 = intrinsic load_deref (ssa_157) (0) /* access=0 */ vec1 32 ssa_160 = isub ssa_158, ssa_159 vec1 32 ssa_160 = isub ssa_158, ssa_159 vec1 32 ssa_161 = deref_var &@17 (function_temp uint) vec1 32 ssa_161 = deref_var &@17 (function_temp uint) intrinsic store_deref (ssa_161, ssa_160) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_161, ssa_160) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_19 */ /* succs: block_19 */ } } block block_19: block block_19: /* preds: block_17 block_18 */ /* preds: block_17 block_18 */ vec1 32 ssa_162 = deref_var &@17 (function_temp uint) vec1 32 ssa_162 = deref_var &@17 (function_temp uint) vec1 32 ssa_163 = intrinsic load_deref (ssa_162) (0) /* access=0 */ vec1 32 ssa_163 = intrinsic load_deref (ssa_162) (0) /* access=0 */ vec1 32 ssa_165 = ishl ssa_164, ssa_163 vec1 32 ssa_165 = ishl ssa_164, ssa_163 vec1 32 ssa_166 = deref_var &@16 (function_temp int) vec1 32 ssa_166 = deref_var &@16 (function_temp int) intrinsic store_deref (ssa_166, ssa_165) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_166, ssa_165) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_20 */ /* succs: block_20 */ } } block block_20: block block_20: /* preds: block_15 block_19 */ /* preds: block_15 block_19 */ vec1 32 ssa_167 = deref_var &@16 (function_temp int) vec1 32 ssa_167 = deref_var &@16 (function_temp int) vec1 32 ssa_168 = intrinsic load_deref (ssa_167) (0) /* access=0 */ vec1 32 ssa_168 = intrinsic load_deref (ssa_167) (0) /* access=0 */ vec1 32 ssa_169 = mov ssa_168 vec1 32 ssa_169 = mov ssa_168 vec1 32 ssa_170 = deref_var &@10 (function_temp uint) vec1 32 ssa_170 = deref_var &@10 (function_temp uint) vec1 32 ssa_171 = intrinsic load_deref (ssa_170) (0) /* access=0 */ vec1 32 ssa_171 = intrinsic load_deref (ssa_170) (0) /* access=0 */ vec1 1 ssa_173 = uge ssa_171, ssa_172 vec1 1 ssa_173 = uge ssa_171, ssa_172 /* succs: block_21 block_22 */ /* succs: block_21 block_22 */ if ssa_173 { if ssa_173 { block block_21: block block_21: /* preds: block_20 */ /* preds: block_20 */ vec1 32 ssa_175 = deref_var &@18 (function_temp int) vec1 32 ssa_175 = deref_var &@18 (function_temp int) intrinsic store_deref (ssa_175, ssa_174) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_175, ssa_174) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_26 */ /* succs: block_26 */ } else { } else { block block_22: block block_22: /* preds: block_20 */ /* preds: block_20 */ vec1 32 ssa_176 = deref_var &@10 (function_temp uint) vec1 32 ssa_176 = deref_var &@10 (function_temp uint) vec1 32 ssa_177 = intrinsic load_deref (ssa_176) (0) /* access=0 */ vec1 32 ssa_177 = intrinsic load_deref (ssa_176) (0) /* access=0 */ vec1 1 ssa_179 = ult ssa_177, ssa_178 vec1 1 ssa_179 = ult ssa_177, ssa_178 /* succs: block_23 block_24 */ /* succs: block_23 block_24 */ if ssa_179 { if ssa_179 { block block_23: block block_23: /* preds: block_22 */ /* preds: block_22 */ vec1 32 ssa_181 = deref_var &@19 (function_temp uint) vec1 32 ssa_181 = deref_var &@19 (function_temp uint) intrinsic store_deref (ssa_181, ssa_180) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_181, ssa_180) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_25 */ /* succs: block_25 */ } else { } else { block block_24: block block_24: /* preds: block_22 */ /* preds: block_22 */ vec1 32 ssa_182 = deref_var &@10 (function_temp uint) vec1 32 ssa_182 = deref_var &@10 (function_temp uint) vec1 32 ssa_183 = intrinsic load_deref (ssa_182) (0) /* access=0 */ vec1 32 ssa_183 = intrinsic load_deref (ssa_182) (0) /* access=0 */ vec1 32 ssa_185 = isub ssa_183, ssa_184 vec1 32 ssa_185 = isub ssa_183, ssa_184 vec1 32 ssa_186 = deref_var &@19 (function_temp uint) vec1 32 ssa_186 = deref_var &@19 (function_temp uint) intrinsic store_deref (ssa_186, ssa_185) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_186, ssa_185) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_25 */ /* succs: block_25 */ } } block block_25: block block_25: /* preds: block_23 block_24 */ /* preds: block_23 block_24 */ vec1 32 ssa_187 = deref_var &@19 (function_temp uint) vec1 32 ssa_187 = deref_var &@19 (function_temp uint) vec1 32 ssa_188 = intrinsic load_deref (ssa_187) (0) /* access=0 */ vec1 32 ssa_188 = intrinsic load_deref (ssa_187) (0) /* access=0 */ vec1 32 ssa_190 = ishl ssa_189, ssa_188 vec1 32 ssa_190 = ishl ssa_189, ssa_188 vec1 32 ssa_191 = deref_var &@18 (function_temp int) vec1 32 ssa_191 = deref_var &@18 (function_temp int) intrinsic store_deref (ssa_191, ssa_190) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_191, ssa_190) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_26 */ /* succs: block_26 */ } } block block_26: block block_26: /* preds: block_21 block_25 */ /* preds: block_21 block_25 */ vec1 32 ssa_192 = deref_var &@18 (function_temp int) vec1 32 ssa_192 = deref_var &@18 (function_temp int) vec1 32 ssa_193 = intrinsic load_deref (ssa_192) (0) /* access=0 */ vec1 32 ssa_193 = intrinsic load_deref (ssa_192) (0) /* access=0 */ vec1 32 ssa_194 = mov ssa_193 vec1 32 ssa_194 = mov ssa_193 vec4 32 ssa_195 = vec4 ssa_119, ssa_144, ssa_169, ssa_194 vec4 32 ssa_195 = vec4 ssa_119, ssa_144, ssa_169, ssa_194 vec1 32 ssa_196 = deref_var &@12 (function_temp uvec4) vec1 32 ssa_196 = deref_var &@12 (function_temp uvec4) intrinsic store_deref (ssa_196, ssa_195) (15, 0) /* wrmask=xyzw */ /* access=0 */ intrinsic store_deref (ssa_196, ssa_195) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_197 = deref_var &@12 (function_temp uvec4) vec1 32 ssa_197 = deref_var &@12 (function_temp uvec4) vec4 32 ssa_198 = intrinsic load_deref (ssa_197) (0) /* access=0 */ vec4 32 ssa_198 = intrinsic load_deref (ssa_197) (0) /* access=0 */ vec1 32 ssa_199 = intrinsic ballot_bit_count_inclusive (ssa_198) () vec1 32 ssa_199 = intrinsic ballot_bit_count_inclusive (ssa_198) () vec1 32 ssa_200 = deref_var &@20 (function_temp uint) vec1 32 ssa_200 = deref_var &@20 (function_temp uint) intrinsic store_deref (ssa_200, ssa_199) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_200, ssa_199) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_201 = deref_var &@20 (function_temp uint) vec1 32 ssa_201 = deref_var &@20 (function_temp uint) vec1 32 ssa_202 = intrinsic load_deref (ssa_201) (0) /* access=0 */ vec1 32 ssa_202 = intrinsic load_deref (ssa_201) (0) /* access=0 */ vec1 32 ssa_203 = deref_var &@11 (function_temp uint) vec1 32 ssa_203 = deref_var &@11 (function_temp uint) vec1 32 ssa_204 = intrinsic load_deref (ssa_203) (0) /* access=0 */ vec1 32 ssa_204 = intrinsic load_deref (ssa_203) (0) /* access=0 */ vec1 1 ssa_205 = ine ssa_202, ssa_204 vec1 1 ssa_205 = ine ssa_202, ssa_204 /* succs: block_27 block_28 */ /* succs: block_27 block_28 */ if ssa_205 { if ssa_205 { block block_27: block block_27: /* preds: block_26 */ /* preds: block_26 */ vec1 32 ssa_206 = deref_var &@8 (function_temp uint) vec1 32 ssa_206 = deref_var &@8 (function_temp uint) vec1 32 ssa_207 = intrinsic load_deref (ssa_206) (0) /* access=0 */ vec1 32 ssa_207 = intrinsic load_deref (ssa_206) (0) /* access=0 */ vec1 32 ssa_209 = iand ssa_207, ssa_208 vec1 32 ssa_209 = iand ssa_207, ssa_208 vec1 32 ssa_210 = deref_var &@8 (function_temp uint) vec1 32 ssa_210 = deref_var &@8 (function_temp uint) intrinsic store_deref (ssa_210, ssa_209) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_210, ssa_209) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_29 */ /* succs: block_29 */ } else { } else { block block_28: block block_28: /* preds: block_26 */ /* preds: block_26 */ /* succs: block_29 */ /* succs: block_29 */ } } block block_29: block block_29: /* preds: block_27 block_28 */ /* preds: block_27 block_28 */ continue continue /* succs: block_1 */ /* succs: block_1 */ } else { } else { block block_30: block block_30: /* preds: block_4 */ /* preds: block_4 */ break break /* succs: block_32 */ /* succs: block_32 */ } } block block_31: block block_31: /* preds: */ /* preds: */ /* succs: block_1 */ /* succs: block_1 */ } } block block_32: block block_32: /* preds: block_30 */ /* preds: block_30 */ vec1 32 ssa_222 = deref_var &@5 (function_temp uint) vec1 32 ssa_222 = deref_var &@5 (function_temp uint) vec1 32 ssa_223 = intrinsic load_deref (ssa_222) (0) /* access=0 */ vec1 32 ssa_223 = intrinsic load_deref (ssa_222) (0) /* access=0 */ vec1 32 ssa_224 = deref_var &@8 (function_temp uint) vec1 32 ssa_224 = deref_var &@8 (function_temp uint) vec1 32 ssa_225 = intrinsic load_deref (ssa_224) (0) /* access=0 */ vec1 32 ssa_225 = intrinsic load_deref (ssa_224) (0) /* access=0 */ vec1 32 ssa_226 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_226 = load_const (0x00000000 /* 0.000000 */) vec1 64 ssa_227 = intrinsic vulkan_resource_index (ssa_226) (0, 0, 7) /* desc-set=0 */ /* binding=0 */ /* des vec1 64 ssa_227 = intrinsic vulkan_resource_index (ssa_226) (0, 0, 7) /* desc-set=0 */ /* binding=0 */ /* des vec1 64 ssa_228 = intrinsic load_vulkan_descriptor (ssa_227) (7) /* desc_type=SSBO */ vec1 64 ssa_228 = intrinsic load_vulkan_descriptor (ssa_227) (7) /* desc_type=SSBO */ vec1 64 ssa_229 = deref_cast (block *)ssa_228 (ssbo block) /* ptr_stride=0, align_mul=0, align_offset=0 */ vec1 64 ssa_229 = deref_cast (block *)ssa_228 (ssbo block) /* ptr_stride=0, align_mul=0, align_offset=0 */ vec1 64 ssa_230 = deref_struct &ssa_229->field0 (ssbo uint[]) /* &((block *)ssa_228)->field0 */ vec1 64 ssa_230 = deref_struct &ssa_229->field0 (ssbo uint[]) /* &((block *)ssa_228)->field0 */ vec1 64 ssa_231 = i2i64 ssa_223 vec1 64 ssa_231 = i2i64 ssa_223 vec1 64 ssa_232 = deref_array &(*ssa_230)[ssa_231] (ssbo uint) /* &((block *)ssa_228)->field0[ssa_231] */ vec1 64 ssa_232 = deref_array &(*ssa_230)[ssa_231] (ssbo uint) /* &((block *)ssa_228)->field0[ssa_231] */ intrinsic store_deref (ssa_232, ssa_225) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_232, ssa_225) (1, 0) /* wrmask=x */ /* access=0 */ return return /* succs: block_33 */ /* succs: block_33 */ block block_33: block block_33: } } NIR (SSA form) for compute shader: NIR (SSA form) for compute shader: shader: MESA_SHADER_COMPUTE shader: MESA_SHADER_COMPUTE local-size: 1, 4, 32 local-size: 1, 4, 32 shared-size: 0 shared-size: 0 inputs: 0 inputs: 0 outputs: 0 outputs: 0 uniforms: 36 uniforms: 36 shared: 0 shared: 0 decl_var ssbo INTERP_MODE_NONE restrict block @0 (~0, 0, 0) decl_var ssbo INTERP_MODE_NONE restrict block @0 (~0, 0, 0) decl_function main (0 params) decl_function main (0 params) impl main { impl main { block block_0: block block_0: /* preds: */ /* preds: */ vec1 32 ssa_0 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_0 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_1 = load_const (0xfffffff7 /* -nan */) vec1 32 ssa_1 = load_const (0xfffffff7 /* -nan */) vec1 32 ssa_2 = load_const (0xffffffff /* -nan */) vec1 32 ssa_2 = load_const (0xffffffff /* -nan */) vec1 32 ssa_3 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_4 = load_const (0x00000080 /* 0.000000 */) vec1 32 ssa_4 = load_const (0x00000080 /* 0.000000 */) vec1 32 ssa_5 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_5 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_6 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_6 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_7 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_7 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_8 = load_const (0xffffffff /* -nan */) vec1 32 ssa_8 = load_const (0xffffffff /* -nan */) vec1 32 ssa_9 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_9 = load_const (0x00000002 /* 0.000000 */) vec3 32 ssa_10 = intrinsic load_num_work_groups () () vec3 32 ssa_10 = intrinsic load_num_work_groups () () vec1 32 ssa_11 = ishl ssa_10.y, ssa_9 vec1 32 ssa_11 = ishl ssa_10.y, ssa_9 vec3 32 ssa_12 = intrinsic load_work_group_id () () vec3 32 ssa_12 = intrinsic load_work_group_id () () vec3 32 ssa_13 = intrinsic load_uniform (ssa_3) (24, 12, 0) /* base=24 */ /* range=12 */ /* dest_type=invalid vec3 32 ssa_13 = intrinsic load_uniform (ssa_3) (24, 12, 0) /* base=24 */ /* range=12 */ /* dest_type=invalid vec1 32 ssa_14 = iadd ssa_12.x, ssa_13.x vec1 32 ssa_14 = iadd ssa_12.x, ssa_13.x vec1 32 ssa_15 = iadd ssa_12.y, ssa_13.y vec1 32 ssa_15 = iadd ssa_12.y, ssa_13.y vec1 32 ssa_16 = iadd ssa_12.z, ssa_13.z vec1 32 ssa_16 = iadd ssa_12.z, ssa_13.z vec1 32 ssa_17 = intrinsic load_subgroup_id () () vec1 32 ssa_17 = intrinsic load_subgroup_id () () vec1 32 ssa_18 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_18 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_19 = ishl ssa_17, ssa_18 vec1 32 ssa_19 = ishl ssa_17, ssa_18 vec1 32 ssa_20 = intrinsic load_subgroup_invocation () () vec1 32 ssa_20 = intrinsic load_subgroup_invocation () () vec1 32 ssa_21 = iadd ssa_20, ssa_19 vec1 32 ssa_21 = iadd ssa_20, ssa_19 vec1 32 ssa_22 = iand ssa_21, ssa_18 vec1 32 ssa_22 = iand ssa_21, ssa_18 vec1 32 ssa_23 = ushr ssa_21, ssa_9 vec1 32 ssa_23 = ushr ssa_21, ssa_9 vec1 32 ssa_24 = ishl ssa_15, ssa_9 vec1 32 ssa_24 = ishl ssa_15, ssa_9 vec1 32 ssa_25 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_25 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_26 = ishl ssa_16, ssa_25 vec1 32 ssa_26 = ishl ssa_16, ssa_25 vec1 32 ssa_27 = iadd ssa_24, ssa_22 vec1 32 ssa_27 = iadd ssa_24, ssa_22 vec1 32 ssa_28 = iadd ssa_26, ssa_23 vec1 32 ssa_28 = iadd ssa_26, ssa_23 vec1 32 ssa_29 = imul ssa_11, ssa_28 vec1 32 ssa_29 = imul ssa_11, ssa_28 vec1 32 ssa_30 = iadd ssa_29, ssa_27 vec1 32 ssa_30 = iadd ssa_29, ssa_27 vec1 32 ssa_31 = imul ssa_10.x, ssa_30 vec1 32 ssa_31 = imul ssa_10.x, ssa_30 vec1 32 ssa_32 = iadd ssa_31, ssa_14 vec1 32 ssa_32 = iadd ssa_31, ssa_14 vec1 32 ssa_33 = iadd ssa_20, ssa_0 vec1 32 ssa_33 = iadd ssa_20, ssa_0 vec1 32 ssa_34 = load_const (0x0000001f /* 0.000000 */) vec1 32 ssa_34 = load_const (0x0000001f /* 0.000000 */) vec1 32 ssa_35 = ineg ssa_20 vec1 32 ssa_35 = ineg ssa_20 vec1 32 ssa_36 = iadd ssa_34, ssa_35 vec1 32 ssa_36 = iadd ssa_34, ssa_35 vec1 32 ssa_37 = ushr ssa_2, ssa_36 vec1 32 ssa_37 = ushr ssa_2, ssa_36 vec1 32 ssa_38 = bit_count ssa_37 vec1 32 ssa_38 = bit_count ssa_37 vec1 32 ssa_39 = ieq32 ssa_33, ssa_38 vec1 32 ssa_39 = ieq32 ssa_33, ssa_38 vec1 32 ssa_40 = b2i32 ssa_39 vec1 32 ssa_40 = b2i32 ssa_39 vec1 32 ssa_41 = ior ssa_40, ssa_9 vec1 32 ssa_41 = ior ssa_40, ssa_9 vec1 32 ssa_42 = intrinsic ballot (ssa_8) () vec1 32 ssa_42 = intrinsic ballot (ssa_8) () vec1 32 ssa_43 = iand ssa_42, ssa_37 vec1 32 ssa_43 = iand ssa_42, ssa_37 vec1 32 ssa_44 = bit_count ssa_43 vec1 32 ssa_44 = bit_count ssa_43 vec1 32 ssa_45 = ult32 ssa_3, ssa_44 vec1 32 ssa_45 = ult32 ssa_3, ssa_44 vec1 32 ssa_46 = b32csel ssa_45, ssa_7, ssa_3 vec1 32 ssa_46 = b32csel ssa_45, ssa_7, ssa_3 vec1 32 ssa_47 = ior ssa_41, ssa_46 vec1 32 ssa_47 = ior ssa_41, ssa_46 vec1 32 ssa_48 = ior ssa_47, ssa_6 vec1 32 ssa_48 = ior ssa_47, ssa_6 /* succs: block_1 */ /* succs: block_1 */ loop { loop { block block_1: block block_1: /* preds: block_0 block_4 */ /* preds: block_0 block_4 */ vec1 32 ssa_49 = phi block_0: ssa_48, block_4: ssa_62 vec1 32 ssa_49 = phi block_0: ssa_48, block_4: ssa_62 vec1 32 ssa_50 = phi block_0: ssa_3, block_4: ssa_63 vec1 32 ssa_50 = phi block_0: ssa_3, block_4: ssa_63 vec1 32 ssa_51 = uge32 ssa_50, ssa_4 vec1 32 ssa_51 = uge32 ssa_50, ssa_4 /* succs: block_2 block_3 */ /* succs: block_2 block_3 */ if ssa_51 { if ssa_51 { block block_2: block block_2: /* preds: block_1 */ /* preds: block_1 */ break break /* succs: block_5 */ /* succs: block_5 */ } else { } else { block block_3: block block_3: /* preds: block_1 */ /* preds: block_1 */ /* succs: block_4 */ /* succs: block_4 */ } } block block_4: block block_4: /* preds: block_3 */ /* preds: block_3 */ vec1 32 ssa_52 = umin ssa_33, ssa_50 vec1 32 ssa_52 = umin ssa_33, ssa_50 vec1 32 ssa_53 = ineg ssa_52 vec1 32 ssa_53 = ineg ssa_52 vec1 32 ssa_54 = iadd ssa_33, ssa_53 vec1 32 ssa_54 = iadd ssa_33, ssa_53 vec1 32 ssa_55 = ishl ssa_2, ssa_50 vec1 32 ssa_55 = ishl ssa_2, ssa_50 vec1 32 ssa_56 = uge32 ssa_50, ssa_5 vec1 32 ssa_56 = uge32 ssa_50, ssa_5 vec1 32 ssa_57 = b32csel ssa_56, ssa_3, ssa_55 vec1 32 ssa_57 = b32csel ssa_56, ssa_3, ssa_55 vec1 32 ssa_58 = iand ssa_57, ssa_37 vec1 32 ssa_58 = iand ssa_57, ssa_37 vec1 32 ssa_59 = bit_count ssa_58 vec1 32 ssa_59 = bit_count ssa_58 vec1 32 ssa_60 = iand ssa_49, ssa_1 vec1 32 ssa_60 = iand ssa_49, ssa_1 vec1 32 ssa_61 = ine32 ssa_59, ssa_54 vec1 32 ssa_61 = ine32 ssa_59, ssa_54 vec1 32 ssa_62 = b32csel ssa_61, ssa_60, ssa_49 vec1 32 ssa_62 = b32csel ssa_61, ssa_60, ssa_49 vec1 32 ssa_63 = iadd ssa_50, ssa_0 vec1 32 ssa_63 = iadd ssa_50, ssa_0 /* succs: block_1 */ /* succs: block_1 */ } } block block_5: block block_5: /* preds: block_2 */ /* preds: block_2 */ vec1 32 ssa_64 = ishl ssa_32, ssa_9 vec1 32 ssa_64 = ishl ssa_32, ssa_9 intrinsic store_ssbo (ssa_49, ssa_9, ssa_64) (1, 0, 4, 0) /* wrmask=x */ /* access=0 */ /* align_mul=4 */ /* intrinsic store_ssbo (ssa_49, ssa_9, ssa_64) (1, 0, 4, 0) /* wrmask=x */ /* access=0 */ /* align_mul=4 */ /* /* succs: block_6 */ /* succs: block_6 */ block block_6: block block_6: } } NIR (final form) for compute shader: NIR (final form) for compute shader: shader: MESA_SHADER_COMPUTE shader: MESA_SHADER_COMPUTE local-size: 1, 4, 32 local-size: 1, 4, 32 shared-size: 0 shared-size: 0 inputs: 0 inputs: 0 outputs: 0 outputs: 0 uniforms: 36 uniforms: 36 shared: 0 shared: 0 decl_var ssbo INTERP_MODE_NONE restrict block @0 (~0, 0, 0) decl_var ssbo INTERP_MODE_NONE restrict block @0 (~0, 0, 0) decl_function main (0 params) decl_function main (0 params) impl main { impl main { decl_reg vec1 32 r3 decl_reg vec1 32 r3 decl_reg vec1 32 r4 decl_reg vec1 32 r4 block block_0: block block_0: /* preds: */ /* preds: */ vec1 32 ssa_0 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_0 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_1 = load_const (0xfffffff7 /* -nan */) vec1 32 ssa_1 = load_const (0xfffffff7 /* -nan */) vec1 32 ssa_2 = load_const (0xffffffff /* -nan */) vec1 32 ssa_2 = load_const (0xffffffff /* -nan */) vec1 32 ssa_3 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_4 = load_const (0x00000080 /* 0.000000 */) vec1 32 ssa_4 = load_const (0x00000080 /* 0.000000 */) vec1 32 ssa_5 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_5 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_6 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_6 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_7 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_7 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_8 = load_const (0xffffffff /* -nan */) vec1 32 ssa_8 = load_const (0xffffffff /* -nan */) vec1 32 ssa_9 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_9 = load_const (0x00000002 /* 0.000000 */) vec3 32 ssa_10 = intrinsic load_num_work_groups () () vec3 32 ssa_10 = intrinsic load_num_work_groups () () vec1 32 ssa_11 = ishl ssa_10.y, ssa_9 vec1 32 ssa_11 = ishl ssa_10.y, ssa_9 vec3 32 ssa_12 = intrinsic load_work_group_id () () vec3 32 ssa_12 = intrinsic load_work_group_id () () vec3 32 ssa_13 = intrinsic load_uniform (ssa_3) (24, 12, 0) /* base=24 */ /* range=12 */ /* dest_type=invalid vec3 32 ssa_13 = intrinsic load_uniform (ssa_3) (24, 12, 0) /* base=24 */ /* range=12 */ /* dest_type=invalid vec1 32 ssa_14 = iadd ssa_12.x, ssa_13.x vec1 32 ssa_14 = iadd ssa_12.x, ssa_13.x vec1 32 ssa_15 = iadd ssa_12.y, ssa_13.y vec1 32 ssa_15 = iadd ssa_12.y, ssa_13.y vec1 32 ssa_16 = iadd ssa_12.z, ssa_13.z vec1 32 ssa_16 = iadd ssa_12.z, ssa_13.z vec1 32 ssa_17 = intrinsic load_subgroup_id () () vec1 32 ssa_17 = intrinsic load_subgroup_id () () vec1 32 ssa_18 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_18 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_19 = ishl ssa_17, ssa_18 vec1 32 ssa_19 = ishl ssa_17, ssa_18 vec1 32 ssa_20 = intrinsic load_subgroup_invocation () () vec1 32 ssa_20 = intrinsic load_subgroup_invocation () () vec1 32 ssa_21 = iadd ssa_20, ssa_19 vec1 32 ssa_21 = iadd ssa_20, ssa_19 vec1 32 ssa_22 = iand ssa_21, ssa_18 vec1 32 ssa_22 = iand ssa_21, ssa_18 vec1 32 ssa_23 = ushr ssa_21, ssa_9 vec1 32 ssa_23 = ushr ssa_21, ssa_9 vec1 32 ssa_24 = ishl ssa_15, ssa_9 vec1 32 ssa_24 = ishl ssa_15, ssa_9 vec1 32 ssa_25 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_25 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_26 = ishl ssa_16, ssa_25 vec1 32 ssa_26 = ishl ssa_16, ssa_25 vec1 32 ssa_27 = iadd ssa_24, ssa_22 vec1 32 ssa_27 = iadd ssa_24, ssa_22 vec1 32 ssa_28 = iadd ssa_26, ssa_23 vec1 32 ssa_28 = iadd ssa_26, ssa_23 vec1 32 ssa_29 = imul ssa_11, ssa_28 vec1 32 ssa_29 = imul ssa_11, ssa_28 vec1 32 ssa_30 = iadd ssa_29, ssa_27 vec1 32 ssa_30 = iadd ssa_29, ssa_27 vec1 32 ssa_31 = imul ssa_10.x, ssa_30 vec1 32 ssa_31 = imul ssa_10.x, ssa_30 vec1 32 ssa_32 = iadd ssa_31, ssa_14 vec1 32 ssa_32 = iadd ssa_31, ssa_14 vec1 32 ssa_33 = iadd ssa_20, ssa_0 vec1 32 ssa_33 = iadd ssa_20, ssa_0 vec1 32 ssa_34 = load_const (0x0000001f /* 0.000000 */) vec1 32 ssa_34 = load_const (0x0000001f /* 0.000000 */) vec1 32 ssa_35 = ineg ssa_20 vec1 32 ssa_35 = ineg ssa_20 vec1 32 ssa_36 = iadd ssa_34, ssa_35 vec1 32 ssa_36 = iadd ssa_34, ssa_35 vec1 32 ssa_37 = ushr ssa_2, ssa_36 vec1 32 ssa_37 = ushr ssa_2, ssa_36 vec1 32 ssa_38 = bit_count ssa_37 vec1 32 ssa_38 = bit_count ssa_37 vec1 32 ssa_39 = ieq32 ssa_33, ssa_38 vec1 32 ssa_39 = ieq32 ssa_33, ssa_38 vec1 32 ssa_40 = b2i32 ssa_39 vec1 32 ssa_40 = b2i32 ssa_39 vec1 32 ssa_41 = ior ssa_40, ssa_9 vec1 32 ssa_41 = ior ssa_40, ssa_9 vec1 32 ssa_42 = intrinsic ballot (ssa_8) () vec1 32 ssa_42 = intrinsic ballot (ssa_8) () vec1 32 ssa_43 = iand ssa_42, ssa_37 vec1 32 ssa_43 = iand ssa_42, ssa_37 vec1 32 ssa_44 = bit_count ssa_43 vec1 32 ssa_44 = bit_count ssa_43 vec1 32 ssa_45 = ult32 ssa_3, ssa_44 vec1 32 ssa_45 = ult32 ssa_3, ssa_44 vec1 32 ssa_46 = b32csel ssa_45, ssa_7, ssa_3 vec1 32 ssa_46 = b32csel ssa_45, ssa_7, ssa_3 vec1 32 ssa_47 = ior ssa_41, ssa_46 vec1 32 ssa_47 = ior ssa_41, ssa_46 r3 = ior ssa_47, ssa_6 r3 = ior ssa_47, ssa_6 r4 = mov ssa_3 r4 = mov ssa_3 /* succs: block_1 */ /* succs: block_1 */ loop { loop { block block_1: block block_1: /* preds: block_0 block_4 */ /* preds: block_0 block_4 */ vec1 32 ssa_51 = uge32 r4, ssa_4 vec1 32 ssa_51 = uge32 r4, ssa_4 /* succs: block_2 block_3 */ /* succs: block_2 block_3 */ if ssa_51 { if ssa_51 { block block_2: block block_2: /* preds: block_1 */ /* preds: block_1 */ break break /* succs: block_5 */ /* succs: block_5 */ } else { } else { block block_3: block block_3: /* preds: block_1 */ /* preds: block_1 */ /* succs: block_4 */ /* succs: block_4 */ } } block block_4: block block_4: /* preds: block_3 */ /* preds: block_3 */ vec1 32 ssa_52 = umin ssa_33, r4 vec1 32 ssa_52 = umin ssa_33, r4 vec1 32 ssa_53 = ineg ssa_52 vec1 32 ssa_53 = ineg ssa_52 vec1 32 ssa_54 = iadd ssa_33, ssa_53 vec1 32 ssa_54 = iadd ssa_33, ssa_53 vec1 32 ssa_55 = ishl ssa_2, r4 vec1 32 ssa_55 = ishl ssa_2, r4 vec1 32 ssa_56 = uge32 r4, ssa_5 vec1 32 ssa_56 = uge32 r4, ssa_5 vec1 32 ssa_57 = b32csel ssa_56, ssa_3, ssa_55 vec1 32 ssa_57 = b32csel ssa_56, ssa_3, ssa_55 vec1 32 ssa_58 = iand ssa_57, ssa_37 vec1 32 ssa_58 = iand ssa_57, ssa_37 vec1 32 ssa_59 = bit_count ssa_58 vec1 32 ssa_59 = bit_count ssa_58 vec1 32 ssa_60 = iand r3, ssa_1 vec1 32 ssa_60 = iand r3, ssa_1 vec1 32 ssa_61 = ine32 ssa_59, ssa_54 vec1 32 ssa_61 = ine32 ssa_59, ssa_54 r3 = b32csel ssa_61, ssa_60, r3 r3 = b32csel ssa_61, ssa_60, r3 r4 = iadd r4, ssa_0 r4 = iadd r4, ssa_0 /* succs: block_1 */ /* succs: block_1 */ } } block block_5: block block_5: /* preds: block_2 */ /* preds: block_2 */ vec1 32 ssa_64 = ishl ssa_32, ssa_9 vec1 32 ssa_64 = ishl ssa_32, ssa_9 intrinsic store_ssbo (r3, ssa_9, ssa_64) (1, 0, 4, 0) /* wrmask=x */ /* access=0 */ /* align_mul=4 */ /* alig intrinsic store_ssbo (r3, ssa_9, ssa_64) (1, 0, 4, 0) /* wrmask=x */ /* access=0 */ /* align_mul=4 */ /* alig /* succs: block_6 */ /* succs: block_6 */ block block_6: block block_6: } } NIR (SSA form) for compute shader: NIR (SSA form) for compute shader: shader: MESA_SHADER_COMPUTE shader: MESA_SHADER_COMPUTE local-size: 1, 4, 32 local-size: 1, 4, 32 shared-size: 0 shared-size: 0 inputs: 0 inputs: 0 outputs: 0 outputs: 0 uniforms: 36 uniforms: 36 shared: 0 shared: 0 decl_var ssbo INTERP_MODE_NONE restrict block @0 (~0, 0, 0) decl_var ssbo INTERP_MODE_NONE restrict block @0 (~0, 0, 0) decl_function main (0 params) decl_function main (0 params) impl main { impl main { block block_0: block block_0: /* preds: */ /* preds: */ vec1 32 ssa_0 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_0 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_1 = load_const (0xfffffff7 /* -nan */) vec1 32 ssa_1 = load_const (0xfffffff7 /* -nan */) vec1 32 ssa_2 = load_const (0xffffffff /* -nan */) vec1 32 ssa_2 = load_const (0xffffffff /* -nan */) vec1 32 ssa_3 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_4 = load_const (0x00000080 /* 0.000000 */) vec1 32 ssa_4 = load_const (0x00000080 /* 0.000000 */) vec1 32 ssa_5 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_5 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_6 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_6 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_7 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_7 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_8 = load_const (0xffffffff /* -nan */) vec1 32 ssa_8 = load_const (0xffffffff /* -nan */) vec1 32 ssa_9 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_9 = load_const (0x00000002 /* 0.000000 */) vec3 32 ssa_10 = intrinsic load_num_work_groups () () vec3 32 ssa_10 = intrinsic load_num_work_groups () () vec1 32 ssa_11 = ishl ssa_10.y, ssa_9 vec1 32 ssa_11 = ishl ssa_10.y, ssa_9 vec3 32 ssa_12 = intrinsic load_work_group_id () () vec3 32 ssa_12 = intrinsic load_work_group_id () () vec3 32 ssa_13 = intrinsic load_uniform (ssa_3) (24, 12, 0) /* base=24 */ /* range=12 */ /* dest_type=invalid vec3 32 ssa_13 = intrinsic load_uniform (ssa_3) (24, 12, 0) /* base=24 */ /* range=12 */ /* dest_type=invalid vec1 32 ssa_14 = iadd ssa_12.x, ssa_13.x vec1 32 ssa_14 = iadd ssa_12.x, ssa_13.x vec1 32 ssa_15 = iadd ssa_12.y, ssa_13.y vec1 32 ssa_15 = iadd ssa_12.y, ssa_13.y vec1 32 ssa_16 = iadd ssa_12.z, ssa_13.z vec1 32 ssa_16 = iadd ssa_12.z, ssa_13.z vec1 32 ssa_17 = intrinsic load_subgroup_id () () vec1 32 ssa_17 = intrinsic load_subgroup_id () () vec1 32 ssa_18 = ishl ssa_17, ssa_7 vec1 32 ssa_18 = ishl ssa_17, ssa_7 vec1 32 ssa_19 = intrinsic load_subgroup_invocation () () vec1 32 ssa_19 = intrinsic load_subgroup_invocation () () vec1 32 ssa_20 = iadd ssa_19, ssa_18 vec1 32 ssa_20 = iadd ssa_19, ssa_18 vec1 32 ssa_21 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_21 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_22 = iand ssa_20, ssa_21 vec1 32 ssa_22 = iand ssa_20, ssa_21 vec1 32 ssa_23 = ushr ssa_20, ssa_9 vec1 32 ssa_23 = ushr ssa_20, ssa_9 vec1 32 ssa_24 = ishl ssa_15, ssa_9 vec1 32 ssa_24 = ishl ssa_15, ssa_9 vec1 32 ssa_25 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_25 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_26 = ishl ssa_16, ssa_25 vec1 32 ssa_26 = ishl ssa_16, ssa_25 vec1 32 ssa_27 = iadd ssa_24, ssa_22 vec1 32 ssa_27 = iadd ssa_24, ssa_22 vec1 32 ssa_28 = iadd ssa_26, ssa_23 vec1 32 ssa_28 = iadd ssa_26, ssa_23 vec1 32 ssa_29 = imul ssa_11, ssa_28 vec1 32 ssa_29 = imul ssa_11, ssa_28 vec1 32 ssa_30 = iadd ssa_29, ssa_27 vec1 32 ssa_30 = iadd ssa_29, ssa_27 vec1 32 ssa_31 = imul ssa_10.x, ssa_30 vec1 32 ssa_31 = imul ssa_10.x, ssa_30 vec1 32 ssa_32 = iadd ssa_31, ssa_14 vec1 32 ssa_32 = iadd ssa_31, ssa_14 vec1 32 ssa_33 = iadd ssa_19, ssa_0 vec1 32 ssa_33 = iadd ssa_19, ssa_0 vec1 32 ssa_34 = load_const (0x0000001f /* 0.000000 */) vec1 32 ssa_34 = load_const (0x0000001f /* 0.000000 */) vec1 32 ssa_35 = ineg ssa_19 vec1 32 ssa_35 = ineg ssa_19 vec1 32 ssa_36 = iadd ssa_34, ssa_35 vec1 32 ssa_36 = iadd ssa_34, ssa_35 vec1 32 ssa_37 = ushr ssa_2, ssa_36 vec1 32 ssa_37 = ushr ssa_2, ssa_36 vec1 32 ssa_38 = bit_count ssa_37 vec1 32 ssa_38 = bit_count ssa_37 vec1 32 ssa_39 = ieq32 ssa_33, ssa_38 vec1 32 ssa_39 = ieq32 ssa_33, ssa_38 vec1 32 ssa_40 = b2i32 ssa_39 vec1 32 ssa_40 = b2i32 ssa_39 vec1 32 ssa_41 = ior ssa_40, ssa_9 vec1 32 ssa_41 = ior ssa_40, ssa_9 vec1 32 ssa_42 = intrinsic ballot (ssa_8) () vec1 32 ssa_42 = intrinsic ballot (ssa_8) () vec1 32 ssa_43 = iand ssa_42, ssa_37 vec1 32 ssa_43 = iand ssa_42, ssa_37 vec1 32 ssa_44 = bit_count ssa_43 vec1 32 ssa_44 = bit_count ssa_43 vec1 32 ssa_45 = ult32 ssa_3, ssa_44 vec1 32 ssa_45 = ult32 ssa_3, ssa_44 vec1 32 ssa_46 = b32csel ssa_45, ssa_7, ssa_3 vec1 32 ssa_46 = b32csel ssa_45, ssa_7, ssa_3 vec1 32 ssa_47 = ior ssa_41, ssa_46 vec1 32 ssa_47 = ior ssa_41, ssa_46 vec1 32 ssa_48 = ior ssa_47, ssa_6 vec1 32 ssa_48 = ior ssa_47, ssa_6 /* succs: block_1 */ /* succs: block_1 */ loop { loop { block block_1: block block_1: /* preds: block_0 block_4 */ /* preds: block_0 block_4 */ vec1 32 ssa_49 = phi block_0: ssa_48, block_4: ssa_62 vec1 32 ssa_49 = phi block_0: ssa_48, block_4: ssa_62 vec1 32 ssa_50 = phi block_0: ssa_3, block_4: ssa_63 vec1 32 ssa_50 = phi block_0: ssa_3, block_4: ssa_63 vec1 32 ssa_51 = uge32 ssa_50, ssa_4 vec1 32 ssa_51 = uge32 ssa_50, ssa_4 /* succs: block_2 block_3 */ /* succs: block_2 block_3 */ if ssa_51 { if ssa_51 { block block_2: block block_2: /* preds: block_1 */ /* preds: block_1 */ break break /* succs: block_5 */ /* succs: block_5 */ } else { } else { block block_3: block block_3: /* preds: block_1 */ /* preds: block_1 */ /* succs: block_4 */ /* succs: block_4 */ } } block block_4: block block_4: /* preds: block_3 */ /* preds: block_3 */ vec1 32 ssa_52 = umin ssa_33, ssa_50 vec1 32 ssa_52 = umin ssa_33, ssa_50 vec1 32 ssa_53 = ineg ssa_52 vec1 32 ssa_53 = ineg ssa_52 vec1 32 ssa_54 = iadd ssa_33, ssa_53 vec1 32 ssa_54 = iadd ssa_33, ssa_53 vec1 32 ssa_55 = ishl ssa_2, ssa_50 vec1 32 ssa_55 = ishl ssa_2, ssa_50 vec1 32 ssa_56 = uge32 ssa_50, ssa_5 vec1 32 ssa_56 = uge32 ssa_50, ssa_5 vec1 32 ssa_57 = b32csel ssa_56, ssa_3, ssa_55 vec1 32 ssa_57 = b32csel ssa_56, ssa_3, ssa_55 vec1 32 ssa_58 = iand ssa_57, ssa_37 vec1 32 ssa_58 = iand ssa_57, ssa_37 vec1 32 ssa_59 = bit_count ssa_58 vec1 32 ssa_59 = bit_count ssa_58 vec1 32 ssa_60 = iand ssa_49, ssa_1 vec1 32 ssa_60 = iand ssa_49, ssa_1 vec1 32 ssa_61 = ine32 ssa_59, ssa_54 vec1 32 ssa_61 = ine32 ssa_59, ssa_54 vec1 32 ssa_62 = b32csel ssa_61, ssa_60, ssa_49 vec1 32 ssa_62 = b32csel ssa_61, ssa_60, ssa_49 vec1 32 ssa_63 = iadd ssa_50, ssa_0 vec1 32 ssa_63 = iadd ssa_50, ssa_0 /* succs: block_1 */ /* succs: block_1 */ } } block block_5: block block_5: /* preds: block_2 */ /* preds: block_2 */ vec1 32 ssa_64 = ishl ssa_32, ssa_9 vec1 32 ssa_64 = ishl ssa_32, ssa_9 intrinsic store_ssbo (ssa_49, ssa_9, ssa_64) (1, 0, 4, 0) /* wrmask=x */ /* access=0 */ /* align_mul=4 */ /* intrinsic store_ssbo (ssa_49, ssa_9, ssa_64) (1, 0, 4, 0) /* wrmask=x */ /* access=0 */ /* align_mul=4 */ /* /* succs: block_6 */ /* succs: block_6 */ block block_6: block block_6: } } NIR (final form) for compute shader: NIR (final form) for compute shader: shader: MESA_SHADER_COMPUTE shader: MESA_SHADER_COMPUTE local-size: 1, 4, 32 local-size: 1, 4, 32 shared-size: 0 shared-size: 0 inputs: 0 inputs: 0 outputs: 0 outputs: 0 uniforms: 36 uniforms: 36 shared: 0 shared: 0 decl_var ssbo INTERP_MODE_NONE restrict block @0 (~0, 0, 0) decl_var ssbo INTERP_MODE_NONE restrict block @0 (~0, 0, 0) decl_function main (0 params) decl_function main (0 params) impl main { impl main { decl_reg vec1 32 r3 decl_reg vec1 32 r3 decl_reg vec1 32 r4 decl_reg vec1 32 r4 block block_0: block block_0: /* preds: */ /* preds: */ vec1 32 ssa_0 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_0 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_1 = load_const (0xfffffff7 /* -nan */) vec1 32 ssa_1 = load_const (0xfffffff7 /* -nan */) vec1 32 ssa_2 = load_const (0xffffffff /* -nan */) vec1 32 ssa_2 = load_const (0xffffffff /* -nan */) vec1 32 ssa_3 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_4 = load_const (0x00000080 /* 0.000000 */) vec1 32 ssa_4 = load_const (0x00000080 /* 0.000000 */) vec1 32 ssa_5 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_5 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_6 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_6 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_7 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_7 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_8 = load_const (0xffffffff /* -nan */) vec1 32 ssa_8 = load_const (0xffffffff /* -nan */) vec1 32 ssa_9 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_9 = load_const (0x00000002 /* 0.000000 */) vec3 32 ssa_10 = intrinsic load_num_work_groups () () vec3 32 ssa_10 = intrinsic load_num_work_groups () () vec1 32 ssa_11 = ishl ssa_10.y, ssa_9 vec1 32 ssa_11 = ishl ssa_10.y, ssa_9 vec3 32 ssa_12 = intrinsic load_work_group_id () () vec3 32 ssa_12 = intrinsic load_work_group_id () () vec3 32 ssa_13 = intrinsic load_uniform (ssa_3) (24, 12, 0) /* base=24 */ /* range=12 */ /* dest_type=invalid vec3 32 ssa_13 = intrinsic load_uniform (ssa_3) (24, 12, 0) /* base=24 */ /* range=12 */ /* dest_type=invalid vec1 32 ssa_14 = iadd ssa_12.x, ssa_13.x vec1 32 ssa_14 = iadd ssa_12.x, ssa_13.x vec1 32 ssa_15 = iadd ssa_12.y, ssa_13.y vec1 32 ssa_15 = iadd ssa_12.y, ssa_13.y vec1 32 ssa_16 = iadd ssa_12.z, ssa_13.z vec1 32 ssa_16 = iadd ssa_12.z, ssa_13.z vec1 32 ssa_17 = intrinsic load_subgroup_id () () vec1 32 ssa_17 = intrinsic load_subgroup_id () () vec1 32 ssa_18 = ishl ssa_17, ssa_7 vec1 32 ssa_18 = ishl ssa_17, ssa_7 vec1 32 ssa_19 = intrinsic load_subgroup_invocation () () vec1 32 ssa_19 = intrinsic load_subgroup_invocation () () vec1 32 ssa_20 = iadd ssa_19, ssa_18 vec1 32 ssa_20 = iadd ssa_19, ssa_18 vec1 32 ssa_21 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_21 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_22 = iand ssa_20, ssa_21 vec1 32 ssa_22 = iand ssa_20, ssa_21 vec1 32 ssa_23 = ushr ssa_20, ssa_9 vec1 32 ssa_23 = ushr ssa_20, ssa_9 vec1 32 ssa_24 = ishl ssa_15, ssa_9 vec1 32 ssa_24 = ishl ssa_15, ssa_9 vec1 32 ssa_25 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_25 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_26 = ishl ssa_16, ssa_25 vec1 32 ssa_26 = ishl ssa_16, ssa_25 vec1 32 ssa_27 = iadd ssa_24, ssa_22 vec1 32 ssa_27 = iadd ssa_24, ssa_22 vec1 32 ssa_28 = iadd ssa_26, ssa_23 vec1 32 ssa_28 = iadd ssa_26, ssa_23 vec1 32 ssa_29 = imul ssa_11, ssa_28 vec1 32 ssa_29 = imul ssa_11, ssa_28 vec1 32 ssa_30 = iadd ssa_29, ssa_27 vec1 32 ssa_30 = iadd ssa_29, ssa_27 vec1 32 ssa_31 = imul ssa_10.x, ssa_30 vec1 32 ssa_31 = imul ssa_10.x, ssa_30 vec1 32 ssa_32 = iadd ssa_31, ssa_14 vec1 32 ssa_32 = iadd ssa_31, ssa_14 vec1 32 ssa_33 = iadd ssa_19, ssa_0 vec1 32 ssa_33 = iadd ssa_19, ssa_0 vec1 32 ssa_34 = load_const (0x0000001f /* 0.000000 */) vec1 32 ssa_34 = load_const (0x0000001f /* 0.000000 */) vec1 32 ssa_35 = ineg ssa_19 vec1 32 ssa_35 = ineg ssa_19 vec1 32 ssa_36 = iadd ssa_34, ssa_35 vec1 32 ssa_36 = iadd ssa_34, ssa_35 vec1 32 ssa_37 = ushr ssa_2, ssa_36 vec1 32 ssa_37 = ushr ssa_2, ssa_36 vec1 32 ssa_38 = bit_count ssa_37 vec1 32 ssa_38 = bit_count ssa_37 vec1 32 ssa_39 = ieq32 ssa_33, ssa_38 vec1 32 ssa_39 = ieq32 ssa_33, ssa_38 vec1 32 ssa_40 = b2i32 ssa_39 vec1 32 ssa_40 = b2i32 ssa_39 vec1 32 ssa_41 = ior ssa_40, ssa_9 vec1 32 ssa_41 = ior ssa_40, ssa_9 vec1 32 ssa_42 = intrinsic ballot (ssa_8) () vec1 32 ssa_42 = intrinsic ballot (ssa_8) () vec1 32 ssa_43 = iand ssa_42, ssa_37 vec1 32 ssa_43 = iand ssa_42, ssa_37 vec1 32 ssa_44 = bit_count ssa_43 vec1 32 ssa_44 = bit_count ssa_43 vec1 32 ssa_45 = ult32 ssa_3, ssa_44 vec1 32 ssa_45 = ult32 ssa_3, ssa_44 vec1 32 ssa_46 = b32csel ssa_45, ssa_7, ssa_3 vec1 32 ssa_46 = b32csel ssa_45, ssa_7, ssa_3 vec1 32 ssa_47 = ior ssa_41, ssa_46 vec1 32 ssa_47 = ior ssa_41, ssa_46 r3 = ior ssa_47, ssa_6 r3 = ior ssa_47, ssa_6 r4 = mov ssa_3 r4 = mov ssa_3 /* succs: block_1 */ /* succs: block_1 */ loop { loop { block block_1: block block_1: /* preds: block_0 block_4 */ /* preds: block_0 block_4 */ vec1 32 ssa_51 = uge32 r4, ssa_4 vec1 32 ssa_51 = uge32 r4, ssa_4 /* succs: block_2 block_3 */ /* succs: block_2 block_3 */ if ssa_51 { if ssa_51 { block block_2: block block_2: /* preds: block_1 */ /* preds: block_1 */ break break /* succs: block_5 */ /* succs: block_5 */ } else { } else { block block_3: block block_3: /* preds: block_1 */ /* preds: block_1 */ /* succs: block_4 */ /* succs: block_4 */ } } block block_4: block block_4: /* preds: block_3 */ /* preds: block_3 */ vec1 32 ssa_52 = umin ssa_33, r4 vec1 32 ssa_52 = umin ssa_33, r4 vec1 32 ssa_53 = ineg ssa_52 vec1 32 ssa_53 = ineg ssa_52 vec1 32 ssa_54 = iadd ssa_33, ssa_53 vec1 32 ssa_54 = iadd ssa_33, ssa_53 vec1 32 ssa_55 = ishl ssa_2, r4 vec1 32 ssa_55 = ishl ssa_2, r4 vec1 32 ssa_56 = uge32 r4, ssa_5 vec1 32 ssa_56 = uge32 r4, ssa_5 vec1 32 ssa_57 = b32csel ssa_56, ssa_3, ssa_55 vec1 32 ssa_57 = b32csel ssa_56, ssa_3, ssa_55 vec1 32 ssa_58 = iand ssa_57, ssa_37 vec1 32 ssa_58 = iand ssa_57, ssa_37 vec1 32 ssa_59 = bit_count ssa_58 vec1 32 ssa_59 = bit_count ssa_58 vec1 32 ssa_60 = iand r3, ssa_1 vec1 32 ssa_60 = iand r3, ssa_1 vec1 32 ssa_61 = ine32 ssa_59, ssa_54 vec1 32 ssa_61 = ine32 ssa_59, ssa_54 r3 = b32csel ssa_61, ssa_60, r3 r3 = b32csel ssa_61, ssa_60, r3 r4 = iadd r4, ssa_0 r4 = iadd r4, ssa_0 /* succs: block_1 */ /* succs: block_1 */ } } block block_5: block block_5: /* preds: block_2 */ /* preds: block_2 */ vec1 32 ssa_64 = ishl ssa_32, ssa_9 vec1 32 ssa_64 = ishl ssa_32, ssa_9 intrinsic store_ssbo (r3, ssa_9, ssa_64) (1, 0, 4, 0) /* wrmask=x */ /* access=0 */ /* align_mul=4 */ /* alig intrinsic store_ssbo (r3, ssa_9, ssa_64) (1, 0, 4, 0) /* wrmask=x */ /* access=0 */ /* align_mul=4 */ /* alig /* succs: block_6 */ /* succs: block_6 */ block block_6: block block_6: } } Native code for unnamed compute shader (null) (sha1 e4e216f3dbbfc6bf630aafd9b3a9e9b1a0c4f4f7) | Native code for unnamed compute shader (null) (sha1 7537284b889f0920c4a00d14e4e43dd426dbc160) SIMD16 shader: 68 instructions. 1 loops. 1726 cycles. 0:0 spills:fills, 3 sends, scheduled with mode top-down. Promot | SIMD16 shader: 67 instructions. 1 loops. 1642 cycles. 0:0 spills:fills, 3 sends, scheduled with mode top-down. Promot START B0 (376 cycles) | START B0 (372 cycles) mov(8) g3<1>UW 0x76543210V { align1 WE_all 1Q }; mov(8) g3<1>UW 0x76543210V { align1 WE_all 1Q }; mov(16) g83<1>UD g0.1<0,1,0>UD { align1 1H compacted }; | mov(16) g81<1>UD g0.1<0,1,0>UD { align1 1H compacted }; mov(16) g85<1>UD g0.6<0,1,0>UD { align1 1H }; | mov(16) g83<1>UD g0.6<0,1,0>UD { align1 1H }; mov(16) g4<1>UD g0.7<0,1,0>UD { align1 1H }; mov(16) g4<1>UD g0.7<0,1,0>UD { align1 1H }; mov(16) g6<1>UD 0xffffffffUD { align1 1H compacted }; mov(16) g6<1>UD 0xffffffffUD { align1 1H compacted }; mov(16) g8<1>UD 0xffffffffUD { align1 1H compacted }; | mov(16) g85<1>UD 0x00000000UD { align1 1H compacted }; mov(16) g87<1>UD 0x00000000UD { align1 1H compacted }; < add(8) g3.8<1>UW g3<8,8,1>UW 0x0008UW { align1 WE_all 1Q }; add(8) g3.8<1>UW g3<8,8,1>UW 0x0008UW { align1 WE_all 1Q }; send(16) g10<1>UW g87<0,1,0>UD 0x04605800 | send(16) g8<1>UW g85<0,1,0>UD 0x04605800 dp data 1 MsgDesc: ( untyped surface read, Surface = 0, SIMD16, Mask = 0x8) mlen 2 rlen 6 dp data 1 MsgDesc: ( untyped surface read, Surface = 0, SIMD16, Mask = 0x8) mlen 2 rlen 6 add(16) g16<1>D g83<8,8,1>D g1.6<0,1,0>D { align1 1H compacted }; | add(16) g14<1>D g81<8,8,1>D g1.6<0,1,0>D { align1 1H compacted }; add(16) g18<1>D g85<8,8,1>D g1.7<0,1,0>D { align1 1H compacted }; | add(16) g16<1>D g83<8,8,1>D g1.7<0,1,0>D { align1 1H compacted }; add(16) g20<1>D g4<8,8,1>D g2<0,1,0>D { align1 1H compacted }; | add(16) g18<1>D g4<8,8,1>D g2<0,1,0>D { align1 1H compacted }; shl(16) g22<1>D g2.1<0,1,0>D 0x00000004UD { align1 1H }; | shl(16) g20<1>D g2.1<0,1,0>D 0x00000004UD { align1 1H }; mov(16) g24<1>D g3<8,8,1>UW { align1 1H }; | mov(16) g22<1>D g3<8,8,1>UW { align1 1H }; shl(16) g32<1>D g18<8,8,1>D 0x00000002UD { align1 1H }; | mov(1) g3.1<1>D 1D { align1 WE_all 1N }; shl(16) g34<1>D g20<8,8,1>D 0x00000005UD { align1 1H }; | shl(16) g30<1>D g16<8,8,1>D 0x00000002UD { align1 1H }; add(16) g26<1>D g24<8,8,1>D g22<8,8,1>D { align1 1H compacted }; | shl(16) g32<1>D g18<8,8,1>D 0x00000005UD { align1 1H }; add(16) g48<1>D g24<8,8,1>D 1D { align1 1H compacted }; | add(16) g24<1>D g22<8,8,1>D g20<8,8,1>D { align1 1H compacted }; add(16) g50<1>D -g24<8,8,1>D 31D { align1 1H compacted }; | add(16) g46<1>D g22<8,8,1>D 1D { align1 1H compacted }; mov(1) g62<2>UW 0x00000000UD { align1 WE_all 1N }; | add(16) g48<1>D -g22<8,8,1>D 31D { align1 1H compacted }; and(16) g28<1>UD g26<8,8,1>UD 0x00000003UD { align1 1H compacted }; | mov(1) g60<2>UW 0x00000000UD { align1 WE_all 1N }; shr(16) g30<1>UD g26<8,8,1>UD 0x00000002UD { align1 1H compacted }; | and(16) g26<1>UD g24<8,8,1>UD 0x00000003UD { align1 1H compacted }; shr(16) g52<1>UD g6<8,8,1>UD g50<8,8,1>UD { align1 1H compacted }; | shr(16) g28<1>UD g24<8,8,1>UD 0x00000002UD { align1 1H compacted }; > shr(16) g50<1>D -g3.1<0,1,0>D g48<8,8,1>D { align1 1H compacted }; > add(16) g34<1>D g30<8,8,1>D g26<8,8,1>D { align1 1H compacted }; add(16) g36<1>D g32<8,8,1>D g28<8,8,1>D { align1 1H compacted }; add(16) g36<1>D g32<8,8,1>D g28<8,8,1>D { align1 1H compacted }; add(16) g38<1>D g34<8,8,1>D g30<8,8,1>D { align1 1H compacted }; | cbit(16) g52<1>UD g50<8,8,1>UD { align1 1H compacted }; cbit(16) g54<1>UD g52<8,8,1>UD { align1 1H compacted }; | cmp.z.f0.0(16) g54<1>D g46<8,8,1>D g52<8,8,1>D { align1 1H compacted }; cmp.z.f0.0(16) g56<1>D g48<8,8,1>D g54<8,8,1>D { align1 1H compacted }; | mov(16) g56<1>D -g54<8,8,1>D { align1 1H compacted }; mov(16) g58<1>D -g56<8,8,1>D { align1 1H compacted }; | or(16) g58<1>UD g56<8,8,1>UD 0x00000002UD { align1 1H compacted }; or(16) g60<1>UD g58<8,8,1>UD 0x00000002UD { align1 1H compacted }; | shl(16) g1<1>D g10<8,8,1>D 0x00000002UD { align1 1H }; shl(16) g1<1>D g12<8,8,1>D 0x00000002UD { align1 1H }; | mul(16) g38<1>D g1<8,8,1>D g36<16,8,2>UW { align1 1H }; mul(16) g40<1>D g1<8,8,1>D g38<16,8,2>UW { align1 1H }; | mul(16) g4<1>D g1<8,8,1>D g36.1<16,8,2>UW { align1 1H }; mul(16) g3<1>D g1<8,8,1>D g38.1<16,8,2>UW { align1 1H }; | add(16) g38.1<2>UW g38.1<16,8,2>UW g4<16,8,2>UW { align1 1H }; add(16) g40.1<2>UW g40.1<16,8,2>UW g3<16,8,2>UW { align1 1H }; | add(16) g40<1>D g38<8,8,1>D g34<8,8,1>D { align1 1H compacted }; add(16) g42<1>D g40<8,8,1>D g36<8,8,1>D { align1 1H compacted }; | mul(16) g42<1>D g8<8,8,1>D g40<16,8,2>UW { align1 1H }; mul(16) g44<1>D g10<8,8,1>D g42<16,8,2>UW { align1 1H }; | mul(16) g16<1>D g8<8,8,1>D g40.1<16,8,2>UW { align1 1H }; mul(16) g4<1>D g10<8,8,1>D g42.1<16,8,2>UW { align1 1H }; | add(16) g42.1<2>UW g42.1<16,8,2>UW g16<16,8,2>UW { align1 1H }; add(16) g44.1<2>UW g44.1<16,8,2>UW g4<16,8,2>UW { align1 1H }; | add(16) g44<1>D g42<8,8,1>D g14<8,8,1>D { align1 1H compacted }; add(16) g46<1>D g44<8,8,1>D g16<8,8,1>D { align1 1H compacted }; | mov(1) f0<1>UW g60<0,1,0>UW { align1 WE_all 1N }; mov(1) f0<1>UW g62<0,1,0>UW { align1 WE_all 1N }; | cmp.nz.f0.0(16) null<1>UD g6<8,8,1>UD 0x00000000UD { align1 1H compacted }; cmp.nz.f0.0(16) null<1>UD g8<8,8,1>UD 0x00000000UD { align1 1H compacted }; | mov(16) g60<1>UD f0<0,1,0>UW { align1 1H }; mov(16) g62<1>UD f0<0,1,0>UW { align1 1H }; | mov(1) g3<1>UD 0x00000000UD { align1 WE_all 1N compacted }; mov(1) g1<1>UD 0x00000000UD { align1 WE_all 1N compacted }; < mov(16) g5<1>UD 0x00000000UD { align1 1H compacted }; mov(16) g5<1>UD 0x00000000UD { align1 1H compacted }; and(16) g64<1>UD g62<8,8,1>UD g52<8,8,1>UD { align1 1H compacted }; | and(16) g62<1>UD g60<8,8,1>UD g50<8,8,1>UD { align1 1H compacted }; cbit(16) g66<1>UD g64<8,8,1>UD { align1 1H compacted }; | cbit(16) g64<1>UD g62<8,8,1>UD { align1 1H compacted }; cmp.g.f0.0(16) null<1>UD g66<8,8,1>UD 0x00000000UD { align1 1H compacted }; | cmp.g.f0.0(16) null<1>UD g64<8,8,1>UD 0x00000000UD { align1 1H compacted }; (-f0.0) sel(16) g67<1>UD g1<0,1,0>UD 0x00000004UD { align1 1H }; | (-f0.0) sel(16) g65<1>UD g3<0,1,0>UD 0x00000004UD { align1 1H }; or(16) g69<1>UD g60<8,8,1>UD g67<8,8,1>UD { align1 1H compacted }; | or(16) g67<1>UD g58<8,8,1>UD g65<8,8,1>UD { align1 1H compacted }; or(16) g90<1>UD g69<8,8,1>UD 0x00000008UD { align1 1H compacted }; | or(16) g88<1>UD g67<8,8,1>UD 0x00000008UD { align1 1H compacted }; END B0 ->B1 END B0 ->B1 START B2 <-B1 <-B3 (260 cycles) START B2 <-B1 <-B3 (260 cycles) LABEL1: LABEL1: cmp.ge.f0.0(16) null<1>UD g5<8,8,1>UD 0x00000080UD { align1 1H compacted }; cmp.ge.f0.0(16) null<1>UD g5<8,8,1>UD 0x00000080UD { align1 1H compacted }; END B1 ->B2 ->B4 END B1 ->B2 ->B4 (+f0.0) break(16) JIP: LABEL0 UIP: LABEL0 { align1 1H }; (+f0.0) break(16) JIP: LABEL0 UIP: LABEL0 { align1 1H }; END B2 ->B1 ->B4 ->B3 END B2 ->B1 ->B4 ->B3 START B3 <-B2 (1060 cycles) | START B3 <-B2 (980 cycles) sel.l(16) g70<1>UD g48<8,8,1>UD g5<8,8,1>UD { align1 1H compacted }; | sel.l(16) g68<1>UD g46<8,8,1>UD g5<8,8,1>UD { align1 1H compacted }; mov(1) g1.1<1>D 1D { align1 WE_all 1N }; | shl(16) g72<1>D -g3.1<0,1,0>D g5<8,8,1>UD { align1 1H }; cmp.ge.f0.0(16) null<1>UD g5<8,8,1>UD 0x00000020UD { align1 1H compacted }; cmp.ge.f0.0(16) null<1>UD g5<8,8,1>UD 0x00000020UD { align1 1H compacted }; and(16) g82<1>UD g90<8,8,1>UD 0xfffffff7UD { align1 1H compacted }; | and(16) g80<1>UD g88<8,8,1>UD 0xfffffff7UD { align1 1H compacted }; add(16) g72<1>D g48<8,8,1>D -g70<8,8,1>D { align1 1H compacted }; < shl(16) g74<1>D -g1.1<0,1,0>D g5<8,8,1>UD { align1 1H }; < add(16) g5<1>D g5<8,8,1>D 1D { align1 1H compacted }; add(16) g5<1>D g5<8,8,1>D 1D { align1 1H compacted }; (-f0.0) sel(16) g76<1>UD g74<8,8,1>UD 0x00000000UD { align1 1H }; | add(16) g70<1>D g46<8,8,1>D -g68<8,8,1>D { align1 1H compacted }; and(16) g78<1>UD g76<8,8,1>UD g52<8,8,1>UD { align1 1H compacted }; | (-f0.0) sel(16) g74<1>UD g72<8,8,1>UD 0x00000000UD { align1 1H }; cbit(16) g80<1>UD g78<8,8,1>UD { align1 1H compacted }; | and(16) g76<1>UD g74<8,8,1>UD g50<8,8,1>UD { align1 1H compacted }; cmp.nz.f0.0(16) null<1>D g80<8,8,1>D g72<8,8,1>D { align1 1H compacted }; | cbit(16) g78<1>UD g76<8,8,1>UD { align1 1H compacted }; (+f0.0) sel(16) g90<1>UD g82<8,8,1>UD g90<8,8,1>UD { align1 1H compacted }; | cmp.nz.f0.0(16) null<1>D g78<8,8,1>D g70<8,8,1>D { align1 1H compacted }; > (+f0.0) sel(16) g88<1>UD g80<8,8,1>UD g88<8,8,1>UD { align1 1H compacted }; LABEL0: LABEL0: while(16) JIP: LABEL1 { align1 1H }; while(16) JIP: LABEL1 { align1 1H }; END B3 ->B2 END B3 ->B2 START B4 <-B1 <-B2 (30 cycles) START B4 <-B1 <-B2 (30 cycles) shl(16) g88<1>D g46<8,8,1>D 0x00000002UD { align1 1H }; | shl(16) g86<1>D g44<8,8,1>D 0x00000002UD { align1 1H }; sends(16) nullUD g88UD g90UD 0x04025e02 0x00000080 | sends(16) nullUD g86UD g88UD 0x04025e02 0x00000080 dp data 1 MsgDesc: ( DC untyped surface write, Surface = 2, SIMD16, Mask = 0xe) mlen 2 ex dp data 1 MsgDesc: ( DC untyped surface write, Surface = 2, SIMD16, Mask = 0xe) mlen 2 ex mov(8) g126<1>UD g0<8,8,1>UD { align1 WE_all 1Q compacted }; mov(8) g126<1>UD g0<8,8,1>UD { align1 WE_all 1Q compacted }; send(16) null<1>UW g126<8,8,1>UW 0x82000000 send(16) null<1>UW g126<8,8,1>UW 0x82000000 thread_spawner MsgDesc: mlen 1 rlen 0 { align1 WE_all 1H EOT }; thread_spawner MsgDesc: mlen 1 rlen 0 { align1 WE_all 1H EOT }; END B4 END B4 NIR (from SPIR-V) for MESA_SHADER_COMPUTE shader: NIR (from SPIR-V) for MESA_SHADER_COMPUTE shader: shader: MESA_SHADER_COMPUTE shader: MESA_SHADER_COMPUTE local-size: 3, 5, 7 local-size: 3, 5, 7 shared-size: 0 shared-size: 0 inputs: 0 inputs: 0 outputs: 0 outputs: 0 uniforms: 0 uniforms: 0 shared: 0 shared: 0 decl_var system INTERP_MODE_NONE uvec3 @0 decl_var system INTERP_MODE_NONE uvec3 @0 decl_var system INTERP_MODE_NONE uvec3 @1 decl_var system INTERP_MODE_NONE uvec3 @1 decl_var system INTERP_MODE_NONE uint @2 decl_var system INTERP_MODE_NONE uint @2 decl_var ssbo INTERP_MODE_NONE restrict block @3 (~0, 0, 0) decl_var ssbo INTERP_MODE_NONE restrict block @3 (~0, 0, 0) decl_function main (0 params) decl_function main (0 params) impl main { impl main { decl_var INTERP_MODE_NONE uvec3 @4 decl_var INTERP_MODE_NONE uvec3 @4 decl_var INTERP_MODE_NONE uint @5 decl_var INTERP_MODE_NONE uint @5 decl_var INTERP_MODE_NONE uvec4 @6 decl_var INTERP_MODE_NONE uvec4 @6 decl_var INTERP_MODE_NONE uvec4 @7 decl_var INTERP_MODE_NONE uvec4 @7 decl_var INTERP_MODE_NONE uint @8 decl_var INTERP_MODE_NONE uint @8 decl_var INTERP_MODE_NONE uint @9 decl_var INTERP_MODE_NONE uint @9 decl_var INTERP_MODE_NONE uint @10 decl_var INTERP_MODE_NONE uint @10 decl_var INTERP_MODE_NONE uint @11 decl_var INTERP_MODE_NONE uint @11 decl_var INTERP_MODE_NONE uvec4 @12 decl_var INTERP_MODE_NONE uvec4 @12 decl_var INTERP_MODE_NONE int @13 decl_var INTERP_MODE_NONE int @13 decl_var INTERP_MODE_NONE int @14 decl_var INTERP_MODE_NONE int @14 decl_var INTERP_MODE_NONE uint @15 decl_var INTERP_MODE_NONE uint @15 decl_var INTERP_MODE_NONE int @16 decl_var INTERP_MODE_NONE int @16 decl_var INTERP_MODE_NONE uint @17 decl_var INTERP_MODE_NONE uint @17 decl_var INTERP_MODE_NONE int @18 decl_var INTERP_MODE_NONE int @18 decl_var INTERP_MODE_NONE uint @19 decl_var INTERP_MODE_NONE uint @19 decl_var INTERP_MODE_NONE uint @20 decl_var INTERP_MODE_NONE uint @20 decl_var INTERP_MODE_NONE bool cont decl_var INTERP_MODE_NONE bool cont block block_0: block block_0: /* preds: */ /* preds: */ vec1 32 ssa_217 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_217 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_208 = load_const (0xfffffff7 /* -nan */) vec1 32 ssa_208 = load_const (0xfffffff7 /* -nan */) vec1 32 ssa_189 = load_const (0xffffffff /* -nan */) vec1 32 ssa_189 = load_const (0xffffffff /* -nan */) vec1 32 ssa_184 = load_const (0x00000060 /* 0.000000 */) vec1 32 ssa_184 = load_const (0x00000060 /* 0.000000 */) vec1 32 ssa_180 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_180 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_178 = load_const (0x00000060 /* 0.000000 */) vec1 32 ssa_178 = load_const (0x00000060 /* 0.000000 */) vec1 32 ssa_174 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_174 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_172 = load_const (0x00000080 /* 0.000000 */) vec1 32 ssa_172 = load_const (0x00000080 /* 0.000000 */) vec1 32 ssa_164 = load_const (0xffffffff /* -nan */) vec1 32 ssa_164 = load_const (0xffffffff /* -nan */) vec1 32 ssa_159 = load_const (0x00000040 /* 0.000000 */) vec1 32 ssa_159 = load_const (0x00000040 /* 0.000000 */) vec1 32 ssa_155 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_155 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_153 = load_const (0x00000040 /* 0.000000 */) vec1 32 ssa_153 = load_const (0x00000040 /* 0.000000 */) vec1 32 ssa_149 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_149 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_147 = load_const (0x00000060 /* 0.000000 */) vec1 32 ssa_147 = load_const (0x00000060 /* 0.000000 */) vec1 32 ssa_139 = load_const (0xffffffff /* -nan */) vec1 32 ssa_139 = load_const (0xffffffff /* -nan */) vec1 32 ssa_134 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_134 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_130 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_130 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_128 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_128 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_124 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_124 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_122 = load_const (0x00000040 /* 0.000000 */) vec1 32 ssa_122 = load_const (0x00000040 /* 0.000000 */) vec1 32 ssa_114 = load_const (0xffffffff /* -nan */) vec1 32 ssa_114 = load_const (0xffffffff /* -nan */) vec1 32 ssa_110 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_110 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_108 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_108 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_95 = load_const (0x00000080 /* 0.000000 */) vec1 32 ssa_95 = load_const (0x00000080 /* 0.000000 */) vec1 32 ssa_91 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_91 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_88 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_88 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_79 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_79 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_78 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_78 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_76 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_76 = load_const (0x00000000 /* 0.000000 */) vec1 1 ssa_73 = load_const (true) vec1 1 ssa_73 = load_const (true) vec1 32 ssa_66 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_66 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_65 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_65 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_63 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_63 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_53 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_53 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_52 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_52 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_43 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_43 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_39 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_39 = load_const (0x00000000 /* 0.000000 */) vec4 32 ssa_37 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, vec4 32 ssa_37 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, vec4 32 ssa_35 = load_const (0xffffffff /* -nan */, 0xffffffff /* -nan */, 0xffffffff /* -nan */, 0xffffffff vec4 32 ssa_35 = load_const (0xffffffff /* -nan */, 0xffffffff /* -nan */, 0xffffffff /* -nan */, 0xffffffff vec3 32 ssa_2 = load_const (0x00000003 /* 0.000000 */, 0x00000005 /* 0.000000 */, 0x00000007 /* 0.000000 */) vec3 32 ssa_2 = load_const (0x00000003 /* 0.000000 */, 0x00000005 /* 0.000000 */, 0x00000007 /* 0.000000 */) vec1 32 ssa_0 = deref_var &@0 (system uvec3) vec1 32 ssa_0 = deref_var &@0 (system uvec3) vec3 32 ssa_1 = intrinsic load_deref (ssa_0) (0) /* access=0 */ vec3 32 ssa_1 = intrinsic load_deref (ssa_0) (0) /* access=0 */ vec3 32 ssa_3 = imul ssa_1, ssa_2 vec3 32 ssa_3 = imul ssa_1, ssa_2 vec1 32 ssa_4 = deref_var &@4 (function_temp uvec3) vec1 32 ssa_4 = deref_var &@4 (function_temp uvec3) intrinsic store_deref (ssa_4, ssa_3) (7, 0) /* wrmask=xyz */ /* access=0 */ intrinsic store_deref (ssa_4, ssa_3) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_5 = deref_var &@4 (function_temp uvec3) vec1 32 ssa_5 = deref_var &@4 (function_temp uvec3) vec3 32 ssa_8 = intrinsic load_deref (ssa_5) (0) /* access=0 */ vec3 32 ssa_8 = intrinsic load_deref (ssa_5) (0) /* access=0 */ vec1 32 ssa_9 = mov ssa_8.x vec1 32 ssa_9 = mov ssa_8.x vec1 32 ssa_10 = deref_var &@4 (function_temp uvec3) vec1 32 ssa_10 = deref_var &@4 (function_temp uvec3) vec3 32 ssa_13 = intrinsic load_deref (ssa_10) (0) /* access=0 */ vec3 32 ssa_13 = intrinsic load_deref (ssa_10) (0) /* access=0 */ vec1 32 ssa_14 = mov ssa_13.y vec1 32 ssa_14 = mov ssa_13.y vec1 32 ssa_15 = deref_var &@1 (system uvec3) vec1 32 ssa_15 = deref_var &@1 (system uvec3) vec3 32 ssa_18 = intrinsic load_deref (ssa_15) (0) /* access=0 */ vec3 32 ssa_18 = intrinsic load_deref (ssa_15) (0) /* access=0 */ vec1 32 ssa_19 = mov ssa_18.z vec1 32 ssa_19 = mov ssa_18.z vec1 32 ssa_20 = imul ssa_14, ssa_19 vec1 32 ssa_20 = imul ssa_14, ssa_19 vec1 32 ssa_21 = deref_var &@1 (system uvec3) vec1 32 ssa_21 = deref_var &@1 (system uvec3) vec3 32 ssa_24 = intrinsic load_deref (ssa_21) (0) /* access=0 */ vec3 32 ssa_24 = intrinsic load_deref (ssa_21) (0) /* access=0 */ vec1 32 ssa_25 = mov ssa_24.y vec1 32 ssa_25 = mov ssa_24.y vec1 32 ssa_26 = iadd ssa_20, ssa_25 vec1 32 ssa_26 = iadd ssa_20, ssa_25 vec1 32 ssa_27 = imul ssa_9, ssa_26 vec1 32 ssa_27 = imul ssa_9, ssa_26 vec1 32 ssa_28 = deref_var &@1 (system uvec3) vec1 32 ssa_28 = deref_var &@1 (system uvec3) vec3 32 ssa_31 = intrinsic load_deref (ssa_28) (0) /* access=0 */ vec3 32 ssa_31 = intrinsic load_deref (ssa_28) (0) /* access=0 */ vec1 32 ssa_32 = mov ssa_31.x vec1 32 ssa_32 = mov ssa_31.x vec1 32 ssa_33 = iadd ssa_27, ssa_32 vec1 32 ssa_33 = iadd ssa_27, ssa_32 vec1 32 ssa_34 = deref_var &@5 (function_temp uint) vec1 32 ssa_34 = deref_var &@5 (function_temp uint) intrinsic store_deref (ssa_34, ssa_33) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_34, ssa_33) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_36 = deref_var &@6 (function_temp uvec4) vec1 32 ssa_36 = deref_var &@6 (function_temp uvec4) intrinsic store_deref (ssa_36, ssa_35) (15, 0) /* wrmask=xyzw */ /* access=0 */ intrinsic store_deref (ssa_36, ssa_35) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_38 = deref_var &@7 (function_temp uvec4) vec1 32 ssa_38 = deref_var &@7 (function_temp uvec4) intrinsic store_deref (ssa_38, ssa_37) (15, 0) /* wrmask=xyzw */ /* access=0 */ intrinsic store_deref (ssa_38, ssa_37) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_40 = deref_var &@8 (function_temp uint) vec1 32 ssa_40 = deref_var &@8 (function_temp uint) intrinsic store_deref (ssa_40, ssa_39) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_40, ssa_39) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_41 = deref_var &@2 (system uint) vec1 32 ssa_41 = deref_var &@2 (system uint) vec1 32 ssa_42 = intrinsic load_deref (ssa_41) (0) /* access=0 */ vec1 32 ssa_42 = intrinsic load_deref (ssa_41) (0) /* access=0 */ vec1 32 ssa_44 = iadd ssa_42, ssa_43 vec1 32 ssa_44 = iadd ssa_42, ssa_43 vec1 32 ssa_45 = deref_var &@9 (function_temp uint) vec1 32 ssa_45 = deref_var &@9 (function_temp uint) intrinsic store_deref (ssa_45, ssa_44) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_45, ssa_44) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_46 = deref_var &@9 (function_temp uint) vec1 32 ssa_46 = deref_var &@9 (function_temp uint) vec1 32 ssa_47 = intrinsic load_deref (ssa_46) (0) /* access=0 */ vec1 32 ssa_47 = intrinsic load_deref (ssa_46) (0) /* access=0 */ vec1 32 ssa_48 = deref_var &@6 (function_temp uvec4) vec1 32 ssa_48 = deref_var &@6 (function_temp uvec4) vec4 32 ssa_49 = intrinsic load_deref (ssa_48) (0) /* access=0 */ vec4 32 ssa_49 = intrinsic load_deref (ssa_48) (0) /* access=0 */ vec1 32 ssa_50 = intrinsic ballot_bit_count_inclusive (ssa_49) () vec1 32 ssa_50 = intrinsic ballot_bit_count_inclusive (ssa_49) () vec1 1 ssa_51 = ieq ssa_47, ssa_50 vec1 1 ssa_51 = ieq ssa_47, ssa_50 vec1 32 ssa_54 = bcsel ssa_51, ssa_53, ssa_52 vec1 32 ssa_54 = bcsel ssa_51, ssa_53, ssa_52 vec1 32 ssa_55 = mov ssa_54 vec1 32 ssa_55 = mov ssa_54 vec1 32 ssa_56 = deref_var &@8 (function_temp uint) vec1 32 ssa_56 = deref_var &@8 (function_temp uint) vec1 32 ssa_57 = intrinsic load_deref (ssa_56) (0) /* access=0 */ vec1 32 ssa_57 = intrinsic load_deref (ssa_56) (0) /* access=0 */ vec1 32 ssa_58 = ior ssa_57, ssa_55 vec1 32 ssa_58 = ior ssa_57, ssa_55 vec1 32 ssa_59 = deref_var &@8 (function_temp uint) vec1 32 ssa_59 = deref_var &@8 (function_temp uint) intrinsic store_deref (ssa_59, ssa_58) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_59, ssa_58) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_60 = deref_var &@7 (function_temp uvec4) vec1 32 ssa_60 = deref_var &@7 (function_temp uvec4) vec4 32 ssa_61 = intrinsic load_deref (ssa_60) (0) /* access=0 */ vec4 32 ssa_61 = intrinsic load_deref (ssa_60) (0) /* access=0 */ vec1 32 ssa_62 = intrinsic ballot_bit_count_inclusive (ssa_61) () vec1 32 ssa_62 = intrinsic ballot_bit_count_inclusive (ssa_61) () vec1 1 ssa_64 = ieq ssa_63, ssa_62 vec1 1 ssa_64 = ieq ssa_63, ssa_62 vec1 32 ssa_67 = bcsel ssa_64, ssa_66, ssa_65 vec1 32 ssa_67 = bcsel ssa_64, ssa_66, ssa_65 vec1 32 ssa_68 = mov ssa_67 vec1 32 ssa_68 = mov ssa_67 vec1 32 ssa_69 = deref_var &@8 (function_temp uint) vec1 32 ssa_69 = deref_var &@8 (function_temp uint) vec1 32 ssa_70 = intrinsic load_deref (ssa_69) (0) /* access=0 */ vec1 32 ssa_70 = intrinsic load_deref (ssa_69) (0) /* access=0 */ vec1 32 ssa_71 = ior ssa_70, ssa_68 vec1 32 ssa_71 = ior ssa_70, ssa_68 vec1 32 ssa_72 = deref_var &@8 (function_temp uint) vec1 32 ssa_72 = deref_var &@8 (function_temp uint) intrinsic store_deref (ssa_72, ssa_71) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_72, ssa_71) (1, 0) /* wrmask=x */ /* access=0 */ vec4 32 ssa_74 = intrinsic ballot (ssa_73) () vec4 32 ssa_74 = intrinsic ballot (ssa_73) () vec1 32 ssa_75 = intrinsic ballot_bit_count_inclusive (ssa_74) () vec1 32 ssa_75 = intrinsic ballot_bit_count_inclusive (ssa_74) () vec1 1 ssa_77 = ult ssa_76, ssa_75 vec1 1 ssa_77 = ult ssa_76, ssa_75 vec1 32 ssa_80 = bcsel ssa_77, ssa_79, ssa_78 vec1 32 ssa_80 = bcsel ssa_77, ssa_79, ssa_78 vec1 32 ssa_81 = mov ssa_80 vec1 32 ssa_81 = mov ssa_80 vec1 32 ssa_82 = deref_var &@8 (function_temp uint) vec1 32 ssa_82 = deref_var &@8 (function_temp uint) vec1 32 ssa_83 = intrinsic load_deref (ssa_82) (0) /* access=0 */ vec1 32 ssa_83 = intrinsic load_deref (ssa_82) (0) /* access=0 */ vec1 32 ssa_84 = ior ssa_83, ssa_81 vec1 32 ssa_84 = ior ssa_83, ssa_81 vec1 32 ssa_85 = deref_var &@8 (function_temp uint) vec1 32 ssa_85 = deref_var &@8 (function_temp uint) intrinsic store_deref (ssa_85, ssa_84) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_85, ssa_84) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_86 = deref_var &@8 (function_temp uint) vec1 32 ssa_86 = deref_var &@8 (function_temp uint) vec1 32 ssa_87 = intrinsic load_deref (ssa_86) (0) /* access=0 */ vec1 32 ssa_87 = intrinsic load_deref (ssa_86) (0) /* access=0 */ vec1 32 ssa_89 = ior ssa_87, ssa_88 vec1 32 ssa_89 = ior ssa_87, ssa_88 vec1 32 ssa_90 = deref_var &@8 (function_temp uint) vec1 32 ssa_90 = deref_var &@8 (function_temp uint) intrinsic store_deref (ssa_90, ssa_89) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_90, ssa_89) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_92 = deref_var &@10 (function_temp uint) vec1 32 ssa_92 = deref_var &@10 (function_temp uint) intrinsic store_deref (ssa_92, ssa_91) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_92, ssa_91) (1, 0) /* wrmask=x */ /* access=0 */ vec1 1 ssa_211 = load_const (false) vec1 1 ssa_211 = load_const (false) vec1 32 ssa_212 = deref_var &cont (function_temp bool) vec1 32 ssa_212 = deref_var &cont (function_temp bool) intrinsic store_deref (ssa_212, ssa_211) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_212, ssa_211) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_1 */ /* succs: block_1 */ loop { loop { block block_1: block block_1: /* preds: block_0 block_29 block_31 */ /* preds: block_0 block_29 block_31 */ vec1 32 ssa_213 = deref_var &cont (function_temp bool) vec1 32 ssa_213 = deref_var &cont (function_temp bool) vec1 1 ssa_214 = intrinsic load_deref (ssa_213) (0) /* access=0 */ vec1 1 ssa_214 = intrinsic load_deref (ssa_213) (0) /* access=0 */ /* succs: block_2 block_3 */ /* succs: block_2 block_3 */ if ssa_214 { if ssa_214 { block block_2: block block_2: /* preds: block_1 */ /* preds: block_1 */ vec1 32 ssa_215 = deref_var &@10 (function_temp uint) vec1 32 ssa_215 = deref_var &@10 (function_temp uint) vec1 32 ssa_216 = intrinsic load_deref (ssa_215) (0) /* access=0 */ vec1 32 ssa_216 = intrinsic load_deref (ssa_215) (0) /* access=0 */ vec1 32 ssa_218 = iadd ssa_216, ssa_217 vec1 32 ssa_218 = iadd ssa_216, ssa_217 vec1 32 ssa_219 = deref_var &@10 (function_temp uint) vec1 32 ssa_219 = deref_var &@10 (function_temp uint) intrinsic store_deref (ssa_219, ssa_218) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_219, ssa_218) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_4 */ /* succs: block_4 */ } else { } else { block block_3: block block_3: /* preds: block_1 */ /* preds: block_1 */ /* succs: block_4 */ /* succs: block_4 */ } } block block_4: block block_4: /* preds: block_2 block_3 */ /* preds: block_2 block_3 */ vec1 1 ssa_220 = load_const (true) vec1 1 ssa_220 = load_const (true) vec1 32 ssa_221 = deref_var &cont (function_temp bool) vec1 32 ssa_221 = deref_var &cont (function_temp bool) intrinsic store_deref (ssa_221, ssa_220) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_221, ssa_220) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_93 = deref_var &@10 (function_temp uint) vec1 32 ssa_93 = deref_var &@10 (function_temp uint) vec1 32 ssa_94 = intrinsic load_deref (ssa_93) (0) /* access=0 */ vec1 32 ssa_94 = intrinsic load_deref (ssa_93) (0) /* access=0 */ vec1 1 ssa_96 = ult ssa_94, ssa_95 vec1 1 ssa_96 = ult ssa_94, ssa_95 /* succs: block_5 block_30 */ /* succs: block_5 block_30 */ if ssa_96 { if ssa_96 { block block_5: block block_5: /* preds: block_4 */ /* preds: block_4 */ vec1 32 ssa_97 = deref_var &@9 (function_temp uint) vec1 32 ssa_97 = deref_var &@9 (function_temp uint) vec1 32 ssa_98 = intrinsic load_deref (ssa_97) (0) /* access=0 */ vec1 32 ssa_98 = intrinsic load_deref (ssa_97) (0) /* access=0 */ vec1 32 ssa_99 = deref_var &@9 (function_temp uint) vec1 32 ssa_99 = deref_var &@9 (function_temp uint) vec1 32 ssa_100 = intrinsic load_deref (ssa_99) (0) /* access=0 */ vec1 32 ssa_100 = intrinsic load_deref (ssa_99) (0) /* access=0 */ vec1 32 ssa_101 = deref_var &@10 (function_temp uint) vec1 32 ssa_101 = deref_var &@10 (function_temp uint) vec1 32 ssa_102 = intrinsic load_deref (ssa_101) (0) /* access=0 */ vec1 32 ssa_102 = intrinsic load_deref (ssa_101) (0) /* access=0 */ vec1 32 ssa_103 = umin ssa_100, ssa_102 vec1 32 ssa_103 = umin ssa_100, ssa_102 vec1 32 ssa_104 = isub ssa_98, ssa_103 vec1 32 ssa_104 = isub ssa_98, ssa_103 vec1 32 ssa_105 = deref_var &@11 (function_temp uint) vec1 32 ssa_105 = deref_var &@11 (function_temp uint) intrinsic store_deref (ssa_105, ssa_104) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_105, ssa_104) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_106 = deref_var &@10 (function_temp uint) vec1 32 ssa_106 = deref_var &@10 (function_temp uint) vec1 32 ssa_107 = intrinsic load_deref (ssa_106) (0) /* access=0 */ vec1 32 ssa_107 = intrinsic load_deref (ssa_106) (0) /* access=0 */ vec1 1 ssa_109 = uge ssa_107, ssa_108 vec1 1 ssa_109 = uge ssa_107, ssa_108 /* succs: block_6 block_7 */ /* succs: block_6 block_7 */ if ssa_109 { if ssa_109 { block block_6: block block_6: /* preds: block_5 */ /* preds: block_5 */ vec1 32 ssa_111 = deref_var &@13 (function_temp int) vec1 32 ssa_111 = deref_var &@13 (function_temp int) intrinsic store_deref (ssa_111, ssa_110) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_111, ssa_110) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_8 */ /* succs: block_8 */ } else { } else { block block_7: block block_7: /* preds: block_5 */ /* preds: block_5 */ vec1 32 ssa_112 = deref_var &@10 (function_temp uint) vec1 32 ssa_112 = deref_var &@10 (function_temp uint) vec1 32 ssa_113 = intrinsic load_deref (ssa_112) (0) /* access=0 */ vec1 32 ssa_113 = intrinsic load_deref (ssa_112) (0) /* access=0 */ vec1 32 ssa_115 = ishl ssa_114, ssa_113 vec1 32 ssa_115 = ishl ssa_114, ssa_113 vec1 32 ssa_116 = deref_var &@13 (function_temp int) vec1 32 ssa_116 = deref_var &@13 (function_temp int) intrinsic store_deref (ssa_116, ssa_115) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_116, ssa_115) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_8 */ /* succs: block_8 */ } } block block_8: block block_8: /* preds: block_6 block_7 */ /* preds: block_6 block_7 */ vec1 32 ssa_117 = deref_var &@13 (function_temp int) vec1 32 ssa_117 = deref_var &@13 (function_temp int) vec1 32 ssa_118 = intrinsic load_deref (ssa_117) (0) /* access=0 */ vec1 32 ssa_118 = intrinsic load_deref (ssa_117) (0) /* access=0 */ vec1 32 ssa_119 = mov ssa_118 vec1 32 ssa_119 = mov ssa_118 vec1 32 ssa_120 = deref_var &@10 (function_temp uint) vec1 32 ssa_120 = deref_var &@10 (function_temp uint) vec1 32 ssa_121 = intrinsic load_deref (ssa_120) (0) /* access=0 */ vec1 32 ssa_121 = intrinsic load_deref (ssa_120) (0) /* access=0 */ vec1 1 ssa_123 = uge ssa_121, ssa_122 vec1 1 ssa_123 = uge ssa_121, ssa_122 /* succs: block_9 block_10 */ /* succs: block_9 block_10 */ if ssa_123 { if ssa_123 { block block_9: block block_9: /* preds: block_8 */ /* preds: block_8 */ vec1 32 ssa_125 = deref_var &@14 (function_temp int) vec1 32 ssa_125 = deref_var &@14 (function_temp int) intrinsic store_deref (ssa_125, ssa_124) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_125, ssa_124) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_14 */ /* succs: block_14 */ } else { } else { block block_10: block block_10: /* preds: block_8 */ /* preds: block_8 */ vec1 32 ssa_126 = deref_var &@10 (function_temp uint) vec1 32 ssa_126 = deref_var &@10 (function_temp uint) vec1 32 ssa_127 = intrinsic load_deref (ssa_126) (0) /* access=0 */ vec1 32 ssa_127 = intrinsic load_deref (ssa_126) (0) /* access=0 */ vec1 1 ssa_129 = ult ssa_127, ssa_128 vec1 1 ssa_129 = ult ssa_127, ssa_128 /* succs: block_11 block_12 */ /* succs: block_11 block_12 */ if ssa_129 { if ssa_129 { block block_11: block block_11: /* preds: block_10 */ /* preds: block_10 */ vec1 32 ssa_131 = deref_var &@15 (function_temp uint) vec1 32 ssa_131 = deref_var &@15 (function_temp uint) intrinsic store_deref (ssa_131, ssa_130) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_131, ssa_130) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_13 */ /* succs: block_13 */ } else { } else { block block_12: block block_12: /* preds: block_10 */ /* preds: block_10 */ vec1 32 ssa_132 = deref_var &@10 (function_temp uint) vec1 32 ssa_132 = deref_var &@10 (function_temp uint) vec1 32 ssa_133 = intrinsic load_deref (ssa_132) (0) /* access=0 */ vec1 32 ssa_133 = intrinsic load_deref (ssa_132) (0) /* access=0 */ vec1 32 ssa_135 = isub ssa_133, ssa_134 vec1 32 ssa_135 = isub ssa_133, ssa_134 vec1 32 ssa_136 = deref_var &@15 (function_temp uint) vec1 32 ssa_136 = deref_var &@15 (function_temp uint) intrinsic store_deref (ssa_136, ssa_135) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_136, ssa_135) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_13 */ /* succs: block_13 */ } } block block_13: block block_13: /* preds: block_11 block_12 */ /* preds: block_11 block_12 */ vec1 32 ssa_137 = deref_var &@15 (function_temp uint) vec1 32 ssa_137 = deref_var &@15 (function_temp uint) vec1 32 ssa_138 = intrinsic load_deref (ssa_137) (0) /* access=0 */ vec1 32 ssa_138 = intrinsic load_deref (ssa_137) (0) /* access=0 */ vec1 32 ssa_140 = ishl ssa_139, ssa_138 vec1 32 ssa_140 = ishl ssa_139, ssa_138 vec1 32 ssa_141 = deref_var &@14 (function_temp int) vec1 32 ssa_141 = deref_var &@14 (function_temp int) intrinsic store_deref (ssa_141, ssa_140) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_141, ssa_140) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_14 */ /* succs: block_14 */ } } block block_14: block block_14: /* preds: block_9 block_13 */ /* preds: block_9 block_13 */ vec1 32 ssa_142 = deref_var &@14 (function_temp int) vec1 32 ssa_142 = deref_var &@14 (function_temp int) vec1 32 ssa_143 = intrinsic load_deref (ssa_142) (0) /* access=0 */ vec1 32 ssa_143 = intrinsic load_deref (ssa_142) (0) /* access=0 */ vec1 32 ssa_144 = mov ssa_143 vec1 32 ssa_144 = mov ssa_143 vec1 32 ssa_145 = deref_var &@10 (function_temp uint) vec1 32 ssa_145 = deref_var &@10 (function_temp uint) vec1 32 ssa_146 = intrinsic load_deref (ssa_145) (0) /* access=0 */ vec1 32 ssa_146 = intrinsic load_deref (ssa_145) (0) /* access=0 */ vec1 1 ssa_148 = uge ssa_146, ssa_147 vec1 1 ssa_148 = uge ssa_146, ssa_147 /* succs: block_15 block_16 */ /* succs: block_15 block_16 */ if ssa_148 { if ssa_148 { block block_15: block block_15: /* preds: block_14 */ /* preds: block_14 */ vec1 32 ssa_150 = deref_var &@16 (function_temp int) vec1 32 ssa_150 = deref_var &@16 (function_temp int) intrinsic store_deref (ssa_150, ssa_149) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_150, ssa_149) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_20 */ /* succs: block_20 */ } else { } else { block block_16: block block_16: /* preds: block_14 */ /* preds: block_14 */ vec1 32 ssa_151 = deref_var &@10 (function_temp uint) vec1 32 ssa_151 = deref_var &@10 (function_temp uint) vec1 32 ssa_152 = intrinsic load_deref (ssa_151) (0) /* access=0 */ vec1 32 ssa_152 = intrinsic load_deref (ssa_151) (0) /* access=0 */ vec1 1 ssa_154 = ult ssa_152, ssa_153 vec1 1 ssa_154 = ult ssa_152, ssa_153 /* succs: block_17 block_18 */ /* succs: block_17 block_18 */ if ssa_154 { if ssa_154 { block block_17: block block_17: /* preds: block_16 */ /* preds: block_16 */ vec1 32 ssa_156 = deref_var &@17 (function_temp uint) vec1 32 ssa_156 = deref_var &@17 (function_temp uint) intrinsic store_deref (ssa_156, ssa_155) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_156, ssa_155) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_19 */ /* succs: block_19 */ } else { } else { block block_18: block block_18: /* preds: block_16 */ /* preds: block_16 */ vec1 32 ssa_157 = deref_var &@10 (function_temp uint) vec1 32 ssa_157 = deref_var &@10 (function_temp uint) vec1 32 ssa_158 = intrinsic load_deref (ssa_157) (0) /* access=0 */ vec1 32 ssa_158 = intrinsic load_deref (ssa_157) (0) /* access=0 */ vec1 32 ssa_160 = isub ssa_158, ssa_159 vec1 32 ssa_160 = isub ssa_158, ssa_159 vec1 32 ssa_161 = deref_var &@17 (function_temp uint) vec1 32 ssa_161 = deref_var &@17 (function_temp uint) intrinsic store_deref (ssa_161, ssa_160) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_161, ssa_160) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_19 */ /* succs: block_19 */ } } block block_19: block block_19: /* preds: block_17 block_18 */ /* preds: block_17 block_18 */ vec1 32 ssa_162 = deref_var &@17 (function_temp uint) vec1 32 ssa_162 = deref_var &@17 (function_temp uint) vec1 32 ssa_163 = intrinsic load_deref (ssa_162) (0) /* access=0 */ vec1 32 ssa_163 = intrinsic load_deref (ssa_162) (0) /* access=0 */ vec1 32 ssa_165 = ishl ssa_164, ssa_163 vec1 32 ssa_165 = ishl ssa_164, ssa_163 vec1 32 ssa_166 = deref_var &@16 (function_temp int) vec1 32 ssa_166 = deref_var &@16 (function_temp int) intrinsic store_deref (ssa_166, ssa_165) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_166, ssa_165) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_20 */ /* succs: block_20 */ } } block block_20: block block_20: /* preds: block_15 block_19 */ /* preds: block_15 block_19 */ vec1 32 ssa_167 = deref_var &@16 (function_temp int) vec1 32 ssa_167 = deref_var &@16 (function_temp int) vec1 32 ssa_168 = intrinsic load_deref (ssa_167) (0) /* access=0 */ vec1 32 ssa_168 = intrinsic load_deref (ssa_167) (0) /* access=0 */ vec1 32 ssa_169 = mov ssa_168 vec1 32 ssa_169 = mov ssa_168 vec1 32 ssa_170 = deref_var &@10 (function_temp uint) vec1 32 ssa_170 = deref_var &@10 (function_temp uint) vec1 32 ssa_171 = intrinsic load_deref (ssa_170) (0) /* access=0 */ vec1 32 ssa_171 = intrinsic load_deref (ssa_170) (0) /* access=0 */ vec1 1 ssa_173 = uge ssa_171, ssa_172 vec1 1 ssa_173 = uge ssa_171, ssa_172 /* succs: block_21 block_22 */ /* succs: block_21 block_22 */ if ssa_173 { if ssa_173 { block block_21: block block_21: /* preds: block_20 */ /* preds: block_20 */ vec1 32 ssa_175 = deref_var &@18 (function_temp int) vec1 32 ssa_175 = deref_var &@18 (function_temp int) intrinsic store_deref (ssa_175, ssa_174) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_175, ssa_174) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_26 */ /* succs: block_26 */ } else { } else { block block_22: block block_22: /* preds: block_20 */ /* preds: block_20 */ vec1 32 ssa_176 = deref_var &@10 (function_temp uint) vec1 32 ssa_176 = deref_var &@10 (function_temp uint) vec1 32 ssa_177 = intrinsic load_deref (ssa_176) (0) /* access=0 */ vec1 32 ssa_177 = intrinsic load_deref (ssa_176) (0) /* access=0 */ vec1 1 ssa_179 = ult ssa_177, ssa_178 vec1 1 ssa_179 = ult ssa_177, ssa_178 /* succs: block_23 block_24 */ /* succs: block_23 block_24 */ if ssa_179 { if ssa_179 { block block_23: block block_23: /* preds: block_22 */ /* preds: block_22 */ vec1 32 ssa_181 = deref_var &@19 (function_temp uint) vec1 32 ssa_181 = deref_var &@19 (function_temp uint) intrinsic store_deref (ssa_181, ssa_180) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_181, ssa_180) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_25 */ /* succs: block_25 */ } else { } else { block block_24: block block_24: /* preds: block_22 */ /* preds: block_22 */ vec1 32 ssa_182 = deref_var &@10 (function_temp uint) vec1 32 ssa_182 = deref_var &@10 (function_temp uint) vec1 32 ssa_183 = intrinsic load_deref (ssa_182) (0) /* access=0 */ vec1 32 ssa_183 = intrinsic load_deref (ssa_182) (0) /* access=0 */ vec1 32 ssa_185 = isub ssa_183, ssa_184 vec1 32 ssa_185 = isub ssa_183, ssa_184 vec1 32 ssa_186 = deref_var &@19 (function_temp uint) vec1 32 ssa_186 = deref_var &@19 (function_temp uint) intrinsic store_deref (ssa_186, ssa_185) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_186, ssa_185) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_25 */ /* succs: block_25 */ } } block block_25: block block_25: /* preds: block_23 block_24 */ /* preds: block_23 block_24 */ vec1 32 ssa_187 = deref_var &@19 (function_temp uint) vec1 32 ssa_187 = deref_var &@19 (function_temp uint) vec1 32 ssa_188 = intrinsic load_deref (ssa_187) (0) /* access=0 */ vec1 32 ssa_188 = intrinsic load_deref (ssa_187) (0) /* access=0 */ vec1 32 ssa_190 = ishl ssa_189, ssa_188 vec1 32 ssa_190 = ishl ssa_189, ssa_188 vec1 32 ssa_191 = deref_var &@18 (function_temp int) vec1 32 ssa_191 = deref_var &@18 (function_temp int) intrinsic store_deref (ssa_191, ssa_190) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_191, ssa_190) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_26 */ /* succs: block_26 */ } } block block_26: block block_26: /* preds: block_21 block_25 */ /* preds: block_21 block_25 */ vec1 32 ssa_192 = deref_var &@18 (function_temp int) vec1 32 ssa_192 = deref_var &@18 (function_temp int) vec1 32 ssa_193 = intrinsic load_deref (ssa_192) (0) /* access=0 */ vec1 32 ssa_193 = intrinsic load_deref (ssa_192) (0) /* access=0 */ vec1 32 ssa_194 = mov ssa_193 vec1 32 ssa_194 = mov ssa_193 vec4 32 ssa_195 = vec4 ssa_119, ssa_144, ssa_169, ssa_194 vec4 32 ssa_195 = vec4 ssa_119, ssa_144, ssa_169, ssa_194 vec1 32 ssa_196 = deref_var &@12 (function_temp uvec4) vec1 32 ssa_196 = deref_var &@12 (function_temp uvec4) intrinsic store_deref (ssa_196, ssa_195) (15, 0) /* wrmask=xyzw */ /* access=0 */ intrinsic store_deref (ssa_196, ssa_195) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_197 = deref_var &@12 (function_temp uvec4) vec1 32 ssa_197 = deref_var &@12 (function_temp uvec4) vec4 32 ssa_198 = intrinsic load_deref (ssa_197) (0) /* access=0 */ vec4 32 ssa_198 = intrinsic load_deref (ssa_197) (0) /* access=0 */ vec1 32 ssa_199 = intrinsic ballot_bit_count_inclusive (ssa_198) () vec1 32 ssa_199 = intrinsic ballot_bit_count_inclusive (ssa_198) () vec1 32 ssa_200 = deref_var &@20 (function_temp uint) vec1 32 ssa_200 = deref_var &@20 (function_temp uint) intrinsic store_deref (ssa_200, ssa_199) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_200, ssa_199) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_201 = deref_var &@20 (function_temp uint) vec1 32 ssa_201 = deref_var &@20 (function_temp uint) vec1 32 ssa_202 = intrinsic load_deref (ssa_201) (0) /* access=0 */ vec1 32 ssa_202 = intrinsic load_deref (ssa_201) (0) /* access=0 */ vec1 32 ssa_203 = deref_var &@11 (function_temp uint) vec1 32 ssa_203 = deref_var &@11 (function_temp uint) vec1 32 ssa_204 = intrinsic load_deref (ssa_203) (0) /* access=0 */ vec1 32 ssa_204 = intrinsic load_deref (ssa_203) (0) /* access=0 */ vec1 1 ssa_205 = ine ssa_202, ssa_204 vec1 1 ssa_205 = ine ssa_202, ssa_204 /* succs: block_27 block_28 */ /* succs: block_27 block_28 */ if ssa_205 { if ssa_205 { block block_27: block block_27: /* preds: block_26 */ /* preds: block_26 */ vec1 32 ssa_206 = deref_var &@8 (function_temp uint) vec1 32 ssa_206 = deref_var &@8 (function_temp uint) vec1 32 ssa_207 = intrinsic load_deref (ssa_206) (0) /* access=0 */ vec1 32 ssa_207 = intrinsic load_deref (ssa_206) (0) /* access=0 */ vec1 32 ssa_209 = iand ssa_207, ssa_208 vec1 32 ssa_209 = iand ssa_207, ssa_208 vec1 32 ssa_210 = deref_var &@8 (function_temp uint) vec1 32 ssa_210 = deref_var &@8 (function_temp uint) intrinsic store_deref (ssa_210, ssa_209) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_210, ssa_209) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_29 */ /* succs: block_29 */ } else { } else { block block_28: block block_28: /* preds: block_26 */ /* preds: block_26 */ /* succs: block_29 */ /* succs: block_29 */ } } block block_29: block block_29: /* preds: block_27 block_28 */ /* preds: block_27 block_28 */ continue continue /* succs: block_1 */ /* succs: block_1 */ } else { } else { block block_30: block block_30: /* preds: block_4 */ /* preds: block_4 */ break break /* succs: block_32 */ /* succs: block_32 */ } } block block_31: block block_31: /* preds: */ /* preds: */ /* succs: block_1 */ /* succs: block_1 */ } } block block_32: block block_32: /* preds: block_30 */ /* preds: block_30 */ vec1 32 ssa_222 = deref_var &@5 (function_temp uint) vec1 32 ssa_222 = deref_var &@5 (function_temp uint) vec1 32 ssa_223 = intrinsic load_deref (ssa_222) (0) /* access=0 */ vec1 32 ssa_223 = intrinsic load_deref (ssa_222) (0) /* access=0 */ vec1 32 ssa_224 = deref_var &@8 (function_temp uint) vec1 32 ssa_224 = deref_var &@8 (function_temp uint) vec1 32 ssa_225 = intrinsic load_deref (ssa_224) (0) /* access=0 */ vec1 32 ssa_225 = intrinsic load_deref (ssa_224) (0) /* access=0 */ vec1 32 ssa_226 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_226 = load_const (0x00000000 /* 0.000000 */) vec1 64 ssa_227 = intrinsic vulkan_resource_index (ssa_226) (0, 0, 7) /* desc-set=0 */ /* binding=0 */ /* des vec1 64 ssa_227 = intrinsic vulkan_resource_index (ssa_226) (0, 0, 7) /* desc-set=0 */ /* binding=0 */ /* des vec1 64 ssa_228 = intrinsic load_vulkan_descriptor (ssa_227) (7) /* desc_type=SSBO */ vec1 64 ssa_228 = intrinsic load_vulkan_descriptor (ssa_227) (7) /* desc_type=SSBO */ vec1 64 ssa_229 = deref_cast (block *)ssa_228 (ssbo block) /* ptr_stride=0, align_mul=0, align_offset=0 */ vec1 64 ssa_229 = deref_cast (block *)ssa_228 (ssbo block) /* ptr_stride=0, align_mul=0, align_offset=0 */ vec1 64 ssa_230 = deref_struct &ssa_229->field0 (ssbo uint[]) /* &((block *)ssa_228)->field0 */ vec1 64 ssa_230 = deref_struct &ssa_229->field0 (ssbo uint[]) /* &((block *)ssa_228)->field0 */ vec1 64 ssa_231 = i2i64 ssa_223 vec1 64 ssa_231 = i2i64 ssa_223 vec1 64 ssa_232 = deref_array &(*ssa_230)[ssa_231] (ssbo uint) /* &((block *)ssa_228)->field0[ssa_231] */ vec1 64 ssa_232 = deref_array &(*ssa_230)[ssa_231] (ssbo uint) /* &((block *)ssa_228)->field0[ssa_231] */ intrinsic store_deref (ssa_232, ssa_225) (1, 0) /* wrmask=x */ /* access=0 */ intrinsic store_deref (ssa_232, ssa_225) (1, 0) /* wrmask=x */ /* access=0 */ return return /* succs: block_33 */ /* succs: block_33 */ block block_33: block block_33: } } NIR (SSA form) for compute shader: NIR (SSA form) for compute shader: shader: MESA_SHADER_COMPUTE shader: MESA_SHADER_COMPUTE local-size: 3, 5, 7 local-size: 3, 5, 7 shared-size: 0 shared-size: 0 inputs: 0 inputs: 0 outputs: 0 outputs: 0 uniforms: 36 uniforms: 36 shared: 0 shared: 0 decl_var ssbo INTERP_MODE_NONE restrict block @0 (~0, 0, 0) decl_var ssbo INTERP_MODE_NONE restrict block @0 (~0, 0, 0) decl_function main (0 params) decl_function main (0 params) impl main { impl main { block block_0: block block_0: /* preds: */ /* preds: */ vec1 32 ssa_0 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_0 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_1 = load_const (0xfffffff7 /* -nan */) vec1 32 ssa_1 = load_const (0xfffffff7 /* -nan */) vec1 32 ssa_2 = load_const (0xffffffff /* -nan */) vec1 32 ssa_2 = load_const (0xffffffff /* -nan */) vec1 32 ssa_3 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_4 = load_const (0x00000080 /* 0.000000 */) vec1 32 ssa_4 = load_const (0x00000080 /* 0.000000 */) vec1 32 ssa_5 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_5 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_6 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_6 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_7 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_7 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_8 = load_const (0xffffffff /* -nan */) vec1 32 ssa_8 = load_const (0xffffffff /* -nan */) vec1 32 ssa_9 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_9 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_10 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_10 = load_const (0x00000005 /* 0.000000 */) vec3 32 ssa_11 = intrinsic load_num_work_groups () () vec3 32 ssa_11 = intrinsic load_num_work_groups () () vec3 32 ssa_12 = load_const (0x00000003 /* 0.000000 */, 0x00000005 /* 0.000000 */, 0x00000007 /* 0.000000 */) vec3 32 ssa_12 = load_const (0x00000003 /* 0.000000 */, 0x00000005 /* 0.000000 */, 0x00000007 /* 0.000000 */) vec3 32 ssa_13 = intrinsic load_work_group_id () () vec3 32 ssa_13 = intrinsic load_work_group_id () () vec3 32 ssa_14 = intrinsic load_uniform (ssa_3) (24, 12, 0) /* base=24 */ /* range=12 */ /* dest_type=invalid vec3 32 ssa_14 = intrinsic load_uniform (ssa_3) (24, 12, 0) /* base=24 */ /* range=12 */ /* dest_type=invalid vec1 32 ssa_15 = iadd ssa_13.x, ssa_14.x vec1 32 ssa_15 = iadd ssa_13.x, ssa_14.x vec1 32 ssa_16 = iadd ssa_13.y, ssa_14.y vec1 32 ssa_16 = iadd ssa_13.y, ssa_14.y vec1 32 ssa_17 = iadd ssa_13.z, ssa_14.z vec1 32 ssa_17 = iadd ssa_13.z, ssa_14.z vec1 32 ssa_18 = intrinsic load_subgroup_id () () vec1 32 ssa_18 = intrinsic load_subgroup_id () () vec1 32 ssa_19 = ishl ssa_18, ssa_9 vec1 32 ssa_19 = ishl ssa_18, ssa_9 vec1 32 ssa_20 = intrinsic load_subgroup_invocation () () vec1 32 ssa_20 = intrinsic load_subgroup_invocation () () vec1 32 ssa_21 = iadd ssa_20, ssa_19 vec1 32 ssa_21 = iadd ssa_20, ssa_19 vec1 32 ssa_22 = load_const (0xaaaaaaab /* -0.000000 */) vec1 32 ssa_22 = load_const (0xaaaaaaab /* -0.000000 */) vec1 32 ssa_23 = umul_high ssa_21, ssa_22 vec1 32 ssa_23 = umul_high ssa_21, ssa_22 vec1 32 ssa_24 = ushr ssa_23, ssa_0 vec1 32 ssa_24 = ushr ssa_23, ssa_0 vec1 32 ssa_25 = imul ssa_24, ssa_9 vec1 32 ssa_25 = imul ssa_24, ssa_9 vec1 32 ssa_26 = ineg ssa_25 vec1 32 ssa_26 = ineg ssa_25 vec1 32 ssa_27 = iadd ssa_21, ssa_26 vec1 32 ssa_27 = iadd ssa_21, ssa_26 vec1 32 ssa_28 = load_const (0xcccccccd /* -107374184.000000 */) vec1 32 ssa_28 = load_const (0xcccccccd /* -107374184.000000 */) vec1 32 ssa_29 = umul_high ssa_24, ssa_28 vec1 32 ssa_29 = umul_high ssa_24, ssa_28 vec1 32 ssa_30 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_30 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_31 = ushr ssa_29, ssa_30 vec1 32 ssa_31 = ushr ssa_29, ssa_30 vec1 32 ssa_32 = imul ssa_31, ssa_10 vec1 32 ssa_32 = imul ssa_31, ssa_10 vec1 32 ssa_33 = ineg ssa_32 vec1 32 ssa_33 = ineg ssa_32 vec1 32 ssa_34 = iadd ssa_24, ssa_33 vec1 32 ssa_34 = iadd ssa_24, ssa_33 vec1 32 ssa_35 = load_const (0x88888889 /* -0.000000 */) vec1 32 ssa_35 = load_const (0x88888889 /* -0.000000 */) vec1 32 ssa_36 = umul_high ssa_21, ssa_35 vec1 32 ssa_36 = umul_high ssa_21, ssa_35 vec1 32 ssa_37 = ushr ssa_36, ssa_9 vec1 32 ssa_37 = ushr ssa_36, ssa_9 vec1 32 ssa_38 = imul ssa_15, ssa_12.x vec1 32 ssa_38 = imul ssa_15, ssa_12.x vec1 32 ssa_39 = imul ssa_16, ssa_12.y vec1 32 ssa_39 = imul ssa_16, ssa_12.y vec1 32 ssa_40 = imul ssa_17, ssa_12.z vec1 32 ssa_40 = imul ssa_17, ssa_12.z vec1 32 ssa_41 = iadd ssa_38, ssa_27 vec1 32 ssa_41 = iadd ssa_38, ssa_27 vec1 32 ssa_42 = iadd ssa_39, ssa_34 vec1 32 ssa_42 = iadd ssa_39, ssa_34 vec1 32 ssa_43 = iadd ssa_40, ssa_37 vec1 32 ssa_43 = iadd ssa_40, ssa_37 vec1 32 ssa_44 = imul ssa_11.y, ssa_10 vec1 32 ssa_44 = imul ssa_11.y, ssa_10 vec1 32 ssa_45 = imul ssa_44, ssa_43 vec1 32 ssa_45 = imul ssa_44, ssa_43 vec1 32 ssa_46 = iadd ssa_45, ssa_42 vec1 32 ssa_46 = iadd ssa_45, ssa_42 vec1 32 ssa_47 = imul ssa_11.x, ssa_9 vec1 32 ssa_47 = imul ssa_11.x, ssa_9 vec1 32 ssa_48 = imul ssa_47, ssa_46 vec1 32 ssa_48 = imul ssa_47, ssa_46 vec1 32 ssa_49 = iadd ssa_48, ssa_41 vec1 32 ssa_49 = iadd ssa_48, ssa_41 vec1 32 ssa_50 = iadd ssa_20, ssa_0 vec1 32 ssa_50 = iadd ssa_20, ssa_0 vec1 32 ssa_51 = load_const (0x0000001f /* 0.000000 */) vec1 32 ssa_51 = load_const (0x0000001f /* 0.000000 */) vec1 32 ssa_52 = ineg ssa_20 vec1 32 ssa_52 = ineg ssa_20 vec1 32 ssa_53 = iadd ssa_51, ssa_52 vec1 32 ssa_53 = iadd ssa_51, ssa_52 vec1 32 ssa_54 = ushr ssa_2, ssa_53 vec1 32 ssa_54 = ushr ssa_2, ssa_53 vec1 32 ssa_55 = bit_count ssa_54 vec1 32 ssa_55 = bit_count ssa_54 vec1 32 ssa_56 = ieq32 ssa_50, ssa_55 vec1 32 ssa_56 = ieq32 ssa_50, ssa_55 vec1 32 ssa_57 = b2i32 ssa_56 vec1 32 ssa_57 = b2i32 ssa_56 vec1 32 ssa_58 = ior ssa_57, ssa_30 vec1 32 ssa_58 = ior ssa_57, ssa_30 vec1 32 ssa_59 = intrinsic ballot (ssa_8) () vec1 32 ssa_59 = intrinsic ballot (ssa_8) () vec1 32 ssa_60 = iand ssa_59, ssa_54 vec1 32 ssa_60 = iand ssa_59, ssa_54 vec1 32 ssa_61 = bit_count ssa_60 vec1 32 ssa_61 = bit_count ssa_60 vec1 32 ssa_62 = ult32 ssa_3, ssa_61 vec1 32 ssa_62 = ult32 ssa_3, ssa_61 vec1 32 ssa_63 = b32csel ssa_62, ssa_7, ssa_3 vec1 32 ssa_63 = b32csel ssa_62, ssa_7, ssa_3 vec1 32 ssa_64 = ior ssa_58, ssa_63 vec1 32 ssa_64 = ior ssa_58, ssa_63 vec1 32 ssa_65 = ior ssa_64, ssa_6 vec1 32 ssa_65 = ior ssa_64, ssa_6 /* succs: block_1 */ /* succs: block_1 */ loop { loop { block block_1: block block_1: /* preds: block_0 block_4 */ /* preds: block_0 block_4 */ vec1 32 ssa_66 = phi block_0: ssa_65, block_4: ssa_79 vec1 32 ssa_66 = phi block_0: ssa_65, block_4: ssa_79 vec1 32 ssa_67 = phi block_0: ssa_3, block_4: ssa_80 vec1 32 ssa_67 = phi block_0: ssa_3, block_4: ssa_80 vec1 32 ssa_68 = uge32 ssa_67, ssa_4 vec1 32 ssa_68 = uge32 ssa_67, ssa_4 /* succs: block_2 block_3 */ /* succs: block_2 block_3 */ if ssa_68 { if ssa_68 { block block_2: block block_2: /* preds: block_1 */ /* preds: block_1 */ break break /* succs: block_5 */ /* succs: block_5 */ } else { } else { block block_3: block block_3: /* preds: block_1 */ /* preds: block_1 */ /* succs: block_4 */ /* succs: block_4 */ } } block block_4: block block_4: /* preds: block_3 */ /* preds: block_3 */ vec1 32 ssa_69 = umin ssa_50, ssa_67 vec1 32 ssa_69 = umin ssa_50, ssa_67 vec1 32 ssa_70 = ineg ssa_69 vec1 32 ssa_70 = ineg ssa_69 vec1 32 ssa_71 = iadd ssa_50, ssa_70 vec1 32 ssa_71 = iadd ssa_50, ssa_70 vec1 32 ssa_72 = ishl ssa_2, ssa_67 vec1 32 ssa_72 = ishl ssa_2, ssa_67 vec1 32 ssa_73 = uge32 ssa_67, ssa_5 vec1 32 ssa_73 = uge32 ssa_67, ssa_5 vec1 32 ssa_74 = b32csel ssa_73, ssa_3, ssa_72 vec1 32 ssa_74 = b32csel ssa_73, ssa_3, ssa_72 vec1 32 ssa_75 = iand ssa_74, ssa_54 vec1 32 ssa_75 = iand ssa_74, ssa_54 vec1 32 ssa_76 = bit_count ssa_75 vec1 32 ssa_76 = bit_count ssa_75 vec1 32 ssa_77 = iand ssa_66, ssa_1 vec1 32 ssa_77 = iand ssa_66, ssa_1 vec1 32 ssa_78 = ine32 ssa_76, ssa_71 vec1 32 ssa_78 = ine32 ssa_76, ssa_71 vec1 32 ssa_79 = b32csel ssa_78, ssa_77, ssa_66 vec1 32 ssa_79 = b32csel ssa_78, ssa_77, ssa_66 vec1 32 ssa_80 = iadd ssa_67, ssa_0 vec1 32 ssa_80 = iadd ssa_67, ssa_0 /* succs: block_1 */ /* succs: block_1 */ } } block block_5: block block_5: /* preds: block_2 */ /* preds: block_2 */ vec1 32 ssa_81 = ishl ssa_49, ssa_30 vec1 32 ssa_81 = ishl ssa_49, ssa_30 intrinsic store_ssbo (ssa_66, ssa_30, ssa_81) (1, 0, 4, 0) /* wrmask=x */ /* access=0 */ /* align_mul=4 */ /* intrinsic store_ssbo (ssa_66, ssa_30, ssa_81) (1, 0, 4, 0) /* wrmask=x */ /* access=0 */ /* align_mul=4 */ /* /* succs: block_6 */ /* succs: block_6 */ block block_6: block block_6: } } NIR (final form) for compute shader: NIR (final form) for compute shader: shader: MESA_SHADER_COMPUTE shader: MESA_SHADER_COMPUTE local-size: 3, 5, 7 local-size: 3, 5, 7 shared-size: 0 shared-size: 0 inputs: 0 inputs: 0 outputs: 0 outputs: 0 uniforms: 36 uniforms: 36 shared: 0 shared: 0 decl_var ssbo INTERP_MODE_NONE restrict block @0 (~0, 0, 0) decl_var ssbo INTERP_MODE_NONE restrict block @0 (~0, 0, 0) decl_function main (0 params) decl_function main (0 params) impl main { impl main { decl_reg vec1 32 r3 decl_reg vec1 32 r3 decl_reg vec1 32 r4 decl_reg vec1 32 r4 block block_0: block block_0: /* preds: */ /* preds: */ vec1 32 ssa_0 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_0 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_1 = load_const (0xfffffff7 /* -nan */) vec1 32 ssa_1 = load_const (0xfffffff7 /* -nan */) vec1 32 ssa_2 = load_const (0xffffffff /* -nan */) vec1 32 ssa_2 = load_const (0xffffffff /* -nan */) vec1 32 ssa_3 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_4 = load_const (0x00000080 /* 0.000000 */) vec1 32 ssa_4 = load_const (0x00000080 /* 0.000000 */) vec1 32 ssa_5 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_5 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_6 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_6 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_7 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_7 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_8 = load_const (0xffffffff /* -nan */) vec1 32 ssa_8 = load_const (0xffffffff /* -nan */) vec1 32 ssa_9 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_9 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_10 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_10 = load_const (0x00000005 /* 0.000000 */) vec3 32 ssa_11 = intrinsic load_num_work_groups () () vec3 32 ssa_11 = intrinsic load_num_work_groups () () vec3 32 ssa_12 = load_const (0x00000003 /* 0.000000 */, 0x00000005 /* 0.000000 */, 0x00000007 /* 0.000000 */) vec3 32 ssa_12 = load_const (0x00000003 /* 0.000000 */, 0x00000005 /* 0.000000 */, 0x00000007 /* 0.000000 */) vec3 32 ssa_13 = intrinsic load_work_group_id () () vec3 32 ssa_13 = intrinsic load_work_group_id () () vec3 32 ssa_14 = intrinsic load_uniform (ssa_3) (24, 12, 0) /* base=24 */ /* range=12 */ /* dest_type=invalid vec3 32 ssa_14 = intrinsic load_uniform (ssa_3) (24, 12, 0) /* base=24 */ /* range=12 */ /* dest_type=invalid vec1 32 ssa_15 = iadd ssa_13.x, ssa_14.x vec1 32 ssa_15 = iadd ssa_13.x, ssa_14.x vec1 32 ssa_16 = iadd ssa_13.y, ssa_14.y vec1 32 ssa_16 = iadd ssa_13.y, ssa_14.y vec1 32 ssa_17 = iadd ssa_13.z, ssa_14.z vec1 32 ssa_17 = iadd ssa_13.z, ssa_14.z vec1 32 ssa_18 = intrinsic load_subgroup_id () () vec1 32 ssa_18 = intrinsic load_subgroup_id () () vec1 32 ssa_19 = ishl ssa_18, ssa_9 vec1 32 ssa_19 = ishl ssa_18, ssa_9 vec1 32 ssa_20 = intrinsic load_subgroup_invocation () () vec1 32 ssa_20 = intrinsic load_subgroup_invocation () () vec1 32 ssa_21 = iadd ssa_20, ssa_19 vec1 32 ssa_21 = iadd ssa_20, ssa_19 vec1 32 ssa_22 = load_const (0xaaaaaaab /* -0.000000 */) vec1 32 ssa_22 = load_const (0xaaaaaaab /* -0.000000 */) vec1 32 ssa_23 = umul_high ssa_21, ssa_22 vec1 32 ssa_23 = umul_high ssa_21, ssa_22 vec1 32 ssa_24 = ushr ssa_23, ssa_0 vec1 32 ssa_24 = ushr ssa_23, ssa_0 vec1 32 ssa_25 = imul ssa_24, ssa_9 vec1 32 ssa_25 = imul ssa_24, ssa_9 vec1 32 ssa_26 = ineg ssa_25 vec1 32 ssa_26 = ineg ssa_25 vec1 32 ssa_27 = iadd ssa_21, ssa_26 vec1 32 ssa_27 = iadd ssa_21, ssa_26 vec1 32 ssa_28 = load_const (0xcccccccd /* -107374184.000000 */) vec1 32 ssa_28 = load_const (0xcccccccd /* -107374184.000000 */) vec1 32 ssa_29 = umul_high ssa_24, ssa_28 vec1 32 ssa_29 = umul_high ssa_24, ssa_28 vec1 32 ssa_30 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_30 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_31 = ushr ssa_29, ssa_30 vec1 32 ssa_31 = ushr ssa_29, ssa_30 vec1 32 ssa_32 = imul ssa_31, ssa_10 vec1 32 ssa_32 = imul ssa_31, ssa_10 vec1 32 ssa_33 = ineg ssa_32 vec1 32 ssa_33 = ineg ssa_32 vec1 32 ssa_34 = iadd ssa_24, ssa_33 vec1 32 ssa_34 = iadd ssa_24, ssa_33 vec1 32 ssa_35 = load_const (0x88888889 /* -0.000000 */) vec1 32 ssa_35 = load_const (0x88888889 /* -0.000000 */) vec1 32 ssa_36 = umul_high ssa_21, ssa_35 vec1 32 ssa_36 = umul_high ssa_21, ssa_35 vec1 32 ssa_37 = ushr ssa_36, ssa_9 vec1 32 ssa_37 = ushr ssa_36, ssa_9 vec1 32 ssa_38 = imul ssa_15, ssa_12.x vec1 32 ssa_38 = imul ssa_15, ssa_12.x vec1 32 ssa_39 = imul ssa_16, ssa_12.y vec1 32 ssa_39 = imul ssa_16, ssa_12.y vec1 32 ssa_40 = imul ssa_17, ssa_12.z vec1 32 ssa_40 = imul ssa_17, ssa_12.z vec1 32 ssa_41 = iadd ssa_38, ssa_27 vec1 32 ssa_41 = iadd ssa_38, ssa_27 vec1 32 ssa_42 = iadd ssa_39, ssa_34 vec1 32 ssa_42 = iadd ssa_39, ssa_34 vec1 32 ssa_43 = iadd ssa_40, ssa_37 vec1 32 ssa_43 = iadd ssa_40, ssa_37 vec1 32 ssa_44 = imul ssa_11.y, ssa_10 vec1 32 ssa_44 = imul ssa_11.y, ssa_10 vec1 32 ssa_45 = imul ssa_44, ssa_43 vec1 32 ssa_45 = imul ssa_44, ssa_43 vec1 32 ssa_46 = iadd ssa_45, ssa_42 vec1 32 ssa_46 = iadd ssa_45, ssa_42 vec1 32 ssa_47 = imul ssa_11.x, ssa_9 vec1 32 ssa_47 = imul ssa_11.x, ssa_9 vec1 32 ssa_48 = imul ssa_47, ssa_46 vec1 32 ssa_48 = imul ssa_47, ssa_46 vec1 32 ssa_49 = iadd ssa_48, ssa_41 vec1 32 ssa_49 = iadd ssa_48, ssa_41 vec1 32 ssa_50 = iadd ssa_20, ssa_0 vec1 32 ssa_50 = iadd ssa_20, ssa_0 vec1 32 ssa_51 = load_const (0x0000001f /* 0.000000 */) vec1 32 ssa_51 = load_const (0x0000001f /* 0.000000 */) vec1 32 ssa_52 = ineg ssa_20 vec1 32 ssa_52 = ineg ssa_20 vec1 32 ssa_53 = iadd ssa_51, ssa_52 vec1 32 ssa_53 = iadd ssa_51, ssa_52 vec1 32 ssa_54 = ushr ssa_2, ssa_53 vec1 32 ssa_54 = ushr ssa_2, ssa_53 vec1 32 ssa_55 = bit_count ssa_54 vec1 32 ssa_55 = bit_count ssa_54 vec1 32 ssa_56 = ieq32 ssa_50, ssa_55 vec1 32 ssa_56 = ieq32 ssa_50, ssa_55 vec1 32 ssa_57 = b2i32 ssa_56 vec1 32 ssa_57 = b2i32 ssa_56 vec1 32 ssa_58 = ior ssa_57, ssa_30 vec1 32 ssa_58 = ior ssa_57, ssa_30 vec1 32 ssa_59 = intrinsic ballot (ssa_8) () vec1 32 ssa_59 = intrinsic ballot (ssa_8) () vec1 32 ssa_60 = iand ssa_59, ssa_54 vec1 32 ssa_60 = iand ssa_59, ssa_54 vec1 32 ssa_61 = bit_count ssa_60 vec1 32 ssa_61 = bit_count ssa_60 vec1 32 ssa_62 = ult32 ssa_3, ssa_61 vec1 32 ssa_62 = ult32 ssa_3, ssa_61 vec1 32 ssa_63 = b32csel ssa_62, ssa_7, ssa_3 vec1 32 ssa_63 = b32csel ssa_62, ssa_7, ssa_3 vec1 32 ssa_64 = ior ssa_58, ssa_63 vec1 32 ssa_64 = ior ssa_58, ssa_63 r3 = ior ssa_64, ssa_6 r3 = ior ssa_64, ssa_6 r4 = mov ssa_3 r4 = mov ssa_3 /* succs: block_1 */ /* succs: block_1 */ loop { loop { block block_1: block block_1: /* preds: block_0 block_4 */ /* preds: block_0 block_4 */ vec1 32 ssa_68 = uge32 r4, ssa_4 vec1 32 ssa_68 = uge32 r4, ssa_4 /* succs: block_2 block_3 */ /* succs: block_2 block_3 */ if ssa_68 { if ssa_68 { block block_2: block block_2: /* preds: block_1 */ /* preds: block_1 */ break break /* succs: block_5 */ /* succs: block_5 */ } else { } else { block block_3: block block_3: /* preds: block_1 */ /* preds: block_1 */ /* succs: block_4 */ /* succs: block_4 */ } } block block_4: block block_4: /* preds: block_3 */ /* preds: block_3 */ vec1 32 ssa_69 = umin ssa_50, r4 vec1 32 ssa_69 = umin ssa_50, r4 vec1 32 ssa_70 = ineg ssa_69 vec1 32 ssa_70 = ineg ssa_69 vec1 32 ssa_71 = iadd ssa_50, ssa_70 vec1 32 ssa_71 = iadd ssa_50, ssa_70 vec1 32 ssa_72 = ishl ssa_2, r4 vec1 32 ssa_72 = ishl ssa_2, r4 vec1 32 ssa_73 = uge32 r4, ssa_5 vec1 32 ssa_73 = uge32 r4, ssa_5 vec1 32 ssa_74 = b32csel ssa_73, ssa_3, ssa_72 vec1 32 ssa_74 = b32csel ssa_73, ssa_3, ssa_72 vec1 32 ssa_75 = iand ssa_74, ssa_54 vec1 32 ssa_75 = iand ssa_74, ssa_54 vec1 32 ssa_76 = bit_count ssa_75 vec1 32 ssa_76 = bit_count ssa_75 vec1 32 ssa_77 = iand r3, ssa_1 vec1 32 ssa_77 = iand r3, ssa_1 vec1 32 ssa_78 = ine32 ssa_76, ssa_71 vec1 32 ssa_78 = ine32 ssa_76, ssa_71 r3 = b32csel ssa_78, ssa_77, r3 r3 = b32csel ssa_78, ssa_77, r3 r4 = iadd r4, ssa_0 r4 = iadd r4, ssa_0 /* succs: block_1 */ /* succs: block_1 */ } } block block_5: block block_5: /* preds: block_2 */ /* preds: block_2 */ vec1 32 ssa_81 = ishl ssa_49, ssa_30 vec1 32 ssa_81 = ishl ssa_49, ssa_30 intrinsic store_ssbo (r3, ssa_30, ssa_81) (1, 0, 4, 0) /* wrmask=x */ /* access=0 */ /* align_mul=4 */ /* ali intrinsic store_ssbo (r3, ssa_30, ssa_81) (1, 0, 4, 0) /* wrmask=x */ /* access=0 */ /* align_mul=4 */ /* ali /* succs: block_6 */ /* succs: block_6 */ block block_6: block block_6: } } NIR (SSA form) for compute shader: NIR (SSA form) for compute shader: shader: MESA_SHADER_COMPUTE shader: MESA_SHADER_COMPUTE local-size: 3, 5, 7 local-size: 3, 5, 7 shared-size: 0 shared-size: 0 inputs: 0 inputs: 0 outputs: 0 outputs: 0 uniforms: 36 uniforms: 36 shared: 0 shared: 0 decl_var ssbo INTERP_MODE_NONE restrict block @0 (~0, 0, 0) decl_var ssbo INTERP_MODE_NONE restrict block @0 (~0, 0, 0) decl_function main (0 params) decl_function main (0 params) impl main { impl main { block block_0: block block_0: /* preds: */ /* preds: */ vec1 32 ssa_0 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_0 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_1 = load_const (0xfffffff7 /* -nan */) vec1 32 ssa_1 = load_const (0xfffffff7 /* -nan */) vec1 32 ssa_2 = load_const (0xffffffff /* -nan */) vec1 32 ssa_2 = load_const (0xffffffff /* -nan */) vec1 32 ssa_3 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_4 = load_const (0x00000080 /* 0.000000 */) vec1 32 ssa_4 = load_const (0x00000080 /* 0.000000 */) vec1 32 ssa_5 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_5 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_6 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_6 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_7 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_7 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_8 = load_const (0xffffffff /* -nan */) vec1 32 ssa_8 = load_const (0xffffffff /* -nan */) vec1 32 ssa_9 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_9 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_10 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_10 = load_const (0x00000005 /* 0.000000 */) vec3 32 ssa_11 = intrinsic load_num_work_groups () () vec3 32 ssa_11 = intrinsic load_num_work_groups () () vec3 32 ssa_12 = load_const (0x00000003 /* 0.000000 */, 0x00000005 /* 0.000000 */, 0x00000007 /* 0.000000 */) vec3 32 ssa_12 = load_const (0x00000003 /* 0.000000 */, 0x00000005 /* 0.000000 */, 0x00000007 /* 0.000000 */) vec3 32 ssa_13 = intrinsic load_work_group_id () () vec3 32 ssa_13 = intrinsic load_work_group_id () () vec3 32 ssa_14 = intrinsic load_uniform (ssa_3) (24, 12, 0) /* base=24 */ /* range=12 */ /* dest_type=invalid vec3 32 ssa_14 = intrinsic load_uniform (ssa_3) (24, 12, 0) /* base=24 */ /* range=12 */ /* dest_type=invalid vec1 32 ssa_15 = iadd ssa_13.x, ssa_14.x vec1 32 ssa_15 = iadd ssa_13.x, ssa_14.x vec1 32 ssa_16 = iadd ssa_13.y, ssa_14.y vec1 32 ssa_16 = iadd ssa_13.y, ssa_14.y vec1 32 ssa_17 = iadd ssa_13.z, ssa_14.z vec1 32 ssa_17 = iadd ssa_13.z, ssa_14.z vec1 32 ssa_18 = intrinsic load_subgroup_id () () vec1 32 ssa_18 = intrinsic load_subgroup_id () () vec1 32 ssa_19 = ishl ssa_18, ssa_7 vec1 32 ssa_19 = ishl ssa_18, ssa_7 vec1 32 ssa_20 = intrinsic load_subgroup_invocation () () vec1 32 ssa_20 = intrinsic load_subgroup_invocation () () vec1 32 ssa_21 = iadd ssa_20, ssa_19 vec1 32 ssa_21 = iadd ssa_20, ssa_19 vec1 32 ssa_22 = load_const (0xaaaaaaab /* -0.000000 */) vec1 32 ssa_22 = load_const (0xaaaaaaab /* -0.000000 */) vec1 32 ssa_23 = umul_high ssa_21, ssa_22 vec1 32 ssa_23 = umul_high ssa_21, ssa_22 vec1 32 ssa_24 = ushr ssa_23, ssa_0 vec1 32 ssa_24 = ushr ssa_23, ssa_0 vec1 32 ssa_25 = imul ssa_24, ssa_9 vec1 32 ssa_25 = imul ssa_24, ssa_9 vec1 32 ssa_26 = ineg ssa_25 vec1 32 ssa_26 = ineg ssa_25 vec1 32 ssa_27 = iadd ssa_21, ssa_26 vec1 32 ssa_27 = iadd ssa_21, ssa_26 vec1 32 ssa_28 = load_const (0xcccccccd /* -107374184.000000 */) vec1 32 ssa_28 = load_const (0xcccccccd /* -107374184.000000 */) vec1 32 ssa_29 = umul_high ssa_24, ssa_28 vec1 32 ssa_29 = umul_high ssa_24, ssa_28 vec1 32 ssa_30 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_30 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_31 = ushr ssa_29, ssa_30 vec1 32 ssa_31 = ushr ssa_29, ssa_30 vec1 32 ssa_32 = imul ssa_31, ssa_10 vec1 32 ssa_32 = imul ssa_31, ssa_10 vec1 32 ssa_33 = ineg ssa_32 vec1 32 ssa_33 = ineg ssa_32 vec1 32 ssa_34 = iadd ssa_24, ssa_33 vec1 32 ssa_34 = iadd ssa_24, ssa_33 vec1 32 ssa_35 = load_const (0x88888889 /* -0.000000 */) vec1 32 ssa_35 = load_const (0x88888889 /* -0.000000 */) vec1 32 ssa_36 = umul_high ssa_21, ssa_35 vec1 32 ssa_36 = umul_high ssa_21, ssa_35 vec1 32 ssa_37 = ushr ssa_36, ssa_9 vec1 32 ssa_37 = ushr ssa_36, ssa_9 vec1 32 ssa_38 = imul ssa_15, ssa_12.x vec1 32 ssa_38 = imul ssa_15, ssa_12.x vec1 32 ssa_39 = imul ssa_16, ssa_12.y vec1 32 ssa_39 = imul ssa_16, ssa_12.y vec1 32 ssa_40 = imul ssa_17, ssa_12.z vec1 32 ssa_40 = imul ssa_17, ssa_12.z vec1 32 ssa_41 = iadd ssa_38, ssa_27 vec1 32 ssa_41 = iadd ssa_38, ssa_27 vec1 32 ssa_42 = iadd ssa_39, ssa_34 vec1 32 ssa_42 = iadd ssa_39, ssa_34 vec1 32 ssa_43 = iadd ssa_40, ssa_37 vec1 32 ssa_43 = iadd ssa_40, ssa_37 vec1 32 ssa_44 = imul ssa_11.y, ssa_10 vec1 32 ssa_44 = imul ssa_11.y, ssa_10 vec1 32 ssa_45 = imul ssa_44, ssa_43 vec1 32 ssa_45 = imul ssa_44, ssa_43 vec1 32 ssa_46 = iadd ssa_45, ssa_42 vec1 32 ssa_46 = iadd ssa_45, ssa_42 vec1 32 ssa_47 = imul ssa_11.x, ssa_9 vec1 32 ssa_47 = imul ssa_11.x, ssa_9 vec1 32 ssa_48 = imul ssa_47, ssa_46 vec1 32 ssa_48 = imul ssa_47, ssa_46 vec1 32 ssa_49 = iadd ssa_48, ssa_41 vec1 32 ssa_49 = iadd ssa_48, ssa_41 vec1 32 ssa_50 = iadd ssa_20, ssa_0 vec1 32 ssa_50 = iadd ssa_20, ssa_0 vec1 32 ssa_51 = load_const (0x0000001f /* 0.000000 */) vec1 32 ssa_51 = load_const (0x0000001f /* 0.000000 */) vec1 32 ssa_52 = ineg ssa_20 vec1 32 ssa_52 = ineg ssa_20 vec1 32 ssa_53 = iadd ssa_51, ssa_52 vec1 32 ssa_53 = iadd ssa_51, ssa_52 vec1 32 ssa_54 = ushr ssa_2, ssa_53 vec1 32 ssa_54 = ushr ssa_2, ssa_53 vec1 32 ssa_55 = bit_count ssa_54 vec1 32 ssa_55 = bit_count ssa_54 vec1 32 ssa_56 = ieq32 ssa_50, ssa_55 vec1 32 ssa_56 = ieq32 ssa_50, ssa_55 vec1 32 ssa_57 = b2i32 ssa_56 vec1 32 ssa_57 = b2i32 ssa_56 vec1 32 ssa_58 = ior ssa_57, ssa_30 vec1 32 ssa_58 = ior ssa_57, ssa_30 vec1 32 ssa_59 = intrinsic ballot (ssa_8) () vec1 32 ssa_59 = intrinsic ballot (ssa_8) () vec1 32 ssa_60 = iand ssa_59, ssa_54 vec1 32 ssa_60 = iand ssa_59, ssa_54 vec1 32 ssa_61 = bit_count ssa_60 vec1 32 ssa_61 = bit_count ssa_60 vec1 32 ssa_62 = ult32 ssa_3, ssa_61 vec1 32 ssa_62 = ult32 ssa_3, ssa_61 vec1 32 ssa_63 = b32csel ssa_62, ssa_7, ssa_3 vec1 32 ssa_63 = b32csel ssa_62, ssa_7, ssa_3 vec1 32 ssa_64 = ior ssa_58, ssa_63 vec1 32 ssa_64 = ior ssa_58, ssa_63 vec1 32 ssa_65 = ior ssa_64, ssa_6 vec1 32 ssa_65 = ior ssa_64, ssa_6 /* succs: block_1 */ /* succs: block_1 */ loop { loop { block block_1: block block_1: /* preds: block_0 block_4 */ /* preds: block_0 block_4 */ vec1 32 ssa_66 = phi block_0: ssa_65, block_4: ssa_79 vec1 32 ssa_66 = phi block_0: ssa_65, block_4: ssa_79 vec1 32 ssa_67 = phi block_0: ssa_3, block_4: ssa_80 vec1 32 ssa_67 = phi block_0: ssa_3, block_4: ssa_80 vec1 32 ssa_68 = uge32 ssa_67, ssa_4 vec1 32 ssa_68 = uge32 ssa_67, ssa_4 /* succs: block_2 block_3 */ /* succs: block_2 block_3 */ if ssa_68 { if ssa_68 { block block_2: block block_2: /* preds: block_1 */ /* preds: block_1 */ break break /* succs: block_5 */ /* succs: block_5 */ } else { } else { block block_3: block block_3: /* preds: block_1 */ /* preds: block_1 */ /* succs: block_4 */ /* succs: block_4 */ } } block block_4: block block_4: /* preds: block_3 */ /* preds: block_3 */ vec1 32 ssa_69 = umin ssa_50, ssa_67 vec1 32 ssa_69 = umin ssa_50, ssa_67 vec1 32 ssa_70 = ineg ssa_69 vec1 32 ssa_70 = ineg ssa_69 vec1 32 ssa_71 = iadd ssa_50, ssa_70 vec1 32 ssa_71 = iadd ssa_50, ssa_70 vec1 32 ssa_72 = ishl ssa_2, ssa_67 vec1 32 ssa_72 = ishl ssa_2, ssa_67 vec1 32 ssa_73 = uge32 ssa_67, ssa_5 vec1 32 ssa_73 = uge32 ssa_67, ssa_5 vec1 32 ssa_74 = b32csel ssa_73, ssa_3, ssa_72 vec1 32 ssa_74 = b32csel ssa_73, ssa_3, ssa_72 vec1 32 ssa_75 = iand ssa_74, ssa_54 vec1 32 ssa_75 = iand ssa_74, ssa_54 vec1 32 ssa_76 = bit_count ssa_75 vec1 32 ssa_76 = bit_count ssa_75 vec1 32 ssa_77 = iand ssa_66, ssa_1 vec1 32 ssa_77 = iand ssa_66, ssa_1 vec1 32 ssa_78 = ine32 ssa_76, ssa_71 vec1 32 ssa_78 = ine32 ssa_76, ssa_71 vec1 32 ssa_79 = b32csel ssa_78, ssa_77, ssa_66 vec1 32 ssa_79 = b32csel ssa_78, ssa_77, ssa_66 vec1 32 ssa_80 = iadd ssa_67, ssa_0 vec1 32 ssa_80 = iadd ssa_67, ssa_0 /* succs: block_1 */ /* succs: block_1 */ } } block block_5: block block_5: /* preds: block_2 */ /* preds: block_2 */ vec1 32 ssa_81 = ishl ssa_49, ssa_30 vec1 32 ssa_81 = ishl ssa_49, ssa_30 intrinsic store_ssbo (ssa_66, ssa_30, ssa_81) (1, 0, 4, 0) /* wrmask=x */ /* access=0 */ /* align_mul=4 */ /* intrinsic store_ssbo (ssa_66, ssa_30, ssa_81) (1, 0, 4, 0) /* wrmask=x */ /* access=0 */ /* align_mul=4 */ /* /* succs: block_6 */ /* succs: block_6 */ block block_6: block block_6: } } NIR (final form) for compute shader: NIR (final form) for compute shader: shader: MESA_SHADER_COMPUTE shader: MESA_SHADER_COMPUTE local-size: 3, 5, 7 local-size: 3, 5, 7 shared-size: 0 shared-size: 0 inputs: 0 inputs: 0 outputs: 0 outputs: 0 uniforms: 36 uniforms: 36 shared: 0 shared: 0 decl_var ssbo INTERP_MODE_NONE restrict block @0 (~0, 0, 0) decl_var ssbo INTERP_MODE_NONE restrict block @0 (~0, 0, 0) decl_function main (0 params) decl_function main (0 params) impl main { impl main { decl_reg vec1 32 r3 decl_reg vec1 32 r3 decl_reg vec1 32 r4 decl_reg vec1 32 r4 block block_0: block block_0: /* preds: */ /* preds: */ vec1 32 ssa_0 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_0 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_1 = load_const (0xfffffff7 /* -nan */) vec1 32 ssa_1 = load_const (0xfffffff7 /* -nan */) vec1 32 ssa_2 = load_const (0xffffffff /* -nan */) vec1 32 ssa_2 = load_const (0xffffffff /* -nan */) vec1 32 ssa_3 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_4 = load_const (0x00000080 /* 0.000000 */) vec1 32 ssa_4 = load_const (0x00000080 /* 0.000000 */) vec1 32 ssa_5 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_5 = load_const (0x00000020 /* 0.000000 */) vec1 32 ssa_6 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_6 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_7 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_7 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_8 = load_const (0xffffffff /* -nan */) vec1 32 ssa_8 = load_const (0xffffffff /* -nan */) vec1 32 ssa_9 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_9 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_10 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_10 = load_const (0x00000005 /* 0.000000 */) vec3 32 ssa_11 = intrinsic load_num_work_groups () () vec3 32 ssa_11 = intrinsic load_num_work_groups () () vec3 32 ssa_12 = load_const (0x00000003 /* 0.000000 */, 0x00000005 /* 0.000000 */, 0x00000007 /* 0.000000 */) vec3 32 ssa_12 = load_const (0x00000003 /* 0.000000 */, 0x00000005 /* 0.000000 */, 0x00000007 /* 0.000000 */) vec3 32 ssa_13 = intrinsic load_work_group_id () () vec3 32 ssa_13 = intrinsic load_work_group_id () () vec3 32 ssa_14 = intrinsic load_uniform (ssa_3) (24, 12, 0) /* base=24 */ /* range=12 */ /* dest_type=invalid vec3 32 ssa_14 = intrinsic load_uniform (ssa_3) (24, 12, 0) /* base=24 */ /* range=12 */ /* dest_type=invalid vec1 32 ssa_15 = iadd ssa_13.x, ssa_14.x vec1 32 ssa_15 = iadd ssa_13.x, ssa_14.x vec1 32 ssa_16 = iadd ssa_13.y, ssa_14.y vec1 32 ssa_16 = iadd ssa_13.y, ssa_14.y vec1 32 ssa_17 = iadd ssa_13.z, ssa_14.z vec1 32 ssa_17 = iadd ssa_13.z, ssa_14.z vec1 32 ssa_18 = intrinsic load_subgroup_id () () vec1 32 ssa_18 = intrinsic load_subgroup_id () () vec1 32 ssa_19 = ishl ssa_18, ssa_7 vec1 32 ssa_19 = ishl ssa_18, ssa_7 vec1 32 ssa_20 = intrinsic load_subgroup_invocation () () vec1 32 ssa_20 = intrinsic load_subgroup_invocation () () vec1 32 ssa_21 = iadd ssa_20, ssa_19 vec1 32 ssa_21 = iadd ssa_20, ssa_19 vec1 32 ssa_22 = load_const (0xaaaaaaab /* -0.000000 */) vec1 32 ssa_22 = load_const (0xaaaaaaab /* -0.000000 */) vec1 32 ssa_23 = umul_high ssa_21, ssa_22 vec1 32 ssa_23 = umul_high ssa_21, ssa_22 vec1 32 ssa_24 = ushr ssa_23, ssa_0 vec1 32 ssa_24 = ushr ssa_23, ssa_0 vec1 32 ssa_25 = imul ssa_24, ssa_9 vec1 32 ssa_25 = imul ssa_24, ssa_9 vec1 32 ssa_26 = ineg ssa_25 vec1 32 ssa_26 = ineg ssa_25 vec1 32 ssa_27 = iadd ssa_21, ssa_26 vec1 32 ssa_27 = iadd ssa_21, ssa_26 vec1 32 ssa_28 = load_const (0xcccccccd /* -107374184.000000 */) vec1 32 ssa_28 = load_const (0xcccccccd /* -107374184.000000 */) vec1 32 ssa_29 = umul_high ssa_24, ssa_28 vec1 32 ssa_29 = umul_high ssa_24, ssa_28 vec1 32 ssa_30 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_30 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_31 = ushr ssa_29, ssa_30 vec1 32 ssa_31 = ushr ssa_29, ssa_30 vec1 32 ssa_32 = imul ssa_31, ssa_10 vec1 32 ssa_32 = imul ssa_31, ssa_10 vec1 32 ssa_33 = ineg ssa_32 vec1 32 ssa_33 = ineg ssa_32 vec1 32 ssa_34 = iadd ssa_24, ssa_33 vec1 32 ssa_34 = iadd ssa_24, ssa_33 vec1 32 ssa_35 = load_const (0x88888889 /* -0.000000 */) vec1 32 ssa_35 = load_const (0x88888889 /* -0.000000 */) vec1 32 ssa_36 = umul_high ssa_21, ssa_35 vec1 32 ssa_36 = umul_high ssa_21, ssa_35 vec1 32 ssa_37 = ushr ssa_36, ssa_9 vec1 32 ssa_37 = ushr ssa_36, ssa_9 vec1 32 ssa_38 = imul ssa_15, ssa_12.x vec1 32 ssa_38 = imul ssa_15, ssa_12.x vec1 32 ssa_39 = imul ssa_16, ssa_12.y vec1 32 ssa_39 = imul ssa_16, ssa_12.y vec1 32 ssa_40 = imul ssa_17, ssa_12.z vec1 32 ssa_40 = imul ssa_17, ssa_12.z vec1 32 ssa_41 = iadd ssa_38, ssa_27 vec1 32 ssa_41 = iadd ssa_38, ssa_27 vec1 32 ssa_42 = iadd ssa_39, ssa_34 vec1 32 ssa_42 = iadd ssa_39, ssa_34 vec1 32 ssa_43 = iadd ssa_40, ssa_37 vec1 32 ssa_43 = iadd ssa_40, ssa_37 vec1 32 ssa_44 = imul ssa_11.y, ssa_10 vec1 32 ssa_44 = imul ssa_11.y, ssa_10 vec1 32 ssa_45 = imul ssa_44, ssa_43 vec1 32 ssa_45 = imul ssa_44, ssa_43 vec1 32 ssa_46 = iadd ssa_45, ssa_42 vec1 32 ssa_46 = iadd ssa_45, ssa_42 vec1 32 ssa_47 = imul ssa_11.x, ssa_9 vec1 32 ssa_47 = imul ssa_11.x, ssa_9 vec1 32 ssa_48 = imul ssa_47, ssa_46 vec1 32 ssa_48 = imul ssa_47, ssa_46 vec1 32 ssa_49 = iadd ssa_48, ssa_41 vec1 32 ssa_49 = iadd ssa_48, ssa_41 vec1 32 ssa_50 = iadd ssa_20, ssa_0 vec1 32 ssa_50 = iadd ssa_20, ssa_0 vec1 32 ssa_51 = load_const (0x0000001f /* 0.000000 */) vec1 32 ssa_51 = load_const (0x0000001f /* 0.000000 */) vec1 32 ssa_52 = ineg ssa_20 vec1 32 ssa_52 = ineg ssa_20 vec1 32 ssa_53 = iadd ssa_51, ssa_52 vec1 32 ssa_53 = iadd ssa_51, ssa_52 vec1 32 ssa_54 = ushr ssa_2, ssa_53 vec1 32 ssa_54 = ushr ssa_2, ssa_53 vec1 32 ssa_55 = bit_count ssa_54 vec1 32 ssa_55 = bit_count ssa_54 vec1 32 ssa_56 = ieq32 ssa_50, ssa_55 vec1 32 ssa_56 = ieq32 ssa_50, ssa_55 vec1 32 ssa_57 = b2i32 ssa_56 vec1 32 ssa_57 = b2i32 ssa_56 vec1 32 ssa_58 = ior ssa_57, ssa_30 vec1 32 ssa_58 = ior ssa_57, ssa_30 vec1 32 ssa_59 = intrinsic ballot (ssa_8) () vec1 32 ssa_59 = intrinsic ballot (ssa_8) () vec1 32 ssa_60 = iand ssa_59, ssa_54 vec1 32 ssa_60 = iand ssa_59, ssa_54 vec1 32 ssa_61 = bit_count ssa_60 vec1 32 ssa_61 = bit_count ssa_60 vec1 32 ssa_62 = ult32 ssa_3, ssa_61 vec1 32 ssa_62 = ult32 ssa_3, ssa_61 vec1 32 ssa_63 = b32csel ssa_62, ssa_7, ssa_3 vec1 32 ssa_63 = b32csel ssa_62, ssa_7, ssa_3 vec1 32 ssa_64 = ior ssa_58, ssa_63 vec1 32 ssa_64 = ior ssa_58, ssa_63 r3 = ior ssa_64, ssa_6 r3 = ior ssa_64, ssa_6 r4 = mov ssa_3 r4 = mov ssa_3 /* succs: block_1 */ /* succs: block_1 */ loop { loop { block block_1: block block_1: /* preds: block_0 block_4 */ /* preds: block_0 block_4 */ vec1 32 ssa_68 = uge32 r4, ssa_4 vec1 32 ssa_68 = uge32 r4, ssa_4 /* succs: block_2 block_3 */ /* succs: block_2 block_3 */ if ssa_68 { if ssa_68 { block block_2: block block_2: /* preds: block_1 */ /* preds: block_1 */ break break /* succs: block_5 */ /* succs: block_5 */ } else { } else { block block_3: block block_3: /* preds: block_1 */ /* preds: block_1 */ /* succs: block_4 */ /* succs: block_4 */ } } block block_4: block block_4: /* preds: block_3 */ /* preds: block_3 */ vec1 32 ssa_69 = umin ssa_50, r4 vec1 32 ssa_69 = umin ssa_50, r4 vec1 32 ssa_70 = ineg ssa_69 vec1 32 ssa_70 = ineg ssa_69 vec1 32 ssa_71 = iadd ssa_50, ssa_70 vec1 32 ssa_71 = iadd ssa_50, ssa_70 vec1 32 ssa_72 = ishl ssa_2, r4 vec1 32 ssa_72 = ishl ssa_2, r4 vec1 32 ssa_73 = uge32 r4, ssa_5 vec1 32 ssa_73 = uge32 r4, ssa_5 vec1 32 ssa_74 = b32csel ssa_73, ssa_3, ssa_72 vec1 32 ssa_74 = b32csel ssa_73, ssa_3, ssa_72 vec1 32 ssa_75 = iand ssa_74, ssa_54 vec1 32 ssa_75 = iand ssa_74, ssa_54 vec1 32 ssa_76 = bit_count ssa_75 vec1 32 ssa_76 = bit_count ssa_75 vec1 32 ssa_77 = iand r3, ssa_1 vec1 32 ssa_77 = iand r3, ssa_1 vec1 32 ssa_78 = ine32 ssa_76, ssa_71 vec1 32 ssa_78 = ine32 ssa_76, ssa_71 r3 = b32csel ssa_78, ssa_77, r3 r3 = b32csel ssa_78, ssa_77, r3 r4 = iadd r4, ssa_0 r4 = iadd r4, ssa_0 /* succs: block_1 */ /* succs: block_1 */ } } block block_5: block block_5: /* preds: block_2 */ /* preds: block_2 */ vec1 32 ssa_81 = ishl ssa_49, ssa_30 vec1 32 ssa_81 = ishl ssa_49, ssa_30 intrinsic store_ssbo (r3, ssa_30, ssa_81) (1, 0, 4, 0) /* wrmask=x */ /* access=0 */ /* align_mul=4 */ /* ali intrinsic store_ssbo (r3, ssa_30, ssa_81) (1, 0, 4, 0) /* wrmask=x */ /* access=0 */ /* align_mul=4 */ /* ali /* succs: block_6 */ /* succs: block_6 */ block block_6: block block_6: } } Native code for unnamed compute shader (null) (sha1 feea8666c241b8fb68825310cee8aa94057ae22e) | Native code for unnamed compute shader (null) (sha1 55027072ea4ba97ce3181014272911eda6ca39a8) SIMD16 shader: 88 instructions. 1 loops. 1858 cycles. 0:0 spills:fills, 3 sends, scheduled with mode top-down. Promot | SIMD16 shader: 87 instructions. 1 loops. 1772 cycles. 0:0 spills:fills, 3 sends, scheduled with mode top-down. Promot START B0 (508 cycles) | START B0 (502 cycles) mov(8) g3<1>UW 0x76543210V { align1 WE_all 1Q }; mov(8) g3<1>UW 0x76543210V { align1 WE_all 1Q }; mov(16) g106<1>UD g0.1<0,1,0>UD { align1 1H compacted }; | mov(16) g104<1>UD g0.1<0,1,0>UD { align1 1H compacted }; mov(16) g108<1>UD g0.6<0,1,0>UD { align1 1H }; | mov(16) g106<1>UD g0.6<0,1,0>UD { align1 1H }; mov(16) g4<1>UD g0.7<0,1,0>UD { align1 1H }; mov(16) g4<1>UD g0.7<0,1,0>UD { align1 1H }; mov(16) g6<1>UD 0xffffffffUD { align1 1H compacted }; mov(16) g6<1>UD 0xffffffffUD { align1 1H compacted }; mov(16) g8<1>UD 0xffffffffUD { align1 1H compacted }; | mov(16) g108<1>UD 0x00000000UD { align1 1H compacted }; mov(16) g110<1>UD 0x00000000UD { align1 1H compacted }; < add(8) g3.8<1>UW g3<8,8,1>UW 0x0008UW { align1 WE_all 1Q }; add(8) g3.8<1>UW g3<8,8,1>UW 0x0008UW { align1 WE_all 1Q }; send(16) g10<1>UW g110<0,1,0>UD 0x04605800 | send(16) g8<1>UW g108<0,1,0>UD 0x04605800 dp data 1 MsgDesc: ( untyped surface read, Surface = 0, SIMD16, Mask = 0x8) mlen 2 rlen 6 dp data 1 MsgDesc: ( untyped surface read, Surface = 0, SIMD16, Mask = 0x8) mlen 2 rlen 6 add(16) g16<1>D g106<8,8,1>D g1.6<0,1,0>D { align1 1H compacted }; | add(16) g14<1>D g104<8,8,1>D g1.6<0,1,0>D { align1 1H compacted }; add(16) g18<1>D g108<8,8,1>D g1.7<0,1,0>D { align1 1H compacted }; | add(16) g16<1>D g106<8,8,1>D g1.7<0,1,0>D { align1 1H compacted }; add(16) g20<1>D g4<8,8,1>D g2<0,1,0>D { align1 1H compacted }; | add(16) g18<1>D g4<8,8,1>D g2<0,1,0>D { align1 1H compacted }; shl(16) g22<1>D g2.1<0,1,0>D 0x00000004UD { align1 1H }; | shl(16) g20<1>D g2.1<0,1,0>D 0x00000004UD { align1 1H }; mov(16) g24<1>D g3<8,8,1>UW { align1 1H }; | mov(16) g22<1>D g3<8,8,1>UW { align1 1H }; mul(16) g47<1>D g16<8,8,1>D 3W { align1 1H }; | mov(1) g1.1<1>D 1D { align1 WE_all 1N }; mul(16) g49<1>D g18<8,8,1>D 5W { align1 1H }; | mul(16) g45<1>D g14<8,8,1>D 3W { align1 1H }; mul(16) g51<1>D g20<8,8,1>D 7W { align1 1H }; | mul(16) g47<1>D g16<8,8,1>D 5W { align1 1H }; add(16) g26<1>D g24<8,8,1>D g22<8,8,1>D { align1 1H compacted }; | mul(16) g49<1>D g18<8,8,1>D 7W { align1 1H }; add(16) g71<1>D g24<8,8,1>D 1D { align1 1H compacted }; | add(16) g24<1>D g22<8,8,1>D g20<8,8,1>D { align1 1H compacted }; add(16) g73<1>D -g24<8,8,1>D 31D { align1 1H compacted }; | add(16) g69<1>D g22<8,8,1>D 1D { align1 1H compacted }; mov(1) g4<2>UW 0x00000000UD { align1 WE_all 1N }; | add(16) g71<1>D -g22<8,8,1>D 31D { align1 1H compacted }; mul(8) acc0<1>UD g26<8,8,1>UD 0xaaabUW { align1 1Q }; | mov(1) g5<2>UW 0x00000000UD { align1 WE_all 1N }; shr(16) g75<1>UD g6<8,8,1>UD g73<8,8,1>UD { align1 1H compacted }; | mul(8) acc0<1>UD g24<8,8,1>UD 0xaaabUW { align1 1Q }; mach(8) g28<1>UD g26<8,8,1>UD 0xaaaaaaabUD { align1 1Q AccWrEnable }; | shr(16) g73<1>D -g1.1<0,1,0>D g71<8,8,1>D { align1 1H compacted }; cbit(16) g77<1>UD g75<8,8,1>UD { align1 1H compacted }; | mach(8) g26<1>UD g24<8,8,1>UD 0xaaaaaaabUD { align1 1Q AccWrEnable }; mul(8) acc0<1>UD g27<8,8,1>UD 0xaaabUW { align1 2Q }; | cbit(16) g75<1>UD g73<8,8,1>UD { align1 1H compacted }; cmp.z.f0.0(16) g79<1>D g71<8,8,1>D g77<8,8,1>D { align1 1H compacted }; | mul(8) acc0<1>UD g25<8,8,1>UD 0xaaabUW { align1 2Q }; mach(8) g29<1>UD g27<8,8,1>UD 0xaaaaaaabUD { align1 2Q AccWrEnable }; | cmp.z.f0.0(16) g77<1>D g69<8,8,1>D g75<8,8,1>D { align1 1H compacted }; mov(16) g81<1>D -g79<8,8,1>D { align1 1H compacted }; | mach(8) g27<1>UD g25<8,8,1>UD 0xaaaaaaabUD { align1 2Q AccWrEnable }; shr(16) g30<1>UD g28<8,8,1>UD 0x00000001UD { align1 1H compacted }; | mov(16) g79<1>D -g77<8,8,1>D { align1 1H compacted }; or(16) g83<1>UD g81<8,8,1>UD 0x00000002UD { align1 1H compacted }; | shr(16) g28<1>UD g26<8,8,1>UD 0x00000001UD { align1 1H compacted }; mul(16) g32<1>D g30<8,8,1>D 3W { align1 1H }; | or(16) g81<1>UD g79<8,8,1>UD 0x00000002UD { align1 1H compacted }; mul(8) acc0<1>UD g30<8,8,1>UD 0xcccdUW { align1 1Q }; | mul(16) g30<1>D g28<8,8,1>D 3W { align1 1H }; add(16) g34<1>D g26<8,8,1>D -g32<8,8,1>D { align1 1H compacted }; | mul(8) acc0<1>UD g28<8,8,1>UD 0xcccdUW { align1 1Q }; mach(8) g36<1>UD g30<8,8,1>UD 0xcccccccdUD { align1 1Q AccWrEnable }; | add(16) g32<1>D g24<8,8,1>D -g30<8,8,1>D { align1 1H compacted }; add(16) g53<1>D g47<8,8,1>D g34<8,8,1>D { align1 1H compacted }; | mach(8) g34<1>UD g28<8,8,1>UD 0xcccccccdUD { align1 1Q AccWrEnable }; mul(8) acc0<1>UD g31<8,8,1>UD 0xcccdUW { align1 2Q }; | add(16) g51<1>D g45<8,8,1>D g32<8,8,1>D { align1 1H compacted }; mach(8) g37<1>UD g31<8,8,1>UD 0xcccccccdUD { align1 2Q AccWrEnable }; | mul(8) acc0<1>UD g29<8,8,1>UD 0xcccdUW { align1 2Q }; shr(16) g38<1>UD g36<8,8,1>UD 0x00000002UD { align1 1H compacted }; | mach(8) g35<1>UD g29<8,8,1>UD 0xcccccccdUD { align1 2Q AccWrEnable }; mul(8) acc0<1>UD g26<8,8,1>UD 0x8889UW { align1 1Q }; | shr(16) g36<1>UD g34<8,8,1>UD 0x00000002UD { align1 1H compacted }; mul(16) g40<1>D g38<8,8,1>D 5W { align1 1H }; | mul(8) acc0<1>UD g24<8,8,1>UD 0x8889UW { align1 1Q }; mach(8) g44<1>UD g26<8,8,1>UD 0x88888889UD { align1 1Q AccWrEnable }; | mul(16) g38<1>D g36<8,8,1>D 5W { align1 1H }; add(16) g42<1>D g30<8,8,1>D -g40<8,8,1>D { align1 1H compacted }; | mach(8) g42<1>UD g24<8,8,1>UD 0x88888889UD { align1 1Q AccWrEnable }; mul(8) acc0<1>UD g27<8,8,1>UD 0x8889UW { align1 2Q }; | add(16) g40<1>D g28<8,8,1>D -g38<8,8,1>D { align1 1H compacted }; add(16) g55<1>D g49<8,8,1>D g42<8,8,1>D { align1 1H compacted }; | mul(8) acc0<1>UD g25<8,8,1>UD 0x8889UW { align1 2Q }; mach(8) g45<1>UD g27<8,8,1>UD 0x88888889UD { align1 2Q AccWrEnable }; | add(16) g53<1>D g47<8,8,1>D g40<8,8,1>D { align1 1H compacted }; shr(16) g46<1>UD g44<8,8,1>UD 0x00000003UD { align1 1H compacted }; | mach(8) g43<1>UD g25<8,8,1>UD 0x88888889UD { align1 2Q AccWrEnable }; add(16) g57<1>D g51<8,8,1>D g46<8,8,1>D { align1 1H compacted }; | shr(16) g44<1>UD g42<8,8,1>UD 0x00000003UD { align1 1H compacted }; mul(16) g59<1>D g12<8,8,1>D 5W { align1 1H }; | mul(16) g57<1>D g10<8,8,1>D 5W { align1 1H }; mul(16) g65<1>D g10<8,8,1>D 3W { align1 1H }; | mul(16) g63<1>D g8<8,8,1>D 3W { align1 1H }; mul(16) g61<1>D g59<8,8,1>D g57<16,8,2>UW { align1 1H }; | add(16) g55<1>D g49<8,8,1>D g44<8,8,1>D { align1 1H compacted }; mul(16) g1<1>D g59<8,8,1>D g57.1<16,8,2>UW { align1 1H }; | mul(16) g59<1>D g57<8,8,1>D g55<16,8,2>UW { align1 1H }; add(16) g61.1<2>UW g61.1<16,8,2>UW g1<16,8,2>UW { align1 1H }; | mul(16) g2<1>D g57<8,8,1>D g55.1<16,8,2>UW { align1 1H }; add(16) g63<1>D g61<8,8,1>D g55<8,8,1>D { align1 1H compacted }; | add(16) g59.1<2>UW g59.1<16,8,2>UW g2<16,8,2>UW { align1 1H }; mul(16) g67<1>D g65<8,8,1>D g63<16,8,2>UW { align1 1H }; | add(16) g61<1>D g59<8,8,1>D g53<8,8,1>D { align1 1H compacted }; mul(16) g2<1>D g65<8,8,1>D g63.1<16,8,2>UW { align1 1H }; | mul(16) g65<1>D g63<8,8,1>D g61<16,8,2>UW { align1 1H }; add(16) g67.1<2>UW g67.1<16,8,2>UW g2<16,8,2>UW { align1 1H }; | mul(16) g3<1>D g63<8,8,1>D g61.1<16,8,2>UW { align1 1H }; add(16) g69<1>D g67<8,8,1>D g53<8,8,1>D { align1 1H compacted }; | add(16) g65.1<2>UW g65.1<16,8,2>UW g3<16,8,2>UW { align1 1H }; mov(1) f0<1>UW g4<0,1,0>UW { align1 WE_all 1N }; | add(16) g67<1>D g65<8,8,1>D g51<8,8,1>D { align1 1H compacted }; cmp.nz.f0.0(16) null<1>UD g8<8,8,1>UD 0x00000000UD { align1 1H compacted }; | mov(1) f0<1>UW g5<0,1,0>UW { align1 WE_all 1N }; mov(16) g85<1>UD f0<0,1,0>UW { align1 1H }; | cmp.nz.f0.0(16) null<1>UD g6<8,8,1>UD 0x00000000UD { align1 1H compacted }; > mov(16) g83<1>UD f0<0,1,0>UW { align1 1H }; mov(1) g1<1>UD 0x00000000UD { align1 WE_all 1N compacted }; mov(1) g1<1>UD 0x00000000UD { align1 WE_all 1N compacted }; mov(16) g5<1>UD 0x00000000UD { align1 1H compacted }; mov(16) g5<1>UD 0x00000000UD { align1 1H compacted }; and(16) g87<1>UD g85<8,8,1>UD g75<8,8,1>UD { align1 1H compacted }; | and(16) g85<1>UD g83<8,8,1>UD g73<8,8,1>UD { align1 1H compacted }; cbit(16) g89<1>UD g87<8,8,1>UD { align1 1H compacted }; | cbit(16) g87<1>UD g85<8,8,1>UD { align1 1H compacted }; cmp.g.f0.0(16) null<1>UD g89<8,8,1>UD 0x00000000UD { align1 1H compacted }; | cmp.g.f0.0(16) null<1>UD g87<8,8,1>UD 0x00000000UD { align1 1H compacted }; (-f0.0) sel(16) g90<1>UD g1<0,1,0>UD 0x00000004UD { align1 1H }; | (-f0.0) sel(16) g88<1>UD g1<0,1,0>UD 0x00000004UD { align1 1H }; or(16) g92<1>UD g83<8,8,1>UD g90<8,8,1>UD { align1 1H compacted }; | or(16) g90<1>UD g81<8,8,1>UD g88<8,8,1>UD { align1 1H compacted }; or(16) g113<1>UD g92<8,8,1>UD 0x00000008UD { align1 1H compacted }; | or(16) g111<1>UD g90<8,8,1>UD 0x00000008UD { align1 1H compacted }; END B0 ->B1 END B0 ->B1 START B2 <-B1 <-B3 (260 cycles) START B2 <-B1 <-B3 (260 cycles) LABEL1: LABEL1: cmp.ge.f0.0(16) null<1>UD g5<8,8,1>UD 0x00000080UD { align1 1H compacted }; cmp.ge.f0.0(16) null<1>UD g5<8,8,1>UD 0x00000080UD { align1 1H compacted }; END B1 ->B2 ->B4 END B1 ->B2 ->B4 (+f0.0) break(16) JIP: LABEL0 UIP: LABEL0 { align1 1H }; (+f0.0) break(16) JIP: LABEL0 UIP: LABEL0 { align1 1H }; END B2 ->B1 ->B4 ->B3 END B2 ->B1 ->B4 ->B3 START B3 <-B2 (1060 cycles) | START B3 <-B2 (980 cycles) sel.l(16) g93<1>UD g71<8,8,1>UD g5<8,8,1>UD { align1 1H compacted }; | sel.l(16) g91<1>UD g69<8,8,1>UD g5<8,8,1>UD { align1 1H compacted }; mov(1) g1.1<1>D 1D { align1 WE_all 1N }; | shl(16) g95<1>D -g1.1<0,1,0>D g5<8,8,1>UD { align1 1H }; cmp.ge.f0.0(16) null<1>UD g5<8,8,1>UD 0x00000020UD { align1 1H compacted }; cmp.ge.f0.0(16) null<1>UD g5<8,8,1>UD 0x00000020UD { align1 1H compacted }; and(16) g105<1>UD g113<8,8,1>UD 0xfffffff7UD { align1 1H compacted }; | and(16) g103<1>UD g111<8,8,1>UD 0xfffffff7UD { align1 1H compacted }; add(16) g95<1>D g71<8,8,1>D -g93<8,8,1>D { align1 1H compacted }; < shl(16) g97<1>D -g1.1<0,1,0>D g5<8,8,1>UD { align1 1H }; < add(16) g5<1>D g5<8,8,1>D 1D { align1 1H compacted }; add(16) g5<1>D g5<8,8,1>D 1D { align1 1H compacted }; (-f0.0) sel(16) g99<1>UD g97<8,8,1>UD 0x00000000UD { align1 1H }; | add(16) g93<1>D g69<8,8,1>D -g91<8,8,1>D { align1 1H compacted }; and(16) g101<1>UD g99<8,8,1>UD g75<8,8,1>UD { align1 1H compacted }; | (-f0.0) sel(16) g97<1>UD g95<8,8,1>UD 0x00000000UD { align1 1H }; cbit(16) g103<1>UD g101<8,8,1>UD { align1 1H compacted }; | and(16) g99<1>UD g97<8,8,1>UD g73<8,8,1>UD { align1 1H compacted }; cmp.nz.f0.0(16) null<1>D g103<8,8,1>D g95<8,8,1>D { align1 1H compacted }; | cbit(16) g101<1>UD g99<8,8,1>UD { align1 1H compacted }; (+f0.0) sel(16) g113<1>UD g105<8,8,1>UD g113<8,8,1>UD { align1 1H compacted }; | cmp.nz.f0.0(16) null<1>D g101<8,8,1>D g93<8,8,1>D { align1 1H compacted }; > (+f0.0) sel(16) g111<1>UD g103<8,8,1>UD g111<8,8,1>UD { align1 1H compacted }; LABEL0: LABEL0: while(16) JIP: LABEL1 { align1 1H }; while(16) JIP: LABEL1 { align1 1H }; END B3 ->B2 END B3 ->B2 START B4 <-B1 <-B2 (30 cycles) START B4 <-B1 <-B2 (30 cycles) shl(16) g111<1>D g69<8,8,1>D 0x00000002UD { align1 1H }; | shl(16) g109<1>D g67<8,8,1>D 0x00000002UD { align1 1H }; sends(16) nullUD g111UD g113UD 0x04025e02 0x00000080 | sends(16) nullUD g109UD g111UD 0x04025e02 0x00000080 dp data 1 MsgDesc: ( DC untyped surface write, Surface = 2, SIMD16, Mask = 0xe) mlen 2 ex dp data 1 MsgDesc: ( DC untyped surface write, Surface = 2, SIMD16, Mask = 0xe) mlen 2 ex mov(8) g126<1>UD g0<8,8,1>UD { align1 WE_all 1Q compacted }; mov(8) g126<1>UD g0<8,8,1>UD { align1 WE_all 1Q compacted }; send(16) null<1>UW g126<8,8,1>UW 0x82000000 send(16) null<1>UW g126<8,8,1>UW 0x82000000 thread_spawner MsgDesc: mlen 1 rlen 0 { align1 WE_all 1H EOT }; thread_spawner MsgDesc: mlen 1 rlen 0 { align1 WE_all 1H EOT }; END B4 END B4