NIR (SSA form) for fragment shader: NIR (SSA form) for fragment shader: shader: MESA_SHADER_FRAGMENT shader: MESA_SHADER_FRAGMENT source_sha1: {0x1da57d93, 0x547dbabd, 0x9f4fbbfa, 0x748d12cc, 0xac6d7518} source_sha1: {0x1da57d93, 0x547dbabd, 0x9f4fbbfa, 0x748d12cc, 0xac6d7518} stage: 4 stage: 4 next_stage: 0 next_stage: 0 num_ubos: 1 num_ubos: 1 num_ssbos: 2 num_ssbos: 2 system_values_read: 0x00000000'00000000'00080000 system_values_read: 0x00000000'00000000'00080000 subgroup_size: 0 subgroup_size: 0 divergence_analysis_run: true divergence_analysis_run: true bit_sizes_float: 0x20 bit_sizes_float: 0x20 bit_sizes_int: 0x61 bit_sizes_int: 0x61 writes_memory: true writes_memory: true origin_upper_left: true origin_upper_left: true inputs: 0 inputs: 0 outputs: 0 outputs: 0 uniforms: 0 uniforms: 0 decl_var ssbo INTERP_MODE_NONE restrict Storage1 (~0, 0, 1) decl_var ssbo INTERP_MODE_NONE restrict Storage1 (~0, 0, 1) decl_var ubo INTERP_MODE_NONE block @0 (~0, 0, 3) decl_var ubo INTERP_MODE_NONE block @0 (~0, 0, 3) decl_var ssbo INTERP_MODE_NONE restrict Storage0 @1 (~0, 0, 0) decl_var ssbo INTERP_MODE_NONE restrict Storage0 @1 (~0, 0, 0) decl_function main (0 params) decl_function main (0 params) impl main { impl main { block block_0: block block_0: /* preds: */ /* preds: */ vec1 32 con ssa_0 = load_const (0x00000000 = 0.000000) vec1 32 con ssa_0 = load_const (0x00000000 = 0.000000) vec1 32 con ssa_1 = load_const (0x00000002 = 0.000000) vec1 32 con ssa_1 = load_const (0x00000002 = 0.000000) vec1 32 con ssa_2 = load_const (0x00000001 = 0.000000) vec1 32 con ssa_2 = load_const (0x00000001 = 0.000000) vec1 32 con ssa_3 = load_const (0x00000010 = 0.000000) vec1 32 con ssa_3 = load_const (0x00000010 = 0.000000) vec4 32 con ssa_4 = intrinsic load_ubo (ssa_1, ssa_3) (access=0, align_mul=1073741824, align_offset=16, range vec4 32 con ssa_4 = intrinsic load_ubo (ssa_1, ssa_3) (access=0, align_mul=1073741824, align_offset=16, range vec1 32 con ssa_5 = iand ssa_4.y, ssa_2 vec1 32 con ssa_5 = iand ssa_4.y, ssa_2 vec1 32 con ssa_6 = extract_u8 ssa_4.y, ssa_1 vec1 32 con ssa_6 = extract_u8 ssa_4.y, ssa_1 vec4 32 div ssa_7 = intrinsic load_frag_coord () () vec4 32 div ssa_7 = intrinsic load_frag_coord () () vec1 32 div ssa_8 = f2u32 ssa_7.y vec1 32 div ssa_8 = f2u32 ssa_7.y vec1 32 con ssa_9 = load_const (0x0000000d = 0.000000) vec1 32 con ssa_9 = load_const (0x0000000d = 0.000000) vec1 32 div ssa_10 = ishl ssa_8, ssa_9 vec1 32 div ssa_10 = ishl ssa_8, ssa_9 vec1 32 div ssa_11 = f2u32 ssa_7.x vec1 32 div ssa_11 = f2u32 ssa_7.x vec1 32 div ssa_12 = iadd ssa_10, ssa_11 vec1 32 div ssa_12 = iadd ssa_10, ssa_11 vec1 32 div ssa_13 = imul ssa_12, ssa_4.x vec1 32 div ssa_13 = imul ssa_12, ssa_4.x vec1 32 div ssa_14 = imul_32x16 ssa_12, ssa_6 vec1 32 div ssa_14 = imul_32x16 ssa_12, ssa_6 vec1 32 div ssa_15 = iadd ssa_4.z, ssa_12 vec1 32 div ssa_15 = iadd ssa_4.z, ssa_12 vec1 32 con ssa_16 = load_const (0x00000038 = 0.000000) vec1 32 con ssa_16 = load_const (0x00000038 = 0.000000) vec1 64 con ssa_17 = intrinsic load_ubo (ssa_1, ssa_16) (access=0, align_mul=1073741824, align_offset=56, ran vec1 64 con ssa_17 = intrinsic load_ubo (ssa_1, ssa_16) (access=0, align_mul=1073741824, align_offset=56, ran vec1 32 div ssa_18 = ishl ssa_14, ssa_1 vec1 32 div ssa_18 = ishl ssa_14, ssa_1 vec1 32 con ssa_19 = ine32 ssa_5, ssa_0 vec1 32 con ssa_19 = ine32 ssa_5, ssa_0 vec1 32 div ssa_20 = ult32 ssa_15, ssa_4.w vec1 32 div ssa_20 = ult32 ssa_15, ssa_4.w /* succs: block_1 block_5 */ /* succs: block_1 block_5 */ if ssa_20 { if ssa_20 { block block_1: block block_1: /* preds: block_0 */ /* preds: block_0 */ vec1 32 con ssa_21 = load_const (0x00000030 = 0.000000) vec1 32 con ssa_21 = load_const (0x00000030 = 0.000000) vec1 64 con ssa_22 = intrinsic load_ubo (ssa_1, ssa_21) (access=0, align_mul=1073741824, align_offset vec1 64 con ssa_22 = intrinsic load_ubo (ssa_1, ssa_21) (access=0, align_mul=1073741824, align_offset vec1 32 con ssa_23 = load_const (0xfffffffc = -nan) vec1 32 con ssa_23 = load_const (0xfffffffc = -nan) vec1 32 div ssa_24 = iand ssa_13, ssa_23 vec1 32 div ssa_24 = iand ssa_13, ssa_23 vec1 32 con ssa_25 = load_const (0x00000024 = 0.000000) vec1 32 con ssa_25 = load_const (0x00000024 = 0.000000) vec1 32 con ssa_26 = intrinsic load_ubo (ssa_1, ssa_25) (access=0, align_mul=1073741824, align_offset vec1 32 con ssa_26 = intrinsic load_ubo (ssa_1, ssa_25) (access=0, align_mul=1073741824, align_offset vec1 32 con ssa_27 = load_const (0x00000008 = 0.000000) vec1 32 con ssa_27 = load_const (0x00000008 = 0.000000) vec1 32 con ssa_28 = load_const (0x00000007 = 0.000000) vec1 32 con ssa_28 = load_const (0x00000007 = 0.000000) vec1 32 con ssa_29 = iand ssa_4.y, ssa_1 vec1 32 con ssa_29 = iand ssa_4.y, ssa_1 vec1 32 con ssa_30 = ishl ssa_29, ssa_28 vec1 32 con ssa_30 = ishl ssa_29, ssa_28 vec1 32 con ssa_31 = load_const (0x7b000808 = 664776890994587263929995856502063104.000000) vec1 32 con ssa_31 = load_const (0x7b000808 = 664776890994587263929995856502063104.000000) vec1 32 con ssa_32 = ior ssa_31, ssa_30 vec1 32 con ssa_32 = ior ssa_31, ssa_30 vec1 32 con ssa_33 = ishl ssa_5, ssa_27 vec1 32 con ssa_33 = ishl ssa_5, ssa_27 vec1 32 div ssa_34 = iadd ssa_18, ssa_3 | vec1 32 con ssa_34 = load_const (0x00000020 = 0.000000) vec1 32 con ssa_35 = load_const (0x00000020 = 0.000000) | vec1 32 con ssa_35 = unpack_64_2x32_split_x ssa_22 vec1 32 div ssa_36 = iadd ssa_18, ssa_35 | vec1 32 con ssa_36 = unpack_64_2x32_split_y ssa_22 vec1 32 con ssa_37 = unpack_64_2x32_split_x ssa_22 | vec1 32 div ssa_37 = iadd ssa_35, ssa_24 vec1 32 con ssa_38 = unpack_64_2x32_split_y ssa_22 | vec1 32 div ssa_38 = ult32 ssa_37, ssa_35 vec1 32 div ssa_39 = iadd ssa_37, ssa_24 | vec1 32 div ssa_39 = b2i32 ssa_38 vec1 32 div ssa_40 = ult32 ssa_39, ssa_37 | vec1 32 div ssa_40 = iadd ssa_39, ssa_36 vec1 32 div ssa_41 = b2i32 ssa_40 | vec1 64 div ssa_41 = pack_64_2x32_split ssa_37, ssa_40 vec1 32 div ssa_42 = iadd ssa_41, ssa_38 | vec1 32 con ssa_42 = unpack_64_2x32_split_x ssa_17 vec1 64 div ssa_43 = pack_64_2x32_split ssa_39, ssa_42 | vec1 32 con ssa_43 = unpack_64_2x32_split_y ssa_17 vec1 32 con ssa_44 = unpack_64_2x32_split_x ssa_17 | vec1 32 div ssa_44 = iadd ssa_42, ssa_18 vec1 32 con ssa_45 = unpack_64_2x32_split_y ssa_17 | vec1 32 div ssa_45 = ult32 ssa_44, ssa_42 vec1 32 div ssa_46 = iadd ssa_44, ssa_18 | vec1 32 div ssa_46 = b2i32 ssa_45 vec1 32 div ssa_47 = ult32 ssa_46, ssa_44 | vec1 32 div ssa_47 = iadd ssa_46, ssa_43 vec1 32 div ssa_48 = b2i32 ssa_47 | vec1 64 div ssa_48 = pack_64_2x32_split ssa_44, ssa_47 vec1 32 div ssa_49 = iadd ssa_48, ssa_45 | vec1 32 div ssa_49 = iadd3 ssa_3, ssa_18, ssa_42 vec1 64 div ssa_50 = pack_64_2x32_split ssa_46, ssa_49 | vec1 32 div ssa_50 = ult32 ssa_49, ssa_42 vec1 32 div ssa_51 = iadd ssa_44, ssa_34 | vec1 32 div ssa_51 = b2i32 ssa_50 vec1 32 div ssa_52 = ult32 ssa_51, ssa_44 | vec1 32 div ssa_52 = iadd ssa_51, ssa_43 vec1 32 div ssa_53 = b2i32 ssa_52 | vec1 64 div ssa_53 = pack_64_2x32_split ssa_49, ssa_52 vec1 32 div ssa_54 = iadd ssa_53, ssa_45 | vec1 32 div ssa_54 = iadd3 ssa_34, ssa_18, ssa_42 vec1 64 div ssa_55 = pack_64_2x32_split ssa_51, ssa_54 | vec1 32 div ssa_55 = ult32 ssa_54, ssa_42 vec1 32 div ssa_56 = iadd ssa_44, ssa_36 | vec1 32 div ssa_56 = b2i32 ssa_55 vec1 32 div ssa_57 = ult32 ssa_56, ssa_44 | vec1 32 div ssa_57 = iadd ssa_56, ssa_43 vec1 32 div ssa_58 = b2i32 ssa_57 | vec1 64 div ssa_58 = pack_64_2x32_split ssa_54, ssa_57 vec1 32 div ssa_59 = iadd ssa_58, ssa_45 < vec1 64 div ssa_60 = pack_64_2x32_split ssa_56, ssa_59 < /* succs: block_2 block_3 */ /* succs: block_2 block_3 */ if ssa_19 { if ssa_19 { block block_2: block block_2: /* preds: block_1 */ /* preds: block_1 */ vec4 32 div ssa_61 = intrinsic load_global (ssa_43) (access=0, align_mul=4, align_offset=0) | vec4 32 div ssa_59 = intrinsic load_global (ssa_41) (access=0, align_mul=4, align_offset=0) vec1 32 div ssa_62 = imul ssa_61.y, ssa_26 | vec1 32 div ssa_60 = imul ssa_59.y, ssa_26 vec1 32 div ssa_63 = iadd ssa_24, ssa_3 | vec1 32 div ssa_61 = iadd3 ssa_3, ssa_24, ssa_35 vec1 32 div ssa_64 = iadd ssa_37, ssa_63 | vec1 32 div ssa_62 = ult32 ssa_61, ssa_35 vec1 32 div ssa_65 = ult32 ssa_64, ssa_37 | vec1 32 div ssa_63 = b2i32 ssa_62 vec1 32 div ssa_66 = b2i32 ssa_65 | vec1 32 div ssa_64 = iadd ssa_63, ssa_36 vec1 32 div ssa_67 = iadd ssa_66, ssa_38 | vec1 64 div ssa_65 = pack_64_2x32_split ssa_61, ssa_64 vec1 64 div ssa_68 = pack_64_2x32_split ssa_64, ssa_67 | vec1 32 div ssa_66 = intrinsic load_global (ssa_65) (access=0, align_mul=4, align_offset=0) vec1 32 div ssa_69 = intrinsic load_global (ssa_68) (access=0, align_mul=4, align_offset=0) | vec4 32 div ssa_67 = vec4 ssa_32, ssa_33, ssa_59.x, ssa_59.z vec4 32 div ssa_70 = vec4 ssa_32, ssa_33, ssa_61.x, ssa_61.z | intrinsic store_global (ssa_67, ssa_48) (wrmask=xyzw /*15*/, access=0, align_mul=4, align_off intrinsic store_global (ssa_70, ssa_50) (wrmask=xyzw /*15*/, access=0, align_mul=4, align_off | vec4 32 div ssa_68 = vec4 ssa_60, ssa_66, ssa_59.w, ssa_59.w vec4 32 div ssa_71 = vec4 ssa_62, ssa_69, ssa_61.w, ssa_61.w | intrinsic store_global (ssa_68, ssa_53) (wrmask=xyzw /*15*/, access=0, align_mul=4, align_off intrinsic store_global (ssa_71, ssa_55) (wrmask=xyzw /*15*/, access=0, align_mul=4, align_off | vec2 32 div ssa_69 = vec2 ssa_66, ssa_15 vec2 32 div ssa_72 = vec2 ssa_69, ssa_15 | intrinsic store_global (ssa_69, ssa_58) (wrmask=xy /*3*/, access=0, align_mul=4, align_offset intrinsic store_global (ssa_72, ssa_60) (wrmask=xy /*3*/, access=0, align_mul=4, align_offset < /* succs: block_4 */ /* succs: block_4 */ } else { } else { block block_3: block block_3: /* preds: block_1 */ /* preds: block_1 */ vec4 32 div ssa_73 = intrinsic load_global (ssa_43) (access=0, align_mul=4, align_offset=0) | vec4 32 div ssa_70 = intrinsic load_global (ssa_41) (access=0, align_mul=4, align_offset=0) vec1 32 div ssa_74 = imul ssa_73.y, ssa_26 | vec1 32 div ssa_71 = imul ssa_70.y, ssa_26 vec4 32 div ssa_75 = vec4 ssa_32, ssa_33, ssa_73.x, ssa_73.z | vec4 32 div ssa_72 = vec4 ssa_32, ssa_33, ssa_70.x, ssa_70.z intrinsic store_global (ssa_75, ssa_50) (wrmask=xyzw /*15*/, access=0, align_mul=4, align_off | intrinsic store_global (ssa_72, ssa_48) (wrmask=xyzw /*15*/, access=0, align_mul=4, align_off vec4 32 div ssa_76 = vec4 ssa_74, ssa_73.w, ssa_0, ssa_73.z | vec4 32 div ssa_73 = vec4 ssa_71, ssa_70.w, ssa_0, ssa_70.z intrinsic store_global (ssa_76, ssa_55) (wrmask=xyzw /*15*/, access=0, align_mul=4, align_off | intrinsic store_global (ssa_73, ssa_53) (wrmask=xyzw /*15*/, access=0, align_mul=4, align_off vec2 32 div ssa_77 = vec2 ssa_73.w, ssa_15 | vec2 32 div ssa_74 = vec2 ssa_70.w, ssa_15 intrinsic store_global (ssa_77, ssa_60) (wrmask=xy /*3*/, access=0, align_mul=4, align_offset | intrinsic store_global (ssa_74, ssa_58) (wrmask=xy /*3*/, access=0, align_mul=4, align_offset /* succs: block_4 */ /* succs: block_4 */ } } block block_4: block block_4: /* preds: block_2 block_3 */ /* preds: block_2 block_3 */ /* succs: block_12 */ /* succs: block_12 */ } else { } else { block block_5: block block_5: /* preds: block_0 */ /* preds: block_0 */ vec1 32 div ssa_78 = ieq32 ssa_15, ssa_4.w | vec1 32 div ssa_75 = ieq32 ssa_15, ssa_4.w /* succs: block_6 block_7 */ /* succs: block_6 block_7 */ if ssa_78 { | if ssa_75 { block block_6: block block_6: /* preds: block_5 */ /* preds: block_5 */ vec1 32 con ssa_79 = load_const (0x00000020 = 0.000000) | vec1 32 con ssa_76 = load_const (0x00000020 = 0.000000) vec1 32 con ssa_80 = intrinsic load_ubo (ssa_1, ssa_79) (access=0, align_mul=1073741824, alig | vec1 32 con ssa_77 = intrinsic load_ubo (ssa_1, ssa_76) (access=0, align_mul=1073741824, alig vec1 32 div ssa_81 = ult32 ssa_15, ssa_80 | vec1 32 div ssa_78 = ult32 ssa_15, ssa_77 /* succs: block_8 */ /* succs: block_8 */ } else { } else { block block_7: block block_7: /* preds: block_5 */ /* preds: block_5 */ vec1 32 con ssa_82 = load_const (0x00000000 = 0.000000) | vec1 32 con ssa_79 = load_const (0x00000000 = 0.000000) /* succs: block_8 */ /* succs: block_8 */ } } block block_8: block block_8: /* preds: block_6 block_7 */ /* preds: block_6 block_7 */ vec1 32 div ssa_83 = phi block_6: ssa_81, block_7: ssa_82 | vec1 32 div ssa_80 = phi block_6: ssa_78, block_7: ssa_79 /* succs: block_9 block_10 */ /* succs: block_9 block_10 */ if ssa_83 { | if ssa_80 { block block_9: block block_9: /* preds: block_8 */ /* preds: block_8 */ vec1 32 con ssa_84 = load_const (0x00000028 = 0.000000) | vec1 32 con ssa_81 = load_const (0x00000028 = 0.000000) vec1 64 con ssa_85 = intrinsic load_ubo (ssa_1, ssa_84) (access=0, align_mul=1073741824, alig | vec1 64 con ssa_82 = intrinsic load_ubo (ssa_1, ssa_81) (access=0, align_mul=1073741824, alig vec1 32 con ssa_86 = load_const (0x18800101 = 0.000000) | vec1 32 con ssa_83 = load_const (0x18800101 = 0.000000) vec1 32 con ssa_87 = unpack_64_2x32_split_x ssa_85 | vec1 32 con ssa_84 = unpack_64_2x32_split_x ssa_82 vec1 32 con ssa_88 = unpack_64_2x32_split_y ssa_85 | vec1 32 con ssa_85 = unpack_64_2x32_split_y ssa_82 vec3 32 con ssa_89 = vec3 ssa_86, ssa_87, ssa_88 | vec3 32 con ssa_86 = vec3 ssa_83, ssa_84, ssa_85 vec1 32 con ssa_90 = unpack_64_2x32_split_x ssa_17 | vec1 32 con ssa_87 = unpack_64_2x32_split_x ssa_17 vec1 32 con ssa_91 = unpack_64_2x32_split_y ssa_17 | vec1 32 con ssa_88 = unpack_64_2x32_split_y ssa_17 vec1 32 div ssa_92 = iadd ssa_90, ssa_18 | vec1 32 div ssa_89 = iadd ssa_87, ssa_18 vec1 32 div ssa_93 = ult32 ssa_92, ssa_90 | vec1 32 div ssa_90 = ult32 ssa_89, ssa_87 vec1 32 div ssa_94 = b2i32 ssa_93 | vec1 32 div ssa_91 = b2i32 ssa_90 vec1 32 div ssa_95 = iadd ssa_94, ssa_91 | vec1 32 div ssa_92 = iadd ssa_91, ssa_88 vec1 64 div ssa_96 = pack_64_2x32_split ssa_92, ssa_95 | vec1 64 div ssa_93 = pack_64_2x32_split ssa_89, ssa_92 intrinsic store_global (ssa_89, ssa_96) (wrmask=xyz /*7*/, access=0, align_mul=4, align_offse | intrinsic store_global (ssa_86, ssa_93) (wrmask=xyz /*7*/, access=0, align_mul=4, align_offse /* succs: block_11 */ /* succs: block_11 */ } else { } else { block block_10: block block_10: /* preds: block_8 */ /* preds: block_8 */ /* succs: block_11 */ /* succs: block_11 */ } } block block_11: block block_11: /* preds: block_9 block_10 */ /* preds: block_9 block_10 */ /* succs: block_12 */ /* succs: block_12 */ } } block block_12: block block_12: /* preds: block_4 block_11 */ /* preds: block_4 block_11 */ /* succs: block_13 */ /* succs: block_13 */ block block_13: block block_13: } } NIR (final form) for fragment shader: NIR (final form) for fragment shader: shader: MESA_SHADER_FRAGMENT shader: MESA_SHADER_FRAGMENT source_sha1: {0x1da57d93, 0x547dbabd, 0x9f4fbbfa, 0x748d12cc, 0xac6d7518} source_sha1: {0x1da57d93, 0x547dbabd, 0x9f4fbbfa, 0x748d12cc, 0xac6d7518} stage: 4 stage: 4 next_stage: 0 next_stage: 0 num_ubos: 1 num_ubos: 1 num_ssbos: 2 num_ssbos: 2 system_values_read: 0x00000000'00000000'00080000 system_values_read: 0x00000000'00000000'00080000 subgroup_size: 0 subgroup_size: 0 divergence_analysis_run: true divergence_analysis_run: true bit_sizes_float: 0x20 bit_sizes_float: 0x20 bit_sizes_int: 0x61 bit_sizes_int: 0x61 writes_memory: true writes_memory: true origin_upper_left: true origin_upper_left: true inputs: 0 inputs: 0 outputs: 0 outputs: 0 uniforms: 0 uniforms: 0 decl_var ssbo INTERP_MODE_NONE restrict Storage1 (~0, 0, 1) decl_var ssbo INTERP_MODE_NONE restrict Storage1 (~0, 0, 1) decl_var ubo INTERP_MODE_NONE block @0 (~0, 0, 3) decl_var ubo INTERP_MODE_NONE block @0 (~0, 0, 3) decl_var ssbo INTERP_MODE_NONE restrict Storage0 @1 (~0, 0, 0) decl_var ssbo INTERP_MODE_NONE restrict Storage0 @1 (~0, 0, 0) decl_function main (0 params) decl_function main (0 params) impl main { impl main { decl_reg vec1 32 div r0 decl_reg vec1 32 div r0 block block_0: block block_0: /* preds: */ /* preds: */ vec1 32 con ssa_0 = load_const (0x00000000 = 0.000000) vec1 32 con ssa_0 = load_const (0x00000000 = 0.000000) vec1 32 con ssa_1 = load_const (0x00000002 = 0.000000) vec1 32 con ssa_1 = load_const (0x00000002 = 0.000000) vec1 32 con ssa_2 = load_const (0x00000001 = 0.000000) vec1 32 con ssa_2 = load_const (0x00000001 = 0.000000) vec1 32 con ssa_3 = load_const (0x00000010 = 0.000000) vec1 32 con ssa_3 = load_const (0x00000010 = 0.000000) vec4 32 con ssa_4 = intrinsic load_ubo (ssa_1, ssa_3) (access=0, align_mul=1073741824, align_offset=16, range vec4 32 con ssa_4 = intrinsic load_ubo (ssa_1, ssa_3) (access=0, align_mul=1073741824, align_offset=16, range vec1 32 con ssa_5 = iand ssa_4.y, ssa_2 vec1 32 con ssa_5 = iand ssa_4.y, ssa_2 vec1 32 con ssa_6 = extract_u8 ssa_4.y, ssa_1 vec1 32 con ssa_6 = extract_u8 ssa_4.y, ssa_1 vec4 32 div ssa_7 = intrinsic load_frag_coord () () vec4 32 div ssa_7 = intrinsic load_frag_coord () () vec1 32 div ssa_8 = f2u32 ssa_7.y vec1 32 div ssa_8 = f2u32 ssa_7.y vec1 32 con ssa_9 = load_const (0x0000000d = 0.000000) vec1 32 con ssa_9 = load_const (0x0000000d = 0.000000) vec1 32 div ssa_10 = ishl ssa_8, ssa_9 vec1 32 div ssa_10 = ishl ssa_8, ssa_9 vec1 32 div ssa_11 = f2u32 ssa_7.x vec1 32 div ssa_11 = f2u32 ssa_7.x vec1 32 div ssa_12 = iadd ssa_10, ssa_11 vec1 32 div ssa_12 = iadd ssa_10, ssa_11 vec1 32 div ssa_13 = imul ssa_12, ssa_4.x vec1 32 div ssa_13 = imul ssa_12, ssa_4.x vec1 32 div ssa_14 = imul_32x16 ssa_12, ssa_6 vec1 32 div ssa_14 = imul_32x16 ssa_12, ssa_6 vec1 32 div ssa_15 = iadd ssa_4.z, ssa_12 vec1 32 div ssa_15 = iadd ssa_4.z, ssa_12 vec1 32 con ssa_16 = load_const (0x00000038 = 0.000000) vec1 32 con ssa_16 = load_const (0x00000038 = 0.000000) vec1 64 con ssa_17 = intrinsic load_ubo (ssa_1, ssa_16) (access=0, align_mul=1073741824, align_offset=56, ran vec1 64 con ssa_17 = intrinsic load_ubo (ssa_1, ssa_16) (access=0, align_mul=1073741824, align_offset=56, ran vec1 32 div ssa_18 = ishl ssa_14, ssa_1 vec1 32 div ssa_18 = ishl ssa_14, ssa_1 vec1 32 div ssa_20 = ult32 ssa_15, ssa_4.w vec1 32 div ssa_20 = ult32 ssa_15, ssa_4.w /* succs: block_1 block_5 */ /* succs: block_1 block_5 */ if ssa_20 { if ssa_20 { block block_1: block block_1: /* preds: block_0 */ /* preds: block_0 */ vec1 32 con ssa_21 = load_const (0x00000030 = 0.000000) vec1 32 con ssa_21 = load_const (0x00000030 = 0.000000) vec1 64 con ssa_22 = intrinsic load_ubo (ssa_1, ssa_21) (access=0, align_mul=1073741824, align_offset vec1 64 con ssa_22 = intrinsic load_ubo (ssa_1, ssa_21) (access=0, align_mul=1073741824, align_offset vec1 32 con ssa_23 = load_const (0xfffffffc = -nan) vec1 32 con ssa_23 = load_const (0xfffffffc = -nan) vec1 32 div ssa_24 = iand ssa_13, ssa_23 vec1 32 div ssa_24 = iand ssa_13, ssa_23 vec1 32 con ssa_25 = load_const (0x00000024 = 0.000000) vec1 32 con ssa_25 = load_const (0x00000024 = 0.000000) vec1 32 con ssa_26 = intrinsic load_ubo (ssa_1, ssa_25) (access=0, align_mul=1073741824, align_offset vec1 32 con ssa_26 = intrinsic load_ubo (ssa_1, ssa_25) (access=0, align_mul=1073741824, align_offset vec1 32 con ssa_27 = load_const (0x00000008 = 0.000000) vec1 32 con ssa_27 = load_const (0x00000008 = 0.000000) vec1 32 con ssa_28 = load_const (0x00000007 = 0.000000) vec1 32 con ssa_28 = load_const (0x00000007 = 0.000000) vec1 32 con ssa_29 = iand ssa_4.y, ssa_1 vec1 32 con ssa_29 = iand ssa_4.y, ssa_1 vec1 32 con ssa_30 = ishl ssa_29, ssa_28 vec1 32 con ssa_30 = ishl ssa_29, ssa_28 vec1 32 con ssa_31 = load_const (0x7b000808 = 664776890994587263929995856502063104.000000) vec1 32 con ssa_31 = load_const (0x7b000808 = 664776890994587263929995856502063104.000000) vec1 32 con ssa_32 = ior ssa_31, ssa_30 vec1 32 con ssa_32 = ior ssa_31, ssa_30 vec1 32 con ssa_33 = ishl ssa_5, ssa_27 vec1 32 con ssa_33 = ishl ssa_5, ssa_27 vec1 32 div ssa_34 = iadd ssa_18, ssa_3 | vec1 32 con ssa_34 = load_const (0x00000020 = 0.000000) vec1 32 con ssa_35 = load_const (0x00000020 = 0.000000) | vec1 32 con ssa_35 = unpack_64_2x32_split_x ssa_22 vec1 32 div ssa_36 = iadd ssa_18, ssa_35 | vec1 32 con ssa_36 = unpack_64_2x32_split_y ssa_22 vec1 32 con ssa_37 = unpack_64_2x32_split_x ssa_22 | vec1 32 div ssa_37 = iadd ssa_35, ssa_24 vec1 32 con ssa_38 = unpack_64_2x32_split_y ssa_22 | vec1 32 div ssa_38 = ult32 ssa_37, ssa_35 vec1 32 div ssa_39 = iadd ssa_37, ssa_24 | vec1 32 div ssa_39 = b2i32 ssa_38 vec1 32 div ssa_40 = ult32 ssa_39, ssa_37 | vec1 32 div ssa_40 = iadd ssa_39, ssa_36 vec1 32 div ssa_41 = b2i32 ssa_40 | vec1 64 div ssa_41 = pack_64_2x32_split ssa_37, ssa_40 vec1 32 div ssa_42 = iadd ssa_41, ssa_38 | vec1 32 con ssa_42 = unpack_64_2x32_split_x ssa_17 vec1 64 div ssa_43 = pack_64_2x32_split ssa_39, ssa_42 | vec1 32 con ssa_43 = unpack_64_2x32_split_y ssa_17 vec1 32 con ssa_44 = unpack_64_2x32_split_x ssa_17 | vec1 32 div ssa_44 = iadd ssa_42, ssa_18 vec1 32 con ssa_45 = unpack_64_2x32_split_y ssa_17 | vec1 32 div ssa_45 = ult32 ssa_44, ssa_42 vec1 32 div ssa_46 = iadd ssa_44, ssa_18 | vec1 32 div ssa_46 = b2i32 ssa_45 vec1 32 div ssa_47 = ult32 ssa_46, ssa_44 | vec1 32 div ssa_47 = iadd ssa_46, ssa_43 vec1 32 div ssa_48 = b2i32 ssa_47 | vec1 64 div ssa_48 = pack_64_2x32_split ssa_44, ssa_47 vec1 32 div ssa_49 = iadd ssa_48, ssa_45 | vec1 32 div ssa_49 = iadd3 ssa_3, ssa_18, ssa_42 vec1 64 div ssa_50 = pack_64_2x32_split ssa_46, ssa_49 | vec1 32 div ssa_50 = ult32 ssa_49, ssa_42 vec1 32 div ssa_51 = iadd ssa_44, ssa_34 | vec1 32 div ssa_51 = b2i32 ssa_50 vec1 32 div ssa_52 = ult32 ssa_51, ssa_44 | vec1 32 div ssa_52 = iadd ssa_51, ssa_43 vec1 32 div ssa_53 = b2i32 ssa_52 | vec1 64 div ssa_53 = pack_64_2x32_split ssa_49, ssa_52 vec1 32 div ssa_54 = iadd ssa_53, ssa_45 | vec1 32 div ssa_54 = iadd3 ssa_34, ssa_18, ssa_42 vec1 64 div ssa_55 = pack_64_2x32_split ssa_51, ssa_54 | vec1 32 div ssa_55 = ult32 ssa_54, ssa_42 vec1 32 div ssa_56 = iadd ssa_44, ssa_36 | vec1 32 div ssa_56 = b2i32 ssa_55 vec1 32 div ssa_57 = ult32 ssa_56, ssa_44 | vec1 32 div ssa_57 = iadd ssa_56, ssa_43 vec1 32 div ssa_58 = b2i32 ssa_57 | vec1 64 div ssa_58 = pack_64_2x32_split ssa_54, ssa_57 vec1 32 div ssa_59 = iadd ssa_58, ssa_45 | vec1 32 div ssa_97 = ine32 ssa_5, ssa_0 vec1 64 div ssa_60 = pack_64_2x32_split ssa_56, ssa_59 < vec1 32 div ssa_100 = ine32 ssa_5, ssa_0 < /* succs: block_2 block_3 */ /* succs: block_2 block_3 */ if ssa_100 { | if ssa_97 { block block_2: block block_2: /* preds: block_1 */ /* preds: block_1 */ vec4 32 div ssa_61 = intrinsic load_global (ssa_43) (access=0, align_mul=4, align_offset=0) | vec4 32 div ssa_59 = intrinsic load_global (ssa_41) (access=0, align_mul=4, align_offset=0) vec1 32 div ssa_62 = imul ssa_61.y, ssa_26 | vec1 32 div ssa_60 = imul ssa_59.y, ssa_26 vec1 32 div ssa_63 = iadd ssa_24, ssa_3 | vec1 32 div ssa_61 = iadd3 ssa_3, ssa_24, ssa_35 vec1 32 div ssa_64 = iadd ssa_37, ssa_63 | vec1 32 div ssa_62 = ult32 ssa_61, ssa_35 vec1 32 div ssa_65 = ult32 ssa_64, ssa_37 | vec1 32 div ssa_63 = b2i32 ssa_62 vec1 32 div ssa_66 = b2i32 ssa_65 | vec1 32 div ssa_64 = iadd ssa_63, ssa_36 vec1 32 div ssa_67 = iadd ssa_66, ssa_38 | vec1 64 div ssa_65 = pack_64_2x32_split ssa_61, ssa_64 vec1 64 div ssa_68 = pack_64_2x32_split ssa_64, ssa_67 | vec1 32 div ssa_66 = intrinsic load_global (ssa_65) (access=0, align_mul=4, align_offset=0) vec1 32 div ssa_69 = intrinsic load_global (ssa_68) (access=0, align_mul=4, align_offset=0) | vec4 32 div ssa_67 = vec4 ssa_32, ssa_33, ssa_59.x, ssa_59.z vec4 32 div ssa_70 = vec4 ssa_32, ssa_33, ssa_61.x, ssa_61.z | intrinsic store_global (ssa_67, ssa_48) (wrmask=xyzw /*15*/, access=0, align_mul=4, align_off intrinsic store_global (ssa_70, ssa_50) (wrmask=xyzw /*15*/, access=0, align_mul=4, align_off | vec4 32 div ssa_68 = vec4 ssa_60, ssa_66, ssa_59.w, ssa_59.w vec4 32 div ssa_71 = vec4 ssa_62, ssa_69, ssa_61.w, ssa_61.w | intrinsic store_global (ssa_68, ssa_53) (wrmask=xyzw /*15*/, access=0, align_mul=4, align_off intrinsic store_global (ssa_71, ssa_55) (wrmask=xyzw /*15*/, access=0, align_mul=4, align_off | vec2 32 div ssa_69 = vec2 ssa_66, ssa_15 vec2 32 div ssa_72 = vec2 ssa_69, ssa_15 | intrinsic store_global (ssa_69, ssa_58) (wrmask=xy /*3*/, access=0, align_mul=4, align_offset intrinsic store_global (ssa_72, ssa_60) (wrmask=xy /*3*/, access=0, align_mul=4, align_offset < /* succs: block_4 */ /* succs: block_4 */ } else { } else { block block_3: block block_3: /* preds: block_1 */ /* preds: block_1 */ vec4 32 div ssa_73 = intrinsic load_global (ssa_43) (access=0, align_mul=4, align_offset=0) | vec4 32 div ssa_70 = intrinsic load_global (ssa_41) (access=0, align_mul=4, align_offset=0) vec1 32 div ssa_74 = imul ssa_73.y, ssa_26 | vec1 32 div ssa_71 = imul ssa_70.y, ssa_26 vec4 32 div ssa_75 = vec4 ssa_32, ssa_33, ssa_73.x, ssa_73.z | vec4 32 div ssa_72 = vec4 ssa_32, ssa_33, ssa_70.x, ssa_70.z intrinsic store_global (ssa_75, ssa_50) (wrmask=xyzw /*15*/, access=0, align_mul=4, align_off | intrinsic store_global (ssa_72, ssa_48) (wrmask=xyzw /*15*/, access=0, align_mul=4, align_off vec4 32 div ssa_76 = vec4 ssa_74, ssa_73.w, ssa_0, ssa_73.z | vec4 32 div ssa_73 = vec4 ssa_71, ssa_70.w, ssa_0, ssa_70.z intrinsic store_global (ssa_76, ssa_55) (wrmask=xyzw /*15*/, access=0, align_mul=4, align_off | intrinsic store_global (ssa_73, ssa_53) (wrmask=xyzw /*15*/, access=0, align_mul=4, align_off vec2 32 div ssa_77 = vec2 ssa_73.w, ssa_15 | vec2 32 div ssa_74 = vec2 ssa_70.w, ssa_15 intrinsic store_global (ssa_77, ssa_60) (wrmask=xy /*3*/, access=0, align_mul=4, align_offset | intrinsic store_global (ssa_74, ssa_58) (wrmask=xy /*3*/, access=0, align_mul=4, align_offset /* succs: block_4 */ /* succs: block_4 */ } } block block_4: block block_4: /* preds: block_2 block_3 */ /* preds: block_2 block_3 */ /* succs: block_12 */ /* succs: block_12 */ } else { } else { block block_5: block block_5: /* preds: block_0 */ /* preds: block_0 */ vec1 32 div ssa_78 = ieq32 ssa_15, ssa_4.w | vec1 32 div ssa_75 = ieq32 ssa_15, ssa_4.w /* succs: block_6 block_7 */ /* succs: block_6 block_7 */ if ssa_78 { | if ssa_75 { block block_6: block block_6: /* preds: block_5 */ /* preds: block_5 */ vec1 32 con ssa_79 = load_const (0x00000020 = 0.000000) | vec1 32 con ssa_76 = load_const (0x00000020 = 0.000000) vec1 32 con ssa_80 = intrinsic load_ubo (ssa_1, ssa_79) (access=0, align_mul=1073741824, alig | vec1 32 con ssa_77 = intrinsic load_ubo (ssa_1, ssa_76) (access=0, align_mul=1073741824, alig div r0 = ult32 ssa_15, ssa_80 | div r0 = ult32 ssa_15, ssa_77 /* succs: block_8 */ /* succs: block_8 */ } else { } else { block block_7: block block_7: /* preds: block_5 */ /* preds: block_5 */ vec1 32 con ssa_82 = load_const (0x00000000 = 0.000000) | vec1 32 con ssa_79 = load_const (0x00000000 = 0.000000) div r0 = mov ssa_82 | div r0 = mov ssa_79 /* succs: block_8 */ /* succs: block_8 */ } } block block_8: block block_8: /* preds: block_6 block_7 */ /* preds: block_6 block_7 */ /* succs: block_9 block_10 */ /* succs: block_9 block_10 */ if r0 { if r0 { block block_9: block block_9: /* preds: block_8 */ /* preds: block_8 */ vec1 32 con ssa_84 = load_const (0x00000028 = 0.000000) | vec1 32 con ssa_81 = load_const (0x00000028 = 0.000000) vec1 64 con ssa_85 = intrinsic load_ubo (ssa_1, ssa_84) (access=0, align_mul=1073741824, alig | vec1 64 con ssa_82 = intrinsic load_ubo (ssa_1, ssa_81) (access=0, align_mul=1073741824, alig vec1 32 con ssa_86 = load_const (0x18800101 = 0.000000) | vec1 32 con ssa_83 = load_const (0x18800101 = 0.000000) vec1 32 con ssa_87 = unpack_64_2x32_split_x ssa_85 | vec1 32 con ssa_84 = unpack_64_2x32_split_x ssa_82 vec1 32 con ssa_88 = unpack_64_2x32_split_y ssa_85 | vec1 32 con ssa_85 = unpack_64_2x32_split_y ssa_82 vec3 32 con ssa_89 = vec3 ssa_86, ssa_87, ssa_88 | vec3 32 con ssa_86 = vec3 ssa_83, ssa_84, ssa_85 vec1 32 con ssa_90 = unpack_64_2x32_split_x ssa_17 | vec1 32 con ssa_87 = unpack_64_2x32_split_x ssa_17 vec1 32 con ssa_91 = unpack_64_2x32_split_y ssa_17 | vec1 32 con ssa_88 = unpack_64_2x32_split_y ssa_17 vec1 32 div ssa_92 = iadd ssa_90, ssa_18 | vec1 32 div ssa_89 = iadd ssa_87, ssa_18 vec1 32 div ssa_93 = ult32 ssa_92, ssa_90 | vec1 32 div ssa_90 = ult32 ssa_89, ssa_87 vec1 32 div ssa_94 = b2i32 ssa_93 | vec1 32 div ssa_91 = b2i32 ssa_90 vec1 32 div ssa_95 = iadd ssa_94, ssa_91 | vec1 32 div ssa_92 = iadd ssa_91, ssa_88 vec1 64 div ssa_96 = pack_64_2x32_split ssa_92, ssa_95 | vec1 64 div ssa_93 = pack_64_2x32_split ssa_89, ssa_92 intrinsic store_global (ssa_89, ssa_96) (wrmask=xyz /*7*/, access=0, align_mul=4, align_offse | intrinsic store_global (ssa_86, ssa_93) (wrmask=xyz /*7*/, access=0, align_mul=4, align_offse /* succs: block_11 */ /* succs: block_11 */ } else { } else { block block_10: block block_10: /* preds: block_8 */ /* preds: block_8 */ /* succs: block_11 */ /* succs: block_11 */ } } block block_11: block block_11: /* preds: block_9 block_10 */ /* preds: block_9 block_10 */ /* succs: block_12 */ /* succs: block_12 */ } } block block_12: block block_12: /* preds: block_4 block_11 */ /* preds: block_4 block_11 */ /* succs: block_13 */ /* succs: block_13 */ block block_13: block block_13: } } Native code for unnamed fragment shader (null) (sha1 db8e4999baff460fbe43b649a6e167cdd89fe347) | Native code for unnamed fragment shader (null) (sha1 fc92b97b9e7b042e0d5a70dc1b4ff7b2aa7f5ff8) SIMD8 shader: 133 instructions. 0 loops. 828 cycles. 0:0 spills:fills, 11 sends, scheduled with mode top-down. Promot | SIMD8 shader: 134 instructions. 0 loops. 820 cycles. 0:0 spills:fills, 11 sends, scheduled with mode top-down. Promot START B0 (106 cycles) START B0 (106 cycles) add(16) g9<1>UW g1.4<2,8,0>UW 0x01000100V { align1 WE_all 1H }; add(16) g9<1>UW g1.4<2,8,0>UW 0x01000100V { align1 WE_all 1H }; add(16) g10<1>UW g1.5<2,8,0>UW 0x01010000V { align1 WE_all 1H }; add(16) g10<1>UW g1.5<2,8,0>UW 0x01010000V { align1 WE_all 1H }; mov(8) g56<1>F g4.5<0,1,0>F { align1 1Q compacted }; | mov(8) g12<1>D 16D { align1 1Q }; and(8) g12<1>UD g4.5<0,1,0>UD 0x00000001UD { align1 1Q compacted }; | mov(8) g57<1>F g4.5<0,1,0>F { align1 1Q compacted }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@3 }; | and(8) g13<1>UD g4.5<0,1,0>UD 0x00000001UD { align1 1Q compacted }; > sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@4 }; mov(8) g7<1>F g9<16,8,2>UW { align1 1Q }; mov(8) g7<1>F g9<16,8,2>UW { align1 1Q }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@2 }; | sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@3 }; mov(8) g8<1>F g10<16,8,2>UW { align1 1Q }; mov(8) g8<1>F g10<16,8,2>UW { align1 1Q }; mov(8) g13<1>UD g56.2<32,8,4>UB { align1 1Q F@3 }; | mov(8) g14<1>UD g57.2<32,8,4>UB { align1 1Q F@3 }; mov(8) g20.1<2>F g5.7<0,1,0>F { align1 1Q }; | mov(8) g21.1<2>F g5.7<0,1,0>F { align1 1Q }; mov(8) g16<1>UD g7<8,8,1>F { align1 1Q F@3 }; | mov(8) g17<1>UD g7<8,8,1>F { align1 1Q F@3 }; mov(8) g14<1>UD g8<8,8,1>F { align1 1Q F@2 }; | mov(8) g15<1>UD g8<8,8,1>F { align1 1Q F@2 }; mov(8) g20<2>F g5.6<0,1,0>F { align1 1Q F@1 compacted }; | mov(8) g21<2>F g5.6<0,1,0>F { align1 1Q F@1 compacted }; shl(8) g15<1>D g14<8,8,1>D 0x0000000dUD { align1 1Q I@1 }; | shl(8) g16<1>D g15<8,8,1>D 0x0000000dUD { align1 1Q I@1 }; add(8) g17<1>D g15<1,1,0>D g16<1,1,0>D { align1 1Q I@1 compacted }; | add(8) g18<1>D g16<1,1,0>D g17<1,1,0>D { align1 1Q I@1 compacted }; mul(8) g18<1>D g17<8,8,1>D g4.8<0,1,0>UW { align1 1Q I@1 }; | mul(8) g19<1>D g18<8,8,1>D g4.8<0,1,0>UW { align1 1Q I@1 }; mul(8) g85<1>D g17<8,8,1>D g4.9<0,1,0>UW { align1 1Q }; | mul(8) g86<1>D g18<8,8,1>D g4.9<0,1,0>UW { align1 1Q }; mul(8) g19<1>D g17<8,8,1>D g13<16,8,2>W { align1 1Q I@7 }; | mul(8) g20<1>D g18<8,8,1>D g14<16,8,2>W { align1 1Q I@7 }; add(8) g64<1>D g4.6<0,1,0>D g17<1,1,0>D { align1 1Q compacted }; | add(8) g65<1>D g4.6<0,1,0>D g18<1,1,0>D { align1 1Q compacted }; add(8) g18.1<2>UW g18.1<16,8,2>UW g85<16,8,2>UW { align1 1Q I@3 }; | add(8) g19.1<2>UW g19.1<16,8,2>UW g86<16,8,2>UW { align1 1Q I@3 }; shl(8) g22<1>D g19<8,8,1>D 0x00000002UD { align1 1Q I@3 }; | shl(8) g23<1>D g20<8,8,1>D 0x00000002UD { align1 1Q I@3 }; cmp.l.f0.0(8) null<1>UD g64<8,8,1>UD g4.7<0,1,0>UD { align1 1Q I@3 }; | cmp.l.f0.0(8) null<1>UD g65<8,8,1>UD g4.7<0,1,0>UD { align1 1Q I@3 }; (+f0.0) if(8) JIP: LABEL1 UIP: LABEL0 { align1 1Q }; (+f0.0) if(8) JIP: LABEL1 UIP: LABEL0 { align1 1Q }; END B0 ->B1 ->B5 END B0 ->B1 ->B5 and(8) g25<1>UD g18<8,8,1>UD 0xfffffffcUD { align1 1Q I@4 }; | and(8) g3<1>UD g19<8,8,1>UD 0xfffffffcUD { align1 1Q I@4 }; and(8) g26<1>UD g4.5<0,1,0>UD 0x00000002UD { align1 1Q compacted }; | and(8) g27<1>UD g4.5<0,1,0>UD 0x00000002UD { align1 1Q compacted }; shl(8) g7<1>D g12<8,8,1>D 0x00000008UD { align1 1Q }; | shl(8) g7<1>D g13<8,8,1>D 0x00000008UD { align1 1Q }; add(8) g28<1>D g22<1,1,0>D 16D { align1 1Q I@6 compacted }; | mov(8) g29<1>D 32D { align1 1Q }; add(8) g29<1>D g22<1,1,0>D 32D { align1 1Q compacted }; | mov(8) g34<1>UD g21<8,4,2>UD { align1 1Q F@1 }; add(8) g33<1>D g20<8,4,2>D g22<1,1,0>D { align1 1Q F@1 compacted }; | add(8) g35<1>D g21<8,4,2>D g23<1,1,0>D { align1 1Q I@7 compacted }; mov(8) g23.1<2>F g5.5<0,1,0>F { align1 1Q }; | mov(8) g24.1<2>F g5.5<0,1,0>F { align1 1Q }; shl(8) g27<1>D g26<8,8,1>D 0x00000007UD { align1 1Q I@5 }; | shl(8) g28<1>D g27<8,8,1>D 0x00000007UD { align1 1Q I@5 }; add(8) g36<1>D g20<8,4,2>D g28<1,1,0>D { align1 1Q I@4 compacted }; | add3(8) g38<1>D g34<8,8,1>D g23<8,8,1>D g12<1,1,1>D { align1 1Q I@3 }; add(8) g39<1>D g20<8,4,2>D g29<1,1,0>D { align1 1Q I@4 compacted }; | add3(8) g41<1>D g34<8,8,1>D g23<8,8,1>D g29<1,1,1>D { align1 1Q I@5 }; mov(8) g67<2>UD g33<4,4,1>UD { align1 1Q I@4 }; | mov(8) g68<2>UD g35<4,4,1>UD { align1 1Q I@4 }; mov(8) g23<2>F g5.4<0,1,0>F { align1 1Q F@1 compacted }; | mov(8) g24<2>F g5.4<0,1,0>F { align1 1Q F@1 compacted }; or(8) g6<1>UD g27<8,8,1>UD 0x7b000808UD { align1 1Q I@4 }; | or(8) g6<1>UD g28<8,8,1>UD 0x7b000808UD { align1 1Q I@4 }; mov(8) g73<2>UD g36<4,4,1>UD { align1 1Q I@4 }; | mov(8) g74<2>UD g38<4,4,1>UD { align1 1Q I@4 }; mov(8) g79<2>UD g39<4,4,1>UD { align1 1Q I@4 }; | mov(8) g80<2>UD g41<4,4,1>UD { align1 1Q I@4 }; add(8) g30<1>D g23<8,4,2>D g25<1,1,0>D { align1 1Q F@1 compacted }; | mov(8) g30<1>UD g24<8,4,2>UD { align1 1Q F@1 }; cmp.l.f0.0(8) g31<1>UD g30<8,8,1>UD g23<8,4,2>UD { align1 1Q I@1 }; | add(8) g31<1>D g24<8,4,2>D g3<1,1,0>D { align1 1Q compacted }; mov(8) g65<2>UD g30<4,4,1>UD { align1 1Q }; | cmp.l.f0.0(8) g32<1>UD g31<8,8,1>UD g24<8,4,2>UD { align1 1Q I@1 }; cmp.l.f0.0(8) g34<1>UD g33<8,8,1>UD g20<8,4,2>UD { align1 1Q }; | mov(8) g66<2>UD g31<4,4,1>UD { align1 1Q }; cmp.l.f0.0(8) g37<1>UD g36<8,8,1>UD g20<8,4,2>UD { align1 1Q }; | cmp.l.f0.0(8) g36<1>UD g35<8,8,1>UD g21<8,4,2>UD { align1 1Q }; cmp.l.f0.0(8) g40<1>UD g39<8,8,1>UD g20<8,4,2>UD { align1 1Q }; | cmp.l.f0.0(8) g39<1>UD g38<8,8,1>UD g21<8,4,2>UD { align1 1Q }; cmp.nz.f0.0(8) null<1>D g12<8,8,1>D 0D { align1 1Q }; | cmp.l.f0.0(8) g42<1>UD g41<8,8,1>UD g21<8,4,2>UD { align1 1Q }; add(8) g32<1>D -g31<8,8,1>D g23.1<8,4,2>D { align1 1Q I@6 }; | cmp.nz.f0.0(8) null<1>D g13<8,8,1>D 0D { align1 1Q }; add(8) g35<1>D -g34<8,8,1>D g20.1<8,4,2>D { align1 1Q I@5 }; | add(8) g33<1>D -g32<8,8,1>D g24.1<8,4,2>D { align1 1Q I@6 }; add(8) g38<1>D -g37<8,8,1>D g20.1<8,4,2>D { align1 1Q I@5 }; | add(8) g37<1>D -g36<8,8,1>D g21.1<8,4,2>D { align1 1Q I@5 }; add(8) g41<1>D -g40<8,8,1>D g20.1<8,4,2>D { align1 1Q I@5 }; | add(8) g40<1>D -g39<8,8,1>D g21.1<8,4,2>D { align1 1Q I@5 }; mov(8) g65.1<2>UD g32<4,4,1>UD { align1 1Q I@4 }; | add(8) g43<1>D -g42<8,8,1>D g21.1<8,4,2>D { align1 1Q I@5 }; mov(8) g67.1<2>UD g35<4,4,1>UD { align1 1Q I@4 }; | mov(8) g66.1<2>UD g33<4,4,1>UD { align1 1Q I@4 }; mov(8) g73.1<2>UD g38<4,4,1>UD { align1 1Q I@4 }; | mov(8) g68.1<2>UD g37<4,4,1>UD { align1 1Q I@4 }; mov(8) g79.1<2>UD g41<4,4,1>UD { align1 1Q I@4 }; | mov(8) g74.1<2>UD g40<4,4,1>UD { align1 1Q I@4 }; > mov(8) g80.1<2>UD g43<4,4,1>UD { align1 1Q I@4 }; (+f0.0) if(8) JIP: LABEL3 UIP: LABEL2 { align1 1Q }; (+f0.0) if(8) JIP: LABEL3 UIP: LABEL2 { align1 1Q }; END B1 ->B2 ->B3 END B1 ->B2 ->B3 START B2 <-B1 (212 cycles) | START B2 <-B1 (200 cycles) sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@5 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@5 }; send(8) g42UD g65UD nullUD 0x0440f582 0x00000000 | send(8) g44UD g66UD nullUD 0x0440f582 0x00000000 ugm MsgDesc: ( load_cmask, a64, d32, xyzw, L1STATE_L3MOCS dst_len = 4, src0_len = 2, src1 ugm MsgDesc: ( load_cmask, a64, d32, xyzw, L1STATE_L3MOCS dst_len = 4, src0_len = 2, src1 add(8) g46<1>D g25<1,1,0>D 16D { align1 1Q compacted }; | add3(8) g48<1>D g30<8,8,1>D g3<8,8,1>D g12<1,1,1>D { align1 1Q }; add(8) g47<1>D g23<8,4,2>D g46<1,1,0>D { align1 1Q I@1 compacted }; | cmp.l.f0.0(8) g49<1>UD g48<8,8,1>UD g24<8,4,2>UD { align1 1Q I@1 }; cmp.l.f0.0(8) g48<1>UD g47<8,8,1>UD g23<8,4,2>UD { align1 1Q I@1 }; | mov(8) g58<2>UD g48<4,4,1>UD { align1 1Q }; mov(8) g57<2>UD g47<4,4,1>UD { align1 1Q }; | add(8) g50<1>D -g49<8,8,1>D g24.1<8,4,2>D { align1 1Q I@2 }; add(8) g49<1>D -g48<8,8,1>D g23.1<8,4,2>D { align1 1Q I@2 }; | mov(8) g58.1<2>UD g50<4,4,1>UD { align1 1Q I@1 }; mov(8) g57.1<2>UD g49<4,4,1>UD { align1 1Q I@1 }; < sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@1 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@1 }; send(8) g60UD g57UD nullUD 0x04101582 0x00000000 | send(8) g61UD g58UD nullUD 0x04101582 0x00000000 ugm MsgDesc: ( load_cmask, a64, d32, x, L1STATE_L3MOCS dst_len = 1, src0_len = 2, src1_le ugm MsgDesc: ( load_cmask, a64, d32, x, L1STATE_L3MOCS dst_len = 1, src0_len = 2, src1_le mul(8) g59<1>D g43<8,8,1>D g5.2<0,1,0>UW { align1 1Q $0.dst }; | mul(8) g60<1>D g45<8,8,1>D g5.2<0,1,0>UW { align1 1Q $0.dst }; mul(8) g86<1>D g43<8,8,1>D g5.3<0,1,0>UW { align1 1Q }; | mul(8) g87<1>D g45<8,8,1>D g5.3<0,1,0>UW { align1 1Q }; mov(8) g8<1>D g42<8,8,1>D { align1 1Q $0.dst }; | mov(8) g8<1>D g44<8,8,1>D { align1 1Q $0.dst }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N $0.dst }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N $0.dst }; mov(8) g9<1>D g44<8,8,1>D { align1 1Q F@6 }; | mov(8) g9<1>D g46<8,8,1>D { align1 1Q F@6 }; add(8) g59.1<2>UW g59.1<16,8,2>UW g86<16,8,2>UW { align1 1Q I@3 }; | add(8) g60.1<2>UW g60.1<16,8,2>UW g87<16,8,2>UW { align1 1Q I@3 }; mov(1) f1<1>UW g1.14<0,1,0>UW { align1 WE_all 1N }; mov(1) f1<1>UW g1.14<0,1,0>UW { align1 WE_all 1N }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@3 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@3 }; (+f1.0) send(8) nullUD g67UD g6UD 0x0400f586 0x00000100 | (+f1.0) send(8) nullUD g68UD g6UD 0x0400f586 0x00000100 ugm MsgDesc: ( store_cmask, a64, d32, xyzw, L1STATE_L3MOCS dst_len = 0, src0_len = 2, src ugm MsgDesc: ( store_cmask, a64, d32, xyzw, L1STATE_L3MOCS dst_len = 0, src0_len = 2, src mov(8) g61<1>D g45<8,8,1>D { align1 1Q $0.dst }; | mov(8) g62<1>D g47<8,8,1>D { align1 1Q $0.dst }; mov(8) g62<1>D g45<8,8,1>D { align1 1Q }; | mov(8) g63<1>D g47<8,8,1>D { align1 1Q }; mov(1) f1<1>UW g1.14<0,1,0>UW { align1 WE_all 1N }; mov(1) f1<1>UW g1.14<0,1,0>UW { align1 WE_all 1N }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N $1.dst }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N $1.dst }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@2 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@2 }; (+f1.0) send(8) nullUD g73UD g59UD 0x0400f586 0x00000100 | (+f1.0) send(8) nullUD g74UD g60UD 0x0400f586 0x00000100 ugm MsgDesc: ( store_cmask, a64, d32, xyzw, L1STATE_L3MOCS dst_len = 0, src0_len = 2, src ugm MsgDesc: ( store_cmask, a64, d32, xyzw, L1STATE_L3MOCS dst_len = 0, src0_len = 2, src mov(8) g63<1>D g60<8,8,1>D { align1 1Q $3.src }; | mov(8) g64<1>D g61<8,8,1>D { align1 1Q $3.src }; mov(1) f1<1>UW g1.14<0,1,0>UW { align1 WE_all 1N }; mov(1) f1<1>UW g1.14<0,1,0>UW { align1 WE_all 1N }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@2 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@2 }; (+f1.0) send(8) nullUD g79UD g63UD 0x04003586 0x00000080 | (+f1.0) send(8) nullUD g80UD g64UD 0x04003586 0x00000080 ugm MsgDesc: ( store_cmask, a64, d32, xy, L1STATE_L3MOCS dst_len = 0, src0_len = 2, src1_ ugm MsgDesc: ( store_cmask, a64, d32, xy, L1STATE_L3MOCS dst_len = 0, src0_len = 2, src1_ else(8) JIP: LABEL2 UIP: LABEL2 { align1 1Q }; else(8) JIP: LABEL2 UIP: LABEL2 { align1 1Q }; END B2 ->B3 ->B4 END B2 ->B3 ->B4 START B3 <-B1 <-B2 (192 cycles) START B3 <-B1 <-B2 (192 cycles) LABEL3: LABEL3: sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@5 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@5 }; send(8) g50UD g65UD nullUD 0x0440f582 0x00000000 | send(8) g51UD g66UD nullUD 0x0440f582 0x00000000 ugm MsgDesc: ( load_cmask, a64, d32, xyzw, L1STATE_L3MOCS dst_len = 4, src0_len = 2, src1 ugm MsgDesc: ( load_cmask, a64, d32, xyzw, L1STATE_L3MOCS dst_len = 4, src0_len = 2, src1 mov(8) g69<1>D g6<8,8,1>D { align1 1Q $2.src }; | mov(8) g70<1>D g6<8,8,1>D { align1 1Q $2.src }; mov(8) g70<1>D g7<8,8,1>D { align1 1Q $2.src }; | mov(8) g71<1>D g7<8,8,1>D { align1 1Q $2.src }; mul(8) g75<1>D g51<8,8,1>D g5.2<0,1,0>UW { align1 1Q $0.dst }; | mul(8) g76<1>D g52<8,8,1>D g5.2<0,1,0>UW { align1 1Q $0.dst }; mul(8) g87<1>D g51<8,8,1>D g5.3<0,1,0>UW { align1 1Q }; | mul(8) g88<1>D g52<8,8,1>D g5.3<0,1,0>UW { align1 1Q }; mov(8) g71<1>D g50<8,8,1>D { align1 1Q $0.dst }; | mov(8) g72<1>D g51<8,8,1>D { align1 1Q $0.dst }; mov(8) g72<1>D g52<8,8,1>D { align1 1Q $0.dst }; | mov(8) g73<1>D g53<8,8,1>D { align1 1Q $0.dst }; add(8) g75.1<2>UW g75.1<16,8,2>UW g87<16,8,2>UW { align1 1Q I@3 }; | add(8) g76.1<2>UW g76.1<16,8,2>UW g88<16,8,2>UW { align1 1Q I@3 }; mov(1) f1<1>UW g1.14<0,1,0>UW { align1 WE_all 1N }; mov(1) f1<1>UW g1.14<0,1,0>UW { align1 WE_all 1N }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@3 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@3 }; (+f1.0) send(8) nullUD g67UD g69UD 0x0400f586 0x00000100 | (+f1.0) send(8) nullUD g68UD g70UD 0x0400f586 0x00000100 ugm MsgDesc: ( store_cmask, a64, d32, xyzw, L1STATE_L3MOCS dst_len = 0, src0_len = 2, src ugm MsgDesc: ( store_cmask, a64, d32, xyzw, L1STATE_L3MOCS dst_len = 0, src0_len = 2, src mov(8) g76<1>D g53<8,8,1>D { align1 1Q $0.dst }; | mov(8) g77<1>D g54<8,8,1>D { align1 1Q $0.dst }; mov(8) g77<1>D 0D { align1 1Q }; | mov(8) g78<1>D 0D { align1 1Q }; mov(8) g78<1>D g52<8,8,1>D { align1 1Q }; | mov(8) g79<1>D g53<8,8,1>D { align1 1Q }; mov(1) f1<1>UW g1.14<0,1,0>UW { align1 WE_all 1N }; mov(1) f1<1>UW g1.14<0,1,0>UW { align1 WE_all 1N }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@2 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@2 }; (+f1.0) send(8) nullUD g73UD g75UD 0x0400f586 0x00000100 | (+f1.0) send(8) nullUD g74UD g76UD 0x0400f586 0x00000100 ugm MsgDesc: ( store_cmask, a64, d32, xyzw, L1STATE_L3MOCS dst_len = 0, src0_len = 2, src ugm MsgDesc: ( store_cmask, a64, d32, xyzw, L1STATE_L3MOCS dst_len = 0, src0_len = 2, src mov(8) g81<1>D g53<8,8,1>D { align1 1Q }; | mov(8) g82<1>D g54<8,8,1>D { align1 1Q }; mov(8) g82<1>D g64<8,8,1>D { align1 1Q $4.src }; | mov(8) g83<1>D g65<8,8,1>D { align1 1Q $4.src }; mov(1) f1<1>UW g1.14<0,1,0>UW { align1 WE_all 1N }; mov(1) f1<1>UW g1.14<0,1,0>UW { align1 WE_all 1N }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@2 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@2 }; (+f1.0) send(8) nullUD g79UD g81UD 0x04003586 0x00000080 | (+f1.0) send(8) nullUD g80UD g82UD 0x04003586 0x00000080 ugm MsgDesc: ( store_cmask, a64, d32, xy, L1STATE_L3MOCS dst_len = 0, src0_len = 2, src1_ ugm MsgDesc: ( store_cmask, a64, d32, xy, L1STATE_L3MOCS dst_len = 0, src0_len = 2, src1_ END B3 ->B4 END B3 ->B4 START B4 <-B3 <-B2 (16 cycles) START B4 <-B3 <-B2 (16 cycles) LABEL2: LABEL2: endif(8) JIP: LABEL4 { align1 1Q }; endif(8) JIP: LABEL4 { align1 1Q }; LABEL4: LABEL4: else(8) JIP: LABEL0 UIP: LABEL0 { align1 1Q }; else(8) JIP: LABEL0 UIP: LABEL0 { align1 1Q }; END B4 ->B5 ->B11 END B4 ->B5 ->B11 START B5 <-B0 <-B4 (24 cycles) START B5 <-B0 <-B4 (24 cycles) LABEL1: LABEL1: cmp.z.f0.0(8) null<1>D g64<8,8,1>D g4.7<0,1,0>D { align1 1Q $4.src }; | cmp.z.f0.0(8) null<1>D g65<8,8,1>D g4.7<0,1,0>D { align1 1Q $4.src }; (+f0.0) if(8) JIP: LABEL6 UIP: LABEL5 { align1 1Q }; (+f0.0) if(8) JIP: LABEL6 UIP: LABEL5 { align1 1Q }; END B5 ->B6 ->B7 END B5 ->B6 ->B7 START B6 <-B5 (10 cycles) START B6 <-B5 (10 cycles) cmp.l.f0.0(8) g11<1>UD g64<1,1,0>UD g5<0,1,0>UD { align1 1Q compacted }; | cmp.l.f0.0(8) g11<1>UD g65<1,1,0>UD g5<0,1,0>UD { align1 1Q compacted }; else(8) JIP: LABEL5 UIP: LABEL5 { align1 1Q }; else(8) JIP: LABEL5 UIP: LABEL5 { align1 1Q }; END B6 ->B7 ->B8 END B6 ->B7 ->B8 START B7 <-B5 <-B6 (4 cycles) START B7 <-B5 <-B6 (4 cycles) LABEL6: LABEL6: mov(8) g11<1>UD 0x00000000UD { align1 1Q I@2 }; mov(8) g11<1>UD 0x00000000UD { align1 1Q I@2 }; END B7 ->B8 END B7 ->B8 START B8 <-B7 <-B6 (34 cycles) START B8 <-B7 <-B6 (34 cycles) LABEL5: LABEL5: endif(8) JIP: LABEL0 { align1 1Q }; endif(8) JIP: LABEL0 { align1 1Q }; mov.nz.f0.0(8) null<1>D g11<8,8,1>D { align1 1Q I@2 }; mov.nz.f0.0(8) null<1>D g11<8,8,1>D { align1 1Q I@2 }; (+f0.0) if(8) JIP: LABEL7 UIP: LABEL7 { align1 1Q }; (+f0.0) if(8) JIP: LABEL7 UIP: LABEL7 { align1 1Q }; END B8 ->B9 ->B10 END B8 ->B9 ->B10 add(8) g53<1>D g20<8,4,2>D g22<1,1,0>D { align1 1Q A@1 compacted }; | add(8) g54<1>D g21<8,4,2>D g23<1,1,0>D { align1 1Q A@1 compacted }; mov(8) g84<1>D 411042049D { align1 1Q }; | mov(8) g85<1>D 411042049D { align1 1Q }; mov(8) g51.1<2>F g5.3<0,1,0>F { align1 1Q }; | mov(8) g52.1<2>F g5.3<0,1,0>F { align1 1Q }; cmp.l.f0.0(8) g54<1>UD g53<8,8,1>UD g20<8,4,2>UD { align1 1Q I@2 }; | cmp.l.f0.0(8) g55<1>UD g54<8,8,1>UD g21<8,4,2>UD { align1 1Q I@2 }; mov(8) g82<2>UD g53<4,4,1>UD { align1 1Q $4.src }; | mov(8) g83<2>UD g54<4,4,1>UD { align1 1Q $4.src }; mov(8) g51<2>F g5.2<0,1,0>F { align1 1Q F@1 compacted }; | mov(8) g52<2>F g5.2<0,1,0>F { align1 1Q F@1 compacted }; add(8) g55<1>D -g54<8,8,1>D g20.1<8,4,2>D { align1 1Q I@2 }; | add(8) g56<1>D -g55<8,8,1>D g21.1<8,4,2>D { align1 1Q I@2 }; mov(8) g85<1>D g51<8,4,2>D { align1 1Q F@1 }; | mov(8) g86<1>D g52<8,4,2>D { align1 1Q F@1 }; mov(8) g86<1>D g51.1<8,4,2>D { align1 1Q }; | mov(8) g87<1>D g52.1<8,4,2>D { align1 1Q }; mov(8) g82.1<2>UD g55<4,4,1>UD { align1 1Q I@3 }; | mov(8) g83.1<2>UD g56<4,4,1>UD { align1 1Q I@3 }; mov(1) f1<1>UW g1.14<0,1,0>UW { align1 WE_all 1N }; mov(1) f1<1>UW g1.14<0,1,0>UW { align1 WE_all 1N }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@2 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@2 }; (+f1.0) send(8) nullUD g82UD g84UD 0x04007586 0x000000c0 | (+f1.0) send(8) nullUD g83UD g85UD 0x04007586 0x000000c0 ugm MsgDesc: ( store_cmask, a64, d32, xyz, L1STATE_L3MOCS dst_len = 0, src0_len = 2, src1 ugm MsgDesc: ( store_cmask, a64, d32, xyz, L1STATE_L3MOCS dst_len = 0, src0_len = 2, src1 END B9 ->B10 END B9 ->B10 START B10 <-B9 <-B8 (8 cycles) START B10 <-B9 <-B8 (8 cycles) LABEL7: LABEL7: endif(8) JIP: LABEL0 { align1 1Q }; endif(8) JIP: LABEL0 { align1 1Q }; END B10 ->B11 END B10 ->B11 START B11 <-B10 <-B4 (10 cycles) START B11 <-B10 <-B4 (10 cycles) LABEL0: LABEL0: endif(8) JIP: LABEL8 { align1 1Q }; endif(8) JIP: LABEL8 { align1 1Q }; LABEL8: LABEL8: sendc(8) nullUD g123UD nullUD 0x08031400 0x00100000 sendc(8) nullUD g123UD nullUD 0x08031400 0x00100000 render MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 4 ex_mlen 0 rlen 0 { align1 1Q A@1 render MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 4 ex_mlen 0 rlen 0 { align1 1Q A@1 END B11 END B11 Native code for unnamed fragment shader (null) (sha1 139d803a7187dc7b9d5897883ba039d0eb560886) | Native code for unnamed fragment shader (null) (sha1 5497f72bea8dbe37ff1a2267c6769520c58fbabc) SIMD16 shader: 178 instructions. 0 loops. 1186 cycles. 0:0 spills:fills, 11 sends, scheduled with mode top-down. Prom | SIMD16 shader: 171 instructions. 0 loops. 1324 cycles. 0:0 spills:fills, 11 sends, scheduled with mode top-down. Prom START B0 (140 cycles) | START B0 (144 cycles) add(32) g78<1>UW g1.4<2,8,0>UW 0x01000100V { align1 WE_all }; | add(32) g75<1>UW g1.4<2,8,0>UW 0x01000100V { align1 WE_all }; add(32) g80<1>UW g1.5<2,8,0>UW 0x01010000V { align1 WE_all }; | add(32) g77<1>UW g1.5<2,8,0>UW 0x01010000V { align1 WE_all }; > mov(16) g79<1>D 16D { align1 1H }; mov(16) g10<1>F g6.5<0,1,0>F { align1 1H compacted }; mov(16) g10<1>F g6.5<0,1,0>F { align1 1H compacted }; and(16) g82<1>UD g6.5<0,1,0>UD 0x00000001UD { align1 1H compacted }; | and(16) g81<1>UD g6.5<0,1,0>UD 0x00000001UD { align1 1H compacted }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@3 }; | sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@4 }; mov(16) g75<1>F g78<16,8,2>UW { align1 1H }; | mov(16) g72<1>F g75<16,8,2>UW { align1 1H }; mov(16) g84<1>UD g10.2<32,8,4>UB { align1 1H F@2 }; | mov(16) g83<1>UD g10.2<32,8,4>UB { align1 1H F@2 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@3 }; | sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@4 }; mov(16) g77<1>F g80<16,8,2>UW { align1 1H }; | mov(16) g74<1>F g77<16,8,2>UW { align1 1H }; mov(8) g72.1<2>F g7.7<0,1,0>F { align1 1Q }; | mov(8) g69.1<2>F g7.7<0,1,0>F { align1 1Q }; mov(8) g2.1<2>F g7.7<0,1,0>F { align1 2Q }; | mov(8) g97.1<2>F g7.7<0,1,0>F { align1 2Q }; mov(16) g90<1>UD g75<8,8,1>F { align1 1H F@4 }; | mov(16) g89<1>UD g72<8,8,1>F { align1 1H F@4 }; mov(16) g86<1>UD g77<8,8,1>F { align1 1H F@3 }; | mov(16) g85<1>UD g74<8,8,1>F { align1 1H F@3 }; mov(8) g72<2>F g7.6<0,1,0>F { align1 1Q F@2 compacted }; | mov(8) g69<2>F g7.6<0,1,0>F { align1 1Q F@2 compacted }; mov(8) g2<2>F g7.6<0,1,0>F { align1 2Q F@2 compacted }; | mov(8) g97<2>F g7.6<0,1,0>F { align1 2Q F@2 compacted }; shl(16) g88<1>D g86<8,8,1>D 0x0000000dUD { align1 1H I@1 }; | shl(16) g87<1>D g85<8,8,1>D 0x0000000dUD { align1 1H I@1 }; add(16) g92<1>D g88<1,1,0>D g90<1,1,0>D { align1 1H I@1 compacted }; | add(16) g91<1>D g87<1,1,0>D g89<1,1,0>D { align1 1H I@1 compacted }; mul(16) g94<1>D g92<8,8,1>D g6.8<0,1,0>UW { align1 1H I@1 }; | mul(16) g93<1>D g91<8,8,1>D g6.8<0,1,0>UW { align1 1H I@1 }; mul(16) g60<1>D g92<8,8,1>D g6.9<0,1,0>UW { align1 1H }; | mul(16) g85<1>D g91<8,8,1>D g6.9<0,1,0>UW { align1 1H }; mul(16) g96<1>D g92<8,8,1>D g84<16,8,2>W { align1 1H I@7 }; | mul(16) g95<1>D g91<8,8,1>D g83<16,8,2>W { align1 1H I@7 }; add(16) g38<1>D g6.6<0,1,0>D g92<1,1,0>D { align1 1H compacted }; | add(16) g35<1>D g6.6<0,1,0>D g91<1,1,0>D { align1 1H compacted }; add(16) g94.1<2>UW g94.1<16,8,2>UW g60<16,8,2>UW { align1 1H I@3 }; | add(16) g93.1<2>UW g93.1<16,8,2>UW g85<16,8,2>UW { align1 1H I@3 }; shl(16) g98<1>D g96<8,8,1>D 0x00000002UD { align1 1H I@3 }; | shl(16) g2<1>D g95<8,8,1>D 0x00000002UD { align1 1H I@3 }; cmp.l.f0.0(16) null<1>UD g38<8,8,1>UD g6.7<0,1,0>UD { align1 1H I@3 }; | cmp.l.f0.0(16) null<1>UD g35<8,8,1>UD g6.7<0,1,0>UD { align1 1H I@3 }; (+f0.0) if(16) JIP: LABEL1 UIP: LABEL0 { align1 1H }; (+f0.0) if(16) JIP: LABEL1 UIP: LABEL0 { align1 1H }; END B0 ->B1 ->B5 END B0 ->B1 ->B5 and(16) g102<1>UD g94<8,8,1>UD 0xfffffffcUD { align1 1H I@4 }; | and(16) g101<1>UD g93<8,8,1>UD 0xfffffffcUD { align1 1H I@4 }; and(16) g104<1>UD g6.5<0,1,0>UD 0x00000002UD { align1 1H compacted }; | and(16) g103<1>UD g6.5<0,1,0>UD 0x00000002UD { align1 1H compacted }; shl(16) g22<1>D g82<8,8,1>D 0x00000008UD { align1 1H }; | shl(16) g19<1>D g81<8,8,1>D 0x00000008UD { align1 1H }; add(16) g108<1>D g98<1,1,0>D 16D { align1 1H I@6 compacted }; | mov(16) g107<1>D 32D { align1 1H }; add(16) g110<1>D g98<1,1,0>D 32D { align1 1H compacted }; | mov(8) g113<1>UD g69<8,4,2>UD { align1 1Q F@2 }; add(8) g31<1>D g72<8,4,2>D g98<1,1,0>D { align1 1Q F@2 compacted }; | mov(8) g114<1>UD g97<8,4,2>UD { align1 2Q F@1 }; add(8) g114<1>D g2<8,4,2>D g99<1,1,0>D { align1 2Q F@1 compacted }; | add(8) g59<1>D g69<8,4,2>D g2<1,1,0>D { align1 1Q I@7 compacted }; mov(8) g74.1<2>F g7.5<0,1,0>F { align1 1Q }; | add(8) g115<1>D g97<8,4,2>D g3<1,1,0>D { align1 2Q I@7 compacted }; mov(8) g100.1<2>F g7.5<0,1,0>F { align1 2Q }; | mov(8) g71.1<2>F g7.5<0,1,0>F { align1 1Q }; shl(16) g106<1>D g104<8,8,1>D 0x00000007UD { align1 1H I@6 }; | mov(8) g99.1<2>F g7.5<0,1,0>F { align1 2Q }; add(8) g34<1>D g72<8,4,2>D g108<1,1,0>D { align1 1Q I@5 compacted }; | shl(16) g105<1>D g103<8,8,1>D 0x00000007UD { align1 1H I@7 }; add(8) g117<1>D g2<8,4,2>D g109<1,1,0>D { align1 2Q I@6 compacted }; | add3(16) g118<1>D g113<8,8,1>D g2<8,8,1>D g79<1,1,1>D { align1 1H I@4 }; add(8) g49<1>D g72<8,4,2>D g110<1,1,0>D { align1 1Q I@6 compacted }; | add3(16) g121<1>D g113<8,8,1>D g2<8,8,1>D g107<1,1,1>D { align1 1H I@7 }; add(8) g120<1>D g2<8,4,2>D g111<1,1,0>D { align1 2Q I@7 compacted }; | mov(8) g41<2>UD g59<4,4,1>UD { align1 1Q I@5 }; mov(8) g44<2>UD g31<4,4,1>UD { align1 1Q I@7 }; | mov(8) g43<2>UD g115<4,4,1>UD { align1 2Q I@5 }; mov(8) g46<2>UD g114<4,4,1>UD { align1 2Q I@7 }; | mov(8) g71<2>F g7.4<0,1,0>F { align1 1Q F@2 compacted }; mov(8) g74<2>F g7.4<0,1,0>F { align1 1Q F@2 compacted }; | mov(8) g99<2>F g7.4<0,1,0>F { align1 2Q F@2 compacted }; mov(8) g100<2>F g7.4<0,1,0>F { align1 2Q F@2 compacted }; | or(16) g17<1>UD g105<8,8,1>UD 0x7b000808UD { align1 1H I@5 }; or(16) g20<1>UD g106<8,8,1>UD 0x7b000808UD { align1 1H I@7 }; | mov(8) g53<2>UD g118<4,4,1>UD { align1 1Q I@5 }; mov(8) g56<2>UD g34<4,4,1>UD { align1 1Q I@7 }; | mov(8) g55<2>UD g119<4,4,1>UD { align1 2Q I@6 }; mov(8) g58<2>UD g117<4,4,1>UD { align1 2Q I@7 }; | mov(8) g65<2>UD g121<4,4,1>UD { align1 1Q I@6 }; mov(8) g68<2>UD g49<4,4,1>UD { align1 1Q I@7 }; | mov(8) g67<2>UD g122<4,4,1>UD { align1 2Q I@7 }; mov(8) g70<2>UD g120<4,4,1>UD { align1 2Q I@7 }; | mov(8) g108<1>UD g71<8,4,2>UD { align1 1Q F@2 }; add(8) g28<1>D g74<8,4,2>D g102<1,1,0>D { align1 1Q F@2 compacted }; | add(8) g52<1>D g71<8,4,2>D g101<1,1,0>D { align1 1Q compacted }; add(8) g111<1>D g100<8,4,2>D g103<1,1,0>D { align1 2Q F@1 compacted }; | mov(8) g109<1>UD g99<8,4,2>UD { align1 2Q F@1 }; cmp.l.f0.0(8) g29<1>UD g28<8,8,1>UD g74<8,4,2>UD { align1 1Q I@2 }; | add(8) g110<1>D g99<8,4,2>D g102<1,1,0>D { align1 2Q compacted }; mov(8) g40<2>UD g28<4,4,1>UD { align1 1Q }; | cmp.l.f0.0(8) g57<1>UD g52<8,8,1>UD g71<8,4,2>UD { align1 1Q I@3 }; cmp.l.f0.0(8) g32<1>UD g31<8,8,1>UD g72<8,4,2>UD { align1 1Q }; | mov(8) g37<2>UD g52<4,4,1>UD { align1 1Q }; cmp.l.f0.0(8) g112<1>UD g111<8,8,1>UD g100<8,4,2>UD { align1 2Q I@4 }; | cmp.l.f0.0(8) g60<1>UD g59<8,8,1>UD g69<8,4,2>UD { align1 1Q }; mov(8) g42<2>UD g111<4,4,1>UD { align1 2Q }; | cmp.l.f0.0(8) g111<1>UD g110<8,8,1>UD g99<8,4,2>UD { align1 2Q I@4 }; cmp.l.f0.0(8) g35<1>UD g34<8,8,1>UD g72<8,4,2>UD { align1 1Q }; | mov(8) g39<2>UD g110<4,4,1>UD { align1 2Q }; cmp.l.f0.0(8) g115<1>UD g114<8,8,1>UD g2<8,4,2>UD { align1 2Q }; | cmp.l.f0.0(8) g62<1>UD g118<8,8,1>UD g69<8,4,2>UD { align1 1Q }; cmp.l.f0.0(8) g50<1>UD g49<8,8,1>UD g72<8,4,2>UD { align1 1Q }; | cmp.l.f0.0(8) g116<1>UD g115<8,8,1>UD g97<8,4,2>UD { align1 2Q }; cmp.l.f0.0(8) g118<1>UD g117<8,8,1>UD g2<8,4,2>UD { align1 2Q }; | cmp.l.f0.0(8) g64<1>UD g121<8,8,1>UD g69<8,4,2>UD { align1 1Q }; add(8) g30<1>D -g29<8,8,1>D g74.1<8,4,2>D { align1 1Q I@7 }; | cmp.l.f0.0(8) g119<1>UD g119<8,8,1>UD g97<8,4,2>UD { align1 2Q }; cmp.l.f0.0(8) g121<1>UD g120<8,8,1>UD g2<8,4,2>UD { align1 2Q }; | add(8) g58<1>D -g57<8,8,1>D g71.1<8,4,2>D { align1 1Q I@7 }; add(8) g33<1>D -g32<8,8,1>D g72.1<8,4,2>D { align1 1Q I@7 }; | cmp.l.f0.0(8) g122<1>UD g122<8,8,1>UD g97<8,4,2>UD { align1 2Q }; cmp.nz.f0.0(16) null<1>D g82<8,8,1>D 0D { align1 1H }; | add(8) g61<1>D -g60<8,8,1>D g69.1<8,4,2>D { align1 1Q I@7 }; add(8) g113<1>D -g112<8,8,1>D g100.1<8,4,2>D { align1 2Q I@7 }; | cmp.nz.f0.0(16) null<1>D g81<8,8,1>D 0D { align1 1H }; add(8) g48<1>D -g35<8,8,1>D g72.1<8,4,2>D { align1 1Q I@7 }; | add(8) g112<1>D -g111<8,8,1>D g99.1<8,4,2>D { align1 2Q I@7 }; add(8) g116<1>D -g115<8,8,1>D g2.1<8,4,2>D { align1 2Q I@7 }; | add(8) g63<1>D -g62<8,8,1>D g69.1<8,4,2>D { align1 1Q I@7 }; add(8) g51<1>D -g50<8,8,1>D g72.1<8,4,2>D { align1 1Q I@7 }; | add(8) g117<1>D -g116<8,8,1>D g97.1<8,4,2>D { align1 2Q I@7 }; add(8) g119<1>D -g118<8,8,1>D g2.1<8,4,2>D { align1 2Q I@7 }; | add(8) g73<1>D -g64<8,8,1>D g69.1<8,4,2>D { align1 1Q I@7 }; mov(8) g40.1<2>UD g30<4,4,1>UD { align1 1Q I@7 }; | add(8) g120<1>D -g119<8,8,1>D g97.1<8,4,2>D { align1 2Q I@7 }; add(8) g122<1>D -g121<8,8,1>D g2.1<8,4,2>D { align1 2Q I@7 }; | mov(8) g37.1<2>UD g58<4,4,1>UD { align1 1Q I@7 }; mov(8) g44.1<2>UD g33<4,4,1>UD { align1 1Q I@7 }; | add(8) g123<1>D -g122<8,8,1>D g97.1<8,4,2>D { align1 2Q I@7 }; mov(8) g42.1<2>UD g113<4,4,1>UD { align1 2Q I@7 }; | mov(8) g41.1<2>UD g61<4,4,1>UD { align1 1Q I@7 }; mov(8) g56.1<2>UD g48<4,4,1>UD { align1 1Q I@7 }; | mov(8) g39.1<2>UD g112<4,4,1>UD { align1 2Q I@7 }; mov(8) g46.1<2>UD g116<4,4,1>UD { align1 2Q I@7 }; | mov(8) g53.1<2>UD g63<4,4,1>UD { align1 1Q I@7 }; mov(8) g68.1<2>UD g51<4,4,1>UD { align1 1Q I@7 }; | mov(8) g43.1<2>UD g117<4,4,1>UD { align1 2Q I@7 }; mov(8) g58.1<2>UD g119<4,4,1>UD { align1 2Q I@7 }; | mov(8) g65.1<2>UD g73<4,4,1>UD { align1 1Q I@7 }; mov(8) g70.1<2>UD g122<4,4,1>UD { align1 2Q I@7 }; | mov(8) g55.1<2>UD g120<4,4,1>UD { align1 2Q I@7 }; > mov(8) g67.1<2>UD g123<4,4,1>UD { align1 2Q I@7 }; (+f0.0) if(16) JIP: LABEL3 UIP: LABEL2 { align1 1H }; (+f0.0) if(16) JIP: LABEL3 UIP: LABEL2 { align1 1H }; END B1 ->B2 ->B3 END B1 ->B2 ->B3 START B2 <-B1 (332 cycles) | START B2 <-B1 (376 cycles) sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@7 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@7 }; send(16) g8UD g40UD nullUD 0x0880f582 0x00000000 | send(16) g8UD g37UD nullUD 0x0880f582 0x00000000 ugm MsgDesc: ( load_cmask, a64, d32, xyzw, L1STATE_L3MOCS dst_len = 8, src0_len = 4, src1 ugm MsgDesc: ( load_cmask, a64, d32, xyzw, L1STATE_L3MOCS dst_len = 8, src0_len = 4, src1 add(16) g123<1>D g102<1,1,0>D 16D { align1 1H compacted }; | add3(16) g124<1>D g108<8,8,1>D g101<8,8,1>D g79<1,1,1>D { align1 1H }; add(8) g52<1>D g74<8,4,2>D g123<1,1,0>D { align1 1Q I@1 compacted }; | cmp.l.f0.0(8) g74<1>UD g124<8,8,1>UD g71<8,4,2>UD { align1 1Q I@1 }; add(8) g124<1>D g100<8,4,2>D g124<1,1,0>D { align1 2Q I@2 compacted }; | cmp.l.f0.0(8) g126<1>UD g125<8,8,1>UD g99<8,4,2>UD { align1 2Q I@2 }; cmp.l.f0.0(8) g53<1>UD g52<8,8,1>UD g74<8,4,2>UD { align1 1Q I@2 }; | mov(8) g45<2>UD g124<4,4,1>UD { align1 1Q }; mov(8) g16<2>UD g52<4,4,1>UD { align1 1Q }; | mov(8) g47<2>UD g125<4,4,1>UD { align1 2Q }; cmp.l.f0.0(8) g125<1>UD g124<8,8,1>UD g100<8,4,2>UD { align1 2Q I@3 }; | add(8) g75<1>D -g74<8,8,1>D g71.1<8,4,2>D { align1 1Q I@4 }; mov(8) g18<2>UD g124<4,4,1>UD { align1 2Q }; | add(8) g127<1>D -g126<8,8,1>D g99.1<8,4,2>D { align1 2Q I@4 }; add(8) g54<1>D -g53<8,8,1>D g74.1<8,4,2>D { align1 1Q I@4 }; | mov(8) g45.1<2>UD g75<4,4,1>UD { align1 1Q I@2 }; add(8) g126<1>D -g125<8,8,1>D g100.1<8,4,2>D { align1 2Q I@3 }; | mov(8) g47.1<2>UD g127<4,4,1>UD { align1 2Q I@2 }; mov(8) g16.1<2>UD g54<4,4,1>UD { align1 1Q I@2 }; < mov(8) g18.1<2>UD g126<4,4,1>UD { align1 2Q I@2 }; < sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@1 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@1 }; send(16) g30UD g16UD nullUD 0x08201582 0x00000000 | send(16) g27UD g45UD nullUD 0x08201582 0x00000000 ugm MsgDesc: ( load_cmask, a64, d32, x, L1STATE_L3MOCS dst_len = 2, src0_len = 4, src1_le ugm MsgDesc: ( load_cmask, a64, d32, x, L1STATE_L3MOCS dst_len = 2, src0_len = 4, src1_le mul(16) g28<1>D g10<8,8,1>D g7.2<0,1,0>UW { align1 1H $0.dst }; | mul(16) g25<1>D g10<8,8,1>D g7.2<0,1,0>UW { align1 1H $0.dst }; mul(16) g61<1>D g10<8,8,1>D g7.3<0,1,0>UW { align1 1H }; | mul(16) g86<1>D g10<8,8,1>D g7.3<0,1,0>UW { align1 1H }; mov(16) g24<1>D g8<8,8,1>D { align1 1H $0.dst }; | mov(16) g21<1>D g8<8,8,1>D { align1 1H $0.dst }; mov(16) g26<1>D g12<8,8,1>D { align1 1H $0.dst }; | mov(16) g23<1>D g12<8,8,1>D { align1 1H $0.dst }; add(16) g28.1<2>UW g28.1<16,8,2>UW g61<16,8,2>UW { align1 1H I@3 }; | add(16) g25.1<2>UW g25.1<16,8,2>UW g86<16,8,2>UW { align1 1H I@3 }; mov(1) f1<1>UW g1.14<0,1,0>UW { align1 WE_all 1N }; mov(1) f1<1>UW g1.14<0,1,0>UW { align1 WE_all 1N }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@3 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@3 }; (+f1.0) send(16) nullUD g44UD g20UD 0x0800f586 0x00000200 | (+f1.0) send(16) nullUD g41UD g17UD 0x0800f586 0x00000200 ugm MsgDesc: ( store_cmask, a64, d32, xyzw, L1STATE_L3MOCS dst_len = 0, src0_len = 4, src ugm MsgDesc: ( store_cmask, a64, d32, xyzw, L1STATE_L3MOCS dst_len = 0, src0_len = 4, src mov(16) g32<1>D g14<8,8,1>D { align1 1H $0.dst }; | mov(16) g29<1>D g14<8,8,1>D { align1 1H $0.dst }; mov(16) g34<1>D g14<8,8,1>D { align1 1H }; | mov(16) g31<1>D g14<8,8,1>D { align1 1H }; mov(1) f1<1>UW g1.14<0,1,0>UW { align1 WE_all 1N }; mov(1) f1<1>UW g1.14<0,1,0>UW { align1 WE_all 1N }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N $1.dst }; < sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@2 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@2 }; (+f1.0) send(16) nullUD g56UD g28UD 0x0800f586 0x00000200 | (+f1.0) send(16) nullUD g53UD g25UD 0x0800f586 0x00000200 ugm MsgDesc: ( store_cmask, a64, d32, xyzw, L1STATE_L3MOCS dst_len = 0, src0_len = 4, src | ugm MsgDesc: ( store_cmask, a64, d32, xyzw, L1STATE_L3MOCS dst_len = 0, src0_len = 4, src mov(16) g36<1>D g30<8,8,1>D { align1 1H $2.src }; | mov(16) g33<1>D g27<8,8,1>D { align1 1H $1.src }; mov(1) f1<1>UW g1.14<0,1,0>UW { align1 WE_all 1N }; mov(1) f1<1>UW g1.14<0,1,0>UW { align1 WE_all 1N }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@2 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@2 }; (+f1.0) send(16) nullUD g68UD g36UD 0x08003586 0x00000100 | (+f1.0) send(16) nullUD g65UD g33UD 0x08003586 0x00000100 ugm MsgDesc: ( store_cmask, a64, d32, xy, L1STATE_L3MOCS dst_len = 0, src0_len = 4, src1_ ugm MsgDesc: ( store_cmask, a64, d32, xy, L1STATE_L3MOCS dst_len = 0, src0_len = 4, src1_ else(16) JIP: LABEL2 UIP: LABEL2 { align1 1H }; else(16) JIP: LABEL2 UIP: LABEL2 { align1 1H }; END B2 ->B3 ->B4 END B2 ->B3 ->B4 START B3 <-B1 <-B2 (274 cycles) | START B3 <-B1 <-B2 (376 cycles) LABEL3: LABEL3: sync nop(1) null<0,1,0>UB { align1 WE_all 1N $1.src }; < sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@5 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@5 }; send(16) g9UD g40UD nullUD 0x0880f582 0x00000000 | send(16) g9UD g37UD nullUD 0x0880f582 0x00000000 ugm MsgDesc: ( load_cmask, a64, d32, xyzw, L1STATE_L3MOCS dst_len = 8, src0_len = 4, src1 ugm MsgDesc: ( load_cmask, a64, d32, xyzw, L1STATE_L3MOCS dst_len = 8, src0_len = 4, src1 mov(16) g48<1>D g20<8,8,1>D { align1 1H $1.src }; | mov(16) g45<1>D g17<8,8,1>D { align1 1H $1.src }; mov(16) g50<1>D g22<8,8,1>D { align1 1H $1.src }; | mov(16) g47<1>D g19<8,8,1>D { align1 1H $1.src }; mul(16) g60<1>D g11<8,8,1>D g7.2<0,1,0>UW { align1 1H $0.dst }; | mul(16) g57<1>D g11<8,8,1>D g7.2<0,1,0>UW { align1 1H $0.dst }; mul(16) g74<1>D g11<8,8,1>D g7.3<0,1,0>UW { align1 1H }; | mul(16) g87<1>D g11<8,8,1>D g7.3<0,1,0>UW { align1 1H }; mov(16) g52<1>D g9<8,8,1>D { align1 1H $0.dst }; | mov(16) g49<1>D g9<8,8,1>D { align1 1H $0.dst }; mov(16) g54<1>D g13<8,8,1>D { align1 1H $0.dst }; | mov(16) g51<1>D g13<8,8,1>D { align1 1H $0.dst }; add(16) g60.1<2>UW g60.1<16,8,2>UW g74<16,8,2>UW { align1 1H I@3 }; | add(16) g57.1<2>UW g57.1<16,8,2>UW g87<16,8,2>UW { align1 1H I@3 }; mov(1) f1<1>UW g1.14<0,1,0>UW { align1 WE_all 1N }; mov(1) f1<1>UW g1.14<0,1,0>UW { align1 WE_all 1N }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@3 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@3 }; (+f1.0) send(16) nullUD g44UD g48UD 0x0800f586 0x00000200 | (+f1.0) send(16) nullUD g41UD g45UD 0x0800f586 0x00000200 ugm MsgDesc: ( store_cmask, a64, d32, xyzw, L1STATE_L3MOCS dst_len = 0, src0_len = 4, src ugm MsgDesc: ( store_cmask, a64, d32, xyzw, L1STATE_L3MOCS dst_len = 0, src0_len = 4, src mov(16) g62<1>D g15<8,8,1>D { align1 1H $0.dst }; | mov(16) g59<1>D g15<8,8,1>D { align1 1H $0.dst }; mov(16) g64<1>D 0D { align1 1H }; | mov(16) g61<1>D 0D { align1 1H }; mov(16) g66<1>D g13<8,8,1>D { align1 1H }; | mov(16) g63<1>D g13<8,8,1>D { align1 1H }; mov(1) f1<1>UW g1.14<0,1,0>UW { align1 WE_all 1N }; mov(1) f1<1>UW g1.14<0,1,0>UW { align1 WE_all 1N }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@2 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@2 }; (+f1.0) send(16) nullUD g56UD g60UD 0x0800f586 0x00000200 | (+f1.0) send(16) nullUD g53UD g57UD 0x0800f586 0x00000200 ugm MsgDesc: ( store_cmask, a64, d32, xyzw, L1STATE_L3MOCS dst_len = 0, src0_len = 4, src | ugm MsgDesc: ( store_cmask, a64, d32, xyzw, L1STATE_L3MOCS dst_len = 0, src0_len = 4, src mov(16) g17<1>D g15<8,8,1>D { align1 1H $1.src }; | mov(16) g46<1>D g15<8,8,1>D { align1 1H $1.src }; mov(16) g19<1>D g38<8,8,1>D { align1 1H $1.src }; | mov(16) g48<1>D g35<8,8,1>D { align1 1H $1.src }; mov(1) f1<1>UW g1.14<0,1,0>UW { align1 WE_all 1N }; mov(1) f1<1>UW g1.14<0,1,0>UW { align1 WE_all 1N }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@2 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@2 }; (+f1.0) send(16) nullUD g68UD g17UD 0x08003586 0x00000100 | (+f1.0) send(16) nullUD g65UD g46UD 0x08003586 0x00000100 ugm MsgDesc: ( store_cmask, a64, d32, xy, L1STATE_L3MOCS dst_len = 0, src0_len = 4, src1_ ugm MsgDesc: ( store_cmask, a64, d32, xy, L1STATE_L3MOCS dst_len = 0, src0_len = 4, src1_ END B3 ->B4 END B3 ->B4 START B4 <-B3 <-B2 (16 cycles) START B4 <-B3 <-B2 (16 cycles) LABEL2: LABEL2: endif(16) JIP: LABEL4 { align1 1H }; endif(16) JIP: LABEL4 { align1 1H }; LABEL4: LABEL4: else(16) JIP: LABEL0 UIP: LABEL0 { align1 1H }; else(16) JIP: LABEL0 UIP: LABEL0 { align1 1H }; END B4 ->B5 ->B11 END B4 ->B5 ->B11 START B5 <-B0 <-B4 (26 cycles) START B5 <-B0 <-B4 (26 cycles) LABEL1: LABEL1: cmp.z.f0.0(16) null<1>D g38<8,8,1>D g6.7<0,1,0>D { align1 1H $1.src }; | cmp.z.f0.0(16) null<1>D g35<8,8,1>D g6.7<0,1,0>D { align1 1H $1.src }; (+f0.0) if(16) JIP: LABEL6 UIP: LABEL5 { align1 1H }; (+f0.0) if(16) JIP: LABEL6 UIP: LABEL5 { align1 1H }; END B5 ->B6 ->B7 END B5 ->B6 ->B7 START B6 <-B5 (12 cycles) START B6 <-B5 (12 cycles) cmp.l.f0.0(16) g81<1>UD g38<1,1,0>UD g7<0,1,0>UD { align1 1H F@5 compacted }; | cmp.l.f0.0(16) g78<1>UD g35<1,1,0>UD g7<0,1,0>UD { align1 1H F@5 compacted }; else(16) JIP: LABEL5 UIP: LABEL5 { align1 1H }; else(16) JIP: LABEL5 UIP: LABEL5 { align1 1H }; END B6 ->B7 ->B8 END B6 ->B7 ->B8 START B7 <-B5 <-B6 (6 cycles) START B7 <-B5 <-B6 (6 cycles) LABEL6: LABEL6: mov(16) g81<1>UD 0x00000000UD { align1 1H A@2 }; | mov(16) g78<1>UD 0x00000000UD { align1 1H A@2 }; END B7 ->B8 END B7 ->B8 START B8 <-B7 <-B6 (36 cycles) START B8 <-B7 <-B6 (36 cycles) LABEL5: LABEL5: endif(16) JIP: LABEL0 { align1 1H }; endif(16) JIP: LABEL0 { align1 1H }; mov.nz.f0.0(16) null<1>D g81<8,8,1>D { align1 1H I@2 }; | mov.nz.f0.0(16) null<1>D g78<8,8,1>D { align1 1H I@2 }; (+f0.0) if(16) JIP: LABEL7 UIP: LABEL7 { align1 1H }; (+f0.0) if(16) JIP: LABEL7 UIP: LABEL7 { align1 1H }; END B8 ->B9 ->B10 END B8 ->B9 ->B10 START B9 <-B8 (90 cycles) | add(8) g78<1>D g69<8,4,2>D g2<1,1,0>D { align1 1Q A@2 compacted }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N $2.src }; | add(8) g6<1>D g97<8,4,2>D g3<1,1,0>D { align1 2Q A@1 compacted }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N $2.src }; | mov(16) g51<1>D 411042049D { align1 1H $1.src }; add(8) g57<1>D g72<8,4,2>D g98<1,1,0>D { align1 1Q A@2 compacted }; | mov(8) g76.1<2>F g7.3<0,1,0>F { align1 1Q }; add(8) g6<1>D g2<8,4,2>D g99<1,1,0>D { align1 2Q A@1 compacted }; < mov(16) g22<1>D 411042049D { align1 1H $1.src }; < sync nop(1) null<0,1,0>UB { align1 WE_all 1N $2.src }; < mov(8) g55.1<2>F g7.3<0,1,0>F { align1 1Q $1.src }; < mov(8) g4.1<2>F g7.3<0,1,0>F { align1 2Q }; mov(8) g4.1<2>F g7.3<0,1,0>F { align1 2Q }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N $2.src }; | cmp.l.f0.0(8) g79<1>UD g78<8,8,1>UD g69<8,4,2>UD { align1 1Q I@3 }; cmp.l.f0.0(8) g58<1>UD g57<8,8,1>UD g72<8,4,2>UD { align1 1Q I@3 }; | cmp.l.f0.0(8) g8<1>UD g6<8,8,1>UD g97<8,4,2>UD { align1 2Q I@3 }; cmp.l.f0.0(8) g8<1>UD g6<8,8,1>UD g2<8,4,2>UD { align1 2Q I@3 }; | mov(8) g47<2>UD g78<4,4,1>UD { align1 1Q $1.src }; mov(8) g18<2>UD g57<4,4,1>UD { align1 1Q $1.src }; | mov(8) g49<2>UD g6<4,4,1>UD { align1 2Q $1.src }; mov(8) g20<2>UD g6<4,4,1>UD { align1 2Q $1.src }; | mov(8) g76<2>F g7.2<0,1,0>F { align1 1Q F@2 compacted }; mov(8) g55<2>F g7.2<0,1,0>F { align1 1Q F@2 compacted }; < mov(8) g4<2>F g7.2<0,1,0>F { align1 2Q F@2 compacted }; mov(8) g4<2>F g7.2<0,1,0>F { align1 2Q F@2 compacted }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N $2.src }; | add(8) g80<1>D -g79<8,8,1>D g69.1<8,4,2>D { align1 1Q I@4 }; add(8) g59<1>D -g58<8,8,1>D g72.1<8,4,2>D { align1 1Q I@4 }; | add(8) g9<1>D -g8<8,8,1>D g97.1<8,4,2>D { align1 2Q I@4 }; add(8) g9<1>D -g8<8,8,1>D g2.1<8,4,2>D { align1 2Q I@4 }; < sync nop(1) null<0,1,0>UB { align1 WE_all 1N $1.src }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N $1.src }; mov(8) g24<1>UD g55<8,4,2>UD { align1 1Q F@2 }; | mov(8) g53<1>UD g76<8,4,2>UD { align1 1Q F@2 }; mov(8) g26<1>UD g55.1<8,4,2>UD { align1 1Q $1.src }; | mov(8) g55<1>UD g76.1<8,4,2>UD { align1 1Q $1.src }; sync nop(1) null<0,1,0>UB { align1 WE_all 3N $1.src }; sync nop(1) null<0,1,0>UB { align1 WE_all 3N $1.src }; mov(8) g25<1>UD g4<8,4,2>UD { align1 2Q F@1 }; | mov(8) g54<1>UD g4<8,4,2>UD { align1 2Q F@1 }; mov(8) g27<1>UD g4.1<8,4,2>UD { align1 2Q $1.src }; | mov(8) g56<1>UD g4.1<8,4,2>UD { align1 2Q $1.src }; mov(8) g18.1<2>UD g59<4,4,1>UD { align1 1Q I@6 }; | mov(8) g47.1<2>UD g80<4,4,1>UD { align1 1Q I@6 }; mov(8) g20.1<2>UD g9<4,4,1>UD { align1 2Q I@6 }; | mov(8) g49.1<2>UD g9<4,4,1>UD { align1 2Q I@6 }; mov(1) f1<1>UW g1.14<0,1,0>UW { align1 WE_all 1N }; mov(1) f1<1>UW g1.14<0,1,0>UW { align1 WE_all 1N }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@2 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@2 }; (+f1.0) send(16) nullUD g18UD g22UD 0x08007586 0x00000180 | (+f1.0) send(16) nullUD g47UD g51UD 0x08007586 0x00000180 ugm MsgDesc: ( store_cmask, a64, d32, xyz, L1STATE_L3MOCS dst_len = 0, src0_len = 4, src1 ugm MsgDesc: ( store_cmask, a64, d32, xyz, L1STATE_L3MOCS dst_len = 0, src0_len = 4, src1 END B9 ->B10 END B9 ->B10 START B10 <-B9 <-B8 (8 cycles) START B10 <-B9 <-B8 (8 cycles) LABEL7: LABEL7: endif(16) JIP: LABEL0 { align1 1H }; endif(16) JIP: LABEL0 { align1 1H }; END B10 ->B11 END B10 ->B11 START B11 <-B10 <-B4 (10 cycles) START B11 <-B10 <-B4 (10 cycles) LABEL0: LABEL0: endif(16) JIP: LABEL8 { align1 1H }; endif(16) JIP: LABEL8 { align1 1H }; LABEL8: LABEL8: sendc(16) nullUD g119UD nullUD 0x10031000 0x00100000 sendc(16) nullUD g119UD nullUD 0x10031000 0x00100000 render MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 8 ex_mlen 0 rlen 0 { align1 1H A@ render MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 8 ex_mlen 0 rlen 0 { align1 1H A@ END B11 END B11 NIR (from SPIR-V) for MESA_SHADER_VERTEX shader: NIR (from SPIR-V) for MESA_SHADER_VERTEX shader: shader: MESA_SHADER_VERTEX shader: MESA_SHADER_VERTEX source_sha1: {0xc53eb86f, 0x5605e25e, 0x3afa45c3, 0x86021b0d, 0x73a6d842} source_sha1: {0xc53eb86f, 0x5605e25e, 0x3afa45c3, 0x86021b0d, 0x73a6d842} stage: 0 stage: 0 next_stage: 0 next_stage: 0 subgroup_size: 2 subgroup_size: 2 inputs: 0 inputs: 0 outputs: 0 outputs: 0 uniforms: 0 uniforms: 0 decl_var shader_in INTERP_MODE_NONE vec4 @0 (VERT_ATTRIB_GENERIC0.xyzw, 0, 0) decl_var shader_in INTERP_MODE_NONE vec4 @0 (VERT_ATTRIB_GENERIC0.xyzw, 0, 0) decl_var shader_out INTERP_MODE_NONE vec4 @1 (VARYING_SLOT_POS.xyzw, 0, 0) decl_var shader_out INTERP_MODE_NONE vec4 @1 (VARYING_SLOT_POS.xyzw, 0, 0) decl_function main (0 params) decl_function main (0 params) impl main { impl main { block block_0: block block_0: /* preds: */ /* preds: */ vec1 32 ssa_0 = deref_var &@0 (shader_in vec4) vec1 32 ssa_0 = deref_var &@0 (shader_in vec4) vec4 32 ssa_1 = intrinsic load_deref (ssa_0) (access=0) vec4 32 ssa_1 = intrinsic load_deref (ssa_0) (access=0) vec1 32 ssa_4 = deref_var &@1 (shader_out vec4) vec1 32 ssa_4 = deref_var &@1 (shader_out vec4) intrinsic store_deref (ssa_4, ssa_1) (wrmask=xyzw /*15*/, access=0) intrinsic store_deref (ssa_4, ssa_1) (wrmask=xyzw /*15*/, access=0) /* succs: block_1 */ /* succs: block_1 */ block block_1: block block_1: } } NIR (from SPIR-V) for MESA_SHADER_FRAGMENT shader: NIR (from SPIR-V) for MESA_SHADER_FRAGMENT shader: shader: MESA_SHADER_FRAGMENT shader: MESA_SHADER_FRAGMENT source_sha1: {0x105d2b2b, 0x833fc1dc, 0xe89a3600, 0x8d3c0610, 0x72eead85} source_sha1: {0x105d2b2b, 0x833fc1dc, 0xe89a3600, 0x8d3c0610, 0x72eead85} stage: 4 stage: 4 next_stage: 0 next_stage: 0 subgroup_size: 2 subgroup_size: 2 uses_sample_shading: true uses_sample_shading: true origin_upper_left: true origin_upper_left: true depth_layout: 1 depth_layout: 1 inputs: 0 inputs: 0 outputs: 0 outputs: 0 uniforms: 120 uniforms: 120 decl_var system INTERP_MODE_NONE vec4 @0 decl_var system INTERP_MODE_NONE vec4 @0 decl_var push_const INTERP_MODE_NONE block @1 decl_var push_const INTERP_MODE_NONE block @1 decl_var system INTERP_MODE_FLAT int @2 decl_var system INTERP_MODE_FLAT int @2 decl_var shader_out INTERP_MODE_NONE vec4 @3 (FRAG_RESULT_DATA1.xyzw, 0, 0) decl_var shader_out INTERP_MODE_NONE vec4 @3 (FRAG_RESULT_DATA1.xyzw, 0, 0) decl_var shader_out INTERP_MODE_NONE vec4 @4 (FRAG_RESULT_DATA3.xyzw, 0, 0) decl_var shader_out INTERP_MODE_NONE vec4 @4 (FRAG_RESULT_DATA3.xyzw, 0, 0) decl_var shader_out INTERP_MODE_NONE ivec4 @5 (FRAG_RESULT_DATA0.xyzw, 0, 0) decl_var shader_out INTERP_MODE_NONE ivec4 @5 (FRAG_RESULT_DATA0.xyzw, 0, 0) decl_var shader_out INTERP_MODE_NONE float @6 (FRAG_RESULT_DEPTH.x, 0, 0) decl_var shader_out INTERP_MODE_NONE float @6 (FRAG_RESULT_DEPTH.x, 0, 0) decl_function main (0 params) decl_function main (0 params) impl main { impl main { decl_var INTERP_MODE_NONE vec2 @7 decl_var INTERP_MODE_NONE vec2 @7 block block_0: block block_0: /* preds: */ /* preds: */ vec1 32 ssa_20 = load_const (0x00000000 = 0.000000) vec1 32 ssa_20 = load_const (0x00000000 = 0.000000) vec1 32 ssa_18 = load_const (0x00000002 = 0.000000) vec1 32 ssa_18 = load_const (0x00000002 = 0.000000) vec1 32 ssa_0 = deref_var &@0 (system vec4) vec1 32 ssa_0 = deref_var &@0 (system vec4) vec4 32 ssa_1 = intrinsic load_deref (ssa_0) (access=0) vec4 32 ssa_1 = intrinsic load_deref (ssa_0) (access=0) vec1 32 ssa_3 = deref_var &@1 (push_const block) vec1 32 ssa_3 = deref_var &@1 (push_const block) vec1 32 ssa_4 = deref_struct &ssa_3->field0 (push_const uvec4) /* &@1.field0 */ vec1 32 ssa_4 = deref_struct &ssa_3->field0 (push_const uvec4) /* &@1.field0 */ vec4 32 ssa_5 = intrinsic load_deref (ssa_4) (access=0) vec4 32 ssa_5 = intrinsic load_deref (ssa_4) (access=0) vec2 32 ssa_7 = u2f32 ssa_5.xy vec2 32 ssa_7 = u2f32 ssa_5.xy vec2 32 ssa_8 = fsub ssa_1.xy, ssa_7 vec2 32 ssa_8 = fsub ssa_1.xy, ssa_7 vec1 32 ssa_9 = deref_var &@1 (push_const block) vec1 32 ssa_9 = deref_var &@1 (push_const block) vec1 32 ssa_10 = deref_struct &ssa_9->field0 (push_const uvec4) /* &@1.field0 */ vec1 32 ssa_10 = deref_struct &ssa_9->field0 (push_const uvec4) /* &@1.field0 */ vec4 32 ssa_11 = intrinsic load_deref (ssa_10) (access=0) vec4 32 ssa_11 = intrinsic load_deref (ssa_10) (access=0) vec2 32 ssa_13 = u2f32 ssa_11.zw vec2 32 ssa_13 = u2f32 ssa_11.zw vec2 32 ssa_14 = fdiv ssa_8, ssa_13 vec2 32 ssa_14 = fdiv ssa_8, ssa_13 vec1 32 ssa_15 = deref_var &@7 (function_temp vec2) vec1 32 ssa_15 = deref_var &@7 (function_temp vec2) intrinsic store_deref (ssa_15, ssa_14) (wrmask=xy /*3*/, access=0) intrinsic store_deref (ssa_15, ssa_14) (wrmask=xy /*3*/, access=0) vec1 32 ssa_16 = deref_var &@2 (system int) vec1 32 ssa_16 = deref_var &@2 (system int) vec1 32 ssa_17 = intrinsic load_deref (ssa_16) (access=0) vec1 32 ssa_17 = intrinsic load_deref (ssa_16) (access=0) vec1 32 ssa_19 = imod ssa_17, ssa_18 vec1 32 ssa_19 = imod ssa_17, ssa_18 vec1 1 ssa_21 = ieq ssa_19, ssa_20 vec1 1 ssa_21 = ieq ssa_19, ssa_20 /* succs: block_1 block_2 */ /* succs: block_1 block_2 */ if ssa_21 { if ssa_21 { block block_1: block block_1: /* preds: block_0 */ /* preds: block_0 */ vec1 32 ssa_22 = deref_var &@1 (push_const block) vec1 32 ssa_22 = deref_var &@1 (push_const block) vec1 32 ssa_23 = deref_struct &ssa_22->field1 (push_const vec4[2]) /* &@1.field1 */ vec1 32 ssa_23 = deref_struct &ssa_22->field1 (push_const vec4[2]) /* &@1.field1 */ vec1 32 ssa_24 = load_const (0x00000000 = 0.000000) vec1 32 ssa_24 = load_const (0x00000000 = 0.000000) vec1 32 ssa_25 = deref_array &(*ssa_23)[0] (push_const vec4) /* &@1.field1[0] */ vec1 32 ssa_25 = deref_array &(*ssa_23)[0] (push_const vec4) /* &@1.field1[0] */ vec4 32 ssa_26 = intrinsic load_deref (ssa_25) (access=0) vec4 32 ssa_26 = intrinsic load_deref (ssa_25) (access=0) vec1 32 ssa_27 = deref_var &@7 (function_temp vec2) vec1 32 ssa_27 = deref_var &@7 (function_temp vec2) vec2 32 ssa_30 = intrinsic load_deref (ssa_27) (access=0) vec2 32 ssa_30 = intrinsic load_deref (ssa_27) (access=0) vec4 32 ssa_32 = fmul ssa_26, ssa_30.xxxx vec4 32 ssa_32 = fmul ssa_26, ssa_30.xxxx vec1 32 ssa_33 = deref_var &@3 (shader_out vec4) vec1 32 ssa_33 = deref_var &@3 (shader_out vec4) intrinsic store_deref (ssa_33, ssa_32) (wrmask=xyzw /*15*/, access=0) intrinsic store_deref (ssa_33, ssa_32) (wrmask=xyzw /*15*/, access=0) vec1 32 ssa_34 = deref_var &@1 (push_const block) vec1 32 ssa_34 = deref_var &@1 (push_const block) vec1 32 ssa_35 = deref_struct &ssa_34->field2 (push_const vec4[2]) /* &@1.field2 */ vec1 32 ssa_35 = deref_struct &ssa_34->field2 (push_const vec4[2]) /* &@1.field2 */ vec1 32 ssa_36 = load_const (0x00000000 = 0.000000) vec1 32 ssa_36 = load_const (0x00000000 = 0.000000) vec1 32 ssa_37 = deref_array &(*ssa_35)[0] (push_const vec4) /* &@1.field2[0] */ vec1 32 ssa_37 = deref_array &(*ssa_35)[0] (push_const vec4) /* &@1.field2[0] */ vec4 32 ssa_38 = intrinsic load_deref (ssa_37) (access=0) vec4 32 ssa_38 = intrinsic load_deref (ssa_37) (access=0) vec1 32 ssa_39 = deref_var &@7 (function_temp vec2) vec1 32 ssa_39 = deref_var &@7 (function_temp vec2) vec2 32 ssa_42 = intrinsic load_deref (ssa_39) (access=0) vec2 32 ssa_42 = intrinsic load_deref (ssa_39) (access=0) vec4 32 ssa_44 = fmul ssa_38, ssa_42.xxxx vec4 32 ssa_44 = fmul ssa_38, ssa_42.xxxx vec1 32 ssa_45 = deref_var &@4 (shader_out vec4) vec1 32 ssa_45 = deref_var &@4 (shader_out vec4) intrinsic store_deref (ssa_45, ssa_44) (wrmask=xyzw /*15*/, access=0) intrinsic store_deref (ssa_45, ssa_44) (wrmask=xyzw /*15*/, access=0) vec1 32 ssa_46 = deref_var &@1 (push_const block) vec1 32 ssa_46 = deref_var &@1 (push_const block) vec1 32 ssa_47 = deref_struct &ssa_46->field3 (push_const ivec4[2]) /* &@1.field3 */ vec1 32 ssa_47 = deref_struct &ssa_46->field3 (push_const ivec4[2]) /* &@1.field3 */ vec1 32 ssa_48 = load_const (0x00000000 = 0.000000) vec1 32 ssa_48 = load_const (0x00000000 = 0.000000) vec1 32 ssa_49 = deref_array &(*ssa_47)[0] (push_const ivec4) /* &@1.field3[0] */ vec1 32 ssa_49 = deref_array &(*ssa_47)[0] (push_const ivec4) /* &@1.field3[0] */ vec4 32 ssa_50 = intrinsic load_deref (ssa_49) (access=0) vec4 32 ssa_50 = intrinsic load_deref (ssa_49) (access=0) vec4 32 ssa_51 = i2f32 ssa_50 vec4 32 ssa_51 = i2f32 ssa_50 vec1 32 ssa_52 = deref_var &@7 (function_temp vec2) vec1 32 ssa_52 = deref_var &@7 (function_temp vec2) vec2 32 ssa_55 = intrinsic load_deref (ssa_52) (access=0) vec2 32 ssa_55 = intrinsic load_deref (ssa_52) (access=0) vec4 32 ssa_57 = fmul ssa_51, ssa_55.xxxx vec4 32 ssa_57 = fmul ssa_51, ssa_55.xxxx vec4 32 ssa_58 = f2i32 ssa_57 vec4 32 ssa_58 = f2i32 ssa_57 vec1 32 ssa_59 = deref_var &@5 (shader_out ivec4) vec1 32 ssa_59 = deref_var &@5 (shader_out ivec4) intrinsic store_deref (ssa_59, ssa_58) (wrmask=xyzw /*15*/, access=0) intrinsic store_deref (ssa_59, ssa_58) (wrmask=xyzw /*15*/, access=0) vec1 32 ssa_60 = deref_var &@1 (push_const block) vec1 32 ssa_60 = deref_var &@1 (push_const block) vec1 32 ssa_61 = deref_struct &ssa_60->field4 (push_const vec2) /* &@1.field4 */ vec1 32 ssa_61 = deref_struct &ssa_60->field4 (push_const vec2) /* &@1.field4 */ vec1 32 ssa_62 = load_const (0x00000000 = 0.000000) vec1 32 ssa_62 = load_const (0x00000000 = 0.000000) vec1 32 ssa_63 = deref_array &(*ssa_61)[0] (push_const float) /* &@1.field4[0] */ vec1 32 ssa_63 = deref_array &(*ssa_61)[0] (push_const float) /* &@1.field4[0] */ vec1 32 ssa_64 = intrinsic load_deref (ssa_63) (access=0) vec1 32 ssa_64 = intrinsic load_deref (ssa_63) (access=0) vec1 32 ssa_65 = deref_var &@6 (shader_out float) vec1 32 ssa_65 = deref_var &@6 (shader_out float) intrinsic store_deref (ssa_65, ssa_64) (wrmask=x /*1*/, access=0) intrinsic store_deref (ssa_65, ssa_64) (wrmask=x /*1*/, access=0) /* succs: block_3 */ /* succs: block_3 */ } else { } else { block block_2: block block_2: /* preds: block_0 */ /* preds: block_0 */ vec1 32 ssa_66 = deref_var &@1 (push_const block) vec1 32 ssa_66 = deref_var &@1 (push_const block) vec1 32 ssa_67 = deref_struct &ssa_66->field1 (push_const vec4[2]) /* &@1.field1 */ vec1 32 ssa_67 = deref_struct &ssa_66->field1 (push_const vec4[2]) /* &@1.field1 */ vec1 32 ssa_68 = load_const (0x00000001 = 0.000000) vec1 32 ssa_68 = load_const (0x00000001 = 0.000000) vec1 32 ssa_69 = deref_array &(*ssa_67)[1] (push_const vec4) /* &@1.field1[1] */ vec1 32 ssa_69 = deref_array &(*ssa_67)[1] (push_const vec4) /* &@1.field1[1] */ vec4 32 ssa_70 = intrinsic load_deref (ssa_69) (access=0) vec4 32 ssa_70 = intrinsic load_deref (ssa_69) (access=0) vec1 32 ssa_71 = deref_var &@7 (function_temp vec2) vec1 32 ssa_71 = deref_var &@7 (function_temp vec2) vec2 32 ssa_74 = intrinsic load_deref (ssa_71) (access=0) vec2 32 ssa_74 = intrinsic load_deref (ssa_71) (access=0) vec4 32 ssa_76 = fmul ssa_70, ssa_74.yyyy vec4 32 ssa_76 = fmul ssa_70, ssa_74.yyyy vec1 32 ssa_77 = deref_var &@3 (shader_out vec4) vec1 32 ssa_77 = deref_var &@3 (shader_out vec4) intrinsic store_deref (ssa_77, ssa_76) (wrmask=xyzw /*15*/, access=0) intrinsic store_deref (ssa_77, ssa_76) (wrmask=xyzw /*15*/, access=0) vec1 32 ssa_78 = deref_var &@1 (push_const block) vec1 32 ssa_78 = deref_var &@1 (push_const block) vec1 32 ssa_79 = deref_struct &ssa_78->field2 (push_const vec4[2]) /* &@1.field2 */ vec1 32 ssa_79 = deref_struct &ssa_78->field2 (push_const vec4[2]) /* &@1.field2 */ vec1 32 ssa_80 = load_const (0x00000001 = 0.000000) vec1 32 ssa_80 = load_const (0x00000001 = 0.000000) vec1 32 ssa_81 = deref_array &(*ssa_79)[1] (push_const vec4) /* &@1.field2[1] */ vec1 32 ssa_81 = deref_array &(*ssa_79)[1] (push_const vec4) /* &@1.field2[1] */ vec4 32 ssa_82 = intrinsic load_deref (ssa_81) (access=0) vec4 32 ssa_82 = intrinsic load_deref (ssa_81) (access=0) vec1 32 ssa_83 = deref_var &@7 (function_temp vec2) vec1 32 ssa_83 = deref_var &@7 (function_temp vec2) vec2 32 ssa_86 = intrinsic load_deref (ssa_83) (access=0) vec2 32 ssa_86 = intrinsic load_deref (ssa_83) (access=0) vec4 32 ssa_88 = fmul ssa_82, ssa_86.yyyy vec4 32 ssa_88 = fmul ssa_82, ssa_86.yyyy vec1 32 ssa_89 = deref_var &@4 (shader_out vec4) vec1 32 ssa_89 = deref_var &@4 (shader_out vec4) intrinsic store_deref (ssa_89, ssa_88) (wrmask=xyzw /*15*/, access=0) intrinsic store_deref (ssa_89, ssa_88) (wrmask=xyzw /*15*/, access=0) vec1 32 ssa_90 = deref_var &@1 (push_const block) vec1 32 ssa_90 = deref_var &@1 (push_const block) vec1 32 ssa_91 = deref_struct &ssa_90->field3 (push_const ivec4[2]) /* &@1.field3 */ vec1 32 ssa_91 = deref_struct &ssa_90->field3 (push_const ivec4[2]) /* &@1.field3 */ vec1 32 ssa_92 = load_const (0x00000001 = 0.000000) vec1 32 ssa_92 = load_const (0x00000001 = 0.000000) vec1 32 ssa_93 = deref_array &(*ssa_91)[1] (push_const ivec4) /* &@1.field3[1] */ vec1 32 ssa_93 = deref_array &(*ssa_91)[1] (push_const ivec4) /* &@1.field3[1] */ vec4 32 ssa_94 = intrinsic load_deref (ssa_93) (access=0) vec4 32 ssa_94 = intrinsic load_deref (ssa_93) (access=0) vec4 32 ssa_95 = i2f32 ssa_94 vec4 32 ssa_95 = i2f32 ssa_94 vec1 32 ssa_96 = deref_var &@7 (function_temp vec2) vec1 32 ssa_96 = deref_var &@7 (function_temp vec2) vec2 32 ssa_99 = intrinsic load_deref (ssa_96) (access=0) vec2 32 ssa_99 = intrinsic load_deref (ssa_96) (access=0) vec4 32 ssa_101 = fmul ssa_95, ssa_99.yyyy vec4 32 ssa_101 = fmul ssa_95, ssa_99.yyyy vec4 32 ssa_102 = f2i32 ssa_101 vec4 32 ssa_102 = f2i32 ssa_101 vec1 32 ssa_103 = deref_var &@5 (shader_out ivec4) vec1 32 ssa_103 = deref_var &@5 (shader_out ivec4) intrinsic store_deref (ssa_103, ssa_102) (wrmask=xyzw /*15*/, access=0) intrinsic store_deref (ssa_103, ssa_102) (wrmask=xyzw /*15*/, access=0) vec1 32 ssa_104 = deref_var &@1 (push_const block) vec1 32 ssa_104 = deref_var &@1 (push_const block) vec1 32 ssa_105 = deref_struct &ssa_104->field4 (push_const vec2) /* &@1.field4 */ vec1 32 ssa_105 = deref_struct &ssa_104->field4 (push_const vec2) /* &@1.field4 */ vec1 32 ssa_106 = load_const (0x00000001 = 0.000000) vec1 32 ssa_106 = load_const (0x00000001 = 0.000000) vec1 32 ssa_107 = deref_array &(*ssa_105)[1] (push_const float) /* &@1.field4[1] */ vec1 32 ssa_107 = deref_array &(*ssa_105)[1] (push_const float) /* &@1.field4[1] */ vec1 32 ssa_108 = intrinsic load_deref (ssa_107) (access=0) vec1 32 ssa_108 = intrinsic load_deref (ssa_107) (access=0) vec1 32 ssa_109 = deref_var &@6 (shader_out float) vec1 32 ssa_109 = deref_var &@6 (shader_out float) intrinsic store_deref (ssa_109, ssa_108) (wrmask=x /*1*/, access=0) intrinsic store_deref (ssa_109, ssa_108) (wrmask=x /*1*/, access=0) /* succs: block_3 */ /* succs: block_3 */ } } block block_3: block block_3: /* preds: block_1 block_2 */ /* preds: block_1 block_2 */ /* succs: block_4 */ /* succs: block_4 */ block block_4: block block_4: } } NIR (SSA form) for vertex shader: NIR (SSA form) for vertex shader: shader: MESA_SHADER_VERTEX shader: MESA_SHADER_VERTEX source_sha1: {0xc53eb86f, 0x5605e25e, 0x3afa45c3, 0x86021b0d, 0x73a6d842} source_sha1: {0xc53eb86f, 0x5605e25e, 0x3afa45c3, 0x86021b0d, 0x73a6d842} stage: 0 stage: 0 next_stage: 0 next_stage: 0 inputs_read: 15 inputs_read: 15 outputs_written: 0 outputs_written: 0 subgroup_size: 2 subgroup_size: 2 divergence_analysis_run: true divergence_analysis_run: true separate_shader: true separate_shader: true inputs: 0 inputs: 0 outputs: 0 outputs: 0 uniforms: 0 uniforms: 0 decl_var shader_in INTERP_MODE_NONE vec4 @0 (VERT_ATTRIB_GENERIC0.xyzw, 15, 0) decl_var shader_in INTERP_MODE_NONE vec4 @0 (VERT_ATTRIB_GENERIC0.xyzw, 15, 0) decl_var shader_out INTERP_MODE_NONE vec4 @1 (VARYING_SLOT_POS.xyzw, 0, 0) decl_var shader_out INTERP_MODE_NONE vec4 @1 (VARYING_SLOT_POS.xyzw, 0, 0) decl_function main (0 params) decl_function main (0 params) impl main { impl main { block block_0: block block_0: /* preds: */ /* preds: */ vec1 32 con ssa_0 = load_const (0x00000000 = 0.000000) vec1 32 con ssa_0 = load_const (0x00000000 = 0.000000) vec4 32 div ssa_1 = intrinsic load_input (ssa_0) (base=0, component=0, dest_type=float32 /*160*/, io location vec4 32 div ssa_1 = intrinsic load_input (ssa_0) (base=0, component=0, dest_type=float32 /*160*/, io location intrinsic store_output (ssa_1, ssa_0) (base=0, wrmask=xyzw /*15*/, component=0, src_type=float32 /*160*/, io intrinsic store_output (ssa_1, ssa_0) (base=0, wrmask=xyzw /*15*/, component=0, src_type=float32 /*160*/, io /* succs: block_1 */ /* succs: block_1 */ block block_1: block block_1: } } NIR (final form) for vertex shader: NIR (final form) for vertex shader: shader: MESA_SHADER_VERTEX shader: MESA_SHADER_VERTEX source_sha1: {0xc53eb86f, 0x5605e25e, 0x3afa45c3, 0x86021b0d, 0x73a6d842} source_sha1: {0xc53eb86f, 0x5605e25e, 0x3afa45c3, 0x86021b0d, 0x73a6d842} stage: 0 stage: 0 next_stage: 0 next_stage: 0 inputs_read: 15 inputs_read: 15 outputs_written: 0 outputs_written: 0 subgroup_size: 2 subgroup_size: 2 divergence_analysis_run: true divergence_analysis_run: true separate_shader: true separate_shader: true inputs: 0 inputs: 0 outputs: 0 outputs: 0 uniforms: 0 uniforms: 0 decl_var shader_in INTERP_MODE_NONE vec4 @0 (VERT_ATTRIB_GENERIC0.xyzw, 15, 0) decl_var shader_in INTERP_MODE_NONE vec4 @0 (VERT_ATTRIB_GENERIC0.xyzw, 15, 0) decl_var shader_out INTERP_MODE_NONE vec4 @1 (VARYING_SLOT_POS.xyzw, 0, 0) decl_var shader_out INTERP_MODE_NONE vec4 @1 (VARYING_SLOT_POS.xyzw, 0, 0) decl_function main (0 params) decl_function main (0 params) impl main { impl main { block block_0: block block_0: /* preds: */ /* preds: */ vec1 32 con ssa_0 = load_const (0x00000000 = 0.000000) vec1 32 con ssa_0 = load_const (0x00000000 = 0.000000) vec4 32 div ssa_1 = intrinsic load_input (ssa_0) (base=0, component=0, dest_type=float32 /*160*/, io location vec4 32 div ssa_1 = intrinsic load_input (ssa_0) (base=0, component=0, dest_type=float32 /*160*/, io location intrinsic store_output (ssa_1, ssa_0) (base=0, wrmask=xyzw /*15*/, component=0, src_type=float32 /*160*/, io intrinsic store_output (ssa_1, ssa_0) (base=0, wrmask=xyzw /*15*/, component=0, src_type=float32 /*160*/, io /* succs: block_1 */ /* succs: block_1 */ block block_1: block block_1: } } VS Output VUE map (4 slots, SSO) VS Output VUE map (4 slots, SSO) [0] VARYING_SLOT_PSIZ [0] VARYING_SLOT_PSIZ [1] VARYING_SLOT_POS [1] VARYING_SLOT_POS [2] VARYING_SLOT_CLIP_DIST0 [2] VARYING_SLOT_CLIP_DIST0 [3] VARYING_SLOT_CLIP_DIST1 [3] VARYING_SLOT_CLIP_DIST1 Native code for unnamed vertex shader (null) (sha1 b70dfaf2bb58ae45f979a67e09a12f4d8694a075) Native code for unnamed vertex shader (null) (sha1 b70dfaf2bb58ae45f979a67e09a12f4d8694a075) SIMD8 shader: 7 instructions. 0 loops. 22 cycles. 0:0 spills:fills, 1 sends, scheduled with mode top-down. Promoted 0 SIMD8 shader: 7 instructions. 0 loops. 22 cycles. 0:0 spills:fills, 1 sends, scheduled with mode top-down. Promoted 0 START B0 (22 cycles) START B0 (22 cycles) mov(8) g122<1>F g2<1,1,0>F { align1 1Q compacted }; mov(8) g122<1>F g2<1,1,0>F { align1 1Q compacted }; mov(8) g123<1>F g3<1,1,0>F { align1 1Q compacted }; mov(8) g123<1>F g3<1,1,0>F { align1 1Q compacted }; mov(8) g124<1>F g4<1,1,0>F { align1 1Q compacted }; mov(8) g124<1>F g4<1,1,0>F { align1 1Q compacted }; mov(8) g125<1>F g5<1,1,0>F { align1 1Q compacted }; mov(8) g125<1>F g5<1,1,0>F { align1 1Q compacted }; mov(8) g126<1>UD g1<8,8,1>UD { align1 WE_all 1Q }; mov(8) g126<1>UD g1<8,8,1>UD { align1 WE_all 1Q }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N A@1 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N A@1 }; send(8) nullUD g126UD g122UD 0x02080017 0x00000100 send(8) nullUD g126UD g122UD 0x02080017 0x00000100 urb MsgDesc: offset 1 SIMD8 write mlen 1 ex_mlen 4 rlen 0 { align1 1Q A@1 EOT }; urb MsgDesc: offset 1 SIMD8 write mlen 1 ex_mlen 4 rlen 0 { align1 1Q A@1 EOT }; END B0 END B0 NIR (SSA form) for fragment shader: NIR (SSA form) for fragment shader: shader: MESA_SHADER_FRAGMENT shader: MESA_SHADER_FRAGMENT source_sha1: {0x105d2b2b, 0x833fc1dc, 0xe89a3600, 0x8d3c0610, 0x72eead85} source_sha1: {0x105d2b2b, 0x833fc1dc, 0xe89a3600, 0x8d3c0610, 0x72eead85} stage: 4 stage: 4 next_stage: 0 next_stage: 0 outputs_written: 0,4-5,7 outputs_written: 0,4-5,7 system_values_read: 0x00000000'00000000'02880000 system_values_read: 0x00000000'00000000'02880000 subgroup_size: 2 subgroup_size: 2 divergence_analysis_run: true divergence_analysis_run: true bit_sizes_float: 0x20 bit_sizes_float: 0x20 bit_sizes_int: 0x21 bit_sizes_int: 0x21 separate_shader: true separate_shader: true uses_sample_shading: true uses_sample_shading: true origin_upper_left: true origin_upper_left: true depth_layout: 1 depth_layout: 1 inputs: 0 inputs: 0 outputs: 0 outputs: 0 uniforms: 120 uniforms: 120 decl_var push_const INTERP_MODE_NONE block @0 decl_var push_const INTERP_MODE_NONE block @0 decl_var shader_out INTERP_MODE_NONE vec4 @1 (FRAG_RESULT_DATA1.xyzw, 10, 0) decl_var shader_out INTERP_MODE_NONE vec4 @1 (FRAG_RESULT_DATA1.xyzw, 10, 0) decl_var shader_out INTERP_MODE_NONE vec4 @2 (FRAG_RESULT_DATA3.xyzw, 14, 0) decl_var shader_out INTERP_MODE_NONE vec4 @2 (FRAG_RESULT_DATA3.xyzw, 14, 0) decl_var shader_out INTERP_MODE_NONE ivec4 @3 (FRAG_RESULT_DATA0.xyzw, 8, 0) decl_var shader_out INTERP_MODE_NONE ivec4 @3 (FRAG_RESULT_DATA0.xyzw, 8, 0) decl_var shader_out INTERP_MODE_NONE float @4 (FRAG_RESULT_DEPTH.x, 0, 0) decl_var shader_out INTERP_MODE_NONE float @4 (FRAG_RESULT_DEPTH.x, 0, 0) decl_function main (0 params) decl_function main (0 params) impl main { impl main { block block_0: block block_0: /* preds: */ /* preds: */ vec1 32 con ssa_0 = load_const (0x00000000 = 0.000000) vec1 32 con ssa_0 = load_const (0x00000000 = 0.000000) vec4 32 div ssa_1 = intrinsic load_frag_coord () () vec4 32 div ssa_1 = intrinsic load_frag_coord () () vec2 32 div ssa_2 = intrinsic load_sample_pos_or_center () () vec2 32 div ssa_2 = intrinsic load_sample_pos_or_center () () vec1 32 div ssa_3 = fadd ssa_1.x, ssa_2.x vec1 32 div ssa_3 = fadd ssa_1.x, ssa_2.x vec1 32 div ssa_4 = fadd ssa_1.y, ssa_2.y vec1 32 div ssa_4 = fadd ssa_1.y, ssa_2.y vec4 32 con ssa_5 = intrinsic load_uniform (ssa_0) (base=0, range=120, dest_type=invalid /*256*/) vec4 32 con ssa_5 = intrinsic load_uniform (ssa_0) (base=0, range=120, dest_type=invalid /*256*/) vec1 32 con ssa_6 = u2f32 ssa_5.x vec1 32 con ssa_6 = u2f32 ssa_5.x vec1 32 con ssa_7 = u2f32 ssa_5.y vec1 32 con ssa_7 = u2f32 ssa_5.y vec1 32 con ssa_8 = fneg ssa_6 vec1 32 con ssa_8 = fneg ssa_6 vec1 32 div ssa_9 = fadd ssa_3, ssa_8 vec1 32 div ssa_9 = fadd ssa_3, ssa_8 vec1 32 con ssa_10 = fneg ssa_7 vec1 32 con ssa_10 = fneg ssa_7 vec1 32 div ssa_11 = fadd ssa_4, ssa_10 vec1 32 div ssa_11 = fadd ssa_4, ssa_10 vec1 32 con ssa_12 = u2f32 ssa_5.z vec1 32 con ssa_12 = u2f32 ssa_5.z vec1 32 con ssa_13 = u2f32 ssa_5.w vec1 32 con ssa_13 = u2f32 ssa_5.w vec1 32 con ssa_14 = frcp ssa_12 vec1 32 con ssa_14 = frcp ssa_12 vec1 32 div ssa_15 = fmul ssa_9, ssa_14 vec1 32 div ssa_15 = fmul ssa_9, ssa_14 vec1 32 con ssa_16 = frcp ssa_13 vec1 32 con ssa_16 = frcp ssa_13 vec1 32 div ssa_17 = fmul ssa_11, ssa_16 vec1 32 div ssa_17 = fmul ssa_11, ssa_16 vec1 32 div ssa_18 = intrinsic load_sample_id () () vec1 32 div ssa_18 = intrinsic load_sample_id () () vec1 32 con ssa_19 = load_const (0x00000001 = 0.000000) vec1 32 con ssa_19 = load_const (0x00000001 = 0.000000) vec1 32 div ssa_20 = iand ssa_18, ssa_19 vec1 32 div ssa_20 = iand ssa_18, ssa_19 vec1 32 div ssa_21 = ieq32 ssa_20, ssa_0 vec1 32 div ssa_21 = ieq32 ssa_20, ssa_0 /* succs: block_1 block_2 */ /* succs: block_1 block_2 */ if ssa_21 { if ssa_21 { block block_1: block block_1: /* preds: block_0 */ /* preds: block_0 */ vec1 32 con ssa_22 = load_const (0x00000010 = 0.000000) vec1 32 con ssa_22 = load_const (0x00000010 = 0.000000) vec4 32 con ssa_23 = intrinsic load_uniform (ssa_22) (base=0, range=120, dest_type=invalid /*256*/) vec4 32 con ssa_23 = intrinsic load_uniform (ssa_22) (base=0, range=120, dest_type=invalid /*256*/) vec1 32 div ssa_24 = fmul ssa_23.x, ssa_15 vec1 32 div ssa_24 = fmul ssa_23.x, ssa_15 vec1 32 div ssa_25 = fmul ssa_23.y, ssa_15 vec1 32 div ssa_25 = fmul ssa_23.y, ssa_15 vec1 32 div ssa_26 = fmul ssa_23.z, ssa_15 vec1 32 div ssa_26 = fmul ssa_23.z, ssa_15 vec1 32 div ssa_27 = fmul ssa_23.w, ssa_15 vec1 32 div ssa_27 = fmul ssa_23.w, ssa_15 vec1 32 con ssa_28 = load_const (0x00000030 = 0.000000) vec1 32 con ssa_28 = load_const (0x00000030 = 0.000000) vec4 32 con ssa_29 = intrinsic load_uniform (ssa_28) (base=0, range=120, dest_type=invalid /*256*/) vec4 32 con ssa_29 = intrinsic load_uniform (ssa_28) (base=0, range=120, dest_type=invalid /*256*/) vec1 32 div ssa_30 = fmul ssa_29.x, ssa_15 vec1 32 div ssa_30 = fmul ssa_29.x, ssa_15 vec1 32 div ssa_31 = fmul ssa_29.y, ssa_15 vec1 32 div ssa_31 = fmul ssa_29.y, ssa_15 vec1 32 div ssa_32 = fmul ssa_29.z, ssa_15 vec1 32 div ssa_32 = fmul ssa_29.z, ssa_15 vec1 32 div ssa_33 = fmul ssa_29.w, ssa_15 vec1 32 div ssa_33 = fmul ssa_29.w, ssa_15 vec1 32 con ssa_34 = load_const (0x00000050 = 0.000000) vec1 32 con ssa_34 = load_const (0x00000050 = 0.000000) vec4 32 con ssa_35 = intrinsic load_uniform (ssa_34) (base=0, range=120, dest_type=invalid /*256*/) vec4 32 con ssa_35 = intrinsic load_uniform (ssa_34) (base=0, range=120, dest_type=invalid /*256*/) vec1 32 con ssa_36 = i2f32 ssa_35.x vec1 32 con ssa_36 = i2f32 ssa_35.x vec1 32 con ssa_37 = i2f32 ssa_35.y vec1 32 con ssa_37 = i2f32 ssa_35.y vec1 32 con ssa_38 = i2f32 ssa_35.z vec1 32 con ssa_38 = i2f32 ssa_35.z vec1 32 con ssa_39 = i2f32 ssa_35.w vec1 32 con ssa_39 = i2f32 ssa_35.w vec1 32 div ssa_40 = fmul ssa_36, ssa_15 vec1 32 div ssa_40 = fmul ssa_36, ssa_15 vec1 32 div ssa_41 = fmul ssa_37, ssa_15 vec1 32 div ssa_41 = fmul ssa_37, ssa_15 vec1 32 div ssa_42 = fmul ssa_38, ssa_15 vec1 32 div ssa_42 = fmul ssa_38, ssa_15 vec1 32 div ssa_43 = fmul ssa_39, ssa_15 vec1 32 div ssa_43 = fmul ssa_39, ssa_15 vec1 32 div ssa_44 = f2i32 ssa_40 vec1 32 div ssa_44 = f2i32 ssa_40 vec1 32 div ssa_45 = f2i32 ssa_41 vec1 32 div ssa_45 = f2i32 ssa_41 vec1 32 div ssa_46 = f2i32 ssa_42 vec1 32 div ssa_46 = f2i32 ssa_42 vec1 32 div ssa_47 = f2i32 ssa_43 vec1 32 div ssa_47 = f2i32 ssa_43 vec1 32 con ssa_48 = load_const (0x00000070 = 0.000000) vec1 32 con ssa_48 = load_const (0x00000070 = 0.000000) vec1 32 con ssa_49 = intrinsic load_uniform (ssa_48) (base=0, range=120, dest_type=invalid /*256*/) vec1 32 con ssa_49 = intrinsic load_uniform (ssa_48) (base=0, range=120, dest_type=invalid /*256*/) /* succs: block_3 */ /* succs: block_3 */ } else { } else { block block_2: block block_2: /* preds: block_0 */ /* preds: block_0 */ vec1 32 con ssa_50 = load_const (0x00000020 = 0.000000) vec1 32 con ssa_50 = load_const (0x00000020 = 0.000000) vec4 32 con ssa_51 = intrinsic load_uniform (ssa_50) (base=0, range=120, dest_type=invalid /*256*/) vec4 32 con ssa_51 = intrinsic load_uniform (ssa_50) (base=0, range=120, dest_type=invalid /*256*/) vec1 32 div ssa_52 = fmul ssa_51.x, ssa_17 vec1 32 div ssa_52 = fmul ssa_51.x, ssa_17 vec1 32 div ssa_53 = fmul ssa_51.y, ssa_17 vec1 32 div ssa_53 = fmul ssa_51.y, ssa_17 vec1 32 div ssa_54 = fmul ssa_51.z, ssa_17 vec1 32 div ssa_54 = fmul ssa_51.z, ssa_17 vec1 32 div ssa_55 = fmul ssa_51.w, ssa_17 vec1 32 div ssa_55 = fmul ssa_51.w, ssa_17 vec1 32 con ssa_56 = load_const (0x00000040 = 0.000000) vec1 32 con ssa_56 = load_const (0x00000040 = 0.000000) vec4 32 con ssa_57 = intrinsic load_uniform (ssa_56) (base=0, range=120, dest_type=invalid /*256*/) vec4 32 con ssa_57 = intrinsic load_uniform (ssa_56) (base=0, range=120, dest_type=invalid /*256*/) vec1 32 div ssa_58 = fmul ssa_57.x, ssa_17 vec1 32 div ssa_58 = fmul ssa_57.x, ssa_17 vec1 32 div ssa_59 = fmul ssa_57.y, ssa_17 vec1 32 div ssa_59 = fmul ssa_57.y, ssa_17 vec1 32 div ssa_60 = fmul ssa_57.z, ssa_17 vec1 32 div ssa_60 = fmul ssa_57.z, ssa_17 vec1 32 div ssa_61 = fmul ssa_57.w, ssa_17 vec1 32 div ssa_61 = fmul ssa_57.w, ssa_17 vec1 32 con ssa_62 = load_const (0x00000060 = 0.000000) vec1 32 con ssa_62 = load_const (0x00000060 = 0.000000) vec4 32 con ssa_63 = intrinsic load_uniform (ssa_62) (base=0, range=120, dest_type=invalid /*256*/) vec4 32 con ssa_63 = intrinsic load_uniform (ssa_62) (base=0, range=120, dest_type=invalid /*256*/) vec1 32 con ssa_64 = i2f32 ssa_63.x vec1 32 con ssa_64 = i2f32 ssa_63.x vec1 32 con ssa_65 = i2f32 ssa_63.y vec1 32 con ssa_65 = i2f32 ssa_63.y vec1 32 con ssa_66 = i2f32 ssa_63.z vec1 32 con ssa_66 = i2f32 ssa_63.z vec1 32 con ssa_67 = i2f32 ssa_63.w vec1 32 con ssa_67 = i2f32 ssa_63.w vec1 32 div ssa_68 = fmul ssa_64, ssa_17 vec1 32 div ssa_68 = fmul ssa_64, ssa_17 vec1 32 div ssa_69 = fmul ssa_65, ssa_17 vec1 32 div ssa_69 = fmul ssa_65, ssa_17 vec1 32 div ssa_70 = fmul ssa_66, ssa_17 vec1 32 div ssa_70 = fmul ssa_66, ssa_17 vec1 32 div ssa_71 = fmul ssa_67, ssa_17 vec1 32 div ssa_71 = fmul ssa_67, ssa_17 vec1 32 div ssa_72 = f2i32 ssa_68 vec1 32 div ssa_72 = f2i32 ssa_68 vec1 32 div ssa_73 = f2i32 ssa_69 vec1 32 div ssa_73 = f2i32 ssa_69 vec1 32 div ssa_74 = f2i32 ssa_70 vec1 32 div ssa_74 = f2i32 ssa_70 vec1 32 div ssa_75 = f2i32 ssa_71 vec1 32 div ssa_75 = f2i32 ssa_71 vec1 32 con ssa_76 = load_const (0x00000074 = 0.000000) vec1 32 con ssa_76 = load_const (0x00000074 = 0.000000) vec1 32 con ssa_77 = intrinsic load_uniform (ssa_76) (base=0, range=120, dest_type=invalid /*256*/) vec1 32 con ssa_77 = intrinsic load_uniform (ssa_76) (base=0, range=120, dest_type=invalid /*256*/) /* succs: block_3 */ /* succs: block_3 */ } } block block_3: block block_3: /* preds: block_1 block_2 */ /* preds: block_1 block_2 */ vec1 32 div ssa_78 = phi block_1: ssa_49, block_2: ssa_77 vec1 32 div ssa_78 = phi block_1: ssa_49, block_2: ssa_77 vec1 32 div ssa_79 = phi block_1: ssa_44, block_2: ssa_72 vec1 32 div ssa_79 = phi block_1: ssa_44, block_2: ssa_72 vec1 32 div ssa_80 = phi block_1: ssa_45, block_2: ssa_73 vec1 32 div ssa_80 = phi block_1: ssa_45, block_2: ssa_73 vec1 32 div ssa_81 = phi block_1: ssa_46, block_2: ssa_74 vec1 32 div ssa_81 = phi block_1: ssa_46, block_2: ssa_74 vec1 32 div ssa_82 = phi block_1: ssa_47, block_2: ssa_75 vec1 32 div ssa_82 = phi block_1: ssa_47, block_2: ssa_75 vec1 32 div ssa_83 = phi block_1: ssa_30, block_2: ssa_58 vec1 32 div ssa_83 = phi block_1: ssa_30, block_2: ssa_58 vec1 32 div ssa_84 = phi block_1: ssa_31, block_2: ssa_59 vec1 32 div ssa_84 = phi block_1: ssa_31, block_2: ssa_59 vec1 32 div ssa_85 = phi block_1: ssa_32, block_2: ssa_60 vec1 32 div ssa_85 = phi block_1: ssa_32, block_2: ssa_60 vec1 32 div ssa_86 = phi block_1: ssa_33, block_2: ssa_61 vec1 32 div ssa_86 = phi block_1: ssa_33, block_2: ssa_61 vec1 32 div ssa_87 = phi block_1: ssa_24, block_2: ssa_52 vec1 32 div ssa_87 = phi block_1: ssa_24, block_2: ssa_52 vec1 32 div ssa_88 = phi block_1: ssa_25, block_2: ssa_53 vec1 32 div ssa_88 = phi block_1: ssa_25, block_2: ssa_53 vec1 32 div ssa_89 = phi block_1: ssa_26, block_2: ssa_54 vec1 32 div ssa_89 = phi block_1: ssa_26, block_2: ssa_54 vec1 32 div ssa_90 = phi block_1: ssa_27, block_2: ssa_55 vec1 32 div ssa_90 = phi block_1: ssa_27, block_2: ssa_55 vec4 32 div ssa_91 = vec4 ssa_87, ssa_88, ssa_89, ssa_90 vec4 32 div ssa_91 = vec4 ssa_87, ssa_88, ssa_89, ssa_90 vec4 32 div ssa_92 = vec4 ssa_83, ssa_84, ssa_85, ssa_86 vec4 32 div ssa_92 = vec4 ssa_83, ssa_84, ssa_85, ssa_86 vec4 32 div ssa_93 = vec4 ssa_79, ssa_80, ssa_81, ssa_82 vec4 32 div ssa_93 = vec4 ssa_79, ssa_80, ssa_81, ssa_82 intrinsic store_output (ssa_91, ssa_0) (base=10, wrmask=xyzw /*15*/, component=0, src_type=float32 /*160*/, i intrinsic store_output (ssa_91, ssa_0) (base=10, wrmask=xyzw /*15*/, component=0, src_type=float32 /*160*/, i intrinsic store_output (ssa_92, ssa_0) (base=14, wrmask=xyzw /*15*/, component=0, src_type=float32 /*160*/, i intrinsic store_output (ssa_92, ssa_0) (base=14, wrmask=xyzw /*15*/, component=0, src_type=float32 /*160*/, i intrinsic store_output (ssa_93, ssa_0) (base=8, wrmask=xyzw /*15*/, component=0, src_type=int32 /*34*/, io lo intrinsic store_output (ssa_93, ssa_0) (base=8, wrmask=xyzw /*15*/, component=0, src_type=int32 /*34*/, io lo intrinsic store_output (ssa_78, ssa_0) (base=0, wrmask=x /*1*/, component=0, src_type=float32 /*160*/, io loc intrinsic store_output (ssa_78, ssa_0) (base=0, wrmask=x /*1*/, component=0, src_type=float32 /*160*/, io loc /* succs: block_4 */ /* succs: block_4 */ block block_4: block block_4: } } NIR (final form) for fragment shader: NIR (final form) for fragment shader: shader: MESA_SHADER_FRAGMENT shader: MESA_SHADER_FRAGMENT source_sha1: {0x105d2b2b, 0x833fc1dc, 0xe89a3600, 0x8d3c0610, 0x72eead85} source_sha1: {0x105d2b2b, 0x833fc1dc, 0xe89a3600, 0x8d3c0610, 0x72eead85} stage: 4 stage: 4 next_stage: 0 next_stage: 0 outputs_written: 0,4-5,7 outputs_written: 0,4-5,7 system_values_read: 0x00000000'00000000'02880000 system_values_read: 0x00000000'00000000'02880000 subgroup_size: 2 subgroup_size: 2 divergence_analysis_run: true divergence_analysis_run: true bit_sizes_float: 0x20 bit_sizes_float: 0x20 bit_sizes_int: 0x21 bit_sizes_int: 0x21 separate_shader: true separate_shader: true uses_sample_shading: true uses_sample_shading: true origin_upper_left: true origin_upper_left: true depth_layout: 1 depth_layout: 1 inputs: 0 inputs: 0 outputs: 0 outputs: 0 uniforms: 120 uniforms: 120 decl_var push_const INTERP_MODE_NONE block @0 decl_var push_const INTERP_MODE_NONE block @0 decl_var shader_out INTERP_MODE_NONE vec4 @1 (FRAG_RESULT_DATA1.xyzw, 10, 0) decl_var shader_out INTERP_MODE_NONE vec4 @1 (FRAG_RESULT_DATA1.xyzw, 10, 0) decl_var shader_out INTERP_MODE_NONE vec4 @2 (FRAG_RESULT_DATA3.xyzw, 14, 0) decl_var shader_out INTERP_MODE_NONE vec4 @2 (FRAG_RESULT_DATA3.xyzw, 14, 0) decl_var shader_out INTERP_MODE_NONE ivec4 @3 (FRAG_RESULT_DATA0.xyzw, 8, 0) decl_var shader_out INTERP_MODE_NONE ivec4 @3 (FRAG_RESULT_DATA0.xyzw, 8, 0) decl_var shader_out INTERP_MODE_NONE float @4 (FRAG_RESULT_DEPTH.x, 0, 0) decl_var shader_out INTERP_MODE_NONE float @4 (FRAG_RESULT_DEPTH.x, 0, 0) decl_function main (0 params) decl_function main (0 params) impl main { impl main { decl_reg vec1 32 div r0 decl_reg vec1 32 div r0 decl_reg vec1 32 div r1 decl_reg vec1 32 div r1 decl_reg vec1 32 div r2 decl_reg vec1 32 div r2 decl_reg vec1 32 div r3 decl_reg vec1 32 div r3 decl_reg vec1 32 div r4 decl_reg vec1 32 div r4 decl_reg vec1 32 div r5 decl_reg vec1 32 div r5 decl_reg vec1 32 div r6 decl_reg vec1 32 div r6 decl_reg vec1 32 div r7 decl_reg vec1 32 div r7 decl_reg vec1 32 div r8 decl_reg vec1 32 div r8 decl_reg vec1 32 div r9 decl_reg vec1 32 div r9 decl_reg vec1 32 div r10 decl_reg vec1 32 div r10 decl_reg vec1 32 div r11 decl_reg vec1 32 div r11 decl_reg vec1 32 con r12 decl_reg vec1 32 con r12 decl_reg vec1 32 div r13 decl_reg vec1 32 div r13 decl_reg vec1 32 con r14 decl_reg vec1 32 con r14 block block_0: block block_0: /* preds: */ /* preds: */ vec1 32 con ssa_0 = load_const (0x00000000 = 0.000000) vec1 32 con ssa_0 = load_const (0x00000000 = 0.000000) vec4 32 div ssa_1 = intrinsic load_frag_coord () () vec4 32 div ssa_1 = intrinsic load_frag_coord () () vec2 32 div ssa_2 = intrinsic load_sample_pos_or_center () () vec2 32 div ssa_2 = intrinsic load_sample_pos_or_center () () vec1 32 div ssa_3 = fadd ssa_1.x, ssa_2.x vec1 32 div ssa_3 = fadd ssa_1.x, ssa_2.x vec1 32 div ssa_4 = fadd ssa_1.y, ssa_2.y vec1 32 div ssa_4 = fadd ssa_1.y, ssa_2.y vec4 32 con ssa_5 = intrinsic load_uniform (ssa_0) (base=0, range=120, dest_type=invalid /*256*/) vec4 32 con ssa_5 = intrinsic load_uniform (ssa_0) (base=0, range=120, dest_type=invalid /*256*/) vec1 32 con ssa_6 = u2f32 ssa_5.x vec1 32 con ssa_6 = u2f32 ssa_5.x vec1 32 con ssa_7 = u2f32 ssa_5.y vec1 32 con ssa_7 = u2f32 ssa_5.y vec1 32 con ssa_8 = fneg ssa_6 vec1 32 con ssa_8 = fneg ssa_6 vec1 32 div ssa_9 = fadd ssa_3, ssa_8 vec1 32 div ssa_9 = fadd ssa_3, ssa_8 vec1 32 con ssa_10 = fneg ssa_7 vec1 32 con ssa_10 = fneg ssa_7 vec1 32 div ssa_11 = fadd ssa_4, ssa_10 vec1 32 div ssa_11 = fadd ssa_4, ssa_10 vec1 32 con ssa_12 = u2f32 ssa_5.z vec1 32 con ssa_12 = u2f32 ssa_5.z vec1 32 con ssa_13 = u2f32 ssa_5.w vec1 32 con ssa_13 = u2f32 ssa_5.w vec1 32 con ssa_14 = frcp ssa_12 vec1 32 con ssa_14 = frcp ssa_12 vec1 32 div ssa_15 = fmul ssa_9, ssa_14 vec1 32 div ssa_15 = fmul ssa_9, ssa_14 vec1 32 con ssa_16 = frcp ssa_13 vec1 32 con ssa_16 = frcp ssa_13 vec1 32 div ssa_17 = fmul ssa_11, ssa_16 vec1 32 div ssa_17 = fmul ssa_11, ssa_16 vec1 32 div ssa_18 = intrinsic load_sample_id () () vec1 32 div ssa_18 = intrinsic load_sample_id () () vec1 32 con ssa_19 = load_const (0x00000001 = 0.000000) vec1 32 con ssa_19 = load_const (0x00000001 = 0.000000) vec1 32 div ssa_20 = iand ssa_18, ssa_19 vec1 32 div ssa_20 = iand ssa_18, ssa_19 vec1 32 div ssa_21 = ieq32 ssa_20, ssa_0 vec1 32 div ssa_21 = ieq32 ssa_20, ssa_0 /* succs: block_1 block_2 */ /* succs: block_1 block_2 */ if ssa_21 { if ssa_21 { block block_1: block block_1: /* preds: block_0 */ /* preds: block_0 */ vec1 32 con ssa_22 = load_const (0x00000010 = 0.000000) vec1 32 con ssa_22 = load_const (0x00000010 = 0.000000) vec4 32 con ssa_23 = intrinsic load_uniform (ssa_22) (base=0, range=120, dest_type=invalid /*256*/) vec4 32 con ssa_23 = intrinsic load_uniform (ssa_22) (base=0, range=120, dest_type=invalid /*256*/) div r0 = fmul ssa_23.x, ssa_15 div r0 = fmul ssa_23.x, ssa_15 div r1 = fmul ssa_23.y, ssa_15 div r1 = fmul ssa_23.y, ssa_15 div r2 = fmul ssa_23.z, ssa_15 div r2 = fmul ssa_23.z, ssa_15 div r3 = fmul ssa_23.w, ssa_15 div r3 = fmul ssa_23.w, ssa_15 vec1 32 con ssa_28 = load_const (0x00000030 = 0.000000) vec1 32 con ssa_28 = load_const (0x00000030 = 0.000000) vec4 32 con ssa_29 = intrinsic load_uniform (ssa_28) (base=0, range=120, dest_type=invalid /*256*/) vec4 32 con ssa_29 = intrinsic load_uniform (ssa_28) (base=0, range=120, dest_type=invalid /*256*/) div r4 = fmul ssa_29.x, ssa_15 div r4 = fmul ssa_29.x, ssa_15 div r5 = fmul ssa_29.y, ssa_15 div r5 = fmul ssa_29.y, ssa_15 div r6 = fmul ssa_29.z, ssa_15 div r6 = fmul ssa_29.z, ssa_15 div r7 = fmul ssa_29.w, ssa_15 div r7 = fmul ssa_29.w, ssa_15 vec1 32 con ssa_34 = load_const (0x00000050 = 0.000000) vec1 32 con ssa_34 = load_const (0x00000050 = 0.000000) vec4 32 con ssa_35 = intrinsic load_uniform (ssa_34) (base=0, range=120, dest_type=invalid /*256*/) vec4 32 con ssa_35 = intrinsic load_uniform (ssa_34) (base=0, range=120, dest_type=invalid /*256*/) vec1 32 con ssa_36 = i2f32 ssa_35.x vec1 32 con ssa_36 = i2f32 ssa_35.x vec1 32 con ssa_37 = i2f32 ssa_35.y vec1 32 con ssa_37 = i2f32 ssa_35.y vec1 32 con ssa_38 = i2f32 ssa_35.z vec1 32 con ssa_38 = i2f32 ssa_35.z vec1 32 con ssa_39 = i2f32 ssa_35.w vec1 32 con ssa_39 = i2f32 ssa_35.w vec1 32 div ssa_40 = fmul ssa_36, ssa_15 vec1 32 div ssa_40 = fmul ssa_36, ssa_15 vec1 32 div ssa_41 = fmul ssa_37, ssa_15 vec1 32 div ssa_41 = fmul ssa_37, ssa_15 vec1 32 div ssa_42 = fmul ssa_38, ssa_15 vec1 32 div ssa_42 = fmul ssa_38, ssa_15 vec1 32 div ssa_43 = fmul ssa_39, ssa_15 vec1 32 div ssa_43 = fmul ssa_39, ssa_15 div r8 = f2i32 ssa_40 div r8 = f2i32 ssa_40 div r9 = f2i32 ssa_41 div r9 = f2i32 ssa_41 div r10 = f2i32 ssa_42 div r10 = f2i32 ssa_42 div r11 = f2i32 ssa_43 div r11 = f2i32 ssa_43 vec1 32 con ssa_48 = load_const (0x00000070 = 0.000000) vec1 32 con ssa_48 = load_const (0x00000070 = 0.000000) con r12 = intrinsic load_uniform (ssa_48) (base=0, range=120, dest_type=invalid /*256*/) con r12 = intrinsic load_uniform (ssa_48) (base=0, range=120, dest_type=invalid /*256*/) div r13 = mov r12 div r13 = mov r12 /* succs: block_3 */ /* succs: block_3 */ } else { } else { block block_2: block block_2: /* preds: block_0 */ /* preds: block_0 */ vec1 32 con ssa_50 = load_const (0x00000020 = 0.000000) vec1 32 con ssa_50 = load_const (0x00000020 = 0.000000) vec4 32 con ssa_51 = intrinsic load_uniform (ssa_50) (base=0, range=120, dest_type=invalid /*256*/) vec4 32 con ssa_51 = intrinsic load_uniform (ssa_50) (base=0, range=120, dest_type=invalid /*256*/) div r0 = fmul ssa_51.x, ssa_17 div r0 = fmul ssa_51.x, ssa_17 div r1 = fmul ssa_51.y, ssa_17 div r1 = fmul ssa_51.y, ssa_17 div r2 = fmul ssa_51.z, ssa_17 div r2 = fmul ssa_51.z, ssa_17 div r3 = fmul ssa_51.w, ssa_17 div r3 = fmul ssa_51.w, ssa_17 vec1 32 con ssa_56 = load_const (0x00000040 = 0.000000) vec1 32 con ssa_56 = load_const (0x00000040 = 0.000000) vec4 32 con ssa_57 = intrinsic load_uniform (ssa_56) (base=0, range=120, dest_type=invalid /*256*/) vec4 32 con ssa_57 = intrinsic load_uniform (ssa_56) (base=0, range=120, dest_type=invalid /*256*/) div r4 = fmul ssa_57.x, ssa_17 div r4 = fmul ssa_57.x, ssa_17 div r5 = fmul ssa_57.y, ssa_17 div r5 = fmul ssa_57.y, ssa_17 div r6 = fmul ssa_57.z, ssa_17 div r6 = fmul ssa_57.z, ssa_17 div r7 = fmul ssa_57.w, ssa_17 div r7 = fmul ssa_57.w, ssa_17 vec1 32 con ssa_62 = load_const (0x00000060 = 0.000000) vec1 32 con ssa_62 = load_const (0x00000060 = 0.000000) vec4 32 con ssa_63 = intrinsic load_uniform (ssa_62) (base=0, range=120, dest_type=invalid /*256*/) vec4 32 con ssa_63 = intrinsic load_uniform (ssa_62) (base=0, range=120, dest_type=invalid /*256*/) vec1 32 con ssa_64 = i2f32 ssa_63.x vec1 32 con ssa_64 = i2f32 ssa_63.x vec1 32 con ssa_65 = i2f32 ssa_63.y vec1 32 con ssa_65 = i2f32 ssa_63.y vec1 32 con ssa_66 = i2f32 ssa_63.z vec1 32 con ssa_66 = i2f32 ssa_63.z vec1 32 con ssa_67 = i2f32 ssa_63.w vec1 32 con ssa_67 = i2f32 ssa_63.w vec1 32 div ssa_68 = fmul ssa_64, ssa_17 vec1 32 div ssa_68 = fmul ssa_64, ssa_17 vec1 32 div ssa_69 = fmul ssa_65, ssa_17 vec1 32 div ssa_69 = fmul ssa_65, ssa_17 vec1 32 div ssa_70 = fmul ssa_66, ssa_17 vec1 32 div ssa_70 = fmul ssa_66, ssa_17 vec1 32 div ssa_71 = fmul ssa_67, ssa_17 vec1 32 div ssa_71 = fmul ssa_67, ssa_17 div r8 = f2i32 ssa_68 div r8 = f2i32 ssa_68 div r9 = f2i32 ssa_69 div r9 = f2i32 ssa_69 div r10 = f2i32 ssa_70 div r10 = f2i32 ssa_70 div r11 = f2i32 ssa_71 div r11 = f2i32 ssa_71 vec1 32 con ssa_76 = load_const (0x00000074 = 0.000000) vec1 32 con ssa_76 = load_const (0x00000074 = 0.000000) con r14 = intrinsic load_uniform (ssa_76) (base=0, range=120, dest_type=invalid /*256*/) con r14 = intrinsic load_uniform (ssa_76) (base=0, range=120, dest_type=invalid /*256*/) div r13 = mov r14 div r13 = mov r14 /* succs: block_3 */ /* succs: block_3 */ } } block block_3: block block_3: /* preds: block_1 block_2 */ /* preds: block_1 block_2 */ vec4 32 div ssa_91 = vec4 r0, r1, r2, r3 vec4 32 div ssa_91 = vec4 r0, r1, r2, r3 vec4 32 div ssa_92 = vec4 r4, r5, r6, r7 vec4 32 div ssa_92 = vec4 r4, r5, r6, r7 vec4 32 div ssa_93 = vec4 r8, r9, r10, r11 vec4 32 div ssa_93 = vec4 r8, r9, r10, r11 intrinsic store_output (ssa_91, ssa_0) (base=10, wrmask=xyzw /*15*/, component=0, src_type=float32 /*160*/, i intrinsic store_output (ssa_91, ssa_0) (base=10, wrmask=xyzw /*15*/, component=0, src_type=float32 /*160*/, i intrinsic store_output (ssa_92, ssa_0) (base=14, wrmask=xyzw /*15*/, component=0, src_type=float32 /*160*/, i intrinsic store_output (ssa_92, ssa_0) (base=14, wrmask=xyzw /*15*/, component=0, src_type=float32 /*160*/, i intrinsic store_output (ssa_93, ssa_0) (base=8, wrmask=xyzw /*15*/, component=0, src_type=int32 /*34*/, io lo intrinsic store_output (ssa_93, ssa_0) (base=8, wrmask=xyzw /*15*/, component=0, src_type=int32 /*34*/, io lo intrinsic store_output (r13, ssa_0) (base=0, wrmask=x /*1*/, component=0, src_type=float32 /*160*/, io locati intrinsic store_output (r13, ssa_0) (base=0, wrmask=x /*1*/, component=0, src_type=float32 /*160*/, io locati /* succs: block_4 */ /* succs: block_4 */ block block_4: block block_4: } } Native code for unnamed fragment shader (null) (sha1 413f62e4b54e775745e7950e88647d18e40b3b73) Native code for unnamed fragment shader (null) (sha1 413f62e4b54e775745e7950e88647d18e40b3b73) SIMD8 shader: 78 instructions. 0 loops. 1102 cycles. 0:0 spills:fills, 3 sends, scheduled with mode top-down. Promote SIMD8 shader: 78 instructions. 0 loops. 1102 cycles. 0:0 spills:fills, 3 sends, scheduled with mode top-down. Promote START B0 (86 cycles) START B0 (86 cycles) add(16) g9<1>UW g1.4<2,8,0>UW 0x01000100V { align1 WE_all 1H }; add(16) g9<1>UW g1.4<2,8,0>UW 0x01000100V { align1 WE_all 1H }; add(16) g10<1>UW g1.5<2,8,0>UW 0x01010000V { align1 WE_all 1H }; add(16) g10<1>UW g1.5<2,8,0>UW 0x01010000V { align1 WE_all 1H }; mov(8) g12<1>D g4<16,8,2>B { align1 1Q }; mov(8) g12<1>D g4<16,8,2>B { align1 1Q }; mov(8) g14<1>D g4.1<16,8,2>B { align1 1Q }; mov(8) g14<1>D g4.1<16,8,2>B { align1 1Q }; shr(8) g17<1>UW g1<1,8,0>UB 0x44440000V { align1 1Q }; shr(8) g17<1>UW g1<1,8,0>UB 0x44440000V { align1 1Q }; mov(8) g20<1>F g5<0,1,0>UD { align1 1Q compacted }; mov(8) g20<1>F g5<0,1,0>UD { align1 1Q compacted }; mov(8) g21<1>F g5.1<0,1,0>UD { align1 1Q compacted }; mov(8) g21<1>F g5.1<0,1,0>UD { align1 1Q compacted }; mov(8) g24<1>F g5.2<0,1,0>UD { align1 1Q compacted }; mov(8) g24<1>F g5.2<0,1,0>UD { align1 1Q compacted }; mov(8) g25<1>F g5.3<0,1,0>UD { align1 1Q compacted }; mov(8) g25<1>F g5.3<0,1,0>UD { align1 1Q compacted }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@5 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@5 }; mov(8) g2<1>F g9<16,8,2>UW { align1 1Q }; mov(8) g2<1>F g9<16,8,2>UW { align1 1Q }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@4 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@4 }; mov(8) g3<1>F g10<16,8,2>UW { align1 1Q }; mov(8) g3<1>F g10<16,8,2>UW { align1 1Q }; mov(8) g13<1>F g12<1,1,0>D { align1 1Q I@3 compacted }; mov(8) g13<1>F g12<1,1,0>D { align1 1Q I@3 compacted }; mov(8) g15<1>F g14<1,1,0>D { align1 1Q I@2 compacted }; mov(8) g15<1>F g14<1,1,0>D { align1 1Q I@2 compacted }; and(8) g16<1>UD g17<8,8,1>UW 15W { align1 1Q I@1 }; and(8) g16<1>UD g17<8,8,1>UW 15W { align1 1Q I@1 }; math inv(8) g26<1>F g24<8,8,1>F null<8,8,1>F { align1 1Q @6 $0 }; math inv(8) g26<1>F g24<8,8,1>F null<8,8,1>F { align1 1Q @6 $0 }; math inv(8) g28<1>F g25<8,8,1>F null<8,8,1>F { align1 1Q @5 $1 }; math inv(8) g28<1>F g25<8,8,1>F null<8,8,1>F { align1 1Q @5 $1 }; mul(8) g46<1>F g13<1,1,0>F 0x3d800000F /* 0.0625F */ { align1 1Q F@2 compacted }; mul(8) g46<1>F g13<1,1,0>F 0x3d800000F /* 0.0625F */ { align1 1Q F@2 compacted }; mul(8) g11<1>F g15<1,1,0>F 0x3d800000F /* 0.0625F */ { align1 1Q F@2 compacted }; mul(8) g11<1>F g15<1,1,0>F 0x3d800000F /* 0.0625F */ { align1 1Q F@2 compacted }; and.z.f0.0(8) null<1>UD g16<8,8,1>UD 0x00000001UD { align1 1Q I@1 }; and.z.f0.0(8) null<1>UD g16<8,8,1>UD 0x00000001UD { align1 1Q I@1 }; add(8) g18<1>F g2<1,1,0>F g46<1,1,0>F { align1 1Q F@2 compacted }; add(8) g18<1>F g2<1,1,0>F g46<1,1,0>F { align1 1Q F@2 compacted }; add(8) g19<1>F g3<1,1,0>F g11<1,1,0>F { align1 1Q F@2 compacted }; add(8) g19<1>F g3<1,1,0>F g11<1,1,0>F { align1 1Q F@2 compacted }; add(8) g22<1>F g18<1,1,0>F -g20<1,1,0>F { align1 1Q F@2 compacted }; add(8) g22<1>F g18<1,1,0>F -g20<1,1,0>F { align1 1Q F@2 compacted }; add(8) g23<1>F g19<1,1,0>F -g21<1,1,0>F { align1 1Q F@2 compacted }; add(8) g23<1>F g19<1,1,0>F -g21<1,1,0>F { align1 1Q F@2 compacted }; mul(8) g27<1>F g22<1,1,0>F g26<1,1,0>F { align1 1Q @2 $0.dst compacted }; mul(8) g27<1>F g22<1,1,0>F g26<1,1,0>F { align1 1Q @2 $0.dst compacted }; mul(8) g29<1>F g23<1,1,0>F g28<1,1,0>F { align1 1Q @2 $1.dst compacted }; mul(8) g29<1>F g23<1,1,0>F g28<1,1,0>F { align1 1Q @2 $1.dst compacted }; (+f0.0) if(8) JIP: LABEL1 UIP: LABEL0 { align1 1Q }; (+f0.0) if(8) JIP: LABEL1 UIP: LABEL0 { align1 1Q }; END B0 ->B1 ->B2 END B0 ->B1 ->B2 START B1 <-B0 (56 cycles) START B1 <-B0 (56 cycles) mul(8) g51<1>F g5.4<0,1,0>F g27<1,1,0>F { align1 1Q F@2 compacted }; mul(8) g51<1>F g5.4<0,1,0>F g27<1,1,0>F { align1 1Q F@2 compacted }; mul(8) g52<1>F g5.5<0,1,0>F g27<1,1,0>F { align1 1Q compacted }; mul(8) g52<1>F g5.5<0,1,0>F g27<1,1,0>F { align1 1Q compacted }; mul(8) g53<1>F g5.6<0,1,0>F g27<1,1,0>F { align1 1Q compacted }; mul(8) g53<1>F g5.6<0,1,0>F g27<1,1,0>F { align1 1Q compacted }; mul(8) g54<1>F g5.7<0,1,0>F g27<1,1,0>F { align1 1Q compacted }; mul(8) g54<1>F g5.7<0,1,0>F g27<1,1,0>F { align1 1Q compacted }; mul(8) g123<1>F g6.4<0,1,0>F g27<1,1,0>F { align1 1Q compacted }; mul(8) g123<1>F g6.4<0,1,0>F g27<1,1,0>F { align1 1Q compacted }; mul(8) g124<1>F g6.5<0,1,0>F g27<1,1,0>F { align1 1Q compacted }; mul(8) g124<1>F g6.5<0,1,0>F g27<1,1,0>F { align1 1Q compacted }; mul(8) g125<1>F g6.6<0,1,0>F g27<1,1,0>F { align1 1Q compacted }; mul(8) g125<1>F g6.6<0,1,0>F g27<1,1,0>F { align1 1Q compacted }; mul(8) g126<1>F g6.7<0,1,0>F g27<1,1,0>F { align1 1Q compacted }; mul(8) g126<1>F g6.7<0,1,0>F g27<1,1,0>F { align1 1Q compacted }; mov(8) g30<1>F g7.4<0,1,0>D { align1 1Q compacted }; mov(8) g30<1>F g7.4<0,1,0>D { align1 1Q compacted }; mov(8) g31<1>F g7.5<0,1,0>D { align1 1Q compacted }; mov(8) g31<1>F g7.5<0,1,0>D { align1 1Q compacted }; mov(8) g32<1>F g7.6<0,1,0>D { align1 1Q compacted }; mov(8) g32<1>F g7.6<0,1,0>D { align1 1Q compacted }; mov(8) g33<1>F g7.7<0,1,0>D { align1 1Q compacted }; mov(8) g33<1>F g7.7<0,1,0>D { align1 1Q compacted }; mov(8) g122<1>UD g8.4<0,1,0>UD { align1 1Q }; mov(8) g122<1>UD g8.4<0,1,0>UD { align1 1Q }; mul(8) g34<1>F g30<1,1,0>F g27<1,1,0>F { align1 1Q F@4 compacted }; mul(8) g34<1>F g30<1,1,0>F g27<1,1,0>F { align1 1Q F@4 compacted }; mul(8) g35<1>F g31<1,1,0>F g27<1,1,0>F { align1 1Q F@4 compacted }; mul(8) g35<1>F g31<1,1,0>F g27<1,1,0>F { align1 1Q F@4 compacted }; mul(8) g36<1>F g32<1,1,0>F g27<1,1,0>F { align1 1Q F@4 compacted }; mul(8) g36<1>F g32<1,1,0>F g27<1,1,0>F { align1 1Q F@4 compacted }; mul(8) g37<1>F g33<1,1,0>F g27<1,1,0>F { align1 1Q F@4 compacted }; mul(8) g37<1>F g33<1,1,0>F g27<1,1,0>F { align1 1Q F@4 compacted }; mov(8) g47<1>D g34<1,1,0>F { align1 1Q F@4 compacted }; mov(8) g47<1>D g34<1,1,0>F { align1 1Q F@4 compacted }; mov(8) g48<1>D g35<1,1,0>F { align1 1Q F@3 compacted }; mov(8) g48<1>D g35<1,1,0>F { align1 1Q F@3 compacted }; mov(8) g49<1>D g36<1,1,0>F { align1 1Q F@2 compacted }; mov(8) g49<1>D g36<1,1,0>F { align1 1Q F@2 compacted }; mov(8) g50<1>D g37<1,1,0>F { align1 1Q F@1 compacted }; mov(8) g50<1>D g37<1,1,0>F { align1 1Q F@1 compacted }; else(8) JIP: LABEL0 UIP: LABEL0 { align1 1Q }; else(8) JIP: LABEL0 UIP: LABEL0 { align1 1Q }; END B1 ->B2 ->B3 END B1 ->B2 ->B3 START B2 <-B0 <-B1 (48 cycles) START B2 <-B0 <-B1 (48 cycles) LABEL1: LABEL1: mul(8) g51<1>F g6<0,1,0>F g29<1,1,0>F { align1 1Q F@1 compacted }; mul(8) g51<1>F g6<0,1,0>F g29<1,1,0>F { align1 1Q F@1 compacted }; mul(8) g52<1>F g6.1<0,1,0>F g29<1,1,0>F { align1 1Q compacted }; mul(8) g52<1>F g6.1<0,1,0>F g29<1,1,0>F { align1 1Q compacted }; mul(8) g53<1>F g6.2<0,1,0>F g29<1,1,0>F { align1 1Q compacted }; mul(8) g53<1>F g6.2<0,1,0>F g29<1,1,0>F { align1 1Q compacted }; mul(8) g54<1>F g6.3<0,1,0>F g29<1,1,0>F { align1 1Q compacted }; mul(8) g54<1>F g6.3<0,1,0>F g29<1,1,0>F { align1 1Q compacted }; mul(8) g123<1>F g7<0,1,0>F g29<1,1,0>F { align1 1Q compacted }; mul(8) g123<1>F g7<0,1,0>F g29<1,1,0>F { align1 1Q compacted }; mul(8) g124<1>F g7.1<0,1,0>F g29<1,1,0>F { align1 1Q compacted }; mul(8) g124<1>F g7.1<0,1,0>F g29<1,1,0>F { align1 1Q compacted }; mul(8) g125<1>F g7.2<0,1,0>F g29<1,1,0>F { align1 1Q compacted }; mul(8) g125<1>F g7.2<0,1,0>F g29<1,1,0>F { align1 1Q compacted }; mul(8) g126<1>F g7.3<0,1,0>F g29<1,1,0>F { align1 1Q compacted }; mul(8) g126<1>F g7.3<0,1,0>F g29<1,1,0>F { align1 1Q compacted }; mov(8) g38<1>F g8<0,1,0>D { align1 1Q compacted }; mov(8) g38<1>F g8<0,1,0>D { align1 1Q compacted }; mov(8) g39<1>F g8.1<0,1,0>D { align1 1Q compacted }; mov(8) g39<1>F g8.1<0,1,0>D { align1 1Q compacted }; mov(8) g40<1>F g8.2<0,1,0>D { align1 1Q compacted }; mov(8) g40<1>F g8.2<0,1,0>D { align1 1Q compacted }; mov(8) g41<1>F g8.3<0,1,0>D { align1 1Q compacted }; mov(8) g41<1>F g8.3<0,1,0>D { align1 1Q compacted }; mov(8) g122<1>UD g8.5<0,1,0>UD { align1 1Q I@6 }; mov(8) g122<1>UD g8.5<0,1,0>UD { align1 1Q I@6 }; mul(8) g42<1>F g38<1,1,0>F g29<1,1,0>F { align1 1Q F@4 compacted }; mul(8) g42<1>F g38<1,1,0>F g29<1,1,0>F { align1 1Q F@4 compacted }; mul(8) g43<1>F g39<1,1,0>F g29<1,1,0>F { align1 1Q F@4 compacted }; mul(8) g43<1>F g39<1,1,0>F g29<1,1,0>F { align1 1Q F@4 compacted }; mul(8) g44<1>F g40<1,1,0>F g29<1,1,0>F { align1 1Q F@4 compacted }; mul(8) g44<1>F g40<1,1,0>F g29<1,1,0>F { align1 1Q F@4 compacted }; mul(8) g45<1>F g41<1,1,0>F g29<1,1,0>F { align1 1Q F@4 compacted }; mul(8) g45<1>F g41<1,1,0>F g29<1,1,0>F { align1 1Q F@4 compacted }; mov(8) g47<1>D g42<1,1,0>F { align1 1Q A@4 compacted }; mov(8) g47<1>D g42<1,1,0>F { align1 1Q A@4 compacted }; mov(8) g48<1>D g43<1,1,0>F { align1 1Q A@3 compacted }; mov(8) g48<1>D g43<1,1,0>F { align1 1Q A@3 compacted }; mov(8) g49<1>D g44<1,1,0>F { align1 1Q A@2 compacted }; mov(8) g49<1>D g44<1,1,0>F { align1 1Q A@2 compacted }; mov(8) g50<1>D g45<1,1,0>F { align1 1Q A@1 compacted }; mov(8) g50<1>D g45<1,1,0>F { align1 1Q A@1 compacted }; END B2 ->B3 END B2 ->B3 START B3 <-B2 <-B1 (912 cycles) START B3 <-B2 <-B1 (912 cycles) LABEL0: LABEL0: endif(8) JIP: LABEL2 { align1 1Q }; endif(8) JIP: LABEL2 { align1 1Q }; LABEL2: LABEL2: sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@2 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@2 }; sendc(8) nullUD g47UD g122UD 0x08030400 0x00000040 sendc(8) nullUD g47UD g122UD 0x08030400 0x00000040 render MsgDesc: RT write SIMD8 Surface = 0 mlen 4 ex_mlen 1 rlen 0 { align1 1Q $2 }; render MsgDesc: RT write SIMD8 Surface = 0 mlen 4 ex_mlen 1 rlen 0 { align1 1Q $2 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N $2.src }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N $2.src }; sendc(8) nullUD g51UD g122UD 0x08030401 0x00001040 sendc(8) nullUD g51UD g122UD 0x08030401 0x00001040 render MsgDesc: RT write SIMD8 Surface = 1 mlen 4 ex_mlen 1 rlen 0 { align1 1Q $3 }; render MsgDesc: RT write SIMD8 Surface = 1 mlen 4 ex_mlen 1 rlen 0 { align1 1Q $3 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N $3.src }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N $3.src }; sendc(8) nullUD g123UD g122UD 0x08031403 0x00003040 sendc(8) nullUD g123UD g122UD 0x08031403 0x00003040 render MsgDesc: RT write SIMD8 LastRT Surface = 3 mlen 4 ex_mlen 1 rlen 0 { align1 1Q A@1 render MsgDesc: RT write SIMD8 LastRT Surface = 3 mlen 4 ex_mlen 1 rlen 0 { align1 1Q A@1 END B3 END B3 Native code for unnamed fragment shader (null) (sha1 6bb4d7f22b785e17a514e6d33646fa731041fc8d) Native code for unnamed fragment shader (null) (sha1 6bb4d7f22b785e17a514e6d33646fa731041fc8d) SIMD16 shader: 79 instructions. 0 loops. 2124 cycles. 0:0 spills:fills, 3 sends, scheduled with mode top-down. Promot SIMD16 shader: 79 instructions. 0 loops. 2124 cycles. 0:0 spills:fills, 3 sends, scheduled with mode top-down. Promot START B0 (136 cycles) START B0 (136 cycles) add(32) g23<1>UW g1.4<2,8,0>UW 0x01000100V { align1 WE_all }; add(32) g23<1>UW g1.4<2,8,0>UW 0x01000100V { align1 WE_all }; add(32) g25<1>UW g1.5<2,8,0>UW 0x01010000V { align1 WE_all }; add(32) g25<1>UW g1.5<2,8,0>UW 0x01010000V { align1 WE_all }; mov(16) g27<1>D g6<16,8,2>B { align1 1H }; mov(16) g27<1>D g6<16,8,2>B { align1 1H }; mov(16) g31<1>D g6.1<16,8,2>B { align1 1H }; mov(16) g31<1>D g6.1<16,8,2>B { align1 1H }; shr(16) g37<1>UW g1<1,8,0>UB 0x44440000V { align1 1H }; shr(16) g37<1>UW g1<1,8,0>UB 0x44440000V { align1 1H }; mov(16) g42<1>F g7<0,1,0>UD { align1 1H compacted }; mov(16) g42<1>F g7<0,1,0>UD { align1 1H compacted }; mov(16) g44<1>F g7.1<0,1,0>UD { align1 1H compacted }; mov(16) g44<1>F g7.1<0,1,0>UD { align1 1H compacted }; mov(16) g49<1>F g7.2<0,1,0>UD { align1 1H compacted }; mov(16) g49<1>F g7.2<0,1,0>UD { align1 1H compacted }; mov(16) g51<1>F g7.3<0,1,0>UD { align1 1H compacted }; mov(16) g51<1>F g7.3<0,1,0>UD { align1 1H compacted }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@5 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@5 }; mov(16) g20<1>F g23<16,8,2>UW { align1 1H }; mov(16) g20<1>F g23<16,8,2>UW { align1 1H }; mov(16) g29<1>F g27<1,1,0>D { align1 1H I@3 compacted }; mov(16) g29<1>F g27<1,1,0>D { align1 1H I@3 compacted }; mov(16) g33<1>F g31<1,1,0>D { align1 1H I@2 compacted }; mov(16) g33<1>F g31<1,1,0>D { align1 1H I@2 compacted }; and(16) g35<1>UD g37<8,8,1>UW 15W { align1 1H I@1 }; and(16) g35<1>UD g37<8,8,1>UW 15W { align1 1H I@1 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@5 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@5 }; mov(16) g22<1>F g25<16,8,2>UW { align1 1H }; mov(16) g22<1>F g25<16,8,2>UW { align1 1H }; math inv(16) g53<1>F g49<8,8,1>F null<8,8,1>F { align1 1H @6 $0 }; math inv(16) g53<1>F g49<8,8,1>F null<8,8,1>F { align1 1H @6 $0 }; math inv(16) g57<1>F g51<8,8,1>F null<8,8,1>F { align1 1H @5 $1 }; math inv(16) g57<1>F g51<8,8,1>F null<8,8,1>F { align1 1H @5 $1 }; mul(16) g91<1>F g29<1,1,0>F 0x3d800000F /* 0.0625F */ { align1 1H F@3 compacted }; mul(16) g91<1>F g29<1,1,0>F 0x3d800000F /* 0.0625F */ { align1 1H F@3 compacted }; mul(16) g26<1>F g33<1,1,0>F 0x3d800000F /* 0.0625F */ { align1 1H F@3 compacted }; mul(16) g26<1>F g33<1,1,0>F 0x3d800000F /* 0.0625F */ { align1 1H F@3 compacted }; and.z.f0.0(16) null<1>UD g35<8,8,1>UD 0x00000001UD { align1 1H I@1 }; and.z.f0.0(16) null<1>UD g35<8,8,1>UD 0x00000001UD { align1 1H I@1 }; add(16) g38<1>F g20<1,1,0>F g91<1,1,0>F { align1 1H F@2 compacted }; add(16) g38<1>F g20<1,1,0>F g91<1,1,0>F { align1 1H F@2 compacted }; add(16) g40<1>F g22<1,1,0>F g26<1,1,0>F { align1 1H F@2 compacted }; add(16) g40<1>F g22<1,1,0>F g26<1,1,0>F { align1 1H F@2 compacted }; add(16) g46<1>F g38<1,1,0>F -g42<1,1,0>F { align1 1H F@2 compacted }; add(16) g46<1>F g38<1,1,0>F -g42<1,1,0>F { align1 1H F@2 compacted }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N $0.src }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N $0.src }; add(16) g48<1>F g40<1,1,0>F -g44<1,1,0>F { align1 1H F@2 compacted }; add(16) g48<1>F g40<1,1,0>F -g44<1,1,0>F { align1 1H F@2 compacted }; mul(16) g55<1>F g46<1,1,0>F g53<1,1,0>F { align1 1H @2 $0.dst compacted }; mul(16) g55<1>F g46<1,1,0>F g53<1,1,0>F { align1 1H @2 $0.dst compacted }; mul(16) g59<1>F g48<1,1,0>F g57<1,1,0>F { align1 1H @2 $1.dst compacted }; mul(16) g59<1>F g48<1,1,0>F g57<1,1,0>F { align1 1H @2 $1.dst compacted }; (+f0.0) if(16) JIP: LABEL1 UIP: LABEL0 { align1 1H }; (+f0.0) if(16) JIP: LABEL1 UIP: LABEL0 { align1 1H }; END B0 ->B1 ->B2 END B0 ->B1 ->B2 START B1 <-B0 (92 cycles) START B1 <-B0 (92 cycles) mul(16) g19<1>F g7.4<0,1,0>F g55<1,1,0>F { align1 1H F@2 compacted }; mul(16) g19<1>F g7.4<0,1,0>F g55<1,1,0>F { align1 1H F@2 compacted }; mul(16) g21<1>F g7.5<0,1,0>F g55<1,1,0>F { align1 1H compacted }; mul(16) g21<1>F g7.5<0,1,0>F g55<1,1,0>F { align1 1H compacted }; mul(16) g23<1>F g7.6<0,1,0>F g55<1,1,0>F { align1 1H compacted }; mul(16) g23<1>F g7.6<0,1,0>F g55<1,1,0>F { align1 1H compacted }; mul(16) g25<1>F g7.7<0,1,0>F g55<1,1,0>F { align1 1H compacted }; mul(16) g25<1>F g7.7<0,1,0>F g55<1,1,0>F { align1 1H compacted }; mul(16) g119<1>F g8.4<0,1,0>F g55<1,1,0>F { align1 1H compacted }; mul(16) g119<1>F g8.4<0,1,0>F g55<1,1,0>F { align1 1H compacted }; mul(16) g121<1>F g8.5<0,1,0>F g55<1,1,0>F { align1 1H compacted }; mul(16) g121<1>F g8.5<0,1,0>F g55<1,1,0>F { align1 1H compacted }; mul(16) g123<1>F g8.6<0,1,0>F g55<1,1,0>F { align1 1H compacted }; mul(16) g123<1>F g8.6<0,1,0>F g55<1,1,0>F { align1 1H compacted }; mul(16) g125<1>F g8.7<0,1,0>F g55<1,1,0>F { align1 1H compacted }; mul(16) g125<1>F g8.7<0,1,0>F g55<1,1,0>F { align1 1H compacted }; mov(16) g61<1>F g9.4<0,1,0>D { align1 1H compacted }; mov(16) g61<1>F g9.4<0,1,0>D { align1 1H compacted }; mov(16) g63<1>F g9.5<0,1,0>D { align1 1H compacted }; mov(16) g63<1>F g9.5<0,1,0>D { align1 1H compacted }; mov(16) g65<1>F g9.6<0,1,0>D { align1 1H compacted }; mov(16) g65<1>F g9.6<0,1,0>D { align1 1H compacted }; mov(16) g67<1>F g9.7<0,1,0>D { align1 1H compacted }; mov(16) g67<1>F g9.7<0,1,0>D { align1 1H compacted }; mov(16) g117<1>UD g10.4<0,1,0>UD { align1 1H }; mov(16) g117<1>UD g10.4<0,1,0>UD { align1 1H }; mul(16) g69<1>F g61<1,1,0>F g55<1,1,0>F { align1 1H F@4 compacted }; mul(16) g69<1>F g61<1,1,0>F g55<1,1,0>F { align1 1H F@4 compacted }; mul(16) g71<1>F g63<1,1,0>F g55<1,1,0>F { align1 1H F@4 compacted }; mul(16) g71<1>F g63<1,1,0>F g55<1,1,0>F { align1 1H F@4 compacted }; mul(16) g73<1>F g65<1,1,0>F g55<1,1,0>F { align1 1H F@4 compacted }; mul(16) g73<1>F g65<1,1,0>F g55<1,1,0>F { align1 1H F@4 compacted }; mul(16) g75<1>F g67<1,1,0>F g55<1,1,0>F { align1 1H F@4 compacted }; mul(16) g75<1>F g67<1,1,0>F g55<1,1,0>F { align1 1H F@4 compacted }; mov(16) g11<1>D g69<1,1,0>F { align1 1H F@4 compacted }; mov(16) g11<1>D g69<1,1,0>F { align1 1H F@4 compacted }; mov(16) g13<1>D g71<1,1,0>F { align1 1H F@3 compacted }; mov(16) g13<1>D g71<1,1,0>F { align1 1H F@3 compacted }; mov(16) g15<1>D g73<1,1,0>F { align1 1H F@2 compacted }; mov(16) g15<1>D g73<1,1,0>F { align1 1H F@2 compacted }; mov(16) g17<1>D g75<1,1,0>F { align1 1H F@1 compacted }; mov(16) g17<1>D g75<1,1,0>F { align1 1H F@1 compacted }; else(16) JIP: LABEL0 UIP: LABEL0 { align1 1H }; else(16) JIP: LABEL0 UIP: LABEL0 { align1 1H }; END B1 ->B2 ->B3 END B1 ->B2 ->B3 START B2 <-B0 <-B1 (84 cycles) START B2 <-B0 <-B1 (84 cycles) LABEL1: LABEL1: mul(16) g19<1>F g8<0,1,0>F g59<1,1,0>F { align1 1H F@1 compacted }; mul(16) g19<1>F g8<0,1,0>F g59<1,1,0>F { align1 1H F@1 compacted }; mul(16) g21<1>F g8.1<0,1,0>F g59<1,1,0>F { align1 1H F@6 compacted }; mul(16) g21<1>F g8.1<0,1,0>F g59<1,1,0>F { align1 1H F@6 compacted }; mul(16) g23<1>F g8.2<0,1,0>F g59<1,1,0>F { align1 1H F@7 compacted }; mul(16) g23<1>F g8.2<0,1,0>F g59<1,1,0>F { align1 1H F@7 compacted }; mul(16) g25<1>F g8.3<0,1,0>F g59<1,1,0>F { align1 1H F@7 compacted }; mul(16) g25<1>F g8.3<0,1,0>F g59<1,1,0>F { align1 1H F@7 compacted }; mul(16) g119<1>F g9<0,1,0>F g59<1,1,0>F { align1 1H compacted }; mul(16) g119<1>F g9<0,1,0>F g59<1,1,0>F { align1 1H compacted }; mul(16) g121<1>F g9.1<0,1,0>F g59<1,1,0>F { align1 1H compacted }; mul(16) g121<1>F g9.1<0,1,0>F g59<1,1,0>F { align1 1H compacted }; mul(16) g123<1>F g9.2<0,1,0>F g59<1,1,0>F { align1 1H compacted }; mul(16) g123<1>F g9.2<0,1,0>F g59<1,1,0>F { align1 1H compacted }; mul(16) g125<1>F g9.3<0,1,0>F g59<1,1,0>F { align1 1H compacted }; mul(16) g125<1>F g9.3<0,1,0>F g59<1,1,0>F { align1 1H compacted }; mov(16) g76<1>F g10<0,1,0>D { align1 1H I@2 compacted }; mov(16) g76<1>F g10<0,1,0>D { align1 1H I@2 compacted }; mov(16) g78<1>F g10.1<0,1,0>D { align1 1H compacted }; mov(16) g78<1>F g10.1<0,1,0>D { align1 1H compacted }; mov(16) g80<1>F g10.2<0,1,0>D { align1 1H compacted }; mov(16) g80<1>F g10.2<0,1,0>D { align1 1H compacted }; mov(16) g82<1>F g10.3<0,1,0>D { align1 1H compacted }; mov(16) g82<1>F g10.3<0,1,0>D { align1 1H compacted }; mov(16) g117<1>UD g10.5<0,1,0>UD { align1 1H I@6 }; mov(16) g117<1>UD g10.5<0,1,0>UD { align1 1H I@6 }; mul(16) g84<1>F g76<1,1,0>F g59<1,1,0>F { align1 1H F@4 compacted }; mul(16) g84<1>F g76<1,1,0>F g59<1,1,0>F { align1 1H F@4 compacted }; mul(16) g86<1>F g78<1,1,0>F g59<1,1,0>F { align1 1H F@4 compacted }; mul(16) g86<1>F g78<1,1,0>F g59<1,1,0>F { align1 1H F@4 compacted }; mul(16) g88<1>F g80<1,1,0>F g59<1,1,0>F { align1 1H F@4 compacted }; mul(16) g88<1>F g80<1,1,0>F g59<1,1,0>F { align1 1H F@4 compacted }; mul(16) g90<1>F g82<1,1,0>F g59<1,1,0>F { align1 1H F@4 compacted }; mul(16) g90<1>F g82<1,1,0>F g59<1,1,0>F { align1 1H F@4 compacted }; mov(16) g11<1>D g84<1,1,0>F { align1 1H A@4 compacted }; mov(16) g11<1>D g84<1,1,0>F { align1 1H A@4 compacted }; mov(16) g13<1>D g86<1,1,0>F { align1 1H A@3 compacted }; mov(16) g13<1>D g86<1,1,0>F { align1 1H A@3 compacted }; mov(16) g15<1>D g88<1,1,0>F { align1 1H A@2 compacted }; mov(16) g15<1>D g88<1,1,0>F { align1 1H A@2 compacted }; mov(16) g17<1>D g90<1,1,0>F { align1 1H A@1 compacted }; mov(16) g17<1>D g90<1,1,0>F { align1 1H A@1 compacted }; END B2 ->B3 END B2 ->B3 START B3 <-B2 <-B1 (1812 cycles) START B3 <-B2 <-B1 (1812 cycles) LABEL0: LABEL0: endif(16) JIP: LABEL2 { align1 1H }; endif(16) JIP: LABEL2 { align1 1H }; LABEL2: LABEL2: sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@2 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@2 }; sendc(16) nullUD g11UD g117UD 0x10030000 0x00000080 sendc(16) nullUD g11UD g117UD 0x10030000 0x00000080 render MsgDesc: RT write SIMD16 Surface = 0 mlen 8 ex_mlen 2 rlen 0 { align1 1H $2 }; render MsgDesc: RT write SIMD16 Surface = 0 mlen 8 ex_mlen 2 rlen 0 { align1 1H $2 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N $2.src }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N $2.src }; sendc(16) nullUD g19UD g117UD 0x10030001 0x00001080 sendc(16) nullUD g19UD g117UD 0x10030001 0x00001080 render MsgDesc: RT write SIMD16 Surface = 1 mlen 8 ex_mlen 2 rlen 0 { align1 1H $3 }; render MsgDesc: RT write SIMD16 Surface = 1 mlen 8 ex_mlen 2 rlen 0 { align1 1H $3 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N $3.src }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N $3.src }; sendc(16) nullUD g119UD g117UD 0x10031003 0x00003080 sendc(16) nullUD g119UD g117UD 0x10031003 0x00003080 render MsgDesc: RT write SIMD16 LastRT Surface = 3 mlen 8 ex_mlen 2 rlen 0 { align1 1H A@ render MsgDesc: RT write SIMD16 LastRT Surface = 3 mlen 8 ex_mlen 2 rlen 0 { align1 1H A@ END B3 END B3 Native code for unnamed fragment shader (null) (sha1 234c75213bd5b652686d03f12ab2706794fa4a04) Native code for unnamed fragment shader (null) (sha1 234c75213bd5b652686d03f12ab2706794fa4a04) SIMD32 shader: 164 instructions. 0 loops. 5120 cycles. 0:0 spills:fills, 6 sends, scheduled with mode top-down. Promo SIMD32 shader: 164 instructions. 0 loops. 5120 cycles. 0:0 spills:fills, 6 sends, scheduled with mode top-down. Promo START B0 (246 cycles) START B0 (246 cycles) add(32) g53<1>UW g1.4<2,8,0>UW 0x01000100V { align1 WE_all }; add(32) g53<1>UW g1.4<2,8,0>UW 0x01000100V { align1 WE_all }; add(32) g55<1>UW g1.5<2,8,0>UW 0x01010000V { align1 WE_all }; add(32) g55<1>UW g1.5<2,8,0>UW 0x01010000V { align1 WE_all }; add(32) g57<1>UW g2.4<2,8,0>UW 0x01000100V { align1 WE_all }; add(32) g57<1>UW g2.4<2,8,0>UW 0x01000100V { align1 WE_all }; add(32) g59<1>UW g2.5<2,8,0>UW 0x01010000V { align1 WE_all }; add(32) g59<1>UW g2.5<2,8,0>UW 0x01010000V { align1 WE_all }; mov(16) g82<1>W g7<8,8,1>W { align1 WE_all 1H }; mov(16) g82<1>W g7<8,8,1>W { align1 WE_all 1H }; mov(16) g61<1>W g12<8,8,1>W { align1 WE_all 1H }; mov(16) g61<1>W g12<8,8,1>W { align1 WE_all 1H }; shr(16) g102<1>UW g1<1,8,0>UB 0x44440000V { align1 1H }; shr(16) g102<1>UW g1<1,8,0>UB 0x44440000V { align1 1H }; shr(16) g72<1>UW g2<1,8,0>UB 0x44440000V { align1 2H }; shr(16) g72<1>UW g2<1,8,0>UB 0x44440000V { align1 2H }; mov(16) g103<1>F g13<0,1,0>UD { align1 1H compacted }; mov(16) g103<1>F g13<0,1,0>UD { align1 1H compacted }; mov(16) g77<1>F g13<0,1,0>UD { align1 2H compacted }; mov(16) g77<1>F g13<0,1,0>UD { align1 2H compacted }; mov(16) g105<1>F g13.1<0,1,0>UD { align1 1H compacted }; mov(16) g105<1>F g13.1<0,1,0>UD { align1 1H compacted }; mov(16) g79<1>F g13.1<0,1,0>UD { align1 2H compacted }; mov(16) g79<1>F g13.1<0,1,0>UD { align1 2H compacted }; mov(16) g110<1>F g13.2<0,1,0>UD { align1 1H compacted }; mov(16) g110<1>F g13.2<0,1,0>UD { align1 1H compacted }; mov(16) g84<1>F g13.2<0,1,0>UD { align1 2H compacted }; mov(16) g84<1>F g13.2<0,1,0>UD { align1 2H compacted }; mov(16) g112<1>F g13.3<0,1,0>UD { align1 1H compacted }; mov(16) g112<1>F g13.3<0,1,0>UD { align1 1H compacted }; mov(16) g86<1>F g13.3<0,1,0>UD { align1 2H compacted }; mov(16) g86<1>F g13.3<0,1,0>UD { align1 2H compacted }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@7 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@7 }; mov(16) g73<1>F g53<16,8,2>UW { align1 1H }; mov(16) g73<1>F g53<16,8,2>UW { align1 1H }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@7 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@7 }; mov(16) g75<1>F g55<16,8,2>UW { align1 1H }; mov(16) g75<1>F g55<16,8,2>UW { align1 1H }; sync nop(1) null<0,1,0>UB { align1 WE_all 5N I@6 }; sync nop(1) null<0,1,0>UB { align1 WE_all 5N I@6 }; mov(16) g50<1>F g57<16,8,2>UW { align1 2H }; mov(16) g50<1>F g57<16,8,2>UW { align1 2H }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@4 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@4 }; mov(16) g90<1>D g82<16,8,2>B { align1 1H }; mov(16) g90<1>D g82<16,8,2>B { align1 1H }; mov(16) g96<1>D g82.1<16,8,2>B { align1 1H }; mov(16) g96<1>D g82.1<16,8,2>B { align1 1H }; sync nop(1) null<0,1,0>UB { align1 WE_all 5N I@5 }; sync nop(1) null<0,1,0>UB { align1 WE_all 5N I@5 }; mov(16) g62<1>D g61<16,8,2>B { align1 2H }; mov(16) g62<1>D g61<16,8,2>B { align1 2H }; mov(16) g66<1>D g61.1<16,8,2>B { align1 2H }; mov(16) g66<1>D g61.1<16,8,2>B { align1 2H }; and(16) g100<1>UD g102<8,8,1>UW 15W { align1 1H I@6 }; and(16) g100<1>UD g102<8,8,1>UW 15W { align1 1H I@6 }; and(16) g70<1>UD g72<8,8,1>UW 15W { align1 2H I@6 }; and(16) g70<1>UD g72<8,8,1>UW 15W { align1 2H I@6 }; math inv(16) g114<1>F g110<8,8,1>F null<8,8,1>F { align1 1H @7 $0 }; math inv(16) g114<1>F g110<8,8,1>F null<8,8,1>F { align1 1H @7 $0 }; mov(16) g52<1>F g59<16,8,2>UW { align1 2H }; mov(16) g52<1>F g59<16,8,2>UW { align1 2H }; math inv(16) g88<1>F g84<8,8,1>F null<8,8,1>F { align1 2H @7 $1 }; math inv(16) g88<1>F g84<8,8,1>F null<8,8,1>F { align1 2H @7 $1 }; math inv(16) g4<1>F g112<8,8,1>F null<8,8,1>F { align1 1H @6 $2 }; math inv(16) g4<1>F g112<8,8,1>F null<8,8,1>F { align1 1H @6 $2 }; math inv(16) g92<1>F g86<8,8,1>F null<8,8,1>F { align1 2H @5 $3 }; math inv(16) g92<1>F g86<8,8,1>F null<8,8,1>F { align1 2H @5 $3 }; mov(16) g94<1>F g90<1,1,0>D { align1 1H I@6 compacted }; mov(16) g94<1>F g90<1,1,0>D { align1 1H I@6 compacted }; mov(16) g98<1>F g96<1,1,0>D { align1 1H I@5 compacted }; mov(16) g98<1>F g96<1,1,0>D { align1 1H I@5 compacted }; mov(16) g64<1>F g62<1,1,0>D { align1 2H I@4 compacted }; mov(16) g64<1>F g62<1,1,0>D { align1 2H I@4 compacted }; mov(16) g68<1>F g66<1,1,0>D { align1 2H I@3 compacted }; mov(16) g68<1>F g66<1,1,0>D { align1 2H I@3 compacted }; and.z.f0.0(16) null<1>UD g100<8,8,1>UD 0x00000001UD { align1 1H I@2 }; and.z.f0.0(16) null<1>UD g100<8,8,1>UD 0x00000001UD { align1 1H I@2 }; and.z.f0.0(16) null<1>UD g70<8,8,1>UD 0x00000001UD { align1 2H I@2 }; and.z.f0.0(16) null<1>UD g70<8,8,1>UD 0x00000001UD { align1 2H I@2 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N $1.src }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N $1.src }; mul(16) g83<1>F g94<1,1,0>F 0x3d800000F /* 0.0625F */ { align1 1H F@4 compacted }; mul(16) g83<1>F g94<1,1,0>F 0x3d800000F /* 0.0625F */ { align1 1H F@4 compacted }; mul(16) g81<1>F g98<1,1,0>F 0x3d800000F /* 0.0625F */ { align1 1H A@4 compacted }; mul(16) g81<1>F g98<1,1,0>F 0x3d800000F /* 0.0625F */ { align1 1H A@4 compacted }; mul(16) g54<1>F g64<1,1,0>F 0x3d800000F /* 0.0625F */ { align1 2H F@4 compacted }; mul(16) g54<1>F g64<1,1,0>F 0x3d800000F /* 0.0625F */ { align1 2H F@4 compacted }; mul(16) g60<1>F g68<1,1,0>F 0x3d800000F /* 0.0625F */ { align1 2H A@4 compacted }; mul(16) g60<1>F g68<1,1,0>F 0x3d800000F /* 0.0625F */ { align1 2H A@4 compacted }; add(16) g56<1>F g73<1,1,0>F g83<1,1,0>F { align1 1H F@4 compacted }; add(16) g56<1>F g73<1,1,0>F g83<1,1,0>F { align1 1H F@4 compacted }; add(16) g58<1>F g75<1,1,0>F g81<1,1,0>F { align1 1H F@4 compacted }; add(16) g58<1>F g75<1,1,0>F g81<1,1,0>F { align1 1H F@4 compacted }; add(16) g73<1>F g50<1,1,0>F g54<1,1,0>F { align1 2H F@4 compacted }; add(16) g73<1>F g50<1,1,0>F g54<1,1,0>F { align1 2H F@4 compacted }; add(16) g75<1>F g52<1,1,0>F g60<1,1,0>F { align1 2H F@4 compacted }; add(16) g75<1>F g52<1,1,0>F g60<1,1,0>F { align1 2H F@4 compacted }; add(16) g107<1>F g56<1,1,0>F -g103<1,1,0>F { align1 1H F@4 compacted }; add(16) g107<1>F g56<1,1,0>F -g103<1,1,0>F { align1 1H F@4 compacted }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N $0.src }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N $0.src }; add(16) g109<1>F g58<1,1,0>F -g105<1,1,0>F { align1 1H F@4 compacted }; add(16) g109<1>F g58<1,1,0>F -g105<1,1,0>F { align1 1H F@4 compacted }; add(16) g81<1>F g73<1,1,0>F -g77<1,1,0>F { align1 2H F@4 compacted }; add(16) g81<1>F g73<1,1,0>F -g77<1,1,0>F { align1 2H F@4 compacted }; add(16) g83<1>F g75<1,1,0>F -g79<1,1,0>F { align1 2H F@4 compacted }; add(16) g83<1>F g75<1,1,0>F -g79<1,1,0>F { align1 2H F@4 compacted }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N $0.dst }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N $0.dst }; mul(16) g2<1>F g107<1,1,0>F g114<1,1,0>F { align1 1H A@4 compacted }; mul(16) g2<1>F g107<1,1,0>F g114<1,1,0>F { align1 1H A@4 compacted }; mul(16) g49<1>F g109<1,1,0>F g4<1,1,0>F { align1 1H @4 $2.dst compacted }; mul(16) g49<1>F g109<1,1,0>F g4<1,1,0>F { align1 1H @4 $2.dst compacted }; mul(16) g90<1>F g81<1,1,0>F g88<1,1,0>F { align1 2H @4 $1.dst compacted }; mul(16) g90<1>F g81<1,1,0>F g88<1,1,0>F { align1 2H @4 $1.dst compacted }; mul(16) g94<1>F g83<1,1,0>F g92<1,1,0>F { align1 2H @4 $3.dst compacted }; mul(16) g94<1>F g83<1,1,0>F g92<1,1,0>F { align1 2H @4 $3.dst compacted }; (+f0.0) if(32) JIP: LABEL1 UIP: LABEL0 { align1 }; (+f0.0) if(32) JIP: LABEL1 UIP: LABEL0 { align1 }; END B0 ->B1 ->B2 END B0 ->B1 ->B2 START B1 <-B0 (180 cycles) START B1 <-B0 (180 cycles) mul(16) g25<1>F g13.4<0,1,0>F g2<1,1,0>F { align1 1H F@4 compacted }; mul(16) g25<1>F g13.4<0,1,0>F g2<1,1,0>F { align1 1H F@4 compacted }; mul(16) g33<1>F g13.4<0,1,0>F g90<1,1,0>F { align1 2H F@3 compacted }; mul(16) g33<1>F g13.4<0,1,0>F g90<1,1,0>F { align1 2H F@3 compacted }; mul(16) g27<1>F g13.5<0,1,0>F g2<1,1,0>F { align1 1H compacted }; mul(16) g27<1>F g13.5<0,1,0>F g2<1,1,0>F { align1 1H compacted }; mul(16) g35<1>F g13.5<0,1,0>F g90<1,1,0>F { align1 2H compacted }; mul(16) g35<1>F g13.5<0,1,0>F g90<1,1,0>F { align1 2H compacted }; mul(16) g29<1>F g13.6<0,1,0>F g2<1,1,0>F { align1 1H compacted }; mul(16) g29<1>F g13.6<0,1,0>F g2<1,1,0>F { align1 1H compacted }; mul(16) g37<1>F g13.6<0,1,0>F g90<1,1,0>F { align1 2H compacted }; mul(16) g37<1>F g13.6<0,1,0>F g90<1,1,0>F { align1 2H compacted }; mul(16) g31<1>F g13.7<0,1,0>F g2<1,1,0>F { align1 1H compacted }; mul(16) g31<1>F g13.7<0,1,0>F g2<1,1,0>F { align1 1H compacted }; mul(16) g39<1>F g13.7<0,1,0>F g90<1,1,0>F { align1 2H compacted }; mul(16) g39<1>F g13.7<0,1,0>F g90<1,1,0>F { align1 2H compacted }; mul(16) g41<1>F g14.4<0,1,0>F g2<1,1,0>F { align1 1H compacted }; mul(16) g41<1>F g14.4<0,1,0>F g2<1,1,0>F { align1 1H compacted }; mul(16) g119<1>F g14.4<0,1,0>F g90<1,1,0>F { align1 2H compacted }; mul(16) g119<1>F g14.4<0,1,0>F g90<1,1,0>F { align1 2H compacted }; mul(16) g43<1>F g14.5<0,1,0>F g2<1,1,0>F { align1 1H compacted }; mul(16) g43<1>F g14.5<0,1,0>F g2<1,1,0>F { align1 1H compacted }; mul(16) g121<1>F g14.5<0,1,0>F g90<1,1,0>F { align1 2H compacted }; mul(16) g121<1>F g14.5<0,1,0>F g90<1,1,0>F { align1 2H compacted }; mul(16) g45<1>F g14.6<0,1,0>F g2<1,1,0>F { align1 1H compacted }; mul(16) g45<1>F g14.6<0,1,0>F g2<1,1,0>F { align1 1H compacted }; mul(16) g123<1>F g14.6<0,1,0>F g90<1,1,0>F { align1 2H compacted }; mul(16) g123<1>F g14.6<0,1,0>F g90<1,1,0>F { align1 2H compacted }; mul(16) g47<1>F g14.7<0,1,0>F g2<1,1,0>F { align1 1H compacted }; mul(16) g47<1>F g14.7<0,1,0>F g2<1,1,0>F { align1 1H compacted }; mul(16) g125<1>F g14.7<0,1,0>F g90<1,1,0>F { align1 2H compacted }; mul(16) g125<1>F g14.7<0,1,0>F g90<1,1,0>F { align1 2H compacted }; mov(16) g5<1>F g15.4<0,1,0>D { align1 1H compacted }; mov(16) g5<1>F g15.4<0,1,0>D { align1 1H compacted }; mov(16) g96<1>F g15.4<0,1,0>D { align1 2H compacted }; mov(16) g96<1>F g15.4<0,1,0>D { align1 2H compacted }; mov(16) g7<1>F g15.5<0,1,0>D { align1 1H compacted }; mov(16) g7<1>F g15.5<0,1,0>D { align1 1H compacted }; mov(16) g98<1>F g15.5<0,1,0>D { align1 2H compacted }; mov(16) g98<1>F g15.5<0,1,0>D { align1 2H compacted }; mov(16) g9<1>F g15.6<0,1,0>D { align1 1H compacted }; mov(16) g9<1>F g15.6<0,1,0>D { align1 1H compacted }; mov(16) g100<1>F g15.6<0,1,0>D { align1 2H I@3 compacted }; mov(16) g100<1>F g15.6<0,1,0>D { align1 2H I@3 compacted }; mov(16) g11<1>F g15.7<0,1,0>D { align1 1H compacted }; mov(16) g11<1>F g15.7<0,1,0>D { align1 1H compacted }; mov(16) g102<1>F g15.7<0,1,0>D { align1 2H I@5 compacted }; mov(16) g102<1>F g15.7<0,1,0>D { align1 2H I@5 compacted }; mov(16) g55<1>UD g16.4<0,1,0>UD { align1 1H }; mov(16) g55<1>UD g16.4<0,1,0>UD { align1 1H }; mov(16) g117<1>UD g16.4<0,1,0>UD { align1 2H }; mov(16) g117<1>UD g16.4<0,1,0>UD { align1 2H }; mul(16) g17<1>F g5<1,1,0>F g2<1,1,0>F { align1 1H F@7 compacted }; mul(16) g17<1>F g5<1,1,0>F g2<1,1,0>F { align1 1H F@7 compacted }; mul(16) g104<1>F g96<1,1,0>F g90<1,1,0>F { align1 2H F@7 compacted }; mul(16) g104<1>F g96<1,1,0>F g90<1,1,0>F { align1 2H F@7 compacted }; mul(16) g51<1>F g7<1,1,0>F g2<1,1,0>F { align1 1H F@7 compacted }; mul(16) g51<1>F g7<1,1,0>F g2<1,1,0>F { align1 1H F@7 compacted }; mul(16) g106<1>F g98<1,1,0>F g90<1,1,0>F { align1 2H F@7 compacted }; mul(16) g106<1>F g98<1,1,0>F g90<1,1,0>F { align1 2H F@7 compacted }; mul(16) g53<1>F g9<1,1,0>F g2<1,1,0>F { align1 1H F@7 compacted }; mul(16) g53<1>F g9<1,1,0>F g2<1,1,0>F { align1 1H F@7 compacted }; mul(16) g108<1>F g100<1,1,0>F g90<1,1,0>F { align1 2H F@7 compacted }; mul(16) g108<1>F g100<1,1,0>F g90<1,1,0>F { align1 2H F@7 compacted }; mul(16) g57<1>F g11<1,1,0>F g2<1,1,0>F { align1 1H F@7 compacted }; mul(16) g57<1>F g11<1,1,0>F g2<1,1,0>F { align1 1H F@7 compacted }; sync nop(1) null<0,1,0>UB { align1 WE_all 5N $0.src }; sync nop(1) null<0,1,0>UB { align1 WE_all 5N $0.src }; mul(16) g110<1>F g102<1,1,0>F g90<1,1,0>F { align1 2H F@7 compacted }; mul(16) g110<1>F g102<1,1,0>F g90<1,1,0>F { align1 2H F@7 compacted }; mov(16) g4<1>D g51<1,1,0>F { align1 1H F@6 compacted }; mov(16) g4<1>D g51<1,1,0>F { align1 1H F@6 compacted }; mov(16) g2<1>D g17<1,1,0>F { align1 1H F@2 compacted }; mov(16) g2<1>D g17<1,1,0>F { align1 1H F@2 compacted }; mov(16) g19<1>D g106<1,1,0>F { align1 2H F@5 compacted }; mov(16) g19<1>D g106<1,1,0>F { align1 2H F@5 compacted }; mov(16) g6<1>D g53<1,1,0>F { align1 1H F@4 compacted }; mov(16) g6<1>D g53<1,1,0>F { align1 1H F@4 compacted }; mov(16) g21<1>D g108<1,1,0>F { align1 2H F@3 compacted }; mov(16) g21<1>D g108<1,1,0>F { align1 2H F@3 compacted }; mov(16) g17<1>D g104<1,1,0>F { align1 2H F@7 compacted }; mov(16) g17<1>D g104<1,1,0>F { align1 2H F@7 compacted }; mov(16) g8<1>D g57<1,1,0>F { align1 1H F@2 compacted }; mov(16) g8<1>D g57<1,1,0>F { align1 1H F@2 compacted }; mov(16) g23<1>D g110<1,1,0>F { align1 2H F@1 compacted }; mov(16) g23<1>D g110<1,1,0>F { align1 2H F@1 compacted }; else(32) JIP: LABEL0 UIP: LABEL0 { align1 }; else(32) JIP: LABEL0 UIP: LABEL0 { align1 }; END B1 ->B2 ->B3 END B1 ->B2 ->B3 START B2 <-B0 <-B1 (182 cycles) START B2 <-B0 <-B1 (182 cycles) LABEL1: LABEL1: mul(16) g25<1>F g14<0,1,0>F g49<1,1,0>F { align1 1H F@3 compacted }; mul(16) g25<1>F g14<0,1,0>F g49<1,1,0>F { align1 1H F@3 compacted }; mul(16) g33<1>F g14<0,1,0>F g94<1,1,0>F { align1 2H F@2 compacted }; mul(16) g33<1>F g14<0,1,0>F g94<1,1,0>F { align1 2H F@2 compacted }; mul(16) g27<1>F g14.1<0,1,0>F g49<1,1,0>F { align1 1H compacted }; mul(16) g27<1>F g14.1<0,1,0>F g49<1,1,0>F { align1 1H compacted }; mul(16) g35<1>F g14.1<0,1,0>F g94<1,1,0>F { align1 2H compacted }; mul(16) g35<1>F g14.1<0,1,0>F g94<1,1,0>F { align1 2H compacted }; mul(16) g29<1>F g14.2<0,1,0>F g49<1,1,0>F { align1 1H compacted }; mul(16) g29<1>F g14.2<0,1,0>F g49<1,1,0>F { align1 1H compacted }; mul(16) g37<1>F g14.2<0,1,0>F g94<1,1,0>F { align1 2H compacted }; mul(16) g37<1>F g14.2<0,1,0>F g94<1,1,0>F { align1 2H compacted }; mul(16) g31<1>F g14.3<0,1,0>F g49<1,1,0>F { align1 1H compacted }; mul(16) g31<1>F g14.3<0,1,0>F g49<1,1,0>F { align1 1H compacted }; mul(16) g39<1>F g14.3<0,1,0>F g94<1,1,0>F { align1 2H compacted }; mul(16) g39<1>F g14.3<0,1,0>F g94<1,1,0>F { align1 2H compacted }; mul(16) g41<1>F g15<0,1,0>F g49<1,1,0>F { align1 1H compacted }; mul(16) g41<1>F g15<0,1,0>F g49<1,1,0>F { align1 1H compacted }; mul(16) g119<1>F g15<0,1,0>F g94<1,1,0>F { align1 2H compacted }; mul(16) g119<1>F g15<0,1,0>F g94<1,1,0>F { align1 2H compacted }; mul(16) g43<1>F g15.1<0,1,0>F g49<1,1,0>F { align1 1H compacted }; mul(16) g43<1>F g15.1<0,1,0>F g49<1,1,0>F { align1 1H compacted }; mul(16) g121<1>F g15.1<0,1,0>F g94<1,1,0>F { align1 2H compacted }; mul(16) g121<1>F g15.1<0,1,0>F g94<1,1,0>F { align1 2H compacted }; mul(16) g45<1>F g15.2<0,1,0>F g49<1,1,0>F { align1 1H compacted }; mul(16) g45<1>F g15.2<0,1,0>F g49<1,1,0>F { align1 1H compacted }; mul(16) g123<1>F g15.2<0,1,0>F g94<1,1,0>F { align1 2H compacted }; mul(16) g123<1>F g15.2<0,1,0>F g94<1,1,0>F { align1 2H compacted }; mul(16) g47<1>F g15.3<0,1,0>F g49<1,1,0>F { align1 1H compacted }; mul(16) g47<1>F g15.3<0,1,0>F g49<1,1,0>F { align1 1H compacted }; mul(16) g125<1>F g15.3<0,1,0>F g94<1,1,0>F { align1 2H compacted }; mul(16) g125<1>F g15.3<0,1,0>F g94<1,1,0>F { align1 2H compacted }; mov(16) g58<1>F g16<0,1,0>D { align1 1H I@3 compacted }; mov(16) g58<1>F g16<0,1,0>D { align1 1H I@3 compacted }; sync nop(1) null<0,1,0>UB { align1 WE_all 5N $0.src }; sync nop(1) null<0,1,0>UB { align1 WE_all 5N $0.src }; sync nop(1) null<0,1,0>UB { align1 WE_all 5N $2.src }; sync nop(1) null<0,1,0>UB { align1 WE_all 5N $2.src }; mov(16) g111<1>F g16<0,1,0>D { align1 2H I@2 compacted }; mov(16) g111<1>F g16<0,1,0>D { align1 2H I@2 compacted }; mov(16) g60<1>F g16.1<0,1,0>D { align1 1H compacted }; mov(16) g60<1>F g16.1<0,1,0>D { align1 1H compacted }; mov(16) g113<1>F g16.1<0,1,0>D { align1 2H $2.src compacted }; mov(16) g113<1>F g16.1<0,1,0>D { align1 2H $2.src compacted }; mov(16) g62<1>F g16.2<0,1,0>D { align1 1H compacted }; mov(16) g62<1>F g16.2<0,1,0>D { align1 1H compacted }; mov(16) g115<1>F g16.2<0,1,0>D { align1 2H compacted }; mov(16) g115<1>F g16.2<0,1,0>D { align1 2H compacted }; mov(16) g64<1>F g16.3<0,1,0>D { align1 1H compacted }; mov(16) g64<1>F g16.3<0,1,0>D { align1 1H compacted }; mov(16) g10<1>F g16.3<0,1,0>D { align1 2H compacted }; mov(16) g10<1>F g16.3<0,1,0>D { align1 2H compacted }; mov(16) g55<1>UD g16.5<0,1,0>UD { align1 1H }; mov(16) g55<1>UD g16.5<0,1,0>UD { align1 1H }; mov(16) g117<1>UD g16.5<0,1,0>UD { align1 2H }; mov(16) g117<1>UD g16.5<0,1,0>UD { align1 2H }; mul(16) g66<1>F g58<1,1,0>F g49<1,1,0>F { align1 1H F@7 compacted }; mul(16) g66<1>F g58<1,1,0>F g49<1,1,0>F { align1 1H F@7 compacted }; sync nop(1) null<0,1,0>UB { align1 WE_all 5N F@7 }; sync nop(1) null<0,1,0>UB { align1 WE_all 5N F@7 }; mul(16) g12<1>F g111<1,1,0>F g94<1,1,0>F { align1 2H compacted }; mul(16) g12<1>F g111<1,1,0>F g94<1,1,0>F { align1 2H compacted }; mul(16) g68<1>F g60<1,1,0>F g49<1,1,0>F { align1 1H F@7 compacted }; mul(16) g68<1>F g60<1,1,0>F g49<1,1,0>F { align1 1H F@7 compacted }; mul(16) g14<1>F g113<1,1,0>F g94<1,1,0>F { align1 2H F@7 compacted }; mul(16) g14<1>F g113<1,1,0>F g94<1,1,0>F { align1 2H F@7 compacted }; mul(16) g70<1>F g62<1,1,0>F g49<1,1,0>F { align1 1H A@4 compacted }; mul(16) g70<1>F g62<1,1,0>F g49<1,1,0>F { align1 1H A@4 compacted }; mul(16) g51<1>F g115<1,1,0>F g94<1,1,0>F { align1 2H F@7 compacted }; mul(16) g51<1>F g115<1,1,0>F g94<1,1,0>F { align1 2H F@7 compacted }; mul(16) g72<1>F g64<1,1,0>F g49<1,1,0>F { align1 1H A@6 compacted }; mul(16) g72<1>F g64<1,1,0>F g49<1,1,0>F { align1 1H A@6 compacted }; mul(16) g53<1>F g10<1,1,0>F g94<1,1,0>F { align1 2H A@7 compacted }; mul(16) g53<1>F g10<1,1,0>F g94<1,1,0>F { align1 2H A@7 compacted }; mov(16) g2<1>D g66<1,1,0>F { align1 1H A@7 compacted }; mov(16) g2<1>D g66<1,1,0>F { align1 1H A@7 compacted }; mov(16) g17<1>D g12<1,1,0>F { align1 2H A@7 compacted }; mov(16) g17<1>D g12<1,1,0>F { align1 2H A@7 compacted }; mov(16) g4<1>D g68<1,1,0>F { align1 1H F@6 compacted }; mov(16) g4<1>D g68<1,1,0>F { align1 1H F@6 compacted }; mov(16) g19<1>D g14<1,1,0>F { align1 2H F@5 compacted }; mov(16) g19<1>D g14<1,1,0>F { align1 2H F@5 compacted }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N F@4 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N F@4 }; mov(16) g6<1>D g70<1,1,0>F { align1 1H compacted }; mov(16) g6<1>D g70<1,1,0>F { align1 1H compacted }; mov(16) g21<1>D g51<1,1,0>F { align1 2H F@3 compacted }; mov(16) g21<1>D g51<1,1,0>F { align1 2H F@3 compacted }; mov(16) g8<1>D g72<1,1,0>F { align1 1H F@2 compacted }; mov(16) g8<1>D g72<1,1,0>F { align1 1H F@2 compacted }; mov(16) g23<1>D g53<1,1,0>F { align1 2H F@1 compacted }; mov(16) g23<1>D g53<1,1,0>F { align1 2H F@1 compacted }; END B2 ->B3 END B2 ->B3 START B3 <-B2 <-B1 (4512 cycles) START B3 <-B2 <-B1 (4512 cycles) LABEL0: LABEL0: endif(32) JIP: LABEL2 { align1 }; endif(32) JIP: LABEL2 { align1 }; LABEL2: LABEL2: sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@3 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@3 }; sendc(16) nullUD g2UD g55UD 0x10030000 0x00000080 sendc(16) nullUD g2UD g55UD 0x10030000 0x00000080 render MsgDesc: RT write SIMD16 Surface = 0 mlen 8 ex_mlen 2 rlen 0 { align1 1H $4 }; render MsgDesc: RT write SIMD16 Surface = 0 mlen 8 ex_mlen 2 rlen 0 { align1 1H $4 }; sync nop(1) null<0,1,0>UB { align1 WE_all 5N I@2 }; sync nop(1) null<0,1,0>UB { align1 WE_all 5N I@2 }; sendc(16) nullUD g17UD g117UD 0x10030800 0x00000080 sendc(16) nullUD g17UD g117UD 0x10030800 0x00000080 render MsgDesc: RT write SIMD16 Hi Surface = 0 mlen 8 ex_mlen 2 rlen 0 { align1 2H $5 }; render MsgDesc: RT write SIMD16 Hi Surface = 0 mlen 8 ex_mlen 2 rlen 0 { align1 2H $5 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N $4.src }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N $4.src }; sendc(16) nullUD g25UD g55UD 0x10030001 0x00001080 sendc(16) nullUD g25UD g55UD 0x10030001 0x00001080 render MsgDesc: RT write SIMD16 Surface = 1 mlen 8 ex_mlen 2 rlen 0 { align1 1H $6 }; render MsgDesc: RT write SIMD16 Surface = 1 mlen 8 ex_mlen 2 rlen 0 { align1 1H $6 }; sync nop(1) null<0,1,0>UB { align1 WE_all 5N $5.src }; sync nop(1) null<0,1,0>UB { align1 WE_all 5N $5.src }; sendc(16) nullUD g33UD g117UD 0x10030801 0x00001080 sendc(16) nullUD g33UD g117UD 0x10030801 0x00001080 render MsgDesc: RT write SIMD16 Hi Surface = 1 mlen 8 ex_mlen 2 rlen 0 { align1 2H $7 }; render MsgDesc: RT write SIMD16 Hi Surface = 1 mlen 8 ex_mlen 2 rlen 0 { align1 2H $7 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N $6.src }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N $6.src }; sendc(16) nullUD g41UD g55UD 0x10031003 0x00003080 sendc(16) nullUD g41UD g55UD 0x10031003 0x00003080 render MsgDesc: RT write SIMD16 LastRT Surface = 3 mlen 8 ex_mlen 2 rlen 0 { align1 1H $8 render MsgDesc: RT write SIMD16 LastRT Surface = 3 mlen 8 ex_mlen 2 rlen 0 { align1 1H $8 sync nop(1) null<0,1,0>UB { align1 WE_all 1N $7.src }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N $7.src }; sendc(16) nullUD g119UD g117UD 0x10031803 0x00003080 sendc(16) nullUD g119UD g117UD 0x10031803 0x00003080 render MsgDesc: RT write SIMD16 Hi LastRT Surface = 3 mlen 8 ex_mlen 2 rlen 0 { align1 2H render MsgDesc: RT write SIMD16 Hi LastRT Surface = 3 mlen 8 ex_mlen 2 rlen 0 { align1 2H END B3 END B3 NIR (from SPIR-V) for MESA_SHADER_FRAGMENT shader: NIR (from SPIR-V) for MESA_SHADER_FRAGMENT shader: shader: MESA_SHADER_FRAGMENT shader: MESA_SHADER_FRAGMENT source_sha1: {0x3d24bac5, 0xe3beb1ae, 0xa14daaad, 0x9f221911, 0x5d3a4df4} source_sha1: {0x3d24bac5, 0xe3beb1ae, 0xa14daaad, 0x9f221911, 0x5d3a4df4} stage: 4 stage: 4 next_stage: 0 next_stage: 0 subgroup_size: 2 subgroup_size: 2 uses_sample_shading: true uses_sample_shading: true origin_upper_left: true origin_upper_left: true depth_layout: 1 depth_layout: 1 inputs: 0 inputs: 0 outputs: 0 outputs: 0 uniforms: 120 uniforms: 120 decl_var system INTERP_MODE_NONE vec4 @0 decl_var system INTERP_MODE_NONE vec4 @0 decl_var push_const INTERP_MODE_NONE block @1 decl_var push_const INTERP_MODE_NONE block @1 decl_var system INTERP_MODE_FLAT int @2 decl_var system INTERP_MODE_FLAT int @2 decl_var shader_out INTERP_MODE_NONE float @3 (FRAG_RESULT_DEPTH.x, 0, 0) decl_var shader_out INTERP_MODE_NONE float @3 (FRAG_RESULT_DEPTH.x, 0, 0) decl_function main (0 params) decl_function main (0 params) impl main { impl main { decl_var INTERP_MODE_NONE vec2 @4 decl_var INTERP_MODE_NONE vec2 @4 block block_0: block block_0: /* preds: */ /* preds: */ vec1 32 ssa_20 = load_const (0x00000000 = 0.000000) vec1 32 ssa_20 = load_const (0x00000000 = 0.000000) vec1 32 ssa_18 = load_const (0x00000002 = 0.000000) vec1 32 ssa_18 = load_const (0x00000002 = 0.000000) vec1 32 ssa_0 = deref_var &@0 (system vec4) vec1 32 ssa_0 = deref_var &@0 (system vec4) vec4 32 ssa_1 = intrinsic load_deref (ssa_0) (access=0) vec4 32 ssa_1 = intrinsic load_deref (ssa_0) (access=0) vec1 32 ssa_3 = deref_var &@1 (push_const block) vec1 32 ssa_3 = deref_var &@1 (push_const block) vec1 32 ssa_4 = deref_struct &ssa_3->field0 (push_const uvec4) /* &@1.field0 */ vec1 32 ssa_4 = deref_struct &ssa_3->field0 (push_const uvec4) /* &@1.field0 */ vec4 32 ssa_5 = intrinsic load_deref (ssa_4) (access=0) vec4 32 ssa_5 = intrinsic load_deref (ssa_4) (access=0) vec2 32 ssa_7 = u2f32 ssa_5.xy vec2 32 ssa_7 = u2f32 ssa_5.xy vec2 32 ssa_8 = fsub ssa_1.xy, ssa_7 vec2 32 ssa_8 = fsub ssa_1.xy, ssa_7 vec1 32 ssa_9 = deref_var &@1 (push_const block) vec1 32 ssa_9 = deref_var &@1 (push_const block) vec1 32 ssa_10 = deref_struct &ssa_9->field0 (push_const uvec4) /* &@1.field0 */ vec1 32 ssa_10 = deref_struct &ssa_9->field0 (push_const uvec4) /* &@1.field0 */ vec4 32 ssa_11 = intrinsic load_deref (ssa_10) (access=0) vec4 32 ssa_11 = intrinsic load_deref (ssa_10) (access=0) vec2 32 ssa_13 = u2f32 ssa_11.zw vec2 32 ssa_13 = u2f32 ssa_11.zw vec2 32 ssa_14 = fdiv ssa_8, ssa_13 vec2 32 ssa_14 = fdiv ssa_8, ssa_13 vec1 32 ssa_15 = deref_var &@4 (function_temp vec2) vec1 32 ssa_15 = deref_var &@4 (function_temp vec2) intrinsic store_deref (ssa_15, ssa_14) (wrmask=xy /*3*/, access=0) intrinsic store_deref (ssa_15, ssa_14) (wrmask=xy /*3*/, access=0) vec1 32 ssa_16 = deref_var &@2 (system int) vec1 32 ssa_16 = deref_var &@2 (system int) vec1 32 ssa_17 = intrinsic load_deref (ssa_16) (access=0) vec1 32 ssa_17 = intrinsic load_deref (ssa_16) (access=0) vec1 32 ssa_19 = imod ssa_17, ssa_18 vec1 32 ssa_19 = imod ssa_17, ssa_18 vec1 1 ssa_21 = ieq ssa_19, ssa_20 vec1 1 ssa_21 = ieq ssa_19, ssa_20 /* succs: block_1 block_2 */ /* succs: block_1 block_2 */ if ssa_21 { if ssa_21 { block block_1: block block_1: /* preds: block_0 */ /* preds: block_0 */ vec1 32 ssa_22 = deref_var &@1 (push_const block) vec1 32 ssa_22 = deref_var &@1 (push_const block) vec1 32 ssa_23 = deref_struct &ssa_22->field4 (push_const vec2) /* &@1.field4 */ vec1 32 ssa_23 = deref_struct &ssa_22->field4 (push_const vec2) /* &@1.field4 */ vec1 32 ssa_24 = load_const (0x00000000 = 0.000000) vec1 32 ssa_24 = load_const (0x00000000 = 0.000000) vec1 32 ssa_25 = deref_array &(*ssa_23)[0] (push_const float) /* &@1.field4[0] */ vec1 32 ssa_25 = deref_array &(*ssa_23)[0] (push_const float) /* &@1.field4[0] */ vec1 32 ssa_26 = intrinsic load_deref (ssa_25) (access=0) vec1 32 ssa_26 = intrinsic load_deref (ssa_25) (access=0) vec1 32 ssa_27 = deref_var &@3 (shader_out float) vec1 32 ssa_27 = deref_var &@3 (shader_out float) intrinsic store_deref (ssa_27, ssa_26) (wrmask=x /*1*/, access=0) intrinsic store_deref (ssa_27, ssa_26) (wrmask=x /*1*/, access=0) /* succs: block_3 */ /* succs: block_3 */ } else { } else { block block_2: block block_2: /* preds: block_0 */ /* preds: block_0 */ vec1 32 ssa_28 = deref_var &@1 (push_const block) vec1 32 ssa_28 = deref_var &@1 (push_const block) vec1 32 ssa_29 = deref_struct &ssa_28->field4 (push_const vec2) /* &@1.field4 */ vec1 32 ssa_29 = deref_struct &ssa_28->field4 (push_const vec2) /* &@1.field4 */ vec1 32 ssa_30 = load_const (0x00000001 = 0.000000) vec1 32 ssa_30 = load_const (0x00000001 = 0.000000) vec1 32 ssa_31 = deref_array &(*ssa_29)[1] (push_const float) /* &@1.field4[1] */ vec1 32 ssa_31 = deref_array &(*ssa_29)[1] (push_const float) /* &@1.field4[1] */ vec1 32 ssa_32 = intrinsic load_deref (ssa_31) (access=0) vec1 32 ssa_32 = intrinsic load_deref (ssa_31) (access=0) vec1 32 ssa_33 = deref_var &@3 (shader_out float) vec1 32 ssa_33 = deref_var &@3 (shader_out float) intrinsic store_deref (ssa_33, ssa_32) (wrmask=x /*1*/, access=0) intrinsic store_deref (ssa_33, ssa_32) (wrmask=x /*1*/, access=0) /* succs: block_3 */ /* succs: block_3 */ } } block block_3: block block_3: /* preds: block_1 block_2 */ /* preds: block_1 block_2 */ /* succs: block_4 */ /* succs: block_4 */ block block_4: block block_4: } } NIR (SSA form) for vertex shader: NIR (SSA form) for vertex shader: shader: MESA_SHADER_VERTEX shader: MESA_SHADER_VERTEX source_sha1: {0xc53eb86f, 0x5605e25e, 0x3afa45c3, 0x86021b0d, 0x73a6d842} source_sha1: {0xc53eb86f, 0x5605e25e, 0x3afa45c3, 0x86021b0d, 0x73a6d842} stage: 0 stage: 0 next_stage: 0 next_stage: 0 inputs_read: 15 inputs_read: 15 outputs_written: 0 outputs_written: 0 subgroup_size: 2 subgroup_size: 2 divergence_analysis_run: true divergence_analysis_run: true separate_shader: true separate_shader: true inputs: 0 inputs: 0 outputs: 0 outputs: 0 uniforms: 0 uniforms: 0 decl_var shader_in INTERP_MODE_NONE vec4 @0 (VERT_ATTRIB_GENERIC0.xyzw, 15, 0) decl_var shader_in INTERP_MODE_NONE vec4 @0 (VERT_ATTRIB_GENERIC0.xyzw, 15, 0) decl_var shader_out INTERP_MODE_NONE vec4 @1 (VARYING_SLOT_POS.xyzw, 0, 0) decl_var shader_out INTERP_MODE_NONE vec4 @1 (VARYING_SLOT_POS.xyzw, 0, 0) decl_function main (0 params) decl_function main (0 params) impl main { impl main { block block_0: block block_0: /* preds: */ /* preds: */ vec1 32 con ssa_0 = load_const (0x00000000 = 0.000000) vec1 32 con ssa_0 = load_const (0x00000000 = 0.000000) vec4 32 div ssa_1 = intrinsic load_input (ssa_0) (base=0, component=0, dest_type=float32 /*160*/, io location vec4 32 div ssa_1 = intrinsic load_input (ssa_0) (base=0, component=0, dest_type=float32 /*160*/, io location intrinsic store_output (ssa_1, ssa_0) (base=0, wrmask=xyzw /*15*/, component=0, src_type=float32 /*160*/, io intrinsic store_output (ssa_1, ssa_0) (base=0, wrmask=xyzw /*15*/, component=0, src_type=float32 /*160*/, io /* succs: block_1 */ /* succs: block_1 */ block block_1: block block_1: } } NIR (final form) for vertex shader: NIR (final form) for vertex shader: shader: MESA_SHADER_VERTEX shader: MESA_SHADER_VERTEX source_sha1: {0xc53eb86f, 0x5605e25e, 0x3afa45c3, 0x86021b0d, 0x73a6d842} source_sha1: {0xc53eb86f, 0x5605e25e, 0x3afa45c3, 0x86021b0d, 0x73a6d842} stage: 0 stage: 0 next_stage: 0 next_stage: 0 inputs_read: 15 inputs_read: 15 outputs_written: 0 outputs_written: 0 subgroup_size: 2 subgroup_size: 2 divergence_analysis_run: true divergence_analysis_run: true separate_shader: true separate_shader: true inputs: 0 inputs: 0 outputs: 0 outputs: 0 uniforms: 0 uniforms: 0 decl_var shader_in INTERP_MODE_NONE vec4 @0 (VERT_ATTRIB_GENERIC0.xyzw, 15, 0) decl_var shader_in INTERP_MODE_NONE vec4 @0 (VERT_ATTRIB_GENERIC0.xyzw, 15, 0) decl_var shader_out INTERP_MODE_NONE vec4 @1 (VARYING_SLOT_POS.xyzw, 0, 0) decl_var shader_out INTERP_MODE_NONE vec4 @1 (VARYING_SLOT_POS.xyzw, 0, 0) decl_function main (0 params) decl_function main (0 params) impl main { impl main { block block_0: block block_0: /* preds: */ /* preds: */ vec1 32 con ssa_0 = load_const (0x00000000 = 0.000000) vec1 32 con ssa_0 = load_const (0x00000000 = 0.000000) vec4 32 div ssa_1 = intrinsic load_input (ssa_0) (base=0, component=0, dest_type=float32 /*160*/, io location vec4 32 div ssa_1 = intrinsic load_input (ssa_0) (base=0, component=0, dest_type=float32 /*160*/, io location intrinsic store_output (ssa_1, ssa_0) (base=0, wrmask=xyzw /*15*/, component=0, src_type=float32 /*160*/, io intrinsic store_output (ssa_1, ssa_0) (base=0, wrmask=xyzw /*15*/, component=0, src_type=float32 /*160*/, io /* succs: block_1 */ /* succs: block_1 */ block block_1: block block_1: } } VS Output VUE map (4 slots, SSO) VS Output VUE map (4 slots, SSO) [0] VARYING_SLOT_PSIZ [0] VARYING_SLOT_PSIZ [1] VARYING_SLOT_POS [1] VARYING_SLOT_POS [2] VARYING_SLOT_CLIP_DIST0 [2] VARYING_SLOT_CLIP_DIST0 [3] VARYING_SLOT_CLIP_DIST1 [3] VARYING_SLOT_CLIP_DIST1 Native code for unnamed vertex shader (null) (sha1 b70dfaf2bb58ae45f979a67e09a12f4d8694a075) Native code for unnamed vertex shader (null) (sha1 b70dfaf2bb58ae45f979a67e09a12f4d8694a075) SIMD8 shader: 7 instructions. 0 loops. 22 cycles. 0:0 spills:fills, 1 sends, scheduled with mode top-down. Promoted 0 SIMD8 shader: 7 instructions. 0 loops. 22 cycles. 0:0 spills:fills, 1 sends, scheduled with mode top-down. Promoted 0 START B0 (22 cycles) START B0 (22 cycles) mov(8) g122<1>F g2<1,1,0>F { align1 1Q compacted }; mov(8) g122<1>F g2<1,1,0>F { align1 1Q compacted }; mov(8) g123<1>F g3<1,1,0>F { align1 1Q compacted }; mov(8) g123<1>F g3<1,1,0>F { align1 1Q compacted }; mov(8) g124<1>F g4<1,1,0>F { align1 1Q compacted }; mov(8) g124<1>F g4<1,1,0>F { align1 1Q compacted }; mov(8) g125<1>F g5<1,1,0>F { align1 1Q compacted }; mov(8) g125<1>F g5<1,1,0>F { align1 1Q compacted }; mov(8) g126<1>UD g1<8,8,1>UD { align1 WE_all 1Q }; mov(8) g126<1>UD g1<8,8,1>UD { align1 WE_all 1Q }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N A@1 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N A@1 }; send(8) nullUD g126UD g122UD 0x02080017 0x00000100 send(8) nullUD g126UD g122UD 0x02080017 0x00000100 urb MsgDesc: offset 1 SIMD8 write mlen 1 ex_mlen 4 rlen 0 { align1 1Q A@1 EOT }; urb MsgDesc: offset 1 SIMD8 write mlen 1 ex_mlen 4 rlen 0 { align1 1Q A@1 EOT }; END B0 END B0 NIR (SSA form) for fragment shader: NIR (SSA form) for fragment shader: shader: MESA_SHADER_FRAGMENT shader: MESA_SHADER_FRAGMENT source_sha1: {0x3d24bac5, 0xe3beb1ae, 0xa14daaad, 0x9f221911, 0x5d3a4df4} source_sha1: {0x3d24bac5, 0xe3beb1ae, 0xa14daaad, 0x9f221911, 0x5d3a4df4} stage: 4 stage: 4 next_stage: 0 next_stage: 0 outputs_written: 0 outputs_written: 0 system_values_read: 0x00000000'00000000'00800000 system_values_read: 0x00000000'00000000'00800000 subgroup_size: 2 subgroup_size: 2 divergence_analysis_run: true divergence_analysis_run: true bit_sizes_int: 0x21 bit_sizes_int: 0x21 separate_shader: true separate_shader: true uses_sample_shading: true uses_sample_shading: true origin_upper_left: true origin_upper_left: true depth_layout: 1 depth_layout: 1 inputs: 0 inputs: 0 outputs: 0 outputs: 0 uniforms: 120 uniforms: 120 decl_var push_const INTERP_MODE_NONE block @0 decl_var push_const INTERP_MODE_NONE block @0 decl_var shader_out INTERP_MODE_NONE float @1 (FRAG_RESULT_DEPTH.x, 0, 0) decl_var shader_out INTERP_MODE_NONE float @1 (FRAG_RESULT_DEPTH.x, 0, 0) decl_function main (0 params) decl_function main (0 params) impl main { impl main { block block_0: block block_0: /* preds: */ /* preds: */ vec1 32 con ssa_0 = load_const (0x00000000 = 0.000000) vec1 32 con ssa_0 = load_const (0x00000000 = 0.000000) vec1 32 div ssa_1 = intrinsic load_sample_id () () vec1 32 div ssa_1 = intrinsic load_sample_id () () vec1 32 con ssa_2 = load_const (0x00000001 = 0.000000) vec1 32 con ssa_2 = load_const (0x00000001 = 0.000000) vec1 32 div ssa_3 = iand ssa_1, ssa_2 vec1 32 div ssa_3 = iand ssa_1, ssa_2 vec1 32 con ssa_4 = load_const (0x00000070 = 0.000000) vec1 32 con ssa_4 = load_const (0x00000070 = 0.000000) vec1 32 con ssa_5 = intrinsic load_uniform (ssa_4) (base=0, range=120, dest_type=invalid /*256*/) vec1 32 con ssa_5 = intrinsic load_uniform (ssa_4) (base=0, range=120, dest_type=invalid /*256*/) vec1 32 con ssa_6 = load_const (0x00000074 = 0.000000) vec1 32 con ssa_6 = load_const (0x00000074 = 0.000000) vec1 32 con ssa_7 = intrinsic load_uniform (ssa_6) (base=0, range=120, dest_type=invalid /*256*/) vec1 32 con ssa_7 = intrinsic load_uniform (ssa_6) (base=0, range=120, dest_type=invalid /*256*/) vec1 32 div ssa_8 = ieq32 ssa_3, ssa_0 vec1 32 div ssa_8 = ieq32 ssa_3, ssa_0 vec1 32 div ssa_9 = b32csel ssa_8, ssa_5, ssa_7 vec1 32 div ssa_9 = b32csel ssa_8, ssa_5, ssa_7 intrinsic store_output (ssa_9, ssa_0) (base=0, wrmask=x /*1*/, component=0, src_type=float32 /*160*/, io loca intrinsic store_output (ssa_9, ssa_0) (base=0, wrmask=x /*1*/, component=0, src_type=float32 /*160*/, io loca /* succs: block_1 */ /* succs: block_1 */ block block_1: block block_1: } } NIR (final form) for fragment shader: NIR (final form) for fragment shader: shader: MESA_SHADER_FRAGMENT shader: MESA_SHADER_FRAGMENT source_sha1: {0x3d24bac5, 0xe3beb1ae, 0xa14daaad, 0x9f221911, 0x5d3a4df4} source_sha1: {0x3d24bac5, 0xe3beb1ae, 0xa14daaad, 0x9f221911, 0x5d3a4df4} stage: 4 stage: 4 next_stage: 0 next_stage: 0 outputs_written: 0 outputs_written: 0 system_values_read: 0x00000000'00000000'00800000 system_values_read: 0x00000000'00000000'00800000 subgroup_size: 2 subgroup_size: 2 divergence_analysis_run: true divergence_analysis_run: true bit_sizes_int: 0x21 bit_sizes_int: 0x21 separate_shader: true separate_shader: true uses_sample_shading: true uses_sample_shading: true origin_upper_left: true origin_upper_left: true depth_layout: 1 depth_layout: 1 inputs: 0 inputs: 0 outputs: 0 outputs: 0 uniforms: 120 uniforms: 120 decl_var push_const INTERP_MODE_NONE block @0 decl_var push_const INTERP_MODE_NONE block @0 decl_var shader_out INTERP_MODE_NONE float @1 (FRAG_RESULT_DEPTH.x, 0, 0) decl_var shader_out INTERP_MODE_NONE float @1 (FRAG_RESULT_DEPTH.x, 0, 0) decl_function main (0 params) decl_function main (0 params) impl main { impl main { block block_0: block block_0: /* preds: */ /* preds: */ vec1 32 con ssa_0 = load_const (0x00000000 = 0.000000) vec1 32 con ssa_0 = load_const (0x00000000 = 0.000000) vec1 32 div ssa_1 = intrinsic load_sample_id () () vec1 32 div ssa_1 = intrinsic load_sample_id () () vec1 32 con ssa_2 = load_const (0x00000001 = 0.000000) vec1 32 con ssa_2 = load_const (0x00000001 = 0.000000) vec1 32 div ssa_3 = iand ssa_1, ssa_2 vec1 32 div ssa_3 = iand ssa_1, ssa_2 vec1 32 con ssa_4 = load_const (0x00000070 = 0.000000) vec1 32 con ssa_4 = load_const (0x00000070 = 0.000000) vec1 32 con ssa_5 = intrinsic load_uniform (ssa_4) (base=0, range=120, dest_type=invalid /*256*/) vec1 32 con ssa_5 = intrinsic load_uniform (ssa_4) (base=0, range=120, dest_type=invalid /*256*/) vec1 32 con ssa_6 = load_const (0x00000074 = 0.000000) vec1 32 con ssa_6 = load_const (0x00000074 = 0.000000) vec1 32 con ssa_7 = intrinsic load_uniform (ssa_6) (base=0, range=120, dest_type=invalid /*256*/) vec1 32 con ssa_7 = intrinsic load_uniform (ssa_6) (base=0, range=120, dest_type=invalid /*256*/) vec1 32 div ssa_8 = ieq32 ssa_3, ssa_0 vec1 32 div ssa_8 = ieq32 ssa_3, ssa_0 vec1 32 div ssa_9 = b32csel ssa_8, ssa_5, ssa_7 vec1 32 div ssa_9 = b32csel ssa_8, ssa_5, ssa_7 intrinsic store_output (ssa_9, ssa_0) (base=0, wrmask=x /*1*/, component=0, src_type=float32 /*160*/, io loca intrinsic store_output (ssa_9, ssa_0) (base=0, wrmask=x /*1*/, component=0, src_type=float32 /*160*/, io loca /* succs: block_1 */ /* succs: block_1 */ block block_1: block block_1: } } Native code for unnamed fragment shader (null) (sha1 afe19f2dbb5ed9a62597aa4ae0d4019c7e2cbc6b) Native code for unnamed fragment shader (null) (sha1 afe19f2dbb5ed9a62597aa4ae0d4019c7e2cbc6b) SIMD8 shader: 5 instructions. 0 loops. 54 cycles. 0:0 spills:fills, 1 sends, scheduled with mode top-down. Promoted 0 SIMD8 shader: 5 instructions. 0 loops. 54 cycles. 0:0 spills:fills, 1 sends, scheduled with mode top-down. Promoted 0 START B0 (54 cycles) START B0 (54 cycles) shr(8) g3<1>UW g1<1,8,0>UB 0x44440000V { align1 1Q }; shr(8) g3<1>UW g1<1,8,0>UB 0x44440000V { align1 1Q }; and(8) g2<1>UD g3<8,8,1>UW 15W { align1 1Q I@1 }; and(8) g2<1>UD g3<8,8,1>UW 15W { align1 1Q I@1 }; and.z.f0.0(8) null<1>UD g2<8,8,1>UD 0x00000001UD { align1 1Q I@1 }; and.z.f0.0(8) null<1>UD g2<8,8,1>UD 0x00000001UD { align1 1Q I@1 }; (+f0.0) sel(8) g122<1>UD g5.4<0,1,0>UD g5.5<0,1,0>UD { align1 1Q }; (+f0.0) sel(8) g122<1>UD g5.4<0,1,0>UD g5.5<0,1,0>UD { align1 1Q }; sendc(8) nullUD g123UD g122UD 0x08031400 0x00100040 sendc(8) nullUD g123UD g122UD 0x08031400 0x00100040 render MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 4 ex_mlen 1 rlen 0 { align1 1Q A@1 render MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 4 ex_mlen 1 rlen 0 { align1 1Q A@1 END B0 END B0 Native code for unnamed fragment shader (null) (sha1 c64cfb2aab2d056c12a196991e4e0b227ec416b1) Native code for unnamed fragment shader (null) (sha1 c64cfb2aab2d056c12a196991e4e0b227ec416b1) SIMD16 shader: 5 instructions. 0 loops. 60 cycles. 0:0 spills:fills, 1 sends, scheduled with mode top-down. Promoted SIMD16 shader: 5 instructions. 0 loops. 60 cycles. 0:0 spills:fills, 1 sends, scheduled with mode top-down. Promoted START B0 (60 cycles) START B0 (60 cycles) shr(16) g4<1>UW g1<1,8,0>UB 0x44440000V { align1 1H }; shr(16) g4<1>UW g1<1,8,0>UB 0x44440000V { align1 1H }; and(16) g2<1>UD g4<8,8,1>UW 15W { align1 1H I@1 }; and(16) g2<1>UD g4<8,8,1>UW 15W { align1 1H I@1 }; and.z.f0.0(16) null<1>UD g2<8,8,1>UD 0x00000001UD { align1 1H I@1 }; and.z.f0.0(16) null<1>UD g2<8,8,1>UD 0x00000001UD { align1 1H I@1 }; (+f0.0) sel(16) g117<1>UD g5.4<0,1,0>UD g5.5<0,1,0>UD { align1 1H }; (+f0.0) sel(16) g117<1>UD g5.4<0,1,0>UD g5.5<0,1,0>UD { align1 1H }; sendc(16) nullUD g119UD g117UD 0x10031000 0x00100080 sendc(16) nullUD g119UD g117UD 0x10031000 0x00100080 render MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 8 ex_mlen 2 rlen 0 { align1 1H A@ render MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 8 ex_mlen 2 rlen 0 { align1 1H A@ END B0 END B0 Native code for unnamed fragment shader (null) (sha1 27452be09eccfdb15b6836f3bb1d43fa65ba9cbf) Native code for unnamed fragment shader (null) (sha1 27452be09eccfdb15b6836f3bb1d43fa65ba9cbf) SIMD32 shader: 11 instructions. 0 loops. 960 cycles. 0:0 spills:fills, 2 sends, scheduled with mode top-down. Promote SIMD32 shader: 11 instructions. 0 loops. 960 cycles. 0:0 spills:fills, 2 sends, scheduled with mode top-down. Promote START B0 (960 cycles) START B0 (960 cycles) shr(16) g9<1>UW g1<1,8,0>UB 0x44440000V { align1 1H }; shr(16) g9<1>UW g1<1,8,0>UB 0x44440000V { align1 1H }; shr(16) g4<1>UW g2<1,8,0>UB 0x44440000V { align1 2H }; shr(16) g4<1>UW g2<1,8,0>UB 0x44440000V { align1 2H }; and(16) g7<1>UD g9<8,8,1>UW 15W { align1 1H I@2 }; and(16) g7<1>UD g9<8,8,1>UW 15W { align1 1H I@2 }; and(16) g2<1>UD g4<8,8,1>UW 15W { align1 2H I@2 }; and(16) g2<1>UD g4<8,8,1>UW 15W { align1 2H I@2 }; and.z.f0.0(16) null<1>UD g7<8,8,1>UD 0x00000001UD { align1 1H I@2 }; and.z.f0.0(16) null<1>UD g7<8,8,1>UD 0x00000001UD { align1 1H I@2 }; and.z.f0.0(16) null<1>UD g2<8,8,1>UD 0x00000001UD { align1 2H I@2 }; and.z.f0.0(16) null<1>UD g2<8,8,1>UD 0x00000001UD { align1 2H I@2 }; (+f0.0) sel(16) g13<1>UD g6.4<0,1,0>UD g6.5<0,1,0>UD { align1 1H }; (+f0.0) sel(16) g13<1>UD g6.4<0,1,0>UD g6.5<0,1,0>UD { align1 1H }; (+f0.0) sel(16) g117<1>UD g6.4<0,1,0>UD g6.5<0,1,0>UD { align1 2H }; (+f0.0) sel(16) g117<1>UD g6.4<0,1,0>UD g6.5<0,1,0>UD { align1 2H }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@2 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@2 }; sendc(16) nullUD g5UD g13UD 0x10031000 0x00100080 sendc(16) nullUD g5UD g13UD 0x10031000 0x00100080 render MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 8 ex_mlen 2 rlen 0 { align1 1H $0 render MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 8 ex_mlen 2 rlen 0 { align1 1H $0 sendc(16) nullUD g119UD g117UD 0x10031800 0x00100080 sendc(16) nullUD g119UD g117UD 0x10031800 0x00100080 render MsgDesc: RT write SIMD16 Hi LastRT Surface = 0 mlen 8 ex_mlen 2 rlen 0 { align1 2H render MsgDesc: RT write SIMD16 Hi LastRT Surface = 0 mlen 8 ex_mlen 2 rlen 0 { align1 2H END B0 END B0 NIR (from SPIR-V) for MESA_SHADER_FRAGMENT shader: NIR (from SPIR-V) for MESA_SHADER_FRAGMENT shader: shader: MESA_SHADER_FRAGMENT shader: MESA_SHADER_FRAGMENT source_sha1: {0xdd3ea721, 0x16552cc9, 0x83165d70, 0x5824ee3f, 0x1dadb651} source_sha1: {0xdd3ea721, 0x16552cc9, 0x83165d70, 0x5824ee3f, 0x1dadb651} stage: 4 stage: 4 next_stage: 0 next_stage: 0 subgroup_size: 2 subgroup_size: 2 uses_sample_shading: true uses_sample_shading: true origin_upper_left: true origin_upper_left: true depth_layout: 1 depth_layout: 1 inputs: 0 inputs: 0 outputs: 0 outputs: 0 uniforms: 120 uniforms: 120 decl_var system INTERP_MODE_NONE vec4 @0 decl_var system INTERP_MODE_NONE vec4 @0 decl_var push_const INTERP_MODE_NONE block @1 decl_var push_const INTERP_MODE_NONE block @1 decl_var system INTERP_MODE_FLAT int @2 decl_var system INTERP_MODE_FLAT int @2 decl_var shader_out INTERP_MODE_NONE vec4 @3 (FRAG_RESULT_DATA0.xyzw, 0, 0) decl_var shader_out INTERP_MODE_NONE vec4 @3 (FRAG_RESULT_DATA0.xyzw, 0, 0) decl_var shader_out INTERP_MODE_NONE vec4 @4 (FRAG_RESULT_DATA3.xyzw, 0, 0) decl_var shader_out INTERP_MODE_NONE vec4 @4 (FRAG_RESULT_DATA3.xyzw, 0, 0) decl_var shader_out INTERP_MODE_NONE float @5 (FRAG_RESULT_DEPTH.x, 0, 0) decl_var shader_out INTERP_MODE_NONE float @5 (FRAG_RESULT_DEPTH.x, 0, 0) decl_function main (0 params) decl_function main (0 params) impl main { impl main { decl_var INTERP_MODE_NONE vec2 @6 decl_var INTERP_MODE_NONE vec2 @6 block block_0: block block_0: /* preds: */ /* preds: */ vec1 32 ssa_20 = load_const (0x00000000 = 0.000000) vec1 32 ssa_20 = load_const (0x00000000 = 0.000000) vec1 32 ssa_18 = load_const (0x00000002 = 0.000000) vec1 32 ssa_18 = load_const (0x00000002 = 0.000000) vec1 32 ssa_0 = deref_var &@0 (system vec4) vec1 32 ssa_0 = deref_var &@0 (system vec4) vec4 32 ssa_1 = intrinsic load_deref (ssa_0) (access=0) vec4 32 ssa_1 = intrinsic load_deref (ssa_0) (access=0) vec1 32 ssa_3 = deref_var &@1 (push_const block) vec1 32 ssa_3 = deref_var &@1 (push_const block) vec1 32 ssa_4 = deref_struct &ssa_3->field0 (push_const uvec4) /* &@1.field0 */ vec1 32 ssa_4 = deref_struct &ssa_3->field0 (push_const uvec4) /* &@1.field0 */ vec4 32 ssa_5 = intrinsic load_deref (ssa_4) (access=0) vec4 32 ssa_5 = intrinsic load_deref (ssa_4) (access=0) vec2 32 ssa_7 = u2f32 ssa_5.xy vec2 32 ssa_7 = u2f32 ssa_5.xy vec2 32 ssa_8 = fsub ssa_1.xy, ssa_7 vec2 32 ssa_8 = fsub ssa_1.xy, ssa_7 vec1 32 ssa_9 = deref_var &@1 (push_const block) vec1 32 ssa_9 = deref_var &@1 (push_const block) vec1 32 ssa_10 = deref_struct &ssa_9->field0 (push_const uvec4) /* &@1.field0 */ vec1 32 ssa_10 = deref_struct &ssa_9->field0 (push_const uvec4) /* &@1.field0 */ vec4 32 ssa_11 = intrinsic load_deref (ssa_10) (access=0) vec4 32 ssa_11 = intrinsic load_deref (ssa_10) (access=0) vec2 32 ssa_13 = u2f32 ssa_11.zw vec2 32 ssa_13 = u2f32 ssa_11.zw vec2 32 ssa_14 = fdiv ssa_8, ssa_13 vec2 32 ssa_14 = fdiv ssa_8, ssa_13 vec1 32 ssa_15 = deref_var &@6 (function_temp vec2) vec1 32 ssa_15 = deref_var &@6 (function_temp vec2) intrinsic store_deref (ssa_15, ssa_14) (wrmask=xy /*3*/, access=0) intrinsic store_deref (ssa_15, ssa_14) (wrmask=xy /*3*/, access=0) vec1 32 ssa_16 = deref_var &@2 (system int) vec1 32 ssa_16 = deref_var &@2 (system int) vec1 32 ssa_17 = intrinsic load_deref (ssa_16) (access=0) vec1 32 ssa_17 = intrinsic load_deref (ssa_16) (access=0) vec1 32 ssa_19 = imod ssa_17, ssa_18 vec1 32 ssa_19 = imod ssa_17, ssa_18 vec1 1 ssa_21 = ieq ssa_19, ssa_20 vec1 1 ssa_21 = ieq ssa_19, ssa_20 /* succs: block_1 block_2 */ /* succs: block_1 block_2 */ if ssa_21 { if ssa_21 { block block_1: block block_1: /* preds: block_0 */ /* preds: block_0 */ vec1 32 ssa_22 = deref_var &@1 (push_const block) vec1 32 ssa_22 = deref_var &@1 (push_const block) vec1 32 ssa_23 = deref_struct &ssa_22->field1 (push_const vec4[2]) /* &@1.field1 */ vec1 32 ssa_23 = deref_struct &ssa_22->field1 (push_const vec4[2]) /* &@1.field1 */ vec1 32 ssa_24 = load_const (0x00000000 = 0.000000) vec1 32 ssa_24 = load_const (0x00000000 = 0.000000) vec1 32 ssa_25 = deref_array &(*ssa_23)[0] (push_const vec4) /* &@1.field1[0] */ vec1 32 ssa_25 = deref_array &(*ssa_23)[0] (push_const vec4) /* &@1.field1[0] */ vec4 32 ssa_26 = intrinsic load_deref (ssa_25) (access=0) vec4 32 ssa_26 = intrinsic load_deref (ssa_25) (access=0) vec1 32 ssa_27 = deref_var &@6 (function_temp vec2) vec1 32 ssa_27 = deref_var &@6 (function_temp vec2) vec2 32 ssa_30 = intrinsic load_deref (ssa_27) (access=0) vec2 32 ssa_30 = intrinsic load_deref (ssa_27) (access=0) vec4 32 ssa_32 = fmul ssa_26, ssa_30.xxxx vec4 32 ssa_32 = fmul ssa_26, ssa_30.xxxx vec1 32 ssa_33 = deref_var &@3 (shader_out vec4) vec1 32 ssa_33 = deref_var &@3 (shader_out vec4) intrinsic store_deref (ssa_33, ssa_32) (wrmask=xyzw /*15*/, access=0) intrinsic store_deref (ssa_33, ssa_32) (wrmask=xyzw /*15*/, access=0) vec1 32 ssa_34 = deref_var &@1 (push_const block) vec1 32 ssa_34 = deref_var &@1 (push_const block) vec1 32 ssa_35 = deref_struct &ssa_34->field2 (push_const vec4[2]) /* &@1.field2 */ vec1 32 ssa_35 = deref_struct &ssa_34->field2 (push_const vec4[2]) /* &@1.field2 */ vec1 32 ssa_36 = load_const (0x00000000 = 0.000000) vec1 32 ssa_36 = load_const (0x00000000 = 0.000000) vec1 32 ssa_37 = deref_array &(*ssa_35)[0] (push_const vec4) /* &@1.field2[0] */ vec1 32 ssa_37 = deref_array &(*ssa_35)[0] (push_const vec4) /* &@1.field2[0] */ vec4 32 ssa_38 = intrinsic load_deref (ssa_37) (access=0) vec4 32 ssa_38 = intrinsic load_deref (ssa_37) (access=0) vec1 32 ssa_39 = deref_var &@6 (function_temp vec2) vec1 32 ssa_39 = deref_var &@6 (function_temp vec2) vec2 32 ssa_42 = intrinsic load_deref (ssa_39) (access=0) vec2 32 ssa_42 = intrinsic load_deref (ssa_39) (access=0) vec4 32 ssa_44 = fmul ssa_38, ssa_42.xxxx vec4 32 ssa_44 = fmul ssa_38, ssa_42.xxxx vec1 32 ssa_45 = deref_var &@4 (shader_out vec4) vec1 32 ssa_45 = deref_var &@4 (shader_out vec4) intrinsic store_deref (ssa_45, ssa_44) (wrmask=xyzw /*15*/, access=0) intrinsic store_deref (ssa_45, ssa_44) (wrmask=xyzw /*15*/, access=0) vec1 32 ssa_46 = deref_var &@1 (push_const block) vec1 32 ssa_46 = deref_var &@1 (push_const block) vec1 32 ssa_47 = deref_struct &ssa_46->field4 (push_const vec2) /* &@1.field4 */ vec1 32 ssa_47 = deref_struct &ssa_46->field4 (push_const vec2) /* &@1.field4 */ vec1 32 ssa_48 = load_const (0x00000000 = 0.000000) vec1 32 ssa_48 = load_const (0x00000000 = 0.000000) vec1 32 ssa_49 = deref_array &(*ssa_47)[0] (push_const float) /* &@1.field4[0] */ vec1 32 ssa_49 = deref_array &(*ssa_47)[0] (push_const float) /* &@1.field4[0] */ vec1 32 ssa_50 = intrinsic load_deref (ssa_49) (access=0) vec1 32 ssa_50 = intrinsic load_deref (ssa_49) (access=0) vec1 32 ssa_51 = deref_var &@5 (shader_out float) vec1 32 ssa_51 = deref_var &@5 (shader_out float) intrinsic store_deref (ssa_51, ssa_50) (wrmask=x /*1*/, access=0) intrinsic store_deref (ssa_51, ssa_50) (wrmask=x /*1*/, access=0) /* succs: block_3 */ /* succs: block_3 */ } else { } else { block block_2: block block_2: /* preds: block_0 */ /* preds: block_0 */ vec1 32 ssa_52 = deref_var &@1 (push_const block) vec1 32 ssa_52 = deref_var &@1 (push_const block) vec1 32 ssa_53 = deref_struct &ssa_52->field1 (push_const vec4[2]) /* &@1.field1 */ vec1 32 ssa_53 = deref_struct &ssa_52->field1 (push_const vec4[2]) /* &@1.field1 */ vec1 32 ssa_54 = load_const (0x00000001 = 0.000000) vec1 32 ssa_54 = load_const (0x00000001 = 0.000000) vec1 32 ssa_55 = deref_array &(*ssa_53)[1] (push_const vec4) /* &@1.field1[1] */ vec1 32 ssa_55 = deref_array &(*ssa_53)[1] (push_const vec4) /* &@1.field1[1] */ vec4 32 ssa_56 = intrinsic load_deref (ssa_55) (access=0) vec4 32 ssa_56 = intrinsic load_deref (ssa_55) (access=0) vec1 32 ssa_57 = deref_var &@6 (function_temp vec2) vec1 32 ssa_57 = deref_var &@6 (function_temp vec2) vec2 32 ssa_60 = intrinsic load_deref (ssa_57) (access=0) vec2 32 ssa_60 = intrinsic load_deref (ssa_57) (access=0) vec4 32 ssa_62 = fmul ssa_56, ssa_60.yyyy vec4 32 ssa_62 = fmul ssa_56, ssa_60.yyyy vec1 32 ssa_63 = deref_var &@3 (shader_out vec4) vec1 32 ssa_63 = deref_var &@3 (shader_out vec4) intrinsic store_deref (ssa_63, ssa_62) (wrmask=xyzw /*15*/, access=0) intrinsic store_deref (ssa_63, ssa_62) (wrmask=xyzw /*15*/, access=0) vec1 32 ssa_64 = deref_var &@1 (push_const block) vec1 32 ssa_64 = deref_var &@1 (push_const block) vec1 32 ssa_65 = deref_struct &ssa_64->field2 (push_const vec4[2]) /* &@1.field2 */ vec1 32 ssa_65 = deref_struct &ssa_64->field2 (push_const vec4[2]) /* &@1.field2 */ vec1 32 ssa_66 = load_const (0x00000001 = 0.000000) vec1 32 ssa_66 = load_const (0x00000001 = 0.000000) vec1 32 ssa_67 = deref_array &(*ssa_65)[1] (push_const vec4) /* &@1.field2[1] */ vec1 32 ssa_67 = deref_array &(*ssa_65)[1] (push_const vec4) /* &@1.field2[1] */ vec4 32 ssa_68 = intrinsic load_deref (ssa_67) (access=0) vec4 32 ssa_68 = intrinsic load_deref (ssa_67) (access=0) vec1 32 ssa_69 = deref_var &@6 (function_temp vec2) vec1 32 ssa_69 = deref_var &@6 (function_temp vec2) vec2 32 ssa_72 = intrinsic load_deref (ssa_69) (access=0) vec2 32 ssa_72 = intrinsic load_deref (ssa_69) (access=0) vec4 32 ssa_74 = fmul ssa_68, ssa_72.yyyy vec4 32 ssa_74 = fmul ssa_68, ssa_72.yyyy vec1 32 ssa_75 = deref_var &@4 (shader_out vec4) vec1 32 ssa_75 = deref_var &@4 (shader_out vec4) intrinsic store_deref (ssa_75, ssa_74) (wrmask=xyzw /*15*/, access=0) intrinsic store_deref (ssa_75, ssa_74) (wrmask=xyzw /*15*/, access=0) vec1 32 ssa_76 = deref_var &@1 (push_const block) vec1 32 ssa_76 = deref_var &@1 (push_const block) vec1 32 ssa_77 = deref_struct &ssa_76->field4 (push_const vec2) /* &@1.field4 */ vec1 32 ssa_77 = deref_struct &ssa_76->field4 (push_const vec2) /* &@1.field4 */ vec1 32 ssa_78 = load_const (0x00000001 = 0.000000) vec1 32 ssa_78 = load_const (0x00000001 = 0.000000) vec1 32 ssa_79 = deref_array &(*ssa_77)[1] (push_const float) /* &@1.field4[1] */ vec1 32 ssa_79 = deref_array &(*ssa_77)[1] (push_const float) /* &@1.field4[1] */ vec1 32 ssa_80 = intrinsic load_deref (ssa_79) (access=0) vec1 32 ssa_80 = intrinsic load_deref (ssa_79) (access=0) vec1 32 ssa_81 = deref_var &@5 (shader_out float) vec1 32 ssa_81 = deref_var &@5 (shader_out float) intrinsic store_deref (ssa_81, ssa_80) (wrmask=x /*1*/, access=0) intrinsic store_deref (ssa_81, ssa_80) (wrmask=x /*1*/, access=0) /* succs: block_3 */ /* succs: block_3 */ } } block block_3: block block_3: /* preds: block_1 block_2 */ /* preds: block_1 block_2 */ /* succs: block_4 */ /* succs: block_4 */ block block_4: block block_4: } } NIR (SSA form) for vertex shader: NIR (SSA form) for vertex shader: shader: MESA_SHADER_VERTEX shader: MESA_SHADER_VERTEX source_sha1: {0xc53eb86f, 0x5605e25e, 0x3afa45c3, 0x86021b0d, 0x73a6d842} source_sha1: {0xc53eb86f, 0x5605e25e, 0x3afa45c3, 0x86021b0d, 0x73a6d842} stage: 0 stage: 0 next_stage: 0 next_stage: 0 inputs_read: 15 inputs_read: 15 outputs_written: 0 outputs_written: 0 subgroup_size: 2 subgroup_size: 2 divergence_analysis_run: true divergence_analysis_run: true separate_shader: true separate_shader: true inputs: 0 inputs: 0 outputs: 0 outputs: 0 uniforms: 0 uniforms: 0 decl_var shader_in INTERP_MODE_NONE vec4 @0 (VERT_ATTRIB_GENERIC0.xyzw, 15, 0) decl_var shader_in INTERP_MODE_NONE vec4 @0 (VERT_ATTRIB_GENERIC0.xyzw, 15, 0) decl_var shader_out INTERP_MODE_NONE vec4 @1 (VARYING_SLOT_POS.xyzw, 0, 0) decl_var shader_out INTERP_MODE_NONE vec4 @1 (VARYING_SLOT_POS.xyzw, 0, 0) decl_function main (0 params) decl_function main (0 params) impl main { impl main { block block_0: block block_0: /* preds: */ /* preds: */ vec1 32 con ssa_0 = load_const (0x00000000 = 0.000000) vec1 32 con ssa_0 = load_const (0x00000000 = 0.000000) vec4 32 div ssa_1 = intrinsic load_input (ssa_0) (base=0, component=0, dest_type=float32 /*160*/, io location vec4 32 div ssa_1 = intrinsic load_input (ssa_0) (base=0, component=0, dest_type=float32 /*160*/, io location intrinsic store_output (ssa_1, ssa_0) (base=0, wrmask=xyzw /*15*/, component=0, src_type=float32 /*160*/, io intrinsic store_output (ssa_1, ssa_0) (base=0, wrmask=xyzw /*15*/, component=0, src_type=float32 /*160*/, io /* succs: block_1 */ /* succs: block_1 */ block block_1: block block_1: } } NIR (final form) for vertex shader: NIR (final form) for vertex shader: shader: MESA_SHADER_VERTEX shader: MESA_SHADER_VERTEX source_sha1: {0xc53eb86f, 0x5605e25e, 0x3afa45c3, 0x86021b0d, 0x73a6d842} source_sha1: {0xc53eb86f, 0x5605e25e, 0x3afa45c3, 0x86021b0d, 0x73a6d842} stage: 0 stage: 0 next_stage: 0 next_stage: 0 inputs_read: 15 inputs_read: 15 outputs_written: 0 outputs_written: 0 subgroup_size: 2 subgroup_size: 2 divergence_analysis_run: true divergence_analysis_run: true separate_shader: true separate_shader: true inputs: 0 inputs: 0 outputs: 0 outputs: 0 uniforms: 0 uniforms: 0 decl_var shader_in INTERP_MODE_NONE vec4 @0 (VERT_ATTRIB_GENERIC0.xyzw, 15, 0) decl_var shader_in INTERP_MODE_NONE vec4 @0 (VERT_ATTRIB_GENERIC0.xyzw, 15, 0) decl_var shader_out INTERP_MODE_NONE vec4 @1 (VARYING_SLOT_POS.xyzw, 0, 0) decl_var shader_out INTERP_MODE_NONE vec4 @1 (VARYING_SLOT_POS.xyzw, 0, 0) decl_function main (0 params) decl_function main (0 params) impl main { impl main { block block_0: block block_0: /* preds: */ /* preds: */ vec1 32 con ssa_0 = load_const (0x00000000 = 0.000000) vec1 32 con ssa_0 = load_const (0x00000000 = 0.000000) vec4 32 div ssa_1 = intrinsic load_input (ssa_0) (base=0, component=0, dest_type=float32 /*160*/, io location vec4 32 div ssa_1 = intrinsic load_input (ssa_0) (base=0, component=0, dest_type=float32 /*160*/, io location intrinsic store_output (ssa_1, ssa_0) (base=0, wrmask=xyzw /*15*/, component=0, src_type=float32 /*160*/, io intrinsic store_output (ssa_1, ssa_0) (base=0, wrmask=xyzw /*15*/, component=0, src_type=float32 /*160*/, io /* succs: block_1 */ /* succs: block_1 */ block block_1: block block_1: } } VS Output VUE map (4 slots, SSO) VS Output VUE map (4 slots, SSO) [0] VARYING_SLOT_PSIZ [0] VARYING_SLOT_PSIZ [1] VARYING_SLOT_POS [1] VARYING_SLOT_POS [2] VARYING_SLOT_CLIP_DIST0 [2] VARYING_SLOT_CLIP_DIST0 [3] VARYING_SLOT_CLIP_DIST1 [3] VARYING_SLOT_CLIP_DIST1 Native code for unnamed vertex shader (null) (sha1 b70dfaf2bb58ae45f979a67e09a12f4d8694a075) Native code for unnamed vertex shader (null) (sha1 b70dfaf2bb58ae45f979a67e09a12f4d8694a075) SIMD8 shader: 7 instructions. 0 loops. 22 cycles. 0:0 spills:fills, 1 sends, scheduled with mode top-down. Promoted 0 SIMD8 shader: 7 instructions. 0 loops. 22 cycles. 0:0 spills:fills, 1 sends, scheduled with mode top-down. Promoted 0 START B0 (22 cycles) START B0 (22 cycles) mov(8) g122<1>F g2<1,1,0>F { align1 1Q compacted }; mov(8) g122<1>F g2<1,1,0>F { align1 1Q compacted }; mov(8) g123<1>F g3<1,1,0>F { align1 1Q compacted }; mov(8) g123<1>F g3<1,1,0>F { align1 1Q compacted }; mov(8) g124<1>F g4<1,1,0>F { align1 1Q compacted }; mov(8) g124<1>F g4<1,1,0>F { align1 1Q compacted }; mov(8) g125<1>F g5<1,1,0>F { align1 1Q compacted }; mov(8) g125<1>F g5<1,1,0>F { align1 1Q compacted }; mov(8) g126<1>UD g1<8,8,1>UD { align1 WE_all 1Q }; mov(8) g126<1>UD g1<8,8,1>UD { align1 WE_all 1Q }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N A@1 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N A@1 }; send(8) nullUD g126UD g122UD 0x02080017 0x00000100 send(8) nullUD g126UD g122UD 0x02080017 0x00000100 urb MsgDesc: offset 1 SIMD8 write mlen 1 ex_mlen 4 rlen 0 { align1 1Q A@1 EOT }; urb MsgDesc: offset 1 SIMD8 write mlen 1 ex_mlen 4 rlen 0 { align1 1Q A@1 EOT }; END B0 END B0 NIR (SSA form) for fragment shader: NIR (SSA form) for fragment shader: shader: MESA_SHADER_FRAGMENT shader: MESA_SHADER_FRAGMENT source_sha1: {0xdd3ea721, 0x16552cc9, 0x83165d70, 0x5824ee3f, 0x1dadb651} source_sha1: {0xdd3ea721, 0x16552cc9, 0x83165d70, 0x5824ee3f, 0x1dadb651} stage: 4 stage: 4 next_stage: 0 next_stage: 0 outputs_written: 0,4,7 outputs_written: 0,4,7 system_values_read: 0x00000000'00000000'02880000 system_values_read: 0x00000000'00000000'02880000 subgroup_size: 2 subgroup_size: 2 divergence_analysis_run: true divergence_analysis_run: true bit_sizes_float: 0x20 bit_sizes_float: 0x20 bit_sizes_int: 0x21 bit_sizes_int: 0x21 separate_shader: true separate_shader: true uses_sample_shading: true uses_sample_shading: true origin_upper_left: true origin_upper_left: true depth_layout: 1 depth_layout: 1 inputs: 0 inputs: 0 outputs: 0 outputs: 0 uniforms: 120 uniforms: 120 decl_var push_const INTERP_MODE_NONE block @0 decl_var push_const INTERP_MODE_NONE block @0 decl_var shader_out INTERP_MODE_NONE vec4 @1 (FRAG_RESULT_DATA0.xyzw, 8, 0) decl_var shader_out INTERP_MODE_NONE vec4 @1 (FRAG_RESULT_DATA0.xyzw, 8, 0) decl_var shader_out INTERP_MODE_NONE vec4 @2 (FRAG_RESULT_DATA3.xyzw, 14, 0) decl_var shader_out INTERP_MODE_NONE vec4 @2 (FRAG_RESULT_DATA3.xyzw, 14, 0) decl_var shader_out INTERP_MODE_NONE float @3 (FRAG_RESULT_DEPTH.x, 0, 0) decl_var shader_out INTERP_MODE_NONE float @3 (FRAG_RESULT_DEPTH.x, 0, 0) decl_function main (0 params) decl_function main (0 params) impl main { impl main { block block_0: block block_0: /* preds: */ /* preds: */ vec1 32 con ssa_0 = load_const (0x00000000 = 0.000000) vec1 32 con ssa_0 = load_const (0x00000000 = 0.000000) vec4 32 div ssa_1 = intrinsic load_frag_coord () () vec4 32 div ssa_1 = intrinsic load_frag_coord () () vec2 32 div ssa_2 = intrinsic load_sample_pos_or_center () () vec2 32 div ssa_2 = intrinsic load_sample_pos_or_center () () vec1 32 div ssa_3 = fadd ssa_1.x, ssa_2.x vec1 32 div ssa_3 = fadd ssa_1.x, ssa_2.x vec1 32 div ssa_4 = fadd ssa_1.y, ssa_2.y vec1 32 div ssa_4 = fadd ssa_1.y, ssa_2.y vec4 32 con ssa_5 = intrinsic load_uniform (ssa_0) (base=0, range=120, dest_type=invalid /*256*/) vec4 32 con ssa_5 = intrinsic load_uniform (ssa_0) (base=0, range=120, dest_type=invalid /*256*/) vec1 32 con ssa_6 = u2f32 ssa_5.x vec1 32 con ssa_6 = u2f32 ssa_5.x vec1 32 con ssa_7 = u2f32 ssa_5.y vec1 32 con ssa_7 = u2f32 ssa_5.y vec1 32 con ssa_8 = fneg ssa_6 vec1 32 con ssa_8 = fneg ssa_6 vec1 32 div ssa_9 = fadd ssa_3, ssa_8 vec1 32 div ssa_9 = fadd ssa_3, ssa_8 vec1 32 con ssa_10 = fneg ssa_7 vec1 32 con ssa_10 = fneg ssa_7 vec1 32 div ssa_11 = fadd ssa_4, ssa_10 vec1 32 div ssa_11 = fadd ssa_4, ssa_10 vec1 32 con ssa_12 = u2f32 ssa_5.z vec1 32 con ssa_12 = u2f32 ssa_5.z vec1 32 con ssa_13 = u2f32 ssa_5.w vec1 32 con ssa_13 = u2f32 ssa_5.w vec1 32 con ssa_14 = frcp ssa_12 vec1 32 con ssa_14 = frcp ssa_12 vec1 32 div ssa_15 = fmul ssa_9, ssa_14 vec1 32 div ssa_15 = fmul ssa_9, ssa_14 vec1 32 con ssa_16 = frcp ssa_13 vec1 32 con ssa_16 = frcp ssa_13 vec1 32 div ssa_17 = fmul ssa_11, ssa_16 vec1 32 div ssa_17 = fmul ssa_11, ssa_16 vec1 32 div ssa_18 = intrinsic load_sample_id () () vec1 32 div ssa_18 = intrinsic load_sample_id () () vec1 32 con ssa_19 = load_const (0x00000001 = 0.000000) vec1 32 con ssa_19 = load_const (0x00000001 = 0.000000) vec1 32 div ssa_20 = iand ssa_18, ssa_19 vec1 32 div ssa_20 = iand ssa_18, ssa_19 vec1 32 div ssa_21 = ieq32 ssa_20, ssa_0 vec1 32 div ssa_21 = ieq32 ssa_20, ssa_0 /* succs: block_1 block_2 */ /* succs: block_1 block_2 */ if ssa_21 { if ssa_21 { block block_1: block block_1: /* preds: block_0 */ /* preds: block_0 */ vec1 32 con ssa_22 = load_const (0x00000010 = 0.000000) vec1 32 con ssa_22 = load_const (0x00000010 = 0.000000) vec4 32 con ssa_23 = intrinsic load_uniform (ssa_22) (base=0, range=120, dest_type=invalid /*256*/) vec4 32 con ssa_23 = intrinsic load_uniform (ssa_22) (base=0, range=120, dest_type=invalid /*256*/) vec1 32 div ssa_24 = fmul ssa_23.x, ssa_15 vec1 32 div ssa_24 = fmul ssa_23.x, ssa_15 vec1 32 div ssa_25 = fmul ssa_23.y, ssa_15 vec1 32 div ssa_25 = fmul ssa_23.y, ssa_15 vec1 32 div ssa_26 = fmul ssa_23.z, ssa_15 vec1 32 div ssa_26 = fmul ssa_23.z, ssa_15 vec1 32 div ssa_27 = fmul ssa_23.w, ssa_15 vec1 32 div ssa_27 = fmul ssa_23.w, ssa_15 vec1 32 con ssa_28 = load_const (0x00000030 = 0.000000) vec1 32 con ssa_28 = load_const (0x00000030 = 0.000000) vec4 32 con ssa_29 = intrinsic load_uniform (ssa_28) (base=0, range=120, dest_type=invalid /*256*/) vec4 32 con ssa_29 = intrinsic load_uniform (ssa_28) (base=0, range=120, dest_type=invalid /*256*/) vec1 32 div ssa_30 = fmul ssa_29.x, ssa_15 vec1 32 div ssa_30 = fmul ssa_29.x, ssa_15 vec1 32 div ssa_31 = fmul ssa_29.y, ssa_15 vec1 32 div ssa_31 = fmul ssa_29.y, ssa_15 vec1 32 div ssa_32 = fmul ssa_29.z, ssa_15 vec1 32 div ssa_32 = fmul ssa_29.z, ssa_15 vec1 32 div ssa_33 = fmul ssa_29.w, ssa_15 vec1 32 div ssa_33 = fmul ssa_29.w, ssa_15 vec1 32 con ssa_34 = load_const (0x00000070 = 0.000000) vec1 32 con ssa_34 = load_const (0x00000070 = 0.000000) vec1 32 con ssa_35 = intrinsic load_uniform (ssa_34) (base=0, range=120, dest_type=invalid /*256*/) vec1 32 con ssa_35 = intrinsic load_uniform (ssa_34) (base=0, range=120, dest_type=invalid /*256*/) /* succs: block_3 */ /* succs: block_3 */ } else { } else { block block_2: block block_2: /* preds: block_0 */ /* preds: block_0 */ vec1 32 con ssa_36 = load_const (0x00000020 = 0.000000) vec1 32 con ssa_36 = load_const (0x00000020 = 0.000000) vec4 32 con ssa_37 = intrinsic load_uniform (ssa_36) (base=0, range=120, dest_type=invalid /*256*/) vec4 32 con ssa_37 = intrinsic load_uniform (ssa_36) (base=0, range=120, dest_type=invalid /*256*/) vec1 32 div ssa_38 = fmul ssa_37.x, ssa_17 vec1 32 div ssa_38 = fmul ssa_37.x, ssa_17 vec1 32 div ssa_39 = fmul ssa_37.y, ssa_17 vec1 32 div ssa_39 = fmul ssa_37.y, ssa_17 vec1 32 div ssa_40 = fmul ssa_37.z, ssa_17 vec1 32 div ssa_40 = fmul ssa_37.z, ssa_17 vec1 32 div ssa_41 = fmul ssa_37.w, ssa_17 vec1 32 div ssa_41 = fmul ssa_37.w, ssa_17 vec1 32 con ssa_42 = load_const (0x00000040 = 0.000000) vec1 32 con ssa_42 = load_const (0x00000040 = 0.000000) vec4 32 con ssa_43 = intrinsic load_uniform (ssa_42) (base=0, range=120, dest_type=invalid /*256*/) vec4 32 con ssa_43 = intrinsic load_uniform (ssa_42) (base=0, range=120, dest_type=invalid /*256*/) vec1 32 div ssa_44 = fmul ssa_43.x, ssa_17 vec1 32 div ssa_44 = fmul ssa_43.x, ssa_17 vec1 32 div ssa_45 = fmul ssa_43.y, ssa_17 vec1 32 div ssa_45 = fmul ssa_43.y, ssa_17 vec1 32 div ssa_46 = fmul ssa_43.z, ssa_17 vec1 32 div ssa_46 = fmul ssa_43.z, ssa_17 vec1 32 div ssa_47 = fmul ssa_43.w, ssa_17 vec1 32 div ssa_47 = fmul ssa_43.w, ssa_17 vec1 32 con ssa_48 = load_const (0x00000074 = 0.000000) vec1 32 con ssa_48 = load_const (0x00000074 = 0.000000) vec1 32 con ssa_49 = intrinsic load_uniform (ssa_48) (base=0, range=120, dest_type=invalid /*256*/) vec1 32 con ssa_49 = intrinsic load_uniform (ssa_48) (base=0, range=120, dest_type=invalid /*256*/) /* succs: block_3 */ /* succs: block_3 */ } } block block_3: block block_3: /* preds: block_1 block_2 */ /* preds: block_1 block_2 */ vec1 32 div ssa_50 = phi block_1: ssa_35, block_2: ssa_49 vec1 32 div ssa_50 = phi block_1: ssa_35, block_2: ssa_49 vec1 32 div ssa_51 = phi block_1: ssa_30, block_2: ssa_44 vec1 32 div ssa_51 = phi block_1: ssa_30, block_2: ssa_44 vec1 32 div ssa_52 = phi block_1: ssa_31, block_2: ssa_45 vec1 32 div ssa_52 = phi block_1: ssa_31, block_2: ssa_45 vec1 32 div ssa_53 = phi block_1: ssa_32, block_2: ssa_46 vec1 32 div ssa_53 = phi block_1: ssa_32, block_2: ssa_46 vec1 32 div ssa_54 = phi block_1: ssa_33, block_2: ssa_47 vec1 32 div ssa_54 = phi block_1: ssa_33, block_2: ssa_47 vec1 32 div ssa_55 = phi block_1: ssa_24, block_2: ssa_38 vec1 32 div ssa_55 = phi block_1: ssa_24, block_2: ssa_38 vec1 32 div ssa_56 = phi block_1: ssa_25, block_2: ssa_39 vec1 32 div ssa_56 = phi block_1: ssa_25, block_2: ssa_39 vec1 32 div ssa_57 = phi block_1: ssa_26, block_2: ssa_40 vec1 32 div ssa_57 = phi block_1: ssa_26, block_2: ssa_40 vec1 32 div ssa_58 = phi block_1: ssa_27, block_2: ssa_41 vec1 32 div ssa_58 = phi block_1: ssa_27, block_2: ssa_41 vec4 32 div ssa_59 = vec4 ssa_55, ssa_56, ssa_57, ssa_58 vec4 32 div ssa_59 = vec4 ssa_55, ssa_56, ssa_57, ssa_58 vec4 32 div ssa_60 = vec4 ssa_51, ssa_52, ssa_53, ssa_54 vec4 32 div ssa_60 = vec4 ssa_51, ssa_52, ssa_53, ssa_54 intrinsic store_output (ssa_59, ssa_0) (base=8, wrmask=xyzw /*15*/, component=0, src_type=float32 /*160*/, io intrinsic store_output (ssa_59, ssa_0) (base=8, wrmask=xyzw /*15*/, component=0, src_type=float32 /*160*/, io intrinsic store_output (ssa_60, ssa_0) (base=14, wrmask=xyzw /*15*/, component=0, src_type=float32 /*160*/, i intrinsic store_output (ssa_60, ssa_0) (base=14, wrmask=xyzw /*15*/, component=0, src_type=float32 /*160*/, i intrinsic store_output (ssa_50, ssa_0) (base=0, wrmask=x /*1*/, component=0, src_type=float32 /*160*/, io loc intrinsic store_output (ssa_50, ssa_0) (base=0, wrmask=x /*1*/, component=0, src_type=float32 /*160*/, io loc /* succs: block_4 */ /* succs: block_4 */ block block_4: block block_4: } } NIR (final form) for fragment shader: NIR (final form) for fragment shader: shader: MESA_SHADER_FRAGMENT shader: MESA_SHADER_FRAGMENT source_sha1: {0xdd3ea721, 0x16552cc9, 0x83165d70, 0x5824ee3f, 0x1dadb651} source_sha1: {0xdd3ea721, 0x16552cc9, 0x83165d70, 0x5824ee3f, 0x1dadb651} stage: 4 stage: 4 next_stage: 0 next_stage: 0 outputs_written: 0,4,7 outputs_written: 0,4,7 system_values_read: 0x00000000'00000000'02880000 system_values_read: 0x00000000'00000000'02880000 subgroup_size: 2 subgroup_size: 2 divergence_analysis_run: true divergence_analysis_run: true bit_sizes_float: 0x20 bit_sizes_float: 0x20 bit_sizes_int: 0x21 bit_sizes_int: 0x21 separate_shader: true separate_shader: true uses_sample_shading: true uses_sample_shading: true origin_upper_left: true origin_upper_left: true depth_layout: 1 depth_layout: 1 inputs: 0 inputs: 0 outputs: 0 outputs: 0 uniforms: 120 uniforms: 120 decl_var push_const INTERP_MODE_NONE block @0 decl_var push_const INTERP_MODE_NONE block @0 decl_var shader_out INTERP_MODE_NONE vec4 @1 (FRAG_RESULT_DATA0.xyzw, 8, 0) decl_var shader_out INTERP_MODE_NONE vec4 @1 (FRAG_RESULT_DATA0.xyzw, 8, 0) decl_var shader_out INTERP_MODE_NONE vec4 @2 (FRAG_RESULT_DATA3.xyzw, 14, 0) decl_var shader_out INTERP_MODE_NONE vec4 @2 (FRAG_RESULT_DATA3.xyzw, 14, 0) decl_var shader_out INTERP_MODE_NONE float @3 (FRAG_RESULT_DEPTH.x, 0, 0) decl_var shader_out INTERP_MODE_NONE float @3 (FRAG_RESULT_DEPTH.x, 0, 0) decl_function main (0 params) decl_function main (0 params) impl main { impl main { decl_reg vec1 32 div r0 decl_reg vec1 32 div r0 decl_reg vec1 32 div r1 decl_reg vec1 32 div r1 decl_reg vec1 32 div r2 decl_reg vec1 32 div r2 decl_reg vec1 32 div r3 decl_reg vec1 32 div r3 decl_reg vec1 32 div r4 decl_reg vec1 32 div r4 decl_reg vec1 32 div r5 decl_reg vec1 32 div r5 decl_reg vec1 32 div r6 decl_reg vec1 32 div r6 decl_reg vec1 32 div r7 decl_reg vec1 32 div r7 decl_reg vec1 32 con r8 decl_reg vec1 32 con r8 decl_reg vec1 32 div r9 decl_reg vec1 32 div r9 decl_reg vec1 32 con r10 decl_reg vec1 32 con r10 block block_0: block block_0: /* preds: */ /* preds: */ vec1 32 con ssa_0 = load_const (0x00000000 = 0.000000) vec1 32 con ssa_0 = load_const (0x00000000 = 0.000000) vec4 32 div ssa_1 = intrinsic load_frag_coord () () vec4 32 div ssa_1 = intrinsic load_frag_coord () () vec2 32 div ssa_2 = intrinsic load_sample_pos_or_center () () vec2 32 div ssa_2 = intrinsic load_sample_pos_or_center () () vec1 32 div ssa_3 = fadd ssa_1.x, ssa_2.x vec1 32 div ssa_3 = fadd ssa_1.x, ssa_2.x vec1 32 div ssa_4 = fadd ssa_1.y, ssa_2.y vec1 32 div ssa_4 = fadd ssa_1.y, ssa_2.y vec4 32 con ssa_5 = intrinsic load_uniform (ssa_0) (base=0, range=120, dest_type=invalid /*256*/) vec4 32 con ssa_5 = intrinsic load_uniform (ssa_0) (base=0, range=120, dest_type=invalid /*256*/) vec1 32 con ssa_6 = u2f32 ssa_5.x vec1 32 con ssa_6 = u2f32 ssa_5.x vec1 32 con ssa_7 = u2f32 ssa_5.y vec1 32 con ssa_7 = u2f32 ssa_5.y vec1 32 con ssa_8 = fneg ssa_6 vec1 32 con ssa_8 = fneg ssa_6 vec1 32 div ssa_9 = fadd ssa_3, ssa_8 vec1 32 div ssa_9 = fadd ssa_3, ssa_8 vec1 32 con ssa_10 = fneg ssa_7 vec1 32 con ssa_10 = fneg ssa_7 vec1 32 div ssa_11 = fadd ssa_4, ssa_10 vec1 32 div ssa_11 = fadd ssa_4, ssa_10 vec1 32 con ssa_12 = u2f32 ssa_5.z vec1 32 con ssa_12 = u2f32 ssa_5.z vec1 32 con ssa_13 = u2f32 ssa_5.w vec1 32 con ssa_13 = u2f32 ssa_5.w vec1 32 con ssa_14 = frcp ssa_12 vec1 32 con ssa_14 = frcp ssa_12 vec1 32 div ssa_15 = fmul ssa_9, ssa_14 vec1 32 div ssa_15 = fmul ssa_9, ssa_14 vec1 32 con ssa_16 = frcp ssa_13 vec1 32 con ssa_16 = frcp ssa_13 vec1 32 div ssa_17 = fmul ssa_11, ssa_16 vec1 32 div ssa_17 = fmul ssa_11, ssa_16 vec1 32 div ssa_18 = intrinsic load_sample_id () () vec1 32 div ssa_18 = intrinsic load_sample_id () () vec1 32 con ssa_19 = load_const (0x00000001 = 0.000000) vec1 32 con ssa_19 = load_const (0x00000001 = 0.000000) vec1 32 div ssa_20 = iand ssa_18, ssa_19 vec1 32 div ssa_20 = iand ssa_18, ssa_19 vec1 32 div ssa_21 = ieq32 ssa_20, ssa_0 vec1 32 div ssa_21 = ieq32 ssa_20, ssa_0 /* succs: block_1 block_2 */ /* succs: block_1 block_2 */ if ssa_21 { if ssa_21 { block block_1: block block_1: /* preds: block_0 */ /* preds: block_0 */ vec1 32 con ssa_22 = load_const (0x00000010 = 0.000000) vec1 32 con ssa_22 = load_const (0x00000010 = 0.000000) vec4 32 con ssa_23 = intrinsic load_uniform (ssa_22) (base=0, range=120, dest_type=invalid /*256*/) vec4 32 con ssa_23 = intrinsic load_uniform (ssa_22) (base=0, range=120, dest_type=invalid /*256*/) div r0 = fmul ssa_23.x, ssa_15 div r0 = fmul ssa_23.x, ssa_15 div r1 = fmul ssa_23.y, ssa_15 div r1 = fmul ssa_23.y, ssa_15 div r2 = fmul ssa_23.z, ssa_15 div r2 = fmul ssa_23.z, ssa_15 div r3 = fmul ssa_23.w, ssa_15 div r3 = fmul ssa_23.w, ssa_15 vec1 32 con ssa_28 = load_const (0x00000030 = 0.000000) vec1 32 con ssa_28 = load_const (0x00000030 = 0.000000) vec4 32 con ssa_29 = intrinsic load_uniform (ssa_28) (base=0, range=120, dest_type=invalid /*256*/) vec4 32 con ssa_29 = intrinsic load_uniform (ssa_28) (base=0, range=120, dest_type=invalid /*256*/) div r4 = fmul ssa_29.x, ssa_15 div r4 = fmul ssa_29.x, ssa_15 div r5 = fmul ssa_29.y, ssa_15 div r5 = fmul ssa_29.y, ssa_15 div r6 = fmul ssa_29.z, ssa_15 div r6 = fmul ssa_29.z, ssa_15 div r7 = fmul ssa_29.w, ssa_15 div r7 = fmul ssa_29.w, ssa_15 vec1 32 con ssa_34 = load_const (0x00000070 = 0.000000) vec1 32 con ssa_34 = load_const (0x00000070 = 0.000000) con r8 = intrinsic load_uniform (ssa_34) (base=0, range=120, dest_type=invalid /*256*/) con r8 = intrinsic load_uniform (ssa_34) (base=0, range=120, dest_type=invalid /*256*/) div r9 = mov r8 div r9 = mov r8 /* succs: block_3 */ /* succs: block_3 */ } else { } else { block block_2: block block_2: /* preds: block_0 */ /* preds: block_0 */ vec1 32 con ssa_36 = load_const (0x00000020 = 0.000000) vec1 32 con ssa_36 = load_const (0x00000020 = 0.000000) vec4 32 con ssa_37 = intrinsic load_uniform (ssa_36) (base=0, range=120, dest_type=invalid /*256*/) vec4 32 con ssa_37 = intrinsic load_uniform (ssa_36) (base=0, range=120, dest_type=invalid /*256*/) div r0 = fmul ssa_37.x, ssa_17 div r0 = fmul ssa_37.x, ssa_17 div r1 = fmul ssa_37.y, ssa_17 div r1 = fmul ssa_37.y, ssa_17 div r2 = fmul ssa_37.z, ssa_17 div r2 = fmul ssa_37.z, ssa_17 div r3 = fmul ssa_37.w, ssa_17 div r3 = fmul ssa_37.w, ssa_17 vec1 32 con ssa_42 = load_const (0x00000040 = 0.000000) vec1 32 con ssa_42 = load_const (0x00000040 = 0.000000) vec4 32 con ssa_43 = intrinsic load_uniform (ssa_42) (base=0, range=120, dest_type=invalid /*256*/) vec4 32 con ssa_43 = intrinsic load_uniform (ssa_42) (base=0, range=120, dest_type=invalid /*256*/) div r4 = fmul ssa_43.x, ssa_17 div r4 = fmul ssa_43.x, ssa_17 div r5 = fmul ssa_43.y, ssa_17 div r5 = fmul ssa_43.y, ssa_17 div r6 = fmul ssa_43.z, ssa_17 div r6 = fmul ssa_43.z, ssa_17 div r7 = fmul ssa_43.w, ssa_17 div r7 = fmul ssa_43.w, ssa_17 vec1 32 con ssa_48 = load_const (0x00000074 = 0.000000) vec1 32 con ssa_48 = load_const (0x00000074 = 0.000000) con r10 = intrinsic load_uniform (ssa_48) (base=0, range=120, dest_type=invalid /*256*/) con r10 = intrinsic load_uniform (ssa_48) (base=0, range=120, dest_type=invalid /*256*/) div r9 = mov r10 div r9 = mov r10 /* succs: block_3 */ /* succs: block_3 */ } } block block_3: block block_3: /* preds: block_1 block_2 */ /* preds: block_1 block_2 */ vec4 32 div ssa_59 = vec4 r0, r1, r2, r3 vec4 32 div ssa_59 = vec4 r0, r1, r2, r3 vec4 32 div ssa_60 = vec4 r4, r5, r6, r7 vec4 32 div ssa_60 = vec4 r4, r5, r6, r7 intrinsic store_output (ssa_59, ssa_0) (base=8, wrmask=xyzw /*15*/, component=0, src_type=float32 /*160*/, io intrinsic store_output (ssa_59, ssa_0) (base=8, wrmask=xyzw /*15*/, component=0, src_type=float32 /*160*/, io intrinsic store_output (ssa_60, ssa_0) (base=14, wrmask=xyzw /*15*/, component=0, src_type=float32 /*160*/, i intrinsic store_output (ssa_60, ssa_0) (base=14, wrmask=xyzw /*15*/, component=0, src_type=float32 /*160*/, i intrinsic store_output (r9, ssa_0) (base=0, wrmask=x /*1*/, component=0, src_type=float32 /*160*/, io locatio intrinsic store_output (r9, ssa_0) (base=0, wrmask=x /*1*/, component=0, src_type=float32 /*160*/, io locatio /* succs: block_4 */ /* succs: block_4 */ block block_4: block block_4: } } Native code for unnamed fragment shader (null) (sha1 02054a36d7ae52bb7aa431e8c99602a4a922bfd6) Native code for unnamed fragment shader (null) (sha1 02054a36d7ae52bb7aa431e8c99602a4a922bfd6) SIMD8 shader: 52 instructions. 0 loops. 592 cycles. 0:0 spills:fills, 2 sends, scheduled with mode top-down. Promoted SIMD8 shader: 52 instructions. 0 loops. 592 cycles. 0:0 spills:fills, 2 sends, scheduled with mode top-down. Promoted START B0 (86 cycles) START B0 (86 cycles) add(16) g9<1>UW g1.4<2,8,0>UW 0x01000100V { align1 WE_all 1H }; add(16) g9<1>UW g1.4<2,8,0>UW 0x01000100V { align1 WE_all 1H }; add(16) g10<1>UW g1.5<2,8,0>UW 0x01010000V { align1 WE_all 1H }; add(16) g10<1>UW g1.5<2,8,0>UW 0x01010000V { align1 WE_all 1H }; mov(8) g12<1>D g4<16,8,2>B { align1 1Q }; mov(8) g12<1>D g4<16,8,2>B { align1 1Q }; mov(8) g14<1>D g4.1<16,8,2>B { align1 1Q }; mov(8) g14<1>D g4.1<16,8,2>B { align1 1Q }; shr(8) g17<1>UW g1<1,8,0>UB 0x44440000V { align1 1Q }; shr(8) g17<1>UW g1<1,8,0>UB 0x44440000V { align1 1Q }; mov(8) g20<1>F g5<0,1,0>UD { align1 1Q compacted }; mov(8) g20<1>F g5<0,1,0>UD { align1 1Q compacted }; mov(8) g21<1>F g5.1<0,1,0>UD { align1 1Q compacted }; mov(8) g21<1>F g5.1<0,1,0>UD { align1 1Q compacted }; mov(8) g24<1>F g5.2<0,1,0>UD { align1 1Q compacted }; mov(8) g24<1>F g5.2<0,1,0>UD { align1 1Q compacted }; mov(8) g25<1>F g5.3<0,1,0>UD { align1 1Q compacted }; mov(8) g25<1>F g5.3<0,1,0>UD { align1 1Q compacted }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@5 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@5 }; mov(8) g2<1>F g9<16,8,2>UW { align1 1Q }; mov(8) g2<1>F g9<16,8,2>UW { align1 1Q }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@4 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@4 }; mov(8) g3<1>F g10<16,8,2>UW { align1 1Q }; mov(8) g3<1>F g10<16,8,2>UW { align1 1Q }; mov(8) g13<1>F g12<1,1,0>D { align1 1Q I@3 compacted }; mov(8) g13<1>F g12<1,1,0>D { align1 1Q I@3 compacted }; mov(8) g15<1>F g14<1,1,0>D { align1 1Q I@2 compacted }; mov(8) g15<1>F g14<1,1,0>D { align1 1Q I@2 compacted }; and(8) g16<1>UD g17<8,8,1>UW 15W { align1 1Q I@1 }; and(8) g16<1>UD g17<8,8,1>UW 15W { align1 1Q I@1 }; math inv(8) g26<1>F g24<8,8,1>F null<8,8,1>F { align1 1Q @6 $0 }; math inv(8) g26<1>F g24<8,8,1>F null<8,8,1>F { align1 1Q @6 $0 }; math inv(8) g28<1>F g25<8,8,1>F null<8,8,1>F { align1 1Q @5 $1 }; math inv(8) g28<1>F g25<8,8,1>F null<8,8,1>F { align1 1Q @5 $1 }; mul(8) g30<1>F g13<1,1,0>F 0x3d800000F /* 0.0625F */ { align1 1Q F@2 compacted }; mul(8) g30<1>F g13<1,1,0>F 0x3d800000F /* 0.0625F */ { align1 1Q F@2 compacted }; mul(8) g11<1>F g15<1,1,0>F 0x3d800000F /* 0.0625F */ { align1 1Q F@2 compacted }; mul(8) g11<1>F g15<1,1,0>F 0x3d800000F /* 0.0625F */ { align1 1Q F@2 compacted }; and.z.f0.0(8) null<1>UD g16<8,8,1>UD 0x00000001UD { align1 1Q I@1 }; and.z.f0.0(8) null<1>UD g16<8,8,1>UD 0x00000001UD { align1 1Q I@1 }; add(8) g18<1>F g2<1,1,0>F g30<1,1,0>F { align1 1Q F@2 compacted }; add(8) g18<1>F g2<1,1,0>F g30<1,1,0>F { align1 1Q F@2 compacted }; add(8) g19<1>F g3<1,1,0>F g11<1,1,0>F { align1 1Q F@2 compacted }; add(8) g19<1>F g3<1,1,0>F g11<1,1,0>F { align1 1Q F@2 compacted }; add(8) g22<1>F g18<1,1,0>F -g20<1,1,0>F { align1 1Q F@2 compacted }; add(8) g22<1>F g18<1,1,0>F -g20<1,1,0>F { align1 1Q F@2 compacted }; add(8) g23<1>F g19<1,1,0>F -g21<1,1,0>F { align1 1Q F@2 compacted }; add(8) g23<1>F g19<1,1,0>F -g21<1,1,0>F { align1 1Q F@2 compacted }; mul(8) g27<1>F g22<1,1,0>F g26<1,1,0>F { align1 1Q @2 $0.dst compacted }; mul(8) g27<1>F g22<1,1,0>F g26<1,1,0>F { align1 1Q @2 $0.dst compacted }; mul(8) g29<1>F g23<1,1,0>F g28<1,1,0>F { align1 1Q @2 $1.dst compacted }; mul(8) g29<1>F g23<1,1,0>F g28<1,1,0>F { align1 1Q @2 $1.dst compacted }; (+f0.0) if(8) JIP: LABEL1 UIP: LABEL0 { align1 1Q }; (+f0.0) if(8) JIP: LABEL1 UIP: LABEL0 { align1 1Q }; END B0 ->B1 ->B2 END B0 ->B1 ->B2 START B1 <-B0 (26 cycles) START B1 <-B0 (26 cycles) mul(8) g31<1>F g5.4<0,1,0>F g27<1,1,0>F { align1 1Q F@2 compacted }; mul(8) g31<1>F g5.4<0,1,0>F g27<1,1,0>F { align1 1Q F@2 compacted }; mul(8) g32<1>F g5.5<0,1,0>F g27<1,1,0>F { align1 1Q compacted }; mul(8) g32<1>F g5.5<0,1,0>F g27<1,1,0>F { align1 1Q compacted }; mul(8) g33<1>F g5.6<0,1,0>F g27<1,1,0>F { align1 1Q compacted }; mul(8) g33<1>F g5.6<0,1,0>F g27<1,1,0>F { align1 1Q compacted }; mul(8) g34<1>F g5.7<0,1,0>F g27<1,1,0>F { align1 1Q compacted }; mul(8) g34<1>F g5.7<0,1,0>F g27<1,1,0>F { align1 1Q compacted }; mul(8) g123<1>F g6.4<0,1,0>F g27<1,1,0>F { align1 1Q compacted }; mul(8) g123<1>F g6.4<0,1,0>F g27<1,1,0>F { align1 1Q compacted }; mul(8) g124<1>F g6.5<0,1,0>F g27<1,1,0>F { align1 1Q compacted }; mul(8) g124<1>F g6.5<0,1,0>F g27<1,1,0>F { align1 1Q compacted }; mul(8) g125<1>F g6.6<0,1,0>F g27<1,1,0>F { align1 1Q compacted }; mul(8) g125<1>F g6.6<0,1,0>F g27<1,1,0>F { align1 1Q compacted }; mul(8) g126<1>F g6.7<0,1,0>F g27<1,1,0>F { align1 1Q compacted }; mul(8) g126<1>F g6.7<0,1,0>F g27<1,1,0>F { align1 1Q compacted }; mov(8) g122<1>UD g8.4<0,1,0>UD { align1 1Q }; mov(8) g122<1>UD g8.4<0,1,0>UD { align1 1Q }; else(8) JIP: LABEL0 UIP: LABEL0 { align1 1Q }; else(8) JIP: LABEL0 UIP: LABEL0 { align1 1Q }; END B1 ->B2 ->B3 END B1 ->B2 ->B3 START B2 <-B0 <-B1 (18 cycles) START B2 <-B0 <-B1 (18 cycles) LABEL1: LABEL1: mul(8) g31<1>F g6<0,1,0>F g29<1,1,0>F { align1 1Q F@1 compacted }; mul(8) g31<1>F g6<0,1,0>F g29<1,1,0>F { align1 1Q F@1 compacted }; mul(8) g32<1>F g6.1<0,1,0>F g29<1,1,0>F { align1 1Q F@7 compacted }; mul(8) g32<1>F g6.1<0,1,0>F g29<1,1,0>F { align1 1Q F@7 compacted }; mul(8) g33<1>F g6.2<0,1,0>F g29<1,1,0>F { align1 1Q F@7 compacted }; mul(8) g33<1>F g6.2<0,1,0>F g29<1,1,0>F { align1 1Q F@7 compacted }; mul(8) g34<1>F g6.3<0,1,0>F g29<1,1,0>F { align1 1Q F@7 compacted }; mul(8) g34<1>F g6.3<0,1,0>F g29<1,1,0>F { align1 1Q F@7 compacted }; mul(8) g123<1>F g7<0,1,0>F g29<1,1,0>F { align1 1Q F@7 compacted }; mul(8) g123<1>F g7<0,1,0>F g29<1,1,0>F { align1 1Q F@7 compacted }; mul(8) g124<1>F g7.1<0,1,0>F g29<1,1,0>F { align1 1Q F@7 compacted }; mul(8) g124<1>F g7.1<0,1,0>F g29<1,1,0>F { align1 1Q F@7 compacted }; mul(8) g125<1>F g7.2<0,1,0>F g29<1,1,0>F { align1 1Q F@7 compacted }; mul(8) g125<1>F g7.2<0,1,0>F g29<1,1,0>F { align1 1Q F@7 compacted }; mul(8) g126<1>F g7.3<0,1,0>F g29<1,1,0>F { align1 1Q F@7 compacted }; mul(8) g126<1>F g7.3<0,1,0>F g29<1,1,0>F { align1 1Q F@7 compacted }; mov(8) g122<1>UD g8.5<0,1,0>UD { align1 1Q I@2 }; mov(8) g122<1>UD g8.5<0,1,0>UD { align1 1Q I@2 }; END B2 ->B3 END B2 ->B3 START B3 <-B2 <-B1 (462 cycles) START B3 <-B2 <-B1 (462 cycles) LABEL0: LABEL0: endif(8) JIP: LABEL2 { align1 1Q }; endif(8) JIP: LABEL2 { align1 1Q }; LABEL2: LABEL2: sync nop(1) null<0,1,0>UB { align1 WE_all 1N A@2 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N A@2 }; sendc(8) nullUD g31UD g122UD 0x08030400 0x00000040 sendc(8) nullUD g31UD g122UD 0x08030400 0x00000040 render MsgDesc: RT write SIMD8 Surface = 0 mlen 4 ex_mlen 1 rlen 0 { align1 1Q $2 }; render MsgDesc: RT write SIMD8 Surface = 0 mlen 4 ex_mlen 1 rlen 0 { align1 1Q $2 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N $2.src }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N $2.src }; sendc(8) nullUD g123UD g122UD 0x08031403 0x00003040 sendc(8) nullUD g123UD g122UD 0x08031403 0x00003040 render MsgDesc: RT write SIMD8 LastRT Surface = 3 mlen 4 ex_mlen 1 rlen 0 { align1 1Q A@1 render MsgDesc: RT write SIMD8 LastRT Surface = 3 mlen 4 ex_mlen 1 rlen 0 { align1 1Q A@1 END B3 END B3 Native code for unnamed fragment shader (null) (sha1 b8dfca72218b0929a16d1d506a42353c6a57d653) Native code for unnamed fragment shader (null) (sha1 b8dfca72218b0929a16d1d506a42353c6a57d653) SIMD16 shader: 53 instructions. 0 loops. 1128 cycles. 0:0 spills:fills, 2 sends, scheduled with mode top-down. Promot SIMD16 shader: 53 instructions. 0 loops. 1128 cycles. 0:0 spills:fills, 2 sends, scheduled with mode top-down. Promot START B0 (136 cycles) START B0 (136 cycles) add(32) g11<1>UW g1.4<2,8,0>UW 0x01000100V { align1 WE_all }; add(32) g11<1>UW g1.4<2,8,0>UW 0x01000100V { align1 WE_all }; add(32) g13<1>UW g1.5<2,8,0>UW 0x01010000V { align1 WE_all }; add(32) g13<1>UW g1.5<2,8,0>UW 0x01010000V { align1 WE_all }; mov(16) g15<1>D g6<16,8,2>B { align1 1H }; mov(16) g15<1>D g6<16,8,2>B { align1 1H }; mov(16) g19<1>D g6.1<16,8,2>B { align1 1H }; mov(16) g19<1>D g6.1<16,8,2>B { align1 1H }; shr(16) g25<1>UW g1<1,8,0>UB 0x44440000V { align1 1H }; shr(16) g25<1>UW g1<1,8,0>UB 0x44440000V { align1 1H }; mov(16) g30<1>F g7<0,1,0>UD { align1 1H compacted }; mov(16) g30<1>F g7<0,1,0>UD { align1 1H compacted }; mov(16) g32<1>F g7.1<0,1,0>UD { align1 1H compacted }; mov(16) g32<1>F g7.1<0,1,0>UD { align1 1H compacted }; mov(16) g37<1>F g7.2<0,1,0>UD { align1 1H compacted }; mov(16) g37<1>F g7.2<0,1,0>UD { align1 1H compacted }; mov(16) g39<1>F g7.3<0,1,0>UD { align1 1H compacted }; mov(16) g39<1>F g7.3<0,1,0>UD { align1 1H compacted }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@5 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@5 }; mov(16) g2<1>F g11<16,8,2>UW { align1 1H }; mov(16) g2<1>F g11<16,8,2>UW { align1 1H }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@4 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@4 }; mov(16) g4<1>F g13<16,8,2>UW { align1 1H }; mov(16) g4<1>F g13<16,8,2>UW { align1 1H }; mov(16) g17<1>F g15<1,1,0>D { align1 1H I@3 compacted }; mov(16) g17<1>F g15<1,1,0>D { align1 1H I@3 compacted }; mov(16) g21<1>F g19<1,1,0>D { align1 1H I@2 compacted }; mov(16) g21<1>F g19<1,1,0>D { align1 1H I@2 compacted }; and(16) g23<1>UD g25<8,8,1>UW 15W { align1 1H I@1 }; and(16) g23<1>UD g25<8,8,1>UW 15W { align1 1H I@1 }; math inv(16) g41<1>F g37<8,8,1>F null<8,8,1>F { align1 1H @6 $0 }; math inv(16) g41<1>F g37<8,8,1>F null<8,8,1>F { align1 1H @6 $0 }; math inv(16) g45<1>F g39<8,8,1>F null<8,8,1>F { align1 1H @5 $1 }; math inv(16) g45<1>F g39<8,8,1>F null<8,8,1>F { align1 1H @5 $1 }; mul(16) g48<1>F g17<1,1,0>F 0x3d800000F /* 0.0625F */ { align1 1H F@2 compacted }; mul(16) g48<1>F g17<1,1,0>F 0x3d800000F /* 0.0625F */ { align1 1H F@2 compacted }; mul(16) g14<1>F g21<1,1,0>F 0x3d800000F /* 0.0625F */ { align1 1H F@2 compacted }; mul(16) g14<1>F g21<1,1,0>F 0x3d800000F /* 0.0625F */ { align1 1H F@2 compacted }; and.z.f0.0(16) null<1>UD g23<8,8,1>UD 0x00000001UD { align1 1H I@1 }; and.z.f0.0(16) null<1>UD g23<8,8,1>UD 0x00000001UD { align1 1H I@1 }; add(16) g26<1>F g2<1,1,0>F g48<1,1,0>F { align1 1H F@2 compacted }; add(16) g26<1>F g2<1,1,0>F g48<1,1,0>F { align1 1H F@2 compacted }; add(16) g28<1>F g4<1,1,0>F g14<1,1,0>F { align1 1H F@2 compacted }; add(16) g28<1>F g4<1,1,0>F g14<1,1,0>F { align1 1H F@2 compacted }; add(16) g34<1>F g26<1,1,0>F -g30<1,1,0>F { align1 1H F@2 compacted }; add(16) g34<1>F g26<1,1,0>F -g30<1,1,0>F { align1 1H F@2 compacted }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N $0.src }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N $0.src }; add(16) g36<1>F g28<1,1,0>F -g32<1,1,0>F { align1 1H F@2 compacted }; add(16) g36<1>F g28<1,1,0>F -g32<1,1,0>F { align1 1H F@2 compacted }; mul(16) g43<1>F g34<1,1,0>F g41<1,1,0>F { align1 1H @2 $0.dst compacted }; mul(16) g43<1>F g34<1,1,0>F g41<1,1,0>F { align1 1H @2 $0.dst compacted }; mul(16) g47<1>F g36<1,1,0>F g45<1,1,0>F { align1 1H @2 $1.dst compacted }; mul(16) g47<1>F g36<1,1,0>F g45<1,1,0>F { align1 1H @2 $1.dst compacted }; (+f0.0) if(16) JIP: LABEL1 UIP: LABEL0 { align1 1H }; (+f0.0) if(16) JIP: LABEL1 UIP: LABEL0 { align1 1H }; END B0 ->B1 ->B2 END B0 ->B1 ->B2 START B1 <-B0 (44 cycles) START B1 <-B0 (44 cycles) mul(16) g49<1>F g7.4<0,1,0>F g43<1,1,0>F { align1 1H F@2 compacted }; mul(16) g49<1>F g7.4<0,1,0>F g43<1,1,0>F { align1 1H F@2 compacted }; mul(16) g51<1>F g7.5<0,1,0>F g43<1,1,0>F { align1 1H compacted }; mul(16) g51<1>F g7.5<0,1,0>F g43<1,1,0>F { align1 1H compacted }; mul(16) g53<1>F g7.6<0,1,0>F g43<1,1,0>F { align1 1H compacted }; mul(16) g53<1>F g7.6<0,1,0>F g43<1,1,0>F { align1 1H compacted }; mul(16) g55<1>F g7.7<0,1,0>F g43<1,1,0>F { align1 1H compacted }; mul(16) g55<1>F g7.7<0,1,0>F g43<1,1,0>F { align1 1H compacted }; mul(16) g119<1>F g8.4<0,1,0>F g43<1,1,0>F { align1 1H compacted }; mul(16) g119<1>F g8.4<0,1,0>F g43<1,1,0>F { align1 1H compacted }; mul(16) g121<1>F g8.5<0,1,0>F g43<1,1,0>F { align1 1H compacted }; mul(16) g121<1>F g8.5<0,1,0>F g43<1,1,0>F { align1 1H compacted }; mul(16) g123<1>F g8.6<0,1,0>F g43<1,1,0>F { align1 1H compacted }; mul(16) g123<1>F g8.6<0,1,0>F g43<1,1,0>F { align1 1H compacted }; mul(16) g125<1>F g8.7<0,1,0>F g43<1,1,0>F { align1 1H compacted }; mul(16) g125<1>F g8.7<0,1,0>F g43<1,1,0>F { align1 1H compacted }; mov(16) g117<1>UD g10.4<0,1,0>UD { align1 1H }; mov(16) g117<1>UD g10.4<0,1,0>UD { align1 1H }; else(16) JIP: LABEL0 UIP: LABEL0 { align1 1H }; else(16) JIP: LABEL0 UIP: LABEL0 { align1 1H }; END B1 ->B2 ->B3 END B1 ->B2 ->B3 START B2 <-B0 <-B1 (36 cycles) START B2 <-B0 <-B1 (36 cycles) LABEL1: LABEL1: mul(16) g49<1>F g8<0,1,0>F g47<1,1,0>F { align1 1H F@1 compacted }; mul(16) g49<1>F g8<0,1,0>F g47<1,1,0>F { align1 1H F@1 compacted }; mul(16) g51<1>F g8.1<0,1,0>F g47<1,1,0>F { align1 1H F@7 compacted }; mul(16) g51<1>F g8.1<0,1,0>F g47<1,1,0>F { align1 1H F@7 compacted }; mul(16) g53<1>F g8.2<0,1,0>F g47<1,1,0>F { align1 1H F@7 compacted }; mul(16) g53<1>F g8.2<0,1,0>F g47<1,1,0>F { align1 1H F@7 compacted }; mul(16) g55<1>F g8.3<0,1,0>F g47<1,1,0>F { align1 1H F@7 compacted }; mul(16) g55<1>F g8.3<0,1,0>F g47<1,1,0>F { align1 1H F@7 compacted }; mul(16) g119<1>F g9<0,1,0>F g47<1,1,0>F { align1 1H F@7 compacted }; mul(16) g119<1>F g9<0,1,0>F g47<1,1,0>F { align1 1H F@7 compacted }; mul(16) g121<1>F g9.1<0,1,0>F g47<1,1,0>F { align1 1H F@7 compacted }; mul(16) g121<1>F g9.1<0,1,0>F g47<1,1,0>F { align1 1H F@7 compacted }; mul(16) g123<1>F g9.2<0,1,0>F g47<1,1,0>F { align1 1H F@7 compacted }; mul(16) g123<1>F g9.2<0,1,0>F g47<1,1,0>F { align1 1H F@7 compacted }; mul(16) g125<1>F g9.3<0,1,0>F g47<1,1,0>F { align1 1H F@7 compacted }; mul(16) g125<1>F g9.3<0,1,0>F g47<1,1,0>F { align1 1H F@7 compacted }; mov(16) g117<1>UD g10.5<0,1,0>UD { align1 1H I@2 }; mov(16) g117<1>UD g10.5<0,1,0>UD { align1 1H I@2 }; END B2 ->B3 END B2 ->B3 START B3 <-B2 <-B1 (912 cycles) START B3 <-B2 <-B1 (912 cycles) LABEL0: LABEL0: endif(16) JIP: LABEL2 { align1 1H }; endif(16) JIP: LABEL2 { align1 1H }; LABEL2: LABEL2: sync nop(1) null<0,1,0>UB { align1 WE_all 1N A@2 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N A@2 }; sendc(16) nullUD g49UD g117UD 0x10030000 0x00000080 sendc(16) nullUD g49UD g117UD 0x10030000 0x00000080 render MsgDesc: RT write SIMD16 Surface = 0 mlen 8 ex_mlen 2 rlen 0 { align1 1H $2 }; render MsgDesc: RT write SIMD16 Surface = 0 mlen 8 ex_mlen 2 rlen 0 { align1 1H $2 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N $2.src }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N $2.src }; sendc(16) nullUD g119UD g117UD 0x10031003 0x00003080 sendc(16) nullUD g119UD g117UD 0x10031003 0x00003080 render MsgDesc: RT write SIMD16 LastRT Surface = 3 mlen 8 ex_mlen 2 rlen 0 { align1 1H A@ render MsgDesc: RT write SIMD16 LastRT Surface = 3 mlen 8 ex_mlen 2 rlen 0 { align1 1H A@ END B3 END B3 Native code for unnamed fragment shader (null) (sha1 36e02da164f8fba34e02524e8e0a1658400204f2) Native code for unnamed fragment shader (null) (sha1 36e02da164f8fba34e02524e8e0a1658400204f2) SIMD32 shader: 107 instructions. 0 loops. 3106 cycles. 0:0 spills:fills, 4 sends, scheduled with mode top-down. Promo SIMD32 shader: 107 instructions. 0 loops. 3106 cycles. 0:0 spills:fills, 4 sends, scheduled with mode top-down. Promo START B0 (242 cycles) START B0 (242 cycles) add(32) g5<1>UW g1.4<2,8,0>UW 0x01000100V { align1 WE_all }; add(32) g5<1>UW g1.4<2,8,0>UW 0x01000100V { align1 WE_all }; add(32) g8<1>UW g1.5<2,8,0>UW 0x01010000V { align1 WE_all }; add(32) g8<1>UW g1.5<2,8,0>UW 0x01010000V { align1 WE_all }; add(32) g10<1>UW g2.4<2,8,0>UW 0x01000100V { align1 WE_all }; add(32) g10<1>UW g2.4<2,8,0>UW 0x01000100V { align1 WE_all }; add(32) g17<1>UW g2.5<2,8,0>UW 0x01010000V { align1 WE_all }; add(32) g17<1>UW g2.5<2,8,0>UW 0x01010000V { align1 WE_all }; mov(16) g76<1>W g7<8,8,1>W { align1 WE_all 1H }; mov(16) g76<1>W g7<8,8,1>W { align1 WE_all 1H }; mov(16) g19<1>W g12<8,8,1>W { align1 WE_all 1H }; mov(16) g19<1>W g12<8,8,1>W { align1 WE_all 1H }; shr(16) g87<1>UW g1<1,8,0>UB 0x44440000V { align1 1H }; shr(16) g87<1>UW g1<1,8,0>UB 0x44440000V { align1 1H }; shr(16) g30<1>UW g2<1,8,0>UB 0x44440000V { align1 2H }; shr(16) g30<1>UW g2<1,8,0>UB 0x44440000V { align1 2H }; mov(16) g93<1>F g13<0,1,0>UD { align1 1H compacted }; mov(16) g93<1>F g13<0,1,0>UD { align1 1H compacted }; mov(16) g35<1>F g13<0,1,0>UD { align1 2H compacted }; mov(16) g35<1>F g13<0,1,0>UD { align1 2H compacted }; mov(16) g95<1>F g13.1<0,1,0>UD { align1 1H compacted }; mov(16) g95<1>F g13.1<0,1,0>UD { align1 1H compacted }; mov(16) g37<1>F g13.1<0,1,0>UD { align1 2H compacted }; mov(16) g37<1>F g13.1<0,1,0>UD { align1 2H compacted }; mov(16) g100<1>F g13.2<0,1,0>UD { align1 1H compacted }; mov(16) g100<1>F g13.2<0,1,0>UD { align1 1H compacted }; mov(16) g42<1>F g13.2<0,1,0>UD { align1 2H compacted }; mov(16) g42<1>F g13.2<0,1,0>UD { align1 2H compacted }; mov(16) g102<1>F g13.3<0,1,0>UD { align1 1H compacted }; mov(16) g102<1>F g13.3<0,1,0>UD { align1 1H compacted }; mov(16) g44<1>F g13.3<0,1,0>UD { align1 2H compacted }; mov(16) g44<1>F g13.3<0,1,0>UD { align1 2H compacted }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@7 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@7 }; mov(16) g71<1>F g5<16,8,2>UW { align1 1H }; mov(16) g71<1>F g5<16,8,2>UW { align1 1H }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@7 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@7 }; mov(16) g73<1>F g8<16,8,2>UW { align1 1H }; mov(16) g73<1>F g8<16,8,2>UW { align1 1H }; sync nop(1) null<0,1,0>UB { align1 WE_all 5N I@1 }; sync nop(1) null<0,1,0>UB { align1 WE_all 5N I@1 }; mov(16) g2<1>F g10<16,8,2>UW { align1 2H }; mov(16) g2<1>F g10<16,8,2>UW { align1 2H }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@4 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@4 }; mov(16) g77<1>D g76<16,8,2>B { align1 1H }; mov(16) g77<1>D g76<16,8,2>B { align1 1H }; mov(16) g81<1>D g76.1<16,8,2>B { align1 1H }; mov(16) g81<1>D g76.1<16,8,2>B { align1 1H }; sync nop(1) null<0,1,0>UB { align1 WE_all 5N I@5 }; sync nop(1) null<0,1,0>UB { align1 WE_all 5N I@5 }; mov(16) g20<1>D g19<16,8,2>B { align1 2H }; mov(16) g20<1>D g19<16,8,2>B { align1 2H }; mov(16) g24<1>D g19.1<16,8,2>B { align1 2H }; mov(16) g24<1>D g19.1<16,8,2>B { align1 2H }; and(16) g85<1>UD g87<8,8,1>UW 15W { align1 1H I@6 }; and(16) g85<1>UD g87<8,8,1>UW 15W { align1 1H I@6 }; and(16) g28<1>UD g30<8,8,1>UW 15W { align1 2H I@6 }; and(16) g28<1>UD g30<8,8,1>UW 15W { align1 2H I@6 }; math inv(16) g104<1>F g100<8,8,1>F null<8,8,1>F { align1 1H @7 $0 }; math inv(16) g104<1>F g100<8,8,1>F null<8,8,1>F { align1 1H @7 $0 }; mov(16) g4<1>F g17<16,8,2>UW { align1 2H }; mov(16) g4<1>F g17<16,8,2>UW { align1 2H }; math inv(16) g46<1>F g42<8,8,1>F null<8,8,1>F { align1 2H @7 $1 }; math inv(16) g46<1>F g42<8,8,1>F null<8,8,1>F { align1 2H @7 $1 }; math inv(16) g108<1>F g102<8,8,1>F null<8,8,1>F { align1 1H @6 $2 }; math inv(16) g108<1>F g102<8,8,1>F null<8,8,1>F { align1 1H @6 $2 }; math inv(16) g50<1>F g44<8,8,1>F null<8,8,1>F { align1 2H @5 $3 }; math inv(16) g50<1>F g44<8,8,1>F null<8,8,1>F { align1 2H @5 $3 }; mov(16) g79<1>F g77<1,1,0>D { align1 1H I@6 compacted }; mov(16) g79<1>F g77<1,1,0>D { align1 1H I@6 compacted }; mov(16) g83<1>F g81<1,1,0>D { align1 1H I@5 compacted }; mov(16) g83<1>F g81<1,1,0>D { align1 1H I@5 compacted }; mov(16) g22<1>F g20<1,1,0>D { align1 2H I@4 compacted }; mov(16) g22<1>F g20<1,1,0>D { align1 2H I@4 compacted }; mov(16) g26<1>F g24<1,1,0>D { align1 2H I@3 compacted }; mov(16) g26<1>F g24<1,1,0>D { align1 2H I@3 compacted }; and.z.f0.0(16) null<1>UD g85<8,8,1>UD 0x00000001UD { align1 1H I@2 }; and.z.f0.0(16) null<1>UD g85<8,8,1>UD 0x00000001UD { align1 1H I@2 }; and.z.f0.0(16) null<1>UD g28<8,8,1>UD 0x00000001UD { align1 2H I@2 }; and.z.f0.0(16) null<1>UD g28<8,8,1>UD 0x00000001UD { align1 2H I@2 }; mul(16) g111<1>F g79<1,1,0>F 0x3d800000F /* 0.0625F */ { align1 1H F@4 compacted }; mul(16) g111<1>F g79<1,1,0>F 0x3d800000F /* 0.0625F */ { align1 1H F@4 compacted }; mul(16) g75<1>F g83<1,1,0>F 0x3d800000F /* 0.0625F */ { align1 1H A@4 compacted }; mul(16) g75<1>F g83<1,1,0>F 0x3d800000F /* 0.0625F */ { align1 1H A@4 compacted }; mul(16) g53<1>F g22<1,1,0>F 0x3d800000F /* 0.0625F */ { align1 2H F@4 compacted }; mul(16) g53<1>F g22<1,1,0>F 0x3d800000F /* 0.0625F */ { align1 2H F@4 compacted }; mul(16) g18<1>F g26<1,1,0>F 0x3d800000F /* 0.0625F */ { align1 2H A@4 compacted }; mul(16) g18<1>F g26<1,1,0>F 0x3d800000F /* 0.0625F */ { align1 2H A@4 compacted }; add(16) g89<1>F g71<1,1,0>F g111<1,1,0>F { align1 1H F@4 compacted }; add(16) g89<1>F g71<1,1,0>F g111<1,1,0>F { align1 1H F@4 compacted }; add(16) g91<1>F g73<1,1,0>F g75<1,1,0>F { align1 1H F@4 compacted }; add(16) g91<1>F g73<1,1,0>F g75<1,1,0>F { align1 1H F@4 compacted }; add(16) g31<1>F g2<1,1,0>F g53<1,1,0>F { align1 2H F@4 compacted }; add(16) g31<1>F g2<1,1,0>F g53<1,1,0>F { align1 2H F@4 compacted }; add(16) g33<1>F g4<1,1,0>F g18<1,1,0>F { align1 2H F@4 compacted }; add(16) g33<1>F g4<1,1,0>F g18<1,1,0>F { align1 2H F@4 compacted }; add(16) g97<1>F g89<1,1,0>F -g93<1,1,0>F { align1 1H F@4 compacted }; add(16) g97<1>F g89<1,1,0>F -g93<1,1,0>F { align1 1H F@4 compacted }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N $0.src }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N $0.src }; add(16) g99<1>F g91<1,1,0>F -g95<1,1,0>F { align1 1H F@4 compacted }; add(16) g99<1>F g91<1,1,0>F -g95<1,1,0>F { align1 1H F@4 compacted }; add(16) g39<1>F g31<1,1,0>F -g35<1,1,0>F { align1 2H F@4 compacted }; add(16) g39<1>F g31<1,1,0>F -g35<1,1,0>F { align1 2H F@4 compacted }; sync nop(1) null<0,1,0>UB { align1 WE_all 5N $1.src }; sync nop(1) null<0,1,0>UB { align1 WE_all 5N $1.src }; add(16) g41<1>F g33<1,1,0>F -g37<1,1,0>F { align1 2H F@4 compacted }; add(16) g41<1>F g33<1,1,0>F -g37<1,1,0>F { align1 2H F@4 compacted }; mul(16) g106<1>F g97<1,1,0>F g104<1,1,0>F { align1 1H @4 $0.dst compacted }; mul(16) g106<1>F g97<1,1,0>F g104<1,1,0>F { align1 1H @4 $0.dst compacted }; mul(16) g110<1>F g99<1,1,0>F g108<1,1,0>F { align1 1H @4 $2.dst compacted }; mul(16) g110<1>F g99<1,1,0>F g108<1,1,0>F { align1 1H @4 $2.dst compacted }; mul(16) g48<1>F g39<1,1,0>F g46<1,1,0>F { align1 2H @4 $1.dst compacted }; mul(16) g48<1>F g39<1,1,0>F g46<1,1,0>F { align1 2H @4 $1.dst compacted }; mul(16) g52<1>F g41<1,1,0>F g50<1,1,0>F { align1 2H @4 $3.dst compacted }; mul(16) g52<1>F g41<1,1,0>F g50<1,1,0>F { align1 2H @4 $3.dst compacted }; (+f0.0) if(32) JIP: LABEL1 UIP: LABEL0 { align1 }; (+f0.0) if(32) JIP: LABEL1 UIP: LABEL0 { align1 }; END B0 ->B1 ->B2 END B0 ->B1 ->B2 START B1 <-B0 (80 cycles) START B1 <-B0 (80 cycles) mul(16) g54<1>F g13.4<0,1,0>F g106<1,1,0>F { align1 1H F@4 compacted }; mul(16) g54<1>F g13.4<0,1,0>F g106<1,1,0>F { align1 1H F@4 compacted }; mul(16) g62<1>F g13.4<0,1,0>F g48<1,1,0>F { align1 2H F@3 compacted }; mul(16) g62<1>F g13.4<0,1,0>F g48<1,1,0>F { align1 2H F@3 compacted }; mul(16) g56<1>F g13.5<0,1,0>F g106<1,1,0>F { align1 1H compacted }; mul(16) g56<1>F g13.5<0,1,0>F g106<1,1,0>F { align1 1H compacted }; mul(16) g64<1>F g13.5<0,1,0>F g48<1,1,0>F { align1 2H compacted }; mul(16) g64<1>F g13.5<0,1,0>F g48<1,1,0>F { align1 2H compacted }; mul(16) g58<1>F g13.6<0,1,0>F g106<1,1,0>F { align1 1H compacted }; mul(16) g58<1>F g13.6<0,1,0>F g106<1,1,0>F { align1 1H compacted }; mul(16) g66<1>F g13.6<0,1,0>F g48<1,1,0>F { align1 2H compacted }; mul(16) g66<1>F g13.6<0,1,0>F g48<1,1,0>F { align1 2H compacted }; mul(16) g60<1>F g13.7<0,1,0>F g106<1,1,0>F { align1 1H compacted }; mul(16) g60<1>F g13.7<0,1,0>F g106<1,1,0>F { align1 1H compacted }; mul(16) g68<1>F g13.7<0,1,0>F g48<1,1,0>F { align1 2H compacted }; mul(16) g68<1>F g13.7<0,1,0>F g48<1,1,0>F { align1 2H compacted }; mul(16) g70<1>F g14.4<0,1,0>F g106<1,1,0>F { align1 1H compacted }; mul(16) g70<1>F g14.4<0,1,0>F g106<1,1,0>F { align1 1H compacted }; mul(16) g119<1>F g14.4<0,1,0>F g48<1,1,0>F { align1 2H compacted }; mul(16) g119<1>F g14.4<0,1,0>F g48<1,1,0>F { align1 2H compacted }; mul(16) g72<1>F g14.5<0,1,0>F g106<1,1,0>F { align1 1H compacted }; mul(16) g72<1>F g14.5<0,1,0>F g106<1,1,0>F { align1 1H compacted }; mul(16) g121<1>F g14.5<0,1,0>F g48<1,1,0>F { align1 2H compacted }; mul(16) g121<1>F g14.5<0,1,0>F g48<1,1,0>F { align1 2H compacted }; mul(16) g74<1>F g14.6<0,1,0>F g106<1,1,0>F { align1 1H compacted }; mul(16) g74<1>F g14.6<0,1,0>F g106<1,1,0>F { align1 1H compacted }; mul(16) g123<1>F g14.6<0,1,0>F g48<1,1,0>F { align1 2H compacted }; mul(16) g123<1>F g14.6<0,1,0>F g48<1,1,0>F { align1 2H compacted }; mul(16) g76<1>F g14.7<0,1,0>F g106<1,1,0>F { align1 1H compacted }; mul(16) g76<1>F g14.7<0,1,0>F g106<1,1,0>F { align1 1H compacted }; mul(16) g125<1>F g14.7<0,1,0>F g48<1,1,0>F { align1 2H compacted }; mul(16) g125<1>F g14.7<0,1,0>F g48<1,1,0>F { align1 2H compacted }; mov(16) g88<1>UD g16.4<0,1,0>UD { align1 1H }; mov(16) g88<1>UD g16.4<0,1,0>UD { align1 1H }; mov(16) g117<1>UD g16.4<0,1,0>UD { align1 2H }; mov(16) g117<1>UD g16.4<0,1,0>UD { align1 2H }; else(32) JIP: LABEL0 UIP: LABEL0 { align1 }; else(32) JIP: LABEL0 UIP: LABEL0 { align1 }; END B1 ->B2 ->B3 END B1 ->B2 ->B3 START B2 <-B0 <-B1 (72 cycles) START B2 <-B0 <-B1 (72 cycles) LABEL1: LABEL1: mul(16) g54<1>F g14<0,1,0>F g110<1,1,0>F { align1 1H F@3 compacted }; mul(16) g54<1>F g14<0,1,0>F g110<1,1,0>F { align1 1H F@3 compacted }; mul(16) g62<1>F g14<0,1,0>F g52<1,1,0>F { align1 2H F@2 compacted }; mul(16) g62<1>F g14<0,1,0>F g52<1,1,0>F { align1 2H F@2 compacted }; mul(16) g56<1>F g14.1<0,1,0>F g110<1,1,0>F { align1 1H compacted }; mul(16) g56<1>F g14.1<0,1,0>F g110<1,1,0>F { align1 1H compacted }; mul(16) g64<1>F g14.1<0,1,0>F g52<1,1,0>F { align1 2H compacted }; mul(16) g64<1>F g14.1<0,1,0>F g52<1,1,0>F { align1 2H compacted }; mul(16) g58<1>F g14.2<0,1,0>F g110<1,1,0>F { align1 1H compacted }; mul(16) g58<1>F g14.2<0,1,0>F g110<1,1,0>F { align1 1H compacted }; mul(16) g66<1>F g14.2<0,1,0>F g52<1,1,0>F { align1 2H compacted }; mul(16) g66<1>F g14.2<0,1,0>F g52<1,1,0>F { align1 2H compacted }; mul(16) g60<1>F g14.3<0,1,0>F g110<1,1,0>F { align1 1H compacted }; mul(16) g60<1>F g14.3<0,1,0>F g110<1,1,0>F { align1 1H compacted }; mul(16) g68<1>F g14.3<0,1,0>F g52<1,1,0>F { align1 2H compacted }; mul(16) g68<1>F g14.3<0,1,0>F g52<1,1,0>F { align1 2H compacted }; mul(16) g70<1>F g15<0,1,0>F g110<1,1,0>F { align1 1H compacted }; mul(16) g70<1>F g15<0,1,0>F g110<1,1,0>F { align1 1H compacted }; mul(16) g119<1>F g15<0,1,0>F g52<1,1,0>F { align1 2H compacted }; mul(16) g119<1>F g15<0,1,0>F g52<1,1,0>F { align1 2H compacted }; mul(16) g72<1>F g15.1<0,1,0>F g110<1,1,0>F { align1 1H compacted }; mul(16) g72<1>F g15.1<0,1,0>F g110<1,1,0>F { align1 1H compacted }; mul(16) g121<1>F g15.1<0,1,0>F g52<1,1,0>F { align1 2H compacted }; mul(16) g121<1>F g15.1<0,1,0>F g52<1,1,0>F { align1 2H compacted }; mul(16) g74<1>F g15.2<0,1,0>F g110<1,1,0>F { align1 1H compacted }; mul(16) g74<1>F g15.2<0,1,0>F g110<1,1,0>F { align1 1H compacted }; mul(16) g123<1>F g15.2<0,1,0>F g52<1,1,0>F { align1 2H compacted }; mul(16) g123<1>F g15.2<0,1,0>F g52<1,1,0>F { align1 2H compacted }; mul(16) g76<1>F g15.3<0,1,0>F g110<1,1,0>F { align1 1H compacted }; mul(16) g76<1>F g15.3<0,1,0>F g110<1,1,0>F { align1 1H compacted }; mul(16) g125<1>F g15.3<0,1,0>F g52<1,1,0>F { align1 2H compacted }; mul(16) g125<1>F g15.3<0,1,0>F g52<1,1,0>F { align1 2H compacted }; mov(16) g88<1>UD g16.5<0,1,0>UD { align1 1H I@3 }; mov(16) g88<1>UD g16.5<0,1,0>UD { align1 1H I@3 }; mov(16) g117<1>UD g16.5<0,1,0>UD { align1 2H I@3 }; mov(16) g117<1>UD g16.5<0,1,0>UD { align1 2H I@3 }; END B2 ->B3 END B2 ->B3 START B3 <-B2 <-B1 (2712 cycles) START B3 <-B2 <-B1 (2712 cycles) LABEL0: LABEL0: endif(32) JIP: LABEL2 { align1 }; endif(32) JIP: LABEL2 { align1 }; LABEL2: LABEL2: sync nop(1) null<0,1,0>UB { align1 WE_all 1N A@3 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N A@3 }; sendc(16) nullUD g54UD g88UD 0x10030000 0x00000080 sendc(16) nullUD g54UD g88UD 0x10030000 0x00000080 render MsgDesc: RT write SIMD16 Surface = 0 mlen 8 ex_mlen 2 rlen 0 { align1 1H $4 }; render MsgDesc: RT write SIMD16 Surface = 0 mlen 8 ex_mlen 2 rlen 0 { align1 1H $4 }; sync nop(1) null<0,1,0>UB { align1 WE_all 5N A@2 }; sync nop(1) null<0,1,0>UB { align1 WE_all 5N A@2 }; sendc(16) nullUD g62UD g117UD 0x10030800 0x00000080 sendc(16) nullUD g62UD g117UD 0x10030800 0x00000080 render MsgDesc: RT write SIMD16 Hi Surface = 0 mlen 8 ex_mlen 2 rlen 0 { align1 2H $5 }; render MsgDesc: RT write SIMD16 Hi Surface = 0 mlen 8 ex_mlen 2 rlen 0 { align1 2H $5 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N $4.src }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N $4.src }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N F@2 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N F@2 }; sendc(16) nullUD g70UD g88UD 0x10031003 0x00003080 sendc(16) nullUD g70UD g88UD 0x10031003 0x00003080 render MsgDesc: RT write SIMD16 LastRT Surface = 3 mlen 8 ex_mlen 2 rlen 0 { align1 1H $6 render MsgDesc: RT write SIMD16 LastRT Surface = 3 mlen 8 ex_mlen 2 rlen 0 { align1 1H $6 sync nop(1) null<0,1,0>UB { align1 WE_all 5N $5.src }; sync nop(1) null<0,1,0>UB { align1 WE_all 5N $5.src }; sendc(16) nullUD g119UD g117UD 0x10031803 0x00003080 sendc(16) nullUD g119UD g117UD 0x10031803 0x00003080 render MsgDesc: RT write SIMD16 Hi LastRT Surface = 3 mlen 8 ex_mlen 2 rlen 0 { align1 2H render MsgDesc: RT write SIMD16 Hi LastRT Surface = 3 mlen 8 ex_mlen 2 rlen 0 { align1 2H END B3 END B3 NIR (from SPIR-V) for MESA_SHADER_COMPUTE shader: NIR (from SPIR-V) for MESA_SHADER_COMPUTE shader: shader: MESA_SHADER_COMPUTE shader: MESA_SHADER_COMPUTE source_sha1: {0x4080c608, 0xef4e4e6b, 0x82f838bb, 0x041ba6fe, 0x4a36e587} source_sha1: {0x4080c608, 0xef4e4e6b, 0x82f838bb, 0x041ba6fe, 0x4a36e587} workgroup-size: 8, 8, 1 workgroup-size: 8, 8, 1 shared-size: 0 shared-size: 0 stage: 5 stage: 5 next_stage: 0 next_stage: 0 num_ssbos: 1 num_ssbos: 1 subgroup_size: 2 subgroup_size: 2 ptr_size: 0 ptr_size: 0 inputs: 0 inputs: 0 outputs: 0 outputs: 0 uniforms: 120 uniforms: 120 decl_var system INTERP_MODE_NONE uvec3 @0 decl_var system INTERP_MODE_NONE uvec3 @0 decl_var push_const INTERP_MODE_NONE block @1 decl_var push_const INTERP_MODE_NONE block @1 decl_var uniform INTERP_MODE_NONE restrict texture2D @2 (~0, 0, 1) decl_var uniform INTERP_MODE_NONE restrict texture2D @2 (~0, 0, 1) decl_var ssbo INTERP_MODE_NONE restrict writeonly block @3 (~0, 0, 0) decl_var ssbo INTERP_MODE_NONE restrict writeonly block @3 (~0, 0, 0) decl_var image INTERP_MODE_NONE restrict writeonly r8g8b8a8_unorm image2DArray @4 (~0, 0, 6) decl_var image INTERP_MODE_NONE restrict writeonly r8g8b8a8_unorm image2DArray @4 (~0, 0, 6) decl_var uniform INTERP_MODE_NONE restrict texture2D @5 (~0, 0, 2) decl_var uniform INTERP_MODE_NONE restrict texture2D @5 (~0, 0, 2) decl_var uniform INTERP_MODE_NONE restrict itexture2D @6 (~0, 0, 3) decl_var uniform INTERP_MODE_NONE restrict itexture2D @6 (~0, 0, 3) decl_var uniform INTERP_MODE_NONE restrict utexture2D @7 (~0, 0, 5) decl_var uniform INTERP_MODE_NONE restrict utexture2D @7 (~0, 0, 5) decl_function main (0 params) decl_function main (0 params) impl main { impl main { decl_var INTERP_MODE_NONE uvec2 @8 decl_var INTERP_MODE_NONE uvec2 @8 decl_var INTERP_MODE_NONE vec2 @9 decl_var INTERP_MODE_NONE vec2 @9 decl_var INTERP_MODE_NONE vec4 @10 decl_var INTERP_MODE_NONE vec4 @10 decl_var INTERP_MODE_NONE vec4 @11 decl_var INTERP_MODE_NONE vec4 @11 decl_var INTERP_MODE_NONE vec4 @12 decl_var INTERP_MODE_NONE vec4 @12 decl_var INTERP_MODE_NONE vec4 @13 decl_var INTERP_MODE_NONE vec4 @13 decl_var INTERP_MODE_NONE vec4 @14 decl_var INTERP_MODE_NONE vec4 @14 decl_var INTERP_MODE_NONE vec4 @15 decl_var INTERP_MODE_NONE vec4 @15 decl_var INTERP_MODE_NONE vec4 @16 decl_var INTERP_MODE_NONE vec4 @16 decl_var INTERP_MODE_NONE vec4 @17 decl_var INTERP_MODE_NONE vec4 @17 decl_var INTERP_MODE_NONE vec4 @18 decl_var INTERP_MODE_NONE vec4 @18 decl_var INTERP_MODE_NONE vec4 @19 decl_var INTERP_MODE_NONE vec4 @19 decl_var INTERP_MODE_NONE vec4 @20 decl_var INTERP_MODE_NONE vec4 @20 decl_var INTERP_MODE_NONE vec4 @21 decl_var INTERP_MODE_NONE vec4 @21 decl_var INTERP_MODE_NONE vec4 @22 decl_var INTERP_MODE_NONE vec4 @22 decl_var INTERP_MODE_NONE ivec4 @23 decl_var INTERP_MODE_NONE ivec4 @23 decl_var INTERP_MODE_NONE ivec4 @24 decl_var INTERP_MODE_NONE ivec4 @24 decl_var INTERP_MODE_NONE ivec4 @25 decl_var INTERP_MODE_NONE ivec4 @25 decl_var INTERP_MODE_NONE ivec4 @26 decl_var INTERP_MODE_NONE ivec4 @26 decl_var INTERP_MODE_NONE ivec4 @27 decl_var INTERP_MODE_NONE ivec4 @27 decl_var INTERP_MODE_NONE ivec4 @28 decl_var INTERP_MODE_NONE ivec4 @28 decl_var INTERP_MODE_NONE ivec4 @29 decl_var INTERP_MODE_NONE ivec4 @29 decl_var INTERP_MODE_NONE ivec4 @30 decl_var INTERP_MODE_NONE ivec4 @30 decl_var INTERP_MODE_NONE ivec4 @31 decl_var INTERP_MODE_NONE ivec4 @31 decl_var INTERP_MODE_NONE vec4 @32 decl_var INTERP_MODE_NONE vec4 @32 decl_var INTERP_MODE_NONE uint @33 decl_var INTERP_MODE_NONE uint @33 decl_var INTERP_MODE_NONE uint @34 decl_var INTERP_MODE_NONE uint @34 decl_var INTERP_MODE_NONE uint @35 decl_var INTERP_MODE_NONE uint @35 decl_var INTERP_MODE_NONE uint @36 decl_var INTERP_MODE_NONE uint @36 decl_var INTERP_MODE_NONE bool return_tmp decl_var INTERP_MODE_NONE bool return_tmp decl_var INTERP_MODE_NONE bool return_tmp@37 decl_var INTERP_MODE_NONE bool return_tmp@37 decl_var INTERP_MODE_NONE bool return_tmp@38 decl_var INTERP_MODE_NONE bool return_tmp@38 decl_var INTERP_MODE_NONE bool return_tmp@39 decl_var INTERP_MODE_NONE bool return_tmp@39 decl_var INTERP_MODE_NONE bool return decl_var INTERP_MODE_NONE bool return decl_var INTERP_MODE_NONE bvec4 @40 decl_var INTERP_MODE_NONE bvec4 @40 decl_var INTERP_MODE_NONE bvec4 @41 decl_var INTERP_MODE_NONE bvec4 @41 block block_0: block block_0: /* preds: */ /* preds: */ vec1 1 ssa_0 = load_const (false) vec1 1 ssa_0 = load_const (false) vec1 32 ssa_1 = deref_var &return (function_temp bool) vec1 32 ssa_1 = deref_var &return (function_temp bool) intrinsic store_deref (ssa_1, ssa_0) (wrmask=x /*1*/, access=0) intrinsic store_deref (ssa_1, ssa_0) (wrmask=x /*1*/, access=0) vec1 32 ssa_2 = undefined vec1 32 ssa_2 = undefined vec1 32 ssa_3 = undefined vec1 32 ssa_3 = undefined vec1 32 ssa_4 = load_const (0x00000004 = 0.000000) vec1 32 ssa_4 = load_const (0x00000004 = 0.000000) vec4 32 ssa_5 = load_const (0x00000000, 0x3f800000, 0x00000000, 0x3f800000) = (0.000000, 1.000000, 0.000000, vec4 32 ssa_5 = load_const (0x00000000, 0x3f800000, 0x00000000, 0x3f800000) = (0.000000, 1.000000, 0.000000, vec1 32 ssa_6 = load_const (0x00000001 = 0.000000) vec1 32 ssa_6 = load_const (0x00000001 = 0.000000) vec1 32 ssa_7 = load_const (0x00000000 = 0.000000) vec1 32 ssa_7 = load_const (0x00000000 = 0.000000) vec1 32 ssa_8 = load_const (0x00000000 = 0.000000) vec1 32 ssa_8 = load_const (0x00000000 = 0.000000) vec4 32 ssa_9 = load_const (0x3f800000, 0x00000000, 0x00000000, 0x3f800000) = (1.000000, 0.000000, 0.000000, vec4 32 ssa_9 = load_const (0x3f800000, 0x00000000, 0x00000000, 0x3f800000) = (1.000000, 0.000000, 0.000000, vec1 32 ssa_10 = undefined vec1 32 ssa_10 = undefined vec1 32 ssa_11 = undefined vec1 32 ssa_11 = undefined vec1 32 ssa_12 = load_const (0x00000002 = 0.000000) vec1 32 ssa_12 = load_const (0x00000002 = 0.000000) vec4 32 ssa_13 = load_const (0x00000000, 0x3f800000, 0x00000000, 0x3f800000) = (0.000000, 1.000000, 0.000000, vec4 32 ssa_13 = load_const (0x00000000, 0x3f800000, 0x00000000, 0x3f800000) = (0.000000, 1.000000, 0.000000, vec1 32 ssa_14 = load_const (0x00000001 = 0.000000) vec1 32 ssa_14 = load_const (0x00000001 = 0.000000) vec4 32 ssa_15 = load_const (0x00000000, 0xffffffac, 0xffffffe0, 0xffffff9d) = (0.000000, -nan, -nan, -nan) vec4 32 ssa_15 = load_const (0x00000000, 0xffffffac, 0xffffffe0, 0xffffff9d) = (0.000000, -nan, -nan, -nan) vec1 32 ssa_16 = load_const (0x00000000 = 0.000000) vec1 32 ssa_16 = load_const (0x00000000 = 0.000000) vec4 32 ssa_17 = load_const (0x3f800000, 0x00000000, 0x00000000, 0x3f800000) = (1.000000, 0.000000, 0.000000, vec4 32 ssa_17 = load_const (0x3f800000, 0x00000000, 0x00000000, 0x3f800000) = (1.000000, 0.000000, 0.000000, vec1 32 ssa_18 = undefined vec1 32 ssa_18 = undefined vec1 32 ssa_19 = undefined vec1 32 ssa_19 = undefined vec1 32 ssa_20 = load_const (0x00000001 = 0.000000) vec1 32 ssa_20 = load_const (0x00000001 = 0.000000) vec4 32 ssa_21 = load_const (0x00000000, 0x3f800000, 0x00000000, 0x3f800000) = (0.000000, 1.000000, 0.000000, vec4 32 ssa_21 = load_const (0x00000000, 0x3f800000, 0x00000000, 0x3f800000) = (0.000000, 1.000000, 0.000000, vec1 32 ssa_22 = load_const (0x00000001 = 0.000000) vec1 32 ssa_22 = load_const (0x00000001 = 0.000000) vec1 32 ssa_23 = load_const (0x3b000000 = 0.001953) vec1 32 ssa_23 = load_const (0x3b000000 = 0.001953) vec1 32 ssa_24 = load_const (0x3b000000 = 0.001953) vec1 32 ssa_24 = load_const (0x3b000000 = 0.001953) vec1 32 ssa_25 = load_const (0x3b000000 = 0.001953) vec1 32 ssa_25 = load_const (0x3b000000 = 0.001953) vec1 32 ssa_26 = load_const (0x3b000000 = 0.001953) vec1 32 ssa_26 = load_const (0x3b000000 = 0.001953) vec4 32 ssa_27 = load_const (0x3dc381f3, 0x3dc9c363, 0x3dc52221, 0x3d9e4e34) = (0.095463, 0.098517, 0.096257, vec4 32 ssa_27 = load_const (0x3dc381f3, 0x3dc9c363, 0x3dc52221, 0x3d9e4e34) = (0.095463, 0.098517, 0.096257, vec1 32 ssa_28 = load_const (0x40000000 = 2.000000) vec1 32 ssa_28 = load_const (0x40000000 = 2.000000) vec1 32 ssa_29 = load_const (0x40000000 = 2.000000) vec1 32 ssa_29 = load_const (0x40000000 = 2.000000) vec1 32 ssa_30 = load_const (0x40000000 = 2.000000) vec1 32 ssa_30 = load_const (0x40000000 = 2.000000) vec1 32 ssa_31 = load_const (0x40000000 = 2.000000) vec1 32 ssa_31 = load_const (0x40000000 = 2.000000) vec1 32 ssa_32 = load_const (0x00000000 = 0.000000) vec1 32 ssa_32 = load_const (0x00000000 = 0.000000) vec4 32 ssa_33 = load_const (0x3f800000, 0x00000000, 0x00000000, 0x3f800000) = (1.000000, 0.000000, 0.000000, vec4 32 ssa_33 = load_const (0x3f800000, 0x00000000, 0x00000000, 0x3f800000) = (1.000000, 0.000000, 0.000000, vec1 32 ssa_34 = undefined vec1 32 ssa_34 = undefined vec1 32 ssa_35 = undefined vec1 32 ssa_35 = undefined vec1 32 ssa_36 = load_const (0x00000000 = 0.000000) vec1 32 ssa_36 = load_const (0x00000000 = 0.000000) vec4 32 ssa_37 = load_const (0x00000000, 0x3f800000, 0x00000000, 0x3f800000) = (0.000000, 1.000000, 0.000000, vec4 32 ssa_37 = load_const (0x00000000, 0x3f800000, 0x00000000, 0x3f800000) = (0.000000, 1.000000, 0.000000, vec1 32 ssa_38 = load_const (0x00000001 = 0.000000) vec1 32 ssa_38 = load_const (0x00000001 = 0.000000) vec1 32 ssa_39 = load_const (0x3c008081 = 0.007843) vec1 32 ssa_39 = load_const (0x3c008081 = 0.007843) vec1 32 ssa_40 = load_const (0x3c008081 = 0.007843) vec1 32 ssa_40 = load_const (0x3c008081 = 0.007843) vec1 32 ssa_41 = load_const (0x3c008081 = 0.007843) vec1 32 ssa_41 = load_const (0x3c008081 = 0.007843) vec1 32 ssa_42 = load_const (0x3c008081 = 0.007843) vec1 32 ssa_42 = load_const (0x3c008081 = 0.007843) vec4 32 ssa_43 = load_const (0x3d85573d, 0x3dc88c03, 0x3d9d07d6, 0x3d97cde7) = (0.065108, 0.097923, 0.076675, vec4 32 ssa_43 = load_const (0x3d85573d, 0x3dc88c03, 0x3d9d07d6, 0x3d97cde7) = (0.065108, 0.097923, 0.076675, vec1 32 ssa_44 = load_const (0x40000000 = 2.000000) vec1 32 ssa_44 = load_const (0x40000000 = 2.000000) vec1 32 ssa_45 = load_const (0x40000000 = 2.000000) vec1 32 ssa_45 = load_const (0x40000000 = 2.000000) vec1 32 ssa_46 = load_const (0x40000000 = 2.000000) vec1 32 ssa_46 = load_const (0x40000000 = 2.000000) vec1 32 ssa_47 = load_const (0x40000000 = 2.000000) vec1 32 ssa_47 = load_const (0x40000000 = 2.000000) vec1 32 ssa_48 = load_const (0x00000000 = 0.000000) vec1 32 ssa_48 = load_const (0x00000000 = 0.000000) vec4 32 ssa_49 = load_const (0x3f800000, 0x00000000, 0x00000000, 0x3f800000) = (1.000000, 0.000000, 0.000000, vec4 32 ssa_49 = load_const (0x3f800000, 0x00000000, 0x00000000, 0x3f800000) = (1.000000, 0.000000, 0.000000, vec2 32 ssa_50 = load_const (0x3f000000, 0x3f000000) = (0.500000, 0.500000) vec2 32 ssa_50 = load_const (0x3f000000, 0x3f000000) = (0.500000, 0.500000) vec1 32 ssa_51 = deref_var &@0 (system uvec3) vec1 32 ssa_51 = deref_var &@0 (system uvec3) vec3 32 ssa_52 = intrinsic load_deref (ssa_51) (access=0) vec3 32 ssa_52 = intrinsic load_deref (ssa_51) (access=0) vec1 32 ssa_53 = deref_var &@1 (push_const block) vec1 32 ssa_53 = deref_var &@1 (push_const block) vec1 32 ssa_54 = deref_struct &ssa_53->field0 (push_const uvec4) /* &@1.field0 */ vec1 32 ssa_54 = deref_struct &ssa_53->field0 (push_const uvec4) /* &@1.field0 */ vec4 32 ssa_55 = intrinsic load_deref (ssa_54) (access=0) vec4 32 ssa_55 = intrinsic load_deref (ssa_54) (access=0) vec2 1 ssa_56 = uge ssa_52.xy, ssa_55.zw vec2 1 ssa_56 = uge ssa_52.xy, ssa_55.zw vec1 1 ssa_57 = load_const (false) vec1 1 ssa_57 = load_const (false) vec1 1 ssa_58 = bany_inequal2 ssa_56, ssa_57.xx vec1 1 ssa_58 = bany_inequal2 ssa_56, ssa_57.xx /* succs: block_1 block_2 */ /* succs: block_1 block_2 */ if ssa_58 { if ssa_58 { block block_1: block block_1: /* preds: block_0 */ /* preds: block_0 */ vec1 1 ssa_59 = load_const (true) vec1 1 ssa_59 = load_const (true) vec1 32 ssa_60 = deref_var &return (function_temp bool) vec1 32 ssa_60 = deref_var &return (function_temp bool) intrinsic store_deref (ssa_60, ssa_59) (wrmask=x /*1*/, access=0) intrinsic store_deref (ssa_60, ssa_59) (wrmask=x /*1*/, access=0) /* succs: block_15 */ /* succs: block_15 */ } else { } else { block block_2: block block_2: /* preds: block_0 */ /* preds: block_0 */ vec1 32 ssa_61 = deref_var &@1 (push_const block) vec1 32 ssa_61 = deref_var &@1 (push_const block) vec1 32 ssa_62 = deref_struct &ssa_61->field0 (push_const uvec4) /* &@1.field0 */ vec1 32 ssa_62 = deref_struct &ssa_61->field0 (push_const uvec4) /* &@1.field0 */ vec4 32 ssa_63 = intrinsic load_deref (ssa_62) (access=0) vec4 32 ssa_63 = intrinsic load_deref (ssa_62) (access=0) vec1 32 ssa_64 = deref_var &@0 (system uvec3) vec1 32 ssa_64 = deref_var &@0 (system uvec3) vec3 32 ssa_65 = intrinsic load_deref (ssa_64) (access=0) vec3 32 ssa_65 = intrinsic load_deref (ssa_64) (access=0) vec2 32 ssa_66 = iadd ssa_63.xy, ssa_65.xy vec2 32 ssa_66 = iadd ssa_63.xy, ssa_65.xy vec1 32 ssa_67 = deref_var &@8 (function_temp uvec2) vec1 32 ssa_67 = deref_var &@8 (function_temp uvec2) intrinsic store_deref (ssa_67, ssa_66) (wrmask=xy /*3*/, access=0) intrinsic store_deref (ssa_67, ssa_66) (wrmask=xy /*3*/, access=0) vec1 32 ssa_68 = deref_var &@0 (system uvec3) vec1 32 ssa_68 = deref_var &@0 (system uvec3) vec3 32 ssa_69 = intrinsic load_deref (ssa_68) (access=0) vec3 32 ssa_69 = intrinsic load_deref (ssa_68) (access=0) vec2 32 ssa_70 = u2f32 ssa_69.xy vec2 32 ssa_70 = u2f32 ssa_69.xy vec2 32 ssa_71 = fadd ssa_70, ssa_50 vec2 32 ssa_71 = fadd ssa_70, ssa_50 vec1 32 ssa_72 = deref_var &@1 (push_const block) vec1 32 ssa_72 = deref_var &@1 (push_const block) vec1 32 ssa_73 = deref_struct &ssa_72->field0 (push_const uvec4) /* &@1.field0 */ vec1 32 ssa_73 = deref_struct &ssa_72->field0 (push_const uvec4) /* &@1.field0 */ vec4 32 ssa_74 = intrinsic load_deref (ssa_73) (access=0) vec4 32 ssa_74 = intrinsic load_deref (ssa_73) (access=0) vec2 32 ssa_75 = u2f32 ssa_74.zw vec2 32 ssa_75 = u2f32 ssa_74.zw vec2 32 ssa_76 = fdiv ssa_71, ssa_75 vec2 32 ssa_76 = fdiv ssa_71, ssa_75 vec1 32 ssa_77 = deref_var &@9 (function_temp vec2) vec1 32 ssa_77 = deref_var &@9 (function_temp vec2) intrinsic store_deref (ssa_77, ssa_76) (wrmask=xy /*3*/, access=0) intrinsic store_deref (ssa_77, ssa_76) (wrmask=xy /*3*/, access=0) vec1 32 ssa_78 = deref_var &@10 (function_temp vec4) vec1 32 ssa_78 = deref_var &@10 (function_temp vec4) intrinsic store_deref (ssa_78, ssa_49) (wrmask=xyzw /*15*/, access=0) intrinsic store_deref (ssa_78, ssa_49) (wrmask=xyzw /*15*/, access=0) vec1 32 ssa_79 = deref_var &@2 (uniform texture2D) vec1 32 ssa_79 = deref_var &@2 (uniform texture2D) vec1 32 ssa_80 = deref_var &@8 (function_temp uvec2) vec1 32 ssa_80 = deref_var &@8 (function_temp uvec2) vec2 32 ssa_81 = intrinsic load_deref (ssa_80) (access=0) vec2 32 ssa_81 = intrinsic load_deref (ssa_80) (access=0) vec4 32 ssa_83 = (float32)txf ssa_79 (texture_deref), ssa_81 (coord), ssa_48 (lod) vec4 32 ssa_83 = (float32)txf ssa_79 (texture_deref), ssa_81 (coord), ssa_48 (lod) vec1 32 ssa_84 = deref_var &@11 (function_temp vec4) vec1 32 ssa_84 = deref_var &@11 (function_temp vec4) intrinsic store_deref (ssa_84, ssa_83) (wrmask=xyzw /*15*/, access=0) intrinsic store_deref (ssa_84, ssa_83) (wrmask=xyzw /*15*/, access=0) vec1 32 ssa_85 = deref_var &@1 (push_const block) vec1 32 ssa_85 = deref_var &@1 (push_const block) vec1 32 ssa_86 = deref_struct &ssa_85->field1 (push_const vec4[2]) /* &@1.field1 */ vec1 32 ssa_86 = deref_struct &ssa_85->field1 (push_const vec4[2]) /* &@1.field1 */ vec1 32 ssa_87 = load_const (0x00000000 = 0.000000) vec1 32 ssa_87 = load_const (0x00000000 = 0.000000) vec1 32 ssa_88 = deref_array &(*ssa_86)[0] (push_const vec4) /* &@1.field1[0] */ vec1 32 ssa_88 = deref_array &(*ssa_86)[0] (push_const vec4) /* &@1.field1[0] */ vec4 32 ssa_89 = intrinsic load_deref (ssa_88) (access=0) vec4 32 ssa_89 = intrinsic load_deref (ssa_88) (access=0) vec1 32 ssa_90 = deref_var &@9 (function_temp vec2) vec1 32 ssa_90 = deref_var &@9 (function_temp vec2) vec2 32 ssa_91 = intrinsic load_deref (ssa_90) (access=0) vec2 32 ssa_91 = intrinsic load_deref (ssa_90) (access=0) vec4 32 ssa_92 = fmul ssa_89, ssa_91.xxxx vec4 32 ssa_92 = fmul ssa_89, ssa_91.xxxx vec1 32 ssa_93 = deref_var &@1 (push_const block) vec1 32 ssa_93 = deref_var &@1 (push_const block) vec1 32 ssa_94 = deref_struct &ssa_93->field1 (push_const vec4[2]) /* &@1.field1 */ vec1 32 ssa_94 = deref_struct &ssa_93->field1 (push_const vec4[2]) /* &@1.field1 */ vec1 32 ssa_95 = load_const (0x00000001 = 0.000000) vec1 32 ssa_95 = load_const (0x00000001 = 0.000000) vec1 32 ssa_96 = deref_array &(*ssa_94)[1] (push_const vec4) /* &@1.field1[1] */ vec1 32 ssa_96 = deref_array &(*ssa_94)[1] (push_const vec4) /* &@1.field1[1] */ vec4 32 ssa_97 = intrinsic load_deref (ssa_96) (access=0) vec4 32 ssa_97 = intrinsic load_deref (ssa_96) (access=0) vec1 32 ssa_98 = deref_var &@9 (function_temp vec2) vec1 32 ssa_98 = deref_var &@9 (function_temp vec2) vec2 32 ssa_99 = intrinsic load_deref (ssa_98) (access=0) vec2 32 ssa_99 = intrinsic load_deref (ssa_98) (access=0) vec4 32 ssa_100 = fmul ssa_97, ssa_99.yyyy vec4 32 ssa_100 = fmul ssa_97, ssa_99.yyyy vec4 32 ssa_101 = fadd ssa_92, ssa_100 vec4 32 ssa_101 = fadd ssa_92, ssa_100 vec4 32 ssa_102 = vec4 ssa_47, ssa_46, ssa_45, ssa_44 vec4 32 ssa_102 = vec4 ssa_47, ssa_46, ssa_45, ssa_44 vec4 32 ssa_103 = fdiv ssa_101, ssa_102 vec4 32 ssa_103 = fdiv ssa_101, ssa_102 vec4 32 ssa_104 = fadd ssa_103, ssa_43 vec4 32 ssa_104 = fadd ssa_103, ssa_43 vec1 32 ssa_105 = deref_var &@12 (function_temp vec4) vec1 32 ssa_105 = deref_var &@12 (function_temp vec4) intrinsic store_deref (ssa_105, ssa_104) (wrmask=xyzw /*15*/, access=0) intrinsic store_deref (ssa_105, ssa_104) (wrmask=xyzw /*15*/, access=0) vec1 32 ssa_106 = deref_var &@1 (push_const block) vec1 32 ssa_106 = deref_var &@1 (push_const block) vec1 32 ssa_107 = deref_struct &ssa_106->field1 (push_const vec4[2]) /* &@1.field1 */ vec1 32 ssa_107 = deref_struct &ssa_106->field1 (push_const vec4[2]) /* &@1.field1 */ vec1 32 ssa_108 = load_const (0x00000000 = 0.000000) vec1 32 ssa_108 = load_const (0x00000000 = 0.000000) vec1 32 ssa_109 = deref_array &(*ssa_107)[0] (push_const vec4) /* &@1.field1[0] */ vec1 32 ssa_109 = deref_array &(*ssa_107)[0] (push_const vec4) /* &@1.field1[0] */ vec4 32 ssa_110 = intrinsic load_deref (ssa_109) (access=0) vec4 32 ssa_110 = intrinsic load_deref (ssa_109) (access=0) vec1 32 ssa_111 = deref_var &@1 (push_const block) vec1 32 ssa_111 = deref_var &@1 (push_const block) vec1 32 ssa_112 = deref_struct &ssa_111->field0 (push_const uvec4) /* &@1.field0 */ vec1 32 ssa_112 = deref_struct &ssa_111->field0 (push_const uvec4) /* &@1.field0 */ vec1 32 ssa_113 = load_const (0x00000002 = 0.000000) vec1 32 ssa_113 = load_const (0x00000002 = 0.000000) vec1 32 ssa_114 = deref_array &(*ssa_112)[2] (push_const uint) /* &@1.field0[2] */ vec1 32 ssa_114 = deref_array &(*ssa_112)[2] (push_const uint) /* &@1.field0[2] */ vec1 32 ssa_115 = intrinsic load_deref (ssa_114) (access=0) vec1 32 ssa_115 = intrinsic load_deref (ssa_114) (access=0) vec1 32 ssa_116 = u2f32 ssa_115 vec1 32 ssa_116 = u2f32 ssa_115 vec4 32 ssa_117 = fdiv ssa_110, ssa_116.xxxx vec4 32 ssa_117 = fdiv ssa_110, ssa_116.xxxx vec1 32 ssa_118 = deref_var &@1 (push_const block) vec1 32 ssa_118 = deref_var &@1 (push_const block) vec1 32 ssa_119 = deref_struct &ssa_118->field1 (push_const vec4[2]) /* &@1.field1 */ vec1 32 ssa_119 = deref_struct &ssa_118->field1 (push_const vec4[2]) /* &@1.field1 */ vec1 32 ssa_120 = load_const (0x00000001 = 0.000000) vec1 32 ssa_120 = load_const (0x00000001 = 0.000000) vec1 32 ssa_121 = deref_array &(*ssa_119)[1] (push_const vec4) /* &@1.field1[1] */ vec1 32 ssa_121 = deref_array &(*ssa_119)[1] (push_const vec4) /* &@1.field1[1] */ vec4 32 ssa_122 = intrinsic load_deref (ssa_121) (access=0) vec4 32 ssa_122 = intrinsic load_deref (ssa_121) (access=0) vec1 32 ssa_123 = deref_var &@1 (push_const block) vec1 32 ssa_123 = deref_var &@1 (push_const block) vec1 32 ssa_124 = deref_struct &ssa_123->field0 (push_const uvec4) /* &@1.field0 */ vec1 32 ssa_124 = deref_struct &ssa_123->field0 (push_const uvec4) /* &@1.field0 */ vec1 32 ssa_125 = load_const (0x00000003 = 0.000000) vec1 32 ssa_125 = load_const (0x00000003 = 0.000000) vec1 32 ssa_126 = deref_array &(*ssa_124)[3] (push_const uint) /* &@1.field0[3] */ vec1 32 ssa_126 = deref_array &(*ssa_124)[3] (push_const uint) /* &@1.field0[3] */ vec1 32 ssa_127 = intrinsic load_deref (ssa_126) (access=0) vec1 32 ssa_127 = intrinsic load_deref (ssa_126) (access=0) vec1 32 ssa_128 = u2f32 ssa_127 vec1 32 ssa_128 = u2f32 ssa_127 vec4 32 ssa_129 = fdiv ssa_122, ssa_128.xxxx vec4 32 ssa_129 = fdiv ssa_122, ssa_128.xxxx vec4 32 ssa_130 = fmax ssa_117, ssa_129 vec4 32 ssa_130 = fmax ssa_117, ssa_129 vec4 32 ssa_131 = vec4 ssa_42, ssa_41, ssa_40, ssa_39 vec4 32 ssa_131 = vec4 ssa_42, ssa_41, ssa_40, ssa_39 vec4 32 ssa_132 = fadd ssa_130, ssa_131 vec4 32 ssa_132 = fadd ssa_130, ssa_131 vec1 32 ssa_133 = deref_var &@11 (function_temp vec4) vec1 32 ssa_133 = deref_var &@11 (function_temp vec4) vec4 32 ssa_134 = intrinsic load_deref (ssa_133) (access=0) vec4 32 ssa_134 = intrinsic load_deref (ssa_133) (access=0) vec1 32 ssa_135 = deref_var &@13 (function_temp vec4) vec1 32 ssa_135 = deref_var &@13 (function_temp vec4) intrinsic store_deref (ssa_135, ssa_134) (wrmask=xyzw /*15*/, access=0) intrinsic store_deref (ssa_135, ssa_134) (wrmask=xyzw /*15*/, access=0) vec1 32 ssa_136 = deref_var &@12 (function_temp vec4) vec1 32 ssa_136 = deref_var &@12 (function_temp vec4) vec4 32 ssa_137 = intrinsic load_deref (ssa_136) (access=0) vec4 32 ssa_137 = intrinsic load_deref (ssa_136) (access=0) vec1 32 ssa_138 = deref_var &@14 (function_temp vec4) vec1 32 ssa_138 = deref_var &@14 (function_temp vec4) intrinsic store_deref (ssa_138, ssa_137) (wrmask=xyzw /*15*/, access=0) intrinsic store_deref (ssa_138, ssa_137) (wrmask=xyzw /*15*/, access=0) vec1 32 ssa_139 = deref_var &@15 (function_temp vec4) vec1 32 ssa_139 = deref_var &@15 (function_temp vec4) intrinsic store_deref (ssa_139, ssa_132) (wrmask=xyzw /*15*/, access=0) intrinsic store_deref (ssa_139, ssa_132) (wrmask=xyzw /*15*/, access=0) vec1 32 ssa_140 = deref_var &return_tmp (function_temp bool) vec1 32 ssa_140 = deref_var &return_tmp (function_temp bool) vec1 32 ssa_141 = deref_var &@13 (function_temp vec4) vec1 32 ssa_141 = deref_var &@13 (function_temp vec4) vec1 32 ssa_142 = deref_var &@14 (function_temp vec4) vec1 32 ssa_142 = deref_var &@14 (function_temp vec4) vec1 32 ssa_143 = deref_var &@15 (function_temp vec4) vec1 32 ssa_143 = deref_var &@15 (function_temp vec4) vec4 32 ssa_147 = intrinsic load_deref (ssa_141) (access=0) vec4 32 ssa_147 = intrinsic load_deref (ssa_141) (access=0) vec4 32 ssa_148 = intrinsic load_deref (ssa_142) (access=0) vec4 32 ssa_148 = intrinsic load_deref (ssa_142) (access=0) vec4 32 ssa_149 = fsub ssa_147, ssa_148 vec4 32 ssa_149 = fsub ssa_147, ssa_148 vec4 32 ssa_150 = fabs ssa_149 vec4 32 ssa_150 = fabs ssa_149 vec4 32 ssa_151 = intrinsic load_deref (ssa_143) (access=0) vec4 32 ssa_151 = intrinsic load_deref (ssa_143) (access=0) vec4 1 ssa_152 = flt! ssa_150, ssa_151 vec4 1 ssa_152 = flt! ssa_150, ssa_151 vec1 1 ssa_153 = load_const (true) vec1 1 ssa_153 = load_const (true) vec1 1 ssa_154 = ball_iequal4 ssa_152, ssa_153.xxxx vec1 1 ssa_154 = ball_iequal4 ssa_152, ssa_153.xxxx intrinsic store_deref (ssa_140, ssa_154) (wrmask=x /*1*/, access=0) intrinsic store_deref (ssa_140, ssa_154) (wrmask=x /*1*/, access=0) vec1 1 ssa_156 = intrinsic load_deref (ssa_140) (access=0) vec1 1 ssa_156 = intrinsic load_deref (ssa_140) (access=0) /* succs: block_3 block_4 */ /* succs: block_3 block_4 */ if ssa_156 { if ssa_156 { block block_3: block block_3: /* preds: block_2 */ /* preds: block_2 */ vec1 32 ssa_157 = load_const (0x00000000 = 0.000000) vec1 32 ssa_157 = load_const (0x00000000 = 0.000000) vec4 32 ssa_158 = intrinsic vulkan_resource_index (ssa_157) (desc_set=0, binding=0, desc_type vec4 32 ssa_158 = intrinsic vulkan_resource_index (ssa_157) (desc_set=0, binding=0, desc_type vec4 32 ssa_159 = intrinsic load_vulkan_descriptor (ssa_158) (desc_type=SSBO /*7*/) vec4 32 ssa_159 = intrinsic load_vulkan_descriptor (ssa_158) (desc_type=SSBO /*7*/) vec4 32 ssa_160 = deref_cast (block *)ssa_159 (ssbo block) /* ptr_stride=0, align_mul=4, alig vec4 32 ssa_160 = deref_cast (block *)ssa_159 (ssbo block) /* ptr_stride=0, align_mul=4, alig vec4 32 ssa_161 = deref_struct &ssa_160->field0 (ssbo uint[3]) /* &((block *)ssa_159)->field0 vec4 32 ssa_161 = deref_struct &ssa_160->field0 (ssbo uint[3]) /* &((block *)ssa_159)->field0 vec1 32 ssa_162 = load_const (0x00000000 = 0.000000) vec1 32 ssa_162 = load_const (0x00000000 = 0.000000) vec4 32 ssa_163 = deref_array &(*ssa_161)[0] (ssbo uint) /* &((block *)ssa_159)->field0[0] */ vec4 32 ssa_163 = deref_array &(*ssa_161)[0] (ssbo uint) /* &((block *)ssa_159)->field0[0] */ vec1 32 ssa_164 = intrinsic deref_atomic (ssa_163, ssa_38) (access=1, atomic_op=iadd) vec1 32 ssa_164 = intrinsic deref_atomic (ssa_163, ssa_38) (access=1, atomic_op=iadd) vec1 32 ssa_165 = deref_var &@10 (function_temp vec4) vec1 32 ssa_165 = deref_var &@10 (function_temp vec4) intrinsic store_deref (ssa_165, ssa_37) (wrmask=xyzw /*15*/, access=0) intrinsic store_deref (ssa_165, ssa_37) (wrmask=xyzw /*15*/, access=0) /* succs: block_5 */ /* succs: block_5 */ } else { } else { block block_4: block block_4: /* preds: block_2 */ /* preds: block_2 */ /* succs: block_5 */ /* succs: block_5 */ } } block block_5: block block_5: /* preds: block_3 block_4 */ /* preds: block_3 block_4 */ vec1 32 ssa_166 = deref_var &@4 (image image2DArray) vec1 32 ssa_166 = deref_var &@4 (image image2DArray) vec1 32 ssa_167 = deref_var &@8 (function_temp uvec2) vec1 32 ssa_167 = deref_var &@8 (function_temp uvec2) vec2 32 ssa_168 = intrinsic load_deref (ssa_167) (access=0) vec2 32 ssa_168 = intrinsic load_deref (ssa_167) (access=0) vec1 32 ssa_169 = deref_var &@10 (function_temp vec4) vec1 32 ssa_169 = deref_var &@10 (function_temp vec4) vec4 32 ssa_170 = intrinsic load_deref (ssa_169) (access=0) vec4 32 ssa_170 = intrinsic load_deref (ssa_169) (access=0) vec4 32 ssa_172 = vec4 ssa_168.x, ssa_168.y, ssa_36, ssa_35 vec4 32 ssa_172 = vec4 ssa_168.x, ssa_168.y, ssa_36, ssa_35 vec1 32 ssa_173 = load_const (0x00000000 = 0.000000) vec1 32 ssa_173 = load_const (0x00000000 = 0.000000) intrinsic image_deref_store (ssa_166, ssa_172, ssa_34, ssa_170, ssa_173) (image_dim=2D /*1*/, image_a intrinsic image_deref_store (ssa_166, ssa_172, ssa_34, ssa_170, ssa_173) (image_dim=2D /*1*/, image_a vec1 32 ssa_174 = deref_var &@16 (function_temp vec4) vec1 32 ssa_174 = deref_var &@16 (function_temp vec4) intrinsic store_deref (ssa_174, ssa_33) (wrmask=xyzw /*15*/, access=0) intrinsic store_deref (ssa_174, ssa_33) (wrmask=xyzw /*15*/, access=0) vec1 32 ssa_175 = deref_var &@5 (uniform texture2D) vec1 32 ssa_175 = deref_var &@5 (uniform texture2D) vec1 32 ssa_176 = deref_var &@8 (function_temp uvec2) vec1 32 ssa_176 = deref_var &@8 (function_temp uvec2) vec2 32 ssa_177 = intrinsic load_deref (ssa_176) (access=0) vec2 32 ssa_177 = intrinsic load_deref (ssa_176) (access=0) vec4 32 ssa_179 = (float32)txf ssa_175 (texture_deref), ssa_177 (coord), ssa_32 (lod) vec4 32 ssa_179 = (float32)txf ssa_175 (texture_deref), ssa_177 (coord), ssa_32 (lod) vec1 32 ssa_180 = deref_var &@17 (function_temp vec4) vec1 32 ssa_180 = deref_var &@17 (function_temp vec4) intrinsic store_deref (ssa_180, ssa_179) (wrmask=xyzw /*15*/, access=0) intrinsic store_deref (ssa_180, ssa_179) (wrmask=xyzw /*15*/, access=0) vec1 32 ssa_181 = deref_var &@1 (push_const block) vec1 32 ssa_181 = deref_var &@1 (push_const block) vec1 32 ssa_182 = deref_struct &ssa_181->field2 (push_const vec4[2]) /* &@1.field2 */ vec1 32 ssa_182 = deref_struct &ssa_181->field2 (push_const vec4[2]) /* &@1.field2 */ vec1 32 ssa_183 = load_const (0x00000000 = 0.000000) vec1 32 ssa_183 = load_const (0x00000000 = 0.000000) vec1 32 ssa_184 = deref_array &(*ssa_182)[0] (push_const vec4) /* &@1.field2[0] */ vec1 32 ssa_184 = deref_array &(*ssa_182)[0] (push_const vec4) /* &@1.field2[0] */ vec4 32 ssa_185 = intrinsic load_deref (ssa_184) (access=0) vec4 32 ssa_185 = intrinsic load_deref (ssa_184) (access=0) vec1 32 ssa_186 = deref_var &@9 (function_temp vec2) vec1 32 ssa_186 = deref_var &@9 (function_temp vec2) vec2 32 ssa_187 = intrinsic load_deref (ssa_186) (access=0) vec2 32 ssa_187 = intrinsic load_deref (ssa_186) (access=0) vec4 32 ssa_188 = fmul ssa_185, ssa_187.xxxx vec4 32 ssa_188 = fmul ssa_185, ssa_187.xxxx vec1 32 ssa_189 = deref_var &@1 (push_const block) vec1 32 ssa_189 = deref_var &@1 (push_const block) vec1 32 ssa_190 = deref_struct &ssa_189->field2 (push_const vec4[2]) /* &@1.field2 */ vec1 32 ssa_190 = deref_struct &ssa_189->field2 (push_const vec4[2]) /* &@1.field2 */ vec1 32 ssa_191 = load_const (0x00000001 = 0.000000) vec1 32 ssa_191 = load_const (0x00000001 = 0.000000) vec1 32 ssa_192 = deref_array &(*ssa_190)[1] (push_const vec4) /* &@1.field2[1] */ vec1 32 ssa_192 = deref_array &(*ssa_190)[1] (push_const vec4) /* &@1.field2[1] */ vec4 32 ssa_193 = intrinsic load_deref (ssa_192) (access=0) vec4 32 ssa_193 = intrinsic load_deref (ssa_192) (access=0) vec1 32 ssa_194 = deref_var &@9 (function_temp vec2) vec1 32 ssa_194 = deref_var &@9 (function_temp vec2) vec2 32 ssa_195 = intrinsic load_deref (ssa_194) (access=0) vec2 32 ssa_195 = intrinsic load_deref (ssa_194) (access=0) vec4 32 ssa_196 = fmul ssa_193, ssa_195.yyyy vec4 32 ssa_196 = fmul ssa_193, ssa_195.yyyy vec4 32 ssa_197 = fadd ssa_188, ssa_196 vec4 32 ssa_197 = fadd ssa_188, ssa_196 vec4 32 ssa_198 = vec4 ssa_31, ssa_30, ssa_29, ssa_28 vec4 32 ssa_198 = vec4 ssa_31, ssa_30, ssa_29, ssa_28 vec4 32 ssa_199 = fdiv ssa_197, ssa_198 vec4 32 ssa_199 = fdiv ssa_197, ssa_198 vec4 32 ssa_200 = fadd ssa_199, ssa_27 vec4 32 ssa_200 = fadd ssa_199, ssa_27 vec1 32 ssa_201 = deref_var &@18 (function_temp vec4) vec1 32 ssa_201 = deref_var &@18 (function_temp vec4) intrinsic store_deref (ssa_201, ssa_200) (wrmask=xyzw /*15*/, access=0) intrinsic store_deref (ssa_201, ssa_200) (wrmask=xyzw /*15*/, access=0) vec1 32 ssa_202 = deref_var &@1 (push_const block) vec1 32 ssa_202 = deref_var &@1 (push_const block) vec1 32 ssa_203 = deref_struct &ssa_202->field2 (push_const vec4[2]) /* &@1.field2 */ vec1 32 ssa_203 = deref_struct &ssa_202->field2 (push_const vec4[2]) /* &@1.field2 */ vec1 32 ssa_204 = load_const (0x00000000 = 0.000000) vec1 32 ssa_204 = load_const (0x00000000 = 0.000000) vec1 32 ssa_205 = deref_array &(*ssa_203)[0] (push_const vec4) /* &@1.field2[0] */ vec1 32 ssa_205 = deref_array &(*ssa_203)[0] (push_const vec4) /* &@1.field2[0] */ vec4 32 ssa_206 = intrinsic load_deref (ssa_205) (access=0) vec4 32 ssa_206 = intrinsic load_deref (ssa_205) (access=0) vec1 32 ssa_207 = deref_var &@1 (push_const block) vec1 32 ssa_207 = deref_var &@1 (push_const block) vec1 32 ssa_208 = deref_struct &ssa_207->field0 (push_const uvec4) /* &@1.field0 */ vec1 32 ssa_208 = deref_struct &ssa_207->field0 (push_const uvec4) /* &@1.field0 */ vec1 32 ssa_209 = load_const (0x00000002 = 0.000000) vec1 32 ssa_209 = load_const (0x00000002 = 0.000000) vec1 32 ssa_210 = deref_array &(*ssa_208)[2] (push_const uint) /* &@1.field0[2] */ vec1 32 ssa_210 = deref_array &(*ssa_208)[2] (push_const uint) /* &@1.field0[2] */ vec1 32 ssa_211 = intrinsic load_deref (ssa_210) (access=0) vec1 32 ssa_211 = intrinsic load_deref (ssa_210) (access=0) vec1 32 ssa_212 = u2f32 ssa_211 vec1 32 ssa_212 = u2f32 ssa_211 vec4 32 ssa_213 = fdiv ssa_206, ssa_212.xxxx vec4 32 ssa_213 = fdiv ssa_206, ssa_212.xxxx vec1 32 ssa_214 = deref_var &@1 (push_const block) vec1 32 ssa_214 = deref_var &@1 (push_const block) vec1 32 ssa_215 = deref_struct &ssa_214->field2 (push_const vec4[2]) /* &@1.field2 */ vec1 32 ssa_215 = deref_struct &ssa_214->field2 (push_const vec4[2]) /* &@1.field2 */ vec1 32 ssa_216 = load_const (0x00000001 = 0.000000) vec1 32 ssa_216 = load_const (0x00000001 = 0.000000) vec1 32 ssa_217 = deref_array &(*ssa_215)[1] (push_const vec4) /* &@1.field2[1] */ vec1 32 ssa_217 = deref_array &(*ssa_215)[1] (push_const vec4) /* &@1.field2[1] */ vec4 32 ssa_218 = intrinsic load_deref (ssa_217) (access=0) vec4 32 ssa_218 = intrinsic load_deref (ssa_217) (access=0) vec1 32 ssa_219 = deref_var &@1 (push_const block) vec1 32 ssa_219 = deref_var &@1 (push_const block) vec1 32 ssa_220 = deref_struct &ssa_219->field0 (push_const uvec4) /* &@1.field0 */ vec1 32 ssa_220 = deref_struct &ssa_219->field0 (push_const uvec4) /* &@1.field0 */ vec1 32 ssa_221 = load_const (0x00000003 = 0.000000) vec1 32 ssa_221 = load_const (0x00000003 = 0.000000) vec1 32 ssa_222 = deref_array &(*ssa_220)[3] (push_const uint) /* &@1.field0[3] */ vec1 32 ssa_222 = deref_array &(*ssa_220)[3] (push_const uint) /* &@1.field0[3] */ vec1 32 ssa_223 = intrinsic load_deref (ssa_222) (access=0) vec1 32 ssa_223 = intrinsic load_deref (ssa_222) (access=0) vec1 32 ssa_224 = u2f32 ssa_223 vec1 32 ssa_224 = u2f32 ssa_223 vec4 32 ssa_225 = fdiv ssa_218, ssa_224.xxxx vec4 32 ssa_225 = fdiv ssa_218, ssa_224.xxxx vec4 32 ssa_226 = fmax ssa_213, ssa_225 vec4 32 ssa_226 = fmax ssa_213, ssa_225 vec4 32 ssa_227 = vec4 ssa_26, ssa_25, ssa_24, ssa_23 vec4 32 ssa_227 = vec4 ssa_26, ssa_25, ssa_24, ssa_23 vec4 32 ssa_228 = fadd ssa_226, ssa_227 vec4 32 ssa_228 = fadd ssa_226, ssa_227 vec1 32 ssa_229 = deref_var &@17 (function_temp vec4) vec1 32 ssa_229 = deref_var &@17 (function_temp vec4) vec4 32 ssa_230 = intrinsic load_deref (ssa_229) (access=0) vec4 32 ssa_230 = intrinsic load_deref (ssa_229) (access=0) vec1 32 ssa_231 = deref_var &@19 (function_temp vec4) vec1 32 ssa_231 = deref_var &@19 (function_temp vec4) intrinsic store_deref (ssa_231, ssa_230) (wrmask=xyzw /*15*/, access=0) intrinsic store_deref (ssa_231, ssa_230) (wrmask=xyzw /*15*/, access=0) vec1 32 ssa_232 = deref_var &@18 (function_temp vec4) vec1 32 ssa_232 = deref_var &@18 (function_temp vec4) vec4 32 ssa_233 = intrinsic load_deref (ssa_232) (access=0) vec4 32 ssa_233 = intrinsic load_deref (ssa_232) (access=0) vec1 32 ssa_234 = deref_var &@20 (function_temp vec4) vec1 32 ssa_234 = deref_var &@20 (function_temp vec4) intrinsic store_deref (ssa_234, ssa_233) (wrmask=xyzw /*15*/, access=0) intrinsic store_deref (ssa_234, ssa_233) (wrmask=xyzw /*15*/, access=0) vec1 32 ssa_235 = deref_var &@21 (function_temp vec4) vec1 32 ssa_235 = deref_var &@21 (function_temp vec4) intrinsic store_deref (ssa_235, ssa_228) (wrmask=xyzw /*15*/, access=0) intrinsic store_deref (ssa_235, ssa_228) (wrmask=xyzw /*15*/, access=0) vec1 32 ssa_236 = deref_var &return_tmp@37 (function_temp bool) vec1 32 ssa_236 = deref_var &return_tmp@37 (function_temp bool) vec1 32 ssa_237 = deref_var &@19 (function_temp vec4) vec1 32 ssa_237 = deref_var &@19 (function_temp vec4) vec1 32 ssa_238 = deref_var &@20 (function_temp vec4) vec1 32 ssa_238 = deref_var &@20 (function_temp vec4) vec1 32 ssa_239 = deref_var &@21 (function_temp vec4) vec1 32 ssa_239 = deref_var &@21 (function_temp vec4) vec4 32 ssa_243 = intrinsic load_deref (ssa_237) (access=0) vec4 32 ssa_243 = intrinsic load_deref (ssa_237) (access=0) vec4 32 ssa_244 = intrinsic load_deref (ssa_238) (access=0) vec4 32 ssa_244 = intrinsic load_deref (ssa_238) (access=0) vec4 32 ssa_245 = fsub ssa_243, ssa_244 vec4 32 ssa_245 = fsub ssa_243, ssa_244 vec4 32 ssa_246 = fabs ssa_245 vec4 32 ssa_246 = fabs ssa_245 vec4 32 ssa_247 = intrinsic load_deref (ssa_239) (access=0) vec4 32 ssa_247 = intrinsic load_deref (ssa_239) (access=0) vec4 1 ssa_248 = flt! ssa_246, ssa_247 vec4 1 ssa_248 = flt! ssa_246, ssa_247 vec1 1 ssa_249 = load_const (true) vec1 1 ssa_249 = load_const (true) vec1 1 ssa_250 = ball_iequal4 ssa_248, ssa_249.xxxx vec1 1 ssa_250 = ball_iequal4 ssa_248, ssa_249.xxxx intrinsic store_deref (ssa_236, ssa_250) (wrmask=x /*1*/, access=0) intrinsic store_deref (ssa_236, ssa_250) (wrmask=x /*1*/, access=0) vec1 1 ssa_252 = intrinsic load_deref (ssa_236) (access=0) vec1 1 ssa_252 = intrinsic load_deref (ssa_236) (access=0) /* succs: block_6 block_7 */ /* succs: block_6 block_7 */ if ssa_252 { if ssa_252 { block block_6: block block_6: /* preds: block_5 */ /* preds: block_5 */ vec1 32 ssa_253 = load_const (0x00000000 = 0.000000) vec1 32 ssa_253 = load_const (0x00000000 = 0.000000) vec4 32 ssa_254 = intrinsic vulkan_resource_index (ssa_253) (desc_set=0, binding=0, desc_type vec4 32 ssa_254 = intrinsic vulkan_resource_index (ssa_253) (desc_set=0, binding=0, desc_type vec4 32 ssa_255 = intrinsic load_vulkan_descriptor (ssa_254) (desc_type=SSBO /*7*/) vec4 32 ssa_255 = intrinsic load_vulkan_descriptor (ssa_254) (desc_type=SSBO /*7*/) vec4 32 ssa_256 = deref_cast (block *)ssa_255 (ssbo block) /* ptr_stride=0, align_mul=4, alig vec4 32 ssa_256 = deref_cast (block *)ssa_255 (ssbo block) /* ptr_stride=0, align_mul=4, alig vec4 32 ssa_257 = deref_struct &ssa_256->field0 (ssbo uint[3]) /* &((block *)ssa_255)->field0 vec4 32 ssa_257 = deref_struct &ssa_256->field0 (ssbo uint[3]) /* &((block *)ssa_255)->field0 vec1 32 ssa_258 = load_const (0x00000001 = 0.000000) vec1 32 ssa_258 = load_const (0x00000001 = 0.000000) vec4 32 ssa_259 = deref_array &(*ssa_257)[1] (ssbo uint) /* &((block *)ssa_255)->field0[1] */ vec4 32 ssa_259 = deref_array &(*ssa_257)[1] (ssbo uint) /* &((block *)ssa_255)->field0[1] */ vec1 32 ssa_260 = intrinsic deref_atomic (ssa_259, ssa_22) (access=1, atomic_op=iadd) vec1 32 ssa_260 = intrinsic deref_atomic (ssa_259, ssa_22) (access=1, atomic_op=iadd) vec1 32 ssa_261 = deref_var &@16 (function_temp vec4) vec1 32 ssa_261 = deref_var &@16 (function_temp vec4) intrinsic store_deref (ssa_261, ssa_21) (wrmask=xyzw /*15*/, access=0) intrinsic store_deref (ssa_261, ssa_21) (wrmask=xyzw /*15*/, access=0) /* succs: block_8 */ /* succs: block_8 */ } else { } else { block block_7: block block_7: /* preds: block_5 */ /* preds: block_5 */ /* succs: block_8 */ /* succs: block_8 */ } } block block_8: block block_8: /* preds: block_6 block_7 */ /* preds: block_6 block_7 */ vec1 32 ssa_262 = deref_var &@4 (image image2DArray) vec1 32 ssa_262 = deref_var &@4 (image image2DArray) vec1 32 ssa_263 = deref_var &@8 (function_temp uvec2) vec1 32 ssa_263 = deref_var &@8 (function_temp uvec2) vec2 32 ssa_264 = intrinsic load_deref (ssa_263) (access=0) vec2 32 ssa_264 = intrinsic load_deref (ssa_263) (access=0) vec1 32 ssa_265 = deref_var &@16 (function_temp vec4) vec1 32 ssa_265 = deref_var &@16 (function_temp vec4) vec4 32 ssa_266 = intrinsic load_deref (ssa_265) (access=0) vec4 32 ssa_266 = intrinsic load_deref (ssa_265) (access=0) vec4 32 ssa_268 = vec4 ssa_264.x, ssa_264.y, ssa_20, ssa_19 vec4 32 ssa_268 = vec4 ssa_264.x, ssa_264.y, ssa_20, ssa_19 vec1 32 ssa_269 = load_const (0x00000000 = 0.000000) vec1 32 ssa_269 = load_const (0x00000000 = 0.000000) intrinsic image_deref_store (ssa_262, ssa_268, ssa_18, ssa_266, ssa_269) (image_dim=2D /*1*/, image_a intrinsic image_deref_store (ssa_262, ssa_268, ssa_18, ssa_266, ssa_269) (image_dim=2D /*1*/, image_a vec1 32 ssa_270 = deref_var &@22 (function_temp vec4) vec1 32 ssa_270 = deref_var &@22 (function_temp vec4) intrinsic store_deref (ssa_270, ssa_17) (wrmask=xyzw /*15*/, access=0) intrinsic store_deref (ssa_270, ssa_17) (wrmask=xyzw /*15*/, access=0) vec1 32 ssa_271 = deref_var &@6 (uniform itexture2D) vec1 32 ssa_271 = deref_var &@6 (uniform itexture2D) vec1 32 ssa_272 = deref_var &@8 (function_temp uvec2) vec1 32 ssa_272 = deref_var &@8 (function_temp uvec2) vec2 32 ssa_273 = intrinsic load_deref (ssa_272) (access=0) vec2 32 ssa_273 = intrinsic load_deref (ssa_272) (access=0) vec4 32 ssa_275 = (int32)txf ssa_271 (texture_deref), ssa_273 (coord), ssa_16 (lod) vec4 32 ssa_275 = (int32)txf ssa_271 (texture_deref), ssa_273 (coord), ssa_16 (lod) vec1 32 ssa_276 = deref_var &@23 (function_temp ivec4) vec1 32 ssa_276 = deref_var &@23 (function_temp ivec4) intrinsic store_deref (ssa_276, ssa_275) (wrmask=xyzw /*15*/, access=0) intrinsic store_deref (ssa_276, ssa_275) (wrmask=xyzw /*15*/, access=0) vec1 32 ssa_277 = deref_var &@24 (function_temp ivec4) vec1 32 ssa_277 = deref_var &@24 (function_temp ivec4) intrinsic store_deref (ssa_277, ssa_15) (wrmask=xyzw /*15*/, access=0) intrinsic store_deref (ssa_277, ssa_15) (wrmask=xyzw /*15*/, access=0) vec1 32 ssa_278 = deref_var &@1 (push_const block) vec1 32 ssa_278 = deref_var &@1 (push_const block) vec1 32 ssa_279 = deref_struct &ssa_278->field3 (push_const ivec4[2]) /* &@1.field3 */ vec1 32 ssa_279 = deref_struct &ssa_278->field3 (push_const ivec4[2]) /* &@1.field3 */ vec1 32 ssa_280 = load_const (0x00000000 = 0.000000) vec1 32 ssa_280 = load_const (0x00000000 = 0.000000) vec1 32 ssa_281 = deref_array &(*ssa_279)[0] (push_const ivec4) /* &@1.field3[0] */ vec1 32 ssa_281 = deref_array &(*ssa_279)[0] (push_const ivec4) /* &@1.field3[0] */ vec4 32 ssa_282 = intrinsic load_deref (ssa_281) (access=0) vec4 32 ssa_282 = intrinsic load_deref (ssa_281) (access=0) vec4 32 ssa_283 = i2f32 ssa_282 vec4 32 ssa_283 = i2f32 ssa_282 vec1 32 ssa_284 = deref_var &@9 (function_temp vec2) vec1 32 ssa_284 = deref_var &@9 (function_temp vec2) vec2 32 ssa_285 = intrinsic load_deref (ssa_284) (access=0) vec2 32 ssa_285 = intrinsic load_deref (ssa_284) (access=0) vec4 32 ssa_286 = fmul ssa_283, ssa_285.xxxx vec4 32 ssa_286 = fmul ssa_283, ssa_285.xxxx vec4 32 ssa_287 = f2i32 ssa_286 vec4 32 ssa_287 = f2i32 ssa_286 vec1 32 ssa_288 = deref_var &@24 (function_temp ivec4) vec1 32 ssa_288 = deref_var &@24 (function_temp ivec4) vec4 32 ssa_289 = intrinsic load_deref (ssa_288) (access=0) vec4 32 ssa_289 = intrinsic load_deref (ssa_288) (access=0) vec4 32 ssa_290 = iadd ssa_287, ssa_289 vec4 32 ssa_290 = iadd ssa_287, ssa_289 vec1 32 ssa_291 = deref_var &@25 (function_temp ivec4) vec1 32 ssa_291 = deref_var &@25 (function_temp ivec4) intrinsic store_deref (ssa_291, ssa_290) (wrmask=xyzw /*15*/, access=0) intrinsic store_deref (ssa_291, ssa_290) (wrmask=xyzw /*15*/, access=0) vec1 32 ssa_292 = deref_var &@1 (push_const block) vec1 32 ssa_292 = deref_var &@1 (push_const block) vec1 32 ssa_293 = deref_struct &ssa_292->field3 (push_const ivec4[2]) /* &@1.field3 */ vec1 32 ssa_293 = deref_struct &ssa_292->field3 (push_const ivec4[2]) /* &@1.field3 */ vec1 32 ssa_294 = load_const (0x00000001 = 0.000000) vec1 32 ssa_294 = load_const (0x00000001 = 0.000000) vec1 32 ssa_295 = deref_array &(*ssa_293)[1] (push_const ivec4) /* &@1.field3[1] */ vec1 32 ssa_295 = deref_array &(*ssa_293)[1] (push_const ivec4) /* &@1.field3[1] */ vec4 32 ssa_296 = intrinsic load_deref (ssa_295) (access=0) vec4 32 ssa_296 = intrinsic load_deref (ssa_295) (access=0) vec4 32 ssa_297 = i2f32 ssa_296 vec4 32 ssa_297 = i2f32 ssa_296 vec1 32 ssa_298 = deref_var &@9 (function_temp vec2) vec1 32 ssa_298 = deref_var &@9 (function_temp vec2) vec2 32 ssa_299 = intrinsic load_deref (ssa_298) (access=0) vec2 32 ssa_299 = intrinsic load_deref (ssa_298) (access=0) vec4 32 ssa_300 = fmul ssa_297, ssa_299.yyyy vec4 32 ssa_300 = fmul ssa_297, ssa_299.yyyy vec4 32 ssa_301 = f2i32 ssa_300 vec4 32 ssa_301 = f2i32 ssa_300 vec1 32 ssa_302 = deref_var &@24 (function_temp ivec4) vec1 32 ssa_302 = deref_var &@24 (function_temp ivec4) vec4 32 ssa_303 = intrinsic load_deref (ssa_302) (access=0) vec4 32 ssa_303 = intrinsic load_deref (ssa_302) (access=0) vec4 32 ssa_304 = iadd ssa_301, ssa_303 vec4 32 ssa_304 = iadd ssa_301, ssa_303 vec1 32 ssa_305 = deref_var &@26 (function_temp ivec4) vec1 32 ssa_305 = deref_var &@26 (function_temp ivec4) intrinsic store_deref (ssa_305, ssa_304) (wrmask=xyzw /*15*/, access=0) intrinsic store_deref (ssa_305, ssa_304) (wrmask=xyzw /*15*/, access=0) vec1 32 ssa_306 = deref_var &@1 (push_const block) vec1 32 ssa_306 = deref_var &@1 (push_const block) vec1 32 ssa_307 = deref_struct &ssa_306->field3 (push_const ivec4[2]) /* &@1.field3 */ vec1 32 ssa_307 = deref_struct &ssa_306->field3 (push_const ivec4[2]) /* &@1.field3 */ vec1 32 ssa_308 = load_const (0x00000000 = 0.000000) vec1 32 ssa_308 = load_const (0x00000000 = 0.000000) vec1 32 ssa_309 = deref_array &(*ssa_307)[0] (push_const ivec4) /* &@1.field3[0] */ vec1 32 ssa_309 = deref_array &(*ssa_307)[0] (push_const ivec4) /* &@1.field3[0] */ vec4 32 ssa_310 = intrinsic load_deref (ssa_309) (access=0) vec4 32 ssa_310 = intrinsic load_deref (ssa_309) (access=0) vec1 32 ssa_311 = deref_var &@1 (push_const block) vec1 32 ssa_311 = deref_var &@1 (push_const block) vec1 32 ssa_312 = deref_struct &ssa_311->field0 (push_const uvec4) /* &@1.field0 */ vec1 32 ssa_312 = deref_struct &ssa_311->field0 (push_const uvec4) /* &@1.field0 */ vec1 32 ssa_313 = load_const (0x00000002 = 0.000000) vec1 32 ssa_313 = load_const (0x00000002 = 0.000000) vec1 32 ssa_314 = deref_array &(*ssa_312)[2] (push_const uint) /* &@1.field0[2] */ vec1 32 ssa_314 = deref_array &(*ssa_312)[2] (push_const uint) /* &@1.field0[2] */ vec1 32 ssa_315 = intrinsic load_deref (ssa_314) (access=0) vec1 32 ssa_315 = intrinsic load_deref (ssa_314) (access=0) vec4 32 ssa_316 = idiv ssa_310, ssa_315.xxxx vec4 32 ssa_316 = idiv ssa_310, ssa_315.xxxx vec1 32 ssa_317 = deref_var &@1 (push_const block) vec1 32 ssa_317 = deref_var &@1 (push_const block) vec1 32 ssa_318 = deref_struct &ssa_317->field3 (push_const ivec4[2]) /* &@1.field3 */ vec1 32 ssa_318 = deref_struct &ssa_317->field3 (push_const ivec4[2]) /* &@1.field3 */ vec1 32 ssa_319 = load_const (0x00000001 = 0.000000) vec1 32 ssa_319 = load_const (0x00000001 = 0.000000) vec1 32 ssa_320 = deref_array &(*ssa_318)[1] (push_const ivec4) /* &@1.field3[1] */ vec1 32 ssa_320 = deref_array &(*ssa_318)[1] (push_const ivec4) /* &@1.field3[1] */ vec4 32 ssa_321 = intrinsic load_deref (ssa_320) (access=0) vec4 32 ssa_321 = intrinsic load_deref (ssa_320) (access=0) vec1 32 ssa_322 = deref_var &@1 (push_const block) vec1 32 ssa_322 = deref_var &@1 (push_const block) vec1 32 ssa_323 = deref_struct &ssa_322->field0 (push_const uvec4) /* &@1.field0 */ vec1 32 ssa_323 = deref_struct &ssa_322->field0 (push_const uvec4) /* &@1.field0 */ vec1 32 ssa_324 = load_const (0x00000003 = 0.000000) vec1 32 ssa_324 = load_const (0x00000003 = 0.000000) vec1 32 ssa_325 = deref_array &(*ssa_323)[3] (push_const uint) /* &@1.field0[3] */ vec1 32 ssa_325 = deref_array &(*ssa_323)[3] (push_const uint) /* &@1.field0[3] */ vec1 32 ssa_326 = intrinsic load_deref (ssa_325) (access=0) vec1 32 ssa_326 = intrinsic load_deref (ssa_325) (access=0) vec4 32 ssa_327 = idiv ssa_321, ssa_326.xxxx vec4 32 ssa_327 = idiv ssa_321, ssa_326.xxxx vec1 32 ssa_328 = deref_var &@23 (function_temp ivec4) vec1 32 ssa_328 = deref_var &@23 (function_temp ivec4) vec4 32 ssa_329 = intrinsic load_deref (ssa_328) (access=0) vec4 32 ssa_329 = intrinsic load_deref (ssa_328) (access=0) vec1 32 ssa_330 = deref_var &@27 (function_temp ivec4) vec1 32 ssa_330 = deref_var &@27 (function_temp ivec4) intrinsic store_deref (ssa_330, ssa_329) (wrmask=xyzw /*15*/, access=0) intrinsic store_deref (ssa_330, ssa_329) (wrmask=xyzw /*15*/, access=0) vec1 32 ssa_331 = deref_var &@25 (function_temp ivec4) vec1 32 ssa_331 = deref_var &@25 (function_temp ivec4) vec4 32 ssa_332 = intrinsic load_deref (ssa_331) (access=0) vec4 32 ssa_332 = intrinsic load_deref (ssa_331) (access=0) vec1 32 ssa_333 = deref_var &@28 (function_temp ivec4) vec1 32 ssa_333 = deref_var &@28 (function_temp ivec4) intrinsic store_deref (ssa_333, ssa_332) (wrmask=xyzw /*15*/, access=0) intrinsic store_deref (ssa_333, ssa_332) (wrmask=xyzw /*15*/, access=0) vec1 32 ssa_334 = deref_var &@26 (function_temp ivec4) vec1 32 ssa_334 = deref_var &@26 (function_temp ivec4) vec4 32 ssa_335 = intrinsic load_deref (ssa_334) (access=0) vec4 32 ssa_335 = intrinsic load_deref (ssa_334) (access=0) vec1 32 ssa_336 = deref_var &@29 (function_temp ivec4) vec1 32 ssa_336 = deref_var &@29 (function_temp ivec4) intrinsic store_deref (ssa_336, ssa_335) (wrmask=xyzw /*15*/, access=0) intrinsic store_deref (ssa_336, ssa_335) (wrmask=xyzw /*15*/, access=0) vec1 32 ssa_337 = deref_var &@30 (function_temp ivec4) vec1 32 ssa_337 = deref_var &@30 (function_temp ivec4) intrinsic store_deref (ssa_337, ssa_316) (wrmask=xyzw /*15*/, access=0) intrinsic store_deref (ssa_337, ssa_316) (wrmask=xyzw /*15*/, access=0) vec1 32 ssa_338 = deref_var &@31 (function_temp ivec4) vec1 32 ssa_338 = deref_var &@31 (function_temp ivec4) intrinsic store_deref (ssa_338, ssa_327) (wrmask=xyzw /*15*/, access=0) intrinsic store_deref (ssa_338, ssa_327) (wrmask=xyzw /*15*/, access=0) vec1 32 ssa_339 = deref_var &return_tmp@38 (function_temp bool) vec1 32 ssa_339 = deref_var &return_tmp@38 (function_temp bool) vec1 32 ssa_340 = deref_var &@27 (function_temp ivec4) vec1 32 ssa_340 = deref_var &@27 (function_temp ivec4) vec1 32 ssa_341 = deref_var &@28 (function_temp ivec4) vec1 32 ssa_341 = deref_var &@28 (function_temp ivec4) vec1 32 ssa_342 = deref_var &@29 (function_temp ivec4) vec1 32 ssa_342 = deref_var &@29 (function_temp ivec4) vec1 32 ssa_343 = deref_var &@30 (function_temp ivec4) vec1 32 ssa_343 = deref_var &@30 (function_temp ivec4) vec1 32 ssa_344 = deref_var &@31 (function_temp ivec4) vec1 32 ssa_344 = deref_var &@31 (function_temp ivec4) vec4 32 ssa_350 = intrinsic load_deref (ssa_340) (access=0) vec4 32 ssa_350 = intrinsic load_deref (ssa_340) (access=0) vec4 32 ssa_351 = intrinsic load_deref (ssa_341) (access=0) vec4 32 ssa_351 = intrinsic load_deref (ssa_341) (access=0) vec4 32 ssa_352 = isub ssa_350, ssa_351 vec4 32 ssa_352 = isub ssa_350, ssa_351 vec4 32 ssa_353 = iabs ssa_352 vec4 32 ssa_353 = iabs ssa_352 vec4 32 ssa_354 = intrinsic load_deref (ssa_343) (access=0) vec4 32 ssa_354 = intrinsic load_deref (ssa_343) (access=0) vec4 1 ssa_355 = ige ssa_354, ssa_353 vec4 1 ssa_355 = ige ssa_354, ssa_353 vec1 32 ssa_356 = deref_var &@40 (function_temp bvec4) vec1 32 ssa_356 = deref_var &@40 (function_temp bvec4) intrinsic store_deref (ssa_356, ssa_355) (wrmask=xyzw /*15*/, access=0) intrinsic store_deref (ssa_356, ssa_355) (wrmask=xyzw /*15*/, access=0) vec4 32 ssa_357 = intrinsic load_deref (ssa_340) (access=0) vec4 32 ssa_357 = intrinsic load_deref (ssa_340) (access=0) vec4 32 ssa_358 = intrinsic load_deref (ssa_342) (access=0) vec4 32 ssa_358 = intrinsic load_deref (ssa_342) (access=0) vec4 32 ssa_359 = isub ssa_357, ssa_358 vec4 32 ssa_359 = isub ssa_357, ssa_358 vec4 32 ssa_360 = iabs ssa_359 vec4 32 ssa_360 = iabs ssa_359 vec4 32 ssa_361 = intrinsic load_deref (ssa_344) (access=0) vec4 32 ssa_361 = intrinsic load_deref (ssa_344) (access=0) vec4 1 ssa_362 = ige ssa_361, ssa_360 vec4 1 ssa_362 = ige ssa_361, ssa_360 vec1 32 ssa_363 = deref_var &@41 (function_temp bvec4) vec1 32 ssa_363 = deref_var &@41 (function_temp bvec4) intrinsic store_deref (ssa_363, ssa_362) (wrmask=xyzw /*15*/, access=0) intrinsic store_deref (ssa_363, ssa_362) (wrmask=xyzw /*15*/, access=0) vec1 32 ssa_364 = deref_var &@40 (function_temp bvec4) vec1 32 ssa_364 = deref_var &@40 (function_temp bvec4) vec4 1 ssa_365 = intrinsic load_deref (ssa_364) (access=0) vec4 1 ssa_365 = intrinsic load_deref (ssa_364) (access=0) vec1 32 ssa_366 = deref_var &@41 (function_temp bvec4) vec1 32 ssa_366 = deref_var &@41 (function_temp bvec4) vec4 1 ssa_367 = intrinsic load_deref (ssa_366) (access=0) vec4 1 ssa_367 = intrinsic load_deref (ssa_366) (access=0) vec1 1 ssa_368 = ior ssa_365.x, ssa_367.x vec1 1 ssa_368 = ior ssa_365.x, ssa_367.x vec1 32 ssa_369 = deref_var &@40 (function_temp bvec4) vec1 32 ssa_369 = deref_var &@40 (function_temp bvec4) vec4 1 ssa_370 = intrinsic load_deref (ssa_369) (access=0) vec4 1 ssa_370 = intrinsic load_deref (ssa_369) (access=0) vec1 32 ssa_371 = deref_var &@41 (function_temp bvec4) vec1 32 ssa_371 = deref_var &@41 (function_temp bvec4) vec4 1 ssa_372 = intrinsic load_deref (ssa_371) (access=0) vec4 1 ssa_372 = intrinsic load_deref (ssa_371) (access=0) vec1 1 ssa_373 = ior ssa_370.y, ssa_372.y vec1 1 ssa_373 = ior ssa_370.y, ssa_372.y vec1 32 ssa_374 = deref_var &@40 (function_temp bvec4) vec1 32 ssa_374 = deref_var &@40 (function_temp bvec4) vec4 1 ssa_375 = intrinsic load_deref (ssa_374) (access=0) vec4 1 ssa_375 = intrinsic load_deref (ssa_374) (access=0) vec1 32 ssa_376 = deref_var &@41 (function_temp bvec4) vec1 32 ssa_376 = deref_var &@41 (function_temp bvec4) vec4 1 ssa_377 = intrinsic load_deref (ssa_376) (access=0) vec4 1 ssa_377 = intrinsic load_deref (ssa_376) (access=0) vec1 1 ssa_378 = ior ssa_375.z, ssa_377.z vec1 1 ssa_378 = ior ssa_375.z, ssa_377.z vec1 32 ssa_379 = deref_var &@40 (function_temp bvec4) vec1 32 ssa_379 = deref_var &@40 (function_temp bvec4) vec4 1 ssa_380 = intrinsic load_deref (ssa_379) (access=0) vec4 1 ssa_380 = intrinsic load_deref (ssa_379) (access=0) vec1 32 ssa_381 = deref_var &@41 (function_temp bvec4) vec1 32 ssa_381 = deref_var &@41 (function_temp bvec4) vec4 1 ssa_382 = intrinsic load_deref (ssa_381) (access=0) vec4 1 ssa_382 = intrinsic load_deref (ssa_381) (access=0) vec1 1 ssa_383 = ior ssa_380.w, ssa_382.w vec1 1 ssa_383 = ior ssa_380.w, ssa_382.w vec4 1 ssa_384 = vec4 ssa_368, ssa_373, ssa_378, ssa_383 vec4 1 ssa_384 = vec4 ssa_368, ssa_373, ssa_378, ssa_383 vec1 1 ssa_385 = load_const (true) vec1 1 ssa_385 = load_const (true) vec1 1 ssa_386 = ball_iequal4 ssa_384, ssa_385.xxxx vec1 1 ssa_386 = ball_iequal4 ssa_384, ssa_385.xxxx intrinsic store_deref (ssa_339, ssa_386) (wrmask=x /*1*/, access=0) intrinsic store_deref (ssa_339, ssa_386) (wrmask=x /*1*/, access=0) vec1 1 ssa_388 = intrinsic load_deref (ssa_339) (access=0) vec1 1 ssa_388 = intrinsic load_deref (ssa_339) (access=0) /* succs: block_9 block_10 */ /* succs: block_9 block_10 */ if ssa_388 { if ssa_388 { block block_9: block block_9: /* preds: block_8 */ /* preds: block_8 */ vec1 32 ssa_389 = load_const (0x00000000 = 0.000000) vec1 32 ssa_389 = load_const (0x00000000 = 0.000000) vec4 32 ssa_390 = intrinsic vulkan_resource_index (ssa_389) (desc_set=0, binding=0, desc_type vec4 32 ssa_390 = intrinsic vulkan_resource_index (ssa_389) (desc_set=0, binding=0, desc_type vec4 32 ssa_391 = intrinsic load_vulkan_descriptor (ssa_390) (desc_type=SSBO /*7*/) vec4 32 ssa_391 = intrinsic load_vulkan_descriptor (ssa_390) (desc_type=SSBO /*7*/) vec4 32 ssa_392 = deref_cast (block *)ssa_391 (ssbo block) /* ptr_stride=0, align_mul=4, alig vec4 32 ssa_392 = deref_cast (block *)ssa_391 (ssbo block) /* ptr_stride=0, align_mul=4, alig vec4 32 ssa_393 = deref_struct &ssa_392->field0 (ssbo uint[3]) /* &((block *)ssa_391)->field0 vec4 32 ssa_393 = deref_struct &ssa_392->field0 (ssbo uint[3]) /* &((block *)ssa_391)->field0 vec1 32 ssa_394 = load_const (0x00000002 = 0.000000) vec1 32 ssa_394 = load_const (0x00000002 = 0.000000) vec4 32 ssa_395 = deref_array &(*ssa_393)[2] (ssbo uint) /* &((block *)ssa_391)->field0[2] */ vec4 32 ssa_395 = deref_array &(*ssa_393)[2] (ssbo uint) /* &((block *)ssa_391)->field0[2] */ vec1 32 ssa_396 = intrinsic deref_atomic (ssa_395, ssa_14) (access=1, atomic_op=iadd) vec1 32 ssa_396 = intrinsic deref_atomic (ssa_395, ssa_14) (access=1, atomic_op=iadd) vec1 32 ssa_397 = deref_var &@22 (function_temp vec4) vec1 32 ssa_397 = deref_var &@22 (function_temp vec4) intrinsic store_deref (ssa_397, ssa_13) (wrmask=xyzw /*15*/, access=0) intrinsic store_deref (ssa_397, ssa_13) (wrmask=xyzw /*15*/, access=0) /* succs: block_11 */ /* succs: block_11 */ } else { } else { block block_10: block block_10: /* preds: block_8 */ /* preds: block_8 */ /* succs: block_11 */ /* succs: block_11 */ } } block block_11: block block_11: /* preds: block_9 block_10 */ /* preds: block_9 block_10 */ vec1 32 ssa_398 = deref_var &@4 (image image2DArray) vec1 32 ssa_398 = deref_var &@4 (image image2DArray) vec1 32 ssa_399 = deref_var &@8 (function_temp uvec2) vec1 32 ssa_399 = deref_var &@8 (function_temp uvec2) vec2 32 ssa_400 = intrinsic load_deref (ssa_399) (access=0) vec2 32 ssa_400 = intrinsic load_deref (ssa_399) (access=0) vec1 32 ssa_401 = deref_var &@22 (function_temp vec4) vec1 32 ssa_401 = deref_var &@22 (function_temp vec4) vec4 32 ssa_402 = intrinsic load_deref (ssa_401) (access=0) vec4 32 ssa_402 = intrinsic load_deref (ssa_401) (access=0) vec4 32 ssa_404 = vec4 ssa_400.x, ssa_400.y, ssa_12, ssa_11 vec4 32 ssa_404 = vec4 ssa_400.x, ssa_400.y, ssa_12, ssa_11 vec1 32 ssa_405 = load_const (0x00000000 = 0.000000) vec1 32 ssa_405 = load_const (0x00000000 = 0.000000) intrinsic image_deref_store (ssa_398, ssa_404, ssa_10, ssa_402, ssa_405) (image_dim=2D /*1*/, image_a intrinsic image_deref_store (ssa_398, ssa_404, ssa_10, ssa_402, ssa_405) (image_dim=2D /*1*/, image_a vec1 32 ssa_406 = deref_var &@32 (function_temp vec4) vec1 32 ssa_406 = deref_var &@32 (function_temp vec4) intrinsic store_deref (ssa_406, ssa_9) (wrmask=xyzw /*15*/, access=0) intrinsic store_deref (ssa_406, ssa_9) (wrmask=xyzw /*15*/, access=0) vec1 32 ssa_407 = deref_var &@7 (uniform utexture2D) vec1 32 ssa_407 = deref_var &@7 (uniform utexture2D) vec1 32 ssa_408 = deref_var &@8 (function_temp uvec2) vec1 32 ssa_408 = deref_var &@8 (function_temp uvec2) vec2 32 ssa_409 = intrinsic load_deref (ssa_408) (access=0) vec2 32 ssa_409 = intrinsic load_deref (ssa_408) (access=0) vec4 32 ssa_411 = (uint32)txf ssa_407 (texture_deref), ssa_409 (coord), ssa_8 (lod) vec4 32 ssa_411 = (uint32)txf ssa_407 (texture_deref), ssa_409 (coord), ssa_8 (lod) vec1 32 ssa_412 = mov ssa_411.x vec1 32 ssa_412 = mov ssa_411.x vec1 32 ssa_413 = deref_var &@33 (function_temp uint) vec1 32 ssa_413 = deref_var &@33 (function_temp uint) intrinsic store_deref (ssa_413, ssa_412) (wrmask=x /*1*/, access=0) intrinsic store_deref (ssa_413, ssa_412) (wrmask=x /*1*/, access=0) vec1 32 ssa_414 = deref_var &@33 (function_temp uint) vec1 32 ssa_414 = deref_var &@33 (function_temp uint) vec1 32 ssa_415 = intrinsic load_deref (ssa_414) (access=0) vec1 32 ssa_415 = intrinsic load_deref (ssa_414) (access=0) vec1 32 ssa_416 = deref_var &@34 (function_temp uint) vec1 32 ssa_416 = deref_var &@34 (function_temp uint) intrinsic store_deref (ssa_416, ssa_415) (wrmask=x /*1*/, access=0) intrinsic store_deref (ssa_416, ssa_415) (wrmask=x /*1*/, access=0) vec1 32 ssa_417 = deref_var &@1 (push_const block) vec1 32 ssa_417 = deref_var &@1 (push_const block) vec1 32 ssa_418 = deref_struct &ssa_417->field5 (push_const uint) /* &@1.field5 */ vec1 32 ssa_418 = deref_struct &ssa_417->field5 (push_const uint) /* &@1.field5 */ vec1 32 ssa_419 = intrinsic load_deref (ssa_418) (access=0) vec1 32 ssa_419 = intrinsic load_deref (ssa_418) (access=0) vec1 32 ssa_420 = deref_var &@35 (function_temp uint) vec1 32 ssa_420 = deref_var &@35 (function_temp uint) intrinsic store_deref (ssa_420, ssa_419) (wrmask=x /*1*/, access=0) intrinsic store_deref (ssa_420, ssa_419) (wrmask=x /*1*/, access=0) vec1 32 ssa_421 = deref_var &@36 (function_temp uint) vec1 32 ssa_421 = deref_var &@36 (function_temp uint) intrinsic store_deref (ssa_421, ssa_7) (wrmask=x /*1*/, access=0) intrinsic store_deref (ssa_421, ssa_7) (wrmask=x /*1*/, access=0) vec1 32 ssa_422 = deref_var &return_tmp@39 (function_temp bool) vec1 32 ssa_422 = deref_var &return_tmp@39 (function_temp bool) vec1 32 ssa_423 = deref_var &@34 (function_temp uint) vec1 32 ssa_423 = deref_var &@34 (function_temp uint) vec1 32 ssa_424 = deref_var &@35 (function_temp uint) vec1 32 ssa_424 = deref_var &@35 (function_temp uint) vec1 32 ssa_425 = deref_var &@36 (function_temp uint) vec1 32 ssa_425 = deref_var &@36 (function_temp uint) vec1 32 ssa_429 = intrinsic load_deref (ssa_423) (access=0) vec1 32 ssa_429 = intrinsic load_deref (ssa_423) (access=0) vec1 32 ssa_430 = intrinsic load_deref (ssa_424) (access=0) vec1 32 ssa_430 = intrinsic load_deref (ssa_424) (access=0) vec1 32 ssa_431 = isub ssa_429, ssa_430 vec1 32 ssa_431 = isub ssa_429, ssa_430 vec1 32 ssa_432 = u2f32 ssa_431 vec1 32 ssa_432 = u2f32 ssa_431 vec1 32 ssa_433 = fabs ssa_432 vec1 32 ssa_433 = fabs ssa_432 vec1 32 ssa_434 = intrinsic load_deref (ssa_425) (access=0) vec1 32 ssa_434 = intrinsic load_deref (ssa_425) (access=0) vec1 32 ssa_435 = u2f32 ssa_434 vec1 32 ssa_435 = u2f32 ssa_434 vec1 1 ssa_436 = fge! ssa_435, ssa_433 vec1 1 ssa_436 = fge! ssa_435, ssa_433 intrinsic store_deref (ssa_422, ssa_436) (wrmask=x /*1*/, access=0) intrinsic store_deref (ssa_422, ssa_436) (wrmask=x /*1*/, access=0) vec1 1 ssa_438 = intrinsic load_deref (ssa_422) (access=0) vec1 1 ssa_438 = intrinsic load_deref (ssa_422) (access=0) /* succs: block_12 block_13 */ /* succs: block_12 block_13 */ if ssa_438 { if ssa_438 { block block_12: block block_12: /* preds: block_11 */ /* preds: block_11 */ vec1 32 ssa_439 = load_const (0x00000000 = 0.000000) vec1 32 ssa_439 = load_const (0x00000000 = 0.000000) vec4 32 ssa_440 = intrinsic vulkan_resource_index (ssa_439) (desc_set=0, binding=0, desc_type vec4 32 ssa_440 = intrinsic vulkan_resource_index (ssa_439) (desc_set=0, binding=0, desc_type vec4 32 ssa_441 = intrinsic load_vulkan_descriptor (ssa_440) (desc_type=SSBO /*7*/) vec4 32 ssa_441 = intrinsic load_vulkan_descriptor (ssa_440) (desc_type=SSBO /*7*/) vec4 32 ssa_442 = deref_cast (block *)ssa_441 (ssbo block) /* ptr_stride=0, align_mul=4, alig vec4 32 ssa_442 = deref_cast (block *)ssa_441 (ssbo block) /* ptr_stride=0, align_mul=4, alig vec4 32 ssa_443 = deref_struct &ssa_442->field2 (ssbo uint) /* &((block *)ssa_441)->field2 */ vec4 32 ssa_443 = deref_struct &ssa_442->field2 (ssbo uint) /* &((block *)ssa_441)->field2 */ vec1 32 ssa_444 = intrinsic deref_atomic (ssa_443, ssa_6) (access=1, atomic_op=iadd) vec1 32 ssa_444 = intrinsic deref_atomic (ssa_443, ssa_6) (access=1, atomic_op=iadd) vec1 32 ssa_445 = deref_var &@32 (function_temp vec4) vec1 32 ssa_445 = deref_var &@32 (function_temp vec4) intrinsic store_deref (ssa_445, ssa_5) (wrmask=xyzw /*15*/, access=0) intrinsic store_deref (ssa_445, ssa_5) (wrmask=xyzw /*15*/, access=0) /* succs: block_14 */ /* succs: block_14 */ } else { } else { block block_13: block block_13: /* preds: block_11 */ /* preds: block_11 */ /* succs: block_14 */ /* succs: block_14 */ } } block block_14: block block_14: /* preds: block_12 block_13 */ /* preds: block_12 block_13 */ vec1 32 ssa_446 = deref_var &@4 (image image2DArray) vec1 32 ssa_446 = deref_var &@4 (image image2DArray) vec1 32 ssa_447 = deref_var &@8 (function_temp uvec2) vec1 32 ssa_447 = deref_var &@8 (function_temp uvec2) vec2 32 ssa_448 = intrinsic load_deref (ssa_447) (access=0) vec2 32 ssa_448 = intrinsic load_deref (ssa_447) (access=0) vec1 32 ssa_449 = deref_var &@32 (function_temp vec4) vec1 32 ssa_449 = deref_var &@32 (function_temp vec4) vec4 32 ssa_450 = intrinsic load_deref (ssa_449) (access=0) vec4 32 ssa_450 = intrinsic load_deref (ssa_449) (access=0) vec4 32 ssa_452 = vec4 ssa_448.x, ssa_448.y, ssa_4, ssa_3 vec4 32 ssa_452 = vec4 ssa_448.x, ssa_448.y, ssa_4, ssa_3 vec1 32 ssa_453 = load_const (0x00000000 = 0.000000) vec1 32 ssa_453 = load_const (0x00000000 = 0.000000) intrinsic image_deref_store (ssa_446, ssa_452, ssa_2, ssa_450, ssa_453) (image_dim=2D /*1*/, image_ar intrinsic image_deref_store (ssa_446, ssa_452, ssa_2, ssa_450, ssa_453) (image_dim=2D /*1*/, image_ar /* succs: block_15 */ /* succs: block_15 */ } } block block_15: block block_15: /* preds: block_1 block_14 */ /* preds: block_1 block_14 */ /* succs: block_16 */ /* succs: block_16 */ block block_16: block block_16: } } NIR (SSA form) for compute shader: NIR (SSA form) for compute shader: shader: MESA_SHADER_COMPUTE shader: MESA_SHADER_COMPUTE source_sha1: {0x4080c608, 0xef4e4e6b, 0x82f838bb, 0x041ba6fe, 0x4a36e587} source_sha1: {0x4080c608, 0xef4e4e6b, 0x82f838bb, 0x041ba6fe, 0x4a36e587} workgroup-size: 8, 8, 1 workgroup-size: 8, 8, 1 shared-size: 0 shared-size: 0 stage: 5 stage: 5 next_stage: 0 next_stage: 0 num_textures: 4 num_textures: 4 num_ssbos: 1 num_ssbos: 1 num_images: 1 num_images: 1 system_values_read: 0x00000000'00000020'00000000 system_values_read: 0x00000000'00000020'00000000 subgroup_size: 2 subgroup_size: 2 divergence_analysis_run: true divergence_analysis_run: true bit_sizes_float: 0x20 bit_sizes_float: 0x20 bit_sizes_int: 0x21 bit_sizes_int: 0x21 separate_shader: true separate_shader: true writes_memory: true writes_memory: true ptr_size: 0 ptr_size: 0 inputs: 0 inputs: 0 outputs: 0 outputs: 0 uniforms: 516 uniforms: 516 decl_var push_const INTERP_MODE_NONE block @0 decl_var push_const INTERP_MODE_NONE block @0 decl_var uniform INTERP_MODE_NONE restrict texture2D @1 (~0, 0, 1) decl_var uniform INTERP_MODE_NONE restrict texture2D @1 (~0, 0, 1) decl_var ssbo INTERP_MODE_NONE restrict writeonly block @2 (~0, 0, 0) decl_var ssbo INTERP_MODE_NONE restrict writeonly block @2 (~0, 0, 0) decl_var image INTERP_MODE_NONE restrict writeonly r8g8b8a8_unorm image2DArray @3 (~0, 0, 6) decl_var image INTERP_MODE_NONE restrict writeonly r8g8b8a8_unorm image2DArray @3 (~0, 0, 6) decl_var uniform INTERP_MODE_NONE restrict texture2D @4 (~0, 0, 2) decl_var uniform INTERP_MODE_NONE restrict texture2D @4 (~0, 0, 2) decl_var uniform INTERP_MODE_NONE restrict itexture2D @5 (~0, 0, 3) decl_var uniform INTERP_MODE_NONE restrict itexture2D @5 (~0, 0, 3) decl_var uniform INTERP_MODE_NONE restrict utexture2D @6 (~0, 0, 5) decl_var uniform INTERP_MODE_NONE restrict utexture2D @6 (~0, 0, 5) decl_function main (0 params) decl_function main (0 params) impl main { impl main { block block_0: block block_0: /* preds: */ /* preds: */ vec1 32 con ssa_0 = undefined vec1 32 con ssa_0 = undefined vec1 32 con ssa_1 = undefined vec1 32 con ssa_1 = undefined vec1 32 con ssa_2 = undefined vec1 32 con ssa_2 = undefined vec1 32 con ssa_3 = undefined vec1 32 con ssa_3 = undefined vec1 32 con ssa_4 = undefined vec1 32 con ssa_4 = undefined vec1 32 con ssa_5 = undefined vec1 32 con ssa_5 = undefined vec1 32 con ssa_6 = undefined vec1 32 con ssa_6 = undefined vec1 32 con ssa_7 = undefined vec1 32 con ssa_7 = undefined vec1 32 con ssa_8 = load_const (0x00000000 = 0.000000) vec1 32 con ssa_8 = load_const (0x00000000 = 0.000000) vec2 32 con ssa_9 = intrinsic load_uniform (ssa_8) (base=504, range=12, dest_type=uint /*4*/) vec2 32 con ssa_9 = intrinsic load_uniform (ssa_8) (base=504, range=12, dest_type=uint /*4*/) vec3 32 con ssa_10 = intrinsic load_workgroup_id_zero_base () () vec3 32 con ssa_10 = intrinsic load_workgroup_id_zero_base () () vec1 32 con ssa_11 = iadd ssa_10.x, ssa_9.x vec1 32 con ssa_11 = iadd ssa_10.x, ssa_9.x vec1 32 con ssa_12 = iadd ssa_10.y, ssa_9.y vec1 32 con ssa_12 = iadd ssa_10.y, ssa_9.y vec1 32 con ssa_13 = intrinsic load_subgroup_id () () vec1 32 con ssa_13 = intrinsic load_subgroup_id () () vec1 32 con ssa_14 = load_const (0x00000003 = 0.000000) vec1 32 con ssa_14 = load_const (0x00000003 = 0.000000) vec1 32 con ssa_15 = ishl ssa_13, ssa_14 vec1 32 con ssa_15 = ishl ssa_13, ssa_14 vec1 32 div ssa_16 = intrinsic load_subgroup_invocation () () vec1 32 div ssa_16 = intrinsic load_subgroup_invocation () () vec1 32 div ssa_17 = iadd ssa_16, ssa_15 vec1 32 div ssa_17 = iadd ssa_16, ssa_15 vec1 32 con ssa_18 = load_const (0x00000002 = 0.000000) vec1 32 con ssa_18 = load_const (0x00000002 = 0.000000) vec1 32 div ssa_19 = ushr ssa_17, ssa_18 vec1 32 div ssa_19 = ushr ssa_17, ssa_18 vec1 32 con ssa_20 = load_const (0x00000007 = 0.000000) vec1 32 con ssa_20 = load_const (0x00000007 = 0.000000) vec1 32 div ssa_21 = iand ssa_19, ssa_20 vec1 32 div ssa_21 = iand ssa_19, ssa_20 vec1 32 con ssa_22 = load_const (0x00000005 = 0.000000) vec1 32 con ssa_22 = load_const (0x00000005 = 0.000000) vec1 32 div ssa_23 = ushr ssa_17, ssa_22 vec1 32 div ssa_23 = ushr ssa_17, ssa_22 vec1 32 div ssa_24 = ishl ssa_23, ssa_18 vec1 32 div ssa_24 = ishl ssa_23, ssa_18 vec1 32 div ssa_25 = iand ssa_17, ssa_14 vec1 32 div ssa_25 = iand ssa_17, ssa_14 vec1 32 div ssa_26 = iadd ssa_25, ssa_24 vec1 32 div ssa_26 = iadd ssa_25, ssa_24 vec1 32 div ssa_27 = iand ssa_26, ssa_20 vec1 32 div ssa_27 = iand ssa_26, ssa_20 vec1 32 con ssa_28 = ishl ssa_11, ssa_14 vec1 32 con ssa_28 = ishl ssa_11, ssa_14 vec1 32 con ssa_29 = ishl ssa_12, ssa_14 vec1 32 con ssa_29 = ishl ssa_12, ssa_14 vec1 32 div ssa_30 = iadd ssa_28, ssa_21 vec1 32 div ssa_30 = iadd ssa_28, ssa_21 vec1 32 div ssa_31 = iadd ssa_29, ssa_27 vec1 32 div ssa_31 = iadd ssa_29, ssa_27 vec4 32 con ssa_32 = intrinsic load_uniform (ssa_8) (base=0, range=120, dest_type=invalid /*256*/) vec4 32 con ssa_32 = intrinsic load_uniform (ssa_8) (base=0, range=120, dest_type=invalid /*256*/) vec1 32 div ssa_33 = uge32 ssa_31, ssa_32.w vec1 32 div ssa_33 = uge32 ssa_31, ssa_32.w vec1 32 div ssa_34 = uge32 ssa_30, ssa_32.z vec1 32 div ssa_34 = uge32 ssa_30, ssa_32.z vec1 32 div ssa_35 = ior ssa_33, ssa_34 vec1 32 div ssa_35 = ior ssa_33, ssa_34 /* succs: block_1 block_2 */ /* succs: block_1 block_2 */ if ssa_35 { if ssa_35 { block block_1: block block_1: /* preds: block_0 */ /* preds: block_0 */ /* succs: block_27 */ /* succs: block_27 */ } else { } else { block block_2: block block_2: /* preds: block_0 */ /* preds: block_0 */ vec1 32 con ssa_36 = load_const (0x00000004 = 0.000000) vec1 32 con ssa_36 = load_const (0x00000004 = 0.000000) vec1 32 con ssa_37 = load_const (0x00000001 = 0.000000) vec1 32 con ssa_37 = load_const (0x00000001 = 0.000000) vec1 32 con ssa_38 = load_const (0xffffffac = -nan) vec1 32 con ssa_38 = load_const (0xffffffac = -nan) vec1 32 con ssa_39 = load_const (0xffffffe0 = -nan) vec1 32 con ssa_39 = load_const (0xffffffe0 = -nan) vec1 32 con ssa_40 = load_const (0xffffff9d = -nan) vec1 32 con ssa_40 = load_const (0xffffff9d = -nan) vec1 32 con ssa_41 = load_const (0x3b000000 = 0.001953) vec1 32 con ssa_41 = load_const (0x3b000000 = 0.001953) vec1 32 con ssa_42 = load_const (0x3c008081 = 0.007843) vec1 32 con ssa_42 = load_const (0x3c008081 = 0.007843) vec1 32 con ssa_43 = load_const (0x3f000000 = 0.500000) vec1 32 con ssa_43 = load_const (0x3f000000 = 0.500000) vec1 32 div ssa_44 = iadd ssa_32.x, ssa_30 vec1 32 div ssa_44 = iadd ssa_32.x, ssa_30 vec1 32 div ssa_45 = iadd ssa_32.y, ssa_31 vec1 32 div ssa_45 = iadd ssa_32.y, ssa_31 vec1 32 div ssa_46 = u2f32 ssa_30 vec1 32 div ssa_46 = u2f32 ssa_30 vec1 32 div ssa_47 = u2f32 ssa_31 vec1 32 div ssa_47 = u2f32 ssa_31 vec1 32 div ssa_48 = fadd ssa_46, ssa_43 vec1 32 div ssa_48 = fadd ssa_46, ssa_43 vec1 32 div ssa_49 = fadd ssa_47, ssa_43 vec1 32 div ssa_49 = fadd ssa_47, ssa_43 vec1 32 con ssa_50 = u2f32 ssa_32.z vec1 32 con ssa_50 = u2f32 ssa_32.z vec1 32 con ssa_51 = u2f32 ssa_32.w vec1 32 con ssa_51 = u2f32 ssa_32.w vec1 32 con ssa_52 = frcp ssa_50 vec1 32 con ssa_52 = frcp ssa_50 vec1 32 div ssa_53 = fmul ssa_48, ssa_52 vec1 32 div ssa_53 = fmul ssa_48, ssa_52 vec1 32 con ssa_54 = frcp ssa_51 vec1 32 con ssa_54 = frcp ssa_51 vec1 32 div ssa_55 = fmul ssa_49, ssa_54 vec1 32 div ssa_55 = fmul ssa_49, ssa_54 vec2 32 div ssa_56 = vec2 ssa_44, ssa_45 vec2 32 div ssa_56 = vec2 ssa_44, ssa_45 vec4 32 div ssa_57 = (float32)txf ssa_56 (coord), ssa_8 (lod), 4 (texture) vec4 32 div ssa_57 = (float32)txf ssa_56 (coord), ssa_8 (lod), 4 (texture) vec1 32 con ssa_58 = load_const (0x00000010 = 0.000000) vec1 32 con ssa_58 = load_const (0x00000010 = 0.000000) vec4 32 con ssa_59 = intrinsic load_uniform (ssa_58) (base=0, range=120, dest_type=invalid /*256*/) vec4 32 con ssa_59 = intrinsic load_uniform (ssa_58) (base=0, range=120, dest_type=invalid /*256*/) vec1 32 con ssa_60 = load_const (0x00000020 = 0.000000) vec1 32 con ssa_60 = load_const (0x00000020 = 0.000000) vec4 32 con ssa_61 = intrinsic load_uniform (ssa_60) (base=0, range=120, dest_type=invalid /*256*/) vec4 32 con ssa_61 = intrinsic load_uniform (ssa_60) (base=0, range=120, dest_type=invalid /*256*/) vec1 32 con ssa_62 = fneg ssa_61.x vec1 32 con ssa_62 = fneg ssa_61.x vec1 32 div ssa_63 = fmul ssa_62, ssa_55 vec1 32 div ssa_63 = fmul ssa_62, ssa_55 vec1 32 con ssa_64 = fneg ssa_61.y vec1 32 con ssa_64 = fneg ssa_61.y vec1 32 div ssa_65 = fmul ssa_64, ssa_55 vec1 32 div ssa_65 = fmul ssa_64, ssa_55 vec1 32 con ssa_66 = fneg ssa_61.z vec1 32 con ssa_66 = fneg ssa_61.z vec1 32 div ssa_67 = fmul ssa_66, ssa_55 vec1 32 div ssa_67 = fmul ssa_66, ssa_55 vec1 32 con ssa_68 = fneg ssa_61.w vec1 32 con ssa_68 = fneg ssa_61.w vec1 32 div ssa_69 = fmul ssa_68, ssa_55 vec1 32 div ssa_69 = fmul ssa_68, ssa_55 vec1 32 con ssa_70 = fneg ssa_59.x vec1 32 con ssa_70 = fneg ssa_59.x vec1 32 div ssa_71 = ffma ssa_70, ssa_53, ssa_63 vec1 32 div ssa_71 = ffma ssa_70, ssa_53, ssa_63 vec1 32 con ssa_72 = fneg ssa_59.y vec1 32 con ssa_72 = fneg ssa_59.y vec1 32 div ssa_73 = ffma ssa_72, ssa_53, ssa_65 vec1 32 div ssa_73 = ffma ssa_72, ssa_53, ssa_65 vec1 32 con ssa_74 = fneg ssa_59.z vec1 32 con ssa_74 = fneg ssa_59.z vec1 32 div ssa_75 = ffma ssa_74, ssa_53, ssa_67 vec1 32 div ssa_75 = ffma ssa_74, ssa_53, ssa_67 vec1 32 con ssa_76 = fneg ssa_59.w vec1 32 con ssa_76 = fneg ssa_59.w vec1 32 div ssa_77 = ffma ssa_76, ssa_53, ssa_69 vec1 32 div ssa_77 = ffma ssa_76, ssa_53, ssa_69 vec1 32 con ssa_78 = load_const (0xbd85573d = -0.065108) vec1 32 con ssa_78 = load_const (0xbd85573d = -0.065108) vec1 32 div ssa_79 = ffma ssa_71, ssa_43, ssa_78 vec1 32 div ssa_79 = ffma ssa_71, ssa_43, ssa_78 vec1 32 con ssa_80 = load_const (0xbdc88c03 = -0.097923) vec1 32 con ssa_80 = load_const (0xbdc88c03 = -0.097923) vec1 32 div ssa_81 = ffma ssa_73, ssa_43, ssa_80 vec1 32 div ssa_81 = ffma ssa_73, ssa_43, ssa_80 vec1 32 con ssa_82 = load_const (0xbd9d07d6 = -0.076675) vec1 32 con ssa_82 = load_const (0xbd9d07d6 = -0.076675) vec1 32 div ssa_83 = ffma ssa_75, ssa_43, ssa_82 vec1 32 div ssa_83 = ffma ssa_75, ssa_43, ssa_82 vec1 32 con ssa_84 = load_const (0xbd97cde7 = -0.074123) vec1 32 con ssa_84 = load_const (0xbd97cde7 = -0.074123) vec1 32 div ssa_85 = ffma ssa_77, ssa_43, ssa_84 vec1 32 div ssa_85 = ffma ssa_77, ssa_43, ssa_84 vec1 32 con ssa_86 = fmul ssa_59.x, ssa_52 vec1 32 con ssa_86 = fmul ssa_59.x, ssa_52 vec1 32 con ssa_87 = fmul ssa_59.y, ssa_52 vec1 32 con ssa_87 = fmul ssa_59.y, ssa_52 vec1 32 con ssa_88 = fmul ssa_59.z, ssa_52 vec1 32 con ssa_88 = fmul ssa_59.z, ssa_52 vec1 32 con ssa_89 = fmul ssa_59.w, ssa_52 vec1 32 con ssa_89 = fmul ssa_59.w, ssa_52 vec1 32 con ssa_90 = fmul ssa_61.x, ssa_54 vec1 32 con ssa_90 = fmul ssa_61.x, ssa_54 vec1 32 con ssa_91 = fmul ssa_61.y, ssa_54 vec1 32 con ssa_91 = fmul ssa_61.y, ssa_54 vec1 32 con ssa_92 = fmul ssa_61.z, ssa_54 vec1 32 con ssa_92 = fmul ssa_61.z, ssa_54 vec1 32 con ssa_93 = fmul ssa_61.w, ssa_54 vec1 32 con ssa_93 = fmul ssa_61.w, ssa_54 vec1 32 con ssa_94 = fmax ssa_86, ssa_90 vec1 32 con ssa_94 = fmax ssa_86, ssa_90 vec1 32 con ssa_95 = fmax ssa_87, ssa_91 vec1 32 con ssa_95 = fmax ssa_87, ssa_91 vec1 32 con ssa_96 = fmax ssa_88, ssa_92 vec1 32 con ssa_96 = fmax ssa_88, ssa_92 vec1 32 con ssa_97 = fmax ssa_89, ssa_93 vec1 32 con ssa_97 = fmax ssa_89, ssa_93 vec1 32 con ssa_98 = fadd ssa_94, ssa_42 vec1 32 con ssa_98 = fadd ssa_94, ssa_42 vec1 32 con ssa_99 = fadd ssa_95, ssa_42 vec1 32 con ssa_99 = fadd ssa_95, ssa_42 vec1 32 con ssa_100 = fadd ssa_96, ssa_42 vec1 32 con ssa_100 = fadd ssa_96, ssa_42 vec1 32 con ssa_101 = fadd ssa_97, ssa_42 vec1 32 con ssa_101 = fadd ssa_97, ssa_42 vec1 32 div ssa_102 = fadd ssa_57.x, ssa_79 vec1 32 div ssa_102 = fadd ssa_57.x, ssa_79 vec1 32 div ssa_103 = fadd ssa_57.y, ssa_81 vec1 32 div ssa_103 = fadd ssa_57.y, ssa_81 vec1 32 div ssa_104 = fadd ssa_57.z, ssa_83 vec1 32 div ssa_104 = fadd ssa_57.z, ssa_83 vec1 32 div ssa_105 = fadd ssa_57.w, ssa_85 vec1 32 div ssa_105 = fadd ssa_57.w, ssa_85 vec1 32 div ssa_106 = fabs ssa_102 vec1 32 div ssa_106 = fabs ssa_102 vec1 32 div ssa_107 = fabs ssa_103 vec1 32 div ssa_107 = fabs ssa_103 vec1 32 div ssa_108 = fabs ssa_104 vec1 32 div ssa_108 = fabs ssa_104 vec1 32 div ssa_109 = fabs ssa_105 vec1 32 div ssa_109 = fabs ssa_105 vec1 32 div ssa_110 = flt32! ssa_109, ssa_101 vec1 32 div ssa_110 = flt32! ssa_109, ssa_101 vec1 32 div ssa_111 = flt32! ssa_108, ssa_100 vec1 32 div ssa_111 = flt32! ssa_108, ssa_100 vec1 32 div ssa_112 = iand ssa_110, ssa_111 vec1 32 div ssa_112 = iand ssa_110, ssa_111 vec1 32 div ssa_113 = flt32! ssa_107, ssa_99 vec1 32 div ssa_113 = flt32! ssa_107, ssa_99 vec1 32 div ssa_114 = iand ssa_112, ssa_113 vec1 32 div ssa_114 = iand ssa_112, ssa_113 vec1 32 div ssa_115 = flt32! ssa_106, ssa_98 vec1 32 div ssa_115 = flt32! ssa_106, ssa_98 vec1 32 div ssa_116 = iand ssa_114, ssa_115 vec1 32 div ssa_116 = iand ssa_114, ssa_115 vec1 32 con ssa_117 = load_const (0x3f800000 = 1.000000) vec1 32 con ssa_117 = load_const (0x3f800000 = 1.000000) /* succs: block_3 block_7 */ /* succs: block_3 block_7 */ if ssa_116 { if ssa_116 { block block_3: block block_3: /* preds: block_2 */ /* preds: block_2 */ vec1 32 con ssa_118 = intrinsic reduce (ssa_37) (reduction_op=iadd /*257*/, cluster_size=0) vec1 32 con ssa_118 = intrinsic reduce (ssa_37) (reduction_op=iadd /*257*/, cluster_size=0) vec1 32 div ssa_119 = intrinsic first_invocation () () vec1 32 div ssa_119 = intrinsic first_invocation () () vec1 32 div ssa_120 = intrinsic load_subgroup_invocation () () vec1 32 div ssa_120 = intrinsic load_subgroup_invocation () () vec1 32 div ssa_121 = ieq32 ssa_120, ssa_119 vec1 32 div ssa_121 = ieq32 ssa_120, ssa_119 /* succs: block_4 block_5 */ /* succs: block_4 block_5 */ if ssa_121 { if ssa_121 { block block_4: block block_4: /* preds: block_3 */ /* preds: block_3 */ vec1 32 div ssa_122 = intrinsic ssbo_atomic (ssa_18, ssa_8, ssa_118) (access=1, atomi vec1 32 div ssa_122 = intrinsic ssbo_atomic (ssa_18, ssa_8, ssa_118) (access=1, atomi /* succs: block_6 */ /* succs: block_6 */ } else { } else { block block_5: block block_5: /* preds: block_3 */ /* preds: block_3 */ /* succs: block_6 */ /* succs: block_6 */ } } block block_6: block block_6: /* preds: block_4 block_5 */ /* preds: block_4 block_5 */ /* succs: block_8 */ /* succs: block_8 */ } else { } else { block block_7: block block_7: /* preds: block_2 */ /* preds: block_2 */ /* succs: block_8 */ /* succs: block_8 */ } } block block_8: block block_8: /* preds: block_6 block_7 */ /* preds: block_6 block_7 */ vec1 32 div ssa_123 = phi block_6: ssa_8, block_7: ssa_117 vec1 32 div ssa_123 = phi block_6: ssa_8, block_7: ssa_117 vec1 32 div ssa_124 = phi block_6: ssa_117, block_7: ssa_8 vec1 32 div ssa_124 = phi block_6: ssa_117, block_7: ssa_8 vec4 32 div ssa_125 = vec4 ssa_123, ssa_124, ssa_8, ssa_117 vec4 32 div ssa_125 = vec4 ssa_123, ssa_124, ssa_8, ssa_117 vec4 32 div ssa_126 = vec4 ssa_44, ssa_45, ssa_8, ssa_7 vec4 32 div ssa_126 = vec4 ssa_44, ssa_45, ssa_8, ssa_7 intrinsic image_store (ssa_14, ssa_126, ssa_6, ssa_125, ssa_8) (image_dim=2D /*1*/, image_array=true intrinsic image_store (ssa_14, ssa_126, ssa_6, ssa_125, ssa_8) (image_dim=2D /*1*/, image_array=true vec4 32 div ssa_127 = (float32)txf ssa_56 (coord), ssa_8 (lod), 5 (texture) vec4 32 div ssa_127 = (float32)txf ssa_56 (coord), ssa_8 (lod), 5 (texture) vec1 32 con ssa_128 = load_const (0x00000030 = 0.000000) vec1 32 con ssa_128 = load_const (0x00000030 = 0.000000) vec4 32 con ssa_129 = intrinsic load_uniform (ssa_128) (base=0, range=120, dest_type=invalid /*256*/) vec4 32 con ssa_129 = intrinsic load_uniform (ssa_128) (base=0, range=120, dest_type=invalid /*256*/) vec1 32 con ssa_130 = load_const (0x00000040 = 0.000000) vec1 32 con ssa_130 = load_const (0x00000040 = 0.000000) vec4 32 con ssa_131 = intrinsic load_uniform (ssa_130) (base=0, range=120, dest_type=invalid /*256*/) vec4 32 con ssa_131 = intrinsic load_uniform (ssa_130) (base=0, range=120, dest_type=invalid /*256*/) vec1 32 con ssa_132 = fneg ssa_131.x vec1 32 con ssa_132 = fneg ssa_131.x vec1 32 div ssa_133 = fmul ssa_132, ssa_55 vec1 32 div ssa_133 = fmul ssa_132, ssa_55 vec1 32 con ssa_134 = fneg ssa_131.y vec1 32 con ssa_134 = fneg ssa_131.y vec1 32 div ssa_135 = fmul ssa_134, ssa_55 vec1 32 div ssa_135 = fmul ssa_134, ssa_55 vec1 32 con ssa_136 = fneg ssa_131.z vec1 32 con ssa_136 = fneg ssa_131.z vec1 32 div ssa_137 = fmul ssa_136, ssa_55 vec1 32 div ssa_137 = fmul ssa_136, ssa_55 vec1 32 con ssa_138 = fneg ssa_131.w vec1 32 con ssa_138 = fneg ssa_131.w vec1 32 div ssa_139 = fmul ssa_138, ssa_55 vec1 32 div ssa_139 = fmul ssa_138, ssa_55 vec1 32 con ssa_140 = fneg ssa_129.x vec1 32 con ssa_140 = fneg ssa_129.x vec1 32 div ssa_141 = ffma ssa_140, ssa_53, ssa_133 vec1 32 div ssa_141 = ffma ssa_140, ssa_53, ssa_133 vec1 32 con ssa_142 = fneg ssa_129.y vec1 32 con ssa_142 = fneg ssa_129.y vec1 32 div ssa_143 = ffma ssa_142, ssa_53, ssa_135 vec1 32 div ssa_143 = ffma ssa_142, ssa_53, ssa_135 vec1 32 con ssa_144 = fneg ssa_129.z vec1 32 con ssa_144 = fneg ssa_129.z vec1 32 div ssa_145 = ffma ssa_144, ssa_53, ssa_137 vec1 32 div ssa_145 = ffma ssa_144, ssa_53, ssa_137 vec1 32 con ssa_146 = fneg ssa_129.w vec1 32 con ssa_146 = fneg ssa_129.w vec1 32 div ssa_147 = ffma ssa_146, ssa_53, ssa_139 vec1 32 div ssa_147 = ffma ssa_146, ssa_53, ssa_139 vec1 32 con ssa_148 = load_const (0xbdc381f3 = -0.095463) vec1 32 con ssa_148 = load_const (0xbdc381f3 = -0.095463) vec1 32 div ssa_149 = ffma ssa_141, ssa_43, ssa_148 vec1 32 div ssa_149 = ffma ssa_141, ssa_43, ssa_148 vec1 32 con ssa_150 = load_const (0xbdc9c363 = -0.098517) vec1 32 con ssa_150 = load_const (0xbdc9c363 = -0.098517) vec1 32 div ssa_151 = ffma ssa_143, ssa_43, ssa_150 vec1 32 div ssa_151 = ffma ssa_143, ssa_43, ssa_150 vec1 32 con ssa_152 = load_const (0xbdc52221 = -0.096257) vec1 32 con ssa_152 = load_const (0xbdc52221 = -0.096257) vec1 32 div ssa_153 = ffma ssa_145, ssa_43, ssa_152 vec1 32 div ssa_153 = ffma ssa_145, ssa_43, ssa_152 vec1 32 con ssa_154 = load_const (0xbd9e4e34 = -0.077298) vec1 32 con ssa_154 = load_const (0xbd9e4e34 = -0.077298) vec1 32 div ssa_155 = ffma ssa_147, ssa_43, ssa_154 vec1 32 div ssa_155 = ffma ssa_147, ssa_43, ssa_154 vec1 32 con ssa_156 = fmul ssa_129.x, ssa_52 vec1 32 con ssa_156 = fmul ssa_129.x, ssa_52 vec1 32 con ssa_157 = fmul ssa_129.y, ssa_52 vec1 32 con ssa_157 = fmul ssa_129.y, ssa_52 vec1 32 con ssa_158 = fmul ssa_129.z, ssa_52 vec1 32 con ssa_158 = fmul ssa_129.z, ssa_52 vec1 32 con ssa_159 = fmul ssa_129.w, ssa_52 vec1 32 con ssa_159 = fmul ssa_129.w, ssa_52 vec1 32 con ssa_160 = fmul ssa_131.x, ssa_54 vec1 32 con ssa_160 = fmul ssa_131.x, ssa_54 vec1 32 con ssa_161 = fmul ssa_131.y, ssa_54 vec1 32 con ssa_161 = fmul ssa_131.y, ssa_54 vec1 32 con ssa_162 = fmul ssa_131.z, ssa_54 vec1 32 con ssa_162 = fmul ssa_131.z, ssa_54 vec1 32 con ssa_163 = fmul ssa_131.w, ssa_54 vec1 32 con ssa_163 = fmul ssa_131.w, ssa_54 vec1 32 con ssa_164 = fmax ssa_156, ssa_160 vec1 32 con ssa_164 = fmax ssa_156, ssa_160 vec1 32 con ssa_165 = fmax ssa_157, ssa_161 vec1 32 con ssa_165 = fmax ssa_157, ssa_161 vec1 32 con ssa_166 = fmax ssa_158, ssa_162 vec1 32 con ssa_166 = fmax ssa_158, ssa_162 vec1 32 con ssa_167 = fmax ssa_159, ssa_163 vec1 32 con ssa_167 = fmax ssa_159, ssa_163 vec1 32 con ssa_168 = fadd ssa_164, ssa_41 vec1 32 con ssa_168 = fadd ssa_164, ssa_41 vec1 32 con ssa_169 = fadd ssa_165, ssa_41 vec1 32 con ssa_169 = fadd ssa_165, ssa_41 vec1 32 con ssa_170 = fadd ssa_166, ssa_41 vec1 32 con ssa_170 = fadd ssa_166, ssa_41 vec1 32 con ssa_171 = fadd ssa_167, ssa_41 vec1 32 con ssa_171 = fadd ssa_167, ssa_41 vec1 32 div ssa_172 = fadd ssa_127.x, ssa_149 vec1 32 div ssa_172 = fadd ssa_127.x, ssa_149 vec1 32 div ssa_173 = fadd ssa_127.y, ssa_151 vec1 32 div ssa_173 = fadd ssa_127.y, ssa_151 vec1 32 div ssa_174 = fadd ssa_127.z, ssa_153 vec1 32 div ssa_174 = fadd ssa_127.z, ssa_153 vec1 32 div ssa_175 = fadd ssa_127.w, ssa_155 vec1 32 div ssa_175 = fadd ssa_127.w, ssa_155 vec1 32 div ssa_176 = fabs ssa_172 vec1 32 div ssa_176 = fabs ssa_172 vec1 32 div ssa_177 = fabs ssa_173 vec1 32 div ssa_177 = fabs ssa_173 vec1 32 div ssa_178 = fabs ssa_174 vec1 32 div ssa_178 = fabs ssa_174 vec1 32 div ssa_179 = fabs ssa_175 vec1 32 div ssa_179 = fabs ssa_175 vec1 32 div ssa_180 = flt32! ssa_179, ssa_171 vec1 32 div ssa_180 = flt32! ssa_179, ssa_171 vec1 32 div ssa_181 = flt32! ssa_178, ssa_170 vec1 32 div ssa_181 = flt32! ssa_178, ssa_170 vec1 32 div ssa_182 = iand ssa_180, ssa_181 vec1 32 div ssa_182 = iand ssa_180, ssa_181 vec1 32 div ssa_183 = flt32! ssa_177, ssa_169 vec1 32 div ssa_183 = flt32! ssa_177, ssa_169 vec1 32 div ssa_184 = iand ssa_182, ssa_183 vec1 32 div ssa_184 = iand ssa_182, ssa_183 vec1 32 div ssa_185 = flt32! ssa_176, ssa_168 vec1 32 div ssa_185 = flt32! ssa_176, ssa_168 vec1 32 div ssa_186 = iand ssa_184, ssa_185 vec1 32 div ssa_186 = iand ssa_184, ssa_185 /* succs: block_9 block_13 */ /* succs: block_9 block_13 */ if ssa_186 { if ssa_186 { block block_9: block block_9: /* preds: block_8 */ /* preds: block_8 */ vec1 32 con ssa_187 = intrinsic reduce (ssa_37) (reduction_op=iadd /*257*/, cluster_size=0) vec1 32 con ssa_187 = intrinsic reduce (ssa_37) (reduction_op=iadd /*257*/, cluster_size=0) vec1 32 div ssa_188 = intrinsic first_invocation () () vec1 32 div ssa_188 = intrinsic first_invocation () () vec1 32 div ssa_189 = intrinsic load_subgroup_invocation () () vec1 32 div ssa_189 = intrinsic load_subgroup_invocation () () vec1 32 div ssa_190 = ieq32 ssa_189, ssa_188 vec1 32 div ssa_190 = ieq32 ssa_189, ssa_188 /* succs: block_10 block_11 */ /* succs: block_10 block_11 */ if ssa_190 { if ssa_190 { block block_10: block block_10: /* preds: block_9 */ /* preds: block_9 */ vec1 32 div ssa_191 = intrinsic ssbo_atomic (ssa_18, ssa_36, ssa_187) (access=1, atom vec1 32 div ssa_191 = intrinsic ssbo_atomic (ssa_18, ssa_36, ssa_187) (access=1, atom /* succs: block_12 */ /* succs: block_12 */ } else { } else { block block_11: block block_11: /* preds: block_9 */ /* preds: block_9 */ /* succs: block_12 */ /* succs: block_12 */ } } block block_12: block block_12: /* preds: block_10 block_11 */ /* preds: block_10 block_11 */ /* succs: block_14 */ /* succs: block_14 */ } else { } else { block block_13: block block_13: /* preds: block_8 */ /* preds: block_8 */ /* succs: block_14 */ /* succs: block_14 */ } } block block_14: block block_14: /* preds: block_12 block_13 */ /* preds: block_12 block_13 */ vec1 32 div ssa_192 = phi block_12: ssa_8, block_13: ssa_117 vec1 32 div ssa_192 = phi block_12: ssa_8, block_13: ssa_117 vec1 32 div ssa_193 = phi block_12: ssa_117, block_13: ssa_8 vec1 32 div ssa_193 = phi block_12: ssa_117, block_13: ssa_8 vec4 32 div ssa_194 = vec4 ssa_192, ssa_193, ssa_8, ssa_117 vec4 32 div ssa_194 = vec4 ssa_192, ssa_193, ssa_8, ssa_117 vec4 32 div ssa_195 = vec4 ssa_44, ssa_45, ssa_37, ssa_5 vec4 32 div ssa_195 = vec4 ssa_44, ssa_45, ssa_37, ssa_5 intrinsic image_store (ssa_14, ssa_195, ssa_4, ssa_194, ssa_8) (image_dim=2D /*1*/, image_array=true intrinsic image_store (ssa_14, ssa_195, ssa_4, ssa_194, ssa_8) (image_dim=2D /*1*/, image_array=true vec4 32 div ssa_196 = (int32)txf ssa_56 (coord), ssa_8 (lod), 6 (texture) vec4 32 div ssa_196 = (int32)txf ssa_56 (coord), ssa_8 (lod), 6 (texture) vec1 32 con ssa_197 = load_const (0x00000050 = 0.000000) vec1 32 con ssa_197 = load_const (0x00000050 = 0.000000) vec4 32 con ssa_198 = intrinsic load_uniform (ssa_197) (base=0, range=120, dest_type=invalid /*256*/) vec4 32 con ssa_198 = intrinsic load_uniform (ssa_197) (base=0, range=120, dest_type=invalid /*256*/) vec1 32 con ssa_199 = i2f32 ssa_198.x vec1 32 con ssa_199 = i2f32 ssa_198.x vec1 32 con ssa_200 = i2f32 ssa_198.y vec1 32 con ssa_200 = i2f32 ssa_198.y vec1 32 con ssa_201 = i2f32 ssa_198.z vec1 32 con ssa_201 = i2f32 ssa_198.z vec1 32 con ssa_202 = i2f32 ssa_198.w vec1 32 con ssa_202 = i2f32 ssa_198.w vec1 32 div ssa_203 = fmul ssa_199, ssa_53 vec1 32 div ssa_203 = fmul ssa_199, ssa_53 vec1 32 div ssa_204 = fmul ssa_200, ssa_53 vec1 32 div ssa_204 = fmul ssa_200, ssa_53 vec1 32 div ssa_205 = fmul ssa_201, ssa_53 vec1 32 div ssa_205 = fmul ssa_201, ssa_53 vec1 32 div ssa_206 = fmul ssa_202, ssa_53 vec1 32 div ssa_206 = fmul ssa_202, ssa_53 vec1 32 div ssa_207 = f2i32 ssa_203 vec1 32 div ssa_207 = f2i32 ssa_203 vec1 32 div ssa_208 = f2i32 ssa_204 vec1 32 div ssa_208 = f2i32 ssa_204 vec1 32 div ssa_209 = f2i32 ssa_205 vec1 32 div ssa_209 = f2i32 ssa_205 vec1 32 div ssa_210 = f2i32 ssa_206 vec1 32 div ssa_210 = f2i32 ssa_206 vec1 32 div ssa_211 = iadd ssa_208, ssa_38 | vec1 32 con ssa_211 = load_const (0x00000060 = 0.000000) vec1 32 div ssa_212 = iadd ssa_209, ssa_39 | vec4 32 con ssa_212 = intrinsic load_uniform (ssa_211) (base=0, range=120, dest_type=invalid /*256*/) vec1 32 div ssa_213 = iadd ssa_210, ssa_40 | vec1 32 con ssa_213 = i2f32 ssa_212.x vec1 32 con ssa_214 = load_const (0x00000060 = 0.000000) | vec1 32 con ssa_214 = i2f32 ssa_212.y vec4 32 con ssa_215 = intrinsic load_uniform (ssa_214) (base=0, range=120, dest_type=invalid /*256*/) | vec1 32 con ssa_215 = i2f32 ssa_212.z vec1 32 con ssa_216 = i2f32 ssa_215.x | vec1 32 con ssa_216 = i2f32 ssa_212.w vec1 32 con ssa_217 = i2f32 ssa_215.y | vec1 32 div ssa_217 = fmul ssa_213, ssa_55 vec1 32 con ssa_218 = i2f32 ssa_215.z | vec1 32 div ssa_218 = fmul ssa_214, ssa_55 vec1 32 con ssa_219 = i2f32 ssa_215.w | vec1 32 div ssa_219 = fmul ssa_215, ssa_55 vec1 32 div ssa_220 = fmul ssa_216, ssa_55 vec1 32 div ssa_220 = fmul ssa_216, ssa_55 vec1 32 div ssa_221 = fmul ssa_217, ssa_55 | vec1 32 div ssa_221 = f2i32 ssa_217 vec1 32 div ssa_222 = fmul ssa_218, ssa_55 | vec1 32 div ssa_222 = f2i32 ssa_218 vec1 32 div ssa_223 = fmul ssa_219, ssa_55 | vec1 32 div ssa_223 = f2i32 ssa_219 vec1 32 div ssa_224 = f2i32 ssa_220 vec1 32 div ssa_224 = f2i32 ssa_220 vec1 32 div ssa_225 = f2i32 ssa_221 | vec1 32 con ssa_225 = iabs! ssa_198.x vec1 32 div ssa_226 = f2i32 ssa_222 | vec1 32 con ssa_226 = iabs! ssa_32.z vec1 32 div ssa_227 = f2i32 ssa_223 | vec1 32 con ssa_227 = ilt32! ssa_198.x, ssa_8 vec1 32 div ssa_228 = iadd ssa_225, ssa_38 | vec1 32 con ssa_228 = ilt32! ssa_32.z, ssa_8 vec1 32 div ssa_229 = iadd ssa_226, ssa_39 | vec1 32 con ssa_229 = ixor! ssa_227, ssa_228 vec1 32 div ssa_230 = iadd ssa_227, ssa_40 | vec1 32 con ssa_230 = u2f32! ssa_226 vec1 32 con ssa_231 = iabs! ssa_198.x | vec1 32 con ssa_231 = frcp! ssa_230 vec1 32 con ssa_232 = iabs! ssa_32.z | vec1 32 con ssa_232 = load_const (0x4f7ffffe = 4294966784.000000) vec1 32 con ssa_233 = ilt32! ssa_198.x, ssa_8 | vec1 32 con ssa_233 = fmul! ssa_231, ssa_232 vec1 32 con ssa_234 = ilt32! ssa_32.z, ssa_8 | vec1 32 con ssa_234 = f2u32! ssa_233 vec1 32 con ssa_235 = ixor! ssa_233, ssa_234 | vec1 32 con ssa_235 = ineg! ssa_226 vec1 32 con ssa_236 = u2f32! ssa_232 | vec1 32 con ssa_236 = imul! ssa_226, ssa_234 vec1 32 con ssa_237 = frcp! ssa_236 | vec1 32 con ssa_237 = ineg! ssa_236 vec1 32 con ssa_238 = load_const (0x4f7ffffe = 4294966784.000000) | vec1 32 con ssa_238 = umul_high! ssa_234, ssa_237 vec1 32 con ssa_239 = fmul! ssa_237, ssa_238 | vec1 32 con ssa_239 = iadd! ssa_234, ssa_238 vec1 32 con ssa_240 = f2u32! ssa_239 | vec1 32 con ssa_240 = umul_high! ssa_225, ssa_239 vec1 32 con ssa_241 = ineg! ssa_232 | vec1 32 con ssa_241 = imul! ssa_240, ssa_226 vec1 32 con ssa_242 = imul! ssa_232, ssa_240 | vec1 32 con ssa_242 = ineg! ssa_241 vec1 32 con ssa_243 = ineg! ssa_242 | vec1 32 con ssa_243 = iadd! ssa_225, ssa_242 vec1 32 con ssa_244 = umul_high! ssa_240, ssa_243 | vec1 32 con ssa_244 = iadd! ssa_240, ssa_37 vec1 32 con ssa_245 = iadd! ssa_240, ssa_244 | vec1 32 con ssa_245 = uge32! ssa_243, ssa_226 vec1 32 con ssa_246 = umul_high! ssa_231, ssa_245 | vec1 32 con ssa_246 = b32csel! ssa_245, ssa_244, ssa_240 vec1 32 con ssa_247 = imul! ssa_246, ssa_232 | vec1 32 con ssa_247 = iadd! ssa_243, ssa_235 vec1 32 con ssa_248 = ineg! ssa_247 | vec1 32 con ssa_248 = b32csel! ssa_245, ssa_247, ssa_243 vec1 32 con ssa_249 = iadd! ssa_231, ssa_248 | vec1 32 con ssa_249 = iadd! ssa_246, ssa_37 vec1 32 con ssa_250 = iadd! ssa_246, ssa_37 | vec1 32 con ssa_250 = uge32! ssa_248, ssa_226 vec1 32 con ssa_251 = uge32! ssa_249, ssa_232 | vec1 32 con ssa_251 = b32csel! ssa_250, ssa_249, ssa_246 vec1 32 con ssa_252 = b32csel! ssa_251, ssa_250, ssa_246 | vec1 32 con ssa_252 = ineg! ssa_251 vec1 32 con ssa_253 = iadd! ssa_249, ssa_241 | vec1 32 con ssa_253 = b32csel! ssa_229, ssa_252, ssa_251 vec1 32 con ssa_254 = b32csel! ssa_251, ssa_253, ssa_249 | vec1 32 con ssa_254 = iabs! ssa_198.y vec1 32 con ssa_255 = iadd! ssa_252, ssa_37 | vec1 32 con ssa_255 = ilt32! ssa_198.y, ssa_8 vec1 32 con ssa_256 = uge32! ssa_254, ssa_232 | vec1 32 con ssa_256 = ixor! ssa_255, ssa_228 vec1 32 con ssa_257 = b32csel! ssa_256, ssa_255, ssa_252 | vec1 32 con ssa_257 = umul_high! ssa_254, ssa_239 vec1 32 con ssa_258 = ineg! ssa_257 | vec1 32 con ssa_258 = imul! ssa_257, ssa_226 vec1 32 con ssa_259 = b32csel! ssa_235, ssa_258, ssa_257 | vec1 32 con ssa_259 = ineg! ssa_258 vec1 32 con ssa_260 = iabs! ssa_198.y | vec1 32 con ssa_260 = iadd! ssa_254, ssa_259 vec1 32 con ssa_261 = ilt32! ssa_198.y, ssa_8 | vec1 32 con ssa_261 = iadd! ssa_257, ssa_37 vec1 32 con ssa_262 = ixor! ssa_261, ssa_234 | vec1 32 con ssa_262 = uge32! ssa_260, ssa_226 vec1 32 con ssa_263 = umul_high! ssa_260, ssa_245 | vec1 32 con ssa_263 = b32csel! ssa_262, ssa_261, ssa_257 vec1 32 con ssa_264 = imul! ssa_263, ssa_232 | vec1 32 con ssa_264 = iadd! ssa_260, ssa_235 vec1 32 con ssa_265 = ineg! ssa_264 | vec1 32 con ssa_265 = b32csel! ssa_262, ssa_264, ssa_260 vec1 32 con ssa_266 = iadd! ssa_260, ssa_265 | vec1 32 con ssa_266 = iadd! ssa_263, ssa_37 vec1 32 con ssa_267 = iadd! ssa_263, ssa_37 | vec1 32 con ssa_267 = uge32! ssa_265, ssa_226 vec1 32 con ssa_268 = uge32! ssa_266, ssa_232 | vec1 32 con ssa_268 = b32csel! ssa_267, ssa_266, ssa_263 vec1 32 con ssa_269 = b32csel! ssa_268, ssa_267, ssa_263 | vec1 32 con ssa_269 = ineg! ssa_268 vec1 32 con ssa_270 = iadd! ssa_266, ssa_241 | vec1 32 con ssa_270 = b32csel! ssa_256, ssa_269, ssa_268 vec1 32 con ssa_271 = b32csel! ssa_268, ssa_270, ssa_266 | vec1 32 con ssa_271 = iabs! ssa_198.z vec1 32 con ssa_272 = iadd! ssa_269, ssa_37 | vec1 32 con ssa_272 = ilt32! ssa_198.z, ssa_8 vec1 32 con ssa_273 = uge32! ssa_271, ssa_232 | vec1 32 con ssa_273 = ixor! ssa_272, ssa_228 vec1 32 con ssa_274 = b32csel! ssa_273, ssa_272, ssa_269 | vec1 32 con ssa_274 = umul_high! ssa_271, ssa_239 vec1 32 con ssa_275 = ineg! ssa_274 | vec1 32 con ssa_275 = imul! ssa_274, ssa_226 vec1 32 con ssa_276 = b32csel! ssa_262, ssa_275, ssa_274 | vec1 32 con ssa_276 = ineg! ssa_275 vec1 32 con ssa_277 = iabs! ssa_198.z | vec1 32 con ssa_277 = iadd! ssa_271, ssa_276 vec1 32 con ssa_278 = ilt32! ssa_198.z, ssa_8 | vec1 32 con ssa_278 = iadd! ssa_274, ssa_37 vec1 32 con ssa_279 = ixor! ssa_278, ssa_234 | vec1 32 con ssa_279 = uge32! ssa_277, ssa_226 vec1 32 con ssa_280 = umul_high! ssa_277, ssa_245 | vec1 32 con ssa_280 = b32csel! ssa_279, ssa_278, ssa_274 vec1 32 con ssa_281 = imul! ssa_280, ssa_232 | vec1 32 con ssa_281 = iadd! ssa_277, ssa_235 vec1 32 con ssa_282 = ineg! ssa_281 | vec1 32 con ssa_282 = b32csel! ssa_279, ssa_281, ssa_277 vec1 32 con ssa_283 = iadd! ssa_277, ssa_282 | vec1 32 con ssa_283 = iadd! ssa_280, ssa_37 vec1 32 con ssa_284 = iadd! ssa_280, ssa_37 | vec1 32 con ssa_284 = uge32! ssa_282, ssa_226 vec1 32 con ssa_285 = uge32! ssa_283, ssa_232 | vec1 32 con ssa_285 = b32csel! ssa_284, ssa_283, ssa_280 vec1 32 con ssa_286 = b32csel! ssa_285, ssa_284, ssa_280 | vec1 32 con ssa_286 = ineg! ssa_285 vec1 32 con ssa_287 = iadd! ssa_283, ssa_241 | vec1 32 con ssa_287 = b32csel! ssa_273, ssa_286, ssa_285 vec1 32 con ssa_288 = b32csel! ssa_285, ssa_287, ssa_283 | vec1 32 con ssa_288 = iabs! ssa_198.w vec1 32 con ssa_289 = iadd! ssa_286, ssa_37 | vec1 32 con ssa_289 = ilt32! ssa_198.w, ssa_8 vec1 32 con ssa_290 = uge32! ssa_288, ssa_232 | vec1 32 con ssa_290 = ixor! ssa_289, ssa_228 vec1 32 con ssa_291 = b32csel! ssa_290, ssa_289, ssa_286 | vec1 32 con ssa_291 = umul_high! ssa_288, ssa_239 vec1 32 con ssa_292 = ineg! ssa_291 | vec1 32 con ssa_292 = imul! ssa_291, ssa_226 vec1 32 con ssa_293 = b32csel! ssa_279, ssa_292, ssa_291 | vec1 32 con ssa_293 = ineg! ssa_292 vec1 32 con ssa_294 = iabs! ssa_198.w | vec1 32 con ssa_294 = iadd! ssa_288, ssa_293 vec1 32 con ssa_295 = ilt32! ssa_198.w, ssa_8 | vec1 32 con ssa_295 = iadd! ssa_291, ssa_37 vec1 32 con ssa_296 = ixor! ssa_295, ssa_234 | vec1 32 con ssa_296 = uge32! ssa_294, ssa_226 vec1 32 con ssa_297 = umul_high! ssa_294, ssa_245 | vec1 32 con ssa_297 = b32csel! ssa_296, ssa_295, ssa_291 vec1 32 con ssa_298 = imul! ssa_297, ssa_232 | vec1 32 con ssa_298 = iadd! ssa_294, ssa_235 vec1 32 con ssa_299 = ineg! ssa_298 | vec1 32 con ssa_299 = b32csel! ssa_296, ssa_298, ssa_294 vec1 32 con ssa_300 = iadd! ssa_294, ssa_299 | vec1 32 con ssa_300 = iadd! ssa_297, ssa_37 vec1 32 con ssa_301 = iadd! ssa_297, ssa_37 | vec1 32 con ssa_301 = uge32! ssa_299, ssa_226 vec1 32 con ssa_302 = uge32! ssa_300, ssa_232 | vec1 32 con ssa_302 = b32csel! ssa_301, ssa_300, ssa_297 vec1 32 con ssa_303 = b32csel! ssa_302, ssa_301, ssa_297 | vec1 32 con ssa_303 = ineg! ssa_302 vec1 32 con ssa_304 = iadd! ssa_300, ssa_241 | vec1 32 con ssa_304 = b32csel! ssa_290, ssa_303, ssa_302 vec1 32 con ssa_305 = b32csel! ssa_302, ssa_304, ssa_300 | vec1 32 con ssa_305 = iabs! ssa_212.x vec1 32 con ssa_306 = iadd! ssa_303, ssa_37 | vec1 32 con ssa_306 = iabs! ssa_32.w vec1 32 con ssa_307 = uge32! ssa_305, ssa_232 | vec1 32 con ssa_307 = ilt32! ssa_212.x, ssa_8 vec1 32 con ssa_308 = b32csel! ssa_307, ssa_306, ssa_303 | vec1 32 con ssa_308 = ilt32! ssa_32.w, ssa_8 vec1 32 con ssa_309 = ineg! ssa_308 | vec1 32 con ssa_309 = ixor! ssa_307, ssa_308 vec1 32 con ssa_310 = b32csel! ssa_296, ssa_309, ssa_308 | vec1 32 con ssa_310 = u2f32! ssa_306 vec1 32 con ssa_311 = iabs! ssa_215.x | vec1 32 con ssa_311 = frcp! ssa_310 vec1 32 con ssa_312 = iabs! ssa_32.w | vec1 32 con ssa_312 = fmul! ssa_311, ssa_232 vec1 32 con ssa_313 = ilt32! ssa_215.x, ssa_8 | vec1 32 con ssa_313 = f2u32! ssa_312 vec1 32 con ssa_314 = ilt32! ssa_32.w, ssa_8 | vec1 32 con ssa_314 = ineg! ssa_306 vec1 32 con ssa_315 = ixor! ssa_313, ssa_314 | vec1 32 con ssa_315 = imul! ssa_306, ssa_313 vec1 32 con ssa_316 = u2f32! ssa_312 | vec1 32 con ssa_316 = ineg! ssa_315 vec1 32 con ssa_317 = frcp! ssa_316 | vec1 32 con ssa_317 = umul_high! ssa_313, ssa_316 vec1 32 con ssa_318 = fmul! ssa_317, ssa_238 | vec1 32 con ssa_318 = iadd! ssa_313, ssa_317 vec1 32 con ssa_319 = f2u32! ssa_318 | vec1 32 con ssa_319 = umul_high! ssa_305, ssa_318 vec1 32 con ssa_320 = ineg! ssa_312 | vec1 32 con ssa_320 = imul! ssa_319, ssa_306 vec1 32 con ssa_321 = imul! ssa_312, ssa_319 | vec1 32 con ssa_321 = ineg! ssa_320 vec1 32 con ssa_322 = ineg! ssa_321 | vec1 32 con ssa_322 = iadd! ssa_305, ssa_321 vec1 32 con ssa_323 = umul_high! ssa_319, ssa_322 | vec1 32 con ssa_323 = iadd! ssa_319, ssa_37 vec1 32 con ssa_324 = iadd! ssa_319, ssa_323 | vec1 32 con ssa_324 = uge32! ssa_322, ssa_306 vec1 32 con ssa_325 = umul_high! ssa_311, ssa_324 | vec1 32 con ssa_325 = b32csel! ssa_324, ssa_323, ssa_319 vec1 32 con ssa_326 = imul! ssa_325, ssa_312 | vec1 32 con ssa_326 = iadd! ssa_322, ssa_314 vec1 32 con ssa_327 = ineg! ssa_326 | vec1 32 con ssa_327 = b32csel! ssa_324, ssa_326, ssa_322 vec1 32 con ssa_328 = iadd! ssa_311, ssa_327 | vec1 32 con ssa_328 = iadd! ssa_325, ssa_37 vec1 32 con ssa_329 = iadd! ssa_325, ssa_37 | vec1 32 con ssa_329 = uge32! ssa_327, ssa_306 vec1 32 con ssa_330 = uge32! ssa_328, ssa_312 | vec1 32 con ssa_330 = b32csel! ssa_329, ssa_328, ssa_325 vec1 32 con ssa_331 = b32csel! ssa_330, ssa_329, ssa_325 | vec1 32 con ssa_331 = ineg! ssa_330 vec1 32 con ssa_332 = iadd! ssa_328, ssa_320 | vec1 32 con ssa_332 = b32csel! ssa_309, ssa_331, ssa_330 vec1 32 con ssa_333 = b32csel! ssa_330, ssa_332, ssa_328 | vec1 32 con ssa_333 = iabs! ssa_212.y vec1 32 con ssa_334 = iadd! ssa_331, ssa_37 | vec1 32 con ssa_334 = ilt32! ssa_212.y, ssa_8 vec1 32 con ssa_335 = uge32! ssa_333, ssa_312 | vec1 32 con ssa_335 = ixor! ssa_334, ssa_308 vec1 32 con ssa_336 = b32csel! ssa_335, ssa_334, ssa_331 | vec1 32 con ssa_336 = umul_high! ssa_333, ssa_318 vec1 32 con ssa_337 = ineg! ssa_336 | vec1 32 con ssa_337 = imul! ssa_336, ssa_306 vec1 32 con ssa_338 = b32csel! ssa_315, ssa_337, ssa_336 | vec1 32 con ssa_338 = ineg! ssa_337 vec1 32 con ssa_339 = iabs! ssa_215.y | vec1 32 con ssa_339 = iadd! ssa_333, ssa_338 vec1 32 con ssa_340 = ilt32! ssa_215.y, ssa_8 | vec1 32 con ssa_340 = iadd! ssa_336, ssa_37 vec1 32 con ssa_341 = ixor! ssa_340, ssa_314 | vec1 32 con ssa_341 = uge32! ssa_339, ssa_306 vec1 32 con ssa_342 = umul_high! ssa_339, ssa_324 | vec1 32 con ssa_342 = b32csel! ssa_341, ssa_340, ssa_336 vec1 32 con ssa_343 = imul! ssa_342, ssa_312 | vec1 32 con ssa_343 = iadd! ssa_339, ssa_314 vec1 32 con ssa_344 = ineg! ssa_343 | vec1 32 con ssa_344 = b32csel! ssa_341, ssa_343, ssa_339 vec1 32 con ssa_345 = iadd! ssa_339, ssa_344 | vec1 32 con ssa_345 = iadd! ssa_342, ssa_37 vec1 32 con ssa_346 = iadd! ssa_342, ssa_37 | vec1 32 con ssa_346 = uge32! ssa_344, ssa_306 vec1 32 con ssa_347 = uge32! ssa_345, ssa_312 | vec1 32 con ssa_347 = b32csel! ssa_346, ssa_345, ssa_342 vec1 32 con ssa_348 = b32csel! ssa_347, ssa_346, ssa_342 | vec1 32 con ssa_348 = ineg! ssa_347 vec1 32 con ssa_349 = iadd! ssa_345, ssa_320 | vec1 32 con ssa_349 = b32csel! ssa_335, ssa_348, ssa_347 vec1 32 con ssa_350 = b32csel! ssa_347, ssa_349, ssa_345 | vec1 32 con ssa_350 = iabs! ssa_212.z vec1 32 con ssa_351 = iadd! ssa_348, ssa_37 | vec1 32 con ssa_351 = ilt32! ssa_212.z, ssa_8 vec1 32 con ssa_352 = uge32! ssa_350, ssa_312 | vec1 32 con ssa_352 = ixor! ssa_351, ssa_308 vec1 32 con ssa_353 = b32csel! ssa_352, ssa_351, ssa_348 | vec1 32 con ssa_353 = umul_high! ssa_350, ssa_318 vec1 32 con ssa_354 = ineg! ssa_353 | vec1 32 con ssa_354 = imul! ssa_353, ssa_306 vec1 32 con ssa_355 = b32csel! ssa_341, ssa_354, ssa_353 | vec1 32 con ssa_355 = ineg! ssa_354 vec1 32 con ssa_356 = iabs! ssa_215.z | vec1 32 con ssa_356 = iadd! ssa_350, ssa_355 vec1 32 con ssa_357 = ilt32! ssa_215.z, ssa_8 | vec1 32 con ssa_357 = iadd! ssa_353, ssa_37 vec1 32 con ssa_358 = ixor! ssa_357, ssa_314 | vec1 32 con ssa_358 = uge32! ssa_356, ssa_306 vec1 32 con ssa_359 = umul_high! ssa_356, ssa_324 | vec1 32 con ssa_359 = b32csel! ssa_358, ssa_357, ssa_353 vec1 32 con ssa_360 = imul! ssa_359, ssa_312 | vec1 32 con ssa_360 = iadd! ssa_356, ssa_314 vec1 32 con ssa_361 = ineg! ssa_360 | vec1 32 con ssa_361 = b32csel! ssa_358, ssa_360, ssa_356 vec1 32 con ssa_362 = iadd! ssa_356, ssa_361 | vec1 32 con ssa_362 = iadd! ssa_359, ssa_37 vec1 32 con ssa_363 = iadd! ssa_359, ssa_37 | vec1 32 con ssa_363 = uge32! ssa_361, ssa_306 vec1 32 con ssa_364 = uge32! ssa_362, ssa_312 | vec1 32 con ssa_364 = b32csel! ssa_363, ssa_362, ssa_359 vec1 32 con ssa_365 = b32csel! ssa_364, ssa_363, ssa_359 | vec1 32 con ssa_365 = ineg! ssa_364 vec1 32 con ssa_366 = iadd! ssa_362, ssa_320 | vec1 32 con ssa_366 = b32csel! ssa_352, ssa_365, ssa_364 vec1 32 con ssa_367 = b32csel! ssa_364, ssa_366, ssa_362 | vec1 32 con ssa_367 = iabs! ssa_212.w vec1 32 con ssa_368 = iadd! ssa_365, ssa_37 | vec1 32 con ssa_368 = ilt32! ssa_212.w, ssa_8 vec1 32 con ssa_369 = uge32! ssa_367, ssa_312 | vec1 32 con ssa_369 = ixor! ssa_368, ssa_308 vec1 32 con ssa_370 = b32csel! ssa_369, ssa_368, ssa_365 | vec1 32 con ssa_370 = umul_high! ssa_367, ssa_318 vec1 32 con ssa_371 = ineg! ssa_370 | vec1 32 con ssa_371 = imul! ssa_370, ssa_306 vec1 32 con ssa_372 = b32csel! ssa_358, ssa_371, ssa_370 | vec1 32 con ssa_372 = ineg! ssa_371 vec1 32 con ssa_373 = iabs! ssa_215.w | vec1 32 con ssa_373 = iadd! ssa_367, ssa_372 vec1 32 con ssa_374 = ilt32! ssa_215.w, ssa_8 | vec1 32 con ssa_374 = iadd! ssa_370, ssa_37 vec1 32 con ssa_375 = ixor! ssa_374, ssa_314 | vec1 32 con ssa_375 = uge32! ssa_373, ssa_306 vec1 32 con ssa_376 = umul_high! ssa_373, ssa_324 | vec1 32 con ssa_376 = b32csel! ssa_375, ssa_374, ssa_370 vec1 32 con ssa_377 = imul! ssa_376, ssa_312 | vec1 32 con ssa_377 = iadd! ssa_373, ssa_314 vec1 32 con ssa_378 = ineg! ssa_377 | vec1 32 con ssa_378 = b32csel! ssa_375, ssa_377, ssa_373 vec1 32 con ssa_379 = iadd! ssa_373, ssa_378 | vec1 32 con ssa_379 = iadd! ssa_376, ssa_37 vec1 32 con ssa_380 = iadd! ssa_376, ssa_37 | vec1 32 con ssa_380 = uge32! ssa_378, ssa_306 vec1 32 con ssa_381 = uge32! ssa_379, ssa_312 | vec1 32 con ssa_381 = b32csel! ssa_380, ssa_379, ssa_376 vec1 32 con ssa_382 = b32csel! ssa_381, ssa_380, ssa_376 | vec1 32 con ssa_382 = ineg! ssa_381 vec1 32 con ssa_383 = iadd! ssa_379, ssa_320 | vec1 32 con ssa_383 = b32csel! ssa_369, ssa_382, ssa_381 vec1 32 con ssa_384 = b32csel! ssa_381, ssa_383, ssa_379 | vec1 32 div ssa_384 = ineg ssa_207 vec1 32 con ssa_385 = iadd! ssa_382, ssa_37 | vec1 32 div ssa_385 = iadd ssa_196.x, ssa_384 vec1 32 con ssa_386 = uge32! ssa_384, ssa_312 | vec1 32 div ssa_386 = iadd3 ssa_38, ssa_208, ssa_196.y vec1 32 con ssa_387 = b32csel! ssa_386, ssa_385, ssa_382 | vec1 32 div ssa_387 = iadd3 ssa_39, ssa_209, ssa_196.z vec1 32 con ssa_388 = ineg! ssa_387 | vec1 32 div ssa_388 = iadd3 ssa_40, ssa_210, ssa_196.w vec1 32 con ssa_389 = b32csel! ssa_375, ssa_388, ssa_387 | vec1 32 div ssa_389 = iabs ssa_385 vec1 32 div ssa_390 = ineg ssa_207 | vec1 32 div ssa_390 = iabs ssa_386 vec1 32 div ssa_391 = iadd ssa_196.x, ssa_390 | vec1 32 div ssa_391 = iabs ssa_387 vec1 32 div ssa_392 = ineg ssa_211 | vec1 32 div ssa_392 = iabs ssa_388 vec1 32 div ssa_393 = iadd ssa_196.y, ssa_392 | vec1 32 div ssa_393 = ineg ssa_221 vec1 32 div ssa_394 = ineg ssa_212 | vec1 32 div ssa_394 = iadd ssa_196.x, ssa_393 vec1 32 div ssa_395 = iadd ssa_196.z, ssa_394 | vec1 32 div ssa_395 = iadd3 ssa_38, ssa_222, ssa_196.y vec1 32 div ssa_396 = ineg ssa_213 | vec1 32 div ssa_396 = iadd3 ssa_39, ssa_223, ssa_196.z vec1 32 div ssa_397 = iadd ssa_196.w, ssa_396 | vec1 32 div ssa_397 = iadd3 ssa_40, ssa_224, ssa_196.w vec1 32 div ssa_398 = iabs ssa_391 | vec1 32 div ssa_398 = iabs ssa_394 vec1 32 div ssa_399 = iabs ssa_393 | vec1 32 div ssa_399 = iabs ssa_395 vec1 32 div ssa_400 = iabs ssa_395 | vec1 32 div ssa_400 = iabs ssa_396 vec1 32 div ssa_401 = iabs ssa_397 vec1 32 div ssa_401 = iabs ssa_397 vec1 32 div ssa_402 = ineg ssa_224 | vec1 32 div ssa_402 = ige32 ssa_332, ssa_398 vec1 32 div ssa_403 = iadd ssa_196.x, ssa_402 | vec1 32 div ssa_403 = ige32 ssa_253, ssa_389 vec1 32 div ssa_404 = ineg ssa_228 | vec1 32 div ssa_404 = ior ssa_403, ssa_402 vec1 32 div ssa_405 = iadd ssa_196.y, ssa_404 | vec1 32 div ssa_405 = ige32 ssa_270, ssa_390 vec1 32 div ssa_406 = ineg ssa_229 | vec1 32 div ssa_406 = ige32 ssa_349, ssa_399 vec1 32 div ssa_407 = iadd ssa_196.z, ssa_406 | vec1 32 div ssa_407 = ior ssa_405, ssa_406 vec1 32 div ssa_408 = ineg ssa_230 | vec1 32 div ssa_408 = ige32 ssa_287, ssa_391 vec1 32 div ssa_409 = iadd ssa_196.w, ssa_408 | vec1 32 div ssa_409 = ige32 ssa_366, ssa_400 vec1 32 div ssa_410 = iabs ssa_403 | vec1 32 div ssa_410 = ior ssa_408, ssa_409 vec1 32 div ssa_411 = iabs ssa_405 | vec1 32 div ssa_411 = ige32 ssa_304, ssa_392 vec1 32 div ssa_412 = iabs ssa_407 | vec1 32 div ssa_412 = ige32 ssa_383, ssa_401 vec1 32 div ssa_413 = iabs ssa_409 | vec1 32 div ssa_413 = ior ssa_411, ssa_412 vec1 32 div ssa_414 = ige32 ssa_338, ssa_410 | vec1 32 div ssa_414 = iand ssa_413, ssa_410 vec1 32 div ssa_415 = ige32 ssa_259, ssa_398 | vec1 32 div ssa_415 = iand ssa_414, ssa_407 vec1 32 div ssa_416 = ior ssa_415, ssa_414 | vec1 32 div ssa_416 = iand ssa_415, ssa_404 vec1 32 div ssa_417 = ige32 ssa_276, ssa_399 < vec1 32 div ssa_418 = ige32 ssa_355, ssa_411 < vec1 32 div ssa_419 = ior ssa_417, ssa_418 < vec1 32 div ssa_420 = ige32 ssa_293, ssa_400 < vec1 32 div ssa_421 = ige32 ssa_372, ssa_412 < vec1 32 div ssa_422 = ior ssa_420, ssa_421 < vec1 32 div ssa_423 = ige32 ssa_310, ssa_401 < vec1 32 div ssa_424 = ige32 ssa_389, ssa_413 < vec1 32 div ssa_425 = ior ssa_423, ssa_424 < vec1 32 div ssa_426 = iand ssa_425, ssa_422 < vec1 32 div ssa_427 = iand ssa_426, ssa_419 < vec1 32 div ssa_428 = iand ssa_427, ssa_416 < /* succs: block_15 block_19 */ /* succs: block_15 block_19 */ if ssa_428 { | if ssa_416 { block block_15: block block_15: /* preds: block_14 */ /* preds: block_14 */ vec1 32 con ssa_429 = load_const (0x00000008 = 0.000000) | vec1 32 con ssa_417 = load_const (0x00000008 = 0.000000) vec1 32 con ssa_430 = intrinsic reduce (ssa_37) (reduction_op=iadd /*257*/, cluster_size=0) | vec1 32 con ssa_418 = intrinsic reduce (ssa_37) (reduction_op=iadd /*257*/, cluster_size=0) vec1 32 div ssa_431 = intrinsic first_invocation () () | vec1 32 div ssa_419 = intrinsic first_invocation () () vec1 32 div ssa_432 = intrinsic load_subgroup_invocation () () | vec1 32 div ssa_420 = intrinsic load_subgroup_invocation () () vec1 32 div ssa_433 = ieq32 ssa_432, ssa_431 | vec1 32 div ssa_421 = ieq32 ssa_420, ssa_419 /* succs: block_16 block_17 */ /* succs: block_16 block_17 */ if ssa_433 { | if ssa_421 { block block_16: block block_16: /* preds: block_15 */ /* preds: block_15 */ vec1 32 div ssa_434 = intrinsic ssbo_atomic (ssa_18, ssa_429, ssa_430) (access=1, ato | vec1 32 div ssa_422 = intrinsic ssbo_atomic (ssa_18, ssa_417, ssa_418) (access=1, ato /* succs: block_18 */ /* succs: block_18 */ } else { } else { block block_17: block block_17: /* preds: block_15 */ /* preds: block_15 */ /* succs: block_18 */ /* succs: block_18 */ } } block block_18: block block_18: /* preds: block_16 block_17 */ /* preds: block_16 block_17 */ /* succs: block_20 */ /* succs: block_20 */ } else { } else { block block_19: block block_19: /* preds: block_14 */ /* preds: block_14 */ /* succs: block_20 */ /* succs: block_20 */ } } block block_20: block block_20: /* preds: block_18 block_19 */ /* preds: block_18 block_19 */ vec1 32 div ssa_435 = phi block_18: ssa_8, block_19: ssa_117 | vec1 32 div ssa_423 = phi block_18: ssa_8, block_19: ssa_117 vec1 32 div ssa_436 = phi block_18: ssa_117, block_19: ssa_8 | vec1 32 div ssa_424 = phi block_18: ssa_117, block_19: ssa_8 vec4 32 div ssa_437 = vec4 ssa_435, ssa_436, ssa_8, ssa_117 | vec4 32 div ssa_425 = vec4 ssa_423, ssa_424, ssa_8, ssa_117 vec4 32 div ssa_438 = vec4 ssa_44, ssa_45, ssa_18, ssa_3 | vec4 32 div ssa_426 = vec4 ssa_44, ssa_45, ssa_18, ssa_3 intrinsic image_store (ssa_14, ssa_438, ssa_2, ssa_437, ssa_8) (image_dim=2D /*1*/, image_array=true | intrinsic image_store (ssa_14, ssa_426, ssa_2, ssa_425, ssa_8) (image_dim=2D /*1*/, image_array=true vec4 32 div ssa_439 = (uint32)txf ssa_56 (coord), ssa_8 (lod), 7 (texture) | vec4 32 div ssa_427 = (uint32)txf ssa_56 (coord), ssa_8 (lod), 7 (texture) vec1 32 con ssa_440 = load_const (0x00000074 = 0.000000) | vec1 32 con ssa_428 = load_const (0x00000074 = 0.000000) vec1 32 con ssa_441 = intrinsic load_uniform (ssa_440) (base=0, range=120, dest_type=invalid /*256*/) | vec1 32 con ssa_429 = intrinsic load_uniform (ssa_428) (base=0, range=120, dest_type=invalid /*256*/) vec1 32 con ssa_442 = ineg ssa_441 | vec1 32 con ssa_430 = ineg ssa_429 vec1 32 div ssa_443 = iadd ssa_439.x, ssa_442 | vec1 32 div ssa_431 = iadd ssa_427.x, ssa_430 vec1 32 div ssa_444 = uge32! ssa_8, ssa_443 | vec1 32 div ssa_432 = uge32! ssa_8, ssa_431 /* succs: block_21 block_25 */ /* succs: block_21 block_25 */ if ssa_444 { | if ssa_432 { block block_21: block block_21: /* preds: block_20 */ /* preds: block_20 */ vec1 32 con ssa_445 = intrinsic reduce (ssa_37) (reduction_op=iadd /*257*/, cluster_size=0) | vec1 32 con ssa_433 = intrinsic reduce (ssa_37) (reduction_op=iadd /*257*/, cluster_size=0) vec1 32 div ssa_446 = intrinsic first_invocation () () | vec1 32 div ssa_434 = intrinsic first_invocation () () vec1 32 div ssa_447 = intrinsic load_subgroup_invocation () () | vec1 32 div ssa_435 = intrinsic load_subgroup_invocation () () vec1 32 div ssa_448 = ieq32 ssa_447, ssa_446 | vec1 32 div ssa_436 = ieq32 ssa_435, ssa_434 /* succs: block_22 block_23 */ /* succs: block_22 block_23 */ if ssa_448 { | if ssa_436 { block block_22: block block_22: /* preds: block_21 */ /* preds: block_21 */ vec1 32 div ssa_449 = intrinsic ssbo_atomic (ssa_18, ssa_58, ssa_445) (access=1, atom | vec1 32 div ssa_437 = intrinsic ssbo_atomic (ssa_18, ssa_58, ssa_433) (access=1, atom /* succs: block_24 */ /* succs: block_24 */ } else { } else { block block_23: block block_23: /* preds: block_21 */ /* preds: block_21 */ /* succs: block_24 */ /* succs: block_24 */ } } block block_24: block block_24: /* preds: block_22 block_23 */ /* preds: block_22 block_23 */ /* succs: block_26 */ /* succs: block_26 */ } else { } else { block block_25: block block_25: /* preds: block_20 */ /* preds: block_20 */ /* succs: block_26 */ /* succs: block_26 */ } } block block_26: block block_26: /* preds: block_24 block_25 */ /* preds: block_24 block_25 */ vec1 32 div ssa_450 = phi block_24: ssa_8, block_25: ssa_117 | vec1 32 div ssa_438 = phi block_24: ssa_8, block_25: ssa_117 vec1 32 div ssa_451 = phi block_24: ssa_117, block_25: ssa_8 | vec1 32 div ssa_439 = phi block_24: ssa_117, block_25: ssa_8 vec4 32 div ssa_452 = vec4 ssa_450, ssa_451, ssa_8, ssa_117 | vec4 32 div ssa_440 = vec4 ssa_438, ssa_439, ssa_8, ssa_117 vec4 32 div ssa_453 = vec4 ssa_44, ssa_45, ssa_36, ssa_1 | vec4 32 div ssa_441 = vec4 ssa_44, ssa_45, ssa_36, ssa_1 intrinsic image_store (ssa_14, ssa_453, ssa_0, ssa_452, ssa_8) (image_dim=2D /*1*/, image_array=true | intrinsic image_store (ssa_14, ssa_441, ssa_0, ssa_440, ssa_8) (image_dim=2D /*1*/, image_array=true /* succs: block_27 */ /* succs: block_27 */ } } block block_27: block block_27: /* preds: block_1 block_26 */ /* preds: block_1 block_26 */ /* succs: block_28 */ /* succs: block_28 */ block block_28: block block_28: } } NIR (final form) for compute shader: NIR (final form) for compute shader: shader: MESA_SHADER_COMPUTE shader: MESA_SHADER_COMPUTE source_sha1: {0x4080c608, 0xef4e4e6b, 0x82f838bb, 0x041ba6fe, 0x4a36e587} source_sha1: {0x4080c608, 0xef4e4e6b, 0x82f838bb, 0x041ba6fe, 0x4a36e587} workgroup-size: 8, 8, 1 workgroup-size: 8, 8, 1 shared-size: 0 shared-size: 0 stage: 5 stage: 5 next_stage: 0 next_stage: 0 num_textures: 4 num_textures: 4 num_ssbos: 1 num_ssbos: 1 num_images: 1 num_images: 1 system_values_read: 0x00000000'00000020'00000000 system_values_read: 0x00000000'00000020'00000000 subgroup_size: 2 subgroup_size: 2 divergence_analysis_run: true divergence_analysis_run: true bit_sizes_float: 0x20 bit_sizes_float: 0x20 bit_sizes_int: 0x21 bit_sizes_int: 0x21 separate_shader: true separate_shader: true writes_memory: true writes_memory: true ptr_size: 0 ptr_size: 0 inputs: 0 inputs: 0 outputs: 0 outputs: 0 uniforms: 516 uniforms: 516 decl_var push_const INTERP_MODE_NONE block @0 decl_var push_const INTERP_MODE_NONE block @0 decl_var uniform INTERP_MODE_NONE restrict texture2D @1 (~0, 0, 1) decl_var uniform INTERP_MODE_NONE restrict texture2D @1 (~0, 0, 1) decl_var ssbo INTERP_MODE_NONE restrict writeonly block @2 (~0, 0, 0) decl_var ssbo INTERP_MODE_NONE restrict writeonly block @2 (~0, 0, 0) decl_var image INTERP_MODE_NONE restrict writeonly r8g8b8a8_unorm image2DArray @3 (~0, 0, 6) decl_var image INTERP_MODE_NONE restrict writeonly r8g8b8a8_unorm image2DArray @3 (~0, 0, 6) decl_var uniform INTERP_MODE_NONE restrict texture2D @4 (~0, 0, 2) decl_var uniform INTERP_MODE_NONE restrict texture2D @4 (~0, 0, 2) decl_var uniform INTERP_MODE_NONE restrict itexture2D @5 (~0, 0, 3) decl_var uniform INTERP_MODE_NONE restrict itexture2D @5 (~0, 0, 3) decl_var uniform INTERP_MODE_NONE restrict utexture2D @6 (~0, 0, 5) decl_var uniform INTERP_MODE_NONE restrict utexture2D @6 (~0, 0, 5) decl_function main (0 params) decl_function main (0 params) impl main { impl main { decl_reg vec1 32 div r0 decl_reg vec1 32 div r0 decl_reg vec1 32 div r1 decl_reg vec1 32 div r1 decl_reg vec1 32 div r2 decl_reg vec1 32 div r2 decl_reg vec1 32 div r3 decl_reg vec1 32 div r3 decl_reg vec1 32 div r4 decl_reg vec1 32 div r4 decl_reg vec1 32 div r5 decl_reg vec1 32 div r5 decl_reg vec1 32 div r6 decl_reg vec1 32 div r6 decl_reg vec1 32 div r7 decl_reg vec1 32 div r7 block block_0: block block_0: /* preds: */ /* preds: */ vec1 32 con ssa_0 = undefined vec1 32 con ssa_0 = undefined vec1 32 con ssa_1 = undefined vec1 32 con ssa_1 = undefined vec1 32 con ssa_2 = undefined vec1 32 con ssa_2 = undefined vec1 32 con ssa_3 = undefined vec1 32 con ssa_3 = undefined vec1 32 con ssa_4 = undefined vec1 32 con ssa_4 = undefined vec1 32 con ssa_5 = undefined vec1 32 con ssa_5 = undefined vec1 32 con ssa_6 = undefined vec1 32 con ssa_6 = undefined vec1 32 con ssa_7 = undefined vec1 32 con ssa_7 = undefined vec1 32 con ssa_8 = load_const (0x00000000 = 0.000000) vec1 32 con ssa_8 = load_const (0x00000000 = 0.000000) vec2 32 con ssa_9 = intrinsic load_uniform (ssa_8) (base=504, range=12, dest_type=uint /*4*/) vec2 32 con ssa_9 = intrinsic load_uniform (ssa_8) (base=504, range=12, dest_type=uint /*4*/) vec3 32 con ssa_10 = intrinsic load_workgroup_id_zero_base () () vec3 32 con ssa_10 = intrinsic load_workgroup_id_zero_base () () vec1 32 con ssa_11 = iadd ssa_10.x, ssa_9.x vec1 32 con ssa_11 = iadd ssa_10.x, ssa_9.x vec1 32 con ssa_12 = iadd ssa_10.y, ssa_9.y vec1 32 con ssa_12 = iadd ssa_10.y, ssa_9.y vec1 32 con ssa_13 = intrinsic load_subgroup_id () () vec1 32 con ssa_13 = intrinsic load_subgroup_id () () vec1 32 con ssa_14 = load_const (0x00000003 = 0.000000) vec1 32 con ssa_14 = load_const (0x00000003 = 0.000000) vec1 32 con ssa_15 = ishl ssa_13, ssa_14 vec1 32 con ssa_15 = ishl ssa_13, ssa_14 vec1 32 div ssa_16 = intrinsic load_subgroup_invocation () () vec1 32 div ssa_16 = intrinsic load_subgroup_invocation () () vec1 32 div ssa_17 = iadd ssa_16, ssa_15 vec1 32 div ssa_17 = iadd ssa_16, ssa_15 vec1 32 con ssa_18 = load_const (0x00000002 = 0.000000) vec1 32 con ssa_18 = load_const (0x00000002 = 0.000000) vec1 32 div ssa_19 = ushr ssa_17, ssa_18 vec1 32 div ssa_19 = ushr ssa_17, ssa_18 vec1 32 con ssa_20 = load_const (0x00000007 = 0.000000) vec1 32 con ssa_20 = load_const (0x00000007 = 0.000000) vec1 32 div ssa_21 = iand ssa_19, ssa_20 vec1 32 div ssa_21 = iand ssa_19, ssa_20 vec1 32 con ssa_22 = load_const (0x00000005 = 0.000000) vec1 32 con ssa_22 = load_const (0x00000005 = 0.000000) vec1 32 div ssa_23 = ushr ssa_17, ssa_22 vec1 32 div ssa_23 = ushr ssa_17, ssa_22 vec1 32 div ssa_24 = ishl ssa_23, ssa_18 vec1 32 div ssa_24 = ishl ssa_23, ssa_18 vec1 32 div ssa_25 = iand ssa_17, ssa_14 vec1 32 div ssa_25 = iand ssa_17, ssa_14 vec1 32 div ssa_26 = iadd ssa_25, ssa_24 vec1 32 div ssa_26 = iadd ssa_25, ssa_24 vec1 32 div ssa_27 = iand ssa_26, ssa_20 vec1 32 div ssa_27 = iand ssa_26, ssa_20 vec1 32 con ssa_28 = ishl ssa_11, ssa_14 vec1 32 con ssa_28 = ishl ssa_11, ssa_14 vec1 32 con ssa_29 = ishl ssa_12, ssa_14 vec1 32 con ssa_29 = ishl ssa_12, ssa_14 vec1 32 div ssa_30 = iadd ssa_28, ssa_21 vec1 32 div ssa_30 = iadd ssa_28, ssa_21 vec1 32 div ssa_31 = iadd ssa_29, ssa_27 vec1 32 div ssa_31 = iadd ssa_29, ssa_27 vec4 32 con ssa_32 = intrinsic load_uniform (ssa_8) (base=0, range=120, dest_type=invalid /*256*/) vec4 32 con ssa_32 = intrinsic load_uniform (ssa_8) (base=0, range=120, dest_type=invalid /*256*/) vec1 32 div ssa_33 = uge32 ssa_31, ssa_32.w vec1 32 div ssa_33 = uge32 ssa_31, ssa_32.w vec1 32 div ssa_34 = uge32 ssa_30, ssa_32.z vec1 32 div ssa_34 = uge32 ssa_30, ssa_32.z vec1 32 div ssa_35 = ior ssa_33, ssa_34 vec1 32 div ssa_35 = ior ssa_33, ssa_34 /* succs: block_1 block_2 */ /* succs: block_1 block_2 */ if ssa_35 { if ssa_35 { block block_1: block block_1: /* preds: block_0 */ /* preds: block_0 */ /* succs: block_27 */ /* succs: block_27 */ } else { } else { block block_2: block block_2: /* preds: block_0 */ /* preds: block_0 */ vec1 32 con ssa_36 = load_const (0x00000004 = 0.000000) vec1 32 con ssa_36 = load_const (0x00000004 = 0.000000) vec1 32 con ssa_37 = load_const (0x00000001 = 0.000000) vec1 32 con ssa_37 = load_const (0x00000001 = 0.000000) vec1 32 con ssa_38 = load_const (0xffffffac = -nan) vec1 32 con ssa_38 = load_const (0xffffffac = -nan) vec1 32 con ssa_39 = load_const (0xffffffe0 = -nan) vec1 32 con ssa_39 = load_const (0xffffffe0 = -nan) vec1 32 con ssa_40 = load_const (0xffffff9d = -nan) vec1 32 con ssa_40 = load_const (0xffffff9d = -nan) vec1 32 con ssa_41 = load_const (0x3b000000 = 0.001953) vec1 32 con ssa_41 = load_const (0x3b000000 = 0.001953) vec1 32 con ssa_42 = load_const (0x3c008081 = 0.007843) vec1 32 con ssa_42 = load_const (0x3c008081 = 0.007843) vec1 32 con ssa_43 = load_const (0x3f000000 = 0.500000) vec1 32 con ssa_43 = load_const (0x3f000000 = 0.500000) vec1 32 div ssa_44 = iadd ssa_32.x, ssa_30 vec1 32 div ssa_44 = iadd ssa_32.x, ssa_30 vec1 32 div ssa_45 = iadd ssa_32.y, ssa_31 vec1 32 div ssa_45 = iadd ssa_32.y, ssa_31 vec1 32 div ssa_46 = u2f32 ssa_30 vec1 32 div ssa_46 = u2f32 ssa_30 vec1 32 div ssa_47 = u2f32 ssa_31 vec1 32 div ssa_47 = u2f32 ssa_31 vec1 32 div ssa_48 = fadd ssa_46, ssa_43 vec1 32 div ssa_48 = fadd ssa_46, ssa_43 vec1 32 div ssa_49 = fadd ssa_47, ssa_43 vec1 32 div ssa_49 = fadd ssa_47, ssa_43 vec1 32 con ssa_50 = u2f32 ssa_32.z vec1 32 con ssa_50 = u2f32 ssa_32.z vec1 32 con ssa_51 = u2f32 ssa_32.w vec1 32 con ssa_51 = u2f32 ssa_32.w vec1 32 con ssa_52 = frcp ssa_50 vec1 32 con ssa_52 = frcp ssa_50 vec1 32 div ssa_53 = fmul ssa_48, ssa_52 vec1 32 div ssa_53 = fmul ssa_48, ssa_52 vec1 32 con ssa_54 = frcp ssa_51 vec1 32 con ssa_54 = frcp ssa_51 vec1 32 div ssa_55 = fmul ssa_49, ssa_54 vec1 32 div ssa_55 = fmul ssa_49, ssa_54 vec2 32 div ssa_56 = vec2 ssa_44, ssa_45 vec2 32 div ssa_56 = vec2 ssa_44, ssa_45 vec4 32 div ssa_57 = (float32)txf ssa_56 (coord), ssa_8 (lod), 4 (texture) vec4 32 div ssa_57 = (float32)txf ssa_56 (coord), ssa_8 (lod), 4 (texture) vec1 32 con ssa_58 = load_const (0x00000010 = 0.000000) vec1 32 con ssa_58 = load_const (0x00000010 = 0.000000) vec4 32 con ssa_59 = intrinsic load_uniform (ssa_58) (base=0, range=120, dest_type=invalid /*256*/) vec4 32 con ssa_59 = intrinsic load_uniform (ssa_58) (base=0, range=120, dest_type=invalid /*256*/) vec1 32 con ssa_60 = load_const (0x00000020 = 0.000000) vec1 32 con ssa_60 = load_const (0x00000020 = 0.000000) vec4 32 con ssa_61 = intrinsic load_uniform (ssa_60) (base=0, range=120, dest_type=invalid /*256*/) vec4 32 con ssa_61 = intrinsic load_uniform (ssa_60) (base=0, range=120, dest_type=invalid /*256*/) vec1 32 con ssa_62 = fneg ssa_61.x vec1 32 con ssa_62 = fneg ssa_61.x vec1 32 div ssa_63 = fmul ssa_62, ssa_55 vec1 32 div ssa_63 = fmul ssa_62, ssa_55 vec1 32 con ssa_64 = fneg ssa_61.y vec1 32 con ssa_64 = fneg ssa_61.y vec1 32 div ssa_65 = fmul ssa_64, ssa_55 vec1 32 div ssa_65 = fmul ssa_64, ssa_55 vec1 32 con ssa_66 = fneg ssa_61.z vec1 32 con ssa_66 = fneg ssa_61.z vec1 32 div ssa_67 = fmul ssa_66, ssa_55 vec1 32 div ssa_67 = fmul ssa_66, ssa_55 vec1 32 con ssa_68 = fneg ssa_61.w vec1 32 con ssa_68 = fneg ssa_61.w vec1 32 div ssa_69 = fmul ssa_68, ssa_55 vec1 32 div ssa_69 = fmul ssa_68, ssa_55 vec1 32 con ssa_70 = fneg ssa_59.x vec1 32 con ssa_70 = fneg ssa_59.x vec1 32 div ssa_71 = ffma ssa_70, ssa_53, ssa_63 vec1 32 div ssa_71 = ffma ssa_70, ssa_53, ssa_63 vec1 32 con ssa_72 = fneg ssa_59.y vec1 32 con ssa_72 = fneg ssa_59.y vec1 32 div ssa_73 = ffma ssa_72, ssa_53, ssa_65 vec1 32 div ssa_73 = ffma ssa_72, ssa_53, ssa_65 vec1 32 con ssa_74 = fneg ssa_59.z vec1 32 con ssa_74 = fneg ssa_59.z vec1 32 div ssa_75 = ffma ssa_74, ssa_53, ssa_67 vec1 32 div ssa_75 = ffma ssa_74, ssa_53, ssa_67 vec1 32 con ssa_76 = fneg ssa_59.w vec1 32 con ssa_76 = fneg ssa_59.w vec1 32 div ssa_77 = ffma ssa_76, ssa_53, ssa_69 vec1 32 div ssa_77 = ffma ssa_76, ssa_53, ssa_69 vec1 32 con ssa_78 = load_const (0xbd85573d = -0.065108) vec1 32 con ssa_78 = load_const (0xbd85573d = -0.065108) vec1 32 div ssa_79 = ffma ssa_71, ssa_43, ssa_78 vec1 32 div ssa_79 = ffma ssa_71, ssa_43, ssa_78 vec1 32 con ssa_80 = load_const (0xbdc88c03 = -0.097923) vec1 32 con ssa_80 = load_const (0xbdc88c03 = -0.097923) vec1 32 div ssa_81 = ffma ssa_73, ssa_43, ssa_80 vec1 32 div ssa_81 = ffma ssa_73, ssa_43, ssa_80 vec1 32 con ssa_82 = load_const (0xbd9d07d6 = -0.076675) vec1 32 con ssa_82 = load_const (0xbd9d07d6 = -0.076675) vec1 32 div ssa_83 = ffma ssa_75, ssa_43, ssa_82 vec1 32 div ssa_83 = ffma ssa_75, ssa_43, ssa_82 vec1 32 con ssa_84 = load_const (0xbd97cde7 = -0.074123) vec1 32 con ssa_84 = load_const (0xbd97cde7 = -0.074123) vec1 32 div ssa_85 = ffma ssa_77, ssa_43, ssa_84 vec1 32 div ssa_85 = ffma ssa_77, ssa_43, ssa_84 vec1 32 con ssa_86 = fmul ssa_59.x, ssa_52 vec1 32 con ssa_86 = fmul ssa_59.x, ssa_52 vec1 32 con ssa_87 = fmul ssa_59.y, ssa_52 vec1 32 con ssa_87 = fmul ssa_59.y, ssa_52 vec1 32 con ssa_88 = fmul ssa_59.z, ssa_52 vec1 32 con ssa_88 = fmul ssa_59.z, ssa_52 vec1 32 con ssa_89 = fmul ssa_59.w, ssa_52 vec1 32 con ssa_89 = fmul ssa_59.w, ssa_52 vec1 32 con ssa_90 = fmul ssa_61.x, ssa_54 vec1 32 con ssa_90 = fmul ssa_61.x, ssa_54 vec1 32 con ssa_91 = fmul ssa_61.y, ssa_54 vec1 32 con ssa_91 = fmul ssa_61.y, ssa_54 vec1 32 con ssa_92 = fmul ssa_61.z, ssa_54 vec1 32 con ssa_92 = fmul ssa_61.z, ssa_54 vec1 32 con ssa_93 = fmul ssa_61.w, ssa_54 vec1 32 con ssa_93 = fmul ssa_61.w, ssa_54 vec1 32 con ssa_94 = fmax ssa_86, ssa_90 vec1 32 con ssa_94 = fmax ssa_86, ssa_90 vec1 32 con ssa_95 = fmax ssa_87, ssa_91 vec1 32 con ssa_95 = fmax ssa_87, ssa_91 vec1 32 con ssa_96 = fmax ssa_88, ssa_92 vec1 32 con ssa_96 = fmax ssa_88, ssa_92 vec1 32 con ssa_97 = fmax ssa_89, ssa_93 vec1 32 con ssa_97 = fmax ssa_89, ssa_93 vec1 32 con ssa_98 = fadd ssa_94, ssa_42 vec1 32 con ssa_98 = fadd ssa_94, ssa_42 vec1 32 con ssa_99 = fadd ssa_95, ssa_42 vec1 32 con ssa_99 = fadd ssa_95, ssa_42 vec1 32 con ssa_100 = fadd ssa_96, ssa_42 vec1 32 con ssa_100 = fadd ssa_96, ssa_42 vec1 32 con ssa_101 = fadd ssa_97, ssa_42 vec1 32 con ssa_101 = fadd ssa_97, ssa_42 vec1 32 div ssa_102 = fadd ssa_57.x, ssa_79 vec1 32 div ssa_102 = fadd ssa_57.x, ssa_79 vec1 32 div ssa_103 = fadd ssa_57.y, ssa_81 vec1 32 div ssa_103 = fadd ssa_57.y, ssa_81 vec1 32 div ssa_104 = fadd ssa_57.z, ssa_83 vec1 32 div ssa_104 = fadd ssa_57.z, ssa_83 vec1 32 div ssa_105 = fadd ssa_57.w, ssa_85 vec1 32 div ssa_105 = fadd ssa_57.w, ssa_85 vec1 32 div ssa_106 = fabs ssa_102 vec1 32 div ssa_106 = fabs ssa_102 vec1 32 div ssa_107 = fabs ssa_103 vec1 32 div ssa_107 = fabs ssa_103 vec1 32 div ssa_108 = fabs ssa_104 vec1 32 div ssa_108 = fabs ssa_104 vec1 32 div ssa_109 = fabs ssa_105 vec1 32 div ssa_109 = fabs ssa_105 vec1 32 div ssa_110 = flt32! ssa_109, ssa_101 vec1 32 div ssa_110 = flt32! ssa_109, ssa_101 vec1 32 div ssa_111 = flt32! ssa_108, ssa_100 vec1 32 div ssa_111 = flt32! ssa_108, ssa_100 vec1 32 div ssa_112 = iand ssa_110, ssa_111 vec1 32 div ssa_112 = iand ssa_110, ssa_111 vec1 32 div ssa_113 = flt32! ssa_107, ssa_99 vec1 32 div ssa_113 = flt32! ssa_107, ssa_99 vec1 32 div ssa_114 = iand ssa_112, ssa_113 vec1 32 div ssa_114 = iand ssa_112, ssa_113 vec1 32 div ssa_115 = flt32! ssa_106, ssa_98 vec1 32 div ssa_115 = flt32! ssa_106, ssa_98 vec1 32 div ssa_116 = iand ssa_114, ssa_115 vec1 32 div ssa_116 = iand ssa_114, ssa_115 vec1 32 con ssa_117 = load_const (0x3f800000 = 1.000000) vec1 32 con ssa_117 = load_const (0x3f800000 = 1.000000) /* succs: block_3 block_7 */ /* succs: block_3 block_7 */ if ssa_116 { if ssa_116 { block block_3: block block_3: /* preds: block_2 */ /* preds: block_2 */ vec1 32 con ssa_118 = intrinsic reduce (ssa_37) (reduction_op=iadd /*257*/, cluster_size=0) vec1 32 con ssa_118 = intrinsic reduce (ssa_37) (reduction_op=iadd /*257*/, cluster_size=0) vec1 32 div ssa_119 = intrinsic first_invocation () () vec1 32 div ssa_119 = intrinsic first_invocation () () vec1 32 div ssa_120 = intrinsic load_subgroup_invocation () () vec1 32 div ssa_120 = intrinsic load_subgroup_invocation () () vec1 32 div ssa_121 = ieq32 ssa_120, ssa_119 vec1 32 div ssa_121 = ieq32 ssa_120, ssa_119 /* succs: block_4 block_5 */ /* succs: block_4 block_5 */ if ssa_121 { if ssa_121 { block block_4: block block_4: /* preds: block_3 */ /* preds: block_3 */ vec1 32 div ssa_122 = intrinsic ssbo_atomic (ssa_18, ssa_8, ssa_118) (access=1, atomi vec1 32 div ssa_122 = intrinsic ssbo_atomic (ssa_18, ssa_8, ssa_118) (access=1, atomi /* succs: block_6 */ /* succs: block_6 */ } else { } else { block block_5: block block_5: /* preds: block_3 */ /* preds: block_3 */ /* succs: block_6 */ /* succs: block_6 */ } } block block_6: block block_6: /* preds: block_4 block_5 */ /* preds: block_4 block_5 */ div r1 = mov ssa_117 div r1 = mov ssa_117 div r0 = mov ssa_8 div r0 = mov ssa_8 /* succs: block_8 */ /* succs: block_8 */ } else { } else { block block_7: block block_7: /* preds: block_2 */ /* preds: block_2 */ div r1 = mov ssa_8 div r1 = mov ssa_8 div r0 = mov ssa_117 div r0 = mov ssa_117 /* succs: block_8 */ /* succs: block_8 */ } } block block_8: block block_8: /* preds: block_6 block_7 */ /* preds: block_6 block_7 */ vec4 32 div ssa_125 = vec4 r0, r1, ssa_8, ssa_117 vec4 32 div ssa_125 = vec4 r0, r1, ssa_8, ssa_117 vec4 32 div ssa_126 = vec4 ssa_44, ssa_45, ssa_8, ssa_7 vec4 32 div ssa_126 = vec4 ssa_44, ssa_45, ssa_8, ssa_7 intrinsic image_store (ssa_14, ssa_126, ssa_6, ssa_125, ssa_8) (image_dim=2D /*1*/, image_array=true intrinsic image_store (ssa_14, ssa_126, ssa_6, ssa_125, ssa_8) (image_dim=2D /*1*/, image_array=true vec4 32 div ssa_127 = (float32)txf ssa_56 (coord), ssa_8 (lod), 5 (texture) vec4 32 div ssa_127 = (float32)txf ssa_56 (coord), ssa_8 (lod), 5 (texture) vec1 32 con ssa_128 = load_const (0x00000030 = 0.000000) vec1 32 con ssa_128 = load_const (0x00000030 = 0.000000) vec4 32 con ssa_129 = intrinsic load_uniform (ssa_128) (base=0, range=120, dest_type=invalid /*256*/) vec4 32 con ssa_129 = intrinsic load_uniform (ssa_128) (base=0, range=120, dest_type=invalid /*256*/) vec1 32 con ssa_130 = load_const (0x00000040 = 0.000000) vec1 32 con ssa_130 = load_const (0x00000040 = 0.000000) vec4 32 con ssa_131 = intrinsic load_uniform (ssa_130) (base=0, range=120, dest_type=invalid /*256*/) vec4 32 con ssa_131 = intrinsic load_uniform (ssa_130) (base=0, range=120, dest_type=invalid /*256*/) vec1 32 con ssa_132 = fneg ssa_131.x vec1 32 con ssa_132 = fneg ssa_131.x vec1 32 div ssa_133 = fmul ssa_132, ssa_55 vec1 32 div ssa_133 = fmul ssa_132, ssa_55 vec1 32 con ssa_134 = fneg ssa_131.y vec1 32 con ssa_134 = fneg ssa_131.y vec1 32 div ssa_135 = fmul ssa_134, ssa_55 vec1 32 div ssa_135 = fmul ssa_134, ssa_55 vec1 32 con ssa_136 = fneg ssa_131.z vec1 32 con ssa_136 = fneg ssa_131.z vec1 32 div ssa_137 = fmul ssa_136, ssa_55 vec1 32 div ssa_137 = fmul ssa_136, ssa_55 vec1 32 con ssa_138 = fneg ssa_131.w vec1 32 con ssa_138 = fneg ssa_131.w vec1 32 div ssa_139 = fmul ssa_138, ssa_55 vec1 32 div ssa_139 = fmul ssa_138, ssa_55 vec1 32 con ssa_140 = fneg ssa_129.x vec1 32 con ssa_140 = fneg ssa_129.x vec1 32 div ssa_141 = ffma ssa_140, ssa_53, ssa_133 vec1 32 div ssa_141 = ffma ssa_140, ssa_53, ssa_133 vec1 32 con ssa_142 = fneg ssa_129.y vec1 32 con ssa_142 = fneg ssa_129.y vec1 32 div ssa_143 = ffma ssa_142, ssa_53, ssa_135 vec1 32 div ssa_143 = ffma ssa_142, ssa_53, ssa_135 vec1 32 con ssa_144 = fneg ssa_129.z vec1 32 con ssa_144 = fneg ssa_129.z vec1 32 div ssa_145 = ffma ssa_144, ssa_53, ssa_137 vec1 32 div ssa_145 = ffma ssa_144, ssa_53, ssa_137 vec1 32 con ssa_146 = fneg ssa_129.w vec1 32 con ssa_146 = fneg ssa_129.w vec1 32 div ssa_147 = ffma ssa_146, ssa_53, ssa_139 vec1 32 div ssa_147 = ffma ssa_146, ssa_53, ssa_139 vec1 32 con ssa_148 = load_const (0xbdc381f3 = -0.095463) vec1 32 con ssa_148 = load_const (0xbdc381f3 = -0.095463) vec1 32 div ssa_149 = ffma ssa_141, ssa_43, ssa_148 vec1 32 div ssa_149 = ffma ssa_141, ssa_43, ssa_148 vec1 32 con ssa_150 = load_const (0xbdc9c363 = -0.098517) vec1 32 con ssa_150 = load_const (0xbdc9c363 = -0.098517) vec1 32 div ssa_151 = ffma ssa_143, ssa_43, ssa_150 vec1 32 div ssa_151 = ffma ssa_143, ssa_43, ssa_150 vec1 32 con ssa_152 = load_const (0xbdc52221 = -0.096257) vec1 32 con ssa_152 = load_const (0xbdc52221 = -0.096257) vec1 32 div ssa_153 = ffma ssa_145, ssa_43, ssa_152 vec1 32 div ssa_153 = ffma ssa_145, ssa_43, ssa_152 vec1 32 con ssa_154 = load_const (0xbd9e4e34 = -0.077298) vec1 32 con ssa_154 = load_const (0xbd9e4e34 = -0.077298) vec1 32 div ssa_155 = ffma ssa_147, ssa_43, ssa_154 vec1 32 div ssa_155 = ffma ssa_147, ssa_43, ssa_154 vec1 32 con ssa_156 = fmul ssa_129.x, ssa_52 vec1 32 con ssa_156 = fmul ssa_129.x, ssa_52 vec1 32 con ssa_157 = fmul ssa_129.y, ssa_52 vec1 32 con ssa_157 = fmul ssa_129.y, ssa_52 vec1 32 con ssa_158 = fmul ssa_129.z, ssa_52 vec1 32 con ssa_158 = fmul ssa_129.z, ssa_52 vec1 32 con ssa_159 = fmul ssa_129.w, ssa_52 vec1 32 con ssa_159 = fmul ssa_129.w, ssa_52 vec1 32 con ssa_160 = fmul ssa_131.x, ssa_54 vec1 32 con ssa_160 = fmul ssa_131.x, ssa_54 vec1 32 con ssa_161 = fmul ssa_131.y, ssa_54 vec1 32 con ssa_161 = fmul ssa_131.y, ssa_54 vec1 32 con ssa_162 = fmul ssa_131.z, ssa_54 vec1 32 con ssa_162 = fmul ssa_131.z, ssa_54 vec1 32 con ssa_163 = fmul ssa_131.w, ssa_54 vec1 32 con ssa_163 = fmul ssa_131.w, ssa_54 vec1 32 con ssa_164 = fmax ssa_156, ssa_160 vec1 32 con ssa_164 = fmax ssa_156, ssa_160 vec1 32 con ssa_165 = fmax ssa_157, ssa_161 vec1 32 con ssa_165 = fmax ssa_157, ssa_161 vec1 32 con ssa_166 = fmax ssa_158, ssa_162 vec1 32 con ssa_166 = fmax ssa_158, ssa_162 vec1 32 con ssa_167 = fmax ssa_159, ssa_163 vec1 32 con ssa_167 = fmax ssa_159, ssa_163 vec1 32 con ssa_168 = fadd ssa_164, ssa_41 vec1 32 con ssa_168 = fadd ssa_164, ssa_41 vec1 32 con ssa_169 = fadd ssa_165, ssa_41 vec1 32 con ssa_169 = fadd ssa_165, ssa_41 vec1 32 con ssa_170 = fadd ssa_166, ssa_41 vec1 32 con ssa_170 = fadd ssa_166, ssa_41 vec1 32 con ssa_171 = fadd ssa_167, ssa_41 vec1 32 con ssa_171 = fadd ssa_167, ssa_41 vec1 32 div ssa_172 = fadd ssa_127.x, ssa_149 vec1 32 div ssa_172 = fadd ssa_127.x, ssa_149 vec1 32 div ssa_173 = fadd ssa_127.y, ssa_151 vec1 32 div ssa_173 = fadd ssa_127.y, ssa_151 vec1 32 div ssa_174 = fadd ssa_127.z, ssa_153 vec1 32 div ssa_174 = fadd ssa_127.z, ssa_153 vec1 32 div ssa_175 = fadd ssa_127.w, ssa_155 vec1 32 div ssa_175 = fadd ssa_127.w, ssa_155 vec1 32 div ssa_176 = fabs ssa_172 vec1 32 div ssa_176 = fabs ssa_172 vec1 32 div ssa_177 = fabs ssa_173 vec1 32 div ssa_177 = fabs ssa_173 vec1 32 div ssa_178 = fabs ssa_174 vec1 32 div ssa_178 = fabs ssa_174 vec1 32 div ssa_179 = fabs ssa_175 vec1 32 div ssa_179 = fabs ssa_175 vec1 32 div ssa_180 = flt32! ssa_179, ssa_171 vec1 32 div ssa_180 = flt32! ssa_179, ssa_171 vec1 32 div ssa_181 = flt32! ssa_178, ssa_170 vec1 32 div ssa_181 = flt32! ssa_178, ssa_170 vec1 32 div ssa_182 = iand ssa_180, ssa_181 vec1 32 div ssa_182 = iand ssa_180, ssa_181 vec1 32 div ssa_183 = flt32! ssa_177, ssa_169 vec1 32 div ssa_183 = flt32! ssa_177, ssa_169 vec1 32 div ssa_184 = iand ssa_182, ssa_183 vec1 32 div ssa_184 = iand ssa_182, ssa_183 vec1 32 div ssa_185 = flt32! ssa_176, ssa_168 vec1 32 div ssa_185 = flt32! ssa_176, ssa_168 vec1 32 div ssa_186 = iand ssa_184, ssa_185 vec1 32 div ssa_186 = iand ssa_184, ssa_185 /* succs: block_9 block_13 */ /* succs: block_9 block_13 */ if ssa_186 { if ssa_186 { block block_9: block block_9: /* preds: block_8 */ /* preds: block_8 */ vec1 32 con ssa_187 = intrinsic reduce (ssa_37) (reduction_op=iadd /*257*/, cluster_size=0) vec1 32 con ssa_187 = intrinsic reduce (ssa_37) (reduction_op=iadd /*257*/, cluster_size=0) vec1 32 div ssa_188 = intrinsic first_invocation () () vec1 32 div ssa_188 = intrinsic first_invocation () () vec1 32 div ssa_189 = intrinsic load_subgroup_invocation () () vec1 32 div ssa_189 = intrinsic load_subgroup_invocation () () vec1 32 div ssa_190 = ieq32 ssa_189, ssa_188 vec1 32 div ssa_190 = ieq32 ssa_189, ssa_188 /* succs: block_10 block_11 */ /* succs: block_10 block_11 */ if ssa_190 { if ssa_190 { block block_10: block block_10: /* preds: block_9 */ /* preds: block_9 */ vec1 32 div ssa_191 = intrinsic ssbo_atomic (ssa_18, ssa_36, ssa_187) (access=1, atom vec1 32 div ssa_191 = intrinsic ssbo_atomic (ssa_18, ssa_36, ssa_187) (access=1, atom /* succs: block_12 */ /* succs: block_12 */ } else { } else { block block_11: block block_11: /* preds: block_9 */ /* preds: block_9 */ /* succs: block_12 */ /* succs: block_12 */ } } block block_12: block block_12: /* preds: block_10 block_11 */ /* preds: block_10 block_11 */ div r3 = mov ssa_117 div r3 = mov ssa_117 div r2 = mov ssa_8 div r2 = mov ssa_8 /* succs: block_14 */ /* succs: block_14 */ } else { } else { block block_13: block block_13: /* preds: block_8 */ /* preds: block_8 */ div r3 = mov ssa_8 div r3 = mov ssa_8 div r2 = mov ssa_117 div r2 = mov ssa_117 /* succs: block_14 */ /* succs: block_14 */ } } block block_14: block block_14: /* preds: block_12 block_13 */ /* preds: block_12 block_13 */ vec4 32 div ssa_194 = vec4 r2, r3, ssa_8, ssa_117 vec4 32 div ssa_194 = vec4 r2, r3, ssa_8, ssa_117 vec4 32 div ssa_195 = vec4 ssa_44, ssa_45, ssa_37, ssa_5 vec4 32 div ssa_195 = vec4 ssa_44, ssa_45, ssa_37, ssa_5 intrinsic image_store (ssa_14, ssa_195, ssa_4, ssa_194, ssa_8) (image_dim=2D /*1*/, image_array=true intrinsic image_store (ssa_14, ssa_195, ssa_4, ssa_194, ssa_8) (image_dim=2D /*1*/, image_array=true vec4 32 div ssa_196 = (int32)txf ssa_56 (coord), ssa_8 (lod), 6 (texture) vec4 32 div ssa_196 = (int32)txf ssa_56 (coord), ssa_8 (lod), 6 (texture) vec1 32 con ssa_197 = load_const (0x00000050 = 0.000000) vec1 32 con ssa_197 = load_const (0x00000050 = 0.000000) vec4 32 con ssa_198 = intrinsic load_uniform (ssa_197) (base=0, range=120, dest_type=invalid /*256*/) vec4 32 con ssa_198 = intrinsic load_uniform (ssa_197) (base=0, range=120, dest_type=invalid /*256*/) vec1 32 con ssa_199 = i2f32 ssa_198.x vec1 32 con ssa_199 = i2f32 ssa_198.x vec1 32 con ssa_200 = i2f32 ssa_198.y vec1 32 con ssa_200 = i2f32 ssa_198.y vec1 32 con ssa_201 = i2f32 ssa_198.z vec1 32 con ssa_201 = i2f32 ssa_198.z vec1 32 con ssa_202 = i2f32 ssa_198.w vec1 32 con ssa_202 = i2f32 ssa_198.w vec1 32 div ssa_203 = fmul ssa_199, ssa_53 vec1 32 div ssa_203 = fmul ssa_199, ssa_53 vec1 32 div ssa_204 = fmul ssa_200, ssa_53 vec1 32 div ssa_204 = fmul ssa_200, ssa_53 vec1 32 div ssa_205 = fmul ssa_201, ssa_53 vec1 32 div ssa_205 = fmul ssa_201, ssa_53 vec1 32 div ssa_206 = fmul ssa_202, ssa_53 vec1 32 div ssa_206 = fmul ssa_202, ssa_53 vec1 32 div ssa_207 = f2i32 ssa_203 vec1 32 div ssa_207 = f2i32 ssa_203 vec1 32 div ssa_208 = f2i32 ssa_204 vec1 32 div ssa_208 = f2i32 ssa_204 vec1 32 div ssa_209 = f2i32 ssa_205 vec1 32 div ssa_209 = f2i32 ssa_205 vec1 32 div ssa_210 = f2i32 ssa_206 vec1 32 div ssa_210 = f2i32 ssa_206 vec1 32 div ssa_211 = iadd ssa_208, ssa_38 | vec1 32 con ssa_211 = load_const (0x00000060 = 0.000000) vec1 32 div ssa_212 = iadd ssa_209, ssa_39 | vec4 32 con ssa_212 = intrinsic load_uniform (ssa_211) (base=0, range=120, dest_type=invalid /*256*/) vec1 32 div ssa_213 = iadd ssa_210, ssa_40 | vec1 32 con ssa_213 = i2f32 ssa_212.x vec1 32 con ssa_214 = load_const (0x00000060 = 0.000000) | vec1 32 con ssa_214 = i2f32 ssa_212.y vec4 32 con ssa_215 = intrinsic load_uniform (ssa_214) (base=0, range=120, dest_type=invalid /*256*/) | vec1 32 con ssa_215 = i2f32 ssa_212.z vec1 32 con ssa_216 = i2f32 ssa_215.x | vec1 32 con ssa_216 = i2f32 ssa_212.w vec1 32 con ssa_217 = i2f32 ssa_215.y | vec1 32 div ssa_217 = fmul ssa_213, ssa_55 vec1 32 con ssa_218 = i2f32 ssa_215.z | vec1 32 div ssa_218 = fmul ssa_214, ssa_55 vec1 32 con ssa_219 = i2f32 ssa_215.w | vec1 32 div ssa_219 = fmul ssa_215, ssa_55 vec1 32 div ssa_220 = fmul ssa_216, ssa_55 vec1 32 div ssa_220 = fmul ssa_216, ssa_55 vec1 32 div ssa_221 = fmul ssa_217, ssa_55 | vec1 32 div ssa_221 = f2i32 ssa_217 vec1 32 div ssa_222 = fmul ssa_218, ssa_55 | vec1 32 div ssa_222 = f2i32 ssa_218 vec1 32 div ssa_223 = fmul ssa_219, ssa_55 | vec1 32 div ssa_223 = f2i32 ssa_219 vec1 32 div ssa_224 = f2i32 ssa_220 vec1 32 div ssa_224 = f2i32 ssa_220 vec1 32 div ssa_225 = f2i32 ssa_221 | vec1 32 con ssa_225 = iabs! ssa_198.x vec1 32 div ssa_226 = f2i32 ssa_222 | vec1 32 con ssa_226 = iabs! ssa_32.z vec1 32 div ssa_227 = f2i32 ssa_223 | vec1 32 con ssa_227 = ilt32! ssa_198.x, ssa_8 vec1 32 div ssa_228 = iadd ssa_225, ssa_38 | vec1 32 con ssa_228 = ilt32! ssa_32.z, ssa_8 vec1 32 div ssa_229 = iadd ssa_226, ssa_39 | vec1 32 con ssa_229 = ixor! ssa_227, ssa_228 vec1 32 div ssa_230 = iadd ssa_227, ssa_40 | vec1 32 con ssa_230 = u2f32! ssa_226 vec1 32 con ssa_231 = iabs! ssa_198.x | vec1 32 con ssa_231 = frcp! ssa_230 vec1 32 con ssa_232 = iabs! ssa_32.z | vec1 32 con ssa_232 = load_const (0x4f7ffffe = 4294966784.000000) vec1 32 con ssa_233 = ilt32! ssa_198.x, ssa_8 | vec1 32 con ssa_233 = fmul! ssa_231, ssa_232 vec1 32 con ssa_234 = ilt32! ssa_32.z, ssa_8 | vec1 32 con ssa_234 = f2u32! ssa_233 vec1 32 con ssa_235 = ixor! ssa_233, ssa_234 | vec1 32 con ssa_235 = ineg! ssa_226 vec1 32 con ssa_236 = u2f32! ssa_232 | vec1 32 con ssa_236 = imul! ssa_226, ssa_234 vec1 32 con ssa_237 = frcp! ssa_236 | vec1 32 con ssa_237 = ineg! ssa_236 vec1 32 con ssa_238 = load_const (0x4f7ffffe = 4294966784.000000) | vec1 32 con ssa_238 = umul_high! ssa_234, ssa_237 vec1 32 con ssa_239 = fmul! ssa_237, ssa_238 | vec1 32 con ssa_239 = iadd! ssa_234, ssa_238 vec1 32 con ssa_240 = f2u32! ssa_239 | vec1 32 con ssa_240 = umul_high! ssa_225, ssa_239 vec1 32 con ssa_241 = ineg! ssa_232 | vec1 32 con ssa_241 = imul! ssa_240, ssa_226 vec1 32 con ssa_242 = imul! ssa_232, ssa_240 | vec1 32 con ssa_242 = ineg! ssa_241 vec1 32 con ssa_243 = ineg! ssa_242 | vec1 32 con ssa_243 = iadd! ssa_225, ssa_242 vec1 32 con ssa_244 = umul_high! ssa_240, ssa_243 | vec1 32 con ssa_244 = iadd! ssa_240, ssa_37 vec1 32 con ssa_245 = iadd! ssa_240, ssa_244 | vec1 32 con ssa_245 = uge32! ssa_243, ssa_226 vec1 32 con ssa_246 = umul_high! ssa_231, ssa_245 | vec1 32 con ssa_246 = b32csel! ssa_245, ssa_244, ssa_240 vec1 32 con ssa_247 = imul! ssa_246, ssa_232 | vec1 32 con ssa_247 = iadd! ssa_243, ssa_235 vec1 32 con ssa_248 = ineg! ssa_247 | vec1 32 con ssa_248 = b32csel! ssa_245, ssa_247, ssa_243 vec1 32 con ssa_249 = iadd! ssa_231, ssa_248 | vec1 32 con ssa_249 = iadd! ssa_246, ssa_37 vec1 32 con ssa_250 = iadd! ssa_246, ssa_37 | vec1 32 con ssa_250 = uge32! ssa_248, ssa_226 vec1 32 con ssa_251 = uge32! ssa_249, ssa_232 | vec1 32 con ssa_251 = b32csel! ssa_250, ssa_249, ssa_246 vec1 32 con ssa_252 = b32csel! ssa_251, ssa_250, ssa_246 | vec1 32 con ssa_252 = ineg! ssa_251 vec1 32 con ssa_253 = iadd! ssa_249, ssa_241 | vec1 32 con ssa_253 = b32csel! ssa_229, ssa_252, ssa_251 vec1 32 con ssa_254 = b32csel! ssa_251, ssa_253, ssa_249 | vec1 32 con ssa_254 = iabs! ssa_198.y vec1 32 con ssa_255 = iadd! ssa_252, ssa_37 | vec1 32 con ssa_255 = ilt32! ssa_198.y, ssa_8 vec1 32 con ssa_256 = uge32! ssa_254, ssa_232 | vec1 32 con ssa_256 = ixor! ssa_255, ssa_228 vec1 32 con ssa_257 = b32csel! ssa_256, ssa_255, ssa_252 | vec1 32 con ssa_257 = umul_high! ssa_254, ssa_239 vec1 32 con ssa_258 = ineg! ssa_257 | vec1 32 con ssa_258 = imul! ssa_257, ssa_226 vec1 32 con ssa_259 = b32csel! ssa_235, ssa_258, ssa_257 | vec1 32 con ssa_259 = ineg! ssa_258 vec1 32 con ssa_260 = iabs! ssa_198.y | vec1 32 con ssa_260 = iadd! ssa_254, ssa_259 vec1 32 con ssa_261 = ilt32! ssa_198.y, ssa_8 | vec1 32 con ssa_261 = iadd! ssa_257, ssa_37 vec1 32 con ssa_262 = ixor! ssa_261, ssa_234 | vec1 32 con ssa_262 = uge32! ssa_260, ssa_226 vec1 32 con ssa_263 = umul_high! ssa_260, ssa_245 | vec1 32 con ssa_263 = b32csel! ssa_262, ssa_261, ssa_257 vec1 32 con ssa_264 = imul! ssa_263, ssa_232 | vec1 32 con ssa_264 = iadd! ssa_260, ssa_235 vec1 32 con ssa_265 = ineg! ssa_264 | vec1 32 con ssa_265 = b32csel! ssa_262, ssa_264, ssa_260 vec1 32 con ssa_266 = iadd! ssa_260, ssa_265 | vec1 32 con ssa_266 = iadd! ssa_263, ssa_37 vec1 32 con ssa_267 = iadd! ssa_263, ssa_37 | vec1 32 con ssa_267 = uge32! ssa_265, ssa_226 vec1 32 con ssa_268 = uge32! ssa_266, ssa_232 | vec1 32 con ssa_268 = b32csel! ssa_267, ssa_266, ssa_263 vec1 32 con ssa_269 = b32csel! ssa_268, ssa_267, ssa_263 | vec1 32 con ssa_269 = ineg! ssa_268 vec1 32 con ssa_270 = iadd! ssa_266, ssa_241 | vec1 32 con ssa_270 = b32csel! ssa_256, ssa_269, ssa_268 vec1 32 con ssa_271 = b32csel! ssa_268, ssa_270, ssa_266 | vec1 32 con ssa_271 = iabs! ssa_198.z vec1 32 con ssa_272 = iadd! ssa_269, ssa_37 | vec1 32 con ssa_272 = ilt32! ssa_198.z, ssa_8 vec1 32 con ssa_273 = uge32! ssa_271, ssa_232 | vec1 32 con ssa_273 = ixor! ssa_272, ssa_228 vec1 32 con ssa_274 = b32csel! ssa_273, ssa_272, ssa_269 | vec1 32 con ssa_274 = umul_high! ssa_271, ssa_239 vec1 32 con ssa_275 = ineg! ssa_274 | vec1 32 con ssa_275 = imul! ssa_274, ssa_226 vec1 32 con ssa_276 = b32csel! ssa_262, ssa_275, ssa_274 | vec1 32 con ssa_276 = ineg! ssa_275 vec1 32 con ssa_277 = iabs! ssa_198.z | vec1 32 con ssa_277 = iadd! ssa_271, ssa_276 vec1 32 con ssa_278 = ilt32! ssa_198.z, ssa_8 | vec1 32 con ssa_278 = iadd! ssa_274, ssa_37 vec1 32 con ssa_279 = ixor! ssa_278, ssa_234 | vec1 32 con ssa_279 = uge32! ssa_277, ssa_226 vec1 32 con ssa_280 = umul_high! ssa_277, ssa_245 | vec1 32 con ssa_280 = b32csel! ssa_279, ssa_278, ssa_274 vec1 32 con ssa_281 = imul! ssa_280, ssa_232 | vec1 32 con ssa_281 = iadd! ssa_277, ssa_235 vec1 32 con ssa_282 = ineg! ssa_281 | vec1 32 con ssa_282 = b32csel! ssa_279, ssa_281, ssa_277 vec1 32 con ssa_283 = iadd! ssa_277, ssa_282 | vec1 32 con ssa_283 = iadd! ssa_280, ssa_37 vec1 32 con ssa_284 = iadd! ssa_280, ssa_37 | vec1 32 con ssa_284 = uge32! ssa_282, ssa_226 vec1 32 con ssa_285 = uge32! ssa_283, ssa_232 | vec1 32 con ssa_285 = b32csel! ssa_284, ssa_283, ssa_280 vec1 32 con ssa_286 = b32csel! ssa_285, ssa_284, ssa_280 | vec1 32 con ssa_286 = ineg! ssa_285 vec1 32 con ssa_287 = iadd! ssa_283, ssa_241 | vec1 32 con ssa_287 = b32csel! ssa_273, ssa_286, ssa_285 vec1 32 con ssa_288 = b32csel! ssa_285, ssa_287, ssa_283 | vec1 32 con ssa_288 = iabs! ssa_198.w vec1 32 con ssa_289 = iadd! ssa_286, ssa_37 | vec1 32 con ssa_289 = ilt32! ssa_198.w, ssa_8 vec1 32 con ssa_290 = uge32! ssa_288, ssa_232 | vec1 32 con ssa_290 = ixor! ssa_289, ssa_228 vec1 32 con ssa_291 = b32csel! ssa_290, ssa_289, ssa_286 | vec1 32 con ssa_291 = umul_high! ssa_288, ssa_239 vec1 32 con ssa_292 = ineg! ssa_291 | vec1 32 con ssa_292 = imul! ssa_291, ssa_226 vec1 32 con ssa_293 = b32csel! ssa_279, ssa_292, ssa_291 | vec1 32 con ssa_293 = ineg! ssa_292 vec1 32 con ssa_294 = iabs! ssa_198.w | vec1 32 con ssa_294 = iadd! ssa_288, ssa_293 vec1 32 con ssa_295 = ilt32! ssa_198.w, ssa_8 | vec1 32 con ssa_295 = iadd! ssa_291, ssa_37 vec1 32 con ssa_296 = ixor! ssa_295, ssa_234 | vec1 32 con ssa_296 = uge32! ssa_294, ssa_226 vec1 32 con ssa_297 = umul_high! ssa_294, ssa_245 | vec1 32 con ssa_297 = b32csel! ssa_296, ssa_295, ssa_291 vec1 32 con ssa_298 = imul! ssa_297, ssa_232 | vec1 32 con ssa_298 = iadd! ssa_294, ssa_235 vec1 32 con ssa_299 = ineg! ssa_298 | vec1 32 con ssa_299 = b32csel! ssa_296, ssa_298, ssa_294 vec1 32 con ssa_300 = iadd! ssa_294, ssa_299 | vec1 32 con ssa_300 = iadd! ssa_297, ssa_37 vec1 32 con ssa_301 = iadd! ssa_297, ssa_37 | vec1 32 con ssa_301 = uge32! ssa_299, ssa_226 vec1 32 con ssa_302 = uge32! ssa_300, ssa_232 | vec1 32 con ssa_302 = b32csel! ssa_301, ssa_300, ssa_297 vec1 32 con ssa_303 = b32csel! ssa_302, ssa_301, ssa_297 | vec1 32 con ssa_303 = ineg! ssa_302 vec1 32 con ssa_304 = iadd! ssa_300, ssa_241 | vec1 32 con ssa_304 = b32csel! ssa_290, ssa_303, ssa_302 vec1 32 con ssa_305 = b32csel! ssa_302, ssa_304, ssa_300 | vec1 32 con ssa_305 = iabs! ssa_212.x vec1 32 con ssa_306 = iadd! ssa_303, ssa_37 | vec1 32 con ssa_306 = iabs! ssa_32.w vec1 32 con ssa_307 = uge32! ssa_305, ssa_232 | vec1 32 con ssa_307 = ilt32! ssa_212.x, ssa_8 vec1 32 con ssa_308 = b32csel! ssa_307, ssa_306, ssa_303 | vec1 32 con ssa_308 = ilt32! ssa_32.w, ssa_8 vec1 32 con ssa_309 = ineg! ssa_308 | vec1 32 con ssa_309 = ixor! ssa_307, ssa_308 vec1 32 con ssa_310 = b32csel! ssa_296, ssa_309, ssa_308 | vec1 32 con ssa_310 = u2f32! ssa_306 vec1 32 con ssa_311 = iabs! ssa_215.x | vec1 32 con ssa_311 = frcp! ssa_310 vec1 32 con ssa_312 = iabs! ssa_32.w | vec1 32 con ssa_312 = fmul! ssa_311, ssa_232 vec1 32 con ssa_313 = ilt32! ssa_215.x, ssa_8 | vec1 32 con ssa_313 = f2u32! ssa_312 vec1 32 con ssa_314 = ilt32! ssa_32.w, ssa_8 | vec1 32 con ssa_314 = ineg! ssa_306 vec1 32 con ssa_315 = ixor! ssa_313, ssa_314 | vec1 32 con ssa_315 = imul! ssa_306, ssa_313 vec1 32 con ssa_316 = u2f32! ssa_312 | vec1 32 con ssa_316 = ineg! ssa_315 vec1 32 con ssa_317 = frcp! ssa_316 | vec1 32 con ssa_317 = umul_high! ssa_313, ssa_316 vec1 32 con ssa_318 = fmul! ssa_317, ssa_238 | vec1 32 con ssa_318 = iadd! ssa_313, ssa_317 vec1 32 con ssa_319 = f2u32! ssa_318 | vec1 32 con ssa_319 = umul_high! ssa_305, ssa_318 vec1 32 con ssa_320 = ineg! ssa_312 | vec1 32 con ssa_320 = imul! ssa_319, ssa_306 vec1 32 con ssa_321 = imul! ssa_312, ssa_319 | vec1 32 con ssa_321 = ineg! ssa_320 vec1 32 con ssa_322 = ineg! ssa_321 | vec1 32 con ssa_322 = iadd! ssa_305, ssa_321 vec1 32 con ssa_323 = umul_high! ssa_319, ssa_322 | vec1 32 con ssa_323 = iadd! ssa_319, ssa_37 vec1 32 con ssa_324 = iadd! ssa_319, ssa_323 | vec1 32 con ssa_324 = uge32! ssa_322, ssa_306 vec1 32 con ssa_325 = umul_high! ssa_311, ssa_324 | vec1 32 con ssa_325 = b32csel! ssa_324, ssa_323, ssa_319 vec1 32 con ssa_326 = imul! ssa_325, ssa_312 | vec1 32 con ssa_326 = iadd! ssa_322, ssa_314 vec1 32 con ssa_327 = ineg! ssa_326 | vec1 32 con ssa_327 = b32csel! ssa_324, ssa_326, ssa_322 vec1 32 con ssa_328 = iadd! ssa_311, ssa_327 | vec1 32 con ssa_328 = iadd! ssa_325, ssa_37 vec1 32 con ssa_329 = iadd! ssa_325, ssa_37 | vec1 32 con ssa_329 = uge32! ssa_327, ssa_306 vec1 32 con ssa_330 = uge32! ssa_328, ssa_312 | vec1 32 con ssa_330 = b32csel! ssa_329, ssa_328, ssa_325 vec1 32 con ssa_331 = b32csel! ssa_330, ssa_329, ssa_325 | vec1 32 con ssa_331 = ineg! ssa_330 vec1 32 con ssa_332 = iadd! ssa_328, ssa_320 | vec1 32 con ssa_332 = b32csel! ssa_309, ssa_331, ssa_330 vec1 32 con ssa_333 = b32csel! ssa_330, ssa_332, ssa_328 | vec1 32 con ssa_333 = iabs! ssa_212.y vec1 32 con ssa_334 = iadd! ssa_331, ssa_37 | vec1 32 con ssa_334 = ilt32! ssa_212.y, ssa_8 vec1 32 con ssa_335 = uge32! ssa_333, ssa_312 | vec1 32 con ssa_335 = ixor! ssa_334, ssa_308 vec1 32 con ssa_336 = b32csel! ssa_335, ssa_334, ssa_331 | vec1 32 con ssa_336 = umul_high! ssa_333, ssa_318 vec1 32 con ssa_337 = ineg! ssa_336 | vec1 32 con ssa_337 = imul! ssa_336, ssa_306 vec1 32 con ssa_338 = b32csel! ssa_315, ssa_337, ssa_336 | vec1 32 con ssa_338 = ineg! ssa_337 vec1 32 con ssa_339 = iabs! ssa_215.y | vec1 32 con ssa_339 = iadd! ssa_333, ssa_338 vec1 32 con ssa_340 = ilt32! ssa_215.y, ssa_8 | vec1 32 con ssa_340 = iadd! ssa_336, ssa_37 vec1 32 con ssa_341 = ixor! ssa_340, ssa_314 | vec1 32 con ssa_341 = uge32! ssa_339, ssa_306 vec1 32 con ssa_342 = umul_high! ssa_339, ssa_324 | vec1 32 con ssa_342 = b32csel! ssa_341, ssa_340, ssa_336 vec1 32 con ssa_343 = imul! ssa_342, ssa_312 | vec1 32 con ssa_343 = iadd! ssa_339, ssa_314 vec1 32 con ssa_344 = ineg! ssa_343 | vec1 32 con ssa_344 = b32csel! ssa_341, ssa_343, ssa_339 vec1 32 con ssa_345 = iadd! ssa_339, ssa_344 | vec1 32 con ssa_345 = iadd! ssa_342, ssa_37 vec1 32 con ssa_346 = iadd! ssa_342, ssa_37 | vec1 32 con ssa_346 = uge32! ssa_344, ssa_306 vec1 32 con ssa_347 = uge32! ssa_345, ssa_312 | vec1 32 con ssa_347 = b32csel! ssa_346, ssa_345, ssa_342 vec1 32 con ssa_348 = b32csel! ssa_347, ssa_346, ssa_342 | vec1 32 con ssa_348 = ineg! ssa_347 vec1 32 con ssa_349 = iadd! ssa_345, ssa_320 | vec1 32 con ssa_349 = b32csel! ssa_335, ssa_348, ssa_347 vec1 32 con ssa_350 = b32csel! ssa_347, ssa_349, ssa_345 | vec1 32 con ssa_350 = iabs! ssa_212.z vec1 32 con ssa_351 = iadd! ssa_348, ssa_37 | vec1 32 con ssa_351 = ilt32! ssa_212.z, ssa_8 vec1 32 con ssa_352 = uge32! ssa_350, ssa_312 | vec1 32 con ssa_352 = ixor! ssa_351, ssa_308 vec1 32 con ssa_353 = b32csel! ssa_352, ssa_351, ssa_348 | vec1 32 con ssa_353 = umul_high! ssa_350, ssa_318 vec1 32 con ssa_354 = ineg! ssa_353 | vec1 32 con ssa_354 = imul! ssa_353, ssa_306 vec1 32 con ssa_355 = b32csel! ssa_341, ssa_354, ssa_353 | vec1 32 con ssa_355 = ineg! ssa_354 vec1 32 con ssa_356 = iabs! ssa_215.z | vec1 32 con ssa_356 = iadd! ssa_350, ssa_355 vec1 32 con ssa_357 = ilt32! ssa_215.z, ssa_8 | vec1 32 con ssa_357 = iadd! ssa_353, ssa_37 vec1 32 con ssa_358 = ixor! ssa_357, ssa_314 | vec1 32 con ssa_358 = uge32! ssa_356, ssa_306 vec1 32 con ssa_359 = umul_high! ssa_356, ssa_324 | vec1 32 con ssa_359 = b32csel! ssa_358, ssa_357, ssa_353 vec1 32 con ssa_360 = imul! ssa_359, ssa_312 | vec1 32 con ssa_360 = iadd! ssa_356, ssa_314 vec1 32 con ssa_361 = ineg! ssa_360 | vec1 32 con ssa_361 = b32csel! ssa_358, ssa_360, ssa_356 vec1 32 con ssa_362 = iadd! ssa_356, ssa_361 | vec1 32 con ssa_362 = iadd! ssa_359, ssa_37 vec1 32 con ssa_363 = iadd! ssa_359, ssa_37 | vec1 32 con ssa_363 = uge32! ssa_361, ssa_306 vec1 32 con ssa_364 = uge32! ssa_362, ssa_312 | vec1 32 con ssa_364 = b32csel! ssa_363, ssa_362, ssa_359 vec1 32 con ssa_365 = b32csel! ssa_364, ssa_363, ssa_359 | vec1 32 con ssa_365 = ineg! ssa_364 vec1 32 con ssa_366 = iadd! ssa_362, ssa_320 | vec1 32 con ssa_366 = b32csel! ssa_352, ssa_365, ssa_364 vec1 32 con ssa_367 = b32csel! ssa_364, ssa_366, ssa_362 | vec1 32 con ssa_367 = iabs! ssa_212.w vec1 32 con ssa_368 = iadd! ssa_365, ssa_37 | vec1 32 con ssa_368 = ilt32! ssa_212.w, ssa_8 vec1 32 con ssa_369 = uge32! ssa_367, ssa_312 | vec1 32 con ssa_369 = ixor! ssa_368, ssa_308 vec1 32 con ssa_370 = b32csel! ssa_369, ssa_368, ssa_365 | vec1 32 con ssa_370 = umul_high! ssa_367, ssa_318 vec1 32 con ssa_371 = ineg! ssa_370 | vec1 32 con ssa_371 = imul! ssa_370, ssa_306 vec1 32 con ssa_372 = b32csel! ssa_358, ssa_371, ssa_370 | vec1 32 con ssa_372 = ineg! ssa_371 vec1 32 con ssa_373 = iabs! ssa_215.w | vec1 32 con ssa_373 = iadd! ssa_367, ssa_372 vec1 32 con ssa_374 = ilt32! ssa_215.w, ssa_8 | vec1 32 con ssa_374 = iadd! ssa_370, ssa_37 vec1 32 con ssa_375 = ixor! ssa_374, ssa_314 | vec1 32 con ssa_375 = uge32! ssa_373, ssa_306 vec1 32 con ssa_376 = umul_high! ssa_373, ssa_324 | vec1 32 con ssa_376 = b32csel! ssa_375, ssa_374, ssa_370 vec1 32 con ssa_377 = imul! ssa_376, ssa_312 | vec1 32 con ssa_377 = iadd! ssa_373, ssa_314 vec1 32 con ssa_378 = ineg! ssa_377 | vec1 32 con ssa_378 = b32csel! ssa_375, ssa_377, ssa_373 vec1 32 con ssa_379 = iadd! ssa_373, ssa_378 | vec1 32 con ssa_379 = iadd! ssa_376, ssa_37 vec1 32 con ssa_380 = iadd! ssa_376, ssa_37 | vec1 32 con ssa_380 = uge32! ssa_378, ssa_306 vec1 32 con ssa_381 = uge32! ssa_379, ssa_312 | vec1 32 con ssa_381 = b32csel! ssa_380, ssa_379, ssa_376 vec1 32 con ssa_382 = b32csel! ssa_381, ssa_380, ssa_376 | vec1 32 con ssa_382 = ineg! ssa_381 vec1 32 con ssa_383 = iadd! ssa_379, ssa_320 | vec1 32 con ssa_383 = b32csel! ssa_369, ssa_382, ssa_381 vec1 32 con ssa_384 = b32csel! ssa_381, ssa_383, ssa_379 | vec1 32 div ssa_384 = ineg ssa_207 vec1 32 con ssa_385 = iadd! ssa_382, ssa_37 | vec1 32 div ssa_385 = iadd ssa_196.x, ssa_384 vec1 32 con ssa_386 = uge32! ssa_384, ssa_312 | vec1 32 div ssa_386 = iadd3 ssa_38, ssa_208, ssa_196.y vec1 32 con ssa_387 = b32csel! ssa_386, ssa_385, ssa_382 | vec1 32 div ssa_387 = iadd3 ssa_39, ssa_209, ssa_196.z vec1 32 con ssa_388 = ineg! ssa_387 | vec1 32 div ssa_388 = iadd3 ssa_40, ssa_210, ssa_196.w vec1 32 con ssa_389 = b32csel! ssa_375, ssa_388, ssa_387 | vec1 32 div ssa_389 = iabs ssa_385 vec1 32 div ssa_390 = ineg ssa_207 | vec1 32 div ssa_390 = iabs ssa_386 vec1 32 div ssa_391 = iadd ssa_196.x, ssa_390 | vec1 32 div ssa_391 = iabs ssa_387 vec1 32 div ssa_392 = ineg ssa_211 | vec1 32 div ssa_392 = iabs ssa_388 vec1 32 div ssa_393 = iadd ssa_196.y, ssa_392 | vec1 32 div ssa_393 = ineg ssa_221 vec1 32 div ssa_394 = ineg ssa_212 | vec1 32 div ssa_394 = iadd ssa_196.x, ssa_393 vec1 32 div ssa_395 = iadd ssa_196.z, ssa_394 | vec1 32 div ssa_395 = iadd3 ssa_38, ssa_222, ssa_196.y vec1 32 div ssa_396 = ineg ssa_213 | vec1 32 div ssa_396 = iadd3 ssa_39, ssa_223, ssa_196.z vec1 32 div ssa_397 = iadd ssa_196.w, ssa_396 | vec1 32 div ssa_397 = iadd3 ssa_40, ssa_224, ssa_196.w vec1 32 div ssa_398 = iabs ssa_391 | vec1 32 div ssa_398 = iabs ssa_394 vec1 32 div ssa_399 = iabs ssa_393 | vec1 32 div ssa_399 = iabs ssa_395 vec1 32 div ssa_400 = iabs ssa_395 | vec1 32 div ssa_400 = iabs ssa_396 vec1 32 div ssa_401 = iabs ssa_397 vec1 32 div ssa_401 = iabs ssa_397 vec1 32 div ssa_402 = ineg ssa_224 | vec1 32 div ssa_402 = ige32 ssa_332, ssa_398 vec1 32 div ssa_403 = iadd ssa_196.x, ssa_402 | vec1 32 div ssa_403 = ige32 ssa_253, ssa_389 vec1 32 div ssa_404 = ineg ssa_228 | vec1 32 div ssa_404 = ior ssa_403, ssa_402 vec1 32 div ssa_405 = iadd ssa_196.y, ssa_404 | vec1 32 div ssa_405 = ige32 ssa_270, ssa_390 vec1 32 div ssa_406 = ineg ssa_229 | vec1 32 div ssa_406 = ige32 ssa_349, ssa_399 vec1 32 div ssa_407 = iadd ssa_196.z, ssa_406 | vec1 32 div ssa_407 = ior ssa_405, ssa_406 vec1 32 div ssa_408 = ineg ssa_230 | vec1 32 div ssa_408 = ige32 ssa_287, ssa_391 vec1 32 div ssa_409 = iadd ssa_196.w, ssa_408 | vec1 32 div ssa_409 = ige32 ssa_366, ssa_400 vec1 32 div ssa_410 = iabs ssa_403 | vec1 32 div ssa_410 = ior ssa_408, ssa_409 vec1 32 div ssa_411 = iabs ssa_405 | vec1 32 div ssa_411 = ige32 ssa_304, ssa_392 vec1 32 div ssa_412 = iabs ssa_407 | vec1 32 div ssa_412 = ige32 ssa_383, ssa_401 vec1 32 div ssa_413 = iabs ssa_409 | vec1 32 div ssa_413 = ior ssa_411, ssa_412 vec1 32 div ssa_414 = ige32 ssa_338, ssa_410 | vec1 32 div ssa_414 = iand ssa_413, ssa_410 vec1 32 div ssa_415 = ige32 ssa_259, ssa_398 | vec1 32 div ssa_415 = iand ssa_414, ssa_407 vec1 32 div ssa_416 = ior ssa_415, ssa_414 | vec1 32 div ssa_416 = iand ssa_415, ssa_404 vec1 32 div ssa_417 = ige32 ssa_276, ssa_399 < vec1 32 div ssa_418 = ige32 ssa_355, ssa_411 < vec1 32 div ssa_419 = ior ssa_417, ssa_418 < vec1 32 div ssa_420 = ige32 ssa_293, ssa_400 < vec1 32 div ssa_421 = ige32 ssa_372, ssa_412 < vec1 32 div ssa_422 = ior ssa_420, ssa_421 < vec1 32 div ssa_423 = ige32 ssa_310, ssa_401 < vec1 32 div ssa_424 = ige32 ssa_389, ssa_413 < vec1 32 div ssa_425 = ior ssa_423, ssa_424 < vec1 32 div ssa_426 = iand ssa_425, ssa_422 < vec1 32 div ssa_427 = iand ssa_426, ssa_419 < vec1 32 div ssa_428 = iand ssa_427, ssa_416 < /* succs: block_15 block_19 */ /* succs: block_15 block_19 */ if ssa_428 { | if ssa_416 { block block_15: block block_15: /* preds: block_14 */ /* preds: block_14 */ vec1 32 con ssa_429 = load_const (0x00000008 = 0.000000) | vec1 32 con ssa_417 = load_const (0x00000008 = 0.000000) vec1 32 con ssa_430 = intrinsic reduce (ssa_37) (reduction_op=iadd /*257*/, cluster_size=0) | vec1 32 con ssa_418 = intrinsic reduce (ssa_37) (reduction_op=iadd /*257*/, cluster_size=0) vec1 32 div ssa_431 = intrinsic first_invocation () () | vec1 32 div ssa_419 = intrinsic first_invocation () () vec1 32 div ssa_432 = intrinsic load_subgroup_invocation () () | vec1 32 div ssa_420 = intrinsic load_subgroup_invocation () () vec1 32 div ssa_433 = ieq32 ssa_432, ssa_431 | vec1 32 div ssa_421 = ieq32 ssa_420, ssa_419 /* succs: block_16 block_17 */ /* succs: block_16 block_17 */ if ssa_433 { | if ssa_421 { block block_16: block block_16: /* preds: block_15 */ /* preds: block_15 */ vec1 32 div ssa_434 = intrinsic ssbo_atomic (ssa_18, ssa_429, ssa_430) (access=1, ato | vec1 32 div ssa_422 = intrinsic ssbo_atomic (ssa_18, ssa_417, ssa_418) (access=1, ato /* succs: block_18 */ /* succs: block_18 */ } else { } else { block block_17: block block_17: /* preds: block_15 */ /* preds: block_15 */ /* succs: block_18 */ /* succs: block_18 */ } } block block_18: block block_18: /* preds: block_16 block_17 */ /* preds: block_16 block_17 */ div r5 = mov ssa_117 div r5 = mov ssa_117 div r4 = mov ssa_8 div r4 = mov ssa_8 /* succs: block_20 */ /* succs: block_20 */ } else { } else { block block_19: block block_19: /* preds: block_14 */ /* preds: block_14 */ div r5 = mov ssa_8 div r5 = mov ssa_8 div r4 = mov ssa_117 div r4 = mov ssa_117 /* succs: block_20 */ /* succs: block_20 */ } } block block_20: block block_20: /* preds: block_18 block_19 */ /* preds: block_18 block_19 */ vec4 32 div ssa_437 = vec4 r4, r5, ssa_8, ssa_117 | vec4 32 div ssa_425 = vec4 r4, r5, ssa_8, ssa_117 vec4 32 div ssa_438 = vec4 ssa_44, ssa_45, ssa_18, ssa_3 | vec4 32 div ssa_426 = vec4 ssa_44, ssa_45, ssa_18, ssa_3 intrinsic image_store (ssa_14, ssa_438, ssa_2, ssa_437, ssa_8) (image_dim=2D /*1*/, image_array=true | intrinsic image_store (ssa_14, ssa_426, ssa_2, ssa_425, ssa_8) (image_dim=2D /*1*/, image_array=true vec4 32 div ssa_439 = (uint32)txf ssa_56 (coord), ssa_8 (lod), 7 (texture) | vec4 32 div ssa_427 = (uint32)txf ssa_56 (coord), ssa_8 (lod), 7 (texture) vec1 32 con ssa_440 = load_const (0x00000074 = 0.000000) | vec1 32 con ssa_428 = load_const (0x00000074 = 0.000000) vec1 32 con ssa_441 = intrinsic load_uniform (ssa_440) (base=0, range=120, dest_type=invalid /*256*/) | vec1 32 con ssa_429 = intrinsic load_uniform (ssa_428) (base=0, range=120, dest_type=invalid /*256*/) vec1 32 con ssa_442 = ineg ssa_441 | vec1 32 con ssa_430 = ineg ssa_429 vec1 32 div ssa_443 = iadd ssa_439.x, ssa_442 | vec1 32 div ssa_431 = iadd ssa_427.x, ssa_430 vec1 32 div ssa_444 = uge32! ssa_8, ssa_443 | vec1 32 div ssa_432 = uge32! ssa_8, ssa_431 /* succs: block_21 block_25 */ /* succs: block_21 block_25 */ if ssa_444 { | if ssa_432 { block block_21: block block_21: /* preds: block_20 */ /* preds: block_20 */ vec1 32 con ssa_445 = intrinsic reduce (ssa_37) (reduction_op=iadd /*257*/, cluster_size=0) | vec1 32 con ssa_433 = intrinsic reduce (ssa_37) (reduction_op=iadd /*257*/, cluster_size=0) vec1 32 div ssa_446 = intrinsic first_invocation () () | vec1 32 div ssa_434 = intrinsic first_invocation () () vec1 32 div ssa_447 = intrinsic load_subgroup_invocation () () | vec1 32 div ssa_435 = intrinsic load_subgroup_invocation () () vec1 32 div ssa_448 = ieq32 ssa_447, ssa_446 | vec1 32 div ssa_436 = ieq32 ssa_435, ssa_434 /* succs: block_22 block_23 */ /* succs: block_22 block_23 */ if ssa_448 { | if ssa_436 { block block_22: block block_22: /* preds: block_21 */ /* preds: block_21 */ vec1 32 div ssa_449 = intrinsic ssbo_atomic (ssa_18, ssa_58, ssa_445) (access=1, atom | vec1 32 div ssa_437 = intrinsic ssbo_atomic (ssa_18, ssa_58, ssa_433) (access=1, atom /* succs: block_24 */ /* succs: block_24 */ } else { } else { block block_23: block block_23: /* preds: block_21 */ /* preds: block_21 */ /* succs: block_24 */ /* succs: block_24 */ } } block block_24: block block_24: /* preds: block_22 block_23 */ /* preds: block_22 block_23 */ div r7 = mov ssa_117 div r7 = mov ssa_117 div r6 = mov ssa_8 div r6 = mov ssa_8 /* succs: block_26 */ /* succs: block_26 */ } else { } else { block block_25: block block_25: /* preds: block_20 */ /* preds: block_20 */ div r7 = mov ssa_8 div r7 = mov ssa_8 div r6 = mov ssa_117 div r6 = mov ssa_117 /* succs: block_26 */ /* succs: block_26 */ } } block block_26: block block_26: /* preds: block_24 block_25 */ /* preds: block_24 block_25 */ vec4 32 div ssa_452 = vec4 r6, r7, ssa_8, ssa_117 | vec4 32 div ssa_440 = vec4 r6, r7, ssa_8, ssa_117 vec4 32 div ssa_453 = vec4 ssa_44, ssa_45, ssa_36, ssa_1 | vec4 32 div ssa_441 = vec4 ssa_44, ssa_45, ssa_36, ssa_1 intrinsic image_store (ssa_14, ssa_453, ssa_0, ssa_452, ssa_8) (image_dim=2D /*1*/, image_array=true | intrinsic image_store (ssa_14, ssa_441, ssa_0, ssa_440, ssa_8) (image_dim=2D /*1*/, image_array=true /* succs: block_27 */ /* succs: block_27 */ } } block block_27: block block_27: /* preds: block_1 block_26 */ /* preds: block_1 block_26 */ /* succs: block_28 */ /* succs: block_28 */ block block_28: block block_28: } } NIR (SSA form) for compute shader: NIR (SSA form) for compute shader: shader: MESA_SHADER_COMPUTE shader: MESA_SHADER_COMPUTE source_sha1: {0x4080c608, 0xef4e4e6b, 0x82f838bb, 0x041ba6fe, 0x4a36e587} source_sha1: {0x4080c608, 0xef4e4e6b, 0x82f838bb, 0x041ba6fe, 0x4a36e587} workgroup-size: 8, 8, 1 workgroup-size: 8, 8, 1 shared-size: 0 shared-size: 0 stage: 5 stage: 5 next_stage: 0 next_stage: 0 num_textures: 4 num_textures: 4 num_ssbos: 1 num_ssbos: 1 num_images: 1 num_images: 1 system_values_read: 0x00000000'00000020'00000000 system_values_read: 0x00000000'00000020'00000000 subgroup_size: 2 subgroup_size: 2 divergence_analysis_run: true divergence_analysis_run: true bit_sizes_float: 0x20 bit_sizes_float: 0x20 bit_sizes_int: 0x21 bit_sizes_int: 0x21 separate_shader: true separate_shader: true writes_memory: true writes_memory: true ptr_size: 0 ptr_size: 0 inputs: 0 inputs: 0 outputs: 0 outputs: 0 uniforms: 516 uniforms: 516 decl_var push_const INTERP_MODE_NONE block @0 decl_var push_const INTERP_MODE_NONE block @0 decl_var uniform INTERP_MODE_NONE restrict texture2D @1 (~0, 0, 1) decl_var uniform INTERP_MODE_NONE restrict texture2D @1 (~0, 0, 1) decl_var ssbo INTERP_MODE_NONE restrict writeonly block @2 (~0, 0, 0) decl_var ssbo INTERP_MODE_NONE restrict writeonly block @2 (~0, 0, 0) decl_var image INTERP_MODE_NONE restrict writeonly r8g8b8a8_unorm image2DArray @3 (~0, 0, 6) decl_var image INTERP_MODE_NONE restrict writeonly r8g8b8a8_unorm image2DArray @3 (~0, 0, 6) decl_var uniform INTERP_MODE_NONE restrict texture2D @4 (~0, 0, 2) decl_var uniform INTERP_MODE_NONE restrict texture2D @4 (~0, 0, 2) decl_var uniform INTERP_MODE_NONE restrict itexture2D @5 (~0, 0, 3) decl_var uniform INTERP_MODE_NONE restrict itexture2D @5 (~0, 0, 3) decl_var uniform INTERP_MODE_NONE restrict utexture2D @6 (~0, 0, 5) decl_var uniform INTERP_MODE_NONE restrict utexture2D @6 (~0, 0, 5) decl_function main (0 params) decl_function main (0 params) impl main { impl main { block block_0: block block_0: /* preds: */ /* preds: */ vec1 32 con ssa_0 = undefined vec1 32 con ssa_0 = undefined vec1 32 con ssa_1 = undefined vec1 32 con ssa_1 = undefined vec1 32 con ssa_2 = undefined vec1 32 con ssa_2 = undefined vec1 32 con ssa_3 = undefined vec1 32 con ssa_3 = undefined vec1 32 con ssa_4 = undefined vec1 32 con ssa_4 = undefined vec1 32 con ssa_5 = undefined vec1 32 con ssa_5 = undefined vec1 32 con ssa_6 = undefined vec1 32 con ssa_6 = undefined vec1 32 con ssa_7 = undefined vec1 32 con ssa_7 = undefined vec1 32 con ssa_8 = load_const (0x00000000 = 0.000000) vec1 32 con ssa_8 = load_const (0x00000000 = 0.000000) vec2 32 con ssa_9 = intrinsic load_uniform (ssa_8) (base=504, range=12, dest_type=uint /*4*/) vec2 32 con ssa_9 = intrinsic load_uniform (ssa_8) (base=504, range=12, dest_type=uint /*4*/) vec3 32 con ssa_10 = intrinsic load_workgroup_id_zero_base () () vec3 32 con ssa_10 = intrinsic load_workgroup_id_zero_base () () vec1 32 con ssa_11 = iadd ssa_10.x, ssa_9.x vec1 32 con ssa_11 = iadd ssa_10.x, ssa_9.x vec1 32 con ssa_12 = iadd ssa_10.y, ssa_9.y vec1 32 con ssa_12 = iadd ssa_10.y, ssa_9.y vec1 32 con ssa_13 = intrinsic load_subgroup_id () () vec1 32 con ssa_13 = intrinsic load_subgroup_id () () vec1 32 con ssa_14 = load_const (0x00000004 = 0.000000) vec1 32 con ssa_14 = load_const (0x00000004 = 0.000000) vec1 32 con ssa_15 = ishl ssa_13, ssa_14 vec1 32 con ssa_15 = ishl ssa_13, ssa_14 vec1 32 div ssa_16 = intrinsic load_subgroup_invocation () () vec1 32 div ssa_16 = intrinsic load_subgroup_invocation () () vec1 32 div ssa_17 = iadd ssa_16, ssa_15 vec1 32 div ssa_17 = iadd ssa_16, ssa_15 vec1 32 con ssa_18 = load_const (0x00000002 = 0.000000) vec1 32 con ssa_18 = load_const (0x00000002 = 0.000000) vec1 32 div ssa_19 = ushr ssa_17, ssa_18 vec1 32 div ssa_19 = ushr ssa_17, ssa_18 vec1 32 con ssa_20 = load_const (0x00000007 = 0.000000) vec1 32 con ssa_20 = load_const (0x00000007 = 0.000000) vec1 32 div ssa_21 = iand ssa_19, ssa_20 vec1 32 div ssa_21 = iand ssa_19, ssa_20 vec1 32 con ssa_22 = load_const (0x00000003 = 0.000000) vec1 32 con ssa_22 = load_const (0x00000003 = 0.000000) vec1 32 con ssa_23 = load_const (0x00000005 = 0.000000) vec1 32 con ssa_23 = load_const (0x00000005 = 0.000000) vec1 32 div ssa_24 = ushr ssa_17, ssa_23 vec1 32 div ssa_24 = ushr ssa_17, ssa_23 vec1 32 div ssa_25 = ishl ssa_24, ssa_18 vec1 32 div ssa_25 = ishl ssa_24, ssa_18 vec1 32 div ssa_26 = iand ssa_17, ssa_22 vec1 32 div ssa_26 = iand ssa_17, ssa_22 vec1 32 div ssa_27 = iadd ssa_26, ssa_25 vec1 32 div ssa_27 = iadd ssa_26, ssa_25 vec1 32 div ssa_28 = iand ssa_27, ssa_20 vec1 32 div ssa_28 = iand ssa_27, ssa_20 vec1 32 con ssa_29 = ishl ssa_11, ssa_22 vec1 32 con ssa_29 = ishl ssa_11, ssa_22 vec1 32 con ssa_30 = ishl ssa_12, ssa_22 vec1 32 con ssa_30 = ishl ssa_12, ssa_22 vec1 32 div ssa_31 = iadd ssa_29, ssa_21 vec1 32 div ssa_31 = iadd ssa_29, ssa_21 vec1 32 div ssa_32 = iadd ssa_30, ssa_28 vec1 32 div ssa_32 = iadd ssa_30, ssa_28 vec4 32 con ssa_33 = intrinsic load_uniform (ssa_8) (base=0, range=120, dest_type=invalid /*256*/) vec4 32 con ssa_33 = intrinsic load_uniform (ssa_8) (base=0, range=120, dest_type=invalid /*256*/) vec1 32 div ssa_34 = uge32 ssa_32, ssa_33.w vec1 32 div ssa_34 = uge32 ssa_32, ssa_33.w vec1 32 div ssa_35 = uge32 ssa_31, ssa_33.z vec1 32 div ssa_35 = uge32 ssa_31, ssa_33.z vec1 32 div ssa_36 = ior ssa_34, ssa_35 vec1 32 div ssa_36 = ior ssa_34, ssa_35 /* succs: block_1 block_2 */ /* succs: block_1 block_2 */ if ssa_36 { if ssa_36 { block block_1: block block_1: /* preds: block_0 */ /* preds: block_0 */ /* succs: block_27 */ /* succs: block_27 */ } else { } else { block block_2: block block_2: /* preds: block_0 */ /* preds: block_0 */ vec1 32 con ssa_37 = load_const (0x00000010 = 0.000000) vec1 32 con ssa_37 = load_const (0x00000010 = 0.000000) vec1 32 con ssa_38 = load_const (0x00000001 = 0.000000) vec1 32 con ssa_38 = load_const (0x00000001 = 0.000000) vec1 32 con ssa_39 = load_const (0xffffffac = -nan) vec1 32 con ssa_39 = load_const (0xffffffac = -nan) vec1 32 con ssa_40 = load_const (0xffffffe0 = -nan) vec1 32 con ssa_40 = load_const (0xffffffe0 = -nan) vec1 32 con ssa_41 = load_const (0xffffff9d = -nan) vec1 32 con ssa_41 = load_const (0xffffff9d = -nan) vec1 32 con ssa_42 = load_const (0x3b000000 = 0.001953) vec1 32 con ssa_42 = load_const (0x3b000000 = 0.001953) vec1 32 con ssa_43 = load_const (0x3c008081 = 0.007843) vec1 32 con ssa_43 = load_const (0x3c008081 = 0.007843) vec1 32 con ssa_44 = load_const (0x3f000000 = 0.500000) vec1 32 con ssa_44 = load_const (0x3f000000 = 0.500000) vec1 32 div ssa_45 = iadd ssa_33.x, ssa_31 vec1 32 div ssa_45 = iadd ssa_33.x, ssa_31 vec1 32 div ssa_46 = iadd ssa_33.y, ssa_32 vec1 32 div ssa_46 = iadd ssa_33.y, ssa_32 vec1 32 div ssa_47 = u2f32 ssa_31 vec1 32 div ssa_47 = u2f32 ssa_31 vec1 32 div ssa_48 = u2f32 ssa_32 vec1 32 div ssa_48 = u2f32 ssa_32 vec1 32 div ssa_49 = fadd ssa_47, ssa_44 vec1 32 div ssa_49 = fadd ssa_47, ssa_44 vec1 32 div ssa_50 = fadd ssa_48, ssa_44 vec1 32 div ssa_50 = fadd ssa_48, ssa_44 vec1 32 con ssa_51 = u2f32 ssa_33.z vec1 32 con ssa_51 = u2f32 ssa_33.z vec1 32 con ssa_52 = u2f32 ssa_33.w vec1 32 con ssa_52 = u2f32 ssa_33.w vec1 32 con ssa_53 = frcp ssa_51 vec1 32 con ssa_53 = frcp ssa_51 vec1 32 div ssa_54 = fmul ssa_49, ssa_53 vec1 32 div ssa_54 = fmul ssa_49, ssa_53 vec1 32 con ssa_55 = frcp ssa_52 vec1 32 con ssa_55 = frcp ssa_52 vec1 32 div ssa_56 = fmul ssa_50, ssa_55 vec1 32 div ssa_56 = fmul ssa_50, ssa_55 vec2 32 div ssa_57 = vec2 ssa_45, ssa_46 vec2 32 div ssa_57 = vec2 ssa_45, ssa_46 vec4 32 div ssa_58 = (float32)txf ssa_57 (coord), ssa_8 (lod), 4 (texture) vec4 32 div ssa_58 = (float32)txf ssa_57 (coord), ssa_8 (lod), 4 (texture) vec4 32 con ssa_59 = intrinsic load_uniform (ssa_37) (base=0, range=120, dest_type=invalid /*256*/) vec4 32 con ssa_59 = intrinsic load_uniform (ssa_37) (base=0, range=120, dest_type=invalid /*256*/) vec1 32 con ssa_60 = load_const (0x00000020 = 0.000000) vec1 32 con ssa_60 = load_const (0x00000020 = 0.000000) vec4 32 con ssa_61 = intrinsic load_uniform (ssa_60) (base=0, range=120, dest_type=invalid /*256*/) vec4 32 con ssa_61 = intrinsic load_uniform (ssa_60) (base=0, range=120, dest_type=invalid /*256*/) vec1 32 con ssa_62 = fneg ssa_61.x vec1 32 con ssa_62 = fneg ssa_61.x vec1 32 div ssa_63 = fmul ssa_62, ssa_56 vec1 32 div ssa_63 = fmul ssa_62, ssa_56 vec1 32 con ssa_64 = fneg ssa_61.y vec1 32 con ssa_64 = fneg ssa_61.y vec1 32 div ssa_65 = fmul ssa_64, ssa_56 vec1 32 div ssa_65 = fmul ssa_64, ssa_56 vec1 32 con ssa_66 = fneg ssa_61.z vec1 32 con ssa_66 = fneg ssa_61.z vec1 32 div ssa_67 = fmul ssa_66, ssa_56 vec1 32 div ssa_67 = fmul ssa_66, ssa_56 vec1 32 con ssa_68 = fneg ssa_61.w vec1 32 con ssa_68 = fneg ssa_61.w vec1 32 div ssa_69 = fmul ssa_68, ssa_56 vec1 32 div ssa_69 = fmul ssa_68, ssa_56 vec1 32 con ssa_70 = fneg ssa_59.x vec1 32 con ssa_70 = fneg ssa_59.x vec1 32 div ssa_71 = ffma ssa_70, ssa_54, ssa_63 vec1 32 div ssa_71 = ffma ssa_70, ssa_54, ssa_63 vec1 32 con ssa_72 = fneg ssa_59.y vec1 32 con ssa_72 = fneg ssa_59.y vec1 32 div ssa_73 = ffma ssa_72, ssa_54, ssa_65 vec1 32 div ssa_73 = ffma ssa_72, ssa_54, ssa_65 vec1 32 con ssa_74 = fneg ssa_59.z vec1 32 con ssa_74 = fneg ssa_59.z vec1 32 div ssa_75 = ffma ssa_74, ssa_54, ssa_67 vec1 32 div ssa_75 = ffma ssa_74, ssa_54, ssa_67 vec1 32 con ssa_76 = fneg ssa_59.w vec1 32 con ssa_76 = fneg ssa_59.w vec1 32 div ssa_77 = ffma ssa_76, ssa_54, ssa_69 vec1 32 div ssa_77 = ffma ssa_76, ssa_54, ssa_69 vec1 32 con ssa_78 = load_const (0xbd85573d = -0.065108) vec1 32 con ssa_78 = load_const (0xbd85573d = -0.065108) vec1 32 div ssa_79 = ffma ssa_71, ssa_44, ssa_78 vec1 32 div ssa_79 = ffma ssa_71, ssa_44, ssa_78 vec1 32 con ssa_80 = load_const (0xbdc88c03 = -0.097923) vec1 32 con ssa_80 = load_const (0xbdc88c03 = -0.097923) vec1 32 div ssa_81 = ffma ssa_73, ssa_44, ssa_80 vec1 32 div ssa_81 = ffma ssa_73, ssa_44, ssa_80 vec1 32 con ssa_82 = load_const (0xbd9d07d6 = -0.076675) vec1 32 con ssa_82 = load_const (0xbd9d07d6 = -0.076675) vec1 32 div ssa_83 = ffma ssa_75, ssa_44, ssa_82 vec1 32 div ssa_83 = ffma ssa_75, ssa_44, ssa_82 vec1 32 con ssa_84 = load_const (0xbd97cde7 = -0.074123) vec1 32 con ssa_84 = load_const (0xbd97cde7 = -0.074123) vec1 32 div ssa_85 = ffma ssa_77, ssa_44, ssa_84 vec1 32 div ssa_85 = ffma ssa_77, ssa_44, ssa_84 vec1 32 con ssa_86 = fmul ssa_59.x, ssa_53 vec1 32 con ssa_86 = fmul ssa_59.x, ssa_53 vec1 32 con ssa_87 = fmul ssa_59.y, ssa_53 vec1 32 con ssa_87 = fmul ssa_59.y, ssa_53 vec1 32 con ssa_88 = fmul ssa_59.z, ssa_53 vec1 32 con ssa_88 = fmul ssa_59.z, ssa_53 vec1 32 con ssa_89 = fmul ssa_59.w, ssa_53 vec1 32 con ssa_89 = fmul ssa_59.w, ssa_53 vec1 32 con ssa_90 = fmul ssa_61.x, ssa_55 vec1 32 con ssa_90 = fmul ssa_61.x, ssa_55 vec1 32 con ssa_91 = fmul ssa_61.y, ssa_55 vec1 32 con ssa_91 = fmul ssa_61.y, ssa_55 vec1 32 con ssa_92 = fmul ssa_61.z, ssa_55 vec1 32 con ssa_92 = fmul ssa_61.z, ssa_55 vec1 32 con ssa_93 = fmul ssa_61.w, ssa_55 vec1 32 con ssa_93 = fmul ssa_61.w, ssa_55 vec1 32 con ssa_94 = fmax ssa_86, ssa_90 vec1 32 con ssa_94 = fmax ssa_86, ssa_90 vec1 32 con ssa_95 = fmax ssa_87, ssa_91 vec1 32 con ssa_95 = fmax ssa_87, ssa_91 vec1 32 con ssa_96 = fmax ssa_88, ssa_92 vec1 32 con ssa_96 = fmax ssa_88, ssa_92 vec1 32 con ssa_97 = fmax ssa_89, ssa_93 vec1 32 con ssa_97 = fmax ssa_89, ssa_93 vec1 32 con ssa_98 = fadd ssa_94, ssa_43 vec1 32 con ssa_98 = fadd ssa_94, ssa_43 vec1 32 con ssa_99 = fadd ssa_95, ssa_43 vec1 32 con ssa_99 = fadd ssa_95, ssa_43 vec1 32 con ssa_100 = fadd ssa_96, ssa_43 vec1 32 con ssa_100 = fadd ssa_96, ssa_43 vec1 32 con ssa_101 = fadd ssa_97, ssa_43 vec1 32 con ssa_101 = fadd ssa_97, ssa_43 vec1 32 div ssa_102 = fadd ssa_58.x, ssa_79 vec1 32 div ssa_102 = fadd ssa_58.x, ssa_79 vec1 32 div ssa_103 = fadd ssa_58.y, ssa_81 vec1 32 div ssa_103 = fadd ssa_58.y, ssa_81 vec1 32 div ssa_104 = fadd ssa_58.z, ssa_83 vec1 32 div ssa_104 = fadd ssa_58.z, ssa_83 vec1 32 div ssa_105 = fadd ssa_58.w, ssa_85 vec1 32 div ssa_105 = fadd ssa_58.w, ssa_85 vec1 32 div ssa_106 = fabs ssa_102 vec1 32 div ssa_106 = fabs ssa_102 vec1 32 div ssa_107 = fabs ssa_103 vec1 32 div ssa_107 = fabs ssa_103 vec1 32 div ssa_108 = fabs ssa_104 vec1 32 div ssa_108 = fabs ssa_104 vec1 32 div ssa_109 = fabs ssa_105 vec1 32 div ssa_109 = fabs ssa_105 vec1 32 div ssa_110 = flt32! ssa_109, ssa_101 vec1 32 div ssa_110 = flt32! ssa_109, ssa_101 vec1 32 div ssa_111 = flt32! ssa_108, ssa_100 vec1 32 div ssa_111 = flt32! ssa_108, ssa_100 vec1 32 div ssa_112 = iand ssa_110, ssa_111 vec1 32 div ssa_112 = iand ssa_110, ssa_111 vec1 32 div ssa_113 = flt32! ssa_107, ssa_99 vec1 32 div ssa_113 = flt32! ssa_107, ssa_99 vec1 32 div ssa_114 = iand ssa_112, ssa_113 vec1 32 div ssa_114 = iand ssa_112, ssa_113 vec1 32 div ssa_115 = flt32! ssa_106, ssa_98 vec1 32 div ssa_115 = flt32! ssa_106, ssa_98 vec1 32 div ssa_116 = iand ssa_114, ssa_115 vec1 32 div ssa_116 = iand ssa_114, ssa_115 vec1 32 con ssa_117 = load_const (0x3f800000 = 1.000000) vec1 32 con ssa_117 = load_const (0x3f800000 = 1.000000) /* succs: block_3 block_7 */ /* succs: block_3 block_7 */ if ssa_116 { if ssa_116 { block block_3: block block_3: /* preds: block_2 */ /* preds: block_2 */ vec1 32 con ssa_118 = intrinsic reduce (ssa_38) (reduction_op=iadd /*257*/, cluster_size=0) vec1 32 con ssa_118 = intrinsic reduce (ssa_38) (reduction_op=iadd /*257*/, cluster_size=0) vec1 32 div ssa_119 = intrinsic first_invocation () () vec1 32 div ssa_119 = intrinsic first_invocation () () vec1 32 div ssa_120 = intrinsic load_subgroup_invocation () () vec1 32 div ssa_120 = intrinsic load_subgroup_invocation () () vec1 32 div ssa_121 = ieq32 ssa_120, ssa_119 vec1 32 div ssa_121 = ieq32 ssa_120, ssa_119 /* succs: block_4 block_5 */ /* succs: block_4 block_5 */ if ssa_121 { if ssa_121 { block block_4: block block_4: /* preds: block_3 */ /* preds: block_3 */ vec1 32 div ssa_122 = intrinsic ssbo_atomic (ssa_18, ssa_8, ssa_118) (access=1, atomi vec1 32 div ssa_122 = intrinsic ssbo_atomic (ssa_18, ssa_8, ssa_118) (access=1, atomi /* succs: block_6 */ /* succs: block_6 */ } else { } else { block block_5: block block_5: /* preds: block_3 */ /* preds: block_3 */ /* succs: block_6 */ /* succs: block_6 */ } } block block_6: block block_6: /* preds: block_4 block_5 */ /* preds: block_4 block_5 */ /* succs: block_8 */ /* succs: block_8 */ } else { } else { block block_7: block block_7: /* preds: block_2 */ /* preds: block_2 */ /* succs: block_8 */ /* succs: block_8 */ } } block block_8: block block_8: /* preds: block_6 block_7 */ /* preds: block_6 block_7 */ vec1 32 div ssa_123 = phi block_6: ssa_8, block_7: ssa_117 vec1 32 div ssa_123 = phi block_6: ssa_8, block_7: ssa_117 vec1 32 div ssa_124 = phi block_6: ssa_117, block_7: ssa_8 vec1 32 div ssa_124 = phi block_6: ssa_117, block_7: ssa_8 vec4 32 div ssa_125 = vec4 ssa_123, ssa_124, ssa_8, ssa_117 vec4 32 div ssa_125 = vec4 ssa_123, ssa_124, ssa_8, ssa_117 vec4 32 div ssa_126 = vec4 ssa_45, ssa_46, ssa_8, ssa_7 vec4 32 div ssa_126 = vec4 ssa_45, ssa_46, ssa_8, ssa_7 intrinsic image_store (ssa_22, ssa_126, ssa_6, ssa_125, ssa_8) (image_dim=2D /*1*/, image_array=true intrinsic image_store (ssa_22, ssa_126, ssa_6, ssa_125, ssa_8) (image_dim=2D /*1*/, image_array=true vec4 32 div ssa_127 = (float32)txf ssa_57 (coord), ssa_8 (lod), 5 (texture) vec4 32 div ssa_127 = (float32)txf ssa_57 (coord), ssa_8 (lod), 5 (texture) vec1 32 con ssa_128 = load_const (0x00000030 = 0.000000) vec1 32 con ssa_128 = load_const (0x00000030 = 0.000000) vec4 32 con ssa_129 = intrinsic load_uniform (ssa_128) (base=0, range=120, dest_type=invalid /*256*/) vec4 32 con ssa_129 = intrinsic load_uniform (ssa_128) (base=0, range=120, dest_type=invalid /*256*/) vec1 32 con ssa_130 = load_const (0x00000040 = 0.000000) vec1 32 con ssa_130 = load_const (0x00000040 = 0.000000) vec4 32 con ssa_131 = intrinsic load_uniform (ssa_130) (base=0, range=120, dest_type=invalid /*256*/) vec4 32 con ssa_131 = intrinsic load_uniform (ssa_130) (base=0, range=120, dest_type=invalid /*256*/) vec1 32 con ssa_132 = fneg ssa_131.x vec1 32 con ssa_132 = fneg ssa_131.x vec1 32 div ssa_133 = fmul ssa_132, ssa_56 vec1 32 div ssa_133 = fmul ssa_132, ssa_56 vec1 32 con ssa_134 = fneg ssa_131.y vec1 32 con ssa_134 = fneg ssa_131.y vec1 32 div ssa_135 = fmul ssa_134, ssa_56 vec1 32 div ssa_135 = fmul ssa_134, ssa_56 vec1 32 con ssa_136 = fneg ssa_131.z vec1 32 con ssa_136 = fneg ssa_131.z vec1 32 div ssa_137 = fmul ssa_136, ssa_56 vec1 32 div ssa_137 = fmul ssa_136, ssa_56 vec1 32 con ssa_138 = fneg ssa_131.w vec1 32 con ssa_138 = fneg ssa_131.w vec1 32 div ssa_139 = fmul ssa_138, ssa_56 vec1 32 div ssa_139 = fmul ssa_138, ssa_56 vec1 32 con ssa_140 = fneg ssa_129.x vec1 32 con ssa_140 = fneg ssa_129.x vec1 32 div ssa_141 = ffma ssa_140, ssa_54, ssa_133 vec1 32 div ssa_141 = ffma ssa_140, ssa_54, ssa_133 vec1 32 con ssa_142 = fneg ssa_129.y vec1 32 con ssa_142 = fneg ssa_129.y vec1 32 div ssa_143 = ffma ssa_142, ssa_54, ssa_135 vec1 32 div ssa_143 = ffma ssa_142, ssa_54, ssa_135 vec1 32 con ssa_144 = fneg ssa_129.z vec1 32 con ssa_144 = fneg ssa_129.z vec1 32 div ssa_145 = ffma ssa_144, ssa_54, ssa_137 vec1 32 div ssa_145 = ffma ssa_144, ssa_54, ssa_137 vec1 32 con ssa_146 = fneg ssa_129.w vec1 32 con ssa_146 = fneg ssa_129.w vec1 32 div ssa_147 = ffma ssa_146, ssa_54, ssa_139 vec1 32 div ssa_147 = ffma ssa_146, ssa_54, ssa_139 vec1 32 con ssa_148 = load_const (0xbdc381f3 = -0.095463) vec1 32 con ssa_148 = load_const (0xbdc381f3 = -0.095463) vec1 32 div ssa_149 = ffma ssa_141, ssa_44, ssa_148 vec1 32 div ssa_149 = ffma ssa_141, ssa_44, ssa_148 vec1 32 con ssa_150 = load_const (0xbdc9c363 = -0.098517) vec1 32 con ssa_150 = load_const (0xbdc9c363 = -0.098517) vec1 32 div ssa_151 = ffma ssa_143, ssa_44, ssa_150 vec1 32 div ssa_151 = ffma ssa_143, ssa_44, ssa_150 vec1 32 con ssa_152 = load_const (0xbdc52221 = -0.096257) vec1 32 con ssa_152 = load_const (0xbdc52221 = -0.096257) vec1 32 div ssa_153 = ffma ssa_145, ssa_44, ssa_152 vec1 32 div ssa_153 = ffma ssa_145, ssa_44, ssa_152 vec1 32 con ssa_154 = load_const (0xbd9e4e34 = -0.077298) vec1 32 con ssa_154 = load_const (0xbd9e4e34 = -0.077298) vec1 32 div ssa_155 = ffma ssa_147, ssa_44, ssa_154 vec1 32 div ssa_155 = ffma ssa_147, ssa_44, ssa_154 vec1 32 con ssa_156 = fmul ssa_129.x, ssa_53 vec1 32 con ssa_156 = fmul ssa_129.x, ssa_53 vec1 32 con ssa_157 = fmul ssa_129.y, ssa_53 vec1 32 con ssa_157 = fmul ssa_129.y, ssa_53 vec1 32 con ssa_158 = fmul ssa_129.z, ssa_53 vec1 32 con ssa_158 = fmul ssa_129.z, ssa_53 vec1 32 con ssa_159 = fmul ssa_129.w, ssa_53 vec1 32 con ssa_159 = fmul ssa_129.w, ssa_53 vec1 32 con ssa_160 = fmul ssa_131.x, ssa_55 vec1 32 con ssa_160 = fmul ssa_131.x, ssa_55 vec1 32 con ssa_161 = fmul ssa_131.y, ssa_55 vec1 32 con ssa_161 = fmul ssa_131.y, ssa_55 vec1 32 con ssa_162 = fmul ssa_131.z, ssa_55 vec1 32 con ssa_162 = fmul ssa_131.z, ssa_55 vec1 32 con ssa_163 = fmul ssa_131.w, ssa_55 vec1 32 con ssa_163 = fmul ssa_131.w, ssa_55 vec1 32 con ssa_164 = fmax ssa_156, ssa_160 vec1 32 con ssa_164 = fmax ssa_156, ssa_160 vec1 32 con ssa_165 = fmax ssa_157, ssa_161 vec1 32 con ssa_165 = fmax ssa_157, ssa_161 vec1 32 con ssa_166 = fmax ssa_158, ssa_162 vec1 32 con ssa_166 = fmax ssa_158, ssa_162 vec1 32 con ssa_167 = fmax ssa_159, ssa_163 vec1 32 con ssa_167 = fmax ssa_159, ssa_163 vec1 32 con ssa_168 = fadd ssa_164, ssa_42 vec1 32 con ssa_168 = fadd ssa_164, ssa_42 vec1 32 con ssa_169 = fadd ssa_165, ssa_42 vec1 32 con ssa_169 = fadd ssa_165, ssa_42 vec1 32 con ssa_170 = fadd ssa_166, ssa_42 vec1 32 con ssa_170 = fadd ssa_166, ssa_42 vec1 32 con ssa_171 = fadd ssa_167, ssa_42 vec1 32 con ssa_171 = fadd ssa_167, ssa_42 vec1 32 div ssa_172 = fadd ssa_127.x, ssa_149 vec1 32 div ssa_172 = fadd ssa_127.x, ssa_149 vec1 32 div ssa_173 = fadd ssa_127.y, ssa_151 vec1 32 div ssa_173 = fadd ssa_127.y, ssa_151 vec1 32 div ssa_174 = fadd ssa_127.z, ssa_153 vec1 32 div ssa_174 = fadd ssa_127.z, ssa_153 vec1 32 div ssa_175 = fadd ssa_127.w, ssa_155 vec1 32 div ssa_175 = fadd ssa_127.w, ssa_155 vec1 32 div ssa_176 = fabs ssa_172 vec1 32 div ssa_176 = fabs ssa_172 vec1 32 div ssa_177 = fabs ssa_173 vec1 32 div ssa_177 = fabs ssa_173 vec1 32 div ssa_178 = fabs ssa_174 vec1 32 div ssa_178 = fabs ssa_174 vec1 32 div ssa_179 = fabs ssa_175 vec1 32 div ssa_179 = fabs ssa_175 vec1 32 div ssa_180 = flt32! ssa_179, ssa_171 vec1 32 div ssa_180 = flt32! ssa_179, ssa_171 vec1 32 div ssa_181 = flt32! ssa_178, ssa_170 vec1 32 div ssa_181 = flt32! ssa_178, ssa_170 vec1 32 div ssa_182 = iand ssa_180, ssa_181 vec1 32 div ssa_182 = iand ssa_180, ssa_181 vec1 32 div ssa_183 = flt32! ssa_177, ssa_169 vec1 32 div ssa_183 = flt32! ssa_177, ssa_169 vec1 32 div ssa_184 = iand ssa_182, ssa_183 vec1 32 div ssa_184 = iand ssa_182, ssa_183 vec1 32 div ssa_185 = flt32! ssa_176, ssa_168 vec1 32 div ssa_185 = flt32! ssa_176, ssa_168 vec1 32 div ssa_186 = iand ssa_184, ssa_185 vec1 32 div ssa_186 = iand ssa_184, ssa_185 /* succs: block_9 block_13 */ /* succs: block_9 block_13 */ if ssa_186 { if ssa_186 { block block_9: block block_9: /* preds: block_8 */ /* preds: block_8 */ vec1 32 con ssa_187 = intrinsic reduce (ssa_38) (reduction_op=iadd /*257*/, cluster_size=0) vec1 32 con ssa_187 = intrinsic reduce (ssa_38) (reduction_op=iadd /*257*/, cluster_size=0) vec1 32 div ssa_188 = intrinsic first_invocation () () vec1 32 div ssa_188 = intrinsic first_invocation () () vec1 32 div ssa_189 = intrinsic load_subgroup_invocation () () vec1 32 div ssa_189 = intrinsic load_subgroup_invocation () () vec1 32 div ssa_190 = ieq32 ssa_189, ssa_188 vec1 32 div ssa_190 = ieq32 ssa_189, ssa_188 /* succs: block_10 block_11 */ /* succs: block_10 block_11 */ if ssa_190 { if ssa_190 { block block_10: block block_10: /* preds: block_9 */ /* preds: block_9 */ vec1 32 div ssa_191 = intrinsic ssbo_atomic (ssa_18, ssa_14, ssa_187) (access=1, atom vec1 32 div ssa_191 = intrinsic ssbo_atomic (ssa_18, ssa_14, ssa_187) (access=1, atom /* succs: block_12 */ /* succs: block_12 */ } else { } else { block block_11: block block_11: /* preds: block_9 */ /* preds: block_9 */ /* succs: block_12 */ /* succs: block_12 */ } } block block_12: block block_12: /* preds: block_10 block_11 */ /* preds: block_10 block_11 */ /* succs: block_14 */ /* succs: block_14 */ } else { } else { block block_13: block block_13: /* preds: block_8 */ /* preds: block_8 */ /* succs: block_14 */ /* succs: block_14 */ } } block block_14: block block_14: /* preds: block_12 block_13 */ /* preds: block_12 block_13 */ vec1 32 div ssa_192 = phi block_12: ssa_8, block_13: ssa_117 vec1 32 div ssa_192 = phi block_12: ssa_8, block_13: ssa_117 vec1 32 div ssa_193 = phi block_12: ssa_117, block_13: ssa_8 vec1 32 div ssa_193 = phi block_12: ssa_117, block_13: ssa_8 vec4 32 div ssa_194 = vec4 ssa_192, ssa_193, ssa_8, ssa_117 vec4 32 div ssa_194 = vec4 ssa_192, ssa_193, ssa_8, ssa_117 vec4 32 div ssa_195 = vec4 ssa_45, ssa_46, ssa_38, ssa_5 vec4 32 div ssa_195 = vec4 ssa_45, ssa_46, ssa_38, ssa_5 intrinsic image_store (ssa_22, ssa_195, ssa_4, ssa_194, ssa_8) (image_dim=2D /*1*/, image_array=true intrinsic image_store (ssa_22, ssa_195, ssa_4, ssa_194, ssa_8) (image_dim=2D /*1*/, image_array=true vec4 32 div ssa_196 = (int32)txf ssa_57 (coord), ssa_8 (lod), 6 (texture) vec4 32 div ssa_196 = (int32)txf ssa_57 (coord), ssa_8 (lod), 6 (texture) vec1 32 con ssa_197 = load_const (0x00000050 = 0.000000) vec1 32 con ssa_197 = load_const (0x00000050 = 0.000000) vec4 32 con ssa_198 = intrinsic load_uniform (ssa_197) (base=0, range=120, dest_type=invalid /*256*/) vec4 32 con ssa_198 = intrinsic load_uniform (ssa_197) (base=0, range=120, dest_type=invalid /*256*/) vec1 32 con ssa_199 = i2f32 ssa_198.x vec1 32 con ssa_199 = i2f32 ssa_198.x vec1 32 con ssa_200 = i2f32 ssa_198.y vec1 32 con ssa_200 = i2f32 ssa_198.y vec1 32 con ssa_201 = i2f32 ssa_198.z vec1 32 con ssa_201 = i2f32 ssa_198.z vec1 32 con ssa_202 = i2f32 ssa_198.w vec1 32 con ssa_202 = i2f32 ssa_198.w vec1 32 div ssa_203 = fmul ssa_199, ssa_54 vec1 32 div ssa_203 = fmul ssa_199, ssa_54 vec1 32 div ssa_204 = fmul ssa_200, ssa_54 vec1 32 div ssa_204 = fmul ssa_200, ssa_54 vec1 32 div ssa_205 = fmul ssa_201, ssa_54 vec1 32 div ssa_205 = fmul ssa_201, ssa_54 vec1 32 div ssa_206 = fmul ssa_202, ssa_54 vec1 32 div ssa_206 = fmul ssa_202, ssa_54 vec1 32 div ssa_207 = f2i32 ssa_203 vec1 32 div ssa_207 = f2i32 ssa_203 vec1 32 div ssa_208 = f2i32 ssa_204 vec1 32 div ssa_208 = f2i32 ssa_204 vec1 32 div ssa_209 = f2i32 ssa_205 vec1 32 div ssa_209 = f2i32 ssa_205 vec1 32 div ssa_210 = f2i32 ssa_206 vec1 32 div ssa_210 = f2i32 ssa_206 vec1 32 div ssa_211 = iadd ssa_208, ssa_39 | vec1 32 con ssa_211 = load_const (0x00000060 = 0.000000) vec1 32 div ssa_212 = iadd ssa_209, ssa_40 | vec4 32 con ssa_212 = intrinsic load_uniform (ssa_211) (base=0, range=120, dest_type=invalid /*256*/) vec1 32 div ssa_213 = iadd ssa_210, ssa_41 | vec1 32 con ssa_213 = i2f32 ssa_212.x vec1 32 con ssa_214 = load_const (0x00000060 = 0.000000) | vec1 32 con ssa_214 = i2f32 ssa_212.y vec4 32 con ssa_215 = intrinsic load_uniform (ssa_214) (base=0, range=120, dest_type=invalid /*256*/) | vec1 32 con ssa_215 = i2f32 ssa_212.z vec1 32 con ssa_216 = i2f32 ssa_215.x | vec1 32 con ssa_216 = i2f32 ssa_212.w vec1 32 con ssa_217 = i2f32 ssa_215.y | vec1 32 div ssa_217 = fmul ssa_213, ssa_56 vec1 32 con ssa_218 = i2f32 ssa_215.z | vec1 32 div ssa_218 = fmul ssa_214, ssa_56 vec1 32 con ssa_219 = i2f32 ssa_215.w | vec1 32 div ssa_219 = fmul ssa_215, ssa_56 vec1 32 div ssa_220 = fmul ssa_216, ssa_56 vec1 32 div ssa_220 = fmul ssa_216, ssa_56 vec1 32 div ssa_221 = fmul ssa_217, ssa_56 | vec1 32 div ssa_221 = f2i32 ssa_217 vec1 32 div ssa_222 = fmul ssa_218, ssa_56 | vec1 32 div ssa_222 = f2i32 ssa_218 vec1 32 div ssa_223 = fmul ssa_219, ssa_56 | vec1 32 div ssa_223 = f2i32 ssa_219 vec1 32 div ssa_224 = f2i32 ssa_220 vec1 32 div ssa_224 = f2i32 ssa_220 vec1 32 div ssa_225 = f2i32 ssa_221 | vec1 32 con ssa_225 = iabs! ssa_198.x vec1 32 div ssa_226 = f2i32 ssa_222 | vec1 32 con ssa_226 = iabs! ssa_33.z vec1 32 div ssa_227 = f2i32 ssa_223 | vec1 32 con ssa_227 = ilt32! ssa_198.x, ssa_8 vec1 32 div ssa_228 = iadd ssa_225, ssa_39 | vec1 32 con ssa_228 = ilt32! ssa_33.z, ssa_8 vec1 32 div ssa_229 = iadd ssa_226, ssa_40 | vec1 32 con ssa_229 = ixor! ssa_227, ssa_228 vec1 32 div ssa_230 = iadd ssa_227, ssa_41 | vec1 32 con ssa_230 = u2f32! ssa_226 vec1 32 con ssa_231 = iabs! ssa_198.x | vec1 32 con ssa_231 = frcp! ssa_230 vec1 32 con ssa_232 = iabs! ssa_33.z | vec1 32 con ssa_232 = load_const (0x4f7ffffe = 4294966784.000000) vec1 32 con ssa_233 = ilt32! ssa_198.x, ssa_8 | vec1 32 con ssa_233 = fmul! ssa_231, ssa_232 vec1 32 con ssa_234 = ilt32! ssa_33.z, ssa_8 | vec1 32 con ssa_234 = f2u32! ssa_233 vec1 32 con ssa_235 = ixor! ssa_233, ssa_234 | vec1 32 con ssa_235 = ineg! ssa_226 vec1 32 con ssa_236 = u2f32! ssa_232 | vec1 32 con ssa_236 = imul! ssa_226, ssa_234 vec1 32 con ssa_237 = frcp! ssa_236 | vec1 32 con ssa_237 = ineg! ssa_236 vec1 32 con ssa_238 = load_const (0x4f7ffffe = 4294966784.000000) | vec1 32 con ssa_238 = umul_high! ssa_234, ssa_237 vec1 32 con ssa_239 = fmul! ssa_237, ssa_238 | vec1 32 con ssa_239 = iadd! ssa_234, ssa_238 vec1 32 con ssa_240 = f2u32! ssa_239 | vec1 32 con ssa_240 = umul_high! ssa_225, ssa_239 vec1 32 con ssa_241 = ineg! ssa_232 | vec1 32 con ssa_241 = imul! ssa_240, ssa_226 vec1 32 con ssa_242 = imul! ssa_232, ssa_240 | vec1 32 con ssa_242 = ineg! ssa_241 vec1 32 con ssa_243 = ineg! ssa_242 | vec1 32 con ssa_243 = iadd! ssa_225, ssa_242 vec1 32 con ssa_244 = umul_high! ssa_240, ssa_243 | vec1 32 con ssa_244 = iadd! ssa_240, ssa_38 vec1 32 con ssa_245 = iadd! ssa_240, ssa_244 | vec1 32 con ssa_245 = uge32! ssa_243, ssa_226 vec1 32 con ssa_246 = umul_high! ssa_231, ssa_245 | vec1 32 con ssa_246 = b32csel! ssa_245, ssa_244, ssa_240 vec1 32 con ssa_247 = imul! ssa_246, ssa_232 | vec1 32 con ssa_247 = iadd! ssa_243, ssa_235 vec1 32 con ssa_248 = ineg! ssa_247 | vec1 32 con ssa_248 = b32csel! ssa_245, ssa_247, ssa_243 vec1 32 con ssa_249 = iadd! ssa_231, ssa_248 | vec1 32 con ssa_249 = iadd! ssa_246, ssa_38 vec1 32 con ssa_250 = iadd! ssa_246, ssa_38 | vec1 32 con ssa_250 = uge32! ssa_248, ssa_226 vec1 32 con ssa_251 = uge32! ssa_249, ssa_232 | vec1 32 con ssa_251 = b32csel! ssa_250, ssa_249, ssa_246 vec1 32 con ssa_252 = b32csel! ssa_251, ssa_250, ssa_246 | vec1 32 con ssa_252 = ineg! ssa_251 vec1 32 con ssa_253 = iadd! ssa_249, ssa_241 | vec1 32 con ssa_253 = b32csel! ssa_229, ssa_252, ssa_251 vec1 32 con ssa_254 = b32csel! ssa_251, ssa_253, ssa_249 | vec1 32 con ssa_254 = iabs! ssa_198.y vec1 32 con ssa_255 = iadd! ssa_252, ssa_38 | vec1 32 con ssa_255 = ilt32! ssa_198.y, ssa_8 vec1 32 con ssa_256 = uge32! ssa_254, ssa_232 | vec1 32 con ssa_256 = ixor! ssa_255, ssa_228 vec1 32 con ssa_257 = b32csel! ssa_256, ssa_255, ssa_252 | vec1 32 con ssa_257 = umul_high! ssa_254, ssa_239 vec1 32 con ssa_258 = ineg! ssa_257 | vec1 32 con ssa_258 = imul! ssa_257, ssa_226 vec1 32 con ssa_259 = b32csel! ssa_235, ssa_258, ssa_257 | vec1 32 con ssa_259 = ineg! ssa_258 vec1 32 con ssa_260 = iabs! ssa_198.y | vec1 32 con ssa_260 = iadd! ssa_254, ssa_259 vec1 32 con ssa_261 = ilt32! ssa_198.y, ssa_8 | vec1 32 con ssa_261 = iadd! ssa_257, ssa_38 vec1 32 con ssa_262 = ixor! ssa_261, ssa_234 | vec1 32 con ssa_262 = uge32! ssa_260, ssa_226 vec1 32 con ssa_263 = umul_high! ssa_260, ssa_245 | vec1 32 con ssa_263 = b32csel! ssa_262, ssa_261, ssa_257 vec1 32 con ssa_264 = imul! ssa_263, ssa_232 | vec1 32 con ssa_264 = iadd! ssa_260, ssa_235 vec1 32 con ssa_265 = ineg! ssa_264 | vec1 32 con ssa_265 = b32csel! ssa_262, ssa_264, ssa_260 vec1 32 con ssa_266 = iadd! ssa_260, ssa_265 | vec1 32 con ssa_266 = iadd! ssa_263, ssa_38 vec1 32 con ssa_267 = iadd! ssa_263, ssa_38 | vec1 32 con ssa_267 = uge32! ssa_265, ssa_226 vec1 32 con ssa_268 = uge32! ssa_266, ssa_232 | vec1 32 con ssa_268 = b32csel! ssa_267, ssa_266, ssa_263 vec1 32 con ssa_269 = b32csel! ssa_268, ssa_267, ssa_263 | vec1 32 con ssa_269 = ineg! ssa_268 vec1 32 con ssa_270 = iadd! ssa_266, ssa_241 | vec1 32 con ssa_270 = b32csel! ssa_256, ssa_269, ssa_268 vec1 32 con ssa_271 = b32csel! ssa_268, ssa_270, ssa_266 | vec1 32 con ssa_271 = iabs! ssa_198.z vec1 32 con ssa_272 = iadd! ssa_269, ssa_38 | vec1 32 con ssa_272 = ilt32! ssa_198.z, ssa_8 vec1 32 con ssa_273 = uge32! ssa_271, ssa_232 | vec1 32 con ssa_273 = ixor! ssa_272, ssa_228 vec1 32 con ssa_274 = b32csel! ssa_273, ssa_272, ssa_269 | vec1 32 con ssa_274 = umul_high! ssa_271, ssa_239 vec1 32 con ssa_275 = ineg! ssa_274 | vec1 32 con ssa_275 = imul! ssa_274, ssa_226 vec1 32 con ssa_276 = b32csel! ssa_262, ssa_275, ssa_274 | vec1 32 con ssa_276 = ineg! ssa_275 vec1 32 con ssa_277 = iabs! ssa_198.z | vec1 32 con ssa_277 = iadd! ssa_271, ssa_276 vec1 32 con ssa_278 = ilt32! ssa_198.z, ssa_8 | vec1 32 con ssa_278 = iadd! ssa_274, ssa_38 vec1 32 con ssa_279 = ixor! ssa_278, ssa_234 | vec1 32 con ssa_279 = uge32! ssa_277, ssa_226 vec1 32 con ssa_280 = umul_high! ssa_277, ssa_245 | vec1 32 con ssa_280 = b32csel! ssa_279, ssa_278, ssa_274 vec1 32 con ssa_281 = imul! ssa_280, ssa_232 | vec1 32 con ssa_281 = iadd! ssa_277, ssa_235 vec1 32 con ssa_282 = ineg! ssa_281 | vec1 32 con ssa_282 = b32csel! ssa_279, ssa_281, ssa_277 vec1 32 con ssa_283 = iadd! ssa_277, ssa_282 | vec1 32 con ssa_283 = iadd! ssa_280, ssa_38 vec1 32 con ssa_284 = iadd! ssa_280, ssa_38 | vec1 32 con ssa_284 = uge32! ssa_282, ssa_226 vec1 32 con ssa_285 = uge32! ssa_283, ssa_232 | vec1 32 con ssa_285 = b32csel! ssa_284, ssa_283, ssa_280 vec1 32 con ssa_286 = b32csel! ssa_285, ssa_284, ssa_280 | vec1 32 con ssa_286 = ineg! ssa_285 vec1 32 con ssa_287 = iadd! ssa_283, ssa_241 | vec1 32 con ssa_287 = b32csel! ssa_273, ssa_286, ssa_285 vec1 32 con ssa_288 = b32csel! ssa_285, ssa_287, ssa_283 | vec1 32 con ssa_288 = iabs! ssa_198.w vec1 32 con ssa_289 = iadd! ssa_286, ssa_38 | vec1 32 con ssa_289 = ilt32! ssa_198.w, ssa_8 vec1 32 con ssa_290 = uge32! ssa_288, ssa_232 | vec1 32 con ssa_290 = ixor! ssa_289, ssa_228 vec1 32 con ssa_291 = b32csel! ssa_290, ssa_289, ssa_286 | vec1 32 con ssa_291 = umul_high! ssa_288, ssa_239 vec1 32 con ssa_292 = ineg! ssa_291 | vec1 32 con ssa_292 = imul! ssa_291, ssa_226 vec1 32 con ssa_293 = b32csel! ssa_279, ssa_292, ssa_291 | vec1 32 con ssa_293 = ineg! ssa_292 vec1 32 con ssa_294 = iabs! ssa_198.w | vec1 32 con ssa_294 = iadd! ssa_288, ssa_293 vec1 32 con ssa_295 = ilt32! ssa_198.w, ssa_8 | vec1 32 con ssa_295 = iadd! ssa_291, ssa_38 vec1 32 con ssa_296 = ixor! ssa_295, ssa_234 | vec1 32 con ssa_296 = uge32! ssa_294, ssa_226 vec1 32 con ssa_297 = umul_high! ssa_294, ssa_245 | vec1 32 con ssa_297 = b32csel! ssa_296, ssa_295, ssa_291 vec1 32 con ssa_298 = imul! ssa_297, ssa_232 | vec1 32 con ssa_298 = iadd! ssa_294, ssa_235 vec1 32 con ssa_299 = ineg! ssa_298 | vec1 32 con ssa_299 = b32csel! ssa_296, ssa_298, ssa_294 vec1 32 con ssa_300 = iadd! ssa_294, ssa_299 | vec1 32 con ssa_300 = iadd! ssa_297, ssa_38 vec1 32 con ssa_301 = iadd! ssa_297, ssa_38 | vec1 32 con ssa_301 = uge32! ssa_299, ssa_226 vec1 32 con ssa_302 = uge32! ssa_300, ssa_232 | vec1 32 con ssa_302 = b32csel! ssa_301, ssa_300, ssa_297 vec1 32 con ssa_303 = b32csel! ssa_302, ssa_301, ssa_297 | vec1 32 con ssa_303 = ineg! ssa_302 vec1 32 con ssa_304 = iadd! ssa_300, ssa_241 | vec1 32 con ssa_304 = b32csel! ssa_290, ssa_303, ssa_302 vec1 32 con ssa_305 = b32csel! ssa_302, ssa_304, ssa_300 | vec1 32 con ssa_305 = iabs! ssa_212.x vec1 32 con ssa_306 = iadd! ssa_303, ssa_38 | vec1 32 con ssa_306 = iabs! ssa_33.w vec1 32 con ssa_307 = uge32! ssa_305, ssa_232 | vec1 32 con ssa_307 = ilt32! ssa_212.x, ssa_8 vec1 32 con ssa_308 = b32csel! ssa_307, ssa_306, ssa_303 | vec1 32 con ssa_308 = ilt32! ssa_33.w, ssa_8 vec1 32 con ssa_309 = ineg! ssa_308 | vec1 32 con ssa_309 = ixor! ssa_307, ssa_308 vec1 32 con ssa_310 = b32csel! ssa_296, ssa_309, ssa_308 | vec1 32 con ssa_310 = u2f32! ssa_306 vec1 32 con ssa_311 = iabs! ssa_215.x | vec1 32 con ssa_311 = frcp! ssa_310 vec1 32 con ssa_312 = iabs! ssa_33.w | vec1 32 con ssa_312 = fmul! ssa_311, ssa_232 vec1 32 con ssa_313 = ilt32! ssa_215.x, ssa_8 | vec1 32 con ssa_313 = f2u32! ssa_312 vec1 32 con ssa_314 = ilt32! ssa_33.w, ssa_8 | vec1 32 con ssa_314 = ineg! ssa_306 vec1 32 con ssa_315 = ixor! ssa_313, ssa_314 | vec1 32 con ssa_315 = imul! ssa_306, ssa_313 vec1 32 con ssa_316 = u2f32! ssa_312 | vec1 32 con ssa_316 = ineg! ssa_315 vec1 32 con ssa_317 = frcp! ssa_316 | vec1 32 con ssa_317 = umul_high! ssa_313, ssa_316 vec1 32 con ssa_318 = fmul! ssa_317, ssa_238 | vec1 32 con ssa_318 = iadd! ssa_313, ssa_317 vec1 32 con ssa_319 = f2u32! ssa_318 | vec1 32 con ssa_319 = umul_high! ssa_305, ssa_318 vec1 32 con ssa_320 = ineg! ssa_312 | vec1 32 con ssa_320 = imul! ssa_319, ssa_306 vec1 32 con ssa_321 = imul! ssa_312, ssa_319 | vec1 32 con ssa_321 = ineg! ssa_320 vec1 32 con ssa_322 = ineg! ssa_321 | vec1 32 con ssa_322 = iadd! ssa_305, ssa_321 vec1 32 con ssa_323 = umul_high! ssa_319, ssa_322 | vec1 32 con ssa_323 = iadd! ssa_319, ssa_38 vec1 32 con ssa_324 = iadd! ssa_319, ssa_323 | vec1 32 con ssa_324 = uge32! ssa_322, ssa_306 vec1 32 con ssa_325 = umul_high! ssa_311, ssa_324 | vec1 32 con ssa_325 = b32csel! ssa_324, ssa_323, ssa_319 vec1 32 con ssa_326 = imul! ssa_325, ssa_312 | vec1 32 con ssa_326 = iadd! ssa_322, ssa_314 vec1 32 con ssa_327 = ineg! ssa_326 | vec1 32 con ssa_327 = b32csel! ssa_324, ssa_326, ssa_322 vec1 32 con ssa_328 = iadd! ssa_311, ssa_327 | vec1 32 con ssa_328 = iadd! ssa_325, ssa_38 vec1 32 con ssa_329 = iadd! ssa_325, ssa_38 | vec1 32 con ssa_329 = uge32! ssa_327, ssa_306 vec1 32 con ssa_330 = uge32! ssa_328, ssa_312 | vec1 32 con ssa_330 = b32csel! ssa_329, ssa_328, ssa_325 vec1 32 con ssa_331 = b32csel! ssa_330, ssa_329, ssa_325 | vec1 32 con ssa_331 = ineg! ssa_330 vec1 32 con ssa_332 = iadd! ssa_328, ssa_320 | vec1 32 con ssa_332 = b32csel! ssa_309, ssa_331, ssa_330 vec1 32 con ssa_333 = b32csel! ssa_330, ssa_332, ssa_328 | vec1 32 con ssa_333 = iabs! ssa_212.y vec1 32 con ssa_334 = iadd! ssa_331, ssa_38 | vec1 32 con ssa_334 = ilt32! ssa_212.y, ssa_8 vec1 32 con ssa_335 = uge32! ssa_333, ssa_312 | vec1 32 con ssa_335 = ixor! ssa_334, ssa_308 vec1 32 con ssa_336 = b32csel! ssa_335, ssa_334, ssa_331 | vec1 32 con ssa_336 = umul_high! ssa_333, ssa_318 vec1 32 con ssa_337 = ineg! ssa_336 | vec1 32 con ssa_337 = imul! ssa_336, ssa_306 vec1 32 con ssa_338 = b32csel! ssa_315, ssa_337, ssa_336 | vec1 32 con ssa_338 = ineg! ssa_337 vec1 32 con ssa_339 = iabs! ssa_215.y | vec1 32 con ssa_339 = iadd! ssa_333, ssa_338 vec1 32 con ssa_340 = ilt32! ssa_215.y, ssa_8 | vec1 32 con ssa_340 = iadd! ssa_336, ssa_38 vec1 32 con ssa_341 = ixor! ssa_340, ssa_314 | vec1 32 con ssa_341 = uge32! ssa_339, ssa_306 vec1 32 con ssa_342 = umul_high! ssa_339, ssa_324 | vec1 32 con ssa_342 = b32csel! ssa_341, ssa_340, ssa_336 vec1 32 con ssa_343 = imul! ssa_342, ssa_312 | vec1 32 con ssa_343 = iadd! ssa_339, ssa_314 vec1 32 con ssa_344 = ineg! ssa_343 | vec1 32 con ssa_344 = b32csel! ssa_341, ssa_343, ssa_339 vec1 32 con ssa_345 = iadd! ssa_339, ssa_344 | vec1 32 con ssa_345 = iadd! ssa_342, ssa_38 vec1 32 con ssa_346 = iadd! ssa_342, ssa_38 | vec1 32 con ssa_346 = uge32! ssa_344, ssa_306 vec1 32 con ssa_347 = uge32! ssa_345, ssa_312 | vec1 32 con ssa_347 = b32csel! ssa_346, ssa_345, ssa_342 vec1 32 con ssa_348 = b32csel! ssa_347, ssa_346, ssa_342 | vec1 32 con ssa_348 = ineg! ssa_347 vec1 32 con ssa_349 = iadd! ssa_345, ssa_320 | vec1 32 con ssa_349 = b32csel! ssa_335, ssa_348, ssa_347 vec1 32 con ssa_350 = b32csel! ssa_347, ssa_349, ssa_345 | vec1 32 con ssa_350 = iabs! ssa_212.z vec1 32 con ssa_351 = iadd! ssa_348, ssa_38 | vec1 32 con ssa_351 = ilt32! ssa_212.z, ssa_8 vec1 32 con ssa_352 = uge32! ssa_350, ssa_312 | vec1 32 con ssa_352 = ixor! ssa_351, ssa_308 vec1 32 con ssa_353 = b32csel! ssa_352, ssa_351, ssa_348 | vec1 32 con ssa_353 = umul_high! ssa_350, ssa_318 vec1 32 con ssa_354 = ineg! ssa_353 | vec1 32 con ssa_354 = imul! ssa_353, ssa_306 vec1 32 con ssa_355 = b32csel! ssa_341, ssa_354, ssa_353 | vec1 32 con ssa_355 = ineg! ssa_354 vec1 32 con ssa_356 = iabs! ssa_215.z | vec1 32 con ssa_356 = iadd! ssa_350, ssa_355 vec1 32 con ssa_357 = ilt32! ssa_215.z, ssa_8 | vec1 32 con ssa_357 = iadd! ssa_353, ssa_38 vec1 32 con ssa_358 = ixor! ssa_357, ssa_314 | vec1 32 con ssa_358 = uge32! ssa_356, ssa_306 vec1 32 con ssa_359 = umul_high! ssa_356, ssa_324 | vec1 32 con ssa_359 = b32csel! ssa_358, ssa_357, ssa_353 vec1 32 con ssa_360 = imul! ssa_359, ssa_312 | vec1 32 con ssa_360 = iadd! ssa_356, ssa_314 vec1 32 con ssa_361 = ineg! ssa_360 | vec1 32 con ssa_361 = b32csel! ssa_358, ssa_360, ssa_356 vec1 32 con ssa_362 = iadd! ssa_356, ssa_361 | vec1 32 con ssa_362 = iadd! ssa_359, ssa_38 vec1 32 con ssa_363 = iadd! ssa_359, ssa_38 | vec1 32 con ssa_363 = uge32! ssa_361, ssa_306 vec1 32 con ssa_364 = uge32! ssa_362, ssa_312 | vec1 32 con ssa_364 = b32csel! ssa_363, ssa_362, ssa_359 vec1 32 con ssa_365 = b32csel! ssa_364, ssa_363, ssa_359 | vec1 32 con ssa_365 = ineg! ssa_364 vec1 32 con ssa_366 = iadd! ssa_362, ssa_320 | vec1 32 con ssa_366 = b32csel! ssa_352, ssa_365, ssa_364 vec1 32 con ssa_367 = b32csel! ssa_364, ssa_366, ssa_362 | vec1 32 con ssa_367 = iabs! ssa_212.w vec1 32 con ssa_368 = iadd! ssa_365, ssa_38 | vec1 32 con ssa_368 = ilt32! ssa_212.w, ssa_8 vec1 32 con ssa_369 = uge32! ssa_367, ssa_312 | vec1 32 con ssa_369 = ixor! ssa_368, ssa_308 vec1 32 con ssa_370 = b32csel! ssa_369, ssa_368, ssa_365 | vec1 32 con ssa_370 = umul_high! ssa_367, ssa_318 vec1 32 con ssa_371 = ineg! ssa_370 | vec1 32 con ssa_371 = imul! ssa_370, ssa_306 vec1 32 con ssa_372 = b32csel! ssa_358, ssa_371, ssa_370 | vec1 32 con ssa_372 = ineg! ssa_371 vec1 32 con ssa_373 = iabs! ssa_215.w | vec1 32 con ssa_373 = iadd! ssa_367, ssa_372 vec1 32 con ssa_374 = ilt32! ssa_215.w, ssa_8 | vec1 32 con ssa_374 = iadd! ssa_370, ssa_38 vec1 32 con ssa_375 = ixor! ssa_374, ssa_314 | vec1 32 con ssa_375 = uge32! ssa_373, ssa_306 vec1 32 con ssa_376 = umul_high! ssa_373, ssa_324 | vec1 32 con ssa_376 = b32csel! ssa_375, ssa_374, ssa_370 vec1 32 con ssa_377 = imul! ssa_376, ssa_312 | vec1 32 con ssa_377 = iadd! ssa_373, ssa_314 vec1 32 con ssa_378 = ineg! ssa_377 | vec1 32 con ssa_378 = b32csel! ssa_375, ssa_377, ssa_373 vec1 32 con ssa_379 = iadd! ssa_373, ssa_378 | vec1 32 con ssa_379 = iadd! ssa_376, ssa_38 vec1 32 con ssa_380 = iadd! ssa_376, ssa_38 | vec1 32 con ssa_380 = uge32! ssa_378, ssa_306 vec1 32 con ssa_381 = uge32! ssa_379, ssa_312 | vec1 32 con ssa_381 = b32csel! ssa_380, ssa_379, ssa_376 vec1 32 con ssa_382 = b32csel! ssa_381, ssa_380, ssa_376 | vec1 32 con ssa_382 = ineg! ssa_381 vec1 32 con ssa_383 = iadd! ssa_379, ssa_320 | vec1 32 con ssa_383 = b32csel! ssa_369, ssa_382, ssa_381 vec1 32 con ssa_384 = b32csel! ssa_381, ssa_383, ssa_379 | vec1 32 div ssa_384 = ineg ssa_207 vec1 32 con ssa_385 = iadd! ssa_382, ssa_38 | vec1 32 div ssa_385 = iadd ssa_196.x, ssa_384 vec1 32 con ssa_386 = uge32! ssa_384, ssa_312 | vec1 32 div ssa_386 = iadd3 ssa_39, ssa_208, ssa_196.y vec1 32 con ssa_387 = b32csel! ssa_386, ssa_385, ssa_382 | vec1 32 div ssa_387 = iadd3 ssa_40, ssa_209, ssa_196.z vec1 32 con ssa_388 = ineg! ssa_387 | vec1 32 div ssa_388 = iadd3 ssa_41, ssa_210, ssa_196.w vec1 32 con ssa_389 = b32csel! ssa_375, ssa_388, ssa_387 | vec1 32 div ssa_389 = iabs ssa_385 vec1 32 div ssa_390 = ineg ssa_207 | vec1 32 div ssa_390 = iabs ssa_386 vec1 32 div ssa_391 = iadd ssa_196.x, ssa_390 | vec1 32 div ssa_391 = iabs ssa_387 vec1 32 div ssa_392 = ineg ssa_211 | vec1 32 div ssa_392 = iabs ssa_388 vec1 32 div ssa_393 = iadd ssa_196.y, ssa_392 | vec1 32 div ssa_393 = ineg ssa_221 vec1 32 div ssa_394 = ineg ssa_212 | vec1 32 div ssa_394 = iadd ssa_196.x, ssa_393 vec1 32 div ssa_395 = iadd ssa_196.z, ssa_394 | vec1 32 div ssa_395 = iadd3 ssa_39, ssa_222, ssa_196.y vec1 32 div ssa_396 = ineg ssa_213 | vec1 32 div ssa_396 = iadd3 ssa_40, ssa_223, ssa_196.z vec1 32 div ssa_397 = iadd ssa_196.w, ssa_396 | vec1 32 div ssa_397 = iadd3 ssa_41, ssa_224, ssa_196.w vec1 32 div ssa_398 = iabs ssa_391 | vec1 32 div ssa_398 = iabs ssa_394 vec1 32 div ssa_399 = iabs ssa_393 | vec1 32 div ssa_399 = iabs ssa_395 vec1 32 div ssa_400 = iabs ssa_395 | vec1 32 div ssa_400 = iabs ssa_396 vec1 32 div ssa_401 = iabs ssa_397 vec1 32 div ssa_401 = iabs ssa_397 vec1 32 div ssa_402 = ineg ssa_224 | vec1 32 div ssa_402 = ige32 ssa_332, ssa_398 vec1 32 div ssa_403 = iadd ssa_196.x, ssa_402 | vec1 32 div ssa_403 = ige32 ssa_253, ssa_389 vec1 32 div ssa_404 = ineg ssa_228 | vec1 32 div ssa_404 = ior ssa_403, ssa_402 vec1 32 div ssa_405 = iadd ssa_196.y, ssa_404 | vec1 32 div ssa_405 = ige32 ssa_270, ssa_390 vec1 32 div ssa_406 = ineg ssa_229 | vec1 32 div ssa_406 = ige32 ssa_349, ssa_399 vec1 32 div ssa_407 = iadd ssa_196.z, ssa_406 | vec1 32 div ssa_407 = ior ssa_405, ssa_406 vec1 32 div ssa_408 = ineg ssa_230 | vec1 32 div ssa_408 = ige32 ssa_287, ssa_391 vec1 32 div ssa_409 = iadd ssa_196.w, ssa_408 | vec1 32 div ssa_409 = ige32 ssa_366, ssa_400 vec1 32 div ssa_410 = iabs ssa_403 | vec1 32 div ssa_410 = ior ssa_408, ssa_409 vec1 32 div ssa_411 = iabs ssa_405 | vec1 32 div ssa_411 = ige32 ssa_304, ssa_392 vec1 32 div ssa_412 = iabs ssa_407 | vec1 32 div ssa_412 = ige32 ssa_383, ssa_401 vec1 32 div ssa_413 = iabs ssa_409 | vec1 32 div ssa_413 = ior ssa_411, ssa_412 vec1 32 div ssa_414 = ige32 ssa_338, ssa_410 | vec1 32 div ssa_414 = iand ssa_413, ssa_410 vec1 32 div ssa_415 = ige32 ssa_259, ssa_398 | vec1 32 div ssa_415 = iand ssa_414, ssa_407 vec1 32 div ssa_416 = ior ssa_415, ssa_414 | vec1 32 div ssa_416 = iand ssa_415, ssa_404 vec1 32 div ssa_417 = ige32 ssa_276, ssa_399 < vec1 32 div ssa_418 = ige32 ssa_355, ssa_411 < vec1 32 div ssa_419 = ior ssa_417, ssa_418 < vec1 32 div ssa_420 = ige32 ssa_293, ssa_400 < vec1 32 div ssa_421 = ige32 ssa_372, ssa_412 < vec1 32 div ssa_422 = ior ssa_420, ssa_421 < vec1 32 div ssa_423 = ige32 ssa_310, ssa_401 < vec1 32 div ssa_424 = ige32 ssa_389, ssa_413 < vec1 32 div ssa_425 = ior ssa_423, ssa_424 < vec1 32 div ssa_426 = iand ssa_425, ssa_422 < vec1 32 div ssa_427 = iand ssa_426, ssa_419 < vec1 32 div ssa_428 = iand ssa_427, ssa_416 < /* succs: block_15 block_19 */ /* succs: block_15 block_19 */ if ssa_428 { | if ssa_416 { block block_15: block block_15: /* preds: block_14 */ /* preds: block_14 */ vec1 32 con ssa_429 = load_const (0x00000008 = 0.000000) | vec1 32 con ssa_417 = load_const (0x00000008 = 0.000000) vec1 32 con ssa_430 = intrinsic reduce (ssa_38) (reduction_op=iadd /*257*/, cluster_size=0) | vec1 32 con ssa_418 = intrinsic reduce (ssa_38) (reduction_op=iadd /*257*/, cluster_size=0) vec1 32 div ssa_431 = intrinsic first_invocation () () | vec1 32 div ssa_419 = intrinsic first_invocation () () vec1 32 div ssa_432 = intrinsic load_subgroup_invocation () () | vec1 32 div ssa_420 = intrinsic load_subgroup_invocation () () vec1 32 div ssa_433 = ieq32 ssa_432, ssa_431 | vec1 32 div ssa_421 = ieq32 ssa_420, ssa_419 /* succs: block_16 block_17 */ /* succs: block_16 block_17 */ if ssa_433 { | if ssa_421 { block block_16: block block_16: /* preds: block_15 */ /* preds: block_15 */ vec1 32 div ssa_434 = intrinsic ssbo_atomic (ssa_18, ssa_429, ssa_430) (access=1, ato | vec1 32 div ssa_422 = intrinsic ssbo_atomic (ssa_18, ssa_417, ssa_418) (access=1, ato /* succs: block_18 */ /* succs: block_18 */ } else { } else { block block_17: block block_17: /* preds: block_15 */ /* preds: block_15 */ /* succs: block_18 */ /* succs: block_18 */ } } block block_18: block block_18: /* preds: block_16 block_17 */ /* preds: block_16 block_17 */ /* succs: block_20 */ /* succs: block_20 */ } else { } else { block block_19: block block_19: /* preds: block_14 */ /* preds: block_14 */ /* succs: block_20 */ /* succs: block_20 */ } } block block_20: block block_20: /* preds: block_18 block_19 */ /* preds: block_18 block_19 */ vec1 32 div ssa_435 = phi block_18: ssa_8, block_19: ssa_117 | vec1 32 div ssa_423 = phi block_18: ssa_8, block_19: ssa_117 vec1 32 div ssa_436 = phi block_18: ssa_117, block_19: ssa_8 | vec1 32 div ssa_424 = phi block_18: ssa_117, block_19: ssa_8 vec4 32 div ssa_437 = vec4 ssa_435, ssa_436, ssa_8, ssa_117 | vec4 32 div ssa_425 = vec4 ssa_423, ssa_424, ssa_8, ssa_117 vec4 32 div ssa_438 = vec4 ssa_45, ssa_46, ssa_18, ssa_3 | vec4 32 div ssa_426 = vec4 ssa_45, ssa_46, ssa_18, ssa_3 intrinsic image_store (ssa_22, ssa_438, ssa_2, ssa_437, ssa_8) (image_dim=2D /*1*/, image_array=true | intrinsic image_store (ssa_22, ssa_426, ssa_2, ssa_425, ssa_8) (image_dim=2D /*1*/, image_array=true vec4 32 div ssa_439 = (uint32)txf ssa_57 (coord), ssa_8 (lod), 7 (texture) | vec4 32 div ssa_427 = (uint32)txf ssa_57 (coord), ssa_8 (lod), 7 (texture) vec1 32 con ssa_440 = load_const (0x00000074 = 0.000000) | vec1 32 con ssa_428 = load_const (0x00000074 = 0.000000) vec1 32 con ssa_441 = intrinsic load_uniform (ssa_440) (base=0, range=120, dest_type=invalid /*256*/) | vec1 32 con ssa_429 = intrinsic load_uniform (ssa_428) (base=0, range=120, dest_type=invalid /*256*/) vec1 32 con ssa_442 = ineg ssa_441 | vec1 32 con ssa_430 = ineg ssa_429 vec1 32 div ssa_443 = iadd ssa_439.x, ssa_442 | vec1 32 div ssa_431 = iadd ssa_427.x, ssa_430 vec1 32 div ssa_444 = uge32! ssa_8, ssa_443 | vec1 32 div ssa_432 = uge32! ssa_8, ssa_431 /* succs: block_21 block_25 */ /* succs: block_21 block_25 */ if ssa_444 { | if ssa_432 { block block_21: block block_21: /* preds: block_20 */ /* preds: block_20 */ vec1 32 con ssa_445 = intrinsic reduce (ssa_38) (reduction_op=iadd /*257*/, cluster_size=0) | vec1 32 con ssa_433 = intrinsic reduce (ssa_38) (reduction_op=iadd /*257*/, cluster_size=0) vec1 32 div ssa_446 = intrinsic first_invocation () () | vec1 32 div ssa_434 = intrinsic first_invocation () () vec1 32 div ssa_447 = intrinsic load_subgroup_invocation () () | vec1 32 div ssa_435 = intrinsic load_subgroup_invocation () () vec1 32 div ssa_448 = ieq32 ssa_447, ssa_446 | vec1 32 div ssa_436 = ieq32 ssa_435, ssa_434 /* succs: block_22 block_23 */ /* succs: block_22 block_23 */ if ssa_448 { | if ssa_436 { block block_22: block block_22: /* preds: block_21 */ /* preds: block_21 */ vec1 32 div ssa_449 = intrinsic ssbo_atomic (ssa_18, ssa_37, ssa_445) (access=1, atom | vec1 32 div ssa_437 = intrinsic ssbo_atomic (ssa_18, ssa_37, ssa_433) (access=1, atom /* succs: block_24 */ /* succs: block_24 */ } else { } else { block block_23: block block_23: /* preds: block_21 */ /* preds: block_21 */ /* succs: block_24 */ /* succs: block_24 */ } } block block_24: block block_24: /* preds: block_22 block_23 */ /* preds: block_22 block_23 */ /* succs: block_26 */ /* succs: block_26 */ } else { } else { block block_25: block block_25: /* preds: block_20 */ /* preds: block_20 */ /* succs: block_26 */ /* succs: block_26 */ } } block block_26: block block_26: /* preds: block_24 block_25 */ /* preds: block_24 block_25 */ vec1 32 div ssa_450 = phi block_24: ssa_8, block_25: ssa_117 | vec1 32 div ssa_438 = phi block_24: ssa_8, block_25: ssa_117 vec1 32 div ssa_451 = phi block_24: ssa_117, block_25: ssa_8 | vec1 32 div ssa_439 = phi block_24: ssa_117, block_25: ssa_8 vec4 32 div ssa_452 = vec4 ssa_450, ssa_451, ssa_8, ssa_117 | vec4 32 div ssa_440 = vec4 ssa_438, ssa_439, ssa_8, ssa_117 vec4 32 div ssa_453 = vec4 ssa_45, ssa_46, ssa_14, ssa_1 | vec4 32 div ssa_441 = vec4 ssa_45, ssa_46, ssa_14, ssa_1 intrinsic image_store (ssa_22, ssa_453, ssa_0, ssa_452, ssa_8) (image_dim=2D /*1*/, image_array=true | intrinsic image_store (ssa_22, ssa_441, ssa_0, ssa_440, ssa_8) (image_dim=2D /*1*/, image_array=true /* succs: block_27 */ /* succs: block_27 */ } } block block_27: block block_27: /* preds: block_1 block_26 */ /* preds: block_1 block_26 */ /* succs: block_28 */ /* succs: block_28 */ block block_28: block block_28: } } NIR (final form) for compute shader: NIR (final form) for compute shader: shader: MESA_SHADER_COMPUTE shader: MESA_SHADER_COMPUTE source_sha1: {0x4080c608, 0xef4e4e6b, 0x82f838bb, 0x041ba6fe, 0x4a36e587} source_sha1: {0x4080c608, 0xef4e4e6b, 0x82f838bb, 0x041ba6fe, 0x4a36e587} workgroup-size: 8, 8, 1 workgroup-size: 8, 8, 1 shared-size: 0 shared-size: 0 stage: 5 stage: 5 next_stage: 0 next_stage: 0 num_textures: 4 num_textures: 4 num_ssbos: 1 num_ssbos: 1 num_images: 1 num_images: 1 system_values_read: 0x00000000'00000020'00000000 system_values_read: 0x00000000'00000020'00000000 subgroup_size: 2 subgroup_size: 2 divergence_analysis_run: true divergence_analysis_run: true bit_sizes_float: 0x20 bit_sizes_float: 0x20 bit_sizes_int: 0x21 bit_sizes_int: 0x21 separate_shader: true separate_shader: true writes_memory: true writes_memory: true ptr_size: 0 ptr_size: 0 inputs: 0 inputs: 0 outputs: 0 outputs: 0 uniforms: 516 uniforms: 516 decl_var push_const INTERP_MODE_NONE block @0 decl_var push_const INTERP_MODE_NONE block @0 decl_var uniform INTERP_MODE_NONE restrict texture2D @1 (~0, 0, 1) decl_var uniform INTERP_MODE_NONE restrict texture2D @1 (~0, 0, 1) decl_var ssbo INTERP_MODE_NONE restrict writeonly block @2 (~0, 0, 0) decl_var ssbo INTERP_MODE_NONE restrict writeonly block @2 (~0, 0, 0) decl_var image INTERP_MODE_NONE restrict writeonly r8g8b8a8_unorm image2DArray @3 (~0, 0, 6) decl_var image INTERP_MODE_NONE restrict writeonly r8g8b8a8_unorm image2DArray @3 (~0, 0, 6) decl_var uniform INTERP_MODE_NONE restrict texture2D @4 (~0, 0, 2) decl_var uniform INTERP_MODE_NONE restrict texture2D @4 (~0, 0, 2) decl_var uniform INTERP_MODE_NONE restrict itexture2D @5 (~0, 0, 3) decl_var uniform INTERP_MODE_NONE restrict itexture2D @5 (~0, 0, 3) decl_var uniform INTERP_MODE_NONE restrict utexture2D @6 (~0, 0, 5) decl_var uniform INTERP_MODE_NONE restrict utexture2D @6 (~0, 0, 5) decl_function main (0 params) decl_function main (0 params) impl main { impl main { decl_reg vec1 32 div r0 decl_reg vec1 32 div r0 decl_reg vec1 32 div r1 decl_reg vec1 32 div r1 decl_reg vec1 32 div r2 decl_reg vec1 32 div r2 decl_reg vec1 32 div r3 decl_reg vec1 32 div r3 decl_reg vec1 32 div r4 decl_reg vec1 32 div r4 decl_reg vec1 32 div r5 decl_reg vec1 32 div r5 decl_reg vec1 32 div r6 decl_reg vec1 32 div r6 decl_reg vec1 32 div r7 decl_reg vec1 32 div r7 block block_0: block block_0: /* preds: */ /* preds: */ vec1 32 con ssa_0 = undefined vec1 32 con ssa_0 = undefined vec1 32 con ssa_1 = undefined vec1 32 con ssa_1 = undefined vec1 32 con ssa_2 = undefined vec1 32 con ssa_2 = undefined vec1 32 con ssa_3 = undefined vec1 32 con ssa_3 = undefined vec1 32 con ssa_4 = undefined vec1 32 con ssa_4 = undefined vec1 32 con ssa_5 = undefined vec1 32 con ssa_5 = undefined vec1 32 con ssa_6 = undefined vec1 32 con ssa_6 = undefined vec1 32 con ssa_7 = undefined vec1 32 con ssa_7 = undefined vec1 32 con ssa_8 = load_const (0x00000000 = 0.000000) vec1 32 con ssa_8 = load_const (0x00000000 = 0.000000) vec2 32 con ssa_9 = intrinsic load_uniform (ssa_8) (base=504, range=12, dest_type=uint /*4*/) vec2 32 con ssa_9 = intrinsic load_uniform (ssa_8) (base=504, range=12, dest_type=uint /*4*/) vec3 32 con ssa_10 = intrinsic load_workgroup_id_zero_base () () vec3 32 con ssa_10 = intrinsic load_workgroup_id_zero_base () () vec1 32 con ssa_11 = iadd ssa_10.x, ssa_9.x vec1 32 con ssa_11 = iadd ssa_10.x, ssa_9.x vec1 32 con ssa_12 = iadd ssa_10.y, ssa_9.y vec1 32 con ssa_12 = iadd ssa_10.y, ssa_9.y vec1 32 con ssa_13 = intrinsic load_subgroup_id () () vec1 32 con ssa_13 = intrinsic load_subgroup_id () () vec1 32 con ssa_14 = load_const (0x00000004 = 0.000000) vec1 32 con ssa_14 = load_const (0x00000004 = 0.000000) vec1 32 con ssa_15 = ishl ssa_13, ssa_14 vec1 32 con ssa_15 = ishl ssa_13, ssa_14 vec1 32 div ssa_16 = intrinsic load_subgroup_invocation () () vec1 32 div ssa_16 = intrinsic load_subgroup_invocation () () vec1 32 div ssa_17 = iadd ssa_16, ssa_15 vec1 32 div ssa_17 = iadd ssa_16, ssa_15 vec1 32 con ssa_18 = load_const (0x00000002 = 0.000000) vec1 32 con ssa_18 = load_const (0x00000002 = 0.000000) vec1 32 div ssa_19 = ushr ssa_17, ssa_18 vec1 32 div ssa_19 = ushr ssa_17, ssa_18 vec1 32 con ssa_20 = load_const (0x00000007 = 0.000000) vec1 32 con ssa_20 = load_const (0x00000007 = 0.000000) vec1 32 div ssa_21 = iand ssa_19, ssa_20 vec1 32 div ssa_21 = iand ssa_19, ssa_20 vec1 32 con ssa_22 = load_const (0x00000003 = 0.000000) vec1 32 con ssa_22 = load_const (0x00000003 = 0.000000) vec1 32 con ssa_23 = load_const (0x00000005 = 0.000000) vec1 32 con ssa_23 = load_const (0x00000005 = 0.000000) vec1 32 div ssa_24 = ushr ssa_17, ssa_23 vec1 32 div ssa_24 = ushr ssa_17, ssa_23 vec1 32 div ssa_25 = ishl ssa_24, ssa_18 vec1 32 div ssa_25 = ishl ssa_24, ssa_18 vec1 32 div ssa_26 = iand ssa_17, ssa_22 vec1 32 div ssa_26 = iand ssa_17, ssa_22 vec1 32 div ssa_27 = iadd ssa_26, ssa_25 vec1 32 div ssa_27 = iadd ssa_26, ssa_25 vec1 32 div ssa_28 = iand ssa_27, ssa_20 vec1 32 div ssa_28 = iand ssa_27, ssa_20 vec1 32 con ssa_29 = ishl ssa_11, ssa_22 vec1 32 con ssa_29 = ishl ssa_11, ssa_22 vec1 32 con ssa_30 = ishl ssa_12, ssa_22 vec1 32 con ssa_30 = ishl ssa_12, ssa_22 vec1 32 div ssa_31 = iadd ssa_29, ssa_21 vec1 32 div ssa_31 = iadd ssa_29, ssa_21 vec1 32 div ssa_32 = iadd ssa_30, ssa_28 vec1 32 div ssa_32 = iadd ssa_30, ssa_28 vec4 32 con ssa_33 = intrinsic load_uniform (ssa_8) (base=0, range=120, dest_type=invalid /*256*/) vec4 32 con ssa_33 = intrinsic load_uniform (ssa_8) (base=0, range=120, dest_type=invalid /*256*/) vec1 32 div ssa_34 = uge32 ssa_32, ssa_33.w vec1 32 div ssa_34 = uge32 ssa_32, ssa_33.w vec1 32 div ssa_35 = uge32 ssa_31, ssa_33.z vec1 32 div ssa_35 = uge32 ssa_31, ssa_33.z vec1 32 div ssa_36 = ior ssa_34, ssa_35 vec1 32 div ssa_36 = ior ssa_34, ssa_35 /* succs: block_1 block_2 */ /* succs: block_1 block_2 */ if ssa_36 { if ssa_36 { block block_1: block block_1: /* preds: block_0 */ /* preds: block_0 */ /* succs: block_27 */ /* succs: block_27 */ } else { } else { block block_2: block block_2: /* preds: block_0 */ /* preds: block_0 */ vec1 32 con ssa_37 = load_const (0x00000010 = 0.000000) vec1 32 con ssa_37 = load_const (0x00000010 = 0.000000) vec1 32 con ssa_38 = load_const (0x00000001 = 0.000000) vec1 32 con ssa_38 = load_const (0x00000001 = 0.000000) vec1 32 con ssa_39 = load_const (0xffffffac = -nan) vec1 32 con ssa_39 = load_const (0xffffffac = -nan) vec1 32 con ssa_40 = load_const (0xffffffe0 = -nan) vec1 32 con ssa_40 = load_const (0xffffffe0 = -nan) vec1 32 con ssa_41 = load_const (0xffffff9d = -nan) vec1 32 con ssa_41 = load_const (0xffffff9d = -nan) vec1 32 con ssa_42 = load_const (0x3b000000 = 0.001953) vec1 32 con ssa_42 = load_const (0x3b000000 = 0.001953) vec1 32 con ssa_43 = load_const (0x3c008081 = 0.007843) vec1 32 con ssa_43 = load_const (0x3c008081 = 0.007843) vec1 32 con ssa_44 = load_const (0x3f000000 = 0.500000) vec1 32 con ssa_44 = load_const (0x3f000000 = 0.500000) vec1 32 div ssa_45 = iadd ssa_33.x, ssa_31 vec1 32 div ssa_45 = iadd ssa_33.x, ssa_31 vec1 32 div ssa_46 = iadd ssa_33.y, ssa_32 vec1 32 div ssa_46 = iadd ssa_33.y, ssa_32 vec1 32 div ssa_47 = u2f32 ssa_31 vec1 32 div ssa_47 = u2f32 ssa_31 vec1 32 div ssa_48 = u2f32 ssa_32 vec1 32 div ssa_48 = u2f32 ssa_32 vec1 32 div ssa_49 = fadd ssa_47, ssa_44 vec1 32 div ssa_49 = fadd ssa_47, ssa_44 vec1 32 div ssa_50 = fadd ssa_48, ssa_44 vec1 32 div ssa_50 = fadd ssa_48, ssa_44 vec1 32 con ssa_51 = u2f32 ssa_33.z vec1 32 con ssa_51 = u2f32 ssa_33.z vec1 32 con ssa_52 = u2f32 ssa_33.w vec1 32 con ssa_52 = u2f32 ssa_33.w vec1 32 con ssa_53 = frcp ssa_51 vec1 32 con ssa_53 = frcp ssa_51 vec1 32 div ssa_54 = fmul ssa_49, ssa_53 vec1 32 div ssa_54 = fmul ssa_49, ssa_53 vec1 32 con ssa_55 = frcp ssa_52 vec1 32 con ssa_55 = frcp ssa_52 vec1 32 div ssa_56 = fmul ssa_50, ssa_55 vec1 32 div ssa_56 = fmul ssa_50, ssa_55 vec2 32 div ssa_57 = vec2 ssa_45, ssa_46 vec2 32 div ssa_57 = vec2 ssa_45, ssa_46 vec4 32 div ssa_58 = (float32)txf ssa_57 (coord), ssa_8 (lod), 4 (texture) vec4 32 div ssa_58 = (float32)txf ssa_57 (coord), ssa_8 (lod), 4 (texture) vec4 32 con ssa_59 = intrinsic load_uniform (ssa_37) (base=0, range=120, dest_type=invalid /*256*/) vec4 32 con ssa_59 = intrinsic load_uniform (ssa_37) (base=0, range=120, dest_type=invalid /*256*/) vec1 32 con ssa_60 = load_const (0x00000020 = 0.000000) vec1 32 con ssa_60 = load_const (0x00000020 = 0.000000) vec4 32 con ssa_61 = intrinsic load_uniform (ssa_60) (base=0, range=120, dest_type=invalid /*256*/) vec4 32 con ssa_61 = intrinsic load_uniform (ssa_60) (base=0, range=120, dest_type=invalid /*256*/) vec1 32 con ssa_62 = fneg ssa_61.x vec1 32 con ssa_62 = fneg ssa_61.x vec1 32 div ssa_63 = fmul ssa_62, ssa_56 vec1 32 div ssa_63 = fmul ssa_62, ssa_56 vec1 32 con ssa_64 = fneg ssa_61.y vec1 32 con ssa_64 = fneg ssa_61.y vec1 32 div ssa_65 = fmul ssa_64, ssa_56 vec1 32 div ssa_65 = fmul ssa_64, ssa_56 vec1 32 con ssa_66 = fneg ssa_61.z vec1 32 con ssa_66 = fneg ssa_61.z vec1 32 div ssa_67 = fmul ssa_66, ssa_56 vec1 32 div ssa_67 = fmul ssa_66, ssa_56 vec1 32 con ssa_68 = fneg ssa_61.w vec1 32 con ssa_68 = fneg ssa_61.w vec1 32 div ssa_69 = fmul ssa_68, ssa_56 vec1 32 div ssa_69 = fmul ssa_68, ssa_56 vec1 32 con ssa_70 = fneg ssa_59.x vec1 32 con ssa_70 = fneg ssa_59.x vec1 32 div ssa_71 = ffma ssa_70, ssa_54, ssa_63 vec1 32 div ssa_71 = ffma ssa_70, ssa_54, ssa_63 vec1 32 con ssa_72 = fneg ssa_59.y vec1 32 con ssa_72 = fneg ssa_59.y vec1 32 div ssa_73 = ffma ssa_72, ssa_54, ssa_65 vec1 32 div ssa_73 = ffma ssa_72, ssa_54, ssa_65 vec1 32 con ssa_74 = fneg ssa_59.z vec1 32 con ssa_74 = fneg ssa_59.z vec1 32 div ssa_75 = ffma ssa_74, ssa_54, ssa_67 vec1 32 div ssa_75 = ffma ssa_74, ssa_54, ssa_67 vec1 32 con ssa_76 = fneg ssa_59.w vec1 32 con ssa_76 = fneg ssa_59.w vec1 32 div ssa_77 = ffma ssa_76, ssa_54, ssa_69 vec1 32 div ssa_77 = ffma ssa_76, ssa_54, ssa_69 vec1 32 con ssa_78 = load_const (0xbd85573d = -0.065108) vec1 32 con ssa_78 = load_const (0xbd85573d = -0.065108) vec1 32 div ssa_79 = ffma ssa_71, ssa_44, ssa_78 vec1 32 div ssa_79 = ffma ssa_71, ssa_44, ssa_78 vec1 32 con ssa_80 = load_const (0xbdc88c03 = -0.097923) vec1 32 con ssa_80 = load_const (0xbdc88c03 = -0.097923) vec1 32 div ssa_81 = ffma ssa_73, ssa_44, ssa_80 vec1 32 div ssa_81 = ffma ssa_73, ssa_44, ssa_80 vec1 32 con ssa_82 = load_const (0xbd9d07d6 = -0.076675) vec1 32 con ssa_82 = load_const (0xbd9d07d6 = -0.076675) vec1 32 div ssa_83 = ffma ssa_75, ssa_44, ssa_82 vec1 32 div ssa_83 = ffma ssa_75, ssa_44, ssa_82 vec1 32 con ssa_84 = load_const (0xbd97cde7 = -0.074123) vec1 32 con ssa_84 = load_const (0xbd97cde7 = -0.074123) vec1 32 div ssa_85 = ffma ssa_77, ssa_44, ssa_84 vec1 32 div ssa_85 = ffma ssa_77, ssa_44, ssa_84 vec1 32 con ssa_86 = fmul ssa_59.x, ssa_53 vec1 32 con ssa_86 = fmul ssa_59.x, ssa_53 vec1 32 con ssa_87 = fmul ssa_59.y, ssa_53 vec1 32 con ssa_87 = fmul ssa_59.y, ssa_53 vec1 32 con ssa_88 = fmul ssa_59.z, ssa_53 vec1 32 con ssa_88 = fmul ssa_59.z, ssa_53 vec1 32 con ssa_89 = fmul ssa_59.w, ssa_53 vec1 32 con ssa_89 = fmul ssa_59.w, ssa_53 vec1 32 con ssa_90 = fmul ssa_61.x, ssa_55 vec1 32 con ssa_90 = fmul ssa_61.x, ssa_55 vec1 32 con ssa_91 = fmul ssa_61.y, ssa_55 vec1 32 con ssa_91 = fmul ssa_61.y, ssa_55 vec1 32 con ssa_92 = fmul ssa_61.z, ssa_55 vec1 32 con ssa_92 = fmul ssa_61.z, ssa_55 vec1 32 con ssa_93 = fmul ssa_61.w, ssa_55 vec1 32 con ssa_93 = fmul ssa_61.w, ssa_55 vec1 32 con ssa_94 = fmax ssa_86, ssa_90 vec1 32 con ssa_94 = fmax ssa_86, ssa_90 vec1 32 con ssa_95 = fmax ssa_87, ssa_91 vec1 32 con ssa_95 = fmax ssa_87, ssa_91 vec1 32 con ssa_96 = fmax ssa_88, ssa_92 vec1 32 con ssa_96 = fmax ssa_88, ssa_92 vec1 32 con ssa_97 = fmax ssa_89, ssa_93 vec1 32 con ssa_97 = fmax ssa_89, ssa_93 vec1 32 con ssa_98 = fadd ssa_94, ssa_43 vec1 32 con ssa_98 = fadd ssa_94, ssa_43 vec1 32 con ssa_99 = fadd ssa_95, ssa_43 vec1 32 con ssa_99 = fadd ssa_95, ssa_43 vec1 32 con ssa_100 = fadd ssa_96, ssa_43 vec1 32 con ssa_100 = fadd ssa_96, ssa_43 vec1 32 con ssa_101 = fadd ssa_97, ssa_43 vec1 32 con ssa_101 = fadd ssa_97, ssa_43 vec1 32 div ssa_102 = fadd ssa_58.x, ssa_79 vec1 32 div ssa_102 = fadd ssa_58.x, ssa_79 vec1 32 div ssa_103 = fadd ssa_58.y, ssa_81 vec1 32 div ssa_103 = fadd ssa_58.y, ssa_81 vec1 32 div ssa_104 = fadd ssa_58.z, ssa_83 vec1 32 div ssa_104 = fadd ssa_58.z, ssa_83 vec1 32 div ssa_105 = fadd ssa_58.w, ssa_85 vec1 32 div ssa_105 = fadd ssa_58.w, ssa_85 vec1 32 div ssa_106 = fabs ssa_102 vec1 32 div ssa_106 = fabs ssa_102 vec1 32 div ssa_107 = fabs ssa_103 vec1 32 div ssa_107 = fabs ssa_103 vec1 32 div ssa_108 = fabs ssa_104 vec1 32 div ssa_108 = fabs ssa_104 vec1 32 div ssa_109 = fabs ssa_105 vec1 32 div ssa_109 = fabs ssa_105 vec1 32 div ssa_110 = flt32! ssa_109, ssa_101 vec1 32 div ssa_110 = flt32! ssa_109, ssa_101 vec1 32 div ssa_111 = flt32! ssa_108, ssa_100 vec1 32 div ssa_111 = flt32! ssa_108, ssa_100 vec1 32 div ssa_112 = iand ssa_110, ssa_111 vec1 32 div ssa_112 = iand ssa_110, ssa_111 vec1 32 div ssa_113 = flt32! ssa_107, ssa_99 vec1 32 div ssa_113 = flt32! ssa_107, ssa_99 vec1 32 div ssa_114 = iand ssa_112, ssa_113 vec1 32 div ssa_114 = iand ssa_112, ssa_113 vec1 32 div ssa_115 = flt32! ssa_106, ssa_98 vec1 32 div ssa_115 = flt32! ssa_106, ssa_98 vec1 32 div ssa_116 = iand ssa_114, ssa_115 vec1 32 div ssa_116 = iand ssa_114, ssa_115 vec1 32 con ssa_117 = load_const (0x3f800000 = 1.000000) vec1 32 con ssa_117 = load_const (0x3f800000 = 1.000000) /* succs: block_3 block_7 */ /* succs: block_3 block_7 */ if ssa_116 { if ssa_116 { block block_3: block block_3: /* preds: block_2 */ /* preds: block_2 */ vec1 32 con ssa_118 = intrinsic reduce (ssa_38) (reduction_op=iadd /*257*/, cluster_size=0) vec1 32 con ssa_118 = intrinsic reduce (ssa_38) (reduction_op=iadd /*257*/, cluster_size=0) vec1 32 div ssa_119 = intrinsic first_invocation () () vec1 32 div ssa_119 = intrinsic first_invocation () () vec1 32 div ssa_120 = intrinsic load_subgroup_invocation () () vec1 32 div ssa_120 = intrinsic load_subgroup_invocation () () vec1 32 div ssa_121 = ieq32 ssa_120, ssa_119 vec1 32 div ssa_121 = ieq32 ssa_120, ssa_119 /* succs: block_4 block_5 */ /* succs: block_4 block_5 */ if ssa_121 { if ssa_121 { block block_4: block block_4: /* preds: block_3 */ /* preds: block_3 */ vec1 32 div ssa_122 = intrinsic ssbo_atomic (ssa_18, ssa_8, ssa_118) (access=1, atomi vec1 32 div ssa_122 = intrinsic ssbo_atomic (ssa_18, ssa_8, ssa_118) (access=1, atomi /* succs: block_6 */ /* succs: block_6 */ } else { } else { block block_5: block block_5: /* preds: block_3 */ /* preds: block_3 */ /* succs: block_6 */ /* succs: block_6 */ } } block block_6: block block_6: /* preds: block_4 block_5 */ /* preds: block_4 block_5 */ div r1 = mov ssa_117 div r1 = mov ssa_117 div r0 = mov ssa_8 div r0 = mov ssa_8 /* succs: block_8 */ /* succs: block_8 */ } else { } else { block block_7: block block_7: /* preds: block_2 */ /* preds: block_2 */ div r1 = mov ssa_8 div r1 = mov ssa_8 div r0 = mov ssa_117 div r0 = mov ssa_117 /* succs: block_8 */ /* succs: block_8 */ } } block block_8: block block_8: /* preds: block_6 block_7 */ /* preds: block_6 block_7 */ vec4 32 div ssa_125 = vec4 r0, r1, ssa_8, ssa_117 vec4 32 div ssa_125 = vec4 r0, r1, ssa_8, ssa_117 vec4 32 div ssa_126 = vec4 ssa_45, ssa_46, ssa_8, ssa_7 vec4 32 div ssa_126 = vec4 ssa_45, ssa_46, ssa_8, ssa_7 intrinsic image_store (ssa_22, ssa_126, ssa_6, ssa_125, ssa_8) (image_dim=2D /*1*/, image_array=true intrinsic image_store (ssa_22, ssa_126, ssa_6, ssa_125, ssa_8) (image_dim=2D /*1*/, image_array=true vec4 32 div ssa_127 = (float32)txf ssa_57 (coord), ssa_8 (lod), 5 (texture) vec4 32 div ssa_127 = (float32)txf ssa_57 (coord), ssa_8 (lod), 5 (texture) vec1 32 con ssa_128 = load_const (0x00000030 = 0.000000) vec1 32 con ssa_128 = load_const (0x00000030 = 0.000000) vec4 32 con ssa_129 = intrinsic load_uniform (ssa_128) (base=0, range=120, dest_type=invalid /*256*/) vec4 32 con ssa_129 = intrinsic load_uniform (ssa_128) (base=0, range=120, dest_type=invalid /*256*/) vec1 32 con ssa_130 = load_const (0x00000040 = 0.000000) vec1 32 con ssa_130 = load_const (0x00000040 = 0.000000) vec4 32 con ssa_131 = intrinsic load_uniform (ssa_130) (base=0, range=120, dest_type=invalid /*256*/) vec4 32 con ssa_131 = intrinsic load_uniform (ssa_130) (base=0, range=120, dest_type=invalid /*256*/) vec1 32 con ssa_132 = fneg ssa_131.x vec1 32 con ssa_132 = fneg ssa_131.x vec1 32 div ssa_133 = fmul ssa_132, ssa_56 vec1 32 div ssa_133 = fmul ssa_132, ssa_56 vec1 32 con ssa_134 = fneg ssa_131.y vec1 32 con ssa_134 = fneg ssa_131.y vec1 32 div ssa_135 = fmul ssa_134, ssa_56 vec1 32 div ssa_135 = fmul ssa_134, ssa_56 vec1 32 con ssa_136 = fneg ssa_131.z vec1 32 con ssa_136 = fneg ssa_131.z vec1 32 div ssa_137 = fmul ssa_136, ssa_56 vec1 32 div ssa_137 = fmul ssa_136, ssa_56 vec1 32 con ssa_138 = fneg ssa_131.w vec1 32 con ssa_138 = fneg ssa_131.w vec1 32 div ssa_139 = fmul ssa_138, ssa_56 vec1 32 div ssa_139 = fmul ssa_138, ssa_56 vec1 32 con ssa_140 = fneg ssa_129.x vec1 32 con ssa_140 = fneg ssa_129.x vec1 32 div ssa_141 = ffma ssa_140, ssa_54, ssa_133 vec1 32 div ssa_141 = ffma ssa_140, ssa_54, ssa_133 vec1 32 con ssa_142 = fneg ssa_129.y vec1 32 con ssa_142 = fneg ssa_129.y vec1 32 div ssa_143 = ffma ssa_142, ssa_54, ssa_135 vec1 32 div ssa_143 = ffma ssa_142, ssa_54, ssa_135 vec1 32 con ssa_144 = fneg ssa_129.z vec1 32 con ssa_144 = fneg ssa_129.z vec1 32 div ssa_145 = ffma ssa_144, ssa_54, ssa_137 vec1 32 div ssa_145 = ffma ssa_144, ssa_54, ssa_137 vec1 32 con ssa_146 = fneg ssa_129.w vec1 32 con ssa_146 = fneg ssa_129.w vec1 32 div ssa_147 = ffma ssa_146, ssa_54, ssa_139 vec1 32 div ssa_147 = ffma ssa_146, ssa_54, ssa_139 vec1 32 con ssa_148 = load_const (0xbdc381f3 = -0.095463) vec1 32 con ssa_148 = load_const (0xbdc381f3 = -0.095463) vec1 32 div ssa_149 = ffma ssa_141, ssa_44, ssa_148 vec1 32 div ssa_149 = ffma ssa_141, ssa_44, ssa_148 vec1 32 con ssa_150 = load_const (0xbdc9c363 = -0.098517) vec1 32 con ssa_150 = load_const (0xbdc9c363 = -0.098517) vec1 32 div ssa_151 = ffma ssa_143, ssa_44, ssa_150 vec1 32 div ssa_151 = ffma ssa_143, ssa_44, ssa_150 vec1 32 con ssa_152 = load_const (0xbdc52221 = -0.096257) vec1 32 con ssa_152 = load_const (0xbdc52221 = -0.096257) vec1 32 div ssa_153 = ffma ssa_145, ssa_44, ssa_152 vec1 32 div ssa_153 = ffma ssa_145, ssa_44, ssa_152 vec1 32 con ssa_154 = load_const (0xbd9e4e34 = -0.077298) vec1 32 con ssa_154 = load_const (0xbd9e4e34 = -0.077298) vec1 32 div ssa_155 = ffma ssa_147, ssa_44, ssa_154 vec1 32 div ssa_155 = ffma ssa_147, ssa_44, ssa_154 vec1 32 con ssa_156 = fmul ssa_129.x, ssa_53 vec1 32 con ssa_156 = fmul ssa_129.x, ssa_53 vec1 32 con ssa_157 = fmul ssa_129.y, ssa_53 vec1 32 con ssa_157 = fmul ssa_129.y, ssa_53 vec1 32 con ssa_158 = fmul ssa_129.z, ssa_53 vec1 32 con ssa_158 = fmul ssa_129.z, ssa_53 vec1 32 con ssa_159 = fmul ssa_129.w, ssa_53 vec1 32 con ssa_159 = fmul ssa_129.w, ssa_53 vec1 32 con ssa_160 = fmul ssa_131.x, ssa_55 vec1 32 con ssa_160 = fmul ssa_131.x, ssa_55 vec1 32 con ssa_161 = fmul ssa_131.y, ssa_55 vec1 32 con ssa_161 = fmul ssa_131.y, ssa_55 vec1 32 con ssa_162 = fmul ssa_131.z, ssa_55 vec1 32 con ssa_162 = fmul ssa_131.z, ssa_55 vec1 32 con ssa_163 = fmul ssa_131.w, ssa_55 vec1 32 con ssa_163 = fmul ssa_131.w, ssa_55 vec1 32 con ssa_164 = fmax ssa_156, ssa_160 vec1 32 con ssa_164 = fmax ssa_156, ssa_160 vec1 32 con ssa_165 = fmax ssa_157, ssa_161 vec1 32 con ssa_165 = fmax ssa_157, ssa_161 vec1 32 con ssa_166 = fmax ssa_158, ssa_162 vec1 32 con ssa_166 = fmax ssa_158, ssa_162 vec1 32 con ssa_167 = fmax ssa_159, ssa_163 vec1 32 con ssa_167 = fmax ssa_159, ssa_163 vec1 32 con ssa_168 = fadd ssa_164, ssa_42 vec1 32 con ssa_168 = fadd ssa_164, ssa_42 vec1 32 con ssa_169 = fadd ssa_165, ssa_42 vec1 32 con ssa_169 = fadd ssa_165, ssa_42 vec1 32 con ssa_170 = fadd ssa_166, ssa_42 vec1 32 con ssa_170 = fadd ssa_166, ssa_42 vec1 32 con ssa_171 = fadd ssa_167, ssa_42 vec1 32 con ssa_171 = fadd ssa_167, ssa_42 vec1 32 div ssa_172 = fadd ssa_127.x, ssa_149 vec1 32 div ssa_172 = fadd ssa_127.x, ssa_149 vec1 32 div ssa_173 = fadd ssa_127.y, ssa_151 vec1 32 div ssa_173 = fadd ssa_127.y, ssa_151 vec1 32 div ssa_174 = fadd ssa_127.z, ssa_153 vec1 32 div ssa_174 = fadd ssa_127.z, ssa_153 vec1 32 div ssa_175 = fadd ssa_127.w, ssa_155 vec1 32 div ssa_175 = fadd ssa_127.w, ssa_155 vec1 32 div ssa_176 = fabs ssa_172 vec1 32 div ssa_176 = fabs ssa_172 vec1 32 div ssa_177 = fabs ssa_173 vec1 32 div ssa_177 = fabs ssa_173 vec1 32 div ssa_178 = fabs ssa_174 vec1 32 div ssa_178 = fabs ssa_174 vec1 32 div ssa_179 = fabs ssa_175 vec1 32 div ssa_179 = fabs ssa_175 vec1 32 div ssa_180 = flt32! ssa_179, ssa_171 vec1 32 div ssa_180 = flt32! ssa_179, ssa_171 vec1 32 div ssa_181 = flt32! ssa_178, ssa_170 vec1 32 div ssa_181 = flt32! ssa_178, ssa_170 vec1 32 div ssa_182 = iand ssa_180, ssa_181 vec1 32 div ssa_182 = iand ssa_180, ssa_181 vec1 32 div ssa_183 = flt32! ssa_177, ssa_169 vec1 32 div ssa_183 = flt32! ssa_177, ssa_169 vec1 32 div ssa_184 = iand ssa_182, ssa_183 vec1 32 div ssa_184 = iand ssa_182, ssa_183 vec1 32 div ssa_185 = flt32! ssa_176, ssa_168 vec1 32 div ssa_185 = flt32! ssa_176, ssa_168 vec1 32 div ssa_186 = iand ssa_184, ssa_185 vec1 32 div ssa_186 = iand ssa_184, ssa_185 /* succs: block_9 block_13 */ /* succs: block_9 block_13 */ if ssa_186 { if ssa_186 { block block_9: block block_9: /* preds: block_8 */ /* preds: block_8 */ vec1 32 con ssa_187 = intrinsic reduce (ssa_38) (reduction_op=iadd /*257*/, cluster_size=0) vec1 32 con ssa_187 = intrinsic reduce (ssa_38) (reduction_op=iadd /*257*/, cluster_size=0) vec1 32 div ssa_188 = intrinsic first_invocation () () vec1 32 div ssa_188 = intrinsic first_invocation () () vec1 32 div ssa_189 = intrinsic load_subgroup_invocation () () vec1 32 div ssa_189 = intrinsic load_subgroup_invocation () () vec1 32 div ssa_190 = ieq32 ssa_189, ssa_188 vec1 32 div ssa_190 = ieq32 ssa_189, ssa_188 /* succs: block_10 block_11 */ /* succs: block_10 block_11 */ if ssa_190 { if ssa_190 { block block_10: block block_10: /* preds: block_9 */ /* preds: block_9 */ vec1 32 div ssa_191 = intrinsic ssbo_atomic (ssa_18, ssa_14, ssa_187) (access=1, atom vec1 32 div ssa_191 = intrinsic ssbo_atomic (ssa_18, ssa_14, ssa_187) (access=1, atom /* succs: block_12 */ /* succs: block_12 */ } else { } else { block block_11: block block_11: /* preds: block_9 */ /* preds: block_9 */ /* succs: block_12 */ /* succs: block_12 */ } } block block_12: block block_12: /* preds: block_10 block_11 */ /* preds: block_10 block_11 */ div r3 = mov ssa_117 div r3 = mov ssa_117 div r2 = mov ssa_8 div r2 = mov ssa_8 /* succs: block_14 */ /* succs: block_14 */ } else { } else { block block_13: block block_13: /* preds: block_8 */ /* preds: block_8 */ div r3 = mov ssa_8 div r3 = mov ssa_8 div r2 = mov ssa_117 div r2 = mov ssa_117 /* succs: block_14 */ /* succs: block_14 */ } } block block_14: block block_14: /* preds: block_12 block_13 */ /* preds: block_12 block_13 */ vec4 32 div ssa_194 = vec4 r2, r3, ssa_8, ssa_117 vec4 32 div ssa_194 = vec4 r2, r3, ssa_8, ssa_117 vec4 32 div ssa_195 = vec4 ssa_45, ssa_46, ssa_38, ssa_5 vec4 32 div ssa_195 = vec4 ssa_45, ssa_46, ssa_38, ssa_5 intrinsic image_store (ssa_22, ssa_195, ssa_4, ssa_194, ssa_8) (image_dim=2D /*1*/, image_array=true intrinsic image_store (ssa_22, ssa_195, ssa_4, ssa_194, ssa_8) (image_dim=2D /*1*/, image_array=true vec4 32 div ssa_196 = (int32)txf ssa_57 (coord), ssa_8 (lod), 6 (texture) vec4 32 div ssa_196 = (int32)txf ssa_57 (coord), ssa_8 (lod), 6 (texture) vec1 32 con ssa_197 = load_const (0x00000050 = 0.000000) vec1 32 con ssa_197 = load_const (0x00000050 = 0.000000) vec4 32 con ssa_198 = intrinsic load_uniform (ssa_197) (base=0, range=120, dest_type=invalid /*256*/) vec4 32 con ssa_198 = intrinsic load_uniform (ssa_197) (base=0, range=120, dest_type=invalid /*256*/) vec1 32 con ssa_199 = i2f32 ssa_198.x vec1 32 con ssa_199 = i2f32 ssa_198.x vec1 32 con ssa_200 = i2f32 ssa_198.y vec1 32 con ssa_200 = i2f32 ssa_198.y vec1 32 con ssa_201 = i2f32 ssa_198.z vec1 32 con ssa_201 = i2f32 ssa_198.z vec1 32 con ssa_202 = i2f32 ssa_198.w vec1 32 con ssa_202 = i2f32 ssa_198.w vec1 32 div ssa_203 = fmul ssa_199, ssa_54 vec1 32 div ssa_203 = fmul ssa_199, ssa_54 vec1 32 div ssa_204 = fmul ssa_200, ssa_54 vec1 32 div ssa_204 = fmul ssa_200, ssa_54 vec1 32 div ssa_205 = fmul ssa_201, ssa_54 vec1 32 div ssa_205 = fmul ssa_201, ssa_54 vec1 32 div ssa_206 = fmul ssa_202, ssa_54 vec1 32 div ssa_206 = fmul ssa_202, ssa_54 vec1 32 div ssa_207 = f2i32 ssa_203 vec1 32 div ssa_207 = f2i32 ssa_203 vec1 32 div ssa_208 = f2i32 ssa_204 vec1 32 div ssa_208 = f2i32 ssa_204 vec1 32 div ssa_209 = f2i32 ssa_205 vec1 32 div ssa_209 = f2i32 ssa_205 vec1 32 div ssa_210 = f2i32 ssa_206 vec1 32 div ssa_210 = f2i32 ssa_206 vec1 32 div ssa_211 = iadd ssa_208, ssa_39 | vec1 32 con ssa_211 = load_const (0x00000060 = 0.000000) vec1 32 div ssa_212 = iadd ssa_209, ssa_40 | vec4 32 con ssa_212 = intrinsic load_uniform (ssa_211) (base=0, range=120, dest_type=invalid /*256*/) vec1 32 div ssa_213 = iadd ssa_210, ssa_41 | vec1 32 con ssa_213 = i2f32 ssa_212.x vec1 32 con ssa_214 = load_const (0x00000060 = 0.000000) | vec1 32 con ssa_214 = i2f32 ssa_212.y vec4 32 con ssa_215 = intrinsic load_uniform (ssa_214) (base=0, range=120, dest_type=invalid /*256*/) | vec1 32 con ssa_215 = i2f32 ssa_212.z vec1 32 con ssa_216 = i2f32 ssa_215.x | vec1 32 con ssa_216 = i2f32 ssa_212.w vec1 32 con ssa_217 = i2f32 ssa_215.y | vec1 32 div ssa_217 = fmul ssa_213, ssa_56 vec1 32 con ssa_218 = i2f32 ssa_215.z | vec1 32 div ssa_218 = fmul ssa_214, ssa_56 vec1 32 con ssa_219 = i2f32 ssa_215.w | vec1 32 div ssa_219 = fmul ssa_215, ssa_56 vec1 32 div ssa_220 = fmul ssa_216, ssa_56 vec1 32 div ssa_220 = fmul ssa_216, ssa_56 vec1 32 div ssa_221 = fmul ssa_217, ssa_56 | vec1 32 div ssa_221 = f2i32 ssa_217 vec1 32 div ssa_222 = fmul ssa_218, ssa_56 | vec1 32 div ssa_222 = f2i32 ssa_218 vec1 32 div ssa_223 = fmul ssa_219, ssa_56 | vec1 32 div ssa_223 = f2i32 ssa_219 vec1 32 div ssa_224 = f2i32 ssa_220 vec1 32 div ssa_224 = f2i32 ssa_220 vec1 32 div ssa_225 = f2i32 ssa_221 | vec1 32 con ssa_225 = iabs! ssa_198.x vec1 32 div ssa_226 = f2i32 ssa_222 | vec1 32 con ssa_226 = iabs! ssa_33.z vec1 32 div ssa_227 = f2i32 ssa_223 | vec1 32 con ssa_227 = ilt32! ssa_198.x, ssa_8 vec1 32 div ssa_228 = iadd ssa_225, ssa_39 | vec1 32 con ssa_228 = ilt32! ssa_33.z, ssa_8 vec1 32 div ssa_229 = iadd ssa_226, ssa_40 | vec1 32 con ssa_229 = ixor! ssa_227, ssa_228 vec1 32 div ssa_230 = iadd ssa_227, ssa_41 | vec1 32 con ssa_230 = u2f32! ssa_226 vec1 32 con ssa_231 = iabs! ssa_198.x | vec1 32 con ssa_231 = frcp! ssa_230 vec1 32 con ssa_232 = iabs! ssa_33.z | vec1 32 con ssa_232 = load_const (0x4f7ffffe = 4294966784.000000) vec1 32 con ssa_233 = ilt32! ssa_198.x, ssa_8 | vec1 32 con ssa_233 = fmul! ssa_231, ssa_232 vec1 32 con ssa_234 = ilt32! ssa_33.z, ssa_8 | vec1 32 con ssa_234 = f2u32! ssa_233 vec1 32 con ssa_235 = ixor! ssa_233, ssa_234 | vec1 32 con ssa_235 = ineg! ssa_226 vec1 32 con ssa_236 = u2f32! ssa_232 | vec1 32 con ssa_236 = imul! ssa_226, ssa_234 vec1 32 con ssa_237 = frcp! ssa_236 | vec1 32 con ssa_237 = ineg! ssa_236 vec1 32 con ssa_238 = load_const (0x4f7ffffe = 4294966784.000000) | vec1 32 con ssa_238 = umul_high! ssa_234, ssa_237 vec1 32 con ssa_239 = fmul! ssa_237, ssa_238 | vec1 32 con ssa_239 = iadd! ssa_234, ssa_238 vec1 32 con ssa_240 = f2u32! ssa_239 | vec1 32 con ssa_240 = umul_high! ssa_225, ssa_239 vec1 32 con ssa_241 = ineg! ssa_232 | vec1 32 con ssa_241 = imul! ssa_240, ssa_226 vec1 32 con ssa_242 = imul! ssa_232, ssa_240 | vec1 32 con ssa_242 = ineg! ssa_241 vec1 32 con ssa_243 = ineg! ssa_242 | vec1 32 con ssa_243 = iadd! ssa_225, ssa_242 vec1 32 con ssa_244 = umul_high! ssa_240, ssa_243 | vec1 32 con ssa_244 = iadd! ssa_240, ssa_38 vec1 32 con ssa_245 = iadd! ssa_240, ssa_244 | vec1 32 con ssa_245 = uge32! ssa_243, ssa_226 vec1 32 con ssa_246 = umul_high! ssa_231, ssa_245 | vec1 32 con ssa_246 = b32csel! ssa_245, ssa_244, ssa_240 vec1 32 con ssa_247 = imul! ssa_246, ssa_232 | vec1 32 con ssa_247 = iadd! ssa_243, ssa_235 vec1 32 con ssa_248 = ineg! ssa_247 | vec1 32 con ssa_248 = b32csel! ssa_245, ssa_247, ssa_243 vec1 32 con ssa_249 = iadd! ssa_231, ssa_248 | vec1 32 con ssa_249 = iadd! ssa_246, ssa_38 vec1 32 con ssa_250 = iadd! ssa_246, ssa_38 | vec1 32 con ssa_250 = uge32! ssa_248, ssa_226 vec1 32 con ssa_251 = uge32! ssa_249, ssa_232 | vec1 32 con ssa_251 = b32csel! ssa_250, ssa_249, ssa_246 vec1 32 con ssa_252 = b32csel! ssa_251, ssa_250, ssa_246 | vec1 32 con ssa_252 = ineg! ssa_251 vec1 32 con ssa_253 = iadd! ssa_249, ssa_241 | vec1 32 con ssa_253 = b32csel! ssa_229, ssa_252, ssa_251 vec1 32 con ssa_254 = b32csel! ssa_251, ssa_253, ssa_249 | vec1 32 con ssa_254 = iabs! ssa_198.y vec1 32 con ssa_255 = iadd! ssa_252, ssa_38 | vec1 32 con ssa_255 = ilt32! ssa_198.y, ssa_8 vec1 32 con ssa_256 = uge32! ssa_254, ssa_232 | vec1 32 con ssa_256 = ixor! ssa_255, ssa_228 vec1 32 con ssa_257 = b32csel! ssa_256, ssa_255, ssa_252 | vec1 32 con ssa_257 = umul_high! ssa_254, ssa_239 vec1 32 con ssa_258 = ineg! ssa_257 | vec1 32 con ssa_258 = imul! ssa_257, ssa_226 vec1 32 con ssa_259 = b32csel! ssa_235, ssa_258, ssa_257 | vec1 32 con ssa_259 = ineg! ssa_258 vec1 32 con ssa_260 = iabs! ssa_198.y | vec1 32 con ssa_260 = iadd! ssa_254, ssa_259 vec1 32 con ssa_261 = ilt32! ssa_198.y, ssa_8 | vec1 32 con ssa_261 = iadd! ssa_257, ssa_38 vec1 32 con ssa_262 = ixor! ssa_261, ssa_234 | vec1 32 con ssa_262 = uge32! ssa_260, ssa_226 vec1 32 con ssa_263 = umul_high! ssa_260, ssa_245 | vec1 32 con ssa_263 = b32csel! ssa_262, ssa_261, ssa_257 vec1 32 con ssa_264 = imul! ssa_263, ssa_232 | vec1 32 con ssa_264 = iadd! ssa_260, ssa_235 vec1 32 con ssa_265 = ineg! ssa_264 | vec1 32 con ssa_265 = b32csel! ssa_262, ssa_264, ssa_260 vec1 32 con ssa_266 = iadd! ssa_260, ssa_265 | vec1 32 con ssa_266 = iadd! ssa_263, ssa_38 vec1 32 con ssa_267 = iadd! ssa_263, ssa_38 | vec1 32 con ssa_267 = uge32! ssa_265, ssa_226 vec1 32 con ssa_268 = uge32! ssa_266, ssa_232 | vec1 32 con ssa_268 = b32csel! ssa_267, ssa_266, ssa_263 vec1 32 con ssa_269 = b32csel! ssa_268, ssa_267, ssa_263 | vec1 32 con ssa_269 = ineg! ssa_268 vec1 32 con ssa_270 = iadd! ssa_266, ssa_241 | vec1 32 con ssa_270 = b32csel! ssa_256, ssa_269, ssa_268 vec1 32 con ssa_271 = b32csel! ssa_268, ssa_270, ssa_266 | vec1 32 con ssa_271 = iabs! ssa_198.z vec1 32 con ssa_272 = iadd! ssa_269, ssa_38 | vec1 32 con ssa_272 = ilt32! ssa_198.z, ssa_8 vec1 32 con ssa_273 = uge32! ssa_271, ssa_232 | vec1 32 con ssa_273 = ixor! ssa_272, ssa_228 vec1 32 con ssa_274 = b32csel! ssa_273, ssa_272, ssa_269 | vec1 32 con ssa_274 = umul_high! ssa_271, ssa_239 vec1 32 con ssa_275 = ineg! ssa_274 | vec1 32 con ssa_275 = imul! ssa_274, ssa_226 vec1 32 con ssa_276 = b32csel! ssa_262, ssa_275, ssa_274 | vec1 32 con ssa_276 = ineg! ssa_275 vec1 32 con ssa_277 = iabs! ssa_198.z | vec1 32 con ssa_277 = iadd! ssa_271, ssa_276 vec1 32 con ssa_278 = ilt32! ssa_198.z, ssa_8 | vec1 32 con ssa_278 = iadd! ssa_274, ssa_38 vec1 32 con ssa_279 = ixor! ssa_278, ssa_234 | vec1 32 con ssa_279 = uge32! ssa_277, ssa_226 vec1 32 con ssa_280 = umul_high! ssa_277, ssa_245 | vec1 32 con ssa_280 = b32csel! ssa_279, ssa_278, ssa_274 vec1 32 con ssa_281 = imul! ssa_280, ssa_232 | vec1 32 con ssa_281 = iadd! ssa_277, ssa_235 vec1 32 con ssa_282 = ineg! ssa_281 | vec1 32 con ssa_282 = b32csel! ssa_279, ssa_281, ssa_277 vec1 32 con ssa_283 = iadd! ssa_277, ssa_282 | vec1 32 con ssa_283 = iadd! ssa_280, ssa_38 vec1 32 con ssa_284 = iadd! ssa_280, ssa_38 | vec1 32 con ssa_284 = uge32! ssa_282, ssa_226 vec1 32 con ssa_285 = uge32! ssa_283, ssa_232 | vec1 32 con ssa_285 = b32csel! ssa_284, ssa_283, ssa_280 vec1 32 con ssa_286 = b32csel! ssa_285, ssa_284, ssa_280 | vec1 32 con ssa_286 = ineg! ssa_285 vec1 32 con ssa_287 = iadd! ssa_283, ssa_241 | vec1 32 con ssa_287 = b32csel! ssa_273, ssa_286, ssa_285 vec1 32 con ssa_288 = b32csel! ssa_285, ssa_287, ssa_283 | vec1 32 con ssa_288 = iabs! ssa_198.w vec1 32 con ssa_289 = iadd! ssa_286, ssa_38 | vec1 32 con ssa_289 = ilt32! ssa_198.w, ssa_8 vec1 32 con ssa_290 = uge32! ssa_288, ssa_232 | vec1 32 con ssa_290 = ixor! ssa_289, ssa_228 vec1 32 con ssa_291 = b32csel! ssa_290, ssa_289, ssa_286 | vec1 32 con ssa_291 = umul_high! ssa_288, ssa_239 vec1 32 con ssa_292 = ineg! ssa_291 | vec1 32 con ssa_292 = imul! ssa_291, ssa_226 vec1 32 con ssa_293 = b32csel! ssa_279, ssa_292, ssa_291 | vec1 32 con ssa_293 = ineg! ssa_292 vec1 32 con ssa_294 = iabs! ssa_198.w | vec1 32 con ssa_294 = iadd! ssa_288, ssa_293 vec1 32 con ssa_295 = ilt32! ssa_198.w, ssa_8 | vec1 32 con ssa_295 = iadd! ssa_291, ssa_38 vec1 32 con ssa_296 = ixor! ssa_295, ssa_234 | vec1 32 con ssa_296 = uge32! ssa_294, ssa_226 vec1 32 con ssa_297 = umul_high! ssa_294, ssa_245 | vec1 32 con ssa_297 = b32csel! ssa_296, ssa_295, ssa_291 vec1 32 con ssa_298 = imul! ssa_297, ssa_232 | vec1 32 con ssa_298 = iadd! ssa_294, ssa_235 vec1 32 con ssa_299 = ineg! ssa_298 | vec1 32 con ssa_299 = b32csel! ssa_296, ssa_298, ssa_294 vec1 32 con ssa_300 = iadd! ssa_294, ssa_299 | vec1 32 con ssa_300 = iadd! ssa_297, ssa_38 vec1 32 con ssa_301 = iadd! ssa_297, ssa_38 | vec1 32 con ssa_301 = uge32! ssa_299, ssa_226 vec1 32 con ssa_302 = uge32! ssa_300, ssa_232 | vec1 32 con ssa_302 = b32csel! ssa_301, ssa_300, ssa_297 vec1 32 con ssa_303 = b32csel! ssa_302, ssa_301, ssa_297 | vec1 32 con ssa_303 = ineg! ssa_302 vec1 32 con ssa_304 = iadd! ssa_300, ssa_241 | vec1 32 con ssa_304 = b32csel! ssa_290, ssa_303, ssa_302 vec1 32 con ssa_305 = b32csel! ssa_302, ssa_304, ssa_300 | vec1 32 con ssa_305 = iabs! ssa_212.x vec1 32 con ssa_306 = iadd! ssa_303, ssa_38 | vec1 32 con ssa_306 = iabs! ssa_33.w vec1 32 con ssa_307 = uge32! ssa_305, ssa_232 | vec1 32 con ssa_307 = ilt32! ssa_212.x, ssa_8 vec1 32 con ssa_308 = b32csel! ssa_307, ssa_306, ssa_303 | vec1 32 con ssa_308 = ilt32! ssa_33.w, ssa_8 vec1 32 con ssa_309 = ineg! ssa_308 | vec1 32 con ssa_309 = ixor! ssa_307, ssa_308 vec1 32 con ssa_310 = b32csel! ssa_296, ssa_309, ssa_308 | vec1 32 con ssa_310 = u2f32! ssa_306 vec1 32 con ssa_311 = iabs! ssa_215.x | vec1 32 con ssa_311 = frcp! ssa_310 vec1 32 con ssa_312 = iabs! ssa_33.w | vec1 32 con ssa_312 = fmul! ssa_311, ssa_232 vec1 32 con ssa_313 = ilt32! ssa_215.x, ssa_8 | vec1 32 con ssa_313 = f2u32! ssa_312 vec1 32 con ssa_314 = ilt32! ssa_33.w, ssa_8 | vec1 32 con ssa_314 = ineg! ssa_306 vec1 32 con ssa_315 = ixor! ssa_313, ssa_314 | vec1 32 con ssa_315 = imul! ssa_306, ssa_313 vec1 32 con ssa_316 = u2f32! ssa_312 | vec1 32 con ssa_316 = ineg! ssa_315 vec1 32 con ssa_317 = frcp! ssa_316 | vec1 32 con ssa_317 = umul_high! ssa_313, ssa_316 vec1 32 con ssa_318 = fmul! ssa_317, ssa_238 | vec1 32 con ssa_318 = iadd! ssa_313, ssa_317 vec1 32 con ssa_319 = f2u32! ssa_318 | vec1 32 con ssa_319 = umul_high! ssa_305, ssa_318 vec1 32 con ssa_320 = ineg! ssa_312 | vec1 32 con ssa_320 = imul! ssa_319, ssa_306 vec1 32 con ssa_321 = imul! ssa_312, ssa_319 | vec1 32 con ssa_321 = ineg! ssa_320 vec1 32 con ssa_322 = ineg! ssa_321 | vec1 32 con ssa_322 = iadd! ssa_305, ssa_321 vec1 32 con ssa_323 = umul_high! ssa_319, ssa_322 | vec1 32 con ssa_323 = iadd! ssa_319, ssa_38 vec1 32 con ssa_324 = iadd! ssa_319, ssa_323 | vec1 32 con ssa_324 = uge32! ssa_322, ssa_306 vec1 32 con ssa_325 = umul_high! ssa_311, ssa_324 | vec1 32 con ssa_325 = b32csel! ssa_324, ssa_323, ssa_319 vec1 32 con ssa_326 = imul! ssa_325, ssa_312 | vec1 32 con ssa_326 = iadd! ssa_322, ssa_314 vec1 32 con ssa_327 = ineg! ssa_326 | vec1 32 con ssa_327 = b32csel! ssa_324, ssa_326, ssa_322 vec1 32 con ssa_328 = iadd! ssa_311, ssa_327 | vec1 32 con ssa_328 = iadd! ssa_325, ssa_38 vec1 32 con ssa_329 = iadd! ssa_325, ssa_38 | vec1 32 con ssa_329 = uge32! ssa_327, ssa_306 vec1 32 con ssa_330 = uge32! ssa_328, ssa_312 | vec1 32 con ssa_330 = b32csel! ssa_329, ssa_328, ssa_325 vec1 32 con ssa_331 = b32csel! ssa_330, ssa_329, ssa_325 | vec1 32 con ssa_331 = ineg! ssa_330 vec1 32 con ssa_332 = iadd! ssa_328, ssa_320 | vec1 32 con ssa_332 = b32csel! ssa_309, ssa_331, ssa_330 vec1 32 con ssa_333 = b32csel! ssa_330, ssa_332, ssa_328 | vec1 32 con ssa_333 = iabs! ssa_212.y vec1 32 con ssa_334 = iadd! ssa_331, ssa_38 | vec1 32 con ssa_334 = ilt32! ssa_212.y, ssa_8 vec1 32 con ssa_335 = uge32! ssa_333, ssa_312 | vec1 32 con ssa_335 = ixor! ssa_334, ssa_308 vec1 32 con ssa_336 = b32csel! ssa_335, ssa_334, ssa_331 | vec1 32 con ssa_336 = umul_high! ssa_333, ssa_318 vec1 32 con ssa_337 = ineg! ssa_336 | vec1 32 con ssa_337 = imul! ssa_336, ssa_306 vec1 32 con ssa_338 = b32csel! ssa_315, ssa_337, ssa_336 | vec1 32 con ssa_338 = ineg! ssa_337 vec1 32 con ssa_339 = iabs! ssa_215.y | vec1 32 con ssa_339 = iadd! ssa_333, ssa_338 vec1 32 con ssa_340 = ilt32! ssa_215.y, ssa_8 | vec1 32 con ssa_340 = iadd! ssa_336, ssa_38 vec1 32 con ssa_341 = ixor! ssa_340, ssa_314 | vec1 32 con ssa_341 = uge32! ssa_339, ssa_306 vec1 32 con ssa_342 = umul_high! ssa_339, ssa_324 | vec1 32 con ssa_342 = b32csel! ssa_341, ssa_340, ssa_336 vec1 32 con ssa_343 = imul! ssa_342, ssa_312 | vec1 32 con ssa_343 = iadd! ssa_339, ssa_314 vec1 32 con ssa_344 = ineg! ssa_343 | vec1 32 con ssa_344 = b32csel! ssa_341, ssa_343, ssa_339 vec1 32 con ssa_345 = iadd! ssa_339, ssa_344 | vec1 32 con ssa_345 = iadd! ssa_342, ssa_38 vec1 32 con ssa_346 = iadd! ssa_342, ssa_38 | vec1 32 con ssa_346 = uge32! ssa_344, ssa_306 vec1 32 con ssa_347 = uge32! ssa_345, ssa_312 | vec1 32 con ssa_347 = b32csel! ssa_346, ssa_345, ssa_342 vec1 32 con ssa_348 = b32csel! ssa_347, ssa_346, ssa_342 | vec1 32 con ssa_348 = ineg! ssa_347 vec1 32 con ssa_349 = iadd! ssa_345, ssa_320 | vec1 32 con ssa_349 = b32csel! ssa_335, ssa_348, ssa_347 vec1 32 con ssa_350 = b32csel! ssa_347, ssa_349, ssa_345 | vec1 32 con ssa_350 = iabs! ssa_212.z vec1 32 con ssa_351 = iadd! ssa_348, ssa_38 | vec1 32 con ssa_351 = ilt32! ssa_212.z, ssa_8 vec1 32 con ssa_352 = uge32! ssa_350, ssa_312 | vec1 32 con ssa_352 = ixor! ssa_351, ssa_308 vec1 32 con ssa_353 = b32csel! ssa_352, ssa_351, ssa_348 | vec1 32 con ssa_353 = umul_high! ssa_350, ssa_318 vec1 32 con ssa_354 = ineg! ssa_353 | vec1 32 con ssa_354 = imul! ssa_353, ssa_306 vec1 32 con ssa_355 = b32csel! ssa_341, ssa_354, ssa_353 | vec1 32 con ssa_355 = ineg! ssa_354 vec1 32 con ssa_356 = iabs! ssa_215.z | vec1 32 con ssa_356 = iadd! ssa_350, ssa_355 vec1 32 con ssa_357 = ilt32! ssa_215.z, ssa_8 | vec1 32 con ssa_357 = iadd! ssa_353, ssa_38 vec1 32 con ssa_358 = ixor! ssa_357, ssa_314 | vec1 32 con ssa_358 = uge32! ssa_356, ssa_306 vec1 32 con ssa_359 = umul_high! ssa_356, ssa_324 | vec1 32 con ssa_359 = b32csel! ssa_358, ssa_357, ssa_353 vec1 32 con ssa_360 = imul! ssa_359, ssa_312 | vec1 32 con ssa_360 = iadd! ssa_356, ssa_314 vec1 32 con ssa_361 = ineg! ssa_360 | vec1 32 con ssa_361 = b32csel! ssa_358, ssa_360, ssa_356 vec1 32 con ssa_362 = iadd! ssa_356, ssa_361 | vec1 32 con ssa_362 = iadd! ssa_359, ssa_38 vec1 32 con ssa_363 = iadd! ssa_359, ssa_38 | vec1 32 con ssa_363 = uge32! ssa_361, ssa_306 vec1 32 con ssa_364 = uge32! ssa_362, ssa_312 | vec1 32 con ssa_364 = b32csel! ssa_363, ssa_362, ssa_359 vec1 32 con ssa_365 = b32csel! ssa_364, ssa_363, ssa_359 | vec1 32 con ssa_365 = ineg! ssa_364 vec1 32 con ssa_366 = iadd! ssa_362, ssa_320 | vec1 32 con ssa_366 = b32csel! ssa_352, ssa_365, ssa_364 vec1 32 con ssa_367 = b32csel! ssa_364, ssa_366, ssa_362 | vec1 32 con ssa_367 = iabs! ssa_212.w vec1 32 con ssa_368 = iadd! ssa_365, ssa_38 | vec1 32 con ssa_368 = ilt32! ssa_212.w, ssa_8 vec1 32 con ssa_369 = uge32! ssa_367, ssa_312 | vec1 32 con ssa_369 = ixor! ssa_368, ssa_308 vec1 32 con ssa_370 = b32csel! ssa_369, ssa_368, ssa_365 | vec1 32 con ssa_370 = umul_high! ssa_367, ssa_318 vec1 32 con ssa_371 = ineg! ssa_370 | vec1 32 con ssa_371 = imul! ssa_370, ssa_306 vec1 32 con ssa_372 = b32csel! ssa_358, ssa_371, ssa_370 | vec1 32 con ssa_372 = ineg! ssa_371 vec1 32 con ssa_373 = iabs! ssa_215.w | vec1 32 con ssa_373 = iadd! ssa_367, ssa_372 vec1 32 con ssa_374 = ilt32! ssa_215.w, ssa_8 | vec1 32 con ssa_374 = iadd! ssa_370, ssa_38 vec1 32 con ssa_375 = ixor! ssa_374, ssa_314 | vec1 32 con ssa_375 = uge32! ssa_373, ssa_306 vec1 32 con ssa_376 = umul_high! ssa_373, ssa_324 | vec1 32 con ssa_376 = b32csel! ssa_375, ssa_374, ssa_370 vec1 32 con ssa_377 = imul! ssa_376, ssa_312 | vec1 32 con ssa_377 = iadd! ssa_373, ssa_314 vec1 32 con ssa_378 = ineg! ssa_377 | vec1 32 con ssa_378 = b32csel! ssa_375, ssa_377, ssa_373 vec1 32 con ssa_379 = iadd! ssa_373, ssa_378 | vec1 32 con ssa_379 = iadd! ssa_376, ssa_38 vec1 32 con ssa_380 = iadd! ssa_376, ssa_38 | vec1 32 con ssa_380 = uge32! ssa_378, ssa_306 vec1 32 con ssa_381 = uge32! ssa_379, ssa_312 | vec1 32 con ssa_381 = b32csel! ssa_380, ssa_379, ssa_376 vec1 32 con ssa_382 = b32csel! ssa_381, ssa_380, ssa_376 | vec1 32 con ssa_382 = ineg! ssa_381 vec1 32 con ssa_383 = iadd! ssa_379, ssa_320 | vec1 32 con ssa_383 = b32csel! ssa_369, ssa_382, ssa_381 vec1 32 con ssa_384 = b32csel! ssa_381, ssa_383, ssa_379 | vec1 32 div ssa_384 = ineg ssa_207 vec1 32 con ssa_385 = iadd! ssa_382, ssa_38 | vec1 32 div ssa_385 = iadd ssa_196.x, ssa_384 vec1 32 con ssa_386 = uge32! ssa_384, ssa_312 | vec1 32 div ssa_386 = iadd3 ssa_39, ssa_208, ssa_196.y vec1 32 con ssa_387 = b32csel! ssa_386, ssa_385, ssa_382 | vec1 32 div ssa_387 = iadd3 ssa_40, ssa_209, ssa_196.z vec1 32 con ssa_388 = ineg! ssa_387 | vec1 32 div ssa_388 = iadd3 ssa_41, ssa_210, ssa_196.w vec1 32 con ssa_389 = b32csel! ssa_375, ssa_388, ssa_387 | vec1 32 div ssa_389 = iabs ssa_385 vec1 32 div ssa_390 = ineg ssa_207 | vec1 32 div ssa_390 = iabs ssa_386 vec1 32 div ssa_391 = iadd ssa_196.x, ssa_390 | vec1 32 div ssa_391 = iabs ssa_387 vec1 32 div ssa_392 = ineg ssa_211 | vec1 32 div ssa_392 = iabs ssa_388 vec1 32 div ssa_393 = iadd ssa_196.y, ssa_392 | vec1 32 div ssa_393 = ineg ssa_221 vec1 32 div ssa_394 = ineg ssa_212 | vec1 32 div ssa_394 = iadd ssa_196.x, ssa_393 vec1 32 div ssa_395 = iadd ssa_196.z, ssa_394 | vec1 32 div ssa_395 = iadd3 ssa_39, ssa_222, ssa_196.y vec1 32 div ssa_396 = ineg ssa_213 | vec1 32 div ssa_396 = iadd3 ssa_40, ssa_223, ssa_196.z vec1 32 div ssa_397 = iadd ssa_196.w, ssa_396 | vec1 32 div ssa_397 = iadd3 ssa_41, ssa_224, ssa_196.w vec1 32 div ssa_398 = iabs ssa_391 | vec1 32 div ssa_398 = iabs ssa_394 vec1 32 div ssa_399 = iabs ssa_393 | vec1 32 div ssa_399 = iabs ssa_395 vec1 32 div ssa_400 = iabs ssa_395 | vec1 32 div ssa_400 = iabs ssa_396 vec1 32 div ssa_401 = iabs ssa_397 vec1 32 div ssa_401 = iabs ssa_397 vec1 32 div ssa_402 = ineg ssa_224 | vec1 32 div ssa_402 = ige32 ssa_332, ssa_398 vec1 32 div ssa_403 = iadd ssa_196.x, ssa_402 | vec1 32 div ssa_403 = ige32 ssa_253, ssa_389 vec1 32 div ssa_404 = ineg ssa_228 | vec1 32 div ssa_404 = ior ssa_403, ssa_402 vec1 32 div ssa_405 = iadd ssa_196.y, ssa_404 | vec1 32 div ssa_405 = ige32 ssa_270, ssa_390 vec1 32 div ssa_406 = ineg ssa_229 | vec1 32 div ssa_406 = ige32 ssa_349, ssa_399 vec1 32 div ssa_407 = iadd ssa_196.z, ssa_406 | vec1 32 div ssa_407 = ior ssa_405, ssa_406 vec1 32 div ssa_408 = ineg ssa_230 | vec1 32 div ssa_408 = ige32 ssa_287, ssa_391 vec1 32 div ssa_409 = iadd ssa_196.w, ssa_408 | vec1 32 div ssa_409 = ige32 ssa_366, ssa_400 vec1 32 div ssa_410 = iabs ssa_403 | vec1 32 div ssa_410 = ior ssa_408, ssa_409 vec1 32 div ssa_411 = iabs ssa_405 | vec1 32 div ssa_411 = ige32 ssa_304, ssa_392 vec1 32 div ssa_412 = iabs ssa_407 | vec1 32 div ssa_412 = ige32 ssa_383, ssa_401 vec1 32 div ssa_413 = iabs ssa_409 | vec1 32 div ssa_413 = ior ssa_411, ssa_412 vec1 32 div ssa_414 = ige32 ssa_338, ssa_410 | vec1 32 div ssa_414 = iand ssa_413, ssa_410 vec1 32 div ssa_415 = ige32 ssa_259, ssa_398 | vec1 32 div ssa_415 = iand ssa_414, ssa_407 vec1 32 div ssa_416 = ior ssa_415, ssa_414 | vec1 32 div ssa_416 = iand ssa_415, ssa_404 vec1 32 div ssa_417 = ige32 ssa_276, ssa_399 < vec1 32 div ssa_418 = ige32 ssa_355, ssa_411 < vec1 32 div ssa_419 = ior ssa_417, ssa_418 < vec1 32 div ssa_420 = ige32 ssa_293, ssa_400 < vec1 32 div ssa_421 = ige32 ssa_372, ssa_412 < vec1 32 div ssa_422 = ior ssa_420, ssa_421 < vec1 32 div ssa_423 = ige32 ssa_310, ssa_401 < vec1 32 div ssa_424 = ige32 ssa_389, ssa_413 < vec1 32 div ssa_425 = ior ssa_423, ssa_424 < vec1 32 div ssa_426 = iand ssa_425, ssa_422 < vec1 32 div ssa_427 = iand ssa_426, ssa_419 < vec1 32 div ssa_428 = iand ssa_427, ssa_416 < /* succs: block_15 block_19 */ /* succs: block_15 block_19 */ if ssa_428 { | if ssa_416 { block block_15: block block_15: /* preds: block_14 */ /* preds: block_14 */ vec1 32 con ssa_429 = load_const (0x00000008 = 0.000000) | vec1 32 con ssa_417 = load_const (0x00000008 = 0.000000) vec1 32 con ssa_430 = intrinsic reduce (ssa_38) (reduction_op=iadd /*257*/, cluster_size=0) | vec1 32 con ssa_418 = intrinsic reduce (ssa_38) (reduction_op=iadd /*257*/, cluster_size=0) vec1 32 div ssa_431 = intrinsic first_invocation () () | vec1 32 div ssa_419 = intrinsic first_invocation () () vec1 32 div ssa_432 = intrinsic load_subgroup_invocation () () | vec1 32 div ssa_420 = intrinsic load_subgroup_invocation () () vec1 32 div ssa_433 = ieq32 ssa_432, ssa_431 | vec1 32 div ssa_421 = ieq32 ssa_420, ssa_419 /* succs: block_16 block_17 */ /* succs: block_16 block_17 */ if ssa_433 { | if ssa_421 { block block_16: block block_16: /* preds: block_15 */ /* preds: block_15 */ vec1 32 div ssa_434 = intrinsic ssbo_atomic (ssa_18, ssa_429, ssa_430) (access=1, ato | vec1 32 div ssa_422 = intrinsic ssbo_atomic (ssa_18, ssa_417, ssa_418) (access=1, ato /* succs: block_18 */ /* succs: block_18 */ } else { } else { block block_17: block block_17: /* preds: block_15 */ /* preds: block_15 */ /* succs: block_18 */ /* succs: block_18 */ } } block block_18: block block_18: /* preds: block_16 block_17 */ /* preds: block_16 block_17 */ div r5 = mov ssa_117 div r5 = mov ssa_117 div r4 = mov ssa_8 div r4 = mov ssa_8 /* succs: block_20 */ /* succs: block_20 */ } else { } else { block block_19: block block_19: /* preds: block_14 */ /* preds: block_14 */ div r5 = mov ssa_8 div r5 = mov ssa_8 div r4 = mov ssa_117 div r4 = mov ssa_117 /* succs: block_20 */ /* succs: block_20 */ } } block block_20: block block_20: /* preds: block_18 block_19 */ /* preds: block_18 block_19 */ vec4 32 div ssa_437 = vec4 r4, r5, ssa_8, ssa_117 | vec4 32 div ssa_425 = vec4 r4, r5, ssa_8, ssa_117 vec4 32 div ssa_438 = vec4 ssa_45, ssa_46, ssa_18, ssa_3 | vec4 32 div ssa_426 = vec4 ssa_45, ssa_46, ssa_18, ssa_3 intrinsic image_store (ssa_22, ssa_438, ssa_2, ssa_437, ssa_8) (image_dim=2D /*1*/, image_array=true | intrinsic image_store (ssa_22, ssa_426, ssa_2, ssa_425, ssa_8) (image_dim=2D /*1*/, image_array=true vec4 32 div ssa_439 = (uint32)txf ssa_57 (coord), ssa_8 (lod), 7 (texture) | vec4 32 div ssa_427 = (uint32)txf ssa_57 (coord), ssa_8 (lod), 7 (texture) vec1 32 con ssa_440 = load_const (0x00000074 = 0.000000) | vec1 32 con ssa_428 = load_const (0x00000074 = 0.000000) vec1 32 con ssa_441 = intrinsic load_uniform (ssa_440) (base=0, range=120, dest_type=invalid /*256*/) | vec1 32 con ssa_429 = intrinsic load_uniform (ssa_428) (base=0, range=120, dest_type=invalid /*256*/) vec1 32 con ssa_442 = ineg ssa_441 | vec1 32 con ssa_430 = ineg ssa_429 vec1 32 div ssa_443 = iadd ssa_439.x, ssa_442 | vec1 32 div ssa_431 = iadd ssa_427.x, ssa_430 vec1 32 div ssa_444 = uge32! ssa_8, ssa_443 | vec1 32 div ssa_432 = uge32! ssa_8, ssa_431 /* succs: block_21 block_25 */ /* succs: block_21 block_25 */ if ssa_444 { | if ssa_432 { block block_21: block block_21: /* preds: block_20 */ /* preds: block_20 */ vec1 32 con ssa_445 = intrinsic reduce (ssa_38) (reduction_op=iadd /*257*/, cluster_size=0) | vec1 32 con ssa_433 = intrinsic reduce (ssa_38) (reduction_op=iadd /*257*/, cluster_size=0) vec1 32 div ssa_446 = intrinsic first_invocation () () | vec1 32 div ssa_434 = intrinsic first_invocation () () vec1 32 div ssa_447 = intrinsic load_subgroup_invocation () () | vec1 32 div ssa_435 = intrinsic load_subgroup_invocation () () vec1 32 div ssa_448 = ieq32 ssa_447, ssa_446 | vec1 32 div ssa_436 = ieq32 ssa_435, ssa_434 /* succs: block_22 block_23 */ /* succs: block_22 block_23 */ if ssa_448 { | if ssa_436 { block block_22: block block_22: /* preds: block_21 */ /* preds: block_21 */ vec1 32 div ssa_449 = intrinsic ssbo_atomic (ssa_18, ssa_37, ssa_445) (access=1, atom | vec1 32 div ssa_437 = intrinsic ssbo_atomic (ssa_18, ssa_37, ssa_433) (access=1, atom /* succs: block_24 */ /* succs: block_24 */ } else { } else { block block_23: block block_23: /* preds: block_21 */ /* preds: block_21 */ /* succs: block_24 */ /* succs: block_24 */ } } block block_24: block block_24: /* preds: block_22 block_23 */ /* preds: block_22 block_23 */ div r7 = mov ssa_117 div r7 = mov ssa_117 div r6 = mov ssa_8 div r6 = mov ssa_8 /* succs: block_26 */ /* succs: block_26 */ } else { } else { block block_25: block block_25: /* preds: block_20 */ /* preds: block_20 */ div r7 = mov ssa_8 div r7 = mov ssa_8 div r6 = mov ssa_117 div r6 = mov ssa_117 /* succs: block_26 */ /* succs: block_26 */ } } block block_26: block block_26: /* preds: block_24 block_25 */ /* preds: block_24 block_25 */ vec4 32 div ssa_452 = vec4 r6, r7, ssa_8, ssa_117 | vec4 32 div ssa_440 = vec4 r6, r7, ssa_8, ssa_117 vec4 32 div ssa_453 = vec4 ssa_45, ssa_46, ssa_14, ssa_1 | vec4 32 div ssa_441 = vec4 ssa_45, ssa_46, ssa_14, ssa_1 intrinsic image_store (ssa_22, ssa_453, ssa_0, ssa_452, ssa_8) (image_dim=2D /*1*/, image_array=true | intrinsic image_store (ssa_22, ssa_441, ssa_0, ssa_440, ssa_8) (image_dim=2D /*1*/, image_array=true /* succs: block_27 */ /* succs: block_27 */ } } block block_27: block block_27: /* preds: block_1 block_26 */ /* preds: block_1 block_26 */ /* succs: block_28 */ /* succs: block_28 */ block block_28: block block_28: } } Native code for unnamed compute shader (null) (sha1 f06ea6d3fb1c8c52120f7bc98b3801810f7fa7a5) | Native code for unnamed compute shader (null) (sha1 ba06dfb1f61cbff99ddbbbd2167dadbf02049b0c) SIMD16 shader: 638 instructions. 0 loops. 9272 cycles. 0:0 spills:fills, 20 sends, scheduled with mode top-down. Prom | SIMD16 shader: 629 instructions. 0 loops. 9288 cycles. 0:0 spills:fills, 20 sends, scheduled with mode top-down. Prom START B0 (278 cycles) | START B0 (326 cycles) and(1) g101<1>UD g0<0,1,0>UD 0xffffffc0UD { align1 WE_all 1N }; | and(1) g117<1>UD g0<0,1,0>UD 0xffffffc0UD { align1 WE_all 1N }; mov(16) g114<1>UD g0.1<0,1,0>UD { align1 1H }; | mov(16) g20<1>UD g0.1<0,1,0>UD { align1 1H }; mov(16) g116<1>UD g0.6<0,1,0>UD { align1 1H }; | mov(16) g22<1>UD g0.6<0,1,0>UD { align1 1H }; and(16) g79<1>UD g0.2<0,1,0>UD 0x000000ffUD { align1 1H compacted }; | and(16) g126<1>UD g0.2<0,1,0>UD 0x000000ffUD { align1 1H compacted }; add(1) g102<1>UD g101<0,1,0>UD 0x00000000UD { align1 WE_all 1N I@4 compacted }; | add(1) g118<1>UD g117<0,1,0>UD 0x00000000UD { align1 WE_all 1N I@4 compacted }; add(1) g103<1>UD g101<0,1,0>UD 0x00000100UD { align1 WE_all 1N compacted }; | add(1) g119<1>UD g117<0,1,0>UD 0x00000100UD { align1 WE_all 1N compacted }; add(1) g104<1>UD g101<0,1,0>UD 0x00000200UD { align1 WE_all 1N compacted }; | add(1) g120<1>UD g117<0,1,0>UD 0x00000200UD { align1 WE_all 1N compacted }; mov(8) g89<1>UW 0x76543210V { align1 WE_all 1Q }; | mov(8) g95<1>UW 0x76543210V { align1 WE_all 1Q }; shl(16) g81<1>D g79<8,8,1>D 0x00000004UD { align1 1H I@5 }; < sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@5 }; < send(1) g1UD g102UD nullUD 0x0280f500 0x00000000 < ugm MsgDesc: ( load, a32, d32, V64, transpose, L1STATE_L3MOCS dst_len = 8, src0_len = 1, < sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@4 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@4 }; send(1) g9UD g103UD nullUD 0x0280f500 0x00000000 | send(1) g1UD g118UD nullUD 0x0280f500 0x00000000 ugm MsgDesc: ( load, a32, d32, V64, transpose, L1STATE_L3MOCS dst_len = 8, src0_len = 1, | ugm MsgDesc: ( load, a32, d32, V64, transpose, L1STATE_L3MOCS dst_len = 8, src0_len = 1, sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@3 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@3 }; send(1) g17UD g104UD nullUD 0x0210c500 0x00000000 | send(1) g9UD g119UD nullUD 0x0280f500 0x00000000 > ugm MsgDesc: ( load, a32, d32, V64, transpose, L1STATE_L3MOCS dst_len = 8, src0_len = 1, > sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@2 }; > send(1) g17UD g120UD nullUD 0x0210c500 0x00000000 ugm MsgDesc: ( load, a32, d32, V8, transpose, L1STATE_L3MOCS dst_len = 1, src0_len = 1, s ugm MsgDesc: ( load, a32, d32, V8, transpose, L1STATE_L3MOCS dst_len = 1, src0_len = 1, s add(8) g89.8<1>UW g89<1,1,0>UW 0x0008UW { align1 WE_all 1Q I@2 compacted }; | add(8) g95.8<1>UW g95<1,1,0>UW 0x0008UW { align1 WE_all 1Q I@1 compacted }; > sync nop(1) null<0,1,0>UB { align1 WE_all 1N $0.dst }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@1 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@1 }; mov(16) g83<1>D g89<8,8,1>UW { align1 1H }; | mov(16) g7<1>D g95<8,8,1>UW { align1 1H }; add(16) g85<1>D g83<1,1,0>D g81<1,1,0>D { align1 1H I@1 compacted }; | sync nop(1) null<0,1,0>UB { align1 WE_all 1N $0.dst }; shr(16) g87<1>UD g85<1,1,0>UD 0x00000002UD { align1 1H I@1 compacted }; | shl(16) g5<1>D g126<8,8,1>D 0x00000004UD { align1 1H I@7 }; shr(16) g92<1>UD g85<1,1,0>UD 0x00000005UD { align1 1H compacted }; < and(16) g96<1>UD g85<1,1,0>UD 0x00000003UD { align1 1H compacted }; < and(16) g90<1>UD g87<1,1,0>UD 0x00000007UD { align1 1H I@3 compacted }; < shl(16) g94<1>D g92<8,8,1>D 0x00000002UD { align1 1H I@3 }; < add(16) g98<1>D g96<1,1,0>D g94<1,1,0>D { align1 1H I@1 compacted }; < sync nop(1) null<0,1,0>UB { align1 WE_all 1N $1.dst }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N $1.dst }; add(16) g75<1>D g114<1,1,0>D g16.6<0,1,0>D { align1 1H compacted }; | add(16) g122<1>D g20<1,1,0>D g16.6<0,1,0>D { align1 1H I@7 compacted }; add(16) g77<1>D g116<1,1,0>D g16.7<0,1,0>D { align1 1H compacted }; | add(16) g124<1>D g22<1,1,0>D g16.7<0,1,0>D { align1 1H I@7 compacted }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N $0.src }; | sync nop(1) null<0,1,0>UB { align1 WE_all 1N $1.dst }; shl(16) g101<1>D g75<8,8,1>D 0x00000003UD { align1 1H I@2 }; | add(16) g9<1>D g7<1,1,0>D g5<1,1,0>D { align1 1H I@3 compacted }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N $1.src }; | shl(16) g24<1>D g122<8,8,1>D 0x00000003UD { align1 1H I@3 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N $2.src }; | shl(16) g26<1>D g124<8,8,1>D 0x00000003UD { align1 1H I@3 }; shl(16) g103<1>D g77<8,8,1>D 0x00000003UD { align1 1H I@2 }; | sync nop(1) null<0,1,0>UB { align1 WE_all 1N $1.dst }; add(16) g105<1>D g101<1,1,0>D g90<1,1,0>D { align1 1H I@2 compacted }; | shr(16) g11<1>UD g9<1,1,0>UD 0x00000002UD { align1 1H I@3 compacted }; and(16) g100<1>UD g98<1,1,0>UD 0x00000007UD { align1 1H I@6 compacted }; | sync nop(1) null<0,1,0>UB { align1 WE_all 1N $1.dst }; add(16) g107<1>D g103<1,1,0>D g100<1,1,0>D { align1 1H I@1 compacted }; | shr(16) g15<1>UD g9<1,1,0>UD 0x00000005UD { align1 1H compacted }; > and(16) g19<1>UD g9<1,1,0>UD 0x00000003UD { align1 1H compacted }; > sync nop(1) null<0,1,0>UB { align1 WE_all 1N $1.dst }; > and(16) g13<1>UD g11<1,1,0>UD 0x00000007UD { align1 1H I@3 compacted }; > sync nop(1) null<0,1,0>UB { align1 WE_all 1N $2.dst }; > shl(16) g17<1>D g15<8,8,1>D 0x00000002UD { align1 1H I@3 }; > add(16) g28<1>D g24<1,1,0>D g13<1,1,0>D { align1 1H I@2 compacted }; > add(16) g21<1>D g19<1,1,0>D g17<1,1,0>D { align1 1H I@2 compacted }; > and(16) g23<1>UD g21<1,1,0>UD 0x00000007UD { align1 1H I@1 compacted }; > add(16) g30<1>D g26<1,1,0>D g23<1,1,0>D { align1 1H I@1 compacted }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N $0.dst }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N $0.dst }; cmp.ge.f0.0(16) g109<1>UD g107<1,1,0>UD g1.3<0,1,0>UD { align1 1H I@1 compacted }; | cmp.ge.f0.0(16) g32<1>UD g30<1,1,0>UD g1.3<0,1,0>UD { align1 1H I@1 compacted }; cmp.ge.f0.0(16) g111<1>UD g105<1,1,0>UD g1.2<0,1,0>UD { align1 1H I@4 compacted }; | cmp.ge.f0.0(16) g34<1>UD g28<1,1,0>UD g1.2<0,1,0>UD { align1 1H I@5 compacted }; or.nz.f0.0(16) null<1>UD g109<8,8,1>UD g111<8,8,1>UD { align1 1H I@1 }; | or.nz.f0.0(16) null<1>UD g32<8,8,1>UD g34<8,8,1>UD { align1 1H I@1 }; (-f0.0) if(16) JIP: LABEL0 UIP: LABEL0 { align1 1H }; (-f0.0) if(16) JIP: LABEL0 UIP: LABEL0 { align1 1H }; END B0 ->B1 ->B22 END B0 ->B1 ->B22 START B1 <-B0 (996 cycles) | START B1 <-B0 (998 cycles) sync nop(1) null<0,1,0>UB { align1 WE_all 1N $1.dst }; < mov(16) g9<1>D 1D { align1 1H }; mov(16) g9<1>D 1D { align1 1H }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N $0.dst }; | mov(16) g11<1>D -84D { align1 1H }; add(16) g5<1>D g1<0,1,0>D g105<1,1,0>D { align1 1H compacted }; | mov(16) g13<1>D -32D { align1 1H }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N $0.dst }; | mov(16) g15<1>D -99D { align1 1H }; add(16) g7<1>D g1.1<0,1,0>D g107<1,1,0>D { align1 1H compacted }; | add(16) g5<1>D g1<0,1,0>D g28<1,1,0>D { align1 1H compacted }; mov(16) g112<1>F g105<1,1,0>UD { align1 1H I@5 compacted }; | add(16) g7<1>D g1.1<0,1,0>D g30<1,1,0>D { align1 1H compacted }; mov(16) g114<1>F g107<1,1,0>UD { align1 1H compacted }; | mov(16) g35<1>F g28<1,1,0>UD { align1 1H I@7 compacted }; mov(16) g120<1>F g1.2<0,1,0>UD { align1 1H compacted }; | mov(16) g37<1>F g30<1,1,0>UD { align1 1H compacted }; mov(16) g122<1>F g1.3<0,1,0>UD { align1 1H compacted }; | mov(16) g43<1>F g1.2<0,1,0>UD { align1 1H compacted }; mov(1) g74<1>D 1032148797D { align1 WE_all 1N }; | mov(16) g45<1>F g1.3<0,1,0>UD { align1 1H compacted }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N A@2 }; | mov(1) g121<1>D 1032148797D { align1 WE_all 1N }; send(16) g102UD g5UD nullUD 0x0885a004 0x00000000 | sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@2 }; > send(16) g18UD g5UD nullUD 0x0885a004 0x00000000 sampler MsgDesc: ld_lz SIMD16 Surface = 4 Sampler = 0 mlen 4 ex_mlen 0 rlen 8 { align1 1H sampler MsgDesc: ld_lz SIMD16 Surface = 4 Sampler = 0 mlen 4 ex_mlen 0 rlen 8 { align1 1H add(16) g116<1>F g112<1,1,0>F 0x3f000000F /* 0.5F */ { align1 1H F@4 compacted }; | add(16) g39<1>F g35<1,1,0>F 0x3f000000F /* 0.5F */ { align1 1H F@4 compacted }; add(16) g118<1>F g114<1,1,0>F 0x3f000000F /* 0.5F */ { align1 1H F@4 compacted }; | add(16) g41<1>F g37<1,1,0>F 0x3f000000F /* 0.5F */ { align1 1H F@4 compacted }; math inv(16) g124<1>F g120<8,8,1>F null<8,8,1>F { align1 1H @4 $4 }; | math inv(16) g47<1>F g43<8,8,1>F null<8,8,1>F { align1 1H @4 $4 }; math inv(16) g126<1>F g122<8,8,1>F null<8,8,1>F { align1 1H @3 $5 }; | math inv(16) g49<1>F g45<8,8,1>F null<8,8,1>F { align1 1H @3 $5 }; mov(1) g74.4<1>D 1056964608D { align1 WE_all 1N I@1 }; | mov(1) g121.4<1>D 1056964608D { align1 WE_all 1N I@1 }; mul(16) g94<1>F g116<1,1,0>F g124<1,1,0>F { align1 1H @2 $4.dst compacted }; | mul(16) g35<1>F g39<1,1,0>F g47<1,1,0>F { align1 1H @2 $4.dst compacted }; mul(16) g31<1>F g1.4<0,1,0>F g124<1,1,0>F { align1 1H compacted }; | mul(16) g71<1>F g1.4<0,1,0>F g47<1,1,0>F { align1 1H compacted }; mul(16) g33<1>F g1.5<0,1,0>F g124<1,1,0>F { align1 1H compacted }; | mul(16) g73<1>F g1.5<0,1,0>F g47<1,1,0>F { align1 1H compacted }; mul(16) g35<1>F g1.6<0,1,0>F g124<1,1,0>F { align1 1H compacted }; | mul(16) g75<1>F g1.6<0,1,0>F g47<1,1,0>F { align1 1H compacted }; mul(16) g37<1>F g1.7<0,1,0>F g124<1,1,0>F { align1 1H compacted }; | mul(16) g77<1>F g1.7<0,1,0>F g47<1,1,0>F { align1 1H compacted }; mul(16) g43<1>F g118<1,1,0>F g126<1,1,0>F { align1 1H @6 $5.dst compacted }; | sync nop(1) null<0,1,0>UB { align1 WE_all 1N $5.dst }; > mul(16) g33<1>F g41<1,1,0>F g49<1,1,0>F { align1 1H A@6 compacted }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N $0.dst }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N $0.dst }; mul(16) g39<1>F g2<0,1,0>F g126<1,1,0>F { align1 1H compacted }; | mul(16) g79<1>F g2<0,1,0>F g49<1,1,0>F { align1 1H compacted }; mul(16) g41<1>F g2.1<0,1,0>F g126<1,1,0>F { align1 1H compacted }; | mul(16) g81<1>F g2.1<0,1,0>F g49<1,1,0>F { align1 1H compacted }; mul(16) g45<1>F g2.2<0,1,0>F g126<1,1,0>F { align1 1H compacted }; | mul(16) g83<1>F g2.2<0,1,0>F g49<1,1,0>F { align1 1H compacted }; mul(16) g47<1>F g2.3<0,1,0>F g126<1,1,0>F { align1 1H compacted }; | mul(16) g85<1>F g2.3<0,1,0>F g49<1,1,0>F { align1 1H compacted }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N $1.dst }; | mul(16) g51<1>F -g2<0,1,0>F g33<1,1,0>F { align1 1H F@5 compacted }; mul(16) g11<1>F -g2<0,1,0>F g43<1,1,0>F { align1 1H F@5 compacted }; | mul(16) g53<1>F -g2.1<0,1,0>F g33<1,1,0>F { align1 1H compacted }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N $1.dst }; | mul(16) g55<1>F -g2.2<0,1,0>F g33<1,1,0>F { align1 1H compacted }; mul(16) g13<1>F -g2.1<0,1,0>F g43<1,1,0>F { align1 1H compacted }; | mul(16) g57<1>F -g2.3<0,1,0>F g33<1,1,0>F { align1 1H compacted }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N $1.dst }; | sel.ge(16) g87<1>F g71<1,1,0>F g79<1,1,0>F { align1 1H F@7 compacted }; mul(16) g15<1>F -g2.2<0,1,0>F g43<1,1,0>F { align1 1H compacted }; | sel.ge(16) g89<1>F g73<1,1,0>F g81<1,1,0>F { align1 1H F@7 compacted }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N $2.dst }; | sel.ge(16) g91<1>F g75<1,1,0>F g83<1,1,0>F { align1 1H F@7 compacted }; mul(16) g17<1>F -g2.3<0,1,0>F g43<1,1,0>F { align1 1H compacted }; | sel.ge(16) g93<1>F g77<1,1,0>F g85<1,1,0>F { align1 1H F@7 compacted }; sel.ge(16) g49<1>F g31<1,1,0>F g39<1,1,0>F { align1 1H F@7 compacted }; | mad(16) g59<1>F g51<8,8,1>F g35<8,8,1>F -g1.4<0,1,0>F { align1 1H F@7 }; sel.ge(16) g51<1>F g33<1,1,0>F g41<1,1,0>F { align1 1H F@7 compacted }; | mad(16) g61<1>F g53<8,8,1>F g35<8,8,1>F -g1.5<0,1,0>F { align1 1H F@7 }; sel.ge(16) g53<1>F g35<1,1,0>F g45<1,1,0>F { align1 1H F@7 compacted }; | mad(16) g63<1>F g55<8,8,1>F g35<8,8,1>F -g1.6<0,1,0>F { align1 1H F@7 }; sel.ge(16) g55<1>F g37<1,1,0>F g47<1,1,0>F { align1 1H F@7 compacted }; | mad(16) g65<1>F g57<8,8,1>F g35<8,8,1>F -g1.7<0,1,0>F { align1 1H F@7 }; mad(16) g19<1>F g11<8,8,1>F g94<8,8,1>F -g1.4<0,1,0>F { align1 1H F@7 }; | add(16) g96<1>F g87<8,8,1>F 0x3c008081F /* 0.00784314F */ { align1 1H F@7 }; mad(16) g21<1>F g13<8,8,1>F g94<8,8,1>F -g1.5<0,1,0>F { align1 1H F@7 }; | add(16) g98<1>F g89<8,8,1>F 0x3c008081F /* 0.00784314F */ { align1 1H F@7 }; mad(16) g23<1>F g15<8,8,1>F g94<8,8,1>F -g1.6<0,1,0>F { align1 1H F@7 }; | add(16) g100<1>F g91<8,8,1>F 0x3c008081F /* 0.00784314F */ { align1 1H F@7 }; mad(16) g25<1>F g17<8,8,1>F g94<8,8,1>F -g1.7<0,1,0>F { align1 1H F@7 }; | add(16) g102<1>F g93<8,8,1>F 0x3c008081F /* 0.00784314F */ { align1 1H F@7 }; add(16) g57<1>F g49<8,8,1>F 0x3c008081F /* 0.00784314F */ { align1 1H F@7 }; < add(16) g59<1>F g51<8,8,1>F 0x3c008081F /* 0.00784314F */ { align1 1H F@7 }; < add(16) g61<1>F g53<8,8,1>F 0x3c008081F /* 0.00784314F */ { align1 1H F@7 }; < add(16) g63<1>F g55<8,8,1>F 0x3c008081F /* 0.00784314F */ { align1 1H F@7 }; < sync nop(1) null<0,1,0>UB { align1 WE_all 1N A@1 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N A@1 }; mad(16) g27<1>F -g74.0<0,1,0>F g74.4<0,1,0>F g19<1,1,1>F { align1 1H }; | mad(16) g67<1>F -g121.0<0,1,0>F g121.4<0,1,0>F g59<1,1,1>F { align1 1H }; mov(1) g74.1<1>D 1036553219D { align1 WE_all 1N F@1 }; | mov(1) g121.1<1>D 1036553219D { align1 WE_all 1N F@1 }; add(16) g65<1>F g102<1,1,0>F g27<1,1,0>F { align1 1H @1 $3.dst compacted }; | add(16) g104<1>F g18<1,1,0>F g67<1,1,0>F { align1 1H @1 $3.dst compacted }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N A@1 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N A@1 }; mad(16) g28<1>F -g74.1<0,1,0>F g74.4<0,1,0>F g21<1,1,1>F { align1 1H }; | mad(16) g68<1>F -g121.1<0,1,0>F g121.4<0,1,0>F g61<1,1,1>F { align1 1H }; mov(1) g74.2<1>D 1033701334D { align1 WE_all 1N F@1 }; | mov(1) g121.2<1>D 1033701334D { align1 WE_all 1N F@1 }; add(16) g67<1>F g104<1,1,0>F g28<1,1,0>F { align1 1H @1 $3.dst compacted }; | add(16) g106<1>F g20<1,1,0>F g68<1,1,0>F { align1 1H @1 $3.dst compacted }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N A@1 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N A@1 }; mad(16) g29<1>F -g74.2<0,1,0>F g74.4<0,1,0>F g23<1,1,1>F { align1 1H }; | mad(16) g69<1>F -g121.2<0,1,0>F g121.4<0,1,0>F g63<1,1,1>F { align1 1H }; mov(1) g74.3<1>D 1033358823D { align1 WE_all 1N F@1 }; | mov(1) g121.3<1>D 1033358823D { align1 WE_all 1N F@1 }; add(16) g69<1>F g106<1,1,0>F g29<1,1,0>F { align1 1H @1 $3.dst compacted }; | add(16) g108<1>F g22<1,1,0>F g69<1,1,0>F { align1 1H @1 $3.dst compacted }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@1 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@1 }; mad(16) g30<1>F -g74.3<0,1,0>F g74.4<0,1,0>F g25<1,1,1>F { align1 1H }; | mad(16) g70<1>F -g121.3<0,1,0>F g121.4<0,1,0>F g65<1,1,1>F { align1 1H }; add(16) g71<1>F g108<1,1,0>F g30<1,1,0>F { align1 1H @1 $3.dst compacted }; | add(16) g110<1>F g24<1,1,0>F g70<1,1,0>F { align1 1H @1 $3.dst compacted }; cmp.l.f0.0(16) g75<1>F (abs)g71<1,1,0>F g63<1,1,0>F { align1 1H F@1 compacted }; | cmp.l.f0.0(16) g112<1>F (abs)g110<1,1,0>F g102<1,1,0>F { align1 1H F@1 compacted }; cmp.l.f0.0(16) g77<1>F (abs)g69<1,1,0>F g61<1,1,0>F { align1 1H F@4 compacted }; | cmp.l.f0.0(16) g114<1>F (abs)g108<1,1,0>F g100<1,1,0>F { align1 1H F@4 compacted }; cmp.l.f0.0(16) g81<1>F (abs)g67<1,1,0>F g59<1,1,0>F { align1 1H F@7 compacted }; | sync nop(1) null<0,1,0>UB { align1 WE_all 1N $0.src }; cmp.l.f0.0(16) g85<1>F (abs)g65<1,1,0>F g57<1,1,0>F { align1 1H F@7 compacted }; | sync nop(1) null<0,1,0>UB { align1 WE_all 1N $1.src }; and(16) g79<1>UD g75<1,1,0>UD g77<1,1,0>UD { align1 1H F@3 compacted }; | cmp.l.f0.0(16) g118<1>F (abs)g106<1,1,0>F g98<1,1,0>F { align1 1H F@7 compacted }; and(16) g83<1>UD g79<1,1,0>UD g81<1,1,0>UD { align1 1H A@1 compacted }; | cmp.l.f0.0(16) g124<1>F (abs)g104<1,1,0>F g96<1,1,0>F { align1 1H F@7 compacted }; and.nz.f0.0(16) null<1>UD g83<8,8,1>UD g85<8,8,1>UD { align1 1H A@1 }; | and(16) g116<1>UD g112<1,1,0>UD g114<1,1,0>UD { align1 1H F@3 compacted }; > and(16) g122<1>UD g116<1,1,0>UD g118<1,1,0>UD { align1 1H A@1 compacted }; > and.nz.f0.0(16) null<1>UD g122<8,8,1>UD g124<8,8,1>UD { align1 1H A@1 }; (+f0.0) if(16) JIP: LABEL2 UIP: LABEL1 { align1 1H }; (+f0.0) if(16) JIP: LABEL2 UIP: LABEL1 { align1 1H }; END B1 ->B2 ->B5 END B1 ->B2 ->B5 START B2 <-B1 (128 cycles) START B2 <-B1 (128 cycles) mov(16) g86<1>D 0D { align1 WE_all 1H }; | mov(16) g125<1>D 0D { align1 WE_all 1H }; mov(16) g86<1>D g9<8,8,1>D { align1 1H }; | mov(16) g125<1>D g9<8,8,1>D { align1 1H }; add(8) g86.1<2>D g86<8,4,2>D g86.1<8,4,2>D { align1 WE_all 1Q I@1 }; | add(8) g125.1<2>D g125<8,4,2>D g125.1<8,4,2>D { align1 WE_all 1Q I@1 }; add(4) g86.2<4>D g86.1<8,2,4>D g86.2<8,2,4>D { align1 WE_all 1N I@1 }; | add(4) g125.2<4>D g125.1<8,2,4>D g125.2<8,2,4>D { align1 WE_all 1N I@1 }; add(4) g86.3<4>D g86.1<8,2,4>D g86.3<8,2,4>D { align1 WE_all 1N I@1 }; | add(4) g125.3<4>D g125.1<8,2,4>D g125.3<8,2,4>D { align1 WE_all 1N I@1 }; add(4) g86.4<1>D g86.3<0,1,0>D g86.4<4,4,1>D { align1 WE_all 1N I@1 }; | add(4) g125.4<1>D g125.3<0,1,0>D g125.4<4,4,1>D { align1 WE_all 1N I@1 }; add(4) g87.4<1>D g87.3<0,1,0>D g87.4<4,4,1>D { align1 WE_all 1N I@2 }; | add(4) g126.4<1>D g126.3<0,1,0>D g126.4<4,4,1>D { align1 WE_all 1N I@2 }; add(8) g87<1>D g86.7<0,1,0>D g87<1,1,0>D { align1 WE_all 1Q I@1 compacted }; | add(8) g126<1>D g125.7<0,1,0>D g126<1,1,0>D { align1 WE_all 1Q I@1 compacted }; fbl(1) g90<1>UD mask0<0,1,0>UD { align1 WE_all 1N compacted }; | fbl(1) g17<1>UD mask0<0,1,0>UD { align1 WE_all 1N compacted }; mov(16) g92<1>D g89<8,8,1>UW { align1 1H }; | mov(16) g19<1>D g95<8,8,1>UW { align1 1H F@7 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@1 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@1 }; cmp.z.f0.0(16) null<1>D g92<8,8,1>D g90<0,1,0>D { align1 1H }; | cmp.z.f0.0(16) null<1>D g19<8,8,1>D g17<0,1,0>D { align1 1H }; (+f0.0) if(16) JIP: LABEL3 UIP: LABEL3 { align1 1H }; (+f0.0) if(16) JIP: LABEL3 UIP: LABEL3 { align1 1H }; END B2 ->B3 ->B4 END B2 ->B3 ->B4 START B3 <-B2 (24 cycles) START B3 <-B2 (24 cycles) mov(16) g118<1>D 0D { align1 1H }; | mov(16) g24<1>D 0D { align1 1H F@5 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@6 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@6 }; mov(16) g120<1>D g87.7<0,1,0>D { align1 1H $4.src }; | mov(16) g26<1>D g126.7<0,1,0>D { align1 1H }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@1 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@1 }; send(16) nullUD g118UD g120UD 0x6404050c 0x02000080 | send(16) nullUD g24UD g26UD 0x6404050c 0x02000080 ugm MsgDesc: ( atomic_add, a32, d32, V1, L1UC_L3WB dst_len = 0, src0_len = 2, src1_len = | ugm MsgDesc: ( atomic_add, a32, d32, V1, L1UC_L3WB dst_len = 0, src0_len = 2, src1_len = END B3 ->B4 END B3 ->B4 START B4 <-B3 <-B2 (24 cycles) START B4 <-B3 <-B2 (24 cycles) LABEL3: LABEL3: endif(16) JIP: LABEL4 { align1 1H }; endif(16) JIP: LABEL4 { align1 1H }; mov(16) g51<1>UD 0x3f800000UD { align1 1H }; | mov(16) g77<1>UD 0x3f800000UD { align1 1H }; mov(16) g49<1>UD 0x00000000UD { align1 1H }; | mov(16) g75<1>UD 0x00000000UD { align1 1H }; LABEL4: LABEL4: else(16) JIP: LABEL1 UIP: LABEL1 { align1 1H }; else(16) JIP: LABEL1 UIP: LABEL1 { align1 1H }; END B4 ->B5 ->B6 END B4 ->B5 ->B6 START B5 <-B1 <-B4 (8 cycles) START B5 <-B1 <-B4 (8 cycles) LABEL2: LABEL2: mov(16) g51<1>UD 0x00000000UD { align1 1H I@3 }; | mov(16) g77<1>UD 0x00000000UD { align1 1H I@3 }; mov(16) g49<1>UD 0x3f800000UD { align1 1H I@3 }; | mov(16) g75<1>UD 0x3f800000UD { align1 1H I@3 }; END B5 ->B6 END B5 ->B6 START B6 <-B5 <-B4 (1768 cycles) START B6 <-B5 <-B4 (1768 cycles) LABEL1: LABEL1: endif(16) JIP: LABEL0 { align1 1H }; endif(16) JIP: LABEL0 { align1 1H }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N $4.src }; | sync nop(1) null<0,1,0>UB { align1 WE_all 1N $6.src }; mov(8) g121<1>D g5<8,8,1>D { align1 1Q $3.src }; | mov(8) g27<1>D g5<8,8,1>D { align1 1Q $3.src }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N $5.src }; | mov(8) g28<1>D g7<8,8,1>D { align1 1Q $3.src }; mov(8) g122<1>D g7<8,8,1>D { align1 1Q $3.src }; | mov(8) g29<1>D 0D { align1 1Q }; mov(8) g123<1>D 0D { align1 1Q $5.src }; | mov(8) g37<1>D g75<8,8,1>D { align1 1Q I@5 }; mov(8) g11<1>D g49<8,8,1>D { align1 1Q I@5 }; | mov(8) g38<1>D g77<8,8,1>D { align1 1Q I@7 }; mov(8) g12<1>D g51<8,8,1>D { align1 1Q I@7 }; | mov(8) g39<1>D 0D { align1 1Q }; mov(8) g13<1>D 0D { align1 1Q }; | mov(8) g40<1>D 1065353216D { align1 1Q }; mov(8) g14<1>D 1065353216D { align1 1Q }; < sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@1 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@1 }; send(8) nullUD g121UD g11UD 0x06035003 0x00000100 | send(8) nullUD g27UD g37UD 0x06035003 0x00000100 dp data 1 MsgDesc: (DC typed surface write, Surface = 3, SIMD16, Mask = 0x0) mlen 3 ex_ml | dp data 1 MsgDesc: (DC typed surface write, Surface = 3, SIMD16, Mask = 0x0) mlen 3 ex_ml sync nop(1) null<0,1,0>UB { align1 WE_all 3N $6.src }; | sync nop(1) null<0,1,0>UB { align1 WE_all 3N $7.src }; mov(8) g12<1>D g6<8,8,1>D { align1 2Q $3.src }; | mov(8) g38<1>D g6<8,8,1>D { align1 2Q $3.src }; sync nop(1) null<0,1,0>UB { align1 WE_all 3N $6.src }; | sync nop(1) null<0,1,0>UB { align1 WE_all 3N $7.src }; mov(8) g13<1>D g8<8,8,1>D { align1 2Q $3.src }; | mov(8) g39<1>D g8<8,8,1>D { align1 2Q $3.src }; mov(8) g14<1>D 0D { align1 2Q $6.src }; | mov(8) g40<1>D 0D { align1 2Q $7.src }; mov(8) g15<1>D g50<8,8,1>D { align1 2Q }; | mov(8) g41<1>D g76<8,8,1>D { align1 2Q }; mov(8) g16<1>D g52<8,8,1>D { align1 2Q }; | mov(8) g42<1>D g78<8,8,1>D { align1 2Q }; mov(8) g17<1>D 0D { align1 2Q }; | mov(8) g43<1>D 0D { align1 2Q $4.src }; mov(8) g18<1>D 1065353216D { align1 2Q }; | mov(8) g44<1>D 1065353216D { align1 2Q $4.src }; sync nop(1) null<0,1,0>UB { align1 WE_all 3N I@1 }; sync nop(1) null<0,1,0>UB { align1 WE_all 3N I@1 }; send(8) nullUD g12UD g15UD 0x06036003 0x00000100 | send(8) nullUD g38UD g41UD 0x06036003 0x00000100 dp data 1 MsgDesc: (DC typed surface write, Surface = 3, SIMD8, Mask = 0x0) mlen 3 ex_mle | dp data 1 MsgDesc: (DC typed surface write, Surface = 3, SIMD8, Mask = 0x0) mlen 3 ex_mle send(16) g96UD g5UD nullUD 0x0885a005 0x00000000 < sampler MsgDesc: ld_lz SIMD16 Surface = 5 Sampler = 0 mlen 4 ex_mlen 0 rlen 8 { align1 1H < sync nop(1) null<0,1,0>UB { align1 WE_all 1N $0.dst }; < mul(16) g104<1>F -g3<0,1,0>F g43<1,1,0>F { align1 1H F@7 compacted }; < mul(16) g106<1>F -g3.1<0,1,0>F g43<1,1,0>F { align1 1H F@7 compacted }; < mul(16) g108<1>F -g3.2<0,1,0>F g43<1,1,0>F { align1 1H F@7 compacted }; < mul(16) g110<1>F -g3.3<0,1,0>F g43<1,1,0>F { align1 1H compacted }; < mov(1) g74.5<1>D 1036222963D { align1 WE_all 1N F@7 }; < mov(1) g61<1>D 1033784884D { align1 WE_all 1N F@7 }; < sync nop(1) null<0,1,0>UB { align1 WE_all 1N $7.src }; < mul(16) g11<1>F g2.4<0,1,0>F g124<1,1,0>F { align1 1H $6.src compacted }; < mul(16) g13<1>F g2.5<0,1,0>F g124<1,1,0>F { align1 1H $7.src compacted }; < mul(16) g15<1>F g2.6<0,1,0>F g124<1,1,0>F { align1 1H $7.src compacted }; < mul(16) g17<1>F g2.7<0,1,0>F g124<1,1,0>F { align1 1H $7.src compacted }; < mul(16) g19<1>F g3<0,1,0>F g126<1,1,0>F { align1 1H compacted }; < mul(16) g21<1>F g3.1<0,1,0>F g126<1,1,0>F { align1 1H compacted }; < mul(16) g23<1>F g3.2<0,1,0>F g126<1,1,0>F { align1 1H compacted }; < mul(16) g25<1>F g3.3<0,1,0>F g126<1,1,0>F { align1 1H compacted }; < mad(16) g112<1>F g104<8,8,1>F g94<8,8,1>F -g2.4<0,1,0>F { align1 1H }; < mad(16) g114<1>F g106<8,8,1>F g94<8,8,1>F -g2.5<0,1,0>F { align1 1H }; < mad(16) g116<1>F g108<8,8,1>F g94<8,8,1>F -g2.6<0,1,0>F { align1 1H }; < mad(16) g118<1>F g110<8,8,1>F g94<8,8,1>F -g2.7<0,1,0>F { align1 1H $4.src }; < sel.ge(16) g27<1>F g11<1,1,0>F g19<1,1,0>F { align1 1H F@7 compacted }; < sel.ge(16) g29<1>F g13<1,1,0>F g21<1,1,0>F { align1 1H F@7 compacted }; < sel.ge(16) g31<1>F g15<1,1,0>F g23<1,1,0>F { align1 1H F@7 compacted }; < sel.ge(16) g33<1>F g17<1,1,0>F g25<1,1,0>F { align1 1H F@7 compacted }; < sync nop(1) null<0,1,0>UB { align1 WE_all 1N $6.src }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N $6.src }; > sync nop(1) null<0,1,0>UB { align1 WE_all 1N F@5 }; > send(16) g19UD g5UD nullUD 0x0885a005 0x00000000 > sampler MsgDesc: ld_lz SIMD16 Surface = 5 Sampler = 0 mlen 4 ex_mlen 0 rlen 8 { align1 1H > sync nop(1) null<0,1,0>UB { align1 WE_all 1N $0.dst }; > mul(16) g27<1>F -g3<0,1,0>F g33<1,1,0>F { align1 1H $7.src compacted }; > mul(16) g29<1>F -g3.1<0,1,0>F g33<1,1,0>F { align1 1H $7.src compacted }; > mul(16) g31<1>F -g3.2<0,1,0>F g33<1,1,0>F { align1 1H compacted }; > sync nop(1) null<0,1,0>UB { align1 WE_all 1N $8.src }; > mul(16) g37<1>F -g3.3<0,1,0>F g33<1,1,0>F { align1 1H $7.src compacted }; > mov(1) g121.5<1>D 1036222963D { align1 WE_all 1N F@7 }; > mov(1) g88<1>D 1033784884D { align1 WE_all 1N }; > mul(16) g52<1>F g2.4<0,1,0>F g47<1,1,0>F { align1 1H compacted }; > mul(16) g54<1>F g2.5<0,1,0>F g47<1,1,0>F { align1 1H compacted }; > mul(16) g56<1>F g2.6<0,1,0>F g47<1,1,0>F { align1 1H compacted }; > mul(16) g58<1>F g2.7<0,1,0>F g47<1,1,0>F { align1 1H compacted }; > mul(16) g60<1>F g3<0,1,0>F g49<1,1,0>F { align1 1H compacted }; > mul(16) g62<1>F g3.1<0,1,0>F g49<1,1,0>F { align1 1H compacted }; > mul(16) g64<1>F g3.2<0,1,0>F g49<1,1,0>F { align1 1H compacted }; > mul(16) g66<1>F g3.3<0,1,0>F g49<1,1,0>F { align1 1H compacted }; > mad(16) g39<1>F g27<8,8,1>F g35<8,8,1>F -g2.4<0,1,0>F { align1 1H $8.src }; > mad(16) g41<1>F g29<8,8,1>F g35<8,8,1>F -g2.5<0,1,0>F { align1 1H $8.src }; > mad(16) g43<1>F g31<8,8,1>F g35<8,8,1>F -g2.6<0,1,0>F { align1 1H $8.src }; > mad(16) g45<1>F g37<8,8,1>F g35<8,8,1>F -g2.7<0,1,0>F { align1 1H $5.src }; > sel.ge(16) g68<1>F g52<1,1,0>F g60<1,1,0>F { align1 1H F@7 compacted }; > sel.ge(16) g70<1>F g54<1,1,0>F g62<1,1,0>F { align1 1H F@7 compacted }; > sel.ge(16) g72<1>F g56<1,1,0>F g64<1,1,0>F { align1 1H F@7 compacted }; > sel.ge(16) g74<1>F g58<1,1,0>F g66<1,1,0>F { align1 1H F@7 compacted }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N A@2 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N A@2 }; mad(16) g120<1>F -g74.5<0,1,0>F g74.4<0,1,0>F g112<1,1,1>F { align1 1H $4.src }; | mad(16) g47<1>F -g121.5<0,1,0>F g121.4<0,1,0>F g39<1,1,1>F { align1 1H }; add(16) g35<1>F g27<1,1,0>F 0x3b000000F /* 0.00195312F */ { align1 1H F@5 compacted }; | add(16) g76<1>F g68<1,1,0>F 0x3b000000F /* 0.00195312F */ { align1 1H A@5 compacted }; mov(1) g74.6<1>D 1036632931D { align1 WE_all 1N F@2 }; | mov(1) g121.6<1>D 1036632931D { align1 WE_all 1N F@2 }; add(16) g37<1>F g29<1,1,0>F 0x3b000000F /* 0.00195312F */ { align1 1H F@5 compacted }; | add(16) g78<1>F g70<1,1,0>F 0x3b000000F /* 0.00195312F */ { align1 1H A@5 compacted }; add(16) g39<1>F g31<1,1,0>F 0x3b000000F /* 0.00195312F */ { align1 1H F@5 compacted }; | add(16) g80<1>F g72<1,1,0>F 0x3b000000F /* 0.00195312F */ { align1 1H F@5 compacted }; add(16) g41<1>F g33<1,1,0>F 0x3b000000F /* 0.00195312F */ { align1 1H F@5 compacted }; | add(16) g82<1>F g74<1,1,0>F 0x3b000000F /* 0.00195312F */ { align1 1H F@5 compacted }; add(16) g45<1>F g96<1,1,0>F g120<1,1,0>F { align1 1H @5 $8.dst compacted }; | add(16) g84<1>F g19<1,1,0>F g47<1,1,0>F { align1 1H @5 $9.dst compacted }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@1 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@1 }; mad(16) g121<1>F -g74.6<0,1,0>F g74.4<0,1,0>F g114<1,1,1>F { align1 1H $6.src }; | mad(16) g48<1>F -g121.6<0,1,0>F g121.4<0,1,0>F g41<1,1,1>F { align1 1H }; mov(1) g74.7<1>D 1036329505D { align1 WE_all 1N F@1 }; | mov(1) g121.7<1>D 1036329505D { align1 WE_all 1N F@1 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@1 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@1 }; mad(16) g124<1>F -g61.0<0,1,0>F g74.4<0,1,0>F g118<1,1,1>F { align1 1H }; | mad(16) g51<1>F -g88.0<0,1,0>F g121.4<0,1,0>F g45<1,1,1>F { align1 1H }; add(16) g47<1>F g98<1,1,0>F g121<1,1,0>F { align1 1H @2 $8.dst compacted }; | add(16) g86<1>F g21<1,1,0>F g48<1,1,0>F { align1 1H @2 $9.dst compacted }; mad(16) g122<1>F -g74.7<0,1,0>F g74.4<0,1,0>F g116<1,1,1>F { align1 1H $6.src }; | mad(16) g49<1>F -g121.7<0,1,0>F g121.4<0,1,0>F g43<1,1,1>F { align1 1H }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N $8.dst }; | add(16) g90<1>F g25<1,1,0>F g51<1,1,0>F { align1 1H @3 $9.dst compacted }; add(16) g51<1>F g102<1,1,0>F g124<1,1,0>F { align1 1H A@3 compacted }; | add(16) g88<1>F g23<1,1,0>F g49<1,1,0>F { align1 1H @2 $9.dst compacted }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N $8.dst }; | cmp.l.f0.0(16) g92<1>F (abs)g90<1,1,0>F g82<1,1,0>F { align1 1H F@2 compacted }; add(16) g49<1>F g100<1,1,0>F g122<1,1,0>F { align1 1H A@2 compacted }; | cmp.l.f0.0(16) g96<1>F (abs)g88<1,1,0>F g80<1,1,0>F { align1 1H F@2 compacted }; cmp.l.f0.0(16) g53<1>F (abs)g51<1,1,0>F g41<1,1,0>F { align1 1H F@2 compacted }; | cmp.l.f0.0(16) g100<1>F (abs)g86<1,1,0>F g78<1,1,0>F { align1 1H F@6 compacted }; cmp.l.f0.0(16) g55<1>F (abs)g49<1,1,0>F g39<1,1,0>F { align1 1H F@2 compacted }; | cmp.l.f0.0(16) g104<1>F (abs)g84<1,1,0>F g76<1,1,0>F { align1 1H F@7 compacted }; cmp.l.f0.0(16) g59<1>F (abs)g47<1,1,0>F g37<1,1,0>F { align1 1H F@6 compacted }; | and(16) g98<1>UD g92<1,1,0>UD g96<1,1,0>UD { align1 1H F@3 compacted }; cmp.l.f0.0(16) g63<1>F (abs)g45<1,1,0>F g35<1,1,0>F { align1 1H F@7 compacted }; | and(16) g102<1>UD g98<1,1,0>UD g100<1,1,0>UD { align1 1H A@1 compacted }; and(16) g57<1>UD g53<1,1,0>UD g55<1,1,0>UD { align1 1H F@3 compacted }; | and.nz.f0.0(16) null<1>UD g102<8,8,1>UD g104<8,8,1>UD { align1 1H A@1 }; and(16) g61<1>UD g57<1,1,0>UD g59<1,1,0>UD { align1 1H A@1 compacted }; < and.nz.f0.0(16) null<1>UD g61<8,8,1>UD g63<8,8,1>UD { align1 1H A@1 }; < (+f0.0) if(16) JIP: LABEL6 UIP: LABEL5 { align1 1H }; (+f0.0) if(16) JIP: LABEL6 UIP: LABEL5 { align1 1H }; END B6 ->B7 ->B10 END B6 ->B7 ->B10 START B7 <-B6 (128 cycles) START B7 <-B6 (128 cycles) mov(16) g64<1>D 0D { align1 WE_all 1H I@2 }; | mov(16) g105<1>D 0D { align1 WE_all 1H I@2 }; mov(16) g64<1>D g9<8,8,1>D { align1 1H }; | mov(16) g105<1>D g9<8,8,1>D { align1 1H }; add(8) g64.1<2>D g64<8,4,2>D g64.1<8,4,2>D { align1 WE_all 1Q I@1 }; | add(8) g105.1<2>D g105<8,4,2>D g105.1<8,4,2>D { align1 WE_all 1Q I@1 }; add(4) g64.2<4>D g64.1<8,2,4>D g64.2<8,2,4>D { align1 WE_all 1N I@1 }; | add(4) g105.2<4>D g105.1<8,2,4>D g105.2<8,2,4>D { align1 WE_all 1N I@1 }; add(4) g64.3<4>D g64.1<8,2,4>D g64.3<8,2,4>D { align1 WE_all 1N I@1 }; | add(4) g105.3<4>D g105.1<8,2,4>D g105.3<8,2,4>D { align1 WE_all 1N I@1 }; add(4) g64.4<1>D g64.3<0,1,0>D g64.4<4,4,1>D { align1 WE_all 1N I@1 }; | add(4) g105.4<1>D g105.3<0,1,0>D g105.4<4,4,1>D { align1 WE_all 1N I@1 }; add(4) g65.4<1>D g65.3<0,1,0>D g65.4<4,4,1>D { align1 WE_all 1N I@2 }; | add(4) g106.4<1>D g106.3<0,1,0>D g106.4<4,4,1>D { align1 WE_all 1N I@2 }; add(8) g65<1>D g64.7<0,1,0>D g65<1,1,0>D { align1 WE_all 1Q I@1 compacted }; | add(8) g106<1>D g105.7<0,1,0>D g106<1,1,0>D { align1 WE_all 1Q I@1 compacted }; fbl(1) g66<1>UD mask0<0,1,0>UD { align1 WE_all 1N compacted }; | fbl(1) g107<1>UD mask0<0,1,0>UD { align1 WE_all 1N compacted }; mov(16) g68<1>D g89<8,8,1>UW { align1 1H }; | mov(16) g109<1>D g95<8,8,1>UW { align1 1H }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@1 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@1 }; cmp.z.f0.0(16) null<1>D g68<8,8,1>D g66<0,1,0>D { align1 1H }; | cmp.z.f0.0(16) null<1>D g109<8,8,1>D g107<0,1,0>D { align1 1H }; (+f0.0) if(16) JIP: LABEL7 UIP: LABEL7 { align1 1H }; (+f0.0) if(16) JIP: LABEL7 UIP: LABEL7 { align1 1H }; END B7 ->B8 ->B9 END B7 ->B8 ->B9 START B8 <-B7 (24 cycles) START B8 <-B7 (24 cycles) mov(16) g16<1>D 4D { align1 1H }; | mov(16) g42<1>D 4D { align1 1H F@7 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@6 }; | sync nop(1) null<0,1,0>UB { align1 WE_all 1N A@6 }; mov(16) g18<1>D g65.7<0,1,0>D { align1 1H }; | mov(16) g44<1>D g106.7<0,1,0>D { align1 1H }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@1 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@1 }; send(16) nullUD g16UD g18UD 0x6404050c 0x02000080 | send(16) nullUD g42UD g44UD 0x6404050c 0x02000080 ugm MsgDesc: ( atomic_add, a32, d32, V1, L1UC_L3WB dst_len = 0, src0_len = 2, src1_len = | ugm MsgDesc: ( atomic_add, a32, d32, V1, L1UC_L3WB dst_len = 0, src0_len = 2, src1_len = END B8 ->B9 END B8 ->B9 START B9 <-B8 <-B7 (24 cycles) START B9 <-B8 <-B7 (24 cycles) LABEL7: LABEL7: endif(16) JIP: LABEL8 { align1 1H }; endif(16) JIP: LABEL8 { align1 1H }; mov(16) g54<1>UD 0x3f800000UD { align1 1H }; | mov(16) g80<1>UD 0x3f800000UD { align1 1H F@3 }; mov(16) g52<1>UD 0x00000000UD { align1 1H F@4 }; | mov(16) g78<1>UD 0x00000000UD { align1 1H F@2 }; LABEL8: LABEL8: else(16) JIP: LABEL5 UIP: LABEL5 { align1 1H }; else(16) JIP: LABEL5 UIP: LABEL5 { align1 1H }; END B9 ->B10 ->B11 END B9 ->B10 ->B11 START B10 <-B6 <-B9 (8 cycles) START B10 <-B6 <-B9 (8 cycles) LABEL6: LABEL6: mov(16) g54<1>UD 0x00000000UD { align1 1H I@3 }; | mov(16) g80<1>UD 0x00000000UD { align1 1H A@3 }; mov(16) g52<1>UD 0x3f800000UD { align1 1H A@3 }; | mov(16) g78<1>UD 0x3f800000UD { align1 1H A@2 }; END B10 ->B11 END B10 ->B11 START B11 <-B10 <-B9 (2996 cycles) | START B11 <-B10 <-B9 (2962 cycles) LABEL5: LABEL5: endif(16) JIP: LABEL0 { align1 1H }; endif(16) JIP: LABEL0 { align1 1H }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N $9.src }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N $9.src }; mov(8) g19<1>D g5<8,8,1>D { align1 1Q $8.src }; | sync nop(1) null<0,1,0>UB { align1 WE_all 1N $10.src }; mov(8) g20<1>D g7<8,8,1>D { align1 1Q $8.src }; | mov(8) g45<1>D g5<8,8,1>D { align1 1Q F@7 }; mov(8) g21<1>D 1D { align1 1Q }; | sync nop(1) null<0,1,0>UB { align1 WE_all 1N $9.src }; mov(8) g22<1>D g52<8,8,1>D { align1 1Q I@5 }; | mov(8) g46<1>D g7<8,8,1>D { align1 1Q F@7 }; mov(8) g23<1>D g54<8,8,1>D { align1 1Q I@7 }; | mov(8) g47<1>D 1D { align1 1Q }; mov(8) g24<1>D 0D { align1 1Q }; | mov(8) g48<1>D g78<8,8,1>D { align1 1Q A@5 }; mov(8) g25<1>D 1065353216D { align1 1Q }; | mov(8) g49<1>D g80<8,8,1>D { align1 1Q A@5 }; > mov(8) g50<1>D 0D { align1 1Q F@5 }; > mov(8) g51<1>D 1065353216D { align1 1Q F@6 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@1 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@1 }; send(8) nullUD g19UD g22UD 0x06035003 0x00000100 | send(8) nullUD g45UD g48UD 0x06035003 0x00000100 dp data 1 MsgDesc: (DC typed surface write, Surface = 3, SIMD16, Mask = 0x0) mlen 3 ex_ml | dp data 1 MsgDesc: (DC typed surface write, Surface = 3, SIMD16, Mask = 0x0) mlen 3 ex_ml sync nop(1) null<0,1,0>UB { align1 WE_all 3N $10.src }; | sync nop(1) null<0,1,0>UB { align1 WE_all 3N $11.src }; mov(8) g23<1>D g6<8,8,1>D { align1 2Q $8.src }; | mov(8) g49<1>D g6<8,8,1>D { align1 2Q $9.src }; sync nop(1) null<0,1,0>UB { align1 WE_all 3N $10.src }; | sync nop(1) null<0,1,0>UB { align1 WE_all 3N $11.src }; mov(8) g24<1>D g8<8,8,1>D { align1 2Q $8.src }; | mov(8) g50<1>D g8<8,8,1>D { align1 2Q $9.src }; mov(8) g25<1>D 1D { align1 2Q $10.src }; | mov(8) g51<1>D 1D { align1 2Q $11.src }; mov(8) g26<1>D g53<8,8,1>D { align1 2Q }; | mov(8) g52<1>D g79<8,8,1>D { align1 2Q F@6 }; mov(8) g27<1>D g55<8,8,1>D { align1 2Q }; | mov(8) g53<1>D g81<8,8,1>D { align1 2Q }; mov(8) g28<1>D 0D { align1 2Q }; | mov(8) g54<1>D 0D { align1 2Q }; mov(8) g29<1>D 1065353216D { align1 2Q }; | mov(8) g55<1>D 1065353216D { align1 2Q }; sync nop(1) null<0,1,0>UB { align1 WE_all 3N I@1 }; sync nop(1) null<0,1,0>UB { align1 WE_all 3N I@1 }; send(8) nullUD g23UD g26UD 0x06036003 0x00000100 | send(8) nullUD g49UD g52UD 0x06036003 0x00000100 dp data 1 MsgDesc: (DC typed surface write, Surface = 3, SIMD8, Mask = 0x0) mlen 3 ex_mle | dp data 1 MsgDesc: (DC typed surface write, Surface = 3, SIMD8, Mask = 0x0) mlen 3 ex_mle sync nop(1) null<0,1,0>UB { align1 WE_all 1N $9.src }; | sync nop(1) null<0,1,0>UB { align1 WE_all 1N F@5 }; send(16) g11UD g5UD nullUD 0x0885a006 0x00000000 | send(16) g17UD g5UD nullUD 0x0885a006 0x00000000 sampler MsgDesc: ld_lz SIMD16 Surface = 6 Sampler = 0 mlen 4 ex_mlen 0 rlen 8 { align1 1H | sampler MsgDesc: ld_lz SIMD16 Surface = 6 Sampler = 0 mlen 4 ex_mlen 0 rlen 8 { align1 1H mov(16) g100<1>F g3.4<0,1,0>D { align1 1H F@5 compacted }; | mov(16) g27<1>F g3.4<0,1,0>D { align1 1H compacted }; mov(16) g103<1>F g3.5<0,1,0>D { align1 1H F@7 compacted }; | mov(16) g29<1>F g3.5<0,1,0>D { align1 1H compacted }; mov(16) g98<1>F g3.6<0,1,0>D { align1 1H F@7 compacted }; | mov(16) g31<1>F g3.6<0,1,0>D { align1 1H compacted }; mov(16) g96<1>F g3.7<0,1,0>D { align1 1H compacted }; | mov(16) g51<1>F g3.7<0,1,0>D { align1 1H $12.src compacted }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N $0.dst }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N $0.dst }; mov(16) g90<1>F g4<0,1,0>D { align1 1H compacted }; | mov(16) g37<1>F g4<0,1,0>D { align1 1H compacted }; mov(16) g92<1>F g4.1<0,1,0>D { align1 1H compacted }; | mov(16) g39<1>F g4.1<0,1,0>D { align1 1H compacted }; mov(16) g45<1>F g4.2<0,1,0>D { align1 1H compacted }; | mov(16) g41<1>F g4.2<0,1,0>D { align1 1H $10.src compacted }; mov(16) g57<1>F g4.3<0,1,0>D { align1 1H compacted }; | mov(16) g49<1>F g4.3<0,1,0>D { align1 1H $12.src compacted }; mov(16) g37<1>D (abs)g3.4<0,1,0>D { align1 1H F@7 }; | mov(16) g43<1>D (abs)g3.4<0,1,0>D { align1 1H $10.src }; mov(16) g39<1>D (abs)g1.2<0,1,0>D { align1 1H }; | mov(16) g45<1>D (abs)g1.2<0,1,0>D { align1 1H $11.src }; cmp.l.f0.0(16) g41<1>D g3.4<0,1,0>D 0D { align1 1H compacted }; | cmp.l.f0.0(16) g47<1>D g3.4<0,1,0>D 0D { align1 1H $11.src compacted }; mov(16) g81<1>D (abs)g1.2<0,1,0>D { align1 1H }; | mov(16) g87<1>D (abs)g1.2<0,1,0>D { align1 1H F@7 }; mov(16) g83<1>D (abs)g1.2<0,1,0>D { align1 1H }; | mov(16) g89<1>D (abs)g1.2<0,1,0>D { align1 1H }; mov(16) g65<1>D (abs)g1.2<0,1,0>D { align1 1H }; < mov(16) g47<1>D (abs)g3.5<0,1,0>D { align1 1H F@7 }; < mov(16) g67<1>D (abs)g1.2<0,1,0>D { align1 1H }; < mov(16) g49<1>D (abs)g3.6<0,1,0>D { align1 1H }; < mov(16) g69<1>D (abs)g1.2<0,1,0>D { align1 1H }; < mov(16) g51<1>D (abs)g3.7<0,1,0>D { align1 1H }; < mov(16) g71<1>D (abs)g1.2<0,1,0>D { align1 1H }; mov(16) g71<1>D (abs)g1.2<0,1,0>D { align1 1H }; mov(16) g53<1>D (abs)g4<0,1,0>D { align1 1H }; | mov(16) g53<1>D (abs)g3.5<0,1,0>D { align1 1H $12.src }; mov(16) g55<1>D (abs)g1.3<0,1,0>D { align1 1H }; | mov(16) g73<1>D (abs)g1.2<0,1,0>D { align1 1H }; mov(16) g85<1>D (abs)g1.3<0,1,0>D { align1 1H }; | mov(16) g55<1>D (abs)g3.6<0,1,0>D { align1 1H $12.src }; mov(16) g87<1>D (abs)g1.3<0,1,0>D { align1 1H }; | mov(16) g75<1>D (abs)g1.2<0,1,0>D { align1 1H F@7 }; mov(16) g73<1>D (abs)g1.3<0,1,0>D { align1 1H }; | mov(16) g57<1>D (abs)g3.7<0,1,0>D { align1 1H }; mov(16) g59<1>D (abs)g4.1<0,1,0>D { align1 1H }; | mov(16) g77<1>D (abs)g1.2<0,1,0>D { align1 1H F@7 }; mov(16) g75<1>D (abs)g1.3<0,1,0>D { align1 1H }; | mov(16) g59<1>D (abs)g4<0,1,0>D { align1 1H }; mov(16) g61<1>D (abs)g4.2<0,1,0>D { align1 1H }; | mov(16) g61<1>D (abs)g1.3<0,1,0>D { align1 1H }; mov(16) g77<1>D (abs)g1.3<0,1,0>D { align1 1H }; | mov(16) g91<1>D (abs)g1.3<0,1,0>D { align1 1H }; mov(16) g63<1>D (abs)g4.3<0,1,0>D { align1 1H }; | mov(16) g93<1>D (abs)g1.3<0,1,0>D { align1 1H }; mov(16) g79<1>D (abs)g1.3<0,1,0>D { align1 1H }; mov(16) g79<1>D (abs)g1.3<0,1,0>D { align1 1H }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N $10.src }; | mov(16) g65<1>D (abs)g4.1<0,1,0>D { align1 1H }; mul(16) g19<1>F g100<1,1,0>F g94<1,1,0>F { align1 1H F@7 compacted }; | mov(16) g81<1>D (abs)g1.3<0,1,0>D { align1 1H }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N $10.src }; | mov(16) g67<1>D (abs)g4.2<0,1,0>D { align1 1H }; mul(16) g21<1>F g103<1,1,0>F g94<1,1,0>F { align1 1H F@7 compacted }; | mov(16) g83<1>D (abs)g1.3<0,1,0>D { align1 1H F@7 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N $11.src }; | mov(16) g69<1>D (abs)g4.3<0,1,0>D { align1 1H }; mul(16) g23<1>F g98<1,1,0>F g94<1,1,0>F { align1 1H F@7 compacted }; | mov(16) g85<1>D (abs)g1.3<0,1,0>D { align1 1H F@7 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N $11.src }; | mul(16) g25<1>F g27<1,1,0>F g35<1,1,0>F { align1 1H F@7 compacted }; mul(16) g25<1>F g96<1,1,0>F g94<1,1,0>F { align1 1H F@7 compacted }; | mov(16) g63<1>F g61<1,1,0>UD { align1 1H I@7 compacted }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N $11.src }; | mul(16) g27<1>F g29<1,1,0>F g35<1,1,0>F { align1 1H F@7 compacted }; mul(16) g29<1>F g90<1,1,0>F g43<1,1,0>F { align1 1H F@7 compacted }; | mul(16) g29<1>F g31<1,1,0>F g35<1,1,0>F { align1 1H F@7 compacted }; mul(16) g31<1>F g92<1,1,0>F g43<1,1,0>F { align1 1H F@7 compacted }; | mul(16) g31<1>F g51<1,1,0>F g35<1,1,0>F { align1 1H F@7 compacted }; mul(16) g33<1>F g45<1,1,0>F g43<1,1,0>F { align1 1H F@7 compacted }; | mov(16) g51<1>F g45<1,1,0>UD { align1 1H compacted }; mul(16) g35<1>F g57<1,1,0>F g43<1,1,0>F { align1 1H F@7 compacted }; | mul(16) g35<1>F g37<1,1,0>F g33<1,1,0>F { align1 1H F@2 compacted }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N $11.src }; | mul(16) g37<1>F g39<1,1,0>F g33<1,1,0>F { align1 1H F@7 compacted }; mov(16) g27<1>D g19<1,1,0>F { align1 1H F@7 compacted }; | mul(16) g39<1>F g41<1,1,0>F g33<1,1,0>F { align1 1H F@7 compacted }; mov(16) g45<1>F g39<1,1,0>UD { align1 1H compacted }; | mul(16) g41<1>F g49<1,1,0>F g33<1,1,0>F { align1 1H F@7 compacted }; mov(16) g57<1>F g55<1,1,0>UD { align1 1H compacted }; | cmp.l.f0.0(16) g49<1>D g1.2<0,1,0>D 0D { align1 1H F@1 compacted }; cmp.l.f0.0(16) g43<1>D g1.2<0,1,0>D 0D { align1 1H F@3 compacted }; | mov(16) g33<1>D g25<1,1,0>F { align1 1H F@1 compacted }; mov(16) g19<1>D g21<1,1,0>F { align1 1H F@7 compacted }; | mov(16) g25<1>D g27<1,1,0>F { align1 1H F@7 compacted }; mov(16) g21<1>D g23<1,1,0>F { align1 1H F@7 compacted }; | mov(16) g27<1>D g29<1,1,0>F { align1 1H F@7 compacted }; mov(16) g23<1>D g25<1,1,0>F { align1 1H F@7 compacted }; | mov(16) g29<1>D g31<1,1,0>F { align1 1H F@6 compacted }; mov(16) g25<1>D g29<1,1,0>F { align1 1H F@6 compacted }; | mov(16) g31<1>D g35<1,1,0>F { align1 1H F@4 compacted }; mov(16) g29<1>D g31<1,1,0>F { align1 1H F@5 compacted }; | mov(16) g35<1>D g37<1,1,0>F { align1 1H F@3 compacted }; mov(16) g31<1>D g33<1,1,0>F { align1 1H F@4 compacted }; | mov(16) g37<1>D g39<1,1,0>F { align1 1H F@2 compacted }; mov(16) g33<1>D g35<1,1,0>F { align1 1H F@3 compacted }; | mov(16) g39<1>D g41<1,1,0>F { align1 1H F@1 compacted }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N A@1 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N A@1 }; math inv(16) g35<1>F g45<8,8,1>F null<8,8,1>F { align1 1H $13 }; | math inv(16) g41<1>F g51<8,8,1>F null<8,8,1>F { align1 1H $14 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N $13.src }; < xor(16) g45<1>UD g41<1,1,0>UD g43<1,1,0>UD { align1 1H I@7 compacted }; < sync nop(1) null<0,1,0>UB { align1 WE_all 1N A@1 }; < math inv(16) g41<1>F g57<8,8,1>F null<8,8,1>F { align1 1H $14 }; < sync nop(1) null<0,1,0>UB { align1 WE_all 1N $14.src }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N $14.src }; add(16) g57<1>D g11<1,1,0>D -g27<1,1,0>D { align1 1H @7 $12.dst compacted }; | xor(16) g51<1>UD g47<1,1,0>UD g49<1,1,0>UD { align1 1H I@7 compacted }; add(16) g27<1>D g19<1,1,0>D -84D { align1 1H I@7 compacted }; | sync nop(1) null<0,1,0>UB { align1 WE_all 1N A@1 }; add(16) g19<1>D g21<1,1,0>D -32D { align1 1H I@7 compacted }; | math inv(16) g47<1>F g63<8,8,1>F null<8,8,1>F { align1 1H $15 }; add(16) g21<1>D g23<1,1,0>D -99D { align1 1H I@7 compacted }; | sync nop(1) null<0,1,0>UB { align1 WE_all 1N $15.src }; add(16) g23<1>D g11<1,1,0>D -g25<1,1,0>D { align1 1H I@7 compacted }; | add(16) g63<1>D g17<1,1,0>D -g33<1,1,0>D { align1 1H @7 $13.dst compacted }; add(16) g25<1>D g29<1,1,0>D -84D { align1 1H I@7 compacted }; | add3(16) g33<1>D g19<8,8,1>D g25<8,8,1>D g11<1,1,1>D { align1 1H @7 $13.dst }; add(16) g29<1>D g31<1,1,0>D -32D { align1 1H I@7 compacted }; | mul(16) g110<1>F g41<8,8,1>F 0x4f7ffffeF /* 4.29497e+09F */ { align1 1H $14.dst }; add(16) g31<1>D g33<1,1,0>D -99D { align1 1H I@7 compacted }; | add3(16) g25<1>D g21<8,8,1>D g27<8,8,1>D g13<1,1,1>D { align1 1H @7 $13.dst }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N $13.dst }; | add3(16) g27<1>D g23<8,8,1>D g29<8,8,1>D g15<1,1,1>D { align1 1H @7 $13.dst }; mul(16) g33<1>F g35<8,8,1>F 0x4f7ffffeF /* 4.29497e+09F */ { align1 1H I@1 }; < mul(16) g35<1>F g41<8,8,1>F 0x4f7ffffeF /* 4.29497e+09F */ { align1 1H $14.dst }; < sync nop(1) null<0,1,0>UB { align1 WE_all 1N $12.dst }; < add(16) g41<1>D g13<1,1,0>D -g27<1,1,0>D { align1 1H A@1 compacted }; < add(16) g27<1>D g15<1,1,0>D -g19<1,1,0>D { align1 1H @7 $12.dst compacted }; < add(16) g19<1>D g17<1,1,0>D -g21<1,1,0>D { align1 1H @7 $12.dst compacted }; < mov(16) g104<1>UD g33<8,8,1>F { align1 1H F@2 }; < add(16) g21<1>D g13<1,1,0>D -g25<1,1,0>D { align1 1H I@7 compacted }; < mov(16) g99<1>UD g35<8,8,1>F { align1 1H F@1 }; < add(16) g25<1>D g15<1,1,0>D -g29<1,1,0>D { align1 1H I@7 compacted }; < add(16) g29<1>D g17<1,1,0>D -g31<1,1,0>D { align1 1H I@7 compacted }; add(16) g29<1>D g17<1,1,0>D -g31<1,1,0>D { align1 1H I@7 compacted }; mul(16) g101<1>D g81<8,8,1>D g104<16,8,2>UW { align1 1H I@5 }; | mov(16) g112<1>UD g110<8,8,1>F { align1 1H F@1 }; mul(16) g81<1>D g83<8,8,1>D g104.1<16,8,2>UW { align1 1H }; | sync nop(1) null<0,1,0>UB { align1 WE_all 1N $15.dst }; mul(16) g108<1>D g85<8,8,1>D g99<16,8,2>UW { align1 1H I@5 }; | mul(16) g17<1>F g47<8,8,1>F 0x4f7ffffeF /* 4.29497e+09F */ { align1 1H I@2 }; mul(16) g90<1>D g87<8,8,1>D g99.1<16,8,2>UW { align1 1H F@7 }; | add3(16) g31<1>D g19<8,8,1>D g35<8,8,1>D g11<1,1,1>D { align1 1H I@7 }; add(16) g101.1<2>UW g101.1<16,8,2>UW g81<16,8,2>UW { align1 1H I@3 }; | add3(16) g11<1>D g21<8,8,1>D g37<8,8,1>D g13<1,1,1>D { align1 1H I@7 }; add(16) g108.1<2>UW g108.1<16,8,2>UW g90<16,8,2>UW { align1 1H I@2 }; | mul(16) g114<1>D g87<8,8,1>D g112<16,8,2>UW { align1 1H I@3 }; mov(16) g106<1>D -g101<8,8,1>D { align1 1H I@2 }; | mul(16) g96<1>D g89<8,8,1>D g112.1<16,8,2>UW { align1 1H }; mov(16) g101<1>D -g108<8,8,1>D { align1 1H I@2 }; | add3(16) g13<1>D g23<8,8,1>D g39<8,8,1>D g15<1,1,1>D { align1 1H }; mul(8) acc0<1>UD g104<8,8,1>UD g106<16,8,2>UW { align1 1Q I@2 }; | mov(16) g15<1>UD g17<8,8,1>F { align1 1H F@1 }; mach(8) g108<1>UD g104<1,1,0>UD g106<1,1,0>UD { align1 1Q compacted AccWrEnable }; | add(16) g114.1<2>UW g114.1<16,8,2>UW g96<16,8,2>UW { align1 1H I@3 }; mul(8) acc0<1>UD g105<8,8,1>UD g107<16,8,2>UW { align1 2Q I@4 }; | mul(16) g19<1>D g91<8,8,1>D g15<16,8,2>UW { align1 1H I@2 }; mach(8) g109<1>UD g105<8,8,1>UD g107<8,8,1>UD { align1 2Q AccWrEnable }; | mul(16) g104<1>D g93<8,8,1>D g15.1<16,8,2>UW { align1 1H }; add(16) g106<1>D g104<1,1,0>D g108<1,1,0>D { align1 1H I@1 compacted }; | mov(16) g116<1>D -g114<8,8,1>D { align1 1H I@3 }; mul(8) acc0<1>UD g37<8,8,1>UD g106<16,8,2>UW { align1 1Q I@1 }; | add(16) g19.1<2>UW g19.1<16,8,2>UW g104<16,8,2>UW { align1 1H I@2 }; mach(8) g112<1>UD g37<1,1,0>UD g106<1,1,0>UD { align1 1Q compacted AccWrEnable }; | mul(8) acc0<1>UD g112<8,8,1>UD g116<16,8,2>UW { align1 1Q I@2 }; mul(8) acc0<1>UD g38<8,8,1>UD g107<16,8,2>UW { align1 2Q I@3 }; | mov(16) g17<1>D -g19<8,8,1>D { align1 1H I@2 }; mach(8) g113<1>UD g38<8,8,1>UD g107<8,8,1>UD { align1 2Q AccWrEnable }; | mach(8) g118<1>UD g112<1,1,0>UD g116<1,1,0>UD { align1 1Q compacted AccWrEnable }; mul(16) g114<1>D g112<8,8,1>D g65<16,8,2>UW { align1 1H I@1 }; | mul(8) acc0<1>UD g113<8,8,1>UD g117<16,8,2>UW { align1 2Q I@5 }; mul(16) g82<1>D g112<8,8,1>D g65.1<16,8,2>UW { align1 1H }; | mach(8) g119<1>UD g113<8,8,1>UD g117<8,8,1>UD { align1 2Q AccWrEnable }; add(16) g118<1>D g112<1,1,0>D 1D { align1 1H compacted }; | add(16) g20<1>D g112<1,1,0>D g118<1,1,0>D { align1 1H I@1 compacted }; mul(8) acc0<1>UD g47<8,8,1>UD g106<16,8,2>UW { align1 1Q }; | mul(8) acc0<1>UD g43<8,8,1>UD g20<16,8,2>UW { align1 1Q I@1 }; add(16) g114.1<2>UW g114.1<16,8,2>UW g82<16,8,2>UW { align1 1H I@3 }; | mach(8) g119<1>UD g43<1,1,0>UD g20<1,1,0>UD { align1 1Q compacted AccWrEnable }; mach(8) g110<1>UD g47<1,1,0>UD g106<1,1,0>UD { align1 1Q compacted AccWrEnable }; | mul(8) acc0<1>UD g44<8,8,1>UD g21<16,8,2>UW { align1 2Q I@3 }; add(16) g116<1>D (abs)g3.4<0,1,0>D -g114<1,1,0>D { align1 1H I@2 compacted }; | sync nop(1) null<0,1,0>UB { align1 WE_all 3N $2.src }; mul(8) acc0<1>UD g48<8,8,1>UD g107<16,8,2>UW { align1 2Q }; | mach(8) g120<1>UD g44<8,8,1>UD g21<8,8,1>UD { align1 2Q AccWrEnable }; cmp.ge.f0.0(16) null<1>UD g116<8,8,1>UD g39<8,8,1>UD { align1 1H I@2 }; | mul(16) g121<1>D g119<8,8,1>D g71<16,8,2>UW { align1 1H I@1 }; add(16) g123<1>D g116<1,1,0>D -(abs)g1.2<0,1,0>D { align1 1H compacted }; | mul(16) g97<1>D g119<8,8,1>D g71.1<16,8,2>UW { align1 1H }; mach(8) g111<1>UD g48<8,8,1>UD g107<8,8,1>UD { align1 2Q AccWrEnable }; | add(16) g125<1>D g119<1,1,0>D 1D { align1 1H compacted }; (+f0.0) sel(16) g121<1>UD g118<1,1,0>UD g112<1,1,0>UD { align1 1H I@7 compacted }; | mul(8) acc0<1>UD g53<8,8,1>UD g20<16,8,2>UW { align1 1Q }; (+f0.0) sel(16) g125<1>UD g123<1,1,0>UD g116<1,1,0>UD { align1 1H I@3 compacted }; | add(16) g121.1<2>UW g121.1<16,8,2>UW g97<16,8,2>UW { align1 1H I@3 }; mul(16) g31<1>D g110<8,8,1>D g67<16,8,2>UW { align1 1H I@3 }; | mach(8) g35<1>UD g53<1,1,0>UD g20<1,1,0>UD { align1 1Q compacted AccWrEnable }; mul(16) g83<1>D g110<8,8,1>D g67.1<16,8,2>UW { align1 1H }; | add(16) g123<1>D (abs)g3.4<0,1,0>D -g121<1,1,0>D { align1 1H I@2 compacted }; add(16) g114<1>D g110<1,1,0>D 1D { align1 1H compacted }; | mul(8) acc0<1>UD g54<8,8,1>UD g21<16,8,2>UW { align1 2Q }; mul(8) acc0<1>UD g49<8,8,1>UD g106<16,8,2>UW { align1 1Q }; | cmp.ge.f0.0(16) null<1>UD g123<8,8,1>UD g45<8,8,1>UD { align1 1H I@2 }; add(16) g11<1>D g121<1,1,0>D 1D { align1 1H I@6 compacted }; | add(16) g37<1>D g123<1,1,0>D -(abs)g1.2<0,1,0>D { align1 1H compacted }; cmp.ge.f0.0(16) null<1>UD g125<8,8,1>UD g39<8,8,1>UD { align1 1H I@6 }; | mach(8) g36<1>UD g54<8,8,1>UD g21<8,8,1>UD { align1 2Q AccWrEnable }; add(16) g31.1<2>UW g31.1<16,8,2>UW g83<16,8,2>UW { align1 1H I@5 }; | (+f0.0) sel(16) g22<1>UD g125<1,1,0>UD g119<1,1,0>UD { align1 1H I@7 compacted }; mach(8) g119<1>UD g49<1,1,0>UD g106<1,1,0>UD { align1 1Q compacted AccWrEnable }; | (+f0.0) sel(16) g41<1>UD g37<1,1,0>UD g123<1,1,0>UD { align1 1H A@2 compacted }; (+f0.0) sel(16) g13<1>UD g11<1,1,0>UD g121<1,1,0>UD { align1 1H I@4 compacted }; | mul(16) g87<1>D g35<8,8,1>D g73<16,8,2>UW { align1 1H I@3 }; add(16) g112<1>D (abs)g3.5<0,1,0>D -g31<1,1,0>D { align1 1H I@3 compacted }; | mul(16) g98<1>D g35<8,8,1>D g73.1<16,8,2>UW { align1 1H }; mul(8) acc0<1>UD g50<8,8,1>UD g107<16,8,2>UW { align1 2Q }; | add(16) g39<1>D g35<1,1,0>D 1D { align1 1H compacted }; cmp.nz.f0.0(16) null<1>D g45<8,8,1>D 0D { align1 1H }; | mul(8) acc0<1>UD g55<8,8,1>UD g20<16,8,2>UW { align1 1Q }; add(16) g116<1>D g112<1,1,0>D -(abs)g1.2<0,1,0>D { align1 1H I@3 compacted }; | add(16) g43<1>D g22<1,1,0>D 1D { align1 1H I@6 compacted }; mach(8) g120<1>UD g50<8,8,1>UD g107<8,8,1>UD { align1 2Q AccWrEnable }; | cmp.ge.f0.0(16) null<1>UD g41<8,8,1>UD g45<8,8,1>UD { align1 1H I@6 }; (+f0.0) sel(16) g108<1>D -g13<1,1,0>D g13<1,1,0>D { align1 1H I@6 compacted }; | add(16) g87.1<2>UW g87.1<16,8,2>UW g98<16,8,2>UW { align1 1H I@5 }; mul(16) g49<1>D g119<8,8,1>D g69<16,8,2>UW { align1 1H I@2 }; | mach(8) g47<1>UD g55<1,1,0>UD g20<1,1,0>UD { align1 1Q F@1 compacted AccWrEnable }; mul(16) g84<1>D g119<8,8,1>D g69.1<16,8,2>UW { align1 1H }; | (+f0.0) sel(16) g53<1>UD g43<1,1,0>UD g22<1,1,0>UD { align1 1H I@4 compacted }; add(16) g123<1>D g119<1,1,0>D 1D { align1 1H compacted }; | add(16) g37<1>D (abs)g3.5<0,1,0>D -g87<1,1,0>D { align1 1H I@3 compacted }; mul(8) acc0<1>UD g51<8,8,1>UD g106<16,8,2>UW { align1 1Q }; | mul(8) acc0<1>UD g56<8,8,1>UD g21<16,8,2>UW { align1 2Q }; cmp.l.f0.0(16) g14<1>D g3.5<0,1,0>D 0D { align1 1H compacted }; | cmp.nz.f0.0(16) null<1>D g51<8,8,1>D 0D { align1 1H }; cmp.ge.f0.0(16) null<1>UD g112<8,8,1>UD g39<8,8,1>UD { align1 1H }; | add(16) g41<1>D g37<1,1,0>D -(abs)g1.2<0,1,0>D { align1 1H I@3 compacted }; add(16) g49.1<2>UW g49.1<16,8,2>UW g84<16,8,2>UW { align1 1H I@5 }; | mach(8) g48<1>UD g56<8,8,1>UD g21<8,8,1>UD { align1 2Q F@1 AccWrEnable }; mach(8) g11<1>UD g51<1,1,0>UD g106<1,1,0>UD { align1 1Q compacted AccWrEnable }; | (+f0.0) sel(16) g22<1>D -g53<1,1,0>D g53<1,1,0>D { align1 1H I@6 compacted }; xor(16) g17<1>UD g14<1,1,0>UD g43<1,1,0>UD { align1 1H I@4 compacted }; | add(16) g53<1>D g47<1,1,0>D 1D { align1 1H I@2 compacted }; (+f0.0) sel(16) g32<1>UD g114<1,1,0>UD g110<1,1,0>UD { align1 1H compacted }; | mul(16) g100<1>D g47<8,8,1>D g75<16,8,2>UW { align1 1H }; (+f0.0) sel(16) g34<1>UD g116<1,1,0>UD g112<1,1,0>UD { align1 1H compacted }; | mul(16) g102<1>D g47<8,8,1>D g75.1<16,8,2>UW { align1 1H }; add(16) g121<1>D (abs)g3.6<0,1,0>D -g49<1,1,0>D { align1 1H I@5 compacted }; | mul(8) acc0<1>UD g57<8,8,1>UD g20<16,8,2>UW { align1 1Q }; mul(8) acc0<1>UD g52<8,8,1>UD g107<16,8,2>UW { align1 2Q }; | cmp.l.f0.0(16) g55<1>D g3.5<0,1,0>D 0D { align1 1H compacted }; add(16) g36<1>D g32<1,1,0>D 1D { align1 1H I@4 compacted }; | cmp.ge.f0.0(16) null<1>UD g37<8,8,1>UD g45<8,8,1>UD { align1 1H }; cmp.ge.f0.0(16) null<1>UD g34<8,8,1>UD g39<8,8,1>UD { align1 1H I@4 }; | add(16) g100.1<2>UW g100.1<16,8,2>UW g102<16,8,2>UW { align1 1H I@4 }; add(16) g125<1>D g121<1,1,0>D -(abs)g1.2<0,1,0>D { align1 1H I@4 compacted }; | mach(8) g71<1>UD g57<1,1,0>UD g20<1,1,0>UD { align1 1Q compacted AccWrEnable }; mach(8) g12<1>UD g52<8,8,1>UD g107<8,8,1>UD { align1 2Q AccWrEnable }; | xor(16) g73<1>UD g55<1,1,0>UD g49<1,1,0>UD { align1 1H I@4 compacted }; (+f0.0) sel(16) g45<1>UD g36<1,1,0>UD g32<1,1,0>UD { align1 1H I@4 compacted }; | (+f0.0) sel(16) g88<1>UD g39<1,1,0>UD g35<1,1,0>UD { align1 1H compacted }; mul(16) g81<1>D g11<8,8,1>D g71<16,8,2>UW { align1 1H I@2 }; | (+f0.0) sel(16) g90<1>UD g41<1,1,0>UD g37<1,1,0>UD { align1 1H compacted }; mul(16) g85<1>D g11<8,8,1>D g71.1<16,8,2>UW { align1 1H }; | add(16) g51<1>D (abs)g3.6<0,1,0>D -g100<1,1,0>D { align1 1H I@5 compacted }; add(16) g15<1>D g11<1,1,0>D 1D { align1 1H compacted }; | mul(8) acc0<1>UD g58<8,8,1>UD g21<16,8,2>UW { align1 2Q }; mul(8) acc0<1>UD g99<8,8,1>UD g101<16,8,2>UW { align1 1Q }; | add(16) g92<1>D g88<1,1,0>D 1D { align1 1H I@4 compacted }; cmp.nz.f0.0(16) null<1>D g17<8,8,1>D 0D { align1 1H }; | cmp.ge.f0.0(16) null<1>UD g90<8,8,1>UD g45<8,8,1>UD { align1 1H I@4 }; add(16) g81.1<2>UW g81.1<16,8,2>UW g85<16,8,2>UW { align1 1H I@4 }; | add(16) g55<1>D g51<1,1,0>D -(abs)g1.2<0,1,0>D { align1 1H I@4 compacted }; mach(8) g110<1>UD g99<1,1,0>UD g101<1,1,0>UD { align1 1Q compacted AccWrEnable }; | mach(8) g72<1>UD g58<8,8,1>UD g21<8,8,1>UD { align1 2Q AccWrEnable }; (+f0.0) sel(16) g117<1>D -g45<1,1,0>D g45<1,1,0>D { align1 1H I@7 compacted }; | (+f0.0) sel(16) g96<1>UD g92<1,1,0>UD g88<1,1,0>UD { align1 1H I@4 compacted }; add(16) g13<1>D (abs)g3.7<0,1,0>D -g81<1,1,0>D { align1 1H I@3 compacted }; | mul(16) g111<1>D g71<8,8,1>D g77<16,8,2>UW { align1 1H I@2 }; mul(8) acc0<1>UD g100<8,8,1>UD g102<16,8,2>UW { align1 2Q }; | mul(16) g103<1>D g71<8,8,1>D g77.1<16,8,2>UW { align1 1H }; cmp.l.f0.0(16) g46<1>D g3.6<0,1,0>D 0D { align1 1H compacted }; | add(16) g75<1>D g71<1,1,0>D 1D { align1 1H compacted }; cmp.ge.f0.0(16) null<1>UD g121<8,8,1>UD g39<8,8,1>UD { align1 1H }; | mul(8) acc0<1>UD g15<8,8,1>UD g17<16,8,2>UW { align1 1Q }; add(16) g17<1>D g13<1,1,0>D -(abs)g1.2<0,1,0>D { align1 1H I@4 compacted }; | cmp.nz.f0.0(16) null<1>D g73<8,8,1>D 0D { align1 1H }; mach(8) g111<1>UD g100<8,8,1>UD g102<8,8,1>UD { align1 2Q AccWrEnable }; | add(16) g111.1<2>UW g111.1<16,8,2>UW g103<16,8,2>UW { align1 1H I@4 }; xor(16) g48<1>UD g46<1,1,0>UD g43<1,1,0>UD { align1 1H I@4 compacted }; | mach(8) g20<1>UD g15<1,1,0>UD g17<1,1,0>UD { align1 1Q compacted AccWrEnable }; (+f0.0) sel(16) g50<1>UD g123<1,1,0>UD g119<1,1,0>UD { align1 1H compacted }; | (+f0.0) sel(16) g42<1>D -g96<1,1,0>D g96<1,1,0>D { align1 1H I@7 compacted }; (+f0.0) sel(16) g65<1>UD g125<1,1,0>UD g121<1,1,0>UD { align1 1H compacted }; | add(16) g73<1>D (abs)g3.7<0,1,0>D -g111<1,1,0>D { align1 1H I@3 compacted }; add(16) g31<1>D g99<1,1,0>D g110<1,1,0>D { align1 1H I@4 compacted }; | mul(8) acc0<1>UD g16<8,8,1>UD g18<16,8,2>UW { align1 2Q }; add(16) g67<1>D g50<1,1,0>D 1D { align1 1H I@3 compacted }; | cmp.l.f0.0(16) g97<1>D g3.6<0,1,0>D 0D { align1 1H compacted }; cmp.ge.f0.0(16) null<1>UD g65<8,8,1>UD g39<8,8,1>UD { align1 1H I@3 }; | cmp.ge.f0.0(16) null<1>UD g51<8,8,1>UD g45<8,8,1>UD { align1 1H }; mul(8) acc0<1>UD g53<8,8,1>UD g31<16,8,2>UW { align1 1Q I@3 }; | add(16) g77<1>D g73<1,1,0>D -(abs)g1.2<0,1,0>D { align1 1H I@4 compacted }; (+f0.0) sel(16) g69<1>UD g67<1,1,0>UD g50<1,1,0>UD { align1 1H I@3 compacted }; | mach(8) g21<1>UD g16<8,8,1>UD g18<8,8,1>UD { align1 2Q AccWrEnable }; mach(8) g33<1>UD g53<1,1,0>UD g31<1,1,0>UD { align1 1Q compacted AccWrEnable }; | xor(16) g99<1>UD g97<1,1,0>UD g49<1,1,0>UD { align1 1H I@4 compacted }; cmp.nz.f0.0(16) null<1>D g48<8,8,1>D 0D { align1 1H I@7 }; | (+f0.0) sel(16) g101<1>UD g53<1,1,0>UD g47<1,1,0>UD { align1 1H compacted }; mul(8) acc0<1>UD g54<8,8,1>UD g32<16,8,2>UW { align1 2Q I@7 }; | (+f0.0) sel(16) g103<1>UD g55<1,1,0>UD g51<1,1,0>UD { align1 1H compacted }; (+f0.0) sel(16) g126<1>D -g69<1,1,0>D g69<1,1,0>D { align1 1H I@4 compacted }; | add(16) g87<1>D g15<1,1,0>D g20<1,1,0>D { align1 1H I@4 compacted }; mach(8) g34<1>UD g54<8,8,1>UD g32<8,8,1>UD { align1 2Q AccWrEnable }; | sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@3 }; cmp.l.f0.0(16) g70<1>D g3.7<0,1,0>D 0D { align1 1H compacted }; | add(16) g105<1>D g101<1,1,0>D 1D { align1 1H compacted }; mul(16) g111<1>D g33<8,8,1>D g73<16,8,2>UW { align1 1H I@2 }; | cmp.ge.f0.0(16) null<1>UD g103<8,8,1>UD g45<8,8,1>UD { align1 1H I@3 }; mul(16) g91<1>D g33<8,8,1>D g73.1<16,8,2>UW { align1 1H F@7 }; | mul(8) acc0<1>UD g59<8,8,1>UD g87<16,8,2>UW { align1 1Q I@3 }; add(16) g37<1>D g33<1,1,0>D 1D { align1 1H compacted }; | (+f0.0) sel(16) g107<1>UD g105<1,1,0>UD g101<1,1,0>UD { align1 1H I@3 compacted }; mul(8) acc0<1>UD g59<8,8,1>UD g31<16,8,2>UW { align1 1Q }; | mach(8) g89<1>UD g59<1,1,0>UD g87<1,1,0>UD { align1 1Q compacted AccWrEnable }; cmp.ge.f0.0(16) null<1>UD g13<8,8,1>UD g39<8,8,1>UD { align1 1H }; | cmp.nz.f0.0(16) null<1>D g99<8,8,1>D 0D { align1 1H I@7 }; xor(16) g72<1>UD g70<1,1,0>UD g43<1,1,0>UD { align1 1H I@6 compacted }; | mul(8) acc0<1>UD g60<8,8,1>UD g88<16,8,2>UW { align1 2Q I@7 }; add(16) g111.1<2>UW g111.1<16,8,2>UW g91<16,8,2>UW { align1 1H I@5 }; | (+f0.0) sel(16) g56<1>D -g107<1,1,0>D g107<1,1,0>D { align1 1H I@4 compacted }; mach(8) g45<1>UD g59<1,1,0>UD g31<1,1,0>UD { align1 1Q compacted AccWrEnable }; | mach(8) g90<1>UD g60<8,8,1>UD g88<8,8,1>UD { align1 2Q AccWrEnable }; (+f0.0) sel(16) g82<1>UD g15<1,1,0>UD g11<1,1,0>UD { align1 1H compacted }; | cmp.l.f0.0(16) g108<1>D g3.7<0,1,0>D 0D { align1 1H compacted }; (+f0.0) sel(16) g84<1>UD g17<1,1,0>UD g13<1,1,0>UD { align1 1H compacted }; | mul(16) g35<1>D g89<8,8,1>D g79<16,8,2>UW { align1 1H I@2 }; add(16) g35<1>D (abs)g4<0,1,0>D -g111<1,1,0>D { align1 1H I@4 compacted }; | mul(16) g105<1>D g89<8,8,1>D g79.1<16,8,2>UW { align1 1H }; mul(8) acc0<1>UD g60<8,8,1>UD g32<16,8,2>UW { align1 2Q }; | add(16) g93<1>D g89<1,1,0>D 1D { align1 1H compacted }; add(16) g86<1>D g82<1,1,0>D 1D { align1 1H I@4 compacted }; | mul(8) acc0<1>UD g65<8,8,1>UD g87<16,8,2>UW { align1 1Q }; cmp.ge.f0.0(16) null<1>UD g84<8,8,1>UD g39<8,8,1>UD { align1 1H I@4 }; | cmp.ge.f0.0(16) null<1>UD g73<8,8,1>UD g45<8,8,1>UD { align1 1H }; add(16) g43<1>D g35<1,1,0>D -(abs)g1.3<0,1,0>D { align1 1H I@4 compacted }; | xor(16) g110<1>UD g108<1,1,0>UD g49<1,1,0>UD { align1 1H I@6 compacted }; mach(8) g46<1>UD g60<8,8,1>UD g32<8,8,1>UD { align1 2Q AccWrEnable }; | add(16) g35.1<2>UW g35.1<16,8,2>UW g105<16,8,2>UW { align1 1H I@5 }; (+f0.0) sel(16) g90<1>UD g86<1,1,0>UD g82<1,1,0>UD { align1 1H I@4 compacted }; | mach(8) g98<1>UD g65<1,1,0>UD g87<1,1,0>UD { align1 1Q compacted AccWrEnable }; mul(16) g12<1>D g45<8,8,1>D g75<16,8,2>UW { align1 1H I@2 }; | (+f0.0) sel(16) g112<1>UD g75<1,1,0>UD g71<1,1,0>UD { align1 1H compacted }; mul(16) g92<1>D g45<8,8,1>D g75.1<16,8,2>UW { align1 1H F@7 }; | (+f0.0) sel(16) g114<1>UD g77<1,1,0>UD g73<1,1,0>UD { align1 1H compacted }; add(16) g49<1>D g45<1,1,0>D 1D { align1 1H compacted }; | add(16) g91<1>D (abs)g4<0,1,0>D -g35<1,1,0>D { align1 1H I@4 compacted }; mul(8) acc0<1>UD g61<8,8,1>UD g31<16,8,2>UW { align1 1Q }; | mul(8) acc0<1>UD g66<8,8,1>UD g88<16,8,2>UW { align1 2Q }; cmp.nz.f0.0(16) null<1>D g72<8,8,1>D 0D { align1 1H }; | add(16) g116<1>D g112<1,1,0>D 1D { align1 1H I@4 compacted }; add(16) g12.1<2>UW g12.1<16,8,2>UW g92<16,8,2>UW { align1 1H I@4 }; | cmp.ge.f0.0(16) null<1>UD g114<8,8,1>UD g45<8,8,1>UD { align1 1H I@4 }; mach(8) g53<1>UD g61<1,1,0>UD g31<1,1,0>UD { align1 1Q compacted AccWrEnable }; | add(16) g96<1>D g91<1,1,0>D -(abs)g1.3<0,1,0>D { align1 1H I@4 compacted }; (+f0.0) sel(16) g92<1>D -g90<1,1,0>D g90<1,1,0>D { align1 1H I@7 compacted }; | mach(8) g99<1>UD g66<8,8,1>UD g88<8,8,1>UD { align1 2Q AccWrEnable }; add(16) g47<1>D (abs)g4.1<0,1,0>D -g12<1,1,0>D { align1 1H I@3 compacted }; | (+f0.0) sel(16) g118<1>UD g116<1,1,0>UD g112<1,1,0>UD { align1 1H I@4 compacted }; mul(8) acc0<1>UD g62<8,8,1>UD g32<16,8,2>UW { align1 2Q }; | mul(16) g51<1>D g98<8,8,1>D g81<16,8,2>UW { align1 1H I@2 }; cmp.l.f0.0(16) g94<1>D g4<0,1,0>D 0D { align1 1H F@7 compacted }; | mul(16) g106<1>D g98<8,8,1>D g81.1<16,8,2>UW { align1 1H }; add(16) g51<1>D g47<1,1,0>D -(abs)g1.3<0,1,0>D { align1 1H I@3 compacted }; | add(16) g102<1>D g98<1,1,0>D 1D { align1 1H compacted }; mach(8) g54<1>UD g62<8,8,1>UD g32<8,8,1>UD { align1 2Q AccWrEnable }; | mul(8) acc0<1>UD g67<8,8,1>UD g87<16,8,2>UW { align1 1Q }; mul(16) g39<1>D g53<8,8,1>D g77<16,8,2>UW { align1 1H A@1 }; | cmp.nz.f0.0(16) null<1>D g110<8,8,1>D 0D { align1 1H }; mul(16) g96<1>D g53<8,8,1>D g77.1<16,8,2>UW { align1 1H F@7 }; | add(16) g51.1<2>UW g51.1<16,8,2>UW g106<16,8,2>UW { align1 1H I@4 }; add(16) g61<1>D g53<1,1,0>D 1D { align1 1H compacted }; | mach(8) g106<1>UD g67<1,1,0>UD g87<1,1,0>UD { align1 1Q compacted AccWrEnable }; mul(8) acc0<1>UD g63<8,8,1>UD g31<16,8,2>UW { align1 1Q }; | (+f0.0) sel(16) g122<1>D -g118<1,1,0>D g118<1,1,0>D { align1 1H I@7 compacted }; add(16) g39.1<2>UW g39.1<16,8,2>UW g96<16,8,2>UW { align1 1H I@3 }; | add(16) g100<1>D (abs)g4.1<0,1,0>D -g51<1,1,0>D { align1 1H I@3 compacted }; cmp.l.f0.0(16) g96<1>D g1.3<0,1,0>D 0D { align1 1H compacted }; | mul(8) acc0<1>UD g68<8,8,1>UD g88<16,8,2>UW { align1 2Q }; mach(8) g67<1>UD g63<1,1,0>UD g31<1,1,0>UD { align1 1Q compacted AccWrEnable }; | cmp.l.f0.0(16) g124<1>D g4<0,1,0>D 0D { align1 1H compacted }; cmp.ge.f0.0(16) null<1>UD g35<8,8,1>UD g55<8,8,1>UD { align1 1H }; | cmp.l.f0.0(16) g126<1>D g1.3<0,1,0>D 0D { align1 1H compacted }; add(16) g59<1>D (abs)g4.2<0,1,0>D -g39<1,1,0>D { align1 1H I@4 compacted }; | cmp.ge.f0.0(16) null<1>UD g91<8,8,1>UD g61<8,8,1>UD { align1 1H }; xor(16) g98<1>UD g94<1,1,0>UD g96<1,1,0>UD { align1 1H A@4 compacted }; | add(16) g104<1>D g100<1,1,0>D -(abs)g1.3<0,1,0>D { align1 1H I@5 compacted }; mul(8) acc0<1>UD g64<8,8,1>UD g32<16,8,2>UW { align1 2Q }; | mach(8) g107<1>UD g68<8,8,1>UD g88<8,8,1>UD { align1 2Q AccWrEnable }; (+f0.0) sel(16) g112<1>UD g37<1,1,0>UD g33<1,1,0>UD { align1 1H compacted }; | xor(16) g2<1>UD g124<1,1,0>UD g126<1,1,0>UD { align1 1H I@4 compacted }; (+f0.0) sel(16) g114<1>UD g43<1,1,0>UD g35<1,1,0>UD { align1 1H compacted }; | (+f0.0) sel(16) g36<1>UD g93<1,1,0>UD g89<1,1,0>UD { align1 1H compacted }; add(16) g65<1>D g59<1,1,0>D -(abs)g1.3<0,1,0>D { align1 1H I@5 compacted }; | (+f0.0) sel(16) g38<1>UD g96<1,1,0>UD g91<1,1,0>UD { align1 1H compacted }; mach(8) g68<1>UD g64<8,8,1>UD g32<8,8,1>UD { align1 2Q AccWrEnable }; | mul(16) g72<1>D g106<8,8,1>D g83<16,8,2>UW { align1 1H I@4 }; add(16) g119<1>D g112<1,1,0>D 1D { align1 1H I@4 compacted }; | mul(16) g108<1>D g106<8,8,1>D g83.1<16,8,2>UW { align1 1H }; cmp.ge.f0.0(16) null<1>UD g114<8,8,1>UD g55<8,8,1>UD { align1 1H I@4 }; | add(16) g110<1>D g106<1,1,0>D 1D { align1 1H compacted }; mul(16) g63<1>D g67<8,8,1>D g79<16,8,2>UW { align1 1H I@3 }; | mul(8) acc0<1>UD g69<8,8,1>UD g87<16,8,2>UW { align1 1Q }; mul(16) g100<1>D g67<8,8,1>D g79.1<16,8,2>UW { align1 1H }; | add(16) g40<1>D g36<1,1,0>D 1D { align1 1H I@6 compacted }; add(16) g71<1>D g67<1,1,0>D 1D { align1 1H compacted }; | cmp.ge.f0.0(16) null<1>UD g38<8,8,1>UD g61<8,8,1>UD { align1 1H I@6 }; (+f0.0) sel(16) g121<1>UD g119<1,1,0>UD g112<1,1,0>UD { align1 1H I@5 compacted }; | add(16) g72.1<2>UW g72.1<16,8,2>UW g108<16,8,2>UW { align1 1H I@5 }; add(16) g63.1<2>UW g63.1<16,8,2>UW g100<16,8,2>UW { align1 1H I@3 }; | mach(8) g114<1>UD g69<1,1,0>UD g87<1,1,0>UD { align1 1Q compacted AccWrEnable }; cmp.nz.f0.0(16) null<1>D g98<8,8,1>D 0D { align1 1H }; | (+f0.0) sel(16) g44<1>UD g40<1,1,0>UD g36<1,1,0>UD { align1 1H A@4 compacted }; add(16) g69<1>D (abs)g4.3<0,1,0>D -g63<1,1,0>D { align1 1H I@2 compacted }; | add(16) g108<1>D (abs)g4.2<0,1,0>D -g72<1,1,0>D { align1 1H I@3 compacted }; (+f0.0) sel(16) g123<1>D -g121<1,1,0>D g121<1,1,0>D { align1 1H I@4 compacted }; | mul(8) acc0<1>UD g70<8,8,1>UD g88<16,8,2>UW { align1 2Q }; add(16) g73<1>D g69<1,1,0>D -(abs)g1.3<0,1,0>D { align1 1H I@2 compacted }; | cmp.nz.f0.0(16) null<1>D g2<8,8,1>D 0D { align1 1H }; cmp.l.f0.0(16) g1<1>D g4.1<0,1,0>D 0D { align1 1H I@1 compacted }; | add(16) g112<1>D g108<1,1,0>D -(abs)g1.3<0,1,0>D { align1 1H I@3 compacted }; cmp.ge.f0.0(16) null<1>UD g47<8,8,1>UD g55<8,8,1>UD { align1 1H }; | mach(8) g115<1>UD g70<8,8,1>UD g88<8,8,1>UD { align1 2Q AccWrEnable }; xor(16) g11<1>UD g1<1,1,0>UD g96<1,1,0>UD { align1 1H I@2 compacted }; | (+f0.0) sel(16) g46<1>D -g44<1,1,0>D g44<1,1,0>D { align1 1H A@6 compacted }; (+f0.0) sel(16) g13<1>UD g49<1,1,0>UD g45<1,1,0>UD { align1 1H compacted }; | mul(16) g87<1>D g114<8,8,1>D g85<16,8,2>UW { align1 1H I@2 }; (+f0.0) sel(16) g15<1>UD g51<1,1,0>UD g47<1,1,0>UD { align1 1H compacted }; | mul(16) g116<1>D g114<8,8,1>D g85.1<16,8,2>UW { align1 1H }; add(16) g17<1>D g13<1,1,0>D 1D { align1 1H I@2 compacted }; | add(16) g118<1>D g114<1,1,0>D 1D { align1 1H compacted }; cmp.ge.f0.0(16) null<1>UD g15<8,8,1>UD g55<8,8,1>UD { align1 1H I@2 }; | cmp.l.f0.0(16) g48<1>D g4.1<0,1,0>D 0D { align1 1H compacted }; (+f0.0) sel(16) g31<1>UD g17<1,1,0>UD g13<1,1,0>UD { align1 1H I@2 compacted }; | cmp.ge.f0.0(16) null<1>UD g100<8,8,1>UD g61<8,8,1>UD { align1 1H }; cmp.nz.f0.0(16) null<1>D g11<8,8,1>D 0D { align1 1H I@6 }; | add(16) g87.1<2>UW g87.1<16,8,2>UW g116<16,8,2>UW { align1 1H I@4 }; (+f0.0) sel(16) g33<1>D -g31<1,1,0>D g31<1,1,0>D { align1 1H I@2 compacted }; | xor(16) g50<1>UD g48<1,1,0>UD g126<1,1,0>UD { align1 1H I@3 compacted }; cmp.l.f0.0(16) g35<1>D g4.2<0,1,0>D 0D { align1 1H compacted }; | (+f0.0) sel(16) g52<1>UD g102<1,1,0>UD g98<1,1,0>UD { align1 1H compacted }; cmp.ge.f0.0(16) null<1>UD g59<8,8,1>UD g55<8,8,1>UD { align1 1H }; | (+f0.0) sel(16) g54<1>UD g104<1,1,0>UD g100<1,1,0>UD { align1 1H compacted }; xor(16) g37<1>UD g35<1,1,0>UD g96<1,1,0>UD { align1 1H I@2 compacted }; | add(16) g116<1>D (abs)g4.3<0,1,0>D -g87<1,1,0>D { align1 1H I@4 compacted }; (+f0.0) sel(16) g43<1>UD g61<1,1,0>UD g53<1,1,0>UD { align1 1H compacted }; | add(16) g58<1>D g52<1,1,0>D 1D { align1 1H I@3 compacted }; (+f0.0) sel(16) g45<1>UD g65<1,1,0>UD g59<1,1,0>UD { align1 1H compacted }; | cmp.ge.f0.0(16) null<1>UD g54<8,8,1>UD g61<8,8,1>UD { align1 1H I@3 }; add(16) g47<1>D g43<1,1,0>D 1D { align1 1H I@2 compacted }; | add(16) g120<1>D g116<1,1,0>D -(abs)g1.3<0,1,0>D { align1 1H I@3 compacted }; cmp.ge.f0.0(16) null<1>UD g45<8,8,1>UD g55<8,8,1>UD { align1 1H I@2 }; | (+f0.0) sel(16) g65<1>UD g58<1,1,0>UD g52<1,1,0>UD { align1 1H I@3 compacted }; (+f0.0) sel(16) g49<1>UD g47<1,1,0>UD g43<1,1,0>UD { align1 1H I@2 compacted }; | cmp.nz.f0.0(16) null<1>D g50<8,8,1>D 0D { align1 1H I@7 }; cmp.nz.f0.0(16) null<1>D g37<8,8,1>D 0D { align1 1H I@6 }; | (+f0.0) sel(16) g67<1>D -g65<1,1,0>D g65<1,1,0>D { align1 1H I@2 compacted }; (+f0.0) sel(16) g51<1>D -g49<1,1,0>D g49<1,1,0>D { align1 1H I@2 compacted }; | cmp.l.f0.0(16) g69<1>D g4.2<0,1,0>D 0D { align1 1H compacted }; cmp.l.f0.0(16) g53<1>D g4.3<0,1,0>D 0D { align1 1H compacted }; | cmp.ge.f0.0(16) null<1>UD g108<8,8,1>UD g61<8,8,1>UD { align1 1H }; cmp.ge.f0.0(16) null<1>UD g69<8,8,1>UD g55<8,8,1>UD { align1 1H }; | xor(16) g71<1>UD g69<1,1,0>UD g126<1,1,0>UD { align1 1H I@2 compacted }; xor(16) g59<1>UD g53<1,1,0>UD g96<1,1,0>UD { align1 1H I@2 compacted }; | (+f0.0) sel(16) g73<1>UD g110<1,1,0>UD g106<1,1,0>UD { align1 1H compacted }; (+f0.0) sel(16) g64<1>UD g71<1,1,0>UD g67<1,1,0>UD { align1 1H compacted }; | (+f0.0) sel(16) g75<1>UD g112<1,1,0>UD g108<1,1,0>UD { align1 1H compacted }; (+f0.0) sel(16) g66<1>UD g73<1,1,0>UD g69<1,1,0>UD { align1 1H compacted }; | add(16) g77<1>D g73<1,1,0>D 1D { align1 1H I@2 compacted }; add(16) g68<1>D g64<1,1,0>D 1D { align1 1H I@2 compacted }; | cmp.ge.f0.0(16) null<1>UD g75<8,8,1>UD g61<8,8,1>UD { align1 1H I@2 }; cmp.ge.f0.0(16) null<1>UD g66<8,8,1>UD g55<8,8,1>UD { align1 1H I@2 }; | (+f0.0) sel(16) g79<1>UD g77<1,1,0>UD g73<1,1,0>UD { align1 1H I@2 compacted }; (+f0.0) sel(16) g70<1>UD g68<1,1,0>UD g64<1,1,0>UD { align1 1H I@2 compacted }; | cmp.nz.f0.0(16) null<1>D g71<8,8,1>D 0D { align1 1H I@6 }; cmp.nz.f0.0(16) null<1>D g59<8,8,1>D 0D { align1 1H I@6 }; | (+f0.0) sel(16) g81<1>D -g79<1,1,0>D g79<1,1,0>D { align1 1H I@2 compacted }; (+f0.0) sel(16) g72<1>D -g70<1,1,0>D g70<1,1,0>D { align1 1H I@2 compacted }; | cmp.l.f0.0(16) g83<1>D g4.3<0,1,0>D 0D { align1 1H compacted }; cmp.ge.f0.0(16) g74<1>D g123<1,1,0>D (abs)g23<1,1,0>D { align1 1H compacted }; | cmp.ge.f0.0(16) null<1>UD g116<8,8,1>UD g61<8,8,1>UD { align1 1H }; cmp.ge.f0.0(16) g76<1>D g108<1,1,0>D (abs)g57<1,1,0>D { align1 1H compacted }; | xor(16) g85<1>UD g83<1,1,0>UD g126<1,1,0>UD { align1 1H I@2 compacted }; cmp.ge.f0.0(16) g80<1>D g117<1,1,0>D (abs)g41<1,1,0>D { align1 1H compacted }; | (+f0.0) sel(16) g88<1>UD g118<1,1,0>UD g114<1,1,0>UD { align1 1H compacted }; cmp.ge.f0.0(16) g82<1>D g33<1,1,0>D (abs)g21<1,1,0>D { align1 1H compacted }; | (+f0.0) sel(16) g90<1>UD g120<1,1,0>UD g116<1,1,0>UD { align1 1H compacted }; cmp.ge.f0.0(16) g86<1>D g126<1,1,0>D (abs)g27<1,1,0>D { align1 1H compacted }; | add(16) g92<1>D g88<1,1,0>D 1D { align1 1H I@2 compacted }; cmp.ge.f0.0(16) g90<1>D g51<1,1,0>D (abs)g25<1,1,0>D { align1 1H compacted }; | cmp.ge.f0.0(16) null<1>UD g90<8,8,1>UD g61<8,8,1>UD { align1 1H I@2 }; or(16) g78<1>UD g76<1,1,0>UD g74<1,1,0>UD { align1 1H I@5 compacted }; | (+f0.0) sel(16) g96<1>UD g92<1,1,0>UD g88<1,1,0>UD { align1 1H I@2 compacted }; cmp.ge.f0.0(16) g94<1>D g92<1,1,0>D (abs)g19<1,1,0>D { align1 1H compacted }; | cmp.nz.f0.0(16) null<1>D g85<8,8,1>D 0D { align1 1H I@6 }; or(16) g84<1>UD g80<1,1,0>UD g82<1,1,0>UD { align1 1H I@5 compacted }; | (+f0.0) sel(16) g98<1>D -g96<1,1,0>D g96<1,1,0>D { align1 1H I@2 compacted }; cmp.ge.f0.0(16) g96<1>D g72<1,1,0>D (abs)g29<1,1,0>D { align1 1H I@7 compacted }; | cmp.ge.f0.0(16) g100<1>D g46<1,1,0>D (abs)g29<1,1,0>D { align1 1H compacted }; or(16) g92<1>UD g86<1,1,0>UD g90<1,1,0>UD { align1 1H I@5 compacted }; | cmp.ge.f0.0(16) g102<1>D g22<1,1,0>D (abs)g63<1,1,0>D { align1 1H compacted }; or(16) g98<1>UD g94<1,1,0>UD g96<1,1,0>UD { align1 1H I@2 compacted }; | cmp.ge.f0.0(16) g106<1>D g42<1,1,0>D (abs)g33<1,1,0>D { align1 1H compacted }; and(16) g100<1>UD g98<1,1,0>UD g92<1,1,0>UD { align1 1H I@1 compacted }; | cmp.ge.f0.0(16) g108<1>D g67<1,1,0>D (abs)g31<1,1,0>D { align1 1H compacted }; and(16) g102<1>UD g100<1,1,0>UD g84<1,1,0>UD { align1 1H I@1 compacted }; | cmp.ge.f0.0(16) g112<1>D g56<1,1,0>D (abs)g25<1,1,0>D { align1 1H compacted }; and.nz.f0.0(16) null<1>UD g102<8,8,1>UD g78<8,8,1>UD { align1 1H I@1 }; | cmp.ge.f0.0(16) g114<1>D g81<1,1,0>D (abs)g11<1,1,0>D { align1 1H compacted }; > or(16) g104<1>UD g102<1,1,0>UD g100<1,1,0>UD { align1 1H I@5 compacted }; > cmp.ge.f0.0(16) g118<1>D g122<1,1,0>D (abs)g27<1,1,0>D { align1 1H compacted }; > or(16) g110<1>UD g106<1,1,0>UD g108<1,1,0>UD { align1 1H I@5 compacted }; > cmp.ge.f0.0(16) g120<1>D g98<1,1,0>D (abs)g13<1,1,0>D { align1 1H I@7 compacted }; > or(16) g116<1>UD g112<1,1,0>UD g114<1,1,0>UD { align1 1H I@5 compacted }; > or(16) g122<1>UD g118<1,1,0>UD g120<1,1,0>UD { align1 1H I@2 compacted }; > and(16) g124<1>UD g122<1,1,0>UD g116<1,1,0>UD { align1 1H I@1 compacted }; > and(16) g126<1>UD g124<1,1,0>UD g110<1,1,0>UD { align1 1H I@1 compacted }; > and.nz.f0.0(16) null<1>UD g126<8,8,1>UD g104<8,8,1>UD { align1 1H I@1 }; (+f0.0) if(16) JIP: LABEL10 UIP: LABEL9 { align1 1H }; (+f0.0) if(16) JIP: LABEL10 UIP: LABEL9 { align1 1H }; END B11 ->B12 ->B15 END B11 ->B12 ->B15 START B12 <-B11 (128 cycles) START B12 <-B11 (128 cycles) mov(16) g103<1>D 0D { align1 WE_all 1H I@2 }; | mov(16) g1<1>D 0D { align1 WE_all 1H }; mov(16) g103<1>D g9<8,8,1>D { align1 1H }; | mov(16) g1<1>D g9<8,8,1>D { align1 1H }; add(8) g103.1<2>D g103<8,4,2>D g103.1<8,4,2>D { align1 WE_all 1Q I@1 }; | add(8) g1.1<2>D g1<8,4,2>D g1.1<8,4,2>D { align1 WE_all 1Q I@1 }; add(4) g103.2<4>D g103.1<8,2,4>D g103.2<8,2,4>D { align1 WE_all 1N I@1 }; | add(4) g1.2<4>D g1.1<8,2,4>D g1.2<8,2,4>D { align1 WE_all 1N I@1 }; add(4) g103.3<4>D g103.1<8,2,4>D g103.3<8,2,4>D { align1 WE_all 1N I@1 }; | add(4) g1.3<4>D g1.1<8,2,4>D g1.3<8,2,4>D { align1 WE_all 1N I@1 }; add(4) g103.4<1>D g103.3<0,1,0>D g103.4<4,4,1>D { align1 WE_all 1N I@1 }; | add(4) g1.4<1>D g1.3<0,1,0>D g1.4<4,4,1>D { align1 WE_all 1N I@1 }; add(4) g104.4<1>D g104.3<0,1,0>D g104.4<4,4,1>D { align1 WE_all 1N I@2 }; | add(4) g2.4<1>D g2.3<0,1,0>D g2.4<4,4,1>D { align1 WE_all 1N I@2 }; add(8) g104<1>D g103.7<0,1,0>D g104<1,1,0>D { align1 WE_all 1Q I@1 compacted }; | add(8) g2<1>D g1.7<0,1,0>D g2<1,1,0>D { align1 WE_all 1Q I@1 compacted }; fbl(1) g105<1>UD mask0<0,1,0>UD { align1 WE_all 1N compacted }; | fbl(1) g11<1>UD mask0<0,1,0>UD { align1 WE_all 1N compacted }; mov(16) g107<1>D g89<8,8,1>UW { align1 1H }; | mov(16) g13<1>D g95<8,8,1>UW { align1 1H }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@1 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@1 }; cmp.z.f0.0(16) null<1>D g107<8,8,1>D g105<0,1,0>D { align1 1H }; | cmp.z.f0.0(16) null<1>D g13<8,8,1>D g11<0,1,0>D { align1 1H }; (+f0.0) if(16) JIP: LABEL11 UIP: LABEL11 { align1 1H }; (+f0.0) if(16) JIP: LABEL11 UIP: LABEL11 { align1 1H }; END B12 ->B13 ->B14 END B12 ->B13 ->B14 START B13 <-B12 (24 cycles) START B13 <-B12 (24 cycles) mov(16) g27<1>D 8D { align1 1H }; | mov(16) g53<1>D 8D { align1 1H }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@6 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@6 }; mov(16) g29<1>D g104.7<0,1,0>D { align1 1H }; | mov(16) g55<1>D g2.7<0,1,0>D { align1 1H }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@1 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@1 }; send(16) nullUD g27UD g29UD 0x6404050c 0x02000080 | send(16) nullUD g53UD g55UD 0x6404050c 0x02000080 ugm MsgDesc: ( atomic_add, a32, d32, V1, L1UC_L3WB dst_len = 0, src0_len = 2, src1_len = | ugm MsgDesc: ( atomic_add, a32, d32, V1, L1UC_L3WB dst_len = 0, src0_len = 2, src1_len = END B13 ->B14 END B13 ->B14 START B14 <-B13 <-B12 (24 cycles) START B14 <-B13 <-B12 (24 cycles) LABEL11: LABEL11: endif(16) JIP: LABEL12 { align1 1H }; endif(16) JIP: LABEL12 { align1 1H }; mov(16) g57<1>UD 0x3f800000UD { align1 1H }; | mov(16) g83<1>UD 0x3f800000UD { align1 1H }; mov(16) g55<1>UD 0x00000000UD { align1 1H F@3 }; | mov(16) g81<1>UD 0x00000000UD { align1 1H }; LABEL12: LABEL12: else(16) JIP: LABEL9 UIP: LABEL9 { align1 1H }; else(16) JIP: LABEL9 UIP: LABEL9 { align1 1H }; END B14 ->B15 ->B16 END B14 ->B15 ->B16 START B15 <-B11 <-B14 (8 cycles) START B15 <-B11 <-B14 (8 cycles) LABEL10: LABEL10: mov(16) g57<1>UD 0x00000000UD { align1 1H I@3 }; | mov(16) g83<1>UD 0x00000000UD { align1 1H I@3 }; mov(16) g55<1>UD 0x3f800000UD { align1 1H A@3 }; | mov(16) g81<1>UD 0x3f800000UD { align1 1H I@3 }; END B15 ->B16 END B15 ->B16 START B16 <-B15 <-B14 (1638 cycles) START B16 <-B15 <-B14 (1638 cycles) LABEL9: LABEL9: endif(16) JIP: LABEL0 { align1 1H }; endif(16) JIP: LABEL0 { align1 1H }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N $12.src }; | sync nop(1) null<0,1,0>UB { align1 WE_all 1N $0.src }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N $15.src }; | mov(8) g56<1>D g5<8,8,1>D { align1 1Q $13.src }; mov(8) g30<1>D g5<8,8,1>D { align1 1Q I@7 }; | mov(8) g57<1>D g7<8,8,1>D { align1 1Q $13.src }; mov(8) g31<1>D g7<8,8,1>D { align1 1Q $12.src }; | mov(8) g58<1>D 2D { align1 1Q }; mov(8) g32<1>D 2D { align1 1Q }; | mov(8) g59<1>D g81<8,8,1>D { align1 1Q I@5 }; mov(8) g33<1>D g55<8,8,1>D { align1 1Q I@5 }; | mov(8) g60<1>D g83<8,8,1>D { align1 1Q I@7 }; mov(8) g34<1>D g57<8,8,1>D { align1 1Q I@7 }; | mov(8) g61<1>D 0D { align1 1Q }; mov(8) g35<1>D 0D { align1 1Q }; | mov(8) g62<1>D 1065353216D { align1 1Q }; mov(8) g36<1>D 1065353216D { align1 1Q }; < sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@1 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@1 }; send(8) nullUD g30UD g33UD 0x06035003 0x00000100 | send(8) nullUD g56UD g59UD 0x06035003 0x00000100 dp data 1 MsgDesc: (DC typed surface write, Surface = 3, SIMD16, Mask = 0x0) mlen 3 ex_ml | dp data 1 MsgDesc: (DC typed surface write, Surface = 3, SIMD16, Mask = 0x0) mlen 3 ex_ml sync nop(1) null<0,1,0>UB { align1 WE_all 3N $0.src }; | sync nop(1) null<0,1,0>UB { align1 WE_all 3N $1.src }; mov(8) g34<1>D g6<8,8,1>D { align1 2Q $12.src }; | mov(8) g60<1>D g6<8,8,1>D { align1 2Q $13.src }; sync nop(1) null<0,1,0>UB { align1 WE_all 3N $0.src }; | sync nop(1) null<0,1,0>UB { align1 WE_all 3N $1.src }; mov(8) g35<1>D g8<8,8,1>D { align1 2Q $12.src }; | mov(8) g61<1>D g8<8,8,1>D { align1 2Q $13.src }; mov(8) g36<1>D 2D { align1 2Q $0.src }; | mov(8) g62<1>D 2D { align1 2Q $1.src }; mov(8) g37<1>D g56<8,8,1>D { align1 2Q }; | mov(8) g63<1>D g82<8,8,1>D { align1 2Q }; mov(8) g38<1>D g58<8,8,1>D { align1 2Q }; | mov(8) g64<1>D g84<8,8,1>D { align1 2Q }; mov(8) g39<1>D 0D { align1 2Q }; | mov(8) g65<1>D 0D { align1 2Q }; mov(8) g40<1>D 1065353216D { align1 2Q }; | mov(8) g66<1>D 1065353216D { align1 2Q }; sync nop(1) null<0,1,0>UB { align1 WE_all 3N I@1 }; sync nop(1) null<0,1,0>UB { align1 WE_all 3N I@1 }; send(8) nullUD g34UD g37UD 0x06036003 0x00000100 | send(8) nullUD g60UD g63UD 0x06036003 0x00000100 dp data 1 MsgDesc: (DC typed surface write, Surface = 3, SIMD8, Mask = 0x0) mlen 3 ex_mle | dp data 1 MsgDesc: (DC typed surface write, Surface = 3, SIMD8, Mask = 0x0) mlen 3 ex_mle send(16) g117UD g5UD nullUD 0x0825a007 0x00000000 | send(16) g23UD g5UD nullUD 0x0825a007 0x00000000 sampler MsgDesc: ld_lz SIMD16 Surface = 7 Sampler = 0 mlen 4 ex_mlen 0 rlen 2 { align1 1H | sampler MsgDesc: ld_lz SIMD16 Surface = 7 Sampler = 0 mlen 4 ex_mlen 0 rlen 2 { align1 1H add(16) g108<1>D g117<1,1,0>D -g4.5<0,1,0>D { align1 1H $2.dst compacted }; | add(16) g14<1>D g23<1,1,0>D -g4.5<0,1,0>D { align1 1H $3.dst compacted }; cmp.le.f0.0(16) null<1>UD g108<8,8,1>UD 0x00000000UD { align1 1H I@1 }; | cmp.le.f0.0(16) null<1>UD g14<8,8,1>UD 0x00000000UD { align1 1H I@1 }; (+f0.0) if(16) JIP: LABEL14 UIP: LABEL13 { align1 1H }; (+f0.0) if(16) JIP: LABEL14 UIP: LABEL13 { align1 1H }; END B16 ->B17 ->B20 END B16 ->B17 ->B20 START B17 <-B16 (128 cycles) START B17 <-B16 (128 cycles) mov(16) g109<1>D 0D { align1 WE_all 1H I@2 }; | mov(16) g15<1>D 0D { align1 WE_all 1H }; mov(16) g109<1>D g9<8,8,1>D { align1 1H }; | mov(16) g15<1>D g9<8,8,1>D { align1 1H }; add(8) g109.1<2>D g109<8,4,2>D g109.1<8,4,2>D { align1 WE_all 1Q I@1 }; | add(8) g15.1<2>D g15<8,4,2>D g15.1<8,4,2>D { align1 WE_all 1Q I@1 }; add(4) g109.2<4>D g109.1<8,2,4>D g109.2<8,2,4>D { align1 WE_all 1N I@1 }; | add(4) g15.2<4>D g15.1<8,2,4>D g15.2<8,2,4>D { align1 WE_all 1N I@1 }; add(4) g109.3<4>D g109.1<8,2,4>D g109.3<8,2,4>D { align1 WE_all 1N I@1 }; | add(4) g15.3<4>D g15.1<8,2,4>D g15.3<8,2,4>D { align1 WE_all 1N I@1 }; add(4) g109.4<1>D g109.3<0,1,0>D g109.4<4,4,1>D { align1 WE_all 1N I@1 }; | add(4) g15.4<1>D g15.3<0,1,0>D g15.4<4,4,1>D { align1 WE_all 1N I@1 }; add(4) g110.4<1>D g110.3<0,1,0>D g110.4<4,4,1>D { align1 WE_all 1N I@2 }; | add(4) g16.4<1>D g16.3<0,1,0>D g16.4<4,4,1>D { align1 WE_all 1N I@2 }; add(8) g110<1>D g109.7<0,1,0>D g110<1,1,0>D { align1 WE_all 1Q I@1 compacted }; | add(8) g16<1>D g15.7<0,1,0>D g16<1,1,0>D { align1 WE_all 1Q I@1 compacted }; fbl(1) g111<1>UD mask0<0,1,0>UD { align1 WE_all 1N compacted }; | fbl(1) g17<1>UD mask0<0,1,0>UD { align1 WE_all 1N compacted }; mov(16) g113<1>D g89<8,8,1>UW { align1 1H }; | mov(16) g19<1>D g95<8,8,1>UW { align1 1H }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@1 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@1 }; cmp.z.f0.0(16) null<1>D g113<8,8,1>D g111<0,1,0>D { align1 1H }; | cmp.z.f0.0(16) null<1>D g19<8,8,1>D g17<0,1,0>D { align1 1H }; (+f0.0) if(16) JIP: LABEL15 UIP: LABEL15 { align1 1H }; (+f0.0) if(16) JIP: LABEL15 UIP: LABEL15 { align1 1H }; END B17 ->B18 ->B19 END B17 ->B18 ->B19 START B18 <-B17 (24 cycles) START B18 <-B17 (24 cycles) mov(16) g38<1>D 16D { align1 1H $1.src }; | mov(16) g64<1>D 16D { align1 1H $2.src }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@6 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@6 }; mov(16) g40<1>D g110.7<0,1,0>D { align1 1H $1.src }; | mov(16) g66<1>D g16.7<0,1,0>D { align1 1H $2.src }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@1 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@1 }; send(16) nullUD g38UD g40UD 0x6404050c 0x02000080 | send(16) nullUD g64UD g66UD 0x6404050c 0x02000080 ugm MsgDesc: ( atomic_add, a32, d32, V1, L1UC_L3WB dst_len = 0, src0_len = 2, src1_len = | ugm MsgDesc: ( atomic_add, a32, d32, V1, L1UC_L3WB dst_len = 0, src0_len = 2, src1_len = END B18 ->B19 END B18 ->B19 START B19 <-B18 <-B17 (24 cycles) START B19 <-B18 <-B17 (24 cycles) LABEL15: LABEL15: endif(16) JIP: LABEL16 { align1 1H }; endif(16) JIP: LABEL16 { align1 1H }; mov(16) g60<1>UD 0x3f800000UD { align1 1H }; | mov(16) g86<1>UD 0x3f800000UD { align1 1H }; mov(16) g58<1>UD 0x00000000UD { align1 1H }; | mov(16) g84<1>UD 0x00000000UD { align1 1H }; LABEL16: LABEL16: else(16) JIP: LABEL13 UIP: LABEL13 { align1 1H }; else(16) JIP: LABEL13 UIP: LABEL13 { align1 1H }; END B19 ->B20 ->B21 END B19 ->B20 ->B21 START B20 <-B16 <-B19 (8 cycles) START B20 <-B16 <-B19 (8 cycles) LABEL14: LABEL14: mov(16) g60<1>UD 0x00000000UD { align1 1H I@3 }; | mov(16) g86<1>UD 0x00000000UD { align1 1H I@3 }; mov(16) g58<1>UD 0x3f800000UD { align1 1H I@3 }; | mov(16) g84<1>UD 0x3f800000UD { align1 1H I@3 }; END B20 ->B21 END B20 ->B21 START B21 <-B20 <-B19 (838 cycles) START B21 <-B20 <-B19 (838 cycles) LABEL13: LABEL13: endif(16) JIP: LABEL0 { align1 1H }; endif(16) JIP: LABEL0 { align1 1H }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N $1.src }; | sync nop(1) null<0,1,0>UB { align1 WE_all 1N $2.src }; mov(8) g41<1>D g5<8,8,1>D { align1 1Q $2.src }; | mov(8) g67<1>D g5<8,8,1>D { align1 1Q $3.src }; mov(8) g42<1>D g7<8,8,1>D { align1 1Q $2.src }; | mov(8) g68<1>D g7<8,8,1>D { align1 1Q $3.src }; mov(8) g43<1>D 4D { align1 1Q }; | mov(8) g69<1>D 4D { align1 1Q }; mov(8) g44<1>D g58<8,8,1>D { align1 1Q I@5 }; | mov(8) g70<1>D g84<8,8,1>D { align1 1Q I@5 }; mov(8) g45<1>D g60<8,8,1>D { align1 1Q I@7 }; | mov(8) g71<1>D g86<8,8,1>D { align1 1Q I@7 }; mov(8) g46<1>D 0D { align1 1Q }; | mov(8) g72<1>D 0D { align1 1Q }; mov(8) g47<1>D 1065353216D { align1 1Q }; | mov(8) g73<1>D 1065353216D { align1 1Q }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@1 }; sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@1 }; send(8) nullUD g41UD g44UD 0x06035003 0x00000100 | send(8) nullUD g67UD g70UD 0x06035003 0x00000100 dp data 1 MsgDesc: (DC typed surface write, Surface = 3, SIMD16, Mask = 0x0) mlen 3 ex_ml | dp data 1 MsgDesc: (DC typed surface write, Surface = 3, SIMD16, Mask = 0x0) mlen 3 ex_ml sync nop(1) null<0,1,0>UB { align1 WE_all 3N $3.src }; | sync nop(1) null<0,1,0>UB { align1 WE_all 3N $4.src }; mov(8) g45<1>D g6<8,8,1>D { align1 2Q $2.src }; | mov(8) g71<1>D g6<8,8,1>D { align1 2Q $3.src }; sync nop(1) null<0,1,0>UB { align1 WE_all 3N $3.src }; | sync nop(1) null<0,1,0>UB { align1 WE_all 3N $4.src }; mov(8) g46<1>D g8<8,8,1>D { align1 2Q $2.src }; | mov(8) g72<1>D g8<8,8,1>D { align1 2Q $3.src }; mov(8) g47<1>D 4D { align1 2Q $3.src }; | mov(8) g73<1>D 4D { align1 2Q $4.src }; mov(8) g48<1>D g59<8,8,1>D { align1 2Q }; | mov(8) g74<1>D g85<8,8,1>D { align1 2Q }; mov(8) g49<1>D g61<8,8,1>D { align1 2Q }; | mov(8) g75<1>D g87<8,8,1>D { align1 2Q }; mov(8) g50<1>D 0D { align1 2Q }; | mov(8) g76<1>D 0D { align1 2Q }; mov(8) g51<1>D 1065353216D { align1 2Q }; | mov(8) g77<1>D 1065353216D { align1 2Q }; sync nop(1) null<0,1,0>UB { align1 WE_all 3N I@1 }; sync nop(1) null<0,1,0>UB { align1 WE_all 3N I@1 }; send(8) nullUD g45UD g48UD 0x06036003 0x00000100 | send(8) nullUD g71UD g74UD 0x06036003 0x00000100 dp data 1 MsgDesc: (DC typed surface write, Surface = 3, SIMD8, Mask = 0x0) mlen 3 ex_mle | dp data 1 MsgDesc: (DC typed surface write, Surface = 3, SIMD8, Mask = 0x0) mlen 3 ex_mle END B21 ->B22 END B21 ->B22 START B22 <-B21 <-B0 (22 cycles) START B22 <-B21 <-B0 (22 cycles) LABEL0: LABEL0: endif(16) JIP: LABEL17 { align1 1H }; endif(16) JIP: LABEL17 { align1 1H }; LABEL17: LABEL17: mov(8) g126<1>UD g0<8,8,1>UD { align1 WE_all 1Q }; mov(8) g126<1>UD g0<8,8,1>UD { align1 WE_all 1Q }; send(16) nullUD g126UD nullUD 0x02000000 0x00000000 send(16) nullUD g126UD nullUD 0x02000000 0x00000000 gateway MsgDesc: (open) mlen 1 ex_mlen 0 rlen 0 { align1 WE_all 1H A@1 EOT }; gateway MsgDesc: (open) mlen 1 ex_mlen 0 rlen 0 { align1 WE_all 1H A@1 EOT }; END B22 END B22