GLSL IR for native fragment shader 0: GLSL IR for native fragment shader 0: ( ( (declare (location=1 shader_in ) vec4 gl_Color) (declare (location=1 shader_in ) vec4 gl_Color) (declare (location=2 shader_out ) vec4 gl_FragColor) (declare (location=2 shader_out ) vec4 gl_FragColor) ( function main ( function main (signature void (signature void (parameters (parameters ) ) ( ( (assign (xyzw) (var_ref gl_FragColor) (var_ref gl_Color) ) (assign (xyzw) (var_ref gl_FragColor) (var_ref gl_Color) ) )) )) ) ) ) ) NIR (SSA form) for fragment shader: NIR (SSA form) for fragment shader: shader: MESA_SHADER_FRAGMENT shader: MESA_SHADER_FRAGMENT name: GLSL0 name: GLSL0 inputs: 0 inputs: 0 outputs: 0 outputs: 0 uniforms: 0 uniforms: 0 shared: 0 shared: 0 decl_var shader_in INTERP_MODE_SMOOTH vec4 gl_Color (VARYING_SLOT_COL0.xyzw, 1, 0) decl_var shader_in INTERP_MODE_SMOOTH vec4 gl_Color (VARYING_SLOT_COL0.xyzw, 1, 0) decl_var shader_out INTERP_MODE_NONE vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 4, 0) decl_var shader_out INTERP_MODE_NONE vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 4, 0) decl_function main (0 params) decl_function main (0 params) impl main { impl main { block block_0: block block_0: /* preds: */ /* preds: */ vec2 32 ssa_0 = intrinsic load_barycentric_pixel () (1) /* interp_mode=1 */ vec2 32 ssa_0 = intrinsic load_barycentric_pixel () (1) /* interp_mode=1 */ vec1 32 ssa_1 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_1 = load_const (0x00000000 /* 0.000000 */) vec4 32 ssa_2 = intrinsic load_interpolated_input (ssa_0, ssa_1) (1, 0) /* base=1 */ /* component=0 vec4 32 ssa_2 = intrinsic load_interpolated_input (ssa_0, ssa_1) (1, 0) /* base=1 */ /* component=0 intrinsic store_output (ssa_2, ssa_1) (4, 15, 0, 160) /* base=4 */ /* wrmask=xyzw */ /* component=0 intrinsic store_output (ssa_2, ssa_1) (4, 15, 0, 160) /* base=4 */ /* wrmask=xyzw */ /* component=0 /* succs: block_1 */ /* succs: block_1 */ block block_1: block block_1: } } NIR (final form) for fragment shader: NIR (final form) for fragment shader: shader: MESA_SHADER_FRAGMENT shader: MESA_SHADER_FRAGMENT name: GLSL0 name: GLSL0 inputs: 0 inputs: 0 outputs: 0 outputs: 0 uniforms: 0 uniforms: 0 shared: 0 shared: 0 decl_var shader_in INTERP_MODE_SMOOTH vec4 gl_Color (VARYING_SLOT_COL0.xyzw, 1, 0) decl_var shader_in INTERP_MODE_SMOOTH vec4 gl_Color (VARYING_SLOT_COL0.xyzw, 1, 0) decl_var shader_out INTERP_MODE_NONE vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 4, 0) decl_var shader_out INTERP_MODE_NONE vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 4, 0) decl_function main (0 params) decl_function main (0 params) impl main { impl main { block block_0: block block_0: /* preds: */ /* preds: */ vec2 32 ssa_0 = intrinsic load_barycentric_pixel () (1) /* interp_mode=1 */ vec2 32 ssa_0 = intrinsic load_barycentric_pixel () (1) /* interp_mode=1 */ vec1 32 ssa_1 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_1 = load_const (0x00000000 /* 0.000000 */) vec4 32 ssa_2 = intrinsic load_interpolated_input (ssa_0, ssa_1) (1, 0) /* base=1 */ /* component=0 vec4 32 ssa_2 = intrinsic load_interpolated_input (ssa_0, ssa_1) (1, 0) /* base=1 */ /* component=0 intrinsic store_output (ssa_2, ssa_1) (4, 15, 0, 160) /* base=4 */ /* wrmask=xyzw */ /* component=0 intrinsic store_output (ssa_2, ssa_1) (4, 15, 0, 160) /* base=4 */ /* wrmask=xyzw */ /* component=0 /* succs: block_1 */ /* succs: block_1 */ block block_1: block block_1: } } Native code for unnamed fragment shader GLSL0 (sha1 35d3e394451b3529b2635792780583af927d5601) Native code for unnamed fragment shader GLSL0 (sha1 35d3e394451b3529b2635792780583af927d5601) SIMD8 shader: 5 instructions. 0 loops. 24 cycles. 0:0 spills:fills, 1 sends, scheduled with mode top-down. P SIMD8 shader: 5 instructions. 0 loops. 24 cycles. 0:0 spills:fills, 1 sends, scheduled with mode top-down. P START B0 (24 cycles) START B0 (24 cycles) pln(8) g124<1>F g4<0,1,0>F g2<8,8,1>F { align1 1Q compacted }; pln(8) g124<1>F g4<0,1,0>F g2<8,8,1>F { align1 1Q compacted }; pln(8) g125<1>F g4.4<0,1,0>F g2<8,8,1>F { align1 1Q compacted }; pln(8) g125<1>F g4.4<0,1,0>F g2<8,8,1>F { align1 1Q compacted }; pln(8) g126<1>F g5<0,1,0>F g2<8,8,1>F { align1 1Q compacted }; pln(8) g126<1>F g5<0,1,0>F g2<8,8,1>F { align1 1Q compacted }; pln(8) g127<1>F g5.4<0,1,0>F g2<8,8,1>F { align1 1Q compacted }; pln(8) g127<1>F g5.4<0,1,0>F g2<8,8,1>F { align1 1Q compacted }; sendc(8) null<1>UW g124<8,8,1>UD 0x88031400 sendc(8) null<1>UW g124<8,8,1>UD 0x88031400 render MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 4 rlen 0 { align1 1Q EOT render MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 4 rlen 0 { align1 1Q EOT END B0 END B0 Native code for unnamed fragment shader GLSL0 (sha1 d49cddaeaed6b622466e3b3476f9832155bc6ab1) Native code for unnamed fragment shader GLSL0 (sha1 d49cddaeaed6b622466e3b3476f9832155bc6ab1) SIMD16 shader: 5 instructions. 0 loops. 34 cycles. 0:0 spills:fills, 1 sends, scheduled with mode top-down. SIMD16 shader: 5 instructions. 0 loops. 34 cycles. 0:0 spills:fills, 1 sends, scheduled with mode top-down. START B0 (34 cycles) START B0 (34 cycles) pln(16) g120<1>F g6<0,1,0>F g2<8,8,1>F { align1 1H compacted }; pln(16) g120<1>F g6<0,1,0>F g2<8,8,1>F { align1 1H compacted }; pln(16) g122<1>F g6.4<0,1,0>F g2<8,8,1>F { align1 1H compacted }; pln(16) g122<1>F g6.4<0,1,0>F g2<8,8,1>F { align1 1H compacted }; pln(16) g124<1>F g7<0,1,0>F g2<8,8,1>F { align1 1H compacted }; pln(16) g124<1>F g7<0,1,0>F g2<8,8,1>F { align1 1H compacted }; pln(16) g126<1>F g7.4<0,1,0>F g2<8,8,1>F { align1 1H compacted }; pln(16) g126<1>F g7.4<0,1,0>F g2<8,8,1>F { align1 1H compacted }; sendc(16) null<1>UW g120<8,8,1>UD 0x90031000 sendc(16) null<1>UW g120<8,8,1>UD 0x90031000 render MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 8 rlen 0 { align1 1H EOT render MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 8 rlen 0 { align1 1H EOT END B0 END B0 GLSL IR for native fragment shader 3: GLSL IR for native fragment shader 3: ( ( (declare (location=19 sys ) vec4 gl_FragCoord) (declare (location=19 sys ) vec4 gl_FragCoord) (declare (location=4 shader_out ) vec4 color) (declare (location=4 shader_out ) vec4 color) ( function main ( function main (signature void (signature void (parameters (parameters ) ) ( ( (declare () dvec2 colord) (declare () dvec2 colord) (declare (temporary ) int compiler_temp) (declare (temporary ) int compiler_temp) (assign (x) (var_ref compiler_temp) (expression int / (expression int f2i (swiz x (var_ref gl_FragCo (assign (x) (var_ref compiler_temp) (expression int / (expression int f2i (swiz x (var_ref gl_FragCo (declare (temporary ) int compiler_temp@2) (declare (temporary ) int compiler_temp@2) (assign (x) (var_ref compiler_temp@2) (expression int / (expression int f2i (swiz y (var_ref gl_Frag (assign (x) (var_ref compiler_temp@2) (expression int / (expression int f2i (swiz y (var_ref gl_Frag (if (expression bool == (expression int % (expression int + (var_ref compiler_temp) (var_ref compiler_ (if (expression bool == (expression int % (expression int + (var_ref compiler_temp) (var_ref compiler_ (assign (xy) (var_ref colord) (constant dvec2 (1.000000 0.0)) ) (assign (xy) (var_ref colord) (constant dvec2 (1.000000 0.0)) ) ) ) ( ( (assign (xy) (var_ref colord) (constant dvec2 (0.0 1.000000)) ) (assign (xy) (var_ref colord) (constant dvec2 (0.0 1.000000)) ) )) )) (declare (temporary ) vec4 compiler_temp@3) (declare (temporary ) vec4 compiler_temp@3) (assign (zw) (var_ref compiler_temp@3) (constant vec2 (0.000000 1.000000)) ) (assign (zw) (var_ref compiler_temp@3) (constant vec2 (0.000000 1.000000)) ) (assign (xy) (var_ref compiler_temp@3) (expression vec2 d2f (var_ref colord) ) ) (assign (xy) (var_ref compiler_temp@3) (expression vec2 d2f (var_ref colord) ) ) (assign (xyzw) (var_ref color) (var_ref compiler_temp@3) ) (assign (xyzw) (var_ref color) (var_ref compiler_temp@3) ) )) )) ) ) ) ) NIR (SSA form) for fragment shader: NIR (SSA form) for fragment shader: shader: MESA_SHADER_FRAGMENT shader: MESA_SHADER_FRAGMENT name: GLSL3 name: GLSL3 inputs: 0 inputs: 0 outputs: 0 outputs: 0 uniforms: 16 uniforms: 16 shared: 0 shared: 0 decl_var uniform INTERP_MODE_NONE vec4 gl_FbWposYTransform (0, 0, 0) decl_var uniform INTERP_MODE_NONE vec4 gl_FbWposYTransform (0, 0, 0) decl_var shader_out INTERP_MODE_NONE vec4 color (FRAG_RESULT_DATA0.xyzw, 8, 0) decl_var shader_out INTERP_MODE_NONE vec4 color (FRAG_RESULT_DATA0.xyzw, 8, 0) decl_function main (0 params) decl_function main (0 params) impl main { impl main { block block_0: block block_0: /* preds: */ /* preds: */ vec1 32 ssa_0 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_0 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_1 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_1 = load_const (0x3f800000 /* 1.000000 */) vec4 32 ssa_2 = intrinsic load_frag_coord () () vec4 32 ssa_2 = intrinsic load_frag_coord () () vec4 32 ssa_3 = intrinsic load_uniform (ssa_0) (0, 16, 160) /* base=0 */ /* range=16 */ /* type=floa vec4 32 ssa_3 = intrinsic load_uniform (ssa_0) (0, 16, 160) /* base=0 */ /* range=16 */ /* type=floa vec4 32 ssa_4 = load_const (0x3f000000 /* 0.500000 */, 0x3f000000 /* 0.500000 */, 0x00000000 /* 0.00 vec4 32 ssa_4 = load_const (0x3f000000 /* 0.500000 */, 0x3f000000 /* 0.500000 */, 0x00000000 /* 0.00 vec1 32 ssa_5 = fadd ssa_2.x, ssa_4.x vec1 32 ssa_5 = fadd ssa_2.x, ssa_4.x vec1 32 ssa_6 = fadd ssa_2.y, ssa_4.y vec1 32 ssa_6 = fadd ssa_2.y, ssa_4.y vec1 32 ssa_7 = ffma ssa_6, ssa_3.x, ssa_3.y vec1 32 ssa_7 = ffma ssa_6, ssa_3.x, ssa_3.y vec1 32 ssa_8 = f2i32 ssa_5 vec1 32 ssa_8 = f2i32 ssa_5 vec1 32 ssa_9 = load_const (0x84210843 /* -0.000000 */) vec1 32 ssa_9 = load_const (0x84210843 /* -0.000000 */) vec1 32 ssa_10 = imul_high ssa_8, ssa_9 vec1 32 ssa_10 = imul_high ssa_8, ssa_9 vec1 32 ssa_11 = iadd ssa_10, ssa_8 vec1 32 ssa_11 = iadd ssa_10, ssa_8 vec1 32 ssa_12 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_12 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_13 = ishr ssa_11, ssa_12 vec1 32 ssa_13 = ishr ssa_11, ssa_12 vec1 32 ssa_14 = load_const (0x0000001f /* 0.000000 */) vec1 32 ssa_14 = load_const (0x0000001f /* 0.000000 */) vec1 32 ssa_15 = ushr ssa_13, ssa_14 vec1 32 ssa_15 = ushr ssa_13, ssa_14 vec1 32 ssa_16 = iadd ssa_13, ssa_15 vec1 32 ssa_16 = iadd ssa_13, ssa_15 vec1 32 ssa_17 = f2i32 ssa_7 vec1 32 ssa_17 = f2i32 ssa_7 vec1 32 ssa_18 = imul_high ssa_17, ssa_9 vec1 32 ssa_18 = imul_high ssa_17, ssa_9 vec1 32 ssa_19 = iadd ssa_18, ssa_17 vec1 32 ssa_19 = iadd ssa_18, ssa_17 vec1 32 ssa_20 = ishr ssa_19, ssa_12 vec1 32 ssa_20 = ishr ssa_19, ssa_12 vec1 32 ssa_21 = ushr ssa_20, ssa_14 vec1 32 ssa_21 = ushr ssa_20, ssa_14 vec1 32 ssa_22 = iadd ssa_20, ssa_21 vec1 32 ssa_22 = iadd ssa_20, ssa_21 vec1 32 ssa_23 = iadd ssa_16, ssa_22 vec1 32 ssa_23 = iadd ssa_16, ssa_22 vec1 32 ssa_24 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_24 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_25 = iand ssa_23, ssa_24 vec1 32 ssa_25 = iand ssa_23, ssa_24 vec1 64 ssa_26 = load_const (0x3ff0000000000000 /* 1.000000 */) vec1 64 ssa_26 = load_const (0x3ff0000000000000 /* 1.000000 */) vec1 64 ssa_27 = load_const (0x 0 /* 0.000000 */) vec1 64 ssa_27 = load_const (0x 0 /* 0.000000 */) vec1 32 ssa_28 = ieq32 ssa_25, ssa_0 vec1 32 ssa_28 = ieq32 ssa_25, ssa_0 vec1 64 ssa_29 = b32csel ssa_28, ssa_26, ssa_27 vec1 64 ssa_29 = b32csel ssa_28, ssa_26, ssa_27 vec1 64 ssa_30 = b32csel ssa_28, ssa_27, ssa_26 vec1 64 ssa_30 = b32csel ssa_28, ssa_27, ssa_26 vec1 32 ssa_31 = f2f32 ssa_29 vec1 32 ssa_31 = f2f32 ssa_29 vec1 32 ssa_32 = f2f32 ssa_30 vec1 32 ssa_32 = f2f32 ssa_30 vec4 32 ssa_33 = vec4 ssa_31, ssa_32, ssa_0, ssa_1 vec4 32 ssa_33 = vec4 ssa_31, ssa_32, ssa_0, ssa_1 intrinsic store_output (ssa_33, ssa_0) (8, 15, 0, 160) /* base=8 */ /* wrmask=xyzw */ /* component=0 intrinsic store_output (ssa_33, ssa_0) (8, 15, 0, 160) /* base=8 */ /* wrmask=xyzw */ /* component=0 /* succs: block_1 */ /* succs: block_1 */ block block_1: block block_1: } } NIR (final form) for fragment shader: NIR (final form) for fragment shader: shader: MESA_SHADER_FRAGMENT shader: MESA_SHADER_FRAGMENT name: GLSL3 name: GLSL3 inputs: 0 inputs: 0 outputs: 0 outputs: 0 uniforms: 16 uniforms: 16 shared: 0 shared: 0 decl_var uniform INTERP_MODE_NONE vec4 gl_FbWposYTransform (0, 0, 0) decl_var uniform INTERP_MODE_NONE vec4 gl_FbWposYTransform (0, 0, 0) decl_var shader_out INTERP_MODE_NONE vec4 color (FRAG_RESULT_DATA0.xyzw, 8, 0) decl_var shader_out INTERP_MODE_NONE vec4 color (FRAG_RESULT_DATA0.xyzw, 8, 0) decl_function main (0 params) decl_function main (0 params) impl main { impl main { block block_0: block block_0: /* preds: */ /* preds: */ vec1 32 ssa_0 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_0 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_1 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_1 = load_const (0x3f800000 /* 1.000000 */) vec4 32 ssa_2 = intrinsic load_frag_coord () () vec4 32 ssa_2 = intrinsic load_frag_coord () () vec4 32 ssa_3 = intrinsic load_uniform (ssa_0) (0, 16, 160) /* base=0 */ /* range=16 */ /* type=floa vec4 32 ssa_3 = intrinsic load_uniform (ssa_0) (0, 16, 160) /* base=0 */ /* range=16 */ /* type=floa vec4 32 ssa_4 = load_const (0x3f000000 /* 0.500000 */, 0x3f000000 /* 0.500000 */, 0x00000000 /* 0.00 vec4 32 ssa_4 = load_const (0x3f000000 /* 0.500000 */, 0x3f000000 /* 0.500000 */, 0x00000000 /* 0.00 vec1 32 ssa_5 = fadd ssa_2.x, ssa_4.x vec1 32 ssa_5 = fadd ssa_2.x, ssa_4.x vec1 32 ssa_6 = fadd ssa_2.y, ssa_4.y vec1 32 ssa_6 = fadd ssa_2.y, ssa_4.y vec1 32 ssa_7 = ffma ssa_6, ssa_3.x, ssa_3.y vec1 32 ssa_7 = ffma ssa_6, ssa_3.x, ssa_3.y vec1 32 ssa_8 = f2i32 ssa_5 vec1 32 ssa_8 = f2i32 ssa_5 vec1 32 ssa_9 = load_const (0x84210843 /* -0.000000 */) vec1 32 ssa_9 = load_const (0x84210843 /* -0.000000 */) vec1 32 ssa_10 = imul_high ssa_8, ssa_9 vec1 32 ssa_10 = imul_high ssa_8, ssa_9 vec1 32 ssa_11 = iadd ssa_10, ssa_8 vec1 32 ssa_11 = iadd ssa_10, ssa_8 vec1 32 ssa_12 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_12 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_13 = ishr ssa_11, ssa_12 vec1 32 ssa_13 = ishr ssa_11, ssa_12 vec1 32 ssa_14 = load_const (0x0000001f /* 0.000000 */) vec1 32 ssa_14 = load_const (0x0000001f /* 0.000000 */) vec1 32 ssa_15 = ushr ssa_13, ssa_14 vec1 32 ssa_15 = ushr ssa_13, ssa_14 vec1 32 ssa_16 = iadd ssa_13, ssa_15 vec1 32 ssa_16 = iadd ssa_13, ssa_15 vec1 32 ssa_17 = f2i32 ssa_7 vec1 32 ssa_17 = f2i32 ssa_7 vec1 32 ssa_18 = imul_high ssa_17, ssa_9 vec1 32 ssa_18 = imul_high ssa_17, ssa_9 vec1 32 ssa_19 = iadd ssa_18, ssa_17 vec1 32 ssa_19 = iadd ssa_18, ssa_17 vec1 32 ssa_20 = ishr ssa_19, ssa_12 vec1 32 ssa_20 = ishr ssa_19, ssa_12 vec1 32 ssa_21 = ushr ssa_20, ssa_14 vec1 32 ssa_21 = ushr ssa_20, ssa_14 vec1 32 ssa_22 = iadd ssa_20, ssa_21 vec1 32 ssa_22 = iadd ssa_20, ssa_21 vec1 32 ssa_23 = iadd ssa_16, ssa_22 vec1 32 ssa_23 = iadd ssa_16, ssa_22 vec1 32 ssa_24 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_24 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_25 = iand ssa_23, ssa_24 vec1 32 ssa_25 = iand ssa_23, ssa_24 vec1 64 ssa_26 = load_const (0x3ff0000000000000 /* 1.000000 */) vec1 64 ssa_26 = load_const (0x3ff0000000000000 /* 1.000000 */) vec1 64 ssa_27 = load_const (0x 0 /* 0.000000 */) vec1 64 ssa_27 = load_const (0x 0 /* 0.000000 */) vec1 32 ssa_28 = ieq32 ssa_25, ssa_0 vec1 32 ssa_28 = ieq32 ssa_25, ssa_0 vec1 64 ssa_29 = b32csel ssa_28, ssa_26, ssa_27 vec1 64 ssa_29 = b32csel ssa_28, ssa_26, ssa_27 vec1 64 ssa_30 = b32csel ssa_28, ssa_27, ssa_26 vec1 64 ssa_30 = b32csel ssa_28, ssa_27, ssa_26 vec1 32 ssa_31 = f2f32 ssa_29 vec1 32 ssa_31 = f2f32 ssa_29 vec1 32 ssa_32 = f2f32 ssa_30 vec1 32 ssa_32 = f2f32 ssa_30 vec4 32 ssa_33 = vec4 ssa_31, ssa_32, ssa_0, ssa_1 vec4 32 ssa_33 = vec4 ssa_31, ssa_32, ssa_0, ssa_1 intrinsic store_output (ssa_33, ssa_0) (8, 15, 0, 160) /* base=8 */ /* wrmask=xyzw */ /* component=0 intrinsic store_output (ssa_33, ssa_0) (8, 15, 0, 160) /* base=8 */ /* wrmask=xyzw */ /* component=0 /* succs: block_1 */ /* succs: block_1 */ block block_1: block block_1: } } Native code for unnamed fragment shader GLSL3 (sha1 b0586b0bb37abb6610a16ce58846a9d25e3a9de1) Native code for unnamed fragment shader GLSL3 (sha1 b0586b0bb37abb6610a16ce58846a9d25e3a9de1) SIMD8 shader: 33 instructions. 0 loops. 280 cycles. 0:0 spills:fills, 1 sends, scheduled with mode top-down. SIMD8 shader: 33 instructions. 0 loops. 280 cycles. 0:0 spills:fills, 1 sends, scheduled with mode top-down. START B0 (280 cycles) START B0 (280 cycles) add(16) g5<1>UW g1.4<1,4,0>UW 0x11001010V { align1 WE_all 1H }; add(16) g5<1>UW g1.4<1,4,0>UW 0x11001010V { align1 WE_all 1H }; dim(1) g22<1>DF 0x3ff0000000000000F /* 1F */ { align1 WE_all 1N }; dim(1) g22<1>DF 0x3ff0000000000000F /* 1F */ { align1 WE_all 1N }; dim(1) g23<1>DF 0x0F /* 0F */ { align1 WE_all 1N }; dim(1) g23<1>DF 0x0F /* 0F */ { align1 WE_all 1N }; mov(8) g126<1>F 0x0VF /* [0F, 0F, 0F, 0F]VF */ { align1 1Q compacted }; mov(8) g126<1>F 0x0VF /* [0F, 0F, 0F, 0F]VF */ { align1 1Q compacted }; mov(8) g127<1>F 0x3f800000F /* 1F */ { align1 1Q }; mov(8) g127<1>F 0x3f800000F /* 1F */ { align1 1Q }; mov(8) g2<1>F g5<8,4,1>UW { align1 1Q }; mov(8) g2<1>F g5<8,4,1>UW { align1 1Q }; mov(8) g3<1>F g5.4<8,4,1>UW { align1 1Q }; mov(8) g3<1>F g5.4<8,4,1>UW { align1 1Q }; add(8) g6<1>F g2<8,8,1>F 0x3f000000F /* 0.5F */ { align1 1Q }; add(8) g6<1>F g2<8,8,1>F 0x3f000000F /* 0.5F */ { align1 1Q }; add(8) g7<1>F g3<8,8,1>F 0x3f000000F /* 0.5F */ { align1 1Q }; add(8) g7<1>F g3<8,8,1>F 0x3f000000F /* 0.5F */ { align1 1Q }; mov(8) g9<1>D g6<8,8,1>F { align1 1Q compacted }; mov(8) g9<1>D g6<8,8,1>F { align1 1Q compacted }; mad(8) g8<1>F g4.1<0,1,0>F g4.0<0,1,0>F g7<4,4,1>F { align16 1Q }; mad(8) g8<1>F g4.1<0,1,0>F g4.0<0,1,0>F g7<4,4,1>F { align16 1Q }; mul(8) acc0<1>D g9<8,8,1>D -2078209981D { align1 1Q }; mul(8) acc0<1>D g9<8,8,1>D -2078209981D { align1 1Q }; mov(8) g15<1>D g8<8,8,1>F { align1 1Q compacted }; mov(8) g15<1>D g8<8,8,1>F { align1 1Q compacted }; mach(8) g10<1>D g9<8,8,1>D -2078209981D { align1 1Q AccWrEnable }; mach(8) g10<1>D g9<8,8,1>D -2078209981D { align1 1Q AccWrEnable }; add(8) g11<1>D g10<8,8,1>D g9<8,8,1>D { align1 1Q compacted }; add(8) g11<1>D g10<8,8,1>D g9<8,8,1>D { align1 1Q compacted }; mul(8) acc0<1>D g15<8,8,1>D -2078209981D { align1 1Q }; mul(8) acc0<1>D g15<8,8,1>D -2078209981D { align1 1Q }; asr(8) g12<1>D g11<8,8,1>D 0x00000004UD { align1 1Q }; asr(8) g12<1>D g11<8,8,1>D 0x00000004UD { align1 1Q }; mach(8) g16<1>D g15<8,8,1>D -2078209981D { align1 1Q AccWrEnable }; mach(8) g16<1>D g15<8,8,1>D -2078209981D { align1 1Q AccWrEnable }; shr(8) g13<1>UD g12<8,8,1>UD 0x0000001fUD { align1 1Q compacted }; shr(8) g13<1>UD g12<8,8,1>UD 0x0000001fUD { align1 1Q compacted }; add(8) g17<1>D g16<8,8,1>D g15<8,8,1>D { align1 1Q compacted }; add(8) g17<1>D g16<8,8,1>D g15<8,8,1>D { align1 1Q compacted }; add(8) g14<1>D g12<8,8,1>D g13<8,8,1>D { align1 1Q compacted }; add(8) g14<1>D g12<8,8,1>D g13<8,8,1>D { align1 1Q compacted }; asr(8) g18<1>D g17<8,8,1>D 0x00000004UD { align1 1Q }; asr(8) g18<1>D g17<8,8,1>D 0x00000004UD { align1 1Q }; shr(8) g19<1>UD g18<8,8,1>UD 0x0000001fUD { align1 1Q compacted }; shr(8) g19<1>UD g18<8,8,1>UD 0x0000001fUD { align1 1Q compacted }; add(8) g20<1>D g18<8,8,1>D g19<8,8,1>D { align1 1Q compacted }; add(8) g20<1>D g18<8,8,1>D g19<8,8,1>D { align1 1Q compacted }; add(8) g21<1>D g14<8,8,1>D g20<8,8,1>D { align1 1Q compacted }; add(8) g21<1>D g14<8,8,1>D g20<8,8,1>D { align1 1Q compacted }; and.z.f0.0(8) null<1>UD g21<8,8,1>UD 0x00000001UD { align1 1Q compacted }; and.z.f0.0(8) null<1>UD g21<8,8,1>UD 0x00000001UD { align1 1Q compacted }; (+f0.0) sel(8) g2<1>DF g22<0,1,0>DF g23<0,1,0>DF { align1 1Q }; (+f0.0) sel(8) g2<1>DF g22<0,1,0>DF g23<0,1,0>DF { align1 1Q }; (+f0.0) sel(8) g4<1>DF g23<0,1,0>DF g22<0,1,0>DF { align1 1Q }; (+f0.0) sel(8) g4<1>DF g23<0,1,0>DF g22<0,1,0>DF { align1 1Q }; mov(8) g24<2>F g2<4,4,1>DF { align1 1Q }; mov(8) g24<2>F g2<4,4,1>DF { align1 1Q }; mov(8) g26<2>F g4<4,4,1>DF { align1 1Q }; mov(8) g26<2>F g4<4,4,1>DF { align1 1Q }; mov(8) g124<1>UD g24<8,4,2>UD { align1 1Q }; mov(8) g124<1>UD g24<8,4,2>UD { align1 1Q }; mov(8) g125<1>UD g26<8,4,2>UD { align1 1Q }; mov(8) g125<1>UD g26<8,4,2>UD { align1 1Q }; sendc(8) null<1>UW g124<8,8,1>UD 0x88031400 sendc(8) null<1>UW g124<8,8,1>UD 0x88031400 render MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 4 rlen 0 { align1 1Q EOT render MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 4 rlen 0 { align1 1Q EOT END B0 END B0 Native code for unnamed fragment shader GLSL3 (sha1 4dbe0b229486c32dc4758d0202222e38a3f36fb8) | Native code for unnamed fragment shader GLSL3 (sha1 bd61805d23e5fc17676d8af8be1255775d4823ff) SIMD16 shader: 44 instructions. 0 loops. 386 cycles. 0:0 spills:fills, 1 sends, scheduled with mode top-down | SIMD16 shader: 45 instructions. 0 loops. 388 cycles. 0:0 spills:fills, 1 sends, scheduled with mode top-down START B0 (386 cycles) | START B0 (388 cycles) add(16) g4<1>UW g1.4<2,4,0>UW 0x10101010V { align1 1H }; add(16) g4<1>UW g1.4<2,4,0>UW 0x10101010V { align1 1H }; add(16) g7<1>UW g1.5<2,4,0>UW 0x11001100V { align1 1H }; add(16) g7<1>UW g1.5<2,4,0>UW 0x11001100V { align1 1H }; > mov(1) g23<1>D 2078209981D { align1 WE_all 1N }; dim(1) g39<1>DF 0x3ff0000000000000F /* 1F */ { align1 WE_all 1N }; dim(1) g39<1>DF 0x3ff0000000000000F /* 1F */ { align1 WE_all 1N }; dim(1) g40<1>DF 0x0F /* 0F */ { align1 WE_all 1N }; dim(1) g40<1>DF 0x0F /* 0F */ { align1 WE_all 1N }; mov(16) g124<1>F 0x0VF /* [0F, 0F, 0F, 0F]VF */ { align1 1H compacted }; mov(16) g124<1>F 0x0VF /* [0F, 0F, 0F, 0F]VF */ { align1 1H compacted }; mov(16) g126<1>F 0x3f800000F /* 1F */ { align1 1H }; mov(16) g126<1>F 0x3f800000F /* 1F */ { align1 1H }; mov(16) g2<1>F g4<8,8,1>UW { align1 1H }; mov(16) g2<1>F g4<8,8,1>UW { align1 1H }; mov(16) g4<1>F g7<8,8,1>UW { align1 1H }; mov(16) g4<1>F g7<8,8,1>UW { align1 1H }; add(16) g7<1>F g2<8,8,1>F 0x3f000000F /* 0.5F */ { align1 1H }; add(16) g7<1>F g2<8,8,1>F 0x3f000000F /* 0.5F */ { align1 1H }; add(16) g9<1>F g4<8,8,1>F 0x3f000000F /* 0.5F */ { align1 1H }; add(16) g9<1>F g4<8,8,1>F 0x3f000000F /* 0.5F */ { align1 1H }; mov(16) g13<1>D g7<8,8,1>F { align1 1H compacted }; mov(16) g13<1>D g7<8,8,1>F { align1 1H compacted }; mad(16) g11<1>F g6.1<0,1,0>F g6.0<0,1,0>F g9<4,4,1>F { align16 1H }; mad(16) g11<1>F g6.1<0,1,0>F g6.0<0,1,0>F g9<4,4,1>F { align16 1H }; mul(8) acc0<1>D g13<8,8,1>D -2078209981D { align1 1Q }; | mul(8) acc0<1>D g13<8,8,1>D -g23<0,1,0>D { align1 1Q compacted }; mov(16) g25<1>D g11<8,8,1>F { align1 1H compacted }; mov(16) g25<1>D g11<8,8,1>F { align1 1H compacted }; mach(8) g15<1>D g13<8,8,1>D -2078209981D { align1 1Q AccWrEnable }; mach(8) g15<1>D g13<8,8,1>D -2078209981D { align1 1Q AccWrEnable }; mul(8) acc0<1>D g14<8,8,1>D -2078209981D { align1 2Q }; | mul(8) acc0<1>D g14<8,8,1>D -g23<0,1,0>D { align1 2Q compacted }; mach(8) g16<1>D g14<8,8,1>D -2078209981D { align1 2Q AccWrEnable }; mach(8) g16<1>D g14<8,8,1>D -2078209981D { align1 2Q AccWrEnable }; add(16) g17<1>D g15<8,8,1>D g13<8,8,1>D { align1 1H compacted }; add(16) g17<1>D g15<8,8,1>D g13<8,8,1>D { align1 1H compacted }; mul(8) acc0<1>D g25<8,8,1>D -2078209981D { align1 1Q }; | mul(8) acc0<1>D g25<8,8,1>D -g23<0,1,0>D { align1 1Q compacted }; asr(16) g19<1>D g17<8,8,1>D 0x00000004UD { align1 1H }; asr(16) g19<1>D g17<8,8,1>D 0x00000004UD { align1 1H }; mach(8) g27<1>D g25<8,8,1>D -2078209981D { align1 1Q AccWrEnable }; mach(8) g27<1>D g25<8,8,1>D -2078209981D { align1 1Q AccWrEnable }; shr(16) g21<1>UD g19<8,8,1>UD 0x0000001fUD { align1 1H compacted }; shr(16) g21<1>UD g19<8,8,1>UD 0x0000001fUD { align1 1H compacted }; mul(8) acc0<1>D g26<8,8,1>D -2078209981D { align1 2Q }; | mul(8) acc0<1>D g26<8,8,1>D -g23<0,1,0>D { align1 2Q compacted }; add(16) g23<1>D g19<8,8,1>D g21<8,8,1>D { align1 1H compacted }; add(16) g23<1>D g19<8,8,1>D g21<8,8,1>D { align1 1H compacted }; mach(8) g28<1>D g26<8,8,1>D -2078209981D { align1 2Q AccWrEnable }; mach(8) g28<1>D g26<8,8,1>D -2078209981D { align1 2Q AccWrEnable }; add(16) g29<1>D g27<8,8,1>D g25<8,8,1>D { align1 1H compacted }; add(16) g29<1>D g27<8,8,1>D g25<8,8,1>D { align1 1H compacted }; asr(16) g31<1>D g29<8,8,1>D 0x00000004UD { align1 1H }; asr(16) g31<1>D g29<8,8,1>D 0x00000004UD { align1 1H }; shr(16) g33<1>UD g31<8,8,1>UD 0x0000001fUD { align1 1H compacted }; shr(16) g33<1>UD g31<8,8,1>UD 0x0000001fUD { align1 1H compacted }; add(16) g35<1>D g31<8,8,1>D g33<8,8,1>D { align1 1H compacted }; add(16) g35<1>D g31<8,8,1>D g33<8,8,1>D { align1 1H compacted }; add(16) g37<1>D g23<8,8,1>D g35<8,8,1>D { align1 1H compacted }; add(16) g37<1>D g23<8,8,1>D g35<8,8,1>D { align1 1H compacted }; and.z.f0.0(16) null<1>UD g37<8,8,1>UD 0x00000001UD { align1 1H compacted }; and.z.f0.0(16) null<1>UD g37<8,8,1>UD 0x00000001UD { align1 1H compacted }; (+f0.0) sel(8) g6<1>DF g39<0,1,0>DF g40<0,1,0>DF { align1 1Q }; (+f0.0) sel(8) g6<1>DF g39<0,1,0>DF g40<0,1,0>DF { align1 1Q }; (+f0.0) sel(8) g2<1>DF g39<0,1,0>DF g40<0,1,0>DF { align1 2Q }; (+f0.0) sel(8) g2<1>DF g39<0,1,0>DF g40<0,1,0>DF { align1 2Q }; (+f0.0) sel(8) g8<1>DF g40<0,1,0>DF g39<0,1,0>DF { align1 1Q }; (+f0.0) sel(8) g8<1>DF g40<0,1,0>DF g39<0,1,0>DF { align1 1Q }; (+f0.0) sel(8) g4<1>DF g40<0,1,0>DF g39<0,1,0>DF { align1 2Q }; (+f0.0) sel(8) g4<1>DF g40<0,1,0>DF g39<0,1,0>DF { align1 2Q }; mov(8) g41<2>F g6<4,4,1>DF { align1 1Q }; mov(8) g41<2>F g6<4,4,1>DF { align1 1Q }; mov(8) g43<2>F g2<4,4,1>DF { align1 2Q }; mov(8) g43<2>F g2<4,4,1>DF { align1 2Q }; mov(8) g45<2>F g8<4,4,1>DF { align1 1Q }; mov(8) g45<2>F g8<4,4,1>DF { align1 1Q }; mov(8) g47<2>F g4<4,4,1>DF { align1 2Q }; mov(8) g47<2>F g4<4,4,1>DF { align1 2Q }; mov(8) g120<1>UD g41<8,4,2>UD { align1 1Q }; mov(8) g120<1>UD g41<8,4,2>UD { align1 1Q }; mov(8) g121<1>UD g43<8,4,2>UD { align1 2Q }; mov(8) g121<1>UD g43<8,4,2>UD { align1 2Q }; mov(8) g122<1>UD g45<8,4,2>UD { align1 1Q }; mov(8) g122<1>UD g45<8,4,2>UD { align1 1Q }; mov(8) g123<1>UD g47<8,4,2>UD { align1 2Q }; mov(8) g123<1>UD g47<8,4,2>UD { align1 2Q }; sendc(16) null<1>UW g120<8,8,1>UD 0x90031000 sendc(16) null<1>UW g120<8,8,1>UD 0x90031000 render MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 8 rlen 0 { align1 1H EOT render MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 8 rlen 0 { align1 1H EOT END B0 END B0 NIR (SSA form) for fragment shader: NIR (SSA form) for fragment shader: shader: MESA_SHADER_FRAGMENT shader: MESA_SHADER_FRAGMENT name: BLORP-clear name: BLORP-clear inputs: 0 inputs: 0 outputs: 0 outputs: 0 uniforms: 0 uniforms: 0 shared: 0 shared: 0 decl_var shader_in INTERP_MODE_FLAT vec4 clear_color (VARYING_SLOT_VAR0.xyzw, 31, 0) decl_var shader_in INTERP_MODE_FLAT vec4 clear_color (VARYING_SLOT_VAR0.xyzw, 31, 0) decl_var shader_out INTERP_MODE_NONE vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 4, 0) decl_var shader_out INTERP_MODE_NONE vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 4, 0) decl_function main (0 params) decl_function main (0 params) impl main { impl main { block block_0: block block_0: /* preds: */ /* preds: */ vec1 32 ssa_0 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_0 = load_const (0x00000000 /* 0.000000 */) vec4 32 ssa_1 = intrinsic load_input (ssa_0) (31, 0, 160) /* base=31 */ /* component=0 */ /* type=fl vec4 32 ssa_1 = intrinsic load_input (ssa_0) (31, 0, 160) /* base=31 */ /* component=0 */ /* type=fl intrinsic store_output (ssa_1, ssa_0) (4, 15, 0, 160) /* base=4 */ /* wrmask=xyzw */ /* component=0 intrinsic store_output (ssa_1, ssa_0) (4, 15, 0, 160) /* base=4 */ /* wrmask=xyzw */ /* component=0 /* succs: block_1 */ /* succs: block_1 */ block block_1: block block_1: } } NIR (final form) for fragment shader: NIR (final form) for fragment shader: shader: MESA_SHADER_FRAGMENT shader: MESA_SHADER_FRAGMENT name: BLORP-clear name: BLORP-clear inputs: 0 inputs: 0 outputs: 0 outputs: 0 uniforms: 0 uniforms: 0 shared: 0 shared: 0 decl_var shader_in INTERP_MODE_FLAT vec4 clear_color (VARYING_SLOT_VAR0.xyzw, 31, 0) decl_var shader_in INTERP_MODE_FLAT vec4 clear_color (VARYING_SLOT_VAR0.xyzw, 31, 0) decl_var shader_out INTERP_MODE_NONE vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 4, 0) decl_var shader_out INTERP_MODE_NONE vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 4, 0) decl_function main (0 params) decl_function main (0 params) impl main { impl main { block block_0: block block_0: /* preds: */ /* preds: */ vec1 32 ssa_0 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_0 = load_const (0x00000000 /* 0.000000 */) vec4 32 ssa_1 = intrinsic load_input (ssa_0) (31, 0, 160) /* base=31 */ /* component=0 */ /* type=fl vec4 32 ssa_1 = intrinsic load_input (ssa_0) (31, 0, 160) /* base=31 */ /* component=0 */ /* type=fl intrinsic store_output (ssa_1, ssa_0) (4, 15, 0, 160) /* base=4 */ /* wrmask=xyzw */ /* component=0 intrinsic store_output (ssa_1, ssa_0) (4, 15, 0, 160) /* base=4 */ /* wrmask=xyzw */ /* component=0 /* succs: block_1 */ /* succs: block_1 */ block block_1: block block_1: } } Native code for unnamed fragment shader BLORP-clear (sha1 59a7767c66f4e77a1b9e860d0b20c65b89004f2f) Native code for unnamed fragment shader BLORP-clear (sha1 59a7767c66f4e77a1b9e860d0b20c65b89004f2f) SIMD16 shader: 2 instructions. 0 loops. 0 cycles. 0:0 spills:fills, 1 sends, scheduled with mode top-down. P SIMD16 shader: 2 instructions. 0 loops. 0 cycles. 0:0 spills:fills, 1 sends, scheduled with mode top-down. P START B0 (0 cycles) START B0 (0 cycles) mov(4) g114<1>F g2.3<8,2,4>F { align1 WE_all 1N }; mov(4) g114<1>F g2.3<8,2,4>F { align1 WE_all 1N }; sendc(16) null<1>UW g114<8,8,1>F 0x82031100 sendc(16) null<1>UW g114<8,8,1>F 0x82031100 render MsgDesc: RT write SIMD16/RepData LastRT Surface = 0 mlen 1 rlen 0 { align render MsgDesc: RT write SIMD16/RepData LastRT Surface = 0 mlen 1 rlen 0 { align END B0 END B0 NIR (SSA form) for fragment shader: NIR (SSA form) for fragment shader: shader: MESA_SHADER_FRAGMENT shader: MESA_SHADER_FRAGMENT name: BLORP-blit name: BLORP-blit inputs: 0 inputs: 0 outputs: 0 outputs: 0 uniforms: 0 uniforms: 0 shared: 0 shared: 0 decl_var shader_in INTERP_MODE_FLAT vec4 coord_transform (VARYING_SLOT_VAR3.xyzw, 34, 0) decl_var shader_in INTERP_MODE_FLAT vec4 coord_transform (VARYING_SLOT_VAR3.xyzw, 34, 0) decl_var shader_in INTERP_MODE_FLAT uint src_z (VARYING_SLOT_VAR5.z, 36, 0) decl_var shader_in INTERP_MODE_FLAT uint src_z (VARYING_SLOT_VAR5.z, 36, 0) decl_var shader_out INTERP_MODE_NONE vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 4, 0) decl_var shader_out INTERP_MODE_NONE vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 4, 0) decl_function main (0 params) decl_function main (0 params) impl main { impl main { block block_0: block block_0: /* preds: */ /* preds: */ vec4 32 ssa_0 = intrinsic load_frag_coord () () vec4 32 ssa_0 = intrinsic load_frag_coord () () vec1 32 ssa_1 = ftrunc ssa_0.x vec1 32 ssa_1 = ftrunc ssa_0.x vec1 32 ssa_2 = ftrunc ssa_0.y vec1 32 ssa_2 = ftrunc ssa_0.y vec1 32 ssa_3 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3 = load_const (0x00000000 /* 0.000000 */) vec4 32 ssa_4 = intrinsic load_input (ssa_3) (34, 0, 160) /* base=34 */ /* component=0 */ /* type=fl vec4 32 ssa_4 = intrinsic load_input (ssa_3) (34, 0, 160) /* base=34 */ /* component=0 */ /* type=fl vec1 32 ssa_5 = ffma ssa_1, ssa_4.x, ssa_4.y vec1 32 ssa_5 = ffma ssa_1, ssa_4.x, ssa_4.y vec1 32 ssa_6 = ffma ssa_2, ssa_4.z, ssa_4.w vec1 32 ssa_6 = ffma ssa_2, ssa_4.z, ssa_4.w vec1 32 ssa_7 = f2i32 ssa_5 vec1 32 ssa_7 = f2i32 ssa_5 vec1 32 ssa_8 = f2i32 ssa_6 vec1 32 ssa_8 = f2i32 ssa_6 vec1 32 ssa_9 = intrinsic load_input (ssa_3) (36, 2, 36) /* base=36 */ /* component=2 */ /* type=uin vec1 32 ssa_9 = intrinsic load_input (ssa_3) (36, 2, 36) /* base=36 */ /* component=2 */ /* type=uin vec3 32 ssa_10 = vec3 ssa_7, ssa_8, ssa_9 vec3 32 ssa_10 = vec3 ssa_7, ssa_8, ssa_9 vec4 32 ssa_11 = txf ssa_10 (coord), ssa_3 (lod), 0 (texture), 0 (sampler) vec4 32 ssa_11 = txf ssa_10 (coord), ssa_3 (lod), 0 (texture), 0 (sampler) intrinsic store_output (ssa_11, ssa_3) (4, 15, 0, 160) /* base=4 */ /* wrmask=xyzw */ /* component=0 intrinsic store_output (ssa_11, ssa_3) (4, 15, 0, 160) /* base=4 */ /* wrmask=xyzw */ /* component=0 /* succs: block_1 */ /* succs: block_1 */ block block_1: block block_1: } } NIR (final form) for fragment shader: NIR (final form) for fragment shader: shader: MESA_SHADER_FRAGMENT shader: MESA_SHADER_FRAGMENT name: BLORP-blit name: BLORP-blit inputs: 0 inputs: 0 outputs: 0 outputs: 0 uniforms: 0 uniforms: 0 shared: 0 shared: 0 decl_var shader_in INTERP_MODE_FLAT vec4 coord_transform (VARYING_SLOT_VAR3.xyzw, 34, 0) decl_var shader_in INTERP_MODE_FLAT vec4 coord_transform (VARYING_SLOT_VAR3.xyzw, 34, 0) decl_var shader_in INTERP_MODE_FLAT uint src_z (VARYING_SLOT_VAR5.z, 36, 0) decl_var shader_in INTERP_MODE_FLAT uint src_z (VARYING_SLOT_VAR5.z, 36, 0) decl_var shader_out INTERP_MODE_NONE vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 4, 0) decl_var shader_out INTERP_MODE_NONE vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 4, 0) decl_function main (0 params) decl_function main (0 params) impl main { impl main { block block_0: block block_0: /* preds: */ /* preds: */ vec4 32 ssa_0 = intrinsic load_frag_coord () () vec4 32 ssa_0 = intrinsic load_frag_coord () () vec1 32 ssa_1 = ftrunc ssa_0.x vec1 32 ssa_1 = ftrunc ssa_0.x vec1 32 ssa_2 = ftrunc ssa_0.y vec1 32 ssa_2 = ftrunc ssa_0.y vec1 32 ssa_3 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3 = load_const (0x00000000 /* 0.000000 */) vec4 32 ssa_4 = intrinsic load_input (ssa_3) (34, 0, 160) /* base=34 */ /* component=0 */ /* type=fl vec4 32 ssa_4 = intrinsic load_input (ssa_3) (34, 0, 160) /* base=34 */ /* component=0 */ /* type=fl vec1 32 ssa_5 = ffma ssa_1, ssa_4.x, ssa_4.y vec1 32 ssa_5 = ffma ssa_1, ssa_4.x, ssa_4.y vec1 32 ssa_6 = ffma ssa_2, ssa_4.z, ssa_4.w vec1 32 ssa_6 = ffma ssa_2, ssa_4.z, ssa_4.w vec1 32 ssa_7 = f2i32 ssa_5 vec1 32 ssa_7 = f2i32 ssa_5 vec1 32 ssa_8 = f2i32 ssa_6 vec1 32 ssa_8 = f2i32 ssa_6 vec1 32 ssa_9 = intrinsic load_input (ssa_3) (36, 2, 36) /* base=36 */ /* component=2 */ /* type=uin vec1 32 ssa_9 = intrinsic load_input (ssa_3) (36, 2, 36) /* base=36 */ /* component=2 */ /* type=uin vec3 32 ssa_10 = vec3 ssa_7, ssa_8, ssa_9 vec3 32 ssa_10 = vec3 ssa_7, ssa_8, ssa_9 vec4 32 ssa_11 = txf ssa_10 (coord), ssa_3 (lod), 0 (texture), 0 (sampler) vec4 32 ssa_11 = txf ssa_10 (coord), ssa_3 (lod), 0 (texture), 0 (sampler) intrinsic store_output (ssa_11, ssa_3) (4, 15, 0, 160) /* base=4 */ /* wrmask=xyzw */ /* component=0 intrinsic store_output (ssa_11, ssa_3) (4, 15, 0, 160) /* base=4 */ /* wrmask=xyzw */ /* component=0 /* succs: block_1 */ /* succs: block_1 */ block block_1: block block_1: } } Native code for unnamed fragment shader BLORP-blit (sha1 b5f79f2448fbf948701e6cf3e32803d1cc0f2595) Native code for unnamed fragment shader BLORP-blit (sha1 b5f79f2448fbf948701e6cf3e32803d1cc0f2595) SIMD8 shader: 13 instructions. 0 loops. 290 cycles. 0:0 spills:fills, 2 sends, scheduled with mode top-down. SIMD8 shader: 13 instructions. 0 loops. 290 cycles. 0:0 spills:fills, 2 sends, scheduled with mode top-down. START B0 (290 cycles) START B0 (290 cycles) add(16) g6<1>UW g1.4<1,4,0>UW 0x11001010V { align1 WE_all 1H }; add(16) g6<1>UW g1.4<1,4,0>UW 0x11001010V { align1 WE_all 1H }; mov(8) g12<1>F 0x0VF /* [0F, 0F, 0F, 0F]VF */ { align1 1Q compacted }; mov(8) g12<1>F 0x0VF /* [0F, 0F, 0F, 0F]VF */ { align1 1Q compacted }; mov(8) g14<1>F g7.3<0,1,0>F { align1 1Q compacted }; mov(8) g14<1>F g7.3<0,1,0>F { align1 1Q compacted }; mov(8) g2<1>F g6<8,4,1>UW { align1 1Q }; mov(8) g2<1>F g6<8,4,1>UW { align1 1Q }; mov(8) g3<1>F g6.4<8,4,1>UW { align1 1Q }; mov(8) g3<1>F g6.4<8,4,1>UW { align1 1Q }; rndz(8) g7<1>F g2<8,8,1>F { align1 1Q compacted }; rndz(8) g7<1>F g2<8,8,1>F { align1 1Q compacted }; rndz(8) g8<1>F g3<8,8,1>F { align1 1Q compacted }; rndz(8) g8<1>F g3<8,8,1>F { align1 1Q compacted }; mad(8) g9<1>F g4.7<0,1,0>F g4.3<0,1,0>F g7<4,4,1>F { align16 1Q }; mad(8) g9<1>F g4.7<0,1,0>F g4.3<0,1,0>F g7<4,4,1>F { align16 1Q }; mad(8) g10<1>F g5.7<0,1,0>F g5.3<0,1,0>F g8<4,4,1>F { align16 1Q }; mad(8) g10<1>F g5.7<0,1,0>F g5.3<0,1,0>F g8<4,4,1>F { align16 1Q }; mov(8) g11<1>D g9<8,8,1>F { align1 1Q compacted }; mov(8) g11<1>D g9<8,8,1>F { align1 1Q compacted }; mov(8) g13<1>D g10<8,8,1>F { align1 1Q compacted }; mov(8) g13<1>D g10<8,8,1>F { align1 1Q compacted }; send(8) g124<1>UW g11<8,8,1>UD 0x08427001 send(8) g124<1>UW g11<8,8,1>UD 0x08427001 sampler MsgDesc: ld SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q }; sampler MsgDesc: ld SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q }; sendc(8) null<1>UW g124<8,8,1>UD 0x88031400 sendc(8) null<1>UW g124<8,8,1>UD 0x88031400 render MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 4 rlen 0 { align1 1Q EOT render MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 4 rlen 0 { align1 1Q EOT END B0 END B0 Native code for unnamed fragment shader BLORP-blit (sha1 204c150c4c5fc0acd48c4691ed822405c0a3c086) Native code for unnamed fragment shader BLORP-blit (sha1 204c150c4c5fc0acd48c4691ed822405c0a3c086) SIMD16 shader: 14 instructions. 0 loops. 306 cycles. 0:0 spills:fills, 2 sends, scheduled with mode top-down SIMD16 shader: 14 instructions. 0 loops. 306 cycles. 0:0 spills:fills, 2 sends, scheduled with mode top-down START B0 (306 cycles) START B0 (306 cycles) add(16) g4<1>UW g1.4<2,4,0>UW 0x10101010V { align1 1H }; add(16) g4<1>UW g1.4<2,4,0>UW 0x10101010V { align1 1H }; add(16) g8<1>UW g1.5<2,4,0>UW 0x11001100V { align1 1H }; add(16) g8<1>UW g1.5<2,4,0>UW 0x11001100V { align1 1H }; mov(16) g12<1>F 0x0VF /* [0F, 0F, 0F, 0F]VF */ { align1 1H compacted }; mov(16) g12<1>F 0x0VF /* [0F, 0F, 0F, 0F]VF */ { align1 1H compacted }; mov(16) g16<1>F g9.3<0,1,0>F { align1 1H compacted }; mov(16) g16<1>F g9.3<0,1,0>F { align1 1H compacted }; mov(16) g2<1>F g4<8,8,1>UW { align1 1H }; mov(16) g2<1>F g4<8,8,1>UW { align1 1H }; mov(16) g4<1>F g8<8,8,1>UW { align1 1H }; mov(16) g4<1>F g8<8,8,1>UW { align1 1H }; rndz(16) g8<1>F g2<8,8,1>F { align1 1H compacted }; rndz(16) g8<1>F g2<8,8,1>F { align1 1H compacted }; rndz(16) g18<1>F g4<8,8,1>F { align1 1H compacted }; rndz(16) g18<1>F g4<8,8,1>F { align1 1H compacted }; mad(16) g20<1>F g6.7<0,1,0>F g6.3<0,1,0>F g8<4,4,1>F { align16 1H }; mad(16) g20<1>F g6.7<0,1,0>F g6.3<0,1,0>F g8<4,4,1>F { align16 1H }; mad(16) g22<1>F g7.7<0,1,0>F g7.3<0,1,0>F g18<4,4,1>F { align16 1H }; mad(16) g22<1>F g7.7<0,1,0>F g7.3<0,1,0>F g18<4,4,1>F { align16 1H }; mov(16) g10<1>D g20<8,8,1>F { align1 1H compacted }; mov(16) g10<1>D g20<8,8,1>F { align1 1H compacted }; mov(16) g14<1>D g22<8,8,1>F { align1 1H compacted }; mov(16) g14<1>D g22<8,8,1>F { align1 1H compacted }; send(16) g120<1>UW g10<8,8,1>UD 0x10847001 send(16) g120<1>UW g10<8,8,1>UD 0x10847001 sampler MsgDesc: ld SIMD16 Surface = 1 Sampler = 0 mlen 8 rlen 8 { align1 1H }; sampler MsgDesc: ld SIMD16 Surface = 1 Sampler = 0 mlen 8 rlen 8 { align1 1H }; sendc(16) null<1>UW g120<8,8,1>UD 0x90031000 sendc(16) null<1>UW g120<8,8,1>UD 0x90031000 render MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 8 rlen 0 { align1 1H EOT render MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 8 rlen 0 { align1 1H EOT END B0 END B0