vec1 32 con ssa_36 = load_const (0x00000100 = 0.000000)
        ...
		vec1 32 con ssa_47 = load_const (0x00000004 = 0.000000)
		vec1 32 con ssa_48 = load_const (0x00000200 = 0.000000)
		/* succs: block_7 */
		loop {
			block block_7:
			/* preds: block_6 block_10 */
			vec1 32 con ssa_49 = phi block_6: ssa_36, block_10: ssa_53
			vec1 32 con ssa_50 = intrinsic load_ssbo (ssa_27, ssa_46) (access=1, align_mul=1073741824, align_offset=56)
			vec1 32 con ssa_51 = intrinsic load_shared (ssa_49) (base=0, align_mul=4, align_offset=0)
			vec1 32 con ssa_52 = fmax ssa_51, ssa_50
			intrinsic store_ssbo (ssa_52, ssa_27, ssa_46) (wrmask=x /*1*/, access=1, align_mul=1073741824, align_offset=56)
			vec1 32 con ssa_53 = iadd ssa_49, ssa_47
			vec1 32 con ssa_54 = uge32 ssa_53, ssa_48
			/* succs: block_8 block_9 */
			if ssa_54 {
				block block_8:
				/* preds: block_7 */
				break
				/* succs: block_11 */
			} else {
				block block_9:
				/* preds: block_7 */
				/* succs: block_10 */
			}
			block block_10:
			/* preds: block_9 */
			/* succs: block_7 */
		}
		block block_11: