diff --git a/src/radeon.h b/src/radeon.h
index eac9fa6..ce9508c 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -1683,6 +1683,7 @@ enum {
     RADEON_CREATE_PIXMAP_TILING_MACRO = 0x10000000,
     RADEON_CREATE_PIXMAP_TILING_MICRO = 0x20000000,
     RADEON_CREATE_PIXMAP_DEPTH = 0x40000000, /* for r200 */
+    RADEON_CREATE_PIXMAP_SZBUFFER = 0x80000000, /* for eg */
 };
 
 #endif /* _RADEON_H_ */
diff --git a/src/radeon_dri2.c b/src/radeon_dri2.c
index 5f1442e..4112d44 100644
--- a/src/radeon_dri2.c
+++ b/src/radeon_dri2.c
@@ -244,10 +244,10 @@ radeon_dri2_create_buffer(DrawablePtr drawable,
     struct dri2_buffer_priv *privates;
     PixmapPtr pixmap, depth_pixmap;
     struct radeon_exa_pixmap_priv *driver_priv;
-    int need_enlarge = 0;
     int flags;
     unsigned front_width;
     uint32_t tiling = 0;
+    unsigned aligned_width = drawable->width;
 
     pixmap = pScreen->GetScreenPixmap(pScreen);
     front_width = pixmap->drawable.width;
@@ -293,11 +293,12 @@ radeon_dri2_create_buffer(DrawablePtr drawable,
 			flags = RADEON_CREATE_PIXMAP_TILING_MICRO;
 		}
 		if (info->ChipFamily >= CHIP_FAMILY_CEDAR)
-		    need_enlarge = 1;
+		    flags |= RADEON_CREATE_PIXMAP_SZBUFFER;
 	    } else
 		flags = RADEON_CREATE_PIXMAP_TILING_MACRO | RADEON_CREATE_PIXMAP_TILING_MICRO;
 	    if (IS_R200_3D || info->ChipFamily == CHIP_FAMILY_RV200 || info->ChipFamily == CHIP_FAMILY_RADEON)
 		flags |= RADEON_CREATE_PIXMAP_DEPTH;
+		
 	    break;
 	case DRI2BufferBackLeft:
 	case DRI2BufferBackRight:
@@ -321,39 +322,6 @@ radeon_dri2_create_buffer(DrawablePtr drawable,
 	if (flags & RADEON_CREATE_PIXMAP_TILING_MACRO)
 	    tiling |= RADEON_TILING_MACRO;
 
-	if (need_enlarge) {
-	    /* evergreen uses separate allocations for depth and stencil
-	     * so we make an extra large depth buffer to cover stencil
-	     * as well.
-	     */
-	    int depth = (format != 0) ? format : drawable->depth;
-	    unsigned aligned_width = drawable->width;
-	    unsigned width_align = drmmode_get_pitch_align(pScrn, drawable->depth / 8, tiling);
-	    unsigned aligned_height;
-	    unsigned height_align = drmmode_get_height_align(pScrn, tiling);
-	    unsigned base_align = drmmode_get_base_align(pScrn, drawable->depth / 8, tiling);
-	    unsigned pitch_bytes;
-	    unsigned size;
-
-	    if (aligned_width == front_width)
-		aligned_width = pScrn->virtualX;
-	    aligned_width = RADEON_ALIGN(aligned_width, width_align);
-	    pitch_bytes = aligned_width * (depth / 8);
-	    aligned_height = RADEON_ALIGN(drawable->height, height_align);
-	    size = pitch_bytes * aligned_height;
-	    size = RADEON_ALIGN(size, base_align);
-	    /* add additional size for stencil */
-	    size += aligned_width * aligned_height;
-	    aligned_height = RADEON_ALIGN(size / pitch_bytes, height_align);
-
-	    pixmap = (*pScreen->CreatePixmap)(pScreen,
-					      aligned_width,
-					      aligned_height,
-					      (format != 0)?format:drawable->depth,
-					      flags);
-
-	} else {
-	    unsigned aligned_width = drawable->width;
 
 	    if (aligned_width == front_width)
 		aligned_width = pScrn->virtualX;
@@ -363,7 +331,6 @@ radeon_dri2_create_buffer(DrawablePtr drawable,
 					      drawable->height,
 					      (format != 0)?format:drawable->depth,
 					      flags);
-	}
     }
 
     if (!pixmap)
diff --git a/src/radeon_drm.h b/src/radeon_drm.h
index 669f390..042e822 100644
--- a/src/radeon_drm.h
+++ b/src/radeon_drm.h
@@ -815,6 +815,8 @@ struct drm_radeon_gem_create {
 #define RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK		0xf
 #define RADEON_TILING_EG_TILE_SPLIT_SHIFT		24
 #define RADEON_TILING_EG_TILE_SPLIT_MASK		0xf
+#define RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT	28
+#define RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK	0xf
 
 struct drm_radeon_gem_set_tiling {
 	uint32_t	handle;
diff --git a/src/radeon_exa.c b/src/radeon_exa.c
index e90a9b6..45945e1 100644
--- a/src/radeon_exa.c
+++ b/src/radeon_exa.c
@@ -522,6 +522,10 @@ void *RADEONEXACreatePixmap2(ScreenPtr pScreen, int width, int height,
 				surface.flags = RADEON_SURF_CLR(surface.flags, MODE);
 				surface.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
 			}
+			if (usage_hint & RADEON_CREATE_PIXMAP_SZBUFFER) {
+				surface.flags |= RADEON_SURF_ZBUFFER;
+				surface.flags |= RADEON_SURF_SBUFFER;
+			}
 			if (radeon_surface_best(info->surf_man, &surface)) {
 				return NULL;
 			}
@@ -539,6 +543,7 @@ void *RADEONEXACreatePixmap2(ScreenPtr pScreen, int width, int height,
 				tiling |= surface.bankh << RADEON_TILING_EG_BANKH_SHIFT;
 				tiling |= surface.mtilea << RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT;
 				tiling |= eg_tile_split(surface.tile_split) << RADEON_TILING_EG_TILE_SPLIT_SHIFT;
+				tiling |= eg_tile_split(surface.stencil_tile_split) << RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT;
 				break;
 			case RADEON_SURF_MODE_1D:
 				tiling |= RADEON_TILING_MICRO;