diff --git a/src/gallium/drivers/r600/evergreen_hw_context.c b/src/gallium/drivers/r600/evergreen_hw_context.c
index 8d260aa..1261fa2 100644
--- a/src/gallium/drivers/r600/evergreen_hw_context.c
+++ b/src/gallium/drivers/r600/evergreen_hw_context.c
@@ -160,9 +160,13 @@ static const struct r600_reg evergreen_context_reg_list[] = {
 	{R_028800_DB_DEPTH_CONTROL, 0, 0},
 	{R_02880C_DB_SHADER_CONTROL, 0, 0},
 	{R_028808_CB_COLOR_CONTROL, 0, 0},
+#if OLDVGT
 	{R_028810_PA_CL_CLIP_CNTL, 0, 0},
+#endif
 	{R_028814_PA_SU_SC_MODE_CNTL, 0, 0},
-	{R_02881C_PA_CL_VS_OUT_CNTL, 0, 0},
+#if OLDVGT
+//	{R_02881C_PA_CL_VS_OUT_CNTL, 0, 0},
+#endif
 	{R_028840_SQ_PGM_START_PS, REG_FLAG_NEED_BO, 0},
 	{R_028844_SQ_PGM_RESOURCES_PS, 0, 0},
 	{R_02884C_SQ_PGM_EXPORTS_PS, 0, 0},
@@ -483,9 +487,13 @@ static const struct r600_reg cayman_context_reg_list[] = {
 	{CM_R_028804_DB_EQAA},
 	{R_028808_CB_COLOR_CONTROL, 0, 0},
 	{R_02880C_DB_SHADER_CONTROL, 0, 0},
+#if OLDVGT
 	{R_028810_PA_CL_CLIP_CNTL, 0, 0},
+#endif
 	{R_028814_PA_SU_SC_MODE_CNTL, 0, 0},
+#if OLDVGT
 	{R_02881C_PA_CL_VS_OUT_CNTL, 0, 0},
+#endif
 	{R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1, 0, 0},
 	{R_028840_SQ_PGM_START_PS, REG_FLAG_NEED_BO, 0},
 	{R_028844_SQ_PGM_RESOURCES_PS, 0, 0},
diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c
index 1a48029..3efae76 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -2173,7 +2173,7 @@ void evergreen_init_state_functions(struct r600_context *rctx)
 	 * !!!
 	 */
 
-	r600_init_atom(rctx, &rctx->atom_pa2.atom, id++, r600_emit_pa2, 3);
+	r600_init_atom(rctx, &rctx->atom_pa2.atom, id++, r600_emit_pa2, 9);
 	rctx->atom_pa2.pa_sc_line_stipple = 0x0000ffff;
 	r600_atom_dirty(rctx, &rctx->atom_pa2.atom);
 
diff --git a/src/gallium/drivers/r600/r600_hw_context.c b/src/gallium/drivers/r600/r600_hw_context.c
index b437070..01c95b9 100644
--- a/src/gallium/drivers/r600/r600_hw_context.c
+++ b/src/gallium/drivers/r600/r600_hw_context.c
@@ -376,9 +376,13 @@ static const struct r600_reg r600_context_reg_list[] = {
 	{R_02844C_PA_CL_VPORT_ZSCALE_0, 0, 0},
 	{R_028450_PA_CL_VPORT_ZOFFSET_0, 0, 0},
 	{R_0286D4_SPI_INTERP_CONTROL_0, 0, 0},
-	{R_028810_PA_CL_CLIP_CNTL, 0, 0},
+#if OLDVGT
+//	{R_028810_PA_CL_CLIP_CNTL, 0, 0},
+#endif
 	{R_028814_PA_SU_SC_MODE_CNTL, 0, 0},
+#if OLDVGT
 	{R_02881C_PA_CL_VS_OUT_CNTL, 0, 0},
+#endif
 	{R_028A00_PA_SU_POINT_SIZE, 0, 0},
 	{R_028A04_PA_SU_POINT_MINMAX, 0, 0},
 	{R_028A08_PA_SU_LINE_CNTL, 0, 0},
@@ -937,6 +941,7 @@ void r600_context_flush(struct r600_context *ctx, unsigned flags)
 	flags |= RADEON_FLUSH_KEEP_TILING_FLAGS;
 
 	/* Flush the CS. */
+{static unsigned cs_id = 0; unsigned i; for (i = 0; i < ctx->cs->cdw; i++) {fprintf(stderr, "[%2d] [%5d] 0x%08x\n", cs_id, i, ctx->cs->buf[i]);} cs_id++;}
 	ctx->ws->cs_flush(ctx->cs, flags);
 
 	ctx->pm4_dirty_cdwords = 0;
diff --git a/src/gallium/drivers/r600/r600_pipe.h b/src/gallium/drivers/r600/r600_pipe.h
index 39653c7..7bdde40 100644
--- a/src/gallium/drivers/r600/r600_pipe.h
+++ b/src/gallium/drivers/r600/r600_pipe.h
@@ -107,6 +107,8 @@ struct r600_sample_mask {
 	uint16_t sample_mask; /* there are only 8 bits on EG, 16 bits on Cayman */
 };
 
+#define OLDVGT 0
+
 enum r600_pipe_state_id {
 	R600_PIPE_STATE_BLEND = 0,
 	R600_PIPE_STATE_BLEND_COLOR,
@@ -116,7 +118,9 @@ enum r600_pipe_state_id {
 	R600_PIPE_STATE_SCISSOR,
 	R600_PIPE_STATE_VIEWPORT,
 	R600_PIPE_STATE_RASTERIZER,
+#if OLDVGT
 	R600_PIPE_STATE_VGT,
+#endif
 	R600_PIPE_STATE_FRAMEBUFFER,
 	R600_PIPE_STATE_DSA,
 	R600_PIPE_STATE_STENCIL_REF,
@@ -325,6 +329,8 @@ struct r600_pa2 {
 	  * it seems to be fine.
 	  */
 	uint32_t			pa_sc_line_stipple;
+	uint32_t			pa_cl_vs_out_cntl;
+	uint32_t			pa_cl_clip_cntl;
 };
 
 struct r600_vgt1 {
@@ -379,7 +385,9 @@ struct r600_context {
 	struct r600_pipe_shader_selector 	*ps_shader;
 	struct r600_pipe_shader_selector 	*vs_shader;
 	struct r600_pipe_rasterizer	*rasterizer;
+#if OLDVGT
 	struct r600_pipe_state          vgt;
+#endif
 	struct r600_pipe_state          spi;
 	struct pipe_query		*current_render_cond;
 	unsigned			current_render_cond_mode;
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index 8d8522d..6c72071 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -2042,7 +2042,11 @@ void r600_init_state_functions(struct r600_context *rctx)
 	 * or piglit regression).
 	 * !!!
 	 */
-	r600_init_atom(rctx, &rctx->atom_pa2.atom, id++, r600_emit_pa2, 3);
+#if OLDVGT
+	r600_init_atom(rctx, &rctx->atom_pa2.atom, id++, r600_emit_pa2, 6);
+#else
+	r600_init_atom(rctx, &rctx->atom_pa2.atom, id++, r600_emit_pa2, 9);
+#endif
 	rctx->atom_pa2.pa_sc_line_stipple = 0x0000ffff;
 	r600_atom_dirty(rctx, &rctx->atom_pa2.atom);
 
@@ -2092,6 +2096,7 @@ void r600_init_state_functions(struct r600_context *rctx)
 	r600_init_atom(rctx, &rctx->atom_vgt2.atom, id++, r600_emit_vgt2, 3);
 	rctx->atom_vgt2.vgt_primitive_type = 0xffffffff;
 
+
 	rctx->context.create_blend_state = r600_create_blend_state;
 	rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state;
 	rctx->context.create_fs_state = r600_create_shader_state_ps;
diff --git a/src/gallium/drivers/r600/r600_state_common.c b/src/gallium/drivers/r600/r600_state_common.c
index 69528a6..3b80753 100644
--- a/src/gallium/drivers/r600/r600_state_common.c
+++ b/src/gallium/drivers/r600/r600_state_common.c
@@ -122,6 +122,10 @@ void r600_emit_pa2(struct r600_context *rctx, struct r600_atom *atom)
 	struct radeon_winsys_cs *cs = rctx->cs;
 
 	r600_write_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE, rctx->atom_pa2.pa_sc_line_stipple);
+	r600_write_context_reg(cs, R_028810_PA_CL_CLIP_CNTL, rctx->atom_pa2.pa_cl_clip_cntl);
+#if !OLDVGT
+	r600_write_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL, rctx->atom_pa2.pa_cl_vs_out_cntl);
+#endif
 }
 
 void r600_emit_vgt1(struct r600_context *rctx, struct r600_atom *atom)
@@ -1262,25 +1266,54 @@ void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
 		r600_atom_dirty(rctx, &rctx->atom_vgt2.atom);
 	}
 
+#if OLDVGT
 	if (rctx->vgt.id != R600_PIPE_STATE_VGT) {
 		rctx->vgt.id = R600_PIPE_STATE_VGT;
 		rctx->vgt.nregs = 0;
 		r600_pipe_state_add_reg(&rctx->vgt, R_02881C_PA_CL_VS_OUT_CNTL, 0);
-		r600_pipe_state_add_reg(&rctx->vgt, R_028810_PA_CL_CLIP_CNTL, 0);
+//		r600_pipe_state_add_reg(&rctx->vgt, R_028810_PA_CL_CLIP_CNTL, 0);
 	}
 
 	rctx->vgt.nregs = 0;
 	r600_pipe_state_mod_reg(&rctx->vgt,
 				rctx->vs_shader->current->pa_cl_vs_out_cntl |
 				(rctx->rasterizer->clip_plane_enable & rctx->vs_shader->current->shader.clip_dist_write));
+#if 0
 	r600_pipe_state_mod_reg(&rctx->vgt,
 				rctx->pa_cl_clip_cntl |
 				(rctx->vs_shader->current->shader.clip_dist_write ||
 				 rctx->vs_shader->current->shader.vs_prohibit_ucps ?
 				 0 : rctx->rasterizer->clip_plane_enable & 0x3F));
+#endif
 
 	r600_context_pipe_state_set(rctx, &rctx->vgt);
 
+	tmp = rctx->pa_cl_clip_cntl |
+		(rctx->vs_shader->current->shader.clip_dist_write ||
+		 rctx->vs_shader->current->shader.vs_prohibit_ucps ?
+		 0 : rctx->rasterizer->clip_plane_enable & 0x3F);
+	if (rctx->atom_pa2.pa_cl_clip_cntl != tmp) {
+		rctx->atom_pa2.pa_cl_clip_cntl = tmp;
+		r600_atom_dirty(rctx, &rctx->atom_pa2.atom);
+	}
+#else
+	tmp = rctx->vs_shader->current->pa_cl_vs_out_cntl |
+		(rctx->rasterizer->clip_plane_enable & rctx->vs_shader->current->shader.clip_dist_write);
+	if (rctx->atom_pa2.pa_cl_vs_out_cntl != tmp) {
+		rctx->atom_pa2.pa_cl_vs_out_cntl = tmp;
+		r600_atom_dirty(rctx, &rctx->atom_pa2.atom);
+	}
+
+	tmp = rctx->pa_cl_clip_cntl |
+		(rctx->vs_shader->current->shader.clip_dist_write ||
+		 rctx->vs_shader->current->shader.vs_prohibit_ucps ?
+		 0 : rctx->rasterizer->clip_plane_enable & 0x3F);
+	if (rctx->atom_pa2.pa_cl_clip_cntl != tmp) {
+		rctx->atom_pa2.pa_cl_clip_cntl = tmp;
+		r600_atom_dirty(rctx, &rctx->atom_pa2.atom);
+	}
+#endif
+
 	/* Enable stream out if needed. */
 	if (rctx->streamout_start) {
 		r600_context_streamout_begin(rctx);