02:58 jennymcreign: don't even try, you can not get much done without me, toxic behaviours have consequences. So the calculations are pretty simple for data compression, since those are odd numbers i use for the format for the decoder and encoder, the maximum is the sum of quadlets values times 8, times 1.5 for a single 32bit value in the hash, all that depends on values used, but we pack amount of the values
02:58 jennymcreign: available into first index for simplicity, so if all numbers are not maximum it can easily under commit, and that is a shocking amount of data it can hold, the values are 4bit combinations, it delta encodes automatically based of the sum which get's incremented by two for each cell which is a single value so you do not have to round and use asymmetry, so we add another times two*amount of
02:58 jennymcreign: values stored, so that formula gives a maximum storage amount when all values are maximum and or when all values are smallest, depending on format , so say we have format 5+9+13+19=44 8 digits saved compared to 52 earlier, the maximum fill with all maximums is 44+22*8 and we divide that value from maximum number of 32bit, then we do times two, times 1.5, minus two , based of
02:58 jennymcreign: count*(first+last)/2 , to get count so final value comes as count*(44*8+X*44*8)/2, so the constant X comes out of iterative procedure with a conditional bound checking for the max machine word digital max value and would be stored back as size to first index, but it's worth to shorten the iterations with divide and conquer.
04:36 norinakamura: it messes up the buttons after hibernate, so button left needs to hold down to get any or basically all the movement, that is for the acpi bug you designed. but back to compression so if all values are maximums, you get round about 300k values on that 528 per field format. without any delta coding present, however if you were to use smaller values then 300k maximums you will delta encode
04:37 norinakamura: and get round about million or more values on the average. and this is only one iteration of compression, only one round gets so much memory. As i told, two rounds of back to back encodings will give you million times million already.
06:09 jevgenikolov: I proved to be too strong for your kill off attempts, we will hit back, i knew i would survive roughly but this neckchip might crack me up sooner or later, and we are going to fully attack you. The calculations are so easy that i do them with calculator only, so 90000*(2+90000)/2 is 4billion somewhere, so those are indexes for maximum values 4294967295/4224(8*528 or 32*66 that was) is
06:09 jevgenikolov: million since 8 fields share an index it's 720000/2 360000, and delta encoding is automatic with the formula i defined and gave. nothing in the computation of superspeed comutation i will upload, i only did the data compression calculations to you, because the ultra peformant computation though only slightly more difficult violates the safety of human beings due to rotten trash beaming
06:09 jevgenikolov: them on request. I nearly once again died into this in cambodia.
08:27 hochiminchi: You do not seem to understand how mentally ill brutes you are. You do not acknowledge your illborn residing or state on this planet at all. It's not only Russians who love me and participate in wiping you out in response to your crimes against me, though they get most momentum, and they are outnumbering others a bit and are one of my favourites, regardless of that, residents from nearly all
08:27 hochiminchi: countries participate in some way or another in attacking you soon. You chose a wrong guy to mess with your amoral kill off attempts, terror and protein robin hood shows. We will kill jacob rothschild too but the fart is nearly dead with it's jewish ass of freescale to natural causes anyways. Totally terrible humans are those british barons rather than USA ones however.
10:16 shurawanpotabne: We actually know who is behind such crimes, jacob killed second time chinese over shared patent, crashed the whole airplane jet, they were before trying their luck similarly on me after cracking up my organs, dynasty of those are trillionnaires with very dirty money, the war will execute against all involved and we will finish all those monsters life chapters for sure. Technically riots
10:16 shurawanpotabne: and rebellion will take place where they will get to killing all that dynasty, no further comments on my side, i promise you this.
13:14 rudolfressing: So let's go over the details a bit what various people told me at overseas, the most interesting talks but very unpleasent was Leeroy, white supremacist, with hitler tattoos, well he told me something that has triggered us to take actions against jewish once again, i never mentioned about the chips previously identified through hospital's medicine fraud , however he told me, that jewish
13:14 rudolfressing: they abuse arian children and i never figured they are after me , by taking their brain stem cells from the neck and leaving them to die just like that, what was more shocking that a year after his talks jews came and did the exact thing to me, where from previous interactions, from three surgeries i have muscle varicosis and marrow entrance holes, where as the promised treatment was
13:14 rudolfressing: never done. This is just shocking where they took it in finland after the marrow entrance this time i had local ansthesia, and i saw from doctors screen and yelled stop it, it's fucked up to share the world with jews smells like they get another holocoust, and hitler and Putin are fine people, trust me, i know what i talk about. I never believed leeroy and i am going to die cause of this.
13:51 karolherbst[d]: I maybe should be more strict in regards to IPs coming from hosters and such..
14:15 dwfreed: banning all of ovh is probably a little too strict, though
14:15 feijsenanton: There are rules that no reentry after a fight such as retaliation, but it wasn't a fight i knocked down leeroy with regret he ran out and chased me after he got up again, this is forgatten, but lumplegs alex and this other kill off crew, they assaulted me from behind, and yes we will go back and eliminate them. Corruption in cambodia is horrible they are handled in a war soon by thais, and
14:15 feijsenanton: they did not charge those people. All this crew of murderers we gonna get to. And surprise surprise your jews did never get anything right here, nor karolherbst, and you kill people who are better than you, well our gangsters ain't gonna be satisfied over this violations. So i gave jack dedman a chanche , he confesses what he did , gives him over to authorities gets anal in prison and he
14:15 feijsenanton: is free to live on paraole , if not he gets killed with others who were involved, same clause applies to Alex "birthlumplegs" Enrico Sif and but i expect others to be over too weak in prison, those get over time killed anyways, very toxic people still however. Sensational what you had arranged, i also go to harass many IRC people, who had put high end words and scam around and over my
14:15 feijsenanton: life, but they get beaten up, however will be free to live afterwards.
14:52 lunafoxgirlvt[d]: Man this reads like a fever dream
15:24 marisszizins: Man it's great that you at all listen what the fuck i am saying, the idiot called me as joss after the implant incident, and why do you think i said i did not die with 2days under spesis, why do you think they are after my cells all the time? For god sakes i do not get fever, last and only time i had fever was when i was 5years old, i am resistant to all of the stis and during five years
15:24 marisszizins: times after only when being thrown parasites in kilotonns for 2weeks, then my system breaks once in five years, and i get what we call a mild nose mucus. Dudes i do not get fevers in life, but i am not immportal either, i get hard tissue pain on teeth sometimes when assaulted , head pain when batted or axed etc. No fever, this chips should cause me cancer but i do not conduct that one
15:24 marisszizins: easily either, due to superior immune system, but i am afraid that they got my range right this time, and implanted a more powerful lethal chip. earlier ones were not getting too close to kill me.
15:25 gfxstrand[d]: steel01[d]: Where is the cutoff for what Tegra devices use the tegra driver for display?
16:30 karolherbst[d]: another scheduling issue on ampere....
16:36 mhenning[d]: another fp16 issue, or is it a different type of instruction this times?
16:37 karolherbst[d]: HMMA
16:37 karolherbst[d]: so... kinda fp16 but not the way you thought it would be 🙃
16:45 mysterymike: I know i insulted and played you cause you deserved that to be done by me, however the calculations are correct the ones i gave, actually i told you the whole time that way but just for revenge and fun messed with you. Can you elaborate what is misunderstood from what i offered? The way i think is mystery , i have strong instincts and and beliefs, hence back in time when they first injured
16:45 mysterymike: me very bad on purpose in the hospital, i knew it was going to happen already but during five years of arguing that dad jammed me onto this thriller and blocked all my possible ways to recover, so it's all clear that they are doing this terror all against me, he also enjoyably hilariously laughed with satisfaction when i was about to kill myself in pain and agony, what a family! But i am
16:45 mysterymike: different i do not such shit.
16:45 mysterymike: i still escaped and did my contribution to the world.
16:50 steel01[d]: gfxstrand[d]: Xavier. Orin uses nvidia-drm for display out. I'm not sure if that is just a software decision or if hardware changes mandate that. I seem to recall a statement that Orin display hardware isn't under host1x, so it may be the latter.
16:54 gfxstrand[d]: Okay
17:03 gigolomaneric: You deserved to get humiliated infront of all of your employers after you scammed about my mental illness, where as i was champion or close to it in arm wrestling at school against all the gym guys, runner, national team member and everywhere i went scored heavy, it seems you can not figure out the numbers without any terror placed at you, saying that a butchered man and ex champion is
17:03 gigolomaneric: mentally ill, you will never get any job in the future, i kicked you out so bad .
17:04 gigolomaneric: gymnastics, i have bag full of diplomas and medals
17:14 karolherbst[d]: uhh.. I think I need read after read latency handling for that one 🥲
17:15 karolherbst[d]: which is a funky concept
17:38 mhenning[d]: read after read doesn't really make sense to me
17:38 mhenning[d]: is it maybe a limit on how often you can issue the instruction?
17:40 mhenning[d]: or if it prevents you from issuing anything for a few cycles, then we already have execution latencies for that
17:41 mohamexiety[d]: why would you ever need read after read handling? :elythink:
17:41 mohamexiety[d]: that should always just work, right?
17:42 mhenning[d]: yeah, traditionally there are no read after read hazards
17:43 mhenning[d]: I suppose an instruction could modify a read register and then put it back when it's done, but that seems unlikely to happen in practice
17:48 karolherbst[d]: there is some transitivity stuff going on
17:49 karolherbst[d]: and rar is a virtual hazard to model that
17:51 mhenning[d]: Not sure what you mean by "transitivity" here
17:53 karolherbst[d]: it's relevant if you look at more than two instructions and order of operations. Like a previously scheduled instruction _might_ read after a later scheduled one. So a fake wait is added between those two, so you won't have to look beyond two instructions to figure out WaR hazards e.g.
17:54 karolherbst[d]: WaR that follows those two
17:55 karolherbst[d]: e.g. something like this: https://gist.github.com/karolherbst/b6ff02426a39e342078064dac41d0d01
17:57 mohamexiety[d]: wait though how would that happen?
17:58 mohamexiety[d]: if you know all the latencies, how would you get to a spot where a prev instruction reads after a later one?
17:58 mhenning[d]: karolherbst[d]: oh, we should probably just fix the scheduler then to handle that case. I don't think we should model anything as a RaR
17:58 karolherbst[d]: uarch reasons.. but I also don't really understand why a WaR hazard wouldn't be enough to model it...
17:59 mohamexiety[d]: what uarch reasons? the compiler is in charge of scheduling and the compiler has full latency info, right?
17:59 karolherbst[d]: sure, but an instruction doesn't have to immediately read a value and it might just take a bit of time
17:59 karolherbst[d]: but dunno...
17:59 karolherbst[d]: not really sure if that's what's going on here anyway
18:01 karolherbst[d]: but I also haven't checked if NAK only looks at the last reader or at all previous readers
18:03 karolherbst[d]: I also don't know if having a rar hazard postpones reading for later scheduled instructions either
18:04 karolherbst[d]: so maybe B _would_ read later as well
18:04 karolherbst[d]: but dunno
18:08 mhenning[d]: I mean, there is no RaR in the scheduler right now. Introducing one is probably a larger change than fixing the "but I also haven't checked if NAK only looks at the last reader or at all previous readers" problem, if it is a problem
18:09 snowycoder[d]: triang3l[d]: Is this tested on dEQP?
18:09 Lyude: crazy question - any engineers at nvidia with experience working on the display stack around here?
18:11 upperwilliam: BTW. even on pipeline measurings LLVM code is hilarious, where as they can just use interrupts and deisgn hazards to measure all needed pipeline stages to pull pcie to clockless mode and give it more async load, GPU pipeline stages in vintage model i suppose lacked interrupts alltogether for the fixed stages they'd probably work, but not on those MMIO shaders, so sure i do not know all the
18:11 upperwilliam: worlds gpu designs, they vary so much model to model, but there is a problem with asics, there is only one caveat, high resolution timers are not possible to be engineered, so this autosar did on FPGA's for picosecond resolution timers XCP xilinx was used there. it can perhaps pull to async fastest mode, it would not report reliable timing.
18:11 gfxstrand[d]: triang3l[d]: We may have to delay the kill until after the critical section but `kill`, i.e., `demote` should be fine inside.
18:12 snowycoder[d]: gfxstrand[d]: If every lane is killed then there's no lane left to handle the unlocks, that could be a major problem
18:16 mhenning[d]: nvidia tends to be reasonably good about that eg. exited threads won't count toward control flow barrier waits
18:17 mhenning[d]: so it's possible we don't need to do anything special (but still need to test to make sure that's true)
18:39 karolherbst[d]: mhenning[d]: yeah.. I wished I'd know what's wrong, but looking at the data I also can't find anything else being wrong...
18:43 upperwilliam: I understand that MMIO based fixed pipeline stuff, can mix any commands and intermix those into pipeline, cause technically the shader units are global and ripple into the pipeline with other commands similarly, it's there i do not have very badass experience on GPUs, only southern island is what i fully studied, but there are lot's of lunatics that need to hear what i and roger penrose
18:43 upperwilliam: who reminds me the calmness of my grandfather and kindness need to listen, there is no concept of time in universe, universe always existed, and it seemed like i do not like or critisize Elon Musk, which i did not do, i like him enough, same for donald trump, i do not consider them as bad persons so far the least. Lot of people i experienced in mental institution where i actually got much
18:43 upperwilliam: experience from, flipped out cause of cosmology and always the dilemma, who was before egg or chicken, i mean when and how the universe started, so satisfy with something as it never started , time was just invented for calculations it's invented or hacked dimension.
19:19 haraldkupper: You should know well, that i do not care what such trash like majority says about cosmology, they are retarded people to me, all except Roger Penrose, who self-evidently seems to make sense to me, tubulus , senses, time, big bang, ashtar , planet X, his theories are coming through with enough sanity. About conciusness of AI, so and so, i showed that those systems can have lot more memory,
19:19 haraldkupper: so i think it can be made somewhat concious not perhaps entirely. Memory of ai can surpass that of human being, but he has a lot of interesting ideas, but that is an old experienced man.
19:27 Lyude: get outta here
19:28 HdkR: It's a busy day today
19:28 Lyude: i'll keep an eye on the chat
19:28 airlied: definitely on the grind today
19:41 pettyalvarez: What i am saying Lyude and HdkR estonian man like me, takes your clueless and senseless LGBT skirt wearing trash just from the hair trust me, and bangs your head against the table, and this is just what i am going to do with you , trust me i will, such shit gives me no lectures about big bangs, nor says who is my wife and who i fuck and what i do.
19:41 HdkR: 💃
19:42 airlied: I just wish I knew how to create this many irc bouncers/clients/hosting machines, it's like a one man kubernetes across the internet
19:43 gfxstrand[d]: Maybe he should work on cloud computing instead of GPUs. He's clearly mastered uptime and redundancy.
19:43 HdkR: I supposed once you get banned across every community, you start to develop a flow to get back in within two minutes.
19:44 HdkR: The AWS outaged today could have used someone with that amount of uptime.
19:44 HdkR: outage*
19:45 airlied: like bro is hitting 5 9s
19:46 Lyude: pettyalvarez: i'll be hetre all day
19:46 chikuwad[d]: fastest ban on this side of OFTC
19:46 Lyude: hehe
19:47 chikuwad[d]: https://tenor.com/view/clint-eastwood-gunslinger-six-shooter-gun-flip-flip-gun-into-holster-gif-12524647873518510513
19:47 Lyude: i wonder he realizes i don't have colored hair yet
19:47 chikuwad[d]: *yet*
19:48 Lyude: :)
19:48 HdkR: I loved when I had bright red dyed hair, was a good time.
19:55 Lyude: tbh i can't believe i'm saying this but it is getting increasingly tempting to try automating this with an llm...
19:55 HdkR: tbh I thought that was dwfreed was going to do :D
19:57 mhenning[d]: Someone else pointed out that a keyword ban could go a long way
19:57 airlied: I think there was 3-4 ircd rewrites before then :-P
19:57 gfxstrand[d]: Wait, he's picking on hair colors now? Should I take that personally?
19:58 triang3l[d]: snowycoder[d]: Unfortunately not by the CTS, it discards based on `gl_FragCoord.x & 1`, and Piglit doesn't seem to have any runtime FSI tests with `discard`, only shader compilation tests with a non-uniform `discard` condition
19:59 triang3l[d]: But you can modify the CTS test 🙃
20:00 triang3l[d]: It's `dEQP-VK.fragment_shader_interlock.basic.discard.*`, and the code is <https://github.com/KhronosGroup/VK-GL-CTS/blob/main/external/vulkancts/modules/vulkan/fragment_shader_interlock/vktFragmentShaderInterlockBasic.cpp>
20:00 snowycoder[d]: I was so happy to finally pass some tests 🙁
20:01 snowycoder[d]: That's a pretty major oversight in the CTS, I would've very easily missed it
20:05 mhenning[d]: I'm sure CTS would be happy to accept a patch that hits that case
20:05 dwfreed: getting a bot running that can, among other things, deal with this guy in an almost completely automated fashion is very high on my OFTC todo list
20:06 dwfreed: in fact, higher than Atheme (new services) or solanum (new ircd)
20:07 dwfreed: There's a lot of technical debt that needs paying, and time to work on OFTC things is unfortunately been going for a premium lately
20:07 dwfreed: (We still have servers running Debian *stretch*, and nothing is newer than bullseye; it's a mess, but I'm working on it)
20:09 HdkR: A million important things to work on, yet not enough time.
20:09 dwfreed: Yeah
20:09 dwfreed: I need like 72 hours in a day and no need for sleep
20:11 diddleyfine: I think you are messing with me, android has just so many servers as jailbroken, they are all free and can be relayed, you banned estonian domain trace immediate routing tables, surveillance me, you know very well that i use vpnjantit and protonvpn cause i am not interested anymore to come here, i swap the ip so that your routing table cause wrong, i see when you async socket is taken out,
20:11 diddleyfine: but matrix and nodes proxy is very easy to be fooled so that signed proxy is gotten out from chromium or matrix client , yes sure i can get in to anywhere i like, and from america i just stole round about 100k documents out of their website by writing a script, with curl, dudes i am a programmer, i maintain all the computers to anyone, cause i am always the smartest, i know how bad ipv4/6
20:11 diddleyfine: ethernet protocol is.
20:24 gfxstrand[d]: steel01[d]: Okay, so I've got it so it doesn't enumerate the nouveau device but does enumerate the tegra device and it's still blowing up. I think something super subtle is going on here.
20:24 gfxstrand[d]: I'm gonna need more logging
20:24 gfxstrand[d]: But I pushed the latest
20:24 gfxstrand[d]: Setting it to tegra gets me the same corruption you're seeing. Setting it to nouveau, I get my log messages but no one ever tries to allocate a BO as far as I can tell
20:25 Lyude: diddleyfine: still here
20:25 Lyude: oh wow
20:26 Lyude: didn't even need to do anything that time
20:26 dwfreed: they'll be back in 5 minutes
20:26 steel01[d]: Huh. If you unset TARGET_GRAPHICS, it will default to swiftshader. Leaving the minigbm, it'll use the new back end with only the tegra driver and not nouveau. That should render correctly like my tests a couple days ago.
20:26 steel01[d]: Not sure how that's effectively different from what you described, though.
20:27 steel01[d]: Though... If drm hwc enables nouveau, something in the kernel drivers might be doing handoffs.
20:28 gfxstrand[d]: I'm trying to figure out the difference between the tegra driver and my nouveau driver.
20:28 gfxstrand[d]: Like, it's not even trying. No BOs get allocated.
20:29 gfxstrand[d]: It just faults trying to get display bounds again, meaning it's probably opening the nouveau node, not the tegra node.
20:32 Lyude: hi
20:32 HdkR: Knock knock. Telegram.
20:35 gfxstrand[d]: Ope! I'm seing BO creates!
20:36 HdkR: 🎉
20:36 karolherbst: Lyude: btw, I started to set up masks on the entire allocated ASNs from those corpo subnets... though not sure if it's worth the trouble because there are a lot of those 🙃
20:37 gfxstrand[d]: lmao... The handles are nouveau handles and not tegra handles so `drv_bo_get_plane_fd()` fails. 🙃
20:38 steel01[d]: This makes sense.
20:38 Lyude: karolherbst: you mean the ones that are being used for ban dodging?
20:38 karolherbst: yeah
20:39 karolherbst: like not just banning the one account or hostmask, but the entire allocated ASN
20:39 Lyude: oh right. i forgot we just get people's IPs on here
20:39 Lyude: tbh I wonder if we should just start adding them to dronebl
20:39 karolherbst: dronebl?
20:40 Lyude: ...assuming that's still a thing in 2025
20:40 karolherbst: heh
20:40 Lyude: karolherbst: yeah - it was a central database for IPs being used to attack stuff like irc networks
20:40 karolherbst: I think the issue is that IPs don't mean much these days
20:40 Lyude: mhm, true.
20:40 karolherbst: like there might be legit users on one of those subnets
20:40 karolherbst: but...
20:40 karolherbst: if none of them are hanging out here I also don't particularly care
20:43 karolherbst: after we add like 2000 of those, we surely have to got them all eventually 🙃
20:44 dwfreed: Lyude: dronebl is still a thing, and I don't know why it hadn't occurred to me to add them, but it's something I can make the bot do when I get to that
20:45 Lyude: yeah
20:45 karolherbst: it's kinda curious how aall those ranges today were assigned to companies in the UAE 🙃
20:45 Lyude: would be a good idea, also thanks!
20:45 Lyude: karolherbst: surprised it isn't russia
20:45 karolherbst: it was also russia
20:46 Lyude: oh ok
20:46 karolherbst: but just one
20:46 karolherbst: but the last 5 were UAE
20:47 karolherbst: wait.. I added 10 entires today.. impressive
20:47 freedom123: .0.1:8888)
20:47 freedom123: Proxy traversal failed.
20:47 freedom123: * Stopped previous connection attempt (121091)
20:48 Lyude: owo what's this
20:48 HdkR: owo
20:48 karolherbst: LLM
20:48 Lyude: our llm or another llm
20:48 karolherbst: there are person who join IRC on a bunch of channels to train their LLM
20:48 karolherbst: dwfreed: ^^
20:49 Lyude: i wish i could be as naive as to think that all AI problems can just be solved with more training data and that power and resources are made up fantasies by people with colored hair
20:50 karolherbst: dunno if this one was an LLM, but also.. the last one "spoke" exactly like that one 🙃
20:51 karolherbst: kinda piped the messages of the c&c thing into the actual channels, kinda wild
20:51 dwfreed: Pretty sure it was them, and they just forgot to make sure they had the right thing in their clipboard
20:52 karolherbst: :D
20:52 karolherbst: maybe
20:52 steel01[d]: gfxstrand[d]: Yeah, this makes a lot of sense. The tegra-drm driver creates all the planes. And on tegra, I presume nouveau has no planes. So to put anything on screen, you have to run it through tegra-drm to apply to a plane.
21:00 nanodrums: I just want you to leave my soul alone in physical space, your friends come to harass me, and it was not my wife, who you screwed i played them, cause i had nothing to do, i knew she was a fucker , but had nothing to do to play along (too serious convictions done in estonia my court's fraud) , i won't accept her not in this life not in another one though in the beginning yes i liked her, but
21:00 nanodrums: for not long when i noticed they are all cracking me up deliberately in cambodia, i had nothing to do to play along, i won't accept such anal bum fuckers into my life. Fuck sakes is that clear? I donated your memory management if that is what you were after,i can program the memory manager the fw's for free that i talked about, just leave my business intact of your terror or it's a war it was
21:00 nanodrums: a twistedest mofo i had ever faced grand deluded mentally ill fucker. You get handled and killed like many before if you do not fuck off from my premise.
21:02 karolherbst: it's been busy today :')
21:17 gfxstrand[d]: steel01[d]: Ugh... It really feels like SurfaceFlinger is starting on a random device. 😩
21:20 gfxstrand[d]: But IDK what switching to the tegra back-end changes
21:22 gfxstrand[d]: I'm going to wipe and re-image
21:22 steel01[d]: gfxstrand[d]: So, I set a prop to tell drm_hwcomposer to use the nouveau device. Iirc, if that's set to tegra, it fails to initialize.
21:22 steel01[d]: https://gitlab.incom.co/CM-Shield/android_device_nvidia_tegra-common/-/blob/lineage-23.0/properties.mk?ref_type=heads#L58-59
21:22 steel01[d]: The other prop used by hwc is pointing to card0, which is tegra. Tbh, I don't know what either are doing specifically, like if one is rendering and the other is for scanout, etc.
21:23 steel01[d]: I think I tried all combinations at one point and this was the only one that put pixels on the screen using dumb buffers. But that's been a couple years.
21:25 gfxstrand[d]: All I'm doing is monkeying around with which back-end we use for gralloc. If I tell gralloc to build for tegra, I get pixels but they're wrong. If I build for nouveau, no pixels
21:26 gfxstrand[d]: And I've got nouveau hacked to enumerate on the tegra device and then allocate on nouveau behind tegra's back.
21:27 steel01[d]: It'd be nice to have someone that understands the android graphics system around to bounce questions off of. Is anyone that works on the FD copy of drm_hwcomposer on this server?
21:27 gfxstrand[d]: no
21:27 steel01[d]: Sadness.
21:30 gfxstrand[d]: Like, what all does TARGET_MINIGBM_PLATFORM control? Is it just what back-end gets built? Or is it plumbed into like 3 other things?
21:30 gfxstrand[d]: Because that's the only one I'm monkeying with
21:33 steel01[d]: https://github.com/LineageOS/android_device_mainline_common/blob/lineage-23.0/optional/minigbm/board.mk#L8
21:33 steel01[d]: We've modularized several things for lineage, so devices don't have to duplicate the same things over and over. That flag mainly gets used here. It's also used to set the appropriate hidl build target name, if hidl is used.
21:33 steel01[d]: https://gitlab.freedesktop.org/gfxstrand/minigbm/-/blob/nouveau/Android.bp?ref_type=heads#L101-110
21:33 steel01[d]: That's then used in minigbm to select the backend, like here.
21:33 steel01[d]: Afaik, it's not plumbed into anything else. It's only selecting the backend inside the minigbm service.
21:34 gfxstrand[d]: That's what I figured
21:34 steel01[d]: Hwc configuration is handled separately. Like via the props I linked earlier.
21:35 steel01[d]: That code is in external/drm_hwcomposer. If you can make any sense of that. It's googles fork of the project, so it's not going to match FD's copy exactly.
21:35 gfxstrand[d]: So it's pretty clear to me that HWComposer and/or SurfaceFlinger isn't even really calling into gralloc. No one even attempts to allocate a BO most of the time.
21:36 gfxstrand[d]: I had one boot where it did but can't reproduce
21:37 steel01[d]: Is it not? It might be using mapper, which is related to gralloc and shares some code but isn't gralloc. This is where I really don't understand the architecture.
21:39 steel01[d]: 01-01 00:00:30.727 736 740 I MESA : Using gralloc0 CrOS API
21:39 steel01[d]: The mesa userspace is aware of gralloc. And afaik, hwc uses the graphics userspace.
21:40 steel01[d]: 01-01 00:00:30.783 736 740 E [minigbm:drv_get_backend(112)]: Looking for backend to match tegra
21:40 steel01[d]: 01-01 00:00:30.783 736 740 E [minigbm:drv_get_backend(116)]: Matched backend tegra
21:40 steel01[d]: 01-01 00:00:30.799 736 740 I RenderEngine: OpenGL ES informations:
21:40 steel01[d]: 01-01 00:00:30.799 736 740 I RenderEngine: vendor : Mesa
21:40 steel01[d]: 01-01 00:00:30.799 736 740 I RenderEngine: renderer : NV13B
21:40 steel01[d]: 01-01 00:00:30.799 736 740 I RenderEngine: version : OpenGL ES 3.2 Mesa 25.2.3
21:40 steel01[d]: RenderEngine is calling into gralloc. The two minigbm lines are prints I added for debugging.
21:41 steel01[d]: And yes, this is on tx2, but the tx1 flow up to this point is effectively the same.
21:41 gfxstrand[d]: Yeah, RenderEngine seems okay here
21:42 x512[m]: I wonder why minigbm is not included in Mesa upstream. Including whole Gallium OpenGL driver just for implementing tiny GBM API is overkill. Especially if using Vulkan.
21:42 steel01[d]: 01-01 00:00:31.112 736 736 E HwcComposer: getPerFrameMetadataKeys failed Status(-8, EX_SERVICE_SPECIFIC): '8: '
21:42 steel01[d]: 01-01 00:00:31.120 736 736 E [minigbm:drv_get_backend(112)]: Looking for backend to match tegra
21:42 steel01[d]: 01-01 00:00:31.120 736 736 E [minigbm:drv_get_backend(116)]: Matched backend tegra
21:42 steel01[d]: Here's minigbm getting called from the hwc pid. So it seems to be doing something.
21:45 steel01[d]: x512[m]: There's a gbm_gralloc driver that uses libdrm to do stuff. That's kind of like a built-in gralloc driver. I'm not entirely certain how it does plumbing. It does work for tegra, but seems like it has the same block linear issues that the minigbm dumb buffer backend has.
21:45 steel01[d]: Or is that what you're saying? Something like minigbm should be used instead of that libdrm thing?
21:47 x512[m]: No, it is different and more generic thoughts.
21:47 gfxstrand[d]: x512[m]: Because minigbm isn't gbm. It was originally an exercise of "what if we rewrote GBM but without any Mesa components?" and then they bolted on a bunch of Android.
21:48 x512[m]: About block linear issues: do you mean that GBM tiled image import/export not working properly? I feel I heard that Nvidia do not plan to support that and OpenGL/Vulkan API is needed to tile/detile image.
21:49 gfxstrand[d]: GBM is fine. It's all the Android stuff that's busted
21:50 gfxstrand[d]: "Real GBM", that is
21:50 steel01[d]: gfxstrand[d]: can explain that better than me. Iiuc, stuff like dumb buffers doesn't use tiles at all, but tegra needs tiles.
21:50 x512[m]: Proprietary Nvidia GBM driver,
21:50 gfxstrand[d]: Presumably that works?
21:51 steel01[d]: Kinda hard to verify that on android as atm, no drm compliant proprietary kernel driver and userspace is available publicly.
21:51 steel01[d]: Unless someone wants to make nouveau support the orin stuff. And add a minigbm backend for that.
21:52 x512[m]: GBM do not integrate great with Vulkan world.
21:52 gfxstrand[d]: <a:shrug_anim:1096500513106841673> It's kinda fine.
21:53 gfxstrand[d]: Zink can be a GBM back-end and then Vulkan allocates everything
21:53 gfxstrand[d]: I mean, yeah, if you're writing a Vulkan-only thing, you don't need GBM. But if you're relying on GBM, it still works.
21:55 x512[m]: Is it possible to make Wayland compositor with pure Vulkan and without GBM? Or GBM is still need for some backward compatibility?
21:55 gfxstrand[d]: Sure
21:56 x512[m]: So GBM is effectively OpenGL-specific thing?
21:57 steel01[d]: Okay, so on the tegra android stuff. If you use the tegra backend, you see what I was seeing. The broken stride on t210. And then I see broken texture creation on t186. The theory was that tegra buffers getting imported into nouveau are losing modifiers. So... is there anything userspace can do here? Or does this become solely a kernel driver issue?
21:58 gfxstrand[d]: I think userspace can work around it
21:59 steel01[d]: So if I'm understanding stuff properly, then using the tegra backend is correct. And what needs fixed is the modifiers issue. Then in theory, stuff just falls into place.
21:59 gfxstrand[d]: But I need to figure out why it's not even trying to use my gralloc first
21:59 steel01[d]: Is it not? How would stuff be on screen, then?
21:59 gfxstrand[d]: Not when I tell it to use my back-end
21:59 gfxstrand[d]: Nothing's on screen
21:59 gfxstrand[d]: Just more hwcomposer blowing up inexplicably
22:00 steel01[d]: Are you talking about the nouveau backend, using nouveau ioctls?
22:00 gfxstrand[d]: I've hacked up the nouveau back-end to pretend to be a tegra back-end
22:00 steel01[d]: Does it report as 'tegra'? Binding to the tegra dri device?
22:00 gfxstrand[d]: yup
22:01 x512[m]: Which one Tegra is using? nvrm? nvgpu?
22:01 gfxstrand[d]: tegra
22:01 steel01[d]: Mmm. That I dunno, then. I know the pure tegra backend puts pixels on screen and stuff is somehow getting passed to nouveau.
22:01 gfxstrand[d]: Well, tegra for display, nouveau for 3D
22:01 gfxstrand[d]: Nouveau starts up fine
22:02 gfxstrand[d]: `RenderEngine: version : OpenGL ES 3.2 Mesa 25.2.3`
22:02 steel01[d]: This is all mainline drivers and mesa. No downstream nvidia drivers like nvrm, nvgpu, nvidia-drm, etc.
22:03 steel01[d]: Alexandre Courbot did a big mesa support push back in like 2014-2015 and... a lot of it still works now, even though it's gotten very little support since.
22:03 mhenning[d]: Anyone want to review https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37922 so I can fix the thing I broke last week?
22:07 gfxstrand[d]: steel01[d]: I'd be tempted to pull in my NVK tegra cache patches, and try running Vulkan-only with the tegra gralloc backend
22:09 gfxstrand[d]: I'm just afraid of making that big of a change
22:09 gfxstrand[d]: But NVK can work around the tiling issues. NGL can't
22:10 gfxstrand[d]: But also, I'd really like to know why SurfaceFlinger dan't find the right device and keeps crashing
22:10 steel01[d]: Mmm. Let me take a try at your nouveau backend changes. See if I can't get stuff to print about what the gbm service is doing.
22:11 steel01[d]: It's possible that depending on the order stuff queries the gbm driver with, it could grab the nouveau device instead of tegra. It *should* always ask for tegra first since that's card0, but probably best to not assume that's deterministic.
22:16 gfxstrand[d]: `drmhwc : No pipelines available. Creating null-display for headless mode`
22:16 gfxstrand[d]: I'm pretty sure that's the problem
22:17 steel01[d]: Mmm. That's similar to what was happening when the nouveau ioctls were used. The graphics stack was unable to find display info. Or probably failed to find displays at all.
22:21 gfxstrand[d]: Okay, for reference, nouveau is card0 and tegra is card1 on my machine
22:21 gfxstrand[d]: So right now we're forcing drm_hwcomposer to use the nouveau node which obviously isn't going to work.
22:21 steel01[d]: Uh. Wow, not sure how that happened. But great, makes my point. Not deterministic.
22:23 steel01[d]: Mmm. And that prop wants a path, not a name. So if the card numbers aren't deterministic... that's a problem.
22:23 gfxstrand[d]: Well, I should be more specific. I'ts minor 0 vs. minor 1
22:24 steel01[d]: Oh, this isn't like /dev/dri/card0 vs 1?
22:24 gfxstrand[d]: maybe?
22:27 steel01[d]: Alright, kicked a build with your changes plus a slight amount of cleanup. Targeting the nouveau backend. I'll see which backend is getting matched.
22:31 gfxstrand[d]: let me push again
22:32 gfxstrand[d]: Okay
22:32 steel01[d]:stops build
22:32 gfxstrand[d]: pushed
22:35 gfxstrand[d]: steel01[d]: I tried with tegra and first boot didn't come up but the second did and now tegra is on minor 0 and nouveau is on minor 1. :facepalm:
22:35 steel01[d]: 0o
22:35 gfxstrand[d]: I don't think it has anything to do with building gralloc for tegra/nouveau since it's a kernel thing and way too early
22:36 steel01[d]: Yeah, exactly. tegra-drm is in the ramdisk. And nouveau is on /vendor. So there shouldn't be any way that nouveau gets probed earlier. Unless tegra-drm got defer'ed there and back again, but I don't know why that'd happen.
22:36 gfxstrand[d]: I'm also seeing
22:36 gfxstrand[d]: 01-01 00:00:16.769 523 523 E drmhwc : Opening dri /dev/dri/card0
22:36 gfxstrand[d]: 01-01 00:00:16.853 523 523 I drmhwc : Attaching connector HDMI-A-1
22:36 gfxstrand[d]: 01-01 00:00:16.854 523 523 I drmhwc : Attaching pipeline 'HDMI-A-1' to the display #0 (Primary)
22:36 gfxstrand[d]: 01-01 00:00:16.881 523 523 I drmhwc : Backend 'generic' for 'HDMI-A-1' and driver 'tegra' was successfully set
22:37 steel01[d]: But okay, if it came up. What's the display look like?
22:37 gfxstrand[d]: I'm not seeing that minigbm nouveau
22:37 gfxstrand[d]: garbled
22:37 steel01[d]: Same stride issue, or new broken?
22:37 gfxstrand[d]: same tiling issue
22:37 steel01[d]: Mmm.
22:38 steel01[d]: gfxstrand[d]: What do you mean you're not seeing minigbm?
22:39 gfxstrand[d]: In my previous attempts, nouveau would come up on minor 0, drmhwc would pick that, and it would fail.
22:39 steel01[d]: If you reproduce that nouveau/tegra-drm init order issue again, can you pull dmesg? Like `adb shell dmesg > dmesg`. I'd be curious to see what the heck the kernel did.
22:39 gfxstrand[d]: My minigbm back-end wouldn't even get called
22:40 steel01[d]: I'll go ahead and let this build go. I added the nouveau backend back in to the init list. Will see if I can reproduce the ordering issue.
22:41 gfxstrand[d]: I just pulled a logcat and a dmesg on my successful(ish) minigbm_tegra boot.
22:41 gfxstrand[d]: Re-buildling now
22:43 steel01[d]: Um. Oi, confusing overlap in terms here. Let me make sure I've got this straight. You're building with `TARGET_MINIGBM_PLATFORM = nouveau`, but you've commented out the nouveau backend from the init list. So the service gets built with drv_nouveau, not drv_tegra. And the only driver available for init is the tegra variant in drv_nouveau.
22:44 gfxstrand[d]: If you set `TARGET_MINIGBM_PLATFORM = nouveau`, it will build two back-ends. One is the normal nouveau back-end. The other is nouveau pretending to be tegra.
22:45 steel01[d]: Right. And that's what you're building and working on, yes?
22:45 gfxstrand[d]: y
22:45 steel01[d]: Okay. Got a tad confused when you said 'minigbm_tegra'. Like... *which* tegra? ><
22:46 gfxstrand[d]: When I say minigbm_tegra, I mean OG tegra
22:46 gfxstrand[d]: But right now minigbm_nouveau can pretend to be tegra
22:46 steel01[d]: Ahhhh... okay. This makes sense now.
22:46 gfxstrand[d]: But I'm starting to think that's not really necessary and that the problem is entirely hwc booting on the wrong fdevice
22:47 steel01[d]: If card0/1 isn't consistent, but drm_hwc wants a hardcoded path... That's gonna be a problem.
22:51 gfxstrand[d]: Oh... I wonder if we don't need to make detect_device_info() smarter
22:57 gfxstrand[d]: Nice!
22:57 gfxstrand[d]: New backtrace!
22:57 gfxstrand[d]: https://cdn.discordapp.com/attachments/1034184951790305330/1429966828435800156/message.txt?ex=68f80fe3&is=68f6be63&hm=1d2ec458b99f81a30aa7db3931c4dcb02383e196086e62e67b8af3de8e0b0fa1&
22:57 gfxstrand[d]: I'm gonna call that a win
22:58 steel01[d]: It's progress at least. 😛
22:58 gfxstrand[d]: [ 183.371924] nouveau 57000000.gpu: fifo: fault 01 [WRITE] at 000000000276c000 engine 00 [gr] client 0f [GPC0/PROP_0] reason 02 [PTE] on channel 3 [04002d2000 BootAnimation[9122]]
22:58 gfxstrand[d]: [ 183.388431] nouveau 57000000.gpu: fifo:000000:0003:[BootAnimation[9122]] rc scheduled
22:58 gfxstrand[d]: [ 183.396944] nouveau 57000000.gpu: fifo:000000: rc scheduled
22:58 gfxstrand[d]: [ 183.403379] nouveau 57000000.gpu: fifo:000000:0003:0003:[BootAnimation[9122]] errored - disabling channel
22:58 gfxstrand[d]: [ 183.413638] nouveau 57000000.gpu: BootAnimation[9115]: channel 3 killed!
22:59 steel01[d]: I got a couple things like that randomly on my tegra backend. If I rebooted after that, it started rendering again. Which is almost more scary. Non-consistent failures.
23:00 gfxstrand[d]: So the key was that minigbm was setting the wrong `dev_type_flags`. We need to say tegra is display-only and nouveau is 3D-only
23:01 steel01[d]: Oh. That list is operable. I wasn't sure if it was or not.
23:01 gfxstrand[d]: Annoyingly, actually getting that right dynamically requires a HW chipset check so it's gonna be a hack for pre-Orin for now
23:03 gfxstrand[d]: Okay this enumeration order randomness is driving me nuts
23:04 steel01[d]: Grab a dmesg if nouveau is card0, please.
23:05 gfxstrand[d]: https://cdn.discordapp.com/attachments/1034184951790305330/1429968744280621107/dmesg.nouveau?ex=68f811ac&is=68f6c02c&hm=56d97f187414fe2e70273027a0d23c63017f9cdff92a1c150ad46d1e5f8ab9df&
23:05 gfxstrand[d]: https://cdn.discordapp.com/attachments/1034184951790305330/1429968744746061884/dmesg.tegra?ex=68f811ac&is=68f6c02c&hm=a5a9c202bec4bc8040904d264372e19e8acd7e96edbe2114f30cb03ce8e80fe4&
23:05 gfxstrand[d]: .nouveau is card0 .tegra is card1
23:05 gfxstrand[d]: And with that, I'm headed home
23:08 steel01[d]: [ 6.449696] [drm] Initialized nouveau 1.4.0 for 57000000.gpu on minor 0
23:08 steel01[d]: *snip*
23:08 steel01[d]: [ 6.670100] [drm] Initialized tegra 1.0.0 for drm on minor 1
23:08 steel01[d]: :wat:
23:09 steel01[d]: versus the other log:
23:09 steel01[d]: [ 6.638876] [drm] Initialized tegra 1.0.0 for drm on minor 0
23:09 steel01[d]: *snip*
23:09 steel01[d]: [ 7.581124] [drm] Initialized nouveau 1.4.0 for 57000000.gpu on minor 1
23:11 steel01[d]: I'm confused. But I can force it to work as desired, by making init wait until the dri dev node is generated. It'll slow boot down a bit, but it's a reasonable trade-off to ensure proper order.
23:24 gfxstrand[d]: steel01[d]: Yup...
23:26 steel01[d]: I wonder if there's a way to make the ramdisk module loading a blocking operation. Seems like it's just firing and forgetting all the module loads.
23:26 steel01[d]: I'll figure something out tonight and post a snippet to be copy-pasted into the tree when you're next working on it.
23:43 steel01[d]: 01-01 00:00:25.659 641 641 F DEBUG : Abort message: 'Failed to create a valid texture. [0xb400002b8e009ed0]:[128,128] isProtected:0 isWriteable:1 format:1'
23:43 steel01[d]: Well, this stack trace is a bit different from yours. It's coming from surfaceflinger.
23:43 steel01[d]: On a tx1 devkit.
23:47 steel01[d]: Then I rebooted and got nouveau as card0 and got a stack trace matching yours. Whee. Yep, I'll force tegra-drm to finish enumerating before the non-ramdisk kernel modules, including nouveau, get loaded.