00:45 soreau: after setting the zink env var, "OpenGL renderer string: zink Vulkan 1.4(NVIDIA GeForce GTX 1660 Ti (NVK TU116) (MESA_NVK))"
00:45 soreau: "wow now i get over 100-120 (high of 160)fps where before is was getting 60-70."
00:45 gfxstrand[d]: \o/
00:46 gfxstrand[d]: What game?
00:48 soreau: gfxstrand[d]: the best one of them all:
00:48 soreau: Wayfire
00:50 soreau: gfxstrand[d]: actually they got the fps readings from "unigine valley" running in wayfire
02:32 gfxstrand[d]: Nice
06:00 brickasynctransfer: https://www.geeksforgeeks.org/asynchronous-data-transfer/ it's a matter of read and write strobes. Hypothetically it's that everything is read-modify-write consisting of read cycles then modify cycles then write cycles, internet has that information, those are 3clocks, previous material suggested pair of cycles which would be read write i.e no indirection. however if the strobe is
06:00 brickasynctransfer: output without data nor clocks of those cycles, likely it will charge in with control over the clocks of receiver device. But you can however read that from accelerator cores logic.
06:16 brickasynctransfer: So what it likely boils down to, if something is not configured correctly engineers had the option to freeze the system, or cause anomaly to go through or just make a performance backdoor, so if it gets no responses from axi or ddr clocks, dma is putting the read and write strobes out, if something was misconfigured, i expect like this, so but they guard for this with dma firmwares,
06:16 brickasynctransfer: and flyby mode is that so colled cyclic mode of incremental or decremental.
06:16 brickasynctransfer: that would mean 1 cycle transfer on bursts or something.
06:57 gendertrends: https://github.com/ZipCPU/wb2axip/blob/master/rtl/axidma.v default is always write-strobe on, so it's clocked after that initial set is write strobe on, since likely they wanted to configure it somehow through axi, so if you do not configure it write the clock goes definitely in. https://ardent-tool.com/comms/Parallel_DMA.html cpu does not use axi inside cpu core, and we know that memory
06:57 gendertrends: reads are back to back controlled by axi/pci configuration instead on most cpus.
07:06 gendertrends: By the way that zipcpu guy when you google that guy, he was on #verilog channel and used to be or is even now, United States Air Force programmer.
20:26 metsikosausi: There is such library as spdk that claims userspace dma access. Anyone knows if it's possible to do dummy access as described in here https://www.analog.com/media/en/technical-documentation/data-sheets/max32670-max32671-errata-sheet-revision-a2-errata.pdf with spdk, like i do not know linux that well anymore at all, that is big library but maybe hugepages and some certain marking and
20:26 metsikosausi: mapping the pci device to userspace, could issue dma transfers as out of memory map dummy reads, i am trying as much as possible and have very few time, thank you!?
20:26 airlied: /msg dwfreed joss .metsikosausi
20:27 airlied: /msg dwfreed .joss metsikosausi
20:27 airlied: oops
20:28 dwfreed: oops
20:30 HdkR: 🎉