00:34 mhenning[d]: https://cdn.discordapp.com/attachments/1034184951790305330/1327435461915836526/image.png?ex=67830e1c&is=6781bc9c&hm=0308874579fe890107b0a584e6b04c13adeb2ffc90228ba17960548955766865&
00:34 mhenning[d]: oh, interesting. it looks like renderdoc is showing us spending almost all of our time in depth-only passes on this trace of baldur's gate 3 I have. I wonder if we're setting up depth attachments in a way that the hardware doesn't like or something
01:42 gfxstrand[d]: It's possible. Or maybe it just really wants zcull?
01:46 mhenning[d]: It kind of looks like it affects depth-only more than color+depth, which would make me guess that it isn't zcull
01:46 mhenning[d]: but I'm just speculating at this point
03:29 gfxstrand[d]: It's possible we're doing something wrong with depth state and forcing late depth testing or something.
03:30 gfxstrand[d]: I wonder if Nvidia hardware would benefit from depth/stencil state optimization. 🤔
22:02 redsheep[d]: I wonder how the multiple encoders and decoders work on Blackwell. Does the work just get distributed by the hardware or gsp, or does the driver need to do something to make use of more than one?
22:03 redsheep[d]: I suppose the dual encoders on ada could probably already be used to check
22:24 dwlsalmeida[d]: redsheep[d]: read in some marketing material that it works transparently
22:25 redsheep[d]: That's good
22:26 redsheep[d]: Though, if it's marketing material they're not going to explain how their drivers work, and they still could be hiding the complexity, no?
22:26 avhe[d]: on tegra you can specify which instance you want the decode to happen to, or there is really basic load balancing (iirc it ping pong between the two decoders)
22:27 dwlsalmeida[d]: Hence why I specifically said “marketing material” 😁
22:27 dwlsalmeida[d]: So it could just be something someone said to boost sales or something lol
22:28 redsheep[d]: Yeah. Sounds like it's probably not a huge concern yet though, worst case would be only getting throughput of one of each and that's still quite a lot
22:28 dwlsalmeida[d]: avhe[d]: Didn’t know they had multiple decoders on tegra
22:51 avhe[d]: on some models only
22:51 avhe[d]: not on the X1 so i haven't looked in detail
23:25 dwlsalmeida[d]: airlied[d]: well, question being, if we're using the same firmware as them, why does it work for them, and not for us? iow: if they're parsing stuff on the firmware, why do we have to send this value?
23:29 airlied[d]: I'm sure the fw is different