01:33dwlsalmeida[d]: Wait this is starting to get a bit weird:
01:34dwlsalmeida[d]: This is the C version with `NVK_DEBUG=push_dump`:
01:34dwlsalmeida[d]: mthd 0000 NV906F_SET_OBJECT
01:34dwlsalmeida[d]: .NVCLASS = (0xc5b0)
01:34dwlsalmeida[d]: .ENGINE = 0x0
01:34dwlsalmeida[d]: [0x00000002] HDR 20018080 subch 4 NINC
01:34dwlsalmeida[d]: mthd 0200 NVC5B0_SET_APPLICATION_ID
01:34dwlsalmeida[d]: .ID = H264
01:34dwlsalmeida[d]: [0x00000004] HDR 20018100 subch 4 NINC
01:34dwlsalmeida[d]: mthd 0400 NVC5B0_SET_CONTROL_PARAMS
01:34dwlsalmeida[d]: .CODEC_TYPE = H264
01:34dwlsalmeida[d]: .GPTIMER_ON = (0x1)
01:34dwlsalmeida[d]: .RET_ERROR = (0x0)
01:34dwlsalmeida[d]: .ERR_CONCEAL_ON = (0x1)
01:34dwlsalmeida[d]: .ERROR_FRM_IDX = (0x0)
01:34dwlsalmeida[d]: .MBTIMER_ON = (0x1)
01:34dwlsalmeida[d]: .EC_INTRA_FRAME_USING_PSLC = (0x0)
01:34dwlsalmeida[d]: .ALL_INTRA_FRAME = (0x0)
01:34dwlsalmeida[d]: .RESERVED = (0x0)
01:34dwlsalmeida[d]: [0x00000006] HDR 20068101 subch 4 NINC
01:34dwlsalmeida[d]: mthd 0404 NVC5B0_SET_DRV_PIC_SETUP_OFFSET
01:34dwlsalmeida[d]: .OFFSET = (0x3ffba0f0)
01:34dwlsalmeida[d]: mthd 0408 NVC5B0_SET_IN_BUF_BASE_OFFSET
01:34dwlsalmeida[d]: .OFFSET = (0x3ffba2f0)
01:35dwlsalmeida[d]: mthd 040c NVC5B0_SET_PICTURE_INDEX
01:35dwlsalmeida[d]: .INDEX = (0x0)
01:35dwlsalmeida[d]: mthd 0410 NVC5B0_SET_SLICE_OFFSETS_BUF_OFFSET
01:35dwlsalmeida[d]: .OFFSET = (0x3ffba0f3)
01:35dwlsalmeida[d]: mthd 0414 NVC5B0_SET_COLOC_DATA_OFFSET
01:35dwlsalmeida[d]: .OFFSET = (0x3ffbbd00)
01:35dwlsalmeida[d]: mthd 0418 NVC5B0_SET_HISTORY_OFFSET
01:35dwlsalmeida[d]: .OFFSET = (0x3ffbb900)
01:35dwlsalmeida[d]: [0x0000000d] HDR 20018109 subch 4 NINC
01:35dwlsalmeida[d]: mthd 0424 NVC5B0_SET_NVDEC_STATUS_OFFSET
01:35dwlsalmeida[d]: .OFFSET = (0x3ffba0f4)
01:35dwlsalmeida[d]: [0x0000000f] HDR 2022810c subch 4 NINC
01:35dwlsalmeida[d]: mthd 0430 NVC5B0_SET_PICTURE_LUMA_OFFSET0
01:35dwlsalmeida[d]: .OFFSET = (0x3ffbb700)
01:35dwlsalmeida[d]: mthd 0434 NVC5B0_SET_PICTURE_LUMA_OFFSET1
01:35dwlsalmeida[d]: .OFFSET = (0x0)
01:35dwlsalmeida[d]: mthd 0438 NVC5B0_SET_PICTURE_LUMA_OFFSET2
01:35dwlsalmeida[d]: etc
01:35dwlsalmeida[d]: This is the Rust version
01:35dwlsalmeida[d]: [0x00000000] HDR 80038080 subch 4 IMMD
01:35dwlsalmeida[d]: mthd 0200 NVC5B0_SET_APPLICATION_ID
01:35dwlsalmeida[d]: .ID = H264
01:35dwlsalmeida[d]: [0x00000001] HDR 20078100 subch 4 NINC
01:35dwlsalmeida[d]: mthd 0400 NVC5B0_SET_CONTROL_PARAMS
01:35dwlsalmeida[d]: .CODEC_TYPE = H264
01:35dwlsalmeida[d]: .GPTIMER_ON = (0x1)
01:35dwlsalmeida[d]: .RET_ERROR = (0x0)
01:35dwlsalmeida[d]: .ERR_CONCEAL_ON = (0x1)
01:35dwlsalmeida[d]: .ERROR_FRM_IDX = (0x0)
01:35dwlsalmeida[d]: .MBTIMER_ON = (0x1)
01:35dwlsalmeida[d]: .EC_INTRA_FRAME_USING_PSLC = (0x0)
01:35dwlsalmeida[d]: .ALL_INTRA_FRAME = (0x0)
01:35dwlsalmeida[d]: .RESERVED = (0x0)
01:35dwlsalmeida[d]: mthd 0404 NVC5B0_SET_DRV_PIC_SETUP_OFFSET
01:35dwlsalmeida[d]: .OFFSET = (0x3fffde00)
01:35dwlsalmeida[d]: mthd 0408 NVC5B0_SET_IN_BUF_BASE_OFFSET
01:35dwlsalmeida[d]: .OFFSET = (0x3fffe000)
01:35dwlsalmeida[d]: mthd 040c NVC5B0_SET_PICTURE_INDEX
01:35dwlsalmeida[d]: .INDEX = (0x0)
01:35dwlsalmeida[d]: mthd 0410 NVC5B0_SET_SLICE_OFFSETS_BUF_OFFSET
01:35dwlsalmeida[d]: .OFFSET = (0x3fffde03)
01:35dwlsalmeida[d]: mthd 0414 NVC5B0_SET_COLOC_DATA_OFFSET
01:35dwlsalmeida[d]: .OFFSET = (0x3ffffb00)
01:35dwlsalmeida[d]: mthd 0418 NVC5B0_SET_HISTORY_OFFSET
01:35dwlsalmeida[d]: .OFFSET = (0x3ffff800)
01:35dwlsalmeida[d]: [0x00000009] HDR 20018109 subch 4 NINC
01:35dwlsalmeida[d]: mthd 0424 NVC5B0_SET_NVDEC_STATUS_OFFSET
01:35dwlsalmeida[d]: .OFFSET = (0x3fffde07)
01:35dwlsalmeida[d]: [0x0000000b] HDR 2022810c subch 4 NINC
01:35dwlsalmeida[d]: mthd 0430 NVC5B0_SET_PICTURE_LUMA_OFFSET0
01:35dwlsalmeida[d]: .OFFSET = (0x3ffffc30)
01:35dwlsalmeida[d]: mthd 0434 NVC5B0_SET_PICTURE_LUMA_OFFSET1
01:35dwlsalmeida[d]: .OFFSET = (0x0)
01:35dwlsalmeida[d]: mthd 0438 NVC5B0_SET_PICTURE_LUMA_OFFSET2
01:35dwlsalmeida[d]: .OFFSET = (0x0)
01:35dwlsalmeida[d]: mthd 043c NVC5B0_SET_PICTURE_LUMA_OFFSET3
01:35dwlsalmeida[d]: .OFFSET = (0x0)
01:35dwlsalmeida[d]: mthd 0440 NVC5B0_SET_PICTURE_LUMA_OFFSET4
01:35dwlsalmeida[d]: .OFFSET = (0x0)
01:35dwlsalmeida[d]: mthd 0444 NVC5B0_SET_PICTURE_LUMA_OFF
01:36dwlsalmeida[d]: the offsets in square brackets do not match
01:37airlied[d]: as long as they encode sane things, it shouldn't matter
01:38airlied[d]: though the first SET_OBJECT seems missing in the rust version
01:40dwlsalmeida[d]: ok, I edited it to force a SET_OBJECT
01:40dwlsalmeida[d]: calling this `append_rust_push` twice seems to be not working, so I moved the set_object to `vkCmdDecodeVideoKHR`
01:41dwlsalmeida[d]: I am trying to pin this down on the Rust version of `nv_push`, which is why I am looking at the offset thing
01:50dwlsalmeida[d]: what is the replacement for `mem->bo->offset` with the new `nvkmd` stuff I wonder?
01:55dwlsalmeida[d]: maybe `nvkmd_mem::va::addr`? `nouveau_ws_alloc_vma` is not called anymore
02:03skeggsb9778[d]: airlied[d]: I don't *think* you need to send it these days anyway (though i'm also not 100% sure of what hw that started on), though it is a way to have HW validate the driver knows what class its speaking to
02:04airlied[d]: you have to set it at least once
02:04airlied[d]: but not sure either
02:05airlied[d]: I think the prop driver sends it anyways
02:05skeggsb9778[d]: SetObject is a misnomer: the GPU provides no mechanism for SW to select any
02:05skeggsb9778[d]: other class interface than the one a given chip supports. SetObject is not
02:05skeggsb9778[d]: required by any engine.
02:05skeggsb9778[d]: from dev_pbdma.ref
02:05skeggsb9778[d]: It used to serve that purpose, it's just verification now
02:06skeggsb9778[d]: dev_pbdma.ref talks a bit more about it in the same section i copied+pasted from
02:06airlied[d]: dwlsalmeida[d]: yeah I think addr is the offset, but I'm not fully across the new code
02:08airlied[d]: dwlsalmeida[d]: do you have some pushbufs generated by C and some by rust in the same submission?
02:30dwlsalmeida[d]: maybe?
02:30dwlsalmeida[d]: (I guess so)
02:31dwlsalmeida[d]: can anyone decipher this?
02:31dwlsalmeida[d]: [23006.154969] nouveau 0000:01:00.0: gsp: rc engn:00000013 chid:40 type:68 scope:1 part:233
02:31dwlsalmeida[d]: [23006.154977] nouveau 0000:01:00.0: fifo:6606c307:0005:0028:[gst-launch-1.0[62742]] errored - disabling channel
02:31dwlsalmeida[d]: [23006.154982] nouveau 0000:01:00.0: gst-launch-1.0[62742]: channel 40 killed!
02:31dwlsalmeida[d]: maybe the firmware log parser thing will help again this time :/
07:20airlied[d]: I'd say you can figure that out without it, not by decoding that, but just checking what userspace is submitting
11:37dwlsalmeida[d]: I’m dumping both pushbufs with nvk_debug=push_dump, and I’ve traced both picture parameters
11:37dwlsalmeida[d]: Something is seriously wrong because this is a single 16x16 I frame, not much can go wrong here
12:31dwlsalmeida[d]: If you look closely, the method headers emitted by the rust nv_push do not match either
21:29airlied[d]: yup, so I think fixing any differences in the C vs rust should be the main priority, since you have working C code