16:13dwlsalmeida[d]: avhe[d]: would you happen to know why your tracer crashes in gstreamer?
16:13dwlsalmeida[d]: Program received signal SIGSEGV, Segmentation fault.
16:13dwlsalmeida[d]: 0x00007ffff7f99bf7 in auto ioctl::{lambda(auto:1&)#6}::operator()<DmaAllocInfo>(DmaAllocInfo&) const ()
16:13dwlsalmeida[d]: from /home/dwls/dev/NvdecTrace/build/linux/x86_64/debug/inject
16:13dwlsalmeida[d]: (gdb) bt
16:13dwlsalmeida[d]: #0 0x00007ffff7f99bf7 in auto ioctl::{lambda(auto:1&)#6}::operator()<DmaAllocInfo>(DmaAllocInfo&) const ()
16:13dwlsalmeida[d]: at /home/dwls/dev/NvdecTrace/build/linux/x86_64/debug/inject
16:13dwlsalmeida[d]: #1 0x00007ffff7f9e7c7 in bool std::__invoke_impl<bool, ioctl::{lambda(auto:1&)#6}&, DmaAllocInfo&>(std::__invoke_other, ioctl::{lambda(auto:1&)#6}&, DmaAllocInfo&) () at /home/dwls/dev/NvdecTrace/build/linux/x86_64/debug/inject
16:13dwlsalmeida[d]: #2 0x00007ffff7f9e280 in std::__invoke_result<ioctl::{lambda(auto:1&)#6}&, DmaAllocInfo&>::type std::__invoke<ioctl::{lambda(auto:1&)#6}&, DmaAllocInfo&>(ioctl::{lambda(auto:1&)#6}&, DmaAllocInfo&) () at /home/dwls/dev/NvdecTrace/build/linux/x86_64/debug/inject
16:13dwlsalmeida[d]: #3 0x00007ffff7f9dd38 in std::_List_iterator<DmaAllocInfo> std::ranges::__find_if_fn::operator()<std::_List_iterator<DmaAllocInfo>, std::_List_iterator<DmaAllocInfo>, std::identity, ioctl::{lambda(auto:1&)#6}>(std::_List_iterator<DmaAllocInfo>, std::_List_iterator<DmaAllocInfo>, ioctl::{lambda(auto:1&)#6}, std::identity) const () at /home/dwls/dev/NvdecTrace/build/linux/x86_64/debug/inject
16:13dwlsalmeida[d]: #4 0x00007ffff7f99c7b in std::__conditional<borrowed_range<std::__cxx11::list<DmaAllocInfo, std::allocator<DmaAllocInfo> >&> >::type<decltype (__begin((declval<std::__cxx11::list<DmaAllocInfo, std::allocator<DmaAllocInfo> >&>)())), std::ranges::dangling> std::ranges::__find_if_fn::operator()<std::__cxx11::list<DmaAllocInfo, std::allocator<DmaAllocInfo> >&, std::identity,
16:13dwlsalmeida[d]: ioctl::{lambda(auto:1&)#6}>(std::__cxx11::list<DmaAllocInfo, std::allocator<DmaAllocInfo> >&, ioctl::{lambda(auto:1&)#6}, std::identity) const () at /home/dwls/dev/NvdecTrace/build/linux/x86_64/debug/inject
16:13dwlsalmeida[d]: ioctl ()
16:14dwlsalmeida[d]: I could debug that myself but I can't get a debug build with symbols, even running `xmake f --menu` and ticking the `debug` build type
16:39dwlsalmeida[d]: yeah, ditching this `xmake` thing altogether and compiling directly with g++ gives:
16:39dwlsalmeida[d]: 619 case NV_ESC_RM_UNMAP_MEMORY: {
16:39dwlsalmeida[d]: 620 auto *params = static_cast<NVOS34_PARAMETERS *>(arg);
16:39dwlsalmeida[d]: 621
16:39dwlsalmeida[d]: 622 if (auto alloc = std::ranges::find_if(g_dma_allocs, [&](auto &a) { return a.mem_hdl == params->hMemory; }); alloc != g_dma_allocs.end()) {
16:39dwlsalmeida[d]: 623 alloc->is_mapped = false;
16:39dwlsalmeida[d]: 624 if (is_address_valid(alloc->cpu_addr)) {
16:39dwlsalmeida[d]: 625 alloc->unmap_backup.resize(alloc->size);
16:39dwlsalmeida[d]: 626 std::memcpy(&*alloc->unmap_backup.begin(), alloc->cpu_addr, alloc->size);
16:39dwlsalmeida[d]: (gdb) p params
16:39dwlsalmeida[d]: $1 = (NVOS34_PARAMETERS *&) @0x7fffffff3700: 0x0
16:44dwlsalmeida[d]: FYI adding a `if (!params) break;` there seems to solve the issue
17:30avhe[d]: hmm strange
17:30avhe[d]: anyway when i tried it on gstreamer i didn't get a crash, but it hanged
17:31avhe[d]: probably because gstreamer uses signals that i don't forward
19:54dwlsalmeida[d]: more interestingly, nothing is captured when using vulkan video
19:55dwlsalmeida[d]: i.e.: `ffmpeg -init_hw_device vulkan -hwaccel_output_format vulkan -hwaccel vulkan -i <file> -vsync passthrough -vf hwdownload,format=nv12,format=pix_fmts=yuv420p -f rawvideo <file>`
19:56dwlsalmeida[d]: strange indeed lol
19:57dwlsalmeida[d]: anyways
20:44avhe[d]: it's probably that the nvdec channel is created through another sequence of ioctls
20:45avhe[d]: cuvid uses the nvidia-push library internally, which is convenient since its source is public in the open-gpu-kernel-modules repo
20:46avhe[d]: but cuda creates compute/dma channels differently
23:21mhenning[d]: huh. The Volta whitepaper includes the footnote "The per-thread program counter (PC) that forms part of the improved SIMT model typically requires two of the register slots per thread."
23:21mhenning[d]: so I guess those registers being inaccessible are from the brogram counters and not from uniform registers