06:58 imanho: LD.E.CG.128 R12, [R20+0x10] (aren't registers 32 bit? What is 128 doing here?)
07:01 imanho: is this supposed to be "aligned" so that data actually goes to R12,R13,R14,R15,R16,R17,R18,R19 ?
07:01 HdkR: imanho: Loads sequentially 128bits
07:01 HdkR: So R12, R13, R14, R15
07:02 imanho: oh got it . so it is 32bit
07:02 imanho: but then about addresses, I was thinking that addresses are 64bit how does it specify it as [R20+0x10] if R20 is merely 32bits?
07:02 HdkR: Sequential again, R20 and R21
07:03 imanho: ohhh... thanks! :HdkR
09:59 imanho: Graphics Exception: ESR 0x504648=0x9 0x504650=0x20 0x504644=0xd3eff2 0x50464c=0x17f (any leads on how I should interpret this?)