11:10karolherbst: pmoreau: I think the biggest issue we have right now is that the arch specific things are spread all over the place. But afaik we don't have half regs on nvc0+ and I don't think we ever emit such
12:42pmoreau: karolherbst: When preparing the second series, I will be reworking my existing patches to take place during the legalisation passes rather than changing the NIR frontend to adapt to different targets, especially regarding those half registers.
12:42karolherbst: yeah.. not sure
12:42karolherbst: I'd prefer to move everything into nir tbh :D
12:43karolherbst: all of those things are easier in nir
12:44karolherbst: this entire half register concept is broken anyway...
12:46pmoreau: I’d also prefer moving everything into NIR, but that’s a much larger change than what I was thinking for that second series. :-D
12:46karolherbst: well.. not everything, but yeah..
12:46karolherbst: there are still regressions and everything
12:47karolherbst: getting rid of the TGSI stuff would be the first step anyway
12:48pmoreau: Well, we do not want to get rid of TGSI before we have NIR fully working, otherwise people might not be super happy about it.
12:49karolherbst: but we already use it for turing :D
12:49karolherbst: I am fairly confident it works, but I think it might make sense to deal with regressions and move one gen at a time over
12:49karolherbst: until we are done or so
12:50pmoreau: Oh, do we? I think I had missed that.
12:50karolherbst: yeah.. volta as well
12:50karolherbst: Ben and I were to lazy to write those assembly functions
12:50karolherbst: so we just use Nir
12:50pmoreau: I guess mostly looking at Tesla for Nouveau, I have missed what happened for those new fancy architectures! :-D
12:52pmoreau: Once I get basic mostly working (not sure if I want to get images working first or leave them for later), I would not be opposed to moving the compute stuff to be a lot more NIR based.
12:54karolherbst: but working on nir regressions with nv50 would be helpful
13:43pmoreau: Is there a way we could do the register allocation with Nir? That could be something I would look into relatively soon, as some of the remaining issues for basics are shortcomings in the current register allocation code.
14:07karolherbst: pmoreau: no
14:07karolherbst: we have a lib for it
14:07karolherbst: it's a completely different approach, but it might allow us to get rid of our own flawed RA
14:08karolherbst: there is just one issue
14:08karolherbst: we do more than just RA in RA
14:08karolherbst: we have reg zer0 handling there
14:08karolherbst: tex stuff
14:08karolherbst: and potentially more things
14:08karolherbst: we also have some hacks for better reg placement to deal with limm mad forms and stuff
14:17glennk: how is nir's support for mixed precision fp32/fp16?
14:19glennk: in particular is there anything for propagating required precision from fbos and textures through shaders?
14:20karolherbst: glennk: it's all explicit
14:20glennk: ok, so mostly pointless then
14:20karolherbst: what do you mean?
14:21glennk: a pretty fair first order approximation of number of shaders using precision modifiers out in the wild: 0 :-)
14:22karolherbst: well it's more common with gles
14:22glennk: even there its a bit sketchy
14:23karolherbst: yeah well
14:24karolherbst: we have to do what the shader is telling us :D
14:24glennk: and things like gnome-shell just set precision highp float
14:24karolherbst: there are precision annotations, but yeah...
14:25karolherbst: anyway, we get all the info the shader contains
14:28glennk: well, the idea is you also need to look at the types of the bound fbos and textures, and compile variants for 8 bit vs 32 bit
14:30karolherbst: do we have to support that with nv30?
14:30karolherbst: but the output in nir is typed
14:30karolherbst: I just think it's probably always a vec4?
14:30karolherbst: not sure
14:30karolherbst: maybe others know
14:30karolherbst: or have similiar problems
14:32glennk: for fragment shaders on nv3x fp16 is ~twice the rate of fp32
14:32karolherbst: anyway... nir in nv30 was just a fun project idea, because atm we don't do any optimizations :D one other path would be glsl -> nir -> tgsi
14:33karolherbst: glennk: mhh, but we have to do it from within shaders?
14:33glennk: nv4x its a little less pronounced but still significant, also nv4x has some odder fixed point formats which may or may not be faster
14:33karolherbst: okay, but with TGSI we also output fp32, no?
14:33karolherbst: what we could do is shader variants and just compile fp16 versions ondemand
14:34glennk: the current backend always outputs fp32, except for some odd ops like branches which cargo cult fp16
14:34karolherbst: "decl_var shader_out INTERP_MODE_SMOOTH vec4 out_1 (VARYING_SLOT_COL0.xyzw, 1, 0)" is what we get normally
14:34karolherbst: but I suspect it could also be a fp16 vec4
14:34karolherbst: ehhh wauit
14:34karolherbst: that's vp
14:34karolherbst: "decl_var shader_out INTERP_MODE_NONE vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0)"
14:35glennk: how do you think one determines if fp16 or fp32 is required for correctly computed output?
14:35karolherbst: st/mesa does?
14:37glennk: i think you are mixing up explicit precision attributes, which i just stated are basically of no practical use, with determining what accuracy the computations require to get correct output
14:37karolherbst: I understood what you mean
14:37karolherbst: soo.. we get the glsl ir and we convert it into nir within st/mesa
14:38karolherbst: but st/mesa could also force the output to be a fp16
14:38karolherbst: or we do
14:38karolherbst: we get the nir handed in and can change whatever we want
14:38glennk: i don't think you quite see the point i am trying to make
14:41karolherbst: I think I do. So you mean if the fbo is of a fp16 format, we could also return fp16 values from withing the fp or not?
14:41karolherbst: I honestly don't see the issue, as we could just do that
14:41glennk: i seem to have lost you somewhere along the way
14:41karolherbst: ohh you also mean for inputed data?
14:43glennk: so for an example if you have something with no precision qualifiers ie effectively vec4 etc in shaders are floats, then to compute an exactly equivalent result using at least one operation reduced to fp16
14:44glennk: in order to determine that you have to look at the range and precision of the actual inputs and outputs the shader gets at runtime
14:44karolherbst: so you mena basic fp32->fp16 opts
14:45karolherbst: so if we know, the inputs are actually fp16, there is no point doing fp32, because it's slower
14:45karolherbst: in case we can make sure, that the fp16 ops would result into the same end result
14:46glennk: that would be a wildly incorrect assumption
14:46glennk: you have to propagate the errors through the shader for each op
14:47glennk: its like value range propagation, but including precision
14:47glennk: and you pre-fill the input and output types and ranges
14:48glennk: i think in practice just flipping between all inputs/outputs fp16 or fp32 would be enough to be useful most of the time
14:49karolherbst: so changing intputs/outputs should be quite easy with shader variants
14:49karolherbst: we just need to look at the full pipeline
14:49karolherbst: which is just vp/fp for nv30 anyway
14:50karolherbst: but I think there are attempts at value range optimizations in nir
14:50glennk: well, can ignore vp on nv30 since its all fp32
14:50karolherbst: like fp32 fp32 or just 32 bit?
14:50karolherbst: could load 32 bit and split the value
14:51glennk: see nvfx_shader.h, its not a complicated ISA
14:52karolherbst: yeah, but I didn't mean it from an ISA perspective
14:53glennk: are you talking about the interpolants between vs->fs?
14:53karolherbst: yes, and generic inputs to vs
14:54karolherbst: like can we pass 2xfp16 values in and between the stages
14:54karolherbst: within a 32bit varying
14:54karolherbst: or input/outpuits
14:54glennk: i don't think so?
14:54karolherbst: why not?
14:54karolherbst: does the hw manipulate the data?
14:55glennk: i think the hardware always interpolates fp32
14:55karolherbst: interpolated inputs and stuff.. if those have to be fp32, okay, sure
14:55karolherbst: but I also meant generic
14:55karolherbst: there are generic input/outputs and fp inputs not being interpolated, no?
14:55karolherbst: at least on later gens we have that
14:55glennk: those are interpolated too, unless flat shading
14:55glennk: or do you mean uniforms/constants?
14:56karolherbst: well uniforms are just passed in
14:56karolherbst: so those should be fine
14:56karolherbst: passing values between stages is more interesting
14:57karolherbst: okay, but we could delcare a "flat" fp32 output/input in vs/fs and split it to two fp16 values?
14:57karolherbst: the annoying bit is just that those things can usually be overwritten and shit :/
14:58glennk: its pretty rare for flats to be used
14:58glennk: typically everything is interpolated
14:58karolherbst: but not all data passed in gets interpolated
14:58karolherbst: there are generic values
14:59glennk: there's nothing special about those
14:59glennk: they get interpolated too according to flat/smooth shade state
14:59glennk: and perspective/linear
15:00karolherbst: but not all
15:00karolherbst: we do have 32 generic varyings
15:00karolherbst: and they do get used
15:01karolherbst: I am just wondering if that stuff is supported on nv30
15:01karolherbst: we have "VARYING_SLOT_VAR0_16BIT" stuff
15:01karolherbst: "32 16-bit vec4 slots packed in 16 32-bit vec4 slots for GLES/mediump."
15:02glennk: you are talking about nvc0 now right?
15:02karolherbst: core stuff
15:02karolherbst: looking at struct gl_varying_slot
15:03karolherbst: so if an application does use a generic varying to push data from a vp to a fp, nv30 does or does not have hw support for it? and if we pass 2xfp16 inside a fp32 slot, do we get the raw data or does the hw anything weird to them?
15:04glennk: i think use of those are gated behind CAP bits
15:04karolherbst: does't seem to be
15:05glennk: PIPE_CAP_GLSL_FEATURE_LEVEL if nothing else
15:05karolherbst: maybe it's just gated on the glsl level
15:05karolherbst: yeah.. let's see
15:05glennk: this is GL 2.1 hardware
15:05karolherbst: generic varying seems to be a gl 2.0 feature
15:06glennk: yes but fp16 isn't
15:06karolherbst: it's raw data
15:06karolherbst: or not
15:06karolherbst: so if you pack two fp16 values within a fp32 generic varying, is the hw doing anything funny or just passing the raw data through?
15:07karolherbst: nir does have support for this packing as it seems
15:07karolherbst: so hence me wondering
15:07karolherbst: or well.. st/mesa
15:09glennk: where would this packing come from?
15:09glennk: are you manually packing bits into a vec2 in GLSL?
15:09karolherbst: we have nir_lower_mediump.c
15:09glennk: again, where is this packing coming from?
15:10glennk: there are no such functions in the GLSL versions that nv4x can support
15:10karolherbst: what do you mean with that? you have fp16 values and don't want to do a fp16 to fp32 conversion just to pass it into the fp
15:11karolherbst: forget about GLSL for a moment
15:11karolherbst: this is all mesa internal
15:11karolherbst: so we find opportunities to use fp16 inside a vp
15:11karolherbst: for whatever reason
15:11karolherbst: be it a texture being actually fp16 or anything else
15:11glennk: forget about vertex programs here
15:12karolherbst: and have a fp16 value we want to pass into the fragment program
15:12glennk: nv3x/nv4x its all 32 bit floats always
15:12glennk: i am talking about texture sampling and framebuffer operations
15:13glennk: vp/fp passing is a bit of a side track - on other hardware its probably more relevant
15:13karolherbst: then if you talk about texture sampling and fb ops, how is that relevant to the shader?
15:14glennk: think about it for more than 2 seconds and you'll figure it out :-)
15:14glennk: maybe if i paste you an actual shader it'll be clearer?
15:24glennk: random gnome-shell shader, picked as its a bit of a dog on the old 6600 i'm testing with
15:25karolherbst: okay.. sure, but what fp16 ops do we actually support in nv30? just texturing or also alu?
15:25glennk: so on this isa its a bit weird
15:26glennk: registers are fp32, but you can set a bit on ops to write them as fp16, its still "stored" as fp32 but uses half the register port bandwidth
15:26karolherbst: okay sure
15:26glennk: and then there's a separate bit for precision of op inputs and the op itself
15:26karolherbst: so we more or less have a full fp16 alu, just use fp32 regs
15:26karolherbst: can we operate on hi/lo bits?
15:27glennk: no, i'm not even sure if fp16 and fp32 are even aliased or separate register files
15:27glennk: but conversions are "free"
15:27karolherbst: shouldn't be complicated in hw
15:28karolherbst: glennk: but then I don't see the problem once a texture is marked as a "fp16" thing
15:30glennk: the problem is there is no propagation algorithm implemented
15:31karolherbst: oh mhh... well
15:31glennk: and computing the precision bars for each op is a bit of a research grade issue
15:31karolherbst: right.. as shaders are still fp32
15:32karolherbst: so if you multiply two fp16 values you still expect fp32 precision
15:32glennk: final output of the shader equivalent to as if it was all fp32
15:32glennk: to be a bit more precise about the wording :-)
15:33karolherbst: the question is.. are there fp16 ops which don't loose precision?
15:33karolherbst: compared to doing it in fp32
15:33karolherbst: but in the end it only matters what glsl expects
15:33karolherbst: and that's almost nothing
15:33karolherbst: we could probably just turn the whole thing to fp16 and nobody would notice
15:34glennk: say you are mixing colors coming from two 8 bit textures
15:34karolherbst: ehh.. but that's int
15:34glennk: and you'd be wrong to assume that because then things like texture coordinates come in and need fp32
15:34karolherbst: int is a totally completely different story
15:34glennk: and the award for missing the point goes to... :-p
15:35karolherbst: ohh coordinates
15:35glennk: by 8 bit i mean snorm so 0 - 1.0 range just to clarify
15:36karolherbst: I guess nv30 doesn't support int textures anyway...
15:37karolherbst: glennk: what we could do is to define "safe" usages and just propagate it this way
15:37karolherbst: we do have search helpers
15:37glennk: how do you know what is safe and not?
15:38karolherbst: it's glsl, not CL
15:38karolherbst: I don't think that for fp16 outputs it really matters
15:39karolherbst: if an op requries fp32, because it's... a hard fp32 then yes, it stays fp16
15:39karolherbst: but why would it matter otherwise?
15:39karolherbst: comparing to constants would be annoying
15:39karolherbst: but those are hard fp32 ops then
15:39karolherbst: you could e.g. back propagate
15:39karolherbst: start with the output
15:40glennk: i did say value range propagation with precision added previously?
15:40karolherbst: yeah, but I don't think we have to go that far
15:41karolherbst: a slight change in result is okay by glsl
15:41glennk: define slight change?
15:42glennk: do you mean like some minor subtexel shifting, or a framebuffer value being off by 1/255?
15:42karolherbst: if you add an opt and the result is different, but not buggy, it's fine
15:43karolherbst: heck.. even the same op in vp and fp is allowed to have different values
15:43karolherbst: unless you specify in the shader they absolutely should have the same
15:44karolherbst: unless it doesn't look "wrong" it's fine to optimize
15:44glennk: how do you intend to algorithmically determine "wrongness" ?
15:44karolherbst: we don't and don't have to
15:45karolherbst: so what happens is, that some CI systems just ping when a trace reports different results
15:45karolherbst: and somebody looks at it and either acks it or not
15:45karolherbst: that's how it's done
15:45karolherbst: again.. it's not CL
15:45karolherbst: if the result changes due to opts nobody cares unless it looks wrong
15:46glennk: are you still thinking in terms of a global shader fp32/fp16 switch?
15:46karolherbst: I never did
15:46glennk: then i'm not sure how you make the decision for each op in the shader
15:47karolherbst: you start with results and go up the sources until you hit something where you don't want to drop from fp32 to fp16
15:47karolherbst: don't have to do the full value range thing for this
15:48karolherbst: if you store a fp32 add as fp16 anyway, you can just make it a fp16 op, and so on
15:48karolherbst: comparing with fp32 constants might be a point you don't want to do it or something
15:48karolherbst: and stop propagating
15:49karolherbst: or if the result is used also for fp32 ops
15:55glennk: last i checked nir output wasn't great for vector ISAs, has that changed recently?
15:56karolherbst: why shouldn't it be greate for vector ISAs?
15:56glennk: tgsi and nv3x/4x are pretty close to 1:1
15:56karolherbst: all ops can be used vectorized
15:57glennk: one comparison point is nir on r600g where its pretty sub par compared to tgsi
15:57karolherbst: mhh, interesting
15:58karolherbst: I wouldn't see why it's a problem there though. you can jsut have vec4 input/outputs if you want to
15:58karolherbst: it only gets annoying once you start doing packing
15:58glennk: well r600g is vliw really
15:58glennk: nv3x is really vector
15:58karolherbst: yeah.. vliw...
15:58glennk: as in only vector, no scalar ops
15:59karolherbst: no problem
15:59glennk: also you get 512 instructions for vertex shaders
15:59karolherbst: then you have vec4 values
15:59karolherbst: okay.. instruction limit is kind of an issue
15:59glennk: fp on nv4x is a bit more generous, 64k i think?
15:59karolherbst: but the idea of using nir was to get optimizations, so you can potentially execute larger shaders
16:00glennk: its kinda pointless if it spits out scalar code
16:00karolherbst: but anholt works on using nir between glsl ir and tgsi
16:00karolherbst: why would it?
16:00karolherbst: nir isn't scalar or vectorized, it's both
16:00karolherbst: and you choose how it should behave
16:00karolherbst: if you want to keep it vectored, fine
16:00karolherbst: you just keep it vectored
16:01karolherbst: there are even passes to merge vectore ops if not all channels are always used and such
16:01karolherbst: we also have nir_opt_vectorize
16:01glennk: but as far as i can tell it can still spit out scalar and vec2/3 etc ops that the backend needs to handle?
16:02karolherbst: well.. worst case the unused channels contain garbage, no?
16:02karolherbst: but yeah.. after optimizations there can be dead channels
16:03glennk: worst case the backend is untested complicated garbage
16:03karolherbst: could be
16:03karolherbst: I just said it would be a fun project :p
16:03karolherbst: not that we should definitly do it
16:03glennk: right, i'm just sort of weighing pros and cons
16:04glennk: tgsi translation is lightweight, nir is not
16:04karolherbst: the main idea would be to get more optimized shaders to make things like gnome-shell less heavy on the hw
16:04glennk: for this particular architecture
16:04karolherbst: we can cache shaders
16:04karolherbst: but yeah
16:04karolherbst: but so is every optimizing compiler
16:05glennk: may be a better option to use nir_to_tgsi
16:05karolherbst: might be
16:05karolherbst: glennk: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8044
16:05glennk: the optimizations don't seem to be helping r600g nir much compared to what sb was doing
16:05glennk: as a comparison point
16:06karolherbst: okay sure, but r600 always had some sort of optimizations happening, no?
16:06karolherbst: and nv30 is just... nothing, or not?
16:07glennk: well, if you disable sb you get something similar to nv30
16:07karolherbst: sure, but we don't have anything like sb, do we?
16:07karolherbst: we could also start adding our own IR to nv30 and do optimizations and everything
16:07karolherbst: would be another option
16:08karolherbst: don't see the point of adding yet another IR
16:08glennk: me neither
16:09karolherbst: I think that gtn and ntt this should be the cheapest way for us, but this MR is so huge and impacts so much, I doubt it will land any time soon
16:09karolherbst: and for nv50 and nvc0 it's probably easier to just drop TGSI then
16:09karolherbst: instead of having to rely on gtn+ntt
16:09karolherbst: as we already support nir there
16:10glennk: also if it increases register usage that basically means all the desktop composition shaders stop compiling
16:10karolherbst: yeah... that's an annoying scheduling issue
16:10glennk: so either nv30 would have to gain a register allocator
16:10karolherbst: glennk: just use src/util/register_allocate.h :p
16:11karolherbst: some even use it directly on the nir and turn ssa values into registers
16:11karolherbst: I think
16:11karolherbst: the question is just.. can we spill on nv30
16:11glennk: hah, no
16:12karolherbst: but yeah..
16:12karolherbst: scheduling is an issue
16:12karolherbst: not sure if there are nir based schedulers already to reduce register usage
16:12glennk: less of an issue on nv30
16:12karolherbst: I meant instruction scheduling
16:12glennk: yeah, not so much of an issue on nv30 hardware
16:13glennk: you mean program dependence graph in the compiler
16:13karolherbst: well.. if that's what is called? I mean the thing where you reorder instruction so your register usage goes down or so
16:13karolherbst: or stalls go down
16:13karolherbst: or something
16:13glennk: emitting instructions in an order to minimize overlapping live ranges
16:13karolherbst: I think there are experiments for that
16:13karolherbst: let's see
16:15glennk: sb's gcm pass is pretty powerful there
16:16karolherbst: yeah..I bet
16:16karolherbst: it was all pre nir afaik
16:16glennk: yeah its a binary r600 ISA to binary optimizer
16:17karolherbst: it operates on the binary directly?
16:17glennk: yeah, thats why it can't handle too many temps
16:17karolherbst: oh wow
16:17glennk: the ISA can only encode so many
16:19glennk: anyway, for nv30/nv40 fragment shaders, to improve performance relative to whats currently in nouveau, 1. reduce number of registers used, its similar to how later architectures get more warps in flight
16:20glennk: and 2. reduce precision to fp16 when possible
16:21glennk: most shaders running on this old hardware will be short enough that there's not a lot of ops for an optimizer to bite into
16:54karolherbst: mupuf, RSpliet, pmoreau: wrote something imporant for a change: https://lists.freedesktop.org/archives/nouveau/2021-August/039142.html would be cool if you'd comment on that. Ben and Lyude are already aware of this. And I hope I didn't forget to ping somebody else
17:22karolherbst: pmoreau: btw.. seems like that forks taking forever is a huge issue... maybe I can figure out how to solve it, but...
17:22karolherbst: ohh.. I have an idea..
17:23karolherbst: well.. not really though
17:23pmoreau: karolherbst: Re register allocation in Nir: ah true we have all those hacks. Mmh, I’ll leave that be for now and still have plenty of other stuff to do.
17:23karolherbst: pmoreau: you came to the same conclusion as I dif :)
17:24pmoreau: Re your email: I will try to reply to it today (or before end of week at the latest), but sounds good to me! Does Ben prefer to Ack/Nack things on the ML?
17:24karolherbst: no clue
17:24karolherbst: but we can't submit to drm on gitlab
17:25karolherbst: not yet at least
17:26pmoreau: Re the fork: Not too surprised in a way, given how big the Linux kernel is with all its history. Maybe trying to use the submodule one could work better for that? But it would have other issues as well.
17:26karolherbst: pmoreau: well.. that process takes like 5 seconds on github
17:26karolherbst: on github all forks are within the same repository
17:26karolherbst: so it's really just adding branches on the remote
17:27karolherbst: gitlab does a real fork
17:27karolherbst: but I am not sure that it still has to take so long...
19:40glennk: huh, what sets up the vertex attribute mapping VS -> FS in nv30 when its not taking the nv30_draw_vbo path?
19:47karolherbst: glennk: do we even have any other draw path?
19:48karolherbst: guess the only other path where it would matter would be a 3d blitter
19:49karolherbst: glennk: that's called from within nv30_draw_vbo
19:49glennk: conditionally called
19:50glennk: for the cases its not called, there appears to be nothing setting up attribute mapping
21:55RSpliet: karolherbst: ack. I have no thoughts yet, I'll let it simmer for a bit and see if I have anything constructive to say/add
22:02RSpliet: I think the goal is good. I think using a platform that supports pull requests could help keep track of smaller patches easier, so I approve of that too. CI is good, but tricky on a tight budget. There's a lot of things I just agree with.
22:03karolherbst: yeah well.. I wouldn't have written it if people wouldn't agree :p
22:04RSpliet: Maybe I wouldn't push for another layer of indirection. I feel like what makes it into *the new drm/nouveau tree* should be good to funnel upwards sort-of-blindly. Perhaps Ben, Dave or someone should invest in training Lyude and you to do good reviews to a point that they trust your judgement
22:05Lyude: RSpliet: yeah I had mentioned something about ben not scaling
22:06Lyude: and i'm happy to do reviews for nouveau, especially since my plate is finally clearing up (albeit slowly)
22:09RSpliet: Lyude: Glad to hear you're anticipating a bit more bandwidth!
22:09Lyude: yeah :), I am excited to get back to working on stuff like nouveau a lot more
22:10RSpliet: The #1 nouveau-killer is lack of peoplepower, so I'm excited about that too :-D
22:14karolherbst: RSpliet: I have drm-misc commit rights ¯\_(ツ)_/¯
22:15karolherbst: and I already used those powers!
22:15karolherbst: danvet already agreed to the idea anyway
22:16karolherbst: more or less
22:16karolherbst: I talked with skeggsb about it and Ben requested to be able to nack the whole thing or something
22:16karolherbst: that's pretty much the only reason I put it in there
22:17karolherbst: or at least "chance to nack"
22:17karolherbst: and I think this trust can only be built up by actually doing it
22:19karolherbst: I can also just push things without skeggsb knowing it, but I thought that might be too drastic and I never wanted to have this "we are doing it this way, end of story" situation to begin with. If skeggsb wants to have a chance to nack stuff, then so be it
22:19karolherbst: worst case I post the series two weeks earlier, hear nothing from skeggsb and push anyway or something.. dunno
22:19karolherbst: but at least I want to have this conversation
22:20karolherbst: and it would be best to have it on the thread :p
22:27mupuf: karolherbst: with gitlab, skeggsb could "approve" the series, to indicate he checked it out :)
22:28mupuf: quickly reading your email, I am pretty pleased to see where things are going
22:28mupuf: and I would like to congratulate Ben for trusting you guys
22:28karolherbst: mupuf: for example
22:29karolherbst: but the idea isn't that skeggsb checks every MR
22:29karolherbst: just the final inclusion thing
22:29karolherbst: because that would be kind of pointless if he would check out every MR anyway
22:29mupuf: karolherbst: then just pinging him before merging is easy too
22:29karolherbst: yeah.. something
22:29mupuf: I'll write a proper answer, but I'm all for Gitlab and CI there
22:30mupuf: as for the "how long does it take to fork nouveau" thing, not sure I really care... How bad is it anyway?
22:30karolherbst: maybe skeggsb is happy with me "announcing to merge into drm-misc-next" 1 or 2 weeks before
22:30karolherbst: mupuf: 10-15 minutes
22:30mupuf: karolherbst: meh then. It's something for gitlab to improve. If fdo is fine with the disk usage, I'm fine with it!
22:30karolherbst: it's not _bad_ but bad enough that some might loose interested doing an MR
22:31karolherbst: but they can always send out emails soo... ¯\_(ツ)_/¯
22:31mupuf: and I guess people will just have their Linux tree anyway
22:31karolherbst: mupuf: sure, but then they can't do MRs against nouveau
22:31karolherbst: not talking about git operations
22:31karolherbst: I meant the fork on the UI
22:31mupuf: You sure?
22:32karolherbst: how can you do a MR on gitlab otherwise?
22:33mupuf: well, there is "change branch"
22:33mupuf: but indeed, it does not seem to be that flexible :s
22:33karolherbst: the UI is broken anyway
22:33mupuf: anyway, bed time!