00:05 karolherbst: fun... my laptop suspended... without me telling it to do so
21:17 karolherbst: imirkin: I bet you also have no clear idea on how that degree stuff works out?
21:17 imirkin: that's a fairly safe bet
21:17 imirkin: i looked into it at one point
21:18 imirkin: but i don't think i ever gained a full understanding
21:18 imirkin: and have since forgotten the things i learned.
21:18 imirkin: if you search for a demonstration that involves simplification, it should talk about that stuff
21:18 imirkin: i found some class materials online when i was looking
21:19 karolherbst: so.. fun thing: if I ignore the nospill flag _or_ just don't abort on the "no spill candidates left" message, RA is just doing fine and succeeds
21:19 karolherbst: of course.. without spilling anything
21:19 imirkin: yes
21:19 imirkin: the nospill thing is broken
21:19 imirkin: for merges/splits
21:19 imirkin: we mark the wrong thing
21:19 karolherbst: ahh
21:20 imirkin: or something
21:20 karolherbst: mhh
21:20 imirkin: that sounds very familiar
21:20 karolherbst: well, it's a merge value indeed
21:20 imirkin: broken is the wrong word
21:20 karolherbst: soo.. technically, "deg 60/60" means we have to spill a value
21:20 imirkin: maybe more like "imperfect"
21:21 karolherbst: weight is inf, because it's marked as no spill
21:21 karolherbst: which causes RA to just fail
21:21 imirkin: basically spilling the full-wide thing makes no sense
21:21 imirkin: you just want to spill its components
21:21 imirkin: but the way this interacts with everything kinda sucks
21:21 karolherbst: yeah... feels like it
21:22 imirkin: thing is, spill or no spill
21:22 imirkin: you still need 4 sequential registers
21:22 imirkin: the problem is that the merged value isn't always used immediately
21:22 karolherbst: well.. sure, but that can be handled on unspilling.. I just fear the code can't handle it
21:22 imirkin: i think that's the real problem.
21:23 imirkin: we should avoid having these merged values have lifetimes of more than 1 instruction
21:23 karolherbst: well.. in this case it's immediatly used
21:23 karolherbst: and never used after the next instruction
21:23 imirkin: then you're just fucked, right
21:23 imirkin: i mean, imagine you spilled it and unspilled it
21:23 imirkin: that'd be no better
21:23 imirkin: right?
21:23 karolherbst: right... but the problem isn't spilling here, right?
21:23 karolherbst: RA marks that value to be spilled, allthough it really doesn't have to
21:24 karolherbst: and that's where that degree stuff is coming in
21:24 imirkin: yeah, dunno, didn't investigate that closely yet
21:24 karolherbst: if degree >= degreeLimit -> add to hi list
21:25 karolherbst: everything in the hi list gets spilled.. unless the value has a weight of inf
21:25 karolherbst: in that case, RA bails
21:25 karolherbst: degreeLimit kind of is the "highest" register which can be used
21:25 karolherbst: degree kind of the "placed" register or something.. of course you can't place a quad reg at 60
21:26 karolherbst: but... the way how that degree value is calculate looks totally bogus to me
21:26 karolherbst: *calculated
21:26 karolherbst: it makes literally no sense
21:26 karolherbst: (that's where this reldegree table comes into play)
21:26 karolherbst: in GCRA::RIG_Node::addInterference
21:29 karolherbst: all those merge gets a suspicily high "degree" value. the other one has 40/60, which... also looks like it just works by accident
23:14 Lyude: [ 826.854346] Lyude:crc907d_ctx_finished:143: (ioread32(&notifier->status)) == 6f000001
23:16 Lyude: YES, I am not getting any crcs yet for reasons I need to investigate but I'm pretty certain I have the display controller writing CRCs somewhere
23:16 imirkin: yay!
23:17 Lyude: as that is the first time I've actually seen the GPU properly mark the crc notifier context as released, and there's no evo hang
23:18 Lyude: or if it isn't actually writing any crcs, it's at least setting things up correctly from what I can tell
23:18 Lyude: oh-yep I think I'm just misreading the frame count
23:35 Lyude: hm, it would seem I might also only have the rg and sf source working atm though
23:35 Lyude: must be pointing it at the wrong sor or something silly
23:38 karolherbst: uffffff
23:39 karolherbst: imirkin: I think I start to understand this relDegree thing...
23:39 imirkin: karolherbst: cool. try to write it down :)
23:39 imirkin: (like in the code comments)
23:39 karolherbst: well
23:39 karolherbst: I don't understand the theory behind it, mind ou
23:39 karolherbst: but I see what's going on
23:39 karolherbst: soooo
23:40 karolherbst: the degree value gets increased by 4 for each single reg live value interfering
23:40 karolherbst: which, if there are 20 live values, means it gets increased quite significantly
23:41 karolherbst: ehhh.. 16 in this case
23:41 karolherbst: if we consider the worst case
23:42 karolherbst: and each of that single reg values get assigned to a different vec4 slot, means, we actually would have to spill the original vec4 value
23:42 karolherbst: I just don't know if that was the intention behind it
23:45 karolherbst: but it would make sense.. kind of
23:45 karolherbst: it just isn't the smartest thing to do
23:46 karolherbst: imirkin: do you know if codegen was purly vec4 based in its RA at some point, or was it always intended to do a scalar allocation?
23:47 imirkin: always scalar afaik
23:47 imirkin: there were some thoughts about making it work for nv30
23:47 imirkin: (which is vec4)
23:47 imirkin: but it is meant for up-to-byte-level things
23:47 imirkin: at the very least, nv50 gpr's are treated as 16-bit things
23:47 imirkin: as far as colors/register numbering go
23:48 imirkin: to make mul's 16-bit args work
23:48 karolherbst: with 13 live values I get "44/60"... there is still an offset of 4 which I don't know where that comes from
23:48 karolherbst: uhm
23:48 karolherbst: 12
23:48 karolherbst: but at least that's how the code behaves
23:56 karolherbst: imirkin: https://github.com/karolherbst/mesa/commit/61fcf928df69484156cfef63a60d4eac953a96ed and hope nothing breaks?