09:14 meeku_: Morning all
09:15 meeku_: Regarding vsync, and I guess this question applies to all gpu's not really just nvidia ones, do we know if they continue to update the legacy vga registers throughout their operation ? IE: with LFB/GOP.. a proper native video mode set, would the i/o 3dah approach still work to detect vsync or do you have to use a device specific method ?
13:00 imirkin: meeku_: i think there's only one way to find out ... no one's been crazy enough to ask such a question
13:00 meeku_: lol i know, I will try this evening on all my machines using the classic wait vblank code and see if it works
13:00 imirkin: in theory it should all map to the same thing
13:01 imirkin: but tbh i don't know what the "legacy" way is
13:01 meeku_: my "hope" is that given the legacy support that once upon a time these sorts of basic things were wired to the VGA compatible regs/ports .. and they probably just got left there
13:02 meeku_: if not.. then I'll have to look at setting up either some sort of interrupt (device specific) or from the docs so-far it looks like it might be possible to use the hw sequencer to setup a wait event for vblank and just query that
13:06 meeku_: the legacy way would be reading from port 03dah and testing bit 3
13:06 imirkin: and then what?
13:06 imirkin: rinse, lather, repeat?
13:06 meeku_: yep
13:07 meeku_: so render to regular memory buffer
13:07 imirkin: always repeat...
13:07 meeku_: wait vblank
13:07 meeku_: copy to lfb
13:07 meeku_: now that the lfb is running fast
13:08 meeku_: so the sort of code I used to use back in the DOS/vga days was something like:
13:08 meeku_: mov dx,03dah
13:08 meeku_: vbl1:
13:08 meeku_: in al,dx
13:08 meeku_: test al,8
13:08 meeku_: jz short vbl1
13:08 meeku_: vbl2:
13:08 meeku_: in al, dx
13:08 meeku_: test al,8
13:08 meeku_: jnz short vbl2
13:08 imirkin: vblank, of course, is a head-specific concept
13:09 meeku_: yes, my thinking is that if it is replicated to the legacy vga ports
13:09 meeku_: it probably(hopefully?) corresponds to the display t hat the LFB is on
13:09 meeku_: which would be the default head
13:09 imirkin: you might get something, but it might not be what you want
13:09 meeku_: possibly.. this is all really speculative
13:09 imirkin: also does port io work in protected mode?
13:09 meeku_: yep
13:09 imirkin: (does the GOP run in protected mode?)
13:10 meeku_: it's in 64bit long mode
13:14 imirkin: mmenzyns: if you're playing with fermi reclock, i hope you're aware that skeggsb has a branch dedicated to the topic, right?
13:15 karolherbst: imirkin: skeggsb was only working on memory reclocking stuff
13:16 karolherbst: when I was asking him he told me he didn't look into any of the engine reclocking bits
13:16 imirkin: oh ok
13:17 mmenzyns: I should have said that explicitly it's only core stuff
13:18 imirkin: it was clear you were doing stuff with engine reclock
13:18 imirkin: i didn't realize that ben hadn't touched that stuff already
13:18 imirkin: also, note that gf119 has a lot of kepler-isms in it
13:52 tmonjalo: Bonjour Nouveau !
13:53 tmonjalo: I'm a french developer going to join Nvidia
13:53 tmonjalo: I am looking for some contacts to have a status about Nvidia relationship and phone discussion
14:04 karolherbst: tmonjalo: did you met John Hubbard at nvidia?
14:10 imirkin_: tmonjalo: afaik that's not a nouveau thing, but a RH thing with Ben
14:17 RSpliet: tmonjalo: congratulations, I'm sure you've landed quite an interesting job. The (limited) developers here are always happy to engage with NVIDIA openly. The most senior nouveau dev is Ben indeed, and RH employs a few others working full-time on nouveau.
14:19 RSpliet: Publicly NVIDIAs engagement has been limited. as I'm sure has been the result of internal "political" procedures. I am under the impression more direct lines exist between NVIDIA and Red Hat, but being on the outside (and at the moment, not actively working on nouveau) I am unable to confirm.
14:24 tmonjalo: I did not contact anybody yet
14:24 tmonjalo: And I don't know really this project (I'm working on networking drivers)
14:24 tmonjalo: So you say that Nvidia hired some Nouveau engineers?
14:24 tmonjalo: Or RedHat hired some?
14:25 RSpliet: Red Hat hired some
14:26 karolherbst: tmonjalo: ohh, so you will work on network stuff at nvidia?
14:26 RSpliet: There used to be one or two NVIDIA employees on nouveau at the time of Googles Pixel C, but they left the project
14:26 karolherbst: tmonjalo: anyway, if you are interested, you can contact John, he is involved in most of the discussions
14:26 karolherbst: or well, the nouveau related ones
14:27 tmonjalo: I am in Mellanox, maintaining DPDK
14:27 tmonjalo: and as you may know Mellanox is joining Nvidia.
14:27 karolherbst: yeah, that's what I thought
14:27 tmonjalo: As an Open Source person, if I can help somewhere...
14:27 karolherbst: complain at your manager, that nvidia should do more open source :p
14:27 karolherbst: management is the biggest issue
14:28 tmonjalo: That's what I'm doing
14:28 tmonjalo: I said to the management that I will talk with you Nouveau
14:28 tmonjalo: So let's talk :)
14:28 RSpliet: Find clever ways of skewing return-on-investment for nouveau to make it sound more attractive? :-P
14:29 tmonjalo: Please what are the full names / email of the contacts?
14:30 karolherbst: tmonjalo: jons is jhubbard@nvidia.com . he is taking care of publishing documentation: https://github.com/NVIDIA/open-gpu-doc/commits/master
14:30 karolherbst: so I don't feel bad sharing his email, as it's already public anyway :p
14:31 tmonjalo: John is contributing to Nouveau?
14:31 karolherbst: not directly
14:31 tmonjalo: Who is Ben?
14:31 karolherbst: Ben is the maintainer of the nouveau kernel driver
14:31 tmonjalo: email please?
14:32 tmonjalo: Ben Skeggs <bskeggs@redhat.com>
14:32 tmonjalo: from MAINTAINERS, OK
14:33 karolherbst: tmonjalo: I think normally it's fine to ask about stuff on the mailing list, as you get a bigger audience and higher chance of responses
14:33 tmonjalo: OK
14:33 karolherbst: poking specific people is usually not the prefered way of an upstream community to be enganged
14:33 tmonjalo: I know
14:33 tmonjalo: I'm just looking for some unofficial opinions
14:33 karolherbst: yeah, then the mailing list is probably the best place
14:33 karolherbst: or IRC :)
14:34 tmonjalo: I thought some developers are french?
14:34 karolherbst: Ben and me are kind of in this weird NDA situation where we can't really talk about everything we are discussing with nvidia, which is super sad and annoying and painful and not how it should be
14:34 karolherbst: tmonjalo: yes
14:35 karolherbst: pmoreau and mupuf
14:35 karolherbst: there were more in the past I think?
14:35 tmonjalo: Ah OK
14:35 tmonjalo: Is it public who is under NDA?
14:35 RSpliet: tmonjalo: also think of what you want to achieve with opening these channels. Just saying you're interested is very kind of you and appreciated, but not particularly productive. Please think about whether you can bring something concrete or whether you with to request something concrete in order to facilitate you contributing (whether it's info, code, or...)
14:36 karolherbst: tmonjalo: everybody working for redhat and nvidia is under the RH-Nvidia-NDA :p
14:37 tmonjalo: OK good to know
14:38 tmonjalo: RSpliet: My first concern is to understand to Nvidia policy/concerns regarding Open Source, because as a maintainer, I want to avoid any issue in future.
14:38 karolherbst: maintainer of what?
14:38 tmonjalo: dpdk.org
14:40 RSpliet: tmonjalo: I think that's best discussed with/through your future NVIDIA overlords, as they are the one constraining you. John Hubbard is a good contact to have I reckon
14:40 tmonjalo: I've read that the GPU doc being published is far from complete. Is it right?
14:40 RSpliet: Correct
14:40 tmonjalo: Is there any promise to complete it?
14:41 RSpliet: No
14:41 RSpliet: https://github.com/kfractal <- might be another good person for you to talk to
14:42 tmonjalo: OK thanks, I got a lot of infos already
14:43 RSpliet: For example: NVIDIAs contributions on the area of DVFS and power management have been notoriously sparse. Their initial investment in nouveau has been for Tegra, which is a lot simpler on these fronts.
14:45 tmonjalo: OK
14:45 tmonjalo: I stay a bit in this channel, in case you have more infos. Thanks
14:50 chf: Hi, is any of the developers interested in hardware donations? I've got at least 15 (mostly older) unused Nvidia cards, and I'm willing to send those for free, as long as postage isn't too expensive.
14:51 RSpliet: chf: what do you consider "older"?
14:54 chf: NV5, 10, 11, 17, 20, 34, 44A (AGP); 42GL, 92, 96, 98 (PCIe), RSpliet
15:01 RSpliet: That's an impressive collection, tempting to try and take some of them off your hands, but... I've been on nouveau-sabbatical recently.
15:02 RSpliet: Some people here mentioned a desire to get some of those NV3x and NV4x devices up and running to fix some long standing issues.
15:03 RSpliet: and there used to be someone here working on building an NV5 emulator I think, as part of a bigger emulation project. She's not here at the moment... wonder if she's interested
15:05 chf: Most of them are attracting dust since a few years. Currently in use are 3 PCIe cards, the NV96 and NV98 from the list above (I can switch to the 92 or 42), and a GF119.
15:06 chf: I've got 3 NV5: 1 x Vanta, 2 x Riva TNT2, the latter differ in RAM size and ROM version.
15:09 chf: 2 x NV34: 10de:0322 GeForce FX 5200 128M, quite common, I think.
15:09 chf: The 4x:
15:10 chf: 10de:0221 GeForce 6200 256M DDR2
15:11 chf: 10de:00cd:10de:029b NV42GL Quadro FX 3450 256M GDDR3
15:14 RSpliet: chf: perhaps it might be good to pop this info onto the mailinglist. I suspect some people might want to sleep over such a decision a night or two, and the ML is more useful for finding back such information than (potential) IRC chat logs :-)
15:49 chf: Done, RSpliet.
15:57 imirkin_: heh, GeForce 256. good times.
16:36 chf: My NV10 is actually an "Elsa Erazor X-A32", imirkin_.
16:36 karolherbst: RSpliet: btw, did you see the PLL bypass lock patch?
16:37 karolherbst: you probably know the most about it, and we were wondering why that bit is set nouveau even though nvidia literally never sets it
16:42 imirkin_: chf: hehe. brands of days past. good to remember...
16:42 imirkin_: i had a Elsa tdfx for a while, recycled from somewhere.
16:42 imirkin_: i think the board cost like $1k new, but it was free by the time it hit my comp
16:42 imirkin_: er, not tdfx ...
16:43 imirkin_: the other one... 3dlabs?
16:43 chf: Voodoo? 3dfx?
16:43 imirkin_: no
16:43 imirkin_: 3dlabs.
16:43 imirkin_: trident or whatever
16:44 chf: S3 chip perhaps
16:44 imirkin_: right. glint was the driver.
16:44 imirkin_: no, 3dlabs made their own boards
16:44 imirkin_: http://vintage3d.org/3dlabs.php#sthash.tuRlxyrw.dpbs
16:47 chf: Ah, this one… never had one, but on the Gloria actually is a S3 for non-3d stuff.
16:47 imirkin_: yeah
16:47 chf: Trident reminds me of something.
16:47 imirkin_: that's probably why it worked :)
16:48 imirkin_: it's all hash in my memory =/
16:51 chf: I think I still have got Trident cards somewhere…
16:51 chf: I've not thrown away anything that still works yet.
16:55 imirkin_: that board started sparking out of the VGA connector... i think i dumped it :)
18:18 meeku_: ok, well on an intel gpu the 03dah port doesn't seem to do anything useful
18:21 meeku_: https://www.irccloud.com/pastebin/CU966hQs/
18:21 meeku_: which would make you think it should still work
18:21 meeku_: even if it's not "ideal"
18:24 imirkin_: "will come from the pipe that the VGA is assigned to"
18:24 imirkin_: might not be assigned anywhere good
18:29 meeku_: the bit whatever value it is, seems to be stuck.. as the loop never exits