15:58 pendingchaos: imirkin_: I don't think NVC0_3D_MACRO_QUERY_BUFFER_WRITE handles big-endian architectures
15:59 pendingchaos: so I think I'll also try to change it to work on them
16:01 imirkin: pendingchaos: BE arches and SSBO's are kinda fubar anyways...
16:01 imirkin: i tend not to worry about that
16:01 imirkin: note that BE arches will configure the board in such a way that all fifo data is byte-swapped too
16:02 imirkin: i.e. if you write 00 00 00 01 into the fifo pushbuf, it will get interpreted as 01 00 00 00 by the hw.
16:18 pendingchaos: so the gpu is always a single (little?) endianness?
16:23 pendingchaos: if so, I don't think I'll have to do anything then
16:30 imirkin: i don't want to lie to you... my understanding of it is somewhat hazy as well. however the *internals* of the gpu are always LE afaik
16:30 imirkin: the BE mode just switches on a lot of implicit BE <-> LE conversions
16:30 imirkin: in places where data width is ambiguous, you can usually specify it
16:30 imirkin: but this barely works with UBO's, and i don't think it can really work with SSBO's
16:31 imirkin: it's largely academic since BE is dead
19:43 gruetzkopf: *mostly dead
19:43 gruetzkopf: there's still quite a bit of ppc-be and mips-be in the hand of people
20:06 imirkin: eh ... but PCIe-capable ones? not so many.
20:06 imirkin: anyways, if someone has such a system and wants to send patches, happy to apply