10:26xaero: how well supported is a 970m as of now?
10:29karolherbst: xaero: should be fine with a recent kernel
10:30karolherbst: xaero: there are issues regarding reclocking on those, but I got a fix for that in the case the fans are controlled by the EC
10:33xaero: mind sharing said fix karolherbst ? :)
10:33xaero: and thanks
13:01karolherbst: yeah, I can get access to a rather cheap laptop with 970M
18:28karolherbst: making good progress with P 0x50 table (sw temperature clock throttling )
18:47karolherbst: okay nice, I can read out when to start downclocking and upclocking again
18:47karolherbst: and if we ignore the other factors (speed of down/up clocking) then we have a solid mechanism for kepler+ GPUs
19:25mupuf: karolherbst: wow, congrats!
19:25mupuf: How did you proceed?
19:33karolherbst: mupuf: changing values inside the vbios and see what changes
19:34mupuf: am I misremembering? I thought this one was really bad and the meaning would change depending on some bits
19:39karolherbst: mupuf: yeah, kind of
19:39karolherbst: there is a type byte on 0x00
19:40mupuf: I see, not so bad then
19:40karolherbst: and for 0x01 I am able to tell what thresholds are important
19:40mupuf: how did you check the thresholds?
19:40mupuf: increased the temperature with nvaforcetemp?
19:41karolherbst: and there are two offset bytes
19:41karolherbst: 16bit values
19:41mupuf: 16 bits, wow :D
19:41karolherbst: 1:32 accuracy
19:41karolherbst: t0 is u16 at 0x2
19:41karolherbst: and a value of 32 means 1°C
19:42karolherbst: then you have a u16 value at +0x12 and +0x14
19:42karolherbst: +0x12 offset for downclock threshold
19:42karolherbst: +0x14 offset for upclock threshold
19:42karolherbst: and you always got +-1
19:43karolherbst: if t0 = 95°C and down offset = 1°C and up offset = 1°C, you get downclocking at 97°C, upclocking at 93°C
19:43karolherbst: there seem to be two more temperatures and 4 more offsets I couldn't figure out what those do
19:43mupuf: I see
19:43karolherbst: I only see type 0x01 in use actually
19:44karolherbst: some vbios have two entries
19:44karolherbst: table exists since kepler
19:44karolherbst: but this is fine for enabling maxwell2 reclocking on "fanless" systems
19:44karolherbst: should be safe enough (tm)
19:44karolherbst: if hidden behind a module parameter
19:45karolherbst: if we hit the downclocking threshold, we just go to the lowest cstate
19:45karolherbst: and ignore those fancy downclock sliding nvidia does
19:45karolherbst: there is an interval in the entry as well
19:45karolherbst: and a speed parameter
19:46karolherbst: so it might state -50MHz / check, and intervall can be 200ms
19:46karolherbst: but we can ignore it for now and add this later if we really want to
19:47karolherbst: most desktop GPUs set the t0 value to 80°C
19:47karolherbst: and have a second entry at 95°C
19:48karolherbst: I even saw 101°C once, no clue why
19:48karolherbst: sounds like a bs value to me
21:05karolherbst: mupuf: we didn't found a more accurate temperature sensor, did we?
21:06mupuf: karolherbst: you need more than half a degree?
21:06karolherbst: because they state temperatures with 1/32 °C precision in the vbios
21:06karolherbst: just wondering
21:06mupuf: well, you can read the temperature straight at the ADC level, but that's it
21:06karolherbst: allthough I only really saw "79.53", which could basically be 79.5
21:07mupuf: I think this is just designed by weirdos
21:07karolherbst: maybe to be future-proof (tm)
21:07mupuf: yeah, right...
21:07RSpliet: Or the low 5 bits are reserved for other uses?
21:07karolherbst: found a "79.38"
21:08karolherbst: RSpliet: uhm, maybe
21:08karolherbst: but then there would be 9 of those in total
21:09karolherbst: and then there you have negative values
21:09karolherbst: "fe ff" and "3e ff"
21:11RSpliet: I didn't look into the data, you'd probably know better. Just stating the sort-of-obvious :-P
21:11karolherbst: yeah dunno, I think those are weirdos indeed
21:11karolherbst: or maybe there is a more precise sensor somewhere
21:11karolherbst: or maybe not
21:26mupuf: a more accurate sensor would make 0 sense, because the temperature is not uniform on the chip
21:28RSpliet: mupuf: talking in the void again? :-P
21:29RSpliet: Happens to the best of us... and me as well!
21:40mupuf: RSpliet: I know, I know :D But hey, he reads the logs when he is back :p