00:00mupuf: Lyude: power gating is quite hard
00:00mupuf: it involves the PMU
00:00mupuf: and I never managed to get it to do anything
00:02Lyude: mupuf: I knew it couldn't have been as easy as that patch was. still, "hard" translates to challenge for me :P
00:03mupuf: it is a complex beast...
00:03mupuf: and honestly, I spent most of my time trying to figure it out
00:03mupuf: but clock gating is hard to follow
00:03mupuf: at the very least, we should reproduce what we know is associated with clock gating
00:05Lyude: mupuf: so just lots of load testing to make sure we don't brownout, and making sure power is actually getting saved correct?
00:05mupuf: well, testing will come from users
00:05mupuf: Recommendations: Run heavy benchmarks for a couple of hours
00:05mupuf: if you get no crashes, it is good enough ;)
00:06mupuf: same recommendations as overclockers, really
00:06Lyude: sounds good to me
00:06mupuf: but we cannot have it on by default
00:06mupuf: I wonder if tainting the kernel would be a little too extreme or not
00:07mupuf: but we should add in the kernel logs or mesa's logs when clock gating and power gating is enabled
00:07Lyude: to be fair I can think of worse things the kernel doesn't taint on that I wish it did
00:07mupuf: or reclocking
00:07mupuf: now, I should probably be in bed already. Good night guys!
00:07Lyude: alright. I'm guessing the eventual plan is to turn it on by default once we actually all the parts implemented and know that it doesn't break?
00:07Lyude: oh, good night!
00:08Lyude: *actually have all
00:08mupuf: Lyude: let's talk about that when we get a hundred users who tested enabling clock gating, while being at the high perflvl
00:09mupuf: when we get to this point, we'll be quite good!
00:09mupuf: clock gating should not introduce as big an instability as improper reclocking does
00:09mupuf: brownouts are a reality though
00:10mupuf: but hopefully, the voltage guard band is safe enough
00:10mupuf: we could create a program that would run benchmarks and report results
00:10mupuf: so we can keep track of the stability
00:10mupuf: but that may be a little extreme :D
00:11mupuf: let's try our best first
00:11mupuf: and we'll see
00:30PyroSamurai: server client conked out, seems I missed rubdos
00:30PyroSamurai: hi mwk
00:31PyroSamurai: btw we have huge list of people on the chat but only see the regulars talking, is that the norm?
00:35Teklad: PyroSamurai: It is.
00:35Teklad: I drop in from time to time to be a slave driver.
00:35PyroSamurai: Doesn't make much sense. I mean you don't really have to lurk on a channel that is publicly logged to make sure you don't miss anything.
00:36Teklad: PyroSamurai: Reading through chat logs is informative.
00:36Teklad: I get to keep up with nouveau progress on Pascal.
00:37PyroSamurai: Teklad: Indeed it is informative, but I mostly referencing those who never talk. They can simple read the public backlog after all.
00:37PyroSamurai: I am*
00:38Teklad: PyroSamurai: I haven't figured that out either... There's thousands of users in your average #xx linux distro channel.
00:38Teklad: Yet maybe 30-50 of them are active.
00:39PyroSamurai: Teklad: that I get though since most channels don't have public logs like nouveau and the freedesktop channels
00:41Teklad: PyroSamurai: But why rot your life away reading logs all day? Lol... that's a TON of log to read.
00:45PyroSamurai: Teklad: lots of good info
00:45Teklad: I'd get fat reading all that info.
00:47PyroSamurai: I think most young people are good at scanning internet info for relevant data. I don't read everything just the technical stuff which helps me understand the process more
00:50PyroSamurai: but yeah HI LURKERS :D
00:55PyroSamurai: btw totally gonna setup a site for RE info, both software and hardware, because I have a hard time finding it myself and it is important so yeah.
01:45Horizon_Brave: I really hate CAPCHA's at certain times....
01:46Horizon_Brave: and by certain times I mean 99% of the time
04:03mooch2: how did i do, s-senpai? https://github.com/envytools/qemu/commit/148c925a54f699c5bc34b4f3ac65bd3353afe3c4
08:04rubdos: PyroSamurai: yeh, you missed me :')
08:04rubdos: PyroSamurai: I'm not sure whether it was nouveau failing on me. I had kind of the same symptoms under proprietary now.
08:04rubdos: Offer still stands though; I can get my hands on several of these T61p's, probably cheaply.
08:05rubdos: So if you guys want one, for RE or other debugging, let me know.
08:13dboyan_: rubdos: Is the bug you are facing a GL-related one? If so, you can try to make an apitrace and see if it is reproducible under nouveau.
08:15karolherbst: mupuf: the effect while running games is kind of low though, there is one, but it's around 2%
08:15karolherbst: maybe even 3%
08:16karolherbst: mupuf: I have this one bit enabled for nearly an entire year now :p
08:17karolherbst: can't say it doesn't affect a desktop GPU though
08:17mupuf: I once managed to get more like 20% when running xonotic and enabling the auto downclock on idle (using the FSRM) and I had no performance drop at all.
08:17mupuf: yep, we just need moar data ;)
08:17karolherbst: auto downclock :p
08:17karolherbst: if I cut the clock through a fsrm by 1/8 I also get a power consumption drop of 50%
08:18karolherbst: but I was speaking about same clock, same voltage just with clock gating enabled/disabled
08:19karolherbst: mupuf: if you want, I could test the affect on the min voltage requiernments with clock gating enabled on my GPU
08:20mupuf: oh, that is a sweet idea!
08:20mupuf: downclocking (without voltage change) is a poor-man's clock gating
08:21mupuf: the FSRM does not change the voltage
08:22karolherbst: I know
08:22mupuf: but I guess we'll need to use envdump's metric dumper to know for sure
08:23karolherbst: I simply enable clock gating on my GPU whenever I load nouveau through nvapoke and also set runpm=0, and I didn't notice any stability problems so far
08:23mupuf: but do this work, I need to add another fan management technique for the gpu: Keep the temperature constant
08:23karolherbst: doesn't matter on my system
08:23karolherbst: you now, EC controlled fan
08:23mupuf: and that will require a calibration phase = knowing how much power each speed requires
08:24mupuf: karolherbst: sure, but the temperature will change and that affects power usage
08:24mupuf: so you get a double effect
08:24mupuf: and Iwant to know, for a constant temperature, what is the power usage
08:24karolherbst: hard to tell
08:24mupuf: and not get the double improvement that a lower power consumption yields
08:24mupuf: not so hard though
08:24mupuf: ok, have to go
08:24mupuf: see you guys!
08:25karolherbst: well, you can only get a range :p
08:25karolherbst: power consumption is really volatile depending on the load
08:25karolherbst: except we disbaled like _all_ the power saving features
08:25karolherbst: no idea how to do that
09:12hakzsam: dboyan_: imirkin_: series pushed
09:12hakzsam: dboyan_: thanks for your work
09:24rubdos: dboyan_: I'm not sure at all. I think something fishy is going on with memory usage.
09:24rubdos: I'll check later; at work now.
10:24dboyan_: hakzsam: Thanks
10:25hakzsam: dboyan_: what's your next task? :)
10:27hakzsam: dboyan_: one interesting thing to do is to run a full piglit against pascal and compare with maxwell
10:27hakzsam: not sure if someone already did that
10:27hakzsam: (compare with maxwell or kepler)
10:53mupuf: hakzsam: there is a maxwell and a pascal in reator
10:53mupuf: the kenrel needs to be updated though
11:30dboyan_: hakzsam: I guess I want to take my gsoc project into account for the following days :)
11:31dboyan_: I might want to do some other stuff if I get more time though
11:32hakzsam: good plan
11:54technohacker: hey devs, just wanted to know whether nouveau is supposed to manage HDMI audio output through the nvidia GPU
11:54technohacker: lspci shows that it is managed by snd_hda_intel
13:58robclark: imirkin_, btw, random question.. how much does codegen care about CFG structure when going (for example) from tgsi -> codegen? Does it care at all about if/loop/etc or just about list of basic blocks and successors/predecessors?
14:04pmoreau: robclark: IIRC, it is sensitive to the type of edges used (tree, back, forward), but there is nothing special to ifs nor loops (besides the join instruction, but I am not sure whether the CFG cares much about it).
14:04robclark: ok, so you care about convergence points.. I guess that basically amounts to having >1 successor?
14:05robclark: err, predecessor
14:06pmoreau: I would say so
14:31imirkin_: robclark: unfortunately that bit of it is the definition of fragile
14:31imirkin_: robclark: you look up 'fragile' in the dictionary, it's defined as 'nouveau cfg'
14:32imirkin_: robclark: aside from various annoyances, the idea is that the CFG edges are annotated based on a MST notion
14:32imirkin_: the tgsi -> nv50 ir converter assigns edge types directly, and gets it wrong
14:32imirkin_: it does have the advantage of working, but i've been quite fearful of trying to "true it up"
14:34imirkin_: basically it's the sort of thing that if i break, i'm not sure i'll be able to fix
14:34robclark: imirkin_, hmm, I was a bit wondering what would happen w/ cl.. consuming spirv (without whatever hints that gfx spirv has about cfg) or llvm (which seems to have no cfg info)..
14:34imirkin_: since i only pretend to understand RA & such
14:35imirkin_: i play a compiler writer on TV :)
14:35robclark: that sounds like a fun tv show :-P
14:35imirkin_: anyways, i mean it needs CFG in that block A goes to block B
14:36imirkin_: but there's no distinction between, say, an if/else and a loop
14:36imirkin_: however there are some heuristics at the end
14:36imirkin_: which see e.g. an if/else that's dependent on a predicate, and it will flip them into predicated things rather than having branches
14:37imirkin_: but it just uses the block structure for that
14:37imirkin_: this will, i suspect, fall FLAT on its face in sight of "more complex control flow"
14:37imirkin_: esp since it likes to know when there's going to be divergence, and when the divergence ends
14:37imirkin_: the way that's thrown in right now is manually up-front by the tgsi -> nv50 ir converter
14:38imirkin_: so if there's no divergence info given by whatever input ir, that won't be great.
14:38imirkin_: (look for OP_JOINAT and OP_JOIN)
14:39imirkin_: further fun is that nv50 and nvc0 do this differently, but it's sufficiently compatible to have a fixup pass post-ra
14:41robclark: ok.. I *think* just given a list of blocks, like llvm (and I guess spirv compute would be similar).. you might have to work out the predecessor blocks yourself but that should give enough info to figure out join points..
14:51imirkin_: yeah, we don't figure it out today, but we could
14:52imirkin_: it's some graph algorithm
14:52imirkin_: we have the graph... and we could copy the graph algo :)
15:19tstellar: robclark: At the API level LLVM blocks know what their predecessors are.
15:20robclark: ahh, ok.. that simplifies thing
16:24pq: that is so weird... I boot my laptop (G96), startx (fluxbox), everything is fine. Quit X, start again: somehow it forgets to repaint the root window at start, showing black instead of wallpaper. If anything causes a region to be redrawn, the correct image appears on that region.
16:25pq: it always forgets to repaint the root window, except on the first start after a (cold) boot.
19:01Lyude: omg no
19:01Lyude: imirkin_: i was in the middle of trying to write my own multisampling test for that post depth coverage extension
19:01Lyude: and then i noticed something. went back to master, and tried running that multisampling test using piglit instead of just launching the binary
19:01Lyude: turns out the test actually works
19:05Lyude: aren't piglit tests supposed to, also just work properly when you run them directly? or have I been misled
19:08imirkin_: not sure what the distinction is.
19:08imirkin_: oh, you were running without -fbo perhaps? that can matter.
19:09imirkin_: or perhaps the person who wrote the test made it work differently?
19:09imirkin_: and/or in automatic mode?
19:10Lyude: man i can't believe how much time i wasted on this aaa
19:10Lyude: and imirkin_ yeah I didn't have -fbo, didn't realize that was a thign I needed
19:10karolherbst: ask early and often :p
19:10Lyude: honestly it didn't even cross my mind
19:11imirkin_: but you learned something :)
19:11Lyude: i learned a good bit!
19:17karolherbst: mupuf: mind replacing the pascal with a maxwell2?
19:18karolherbst: it's now fun if the nouveau module crashes for silly reasons :/
19:29Lyude: hrm, GM108 should be able to support extensions like ARB_post_depth_coverage shouldn't it?
19:30Lyude: oh no, gm200 class
19:30imirkin_: afaik no
19:50Lyude: hold on, I should be able to get mesa working on pascal shouldn't I? or is there something we don't have yet to make that work
19:50Lyude: hm, actually I wonder if maybe the linux-firmware package on here is just out of date
19:52Lyude: skeggsb: do we have the firmware for pascal in fedora yet?
19:58imirkin_: it's in linux-firmware. can't comment on distros.
20:02imirkin_: you need kernel 4.12 (/drm-next) to use it though
20:03Lyude: ahhhh, that explains things
20:03Lyude: thanks for the tip
20:37karolherbst: uhhh, silly pascal card :/
20:38Lyude: actually, does anyone have anything with pascal or maxwell2 in it?
20:38Lyude: that I can ssh into
20:38karolherbst: Lyude: did mupuf set your key up already?
20:38Lyude: i have just killed my pascal machine at home and dxon't have any way of rebooting it :(
20:38Lyude: karolherbst: nope
20:38karolherbst: well, then no :p ask mupuf very nicely then
20:39Lyude: mupuf: can I have access to your nvidia machines pretty please?
20:40karolherbst: uhm.. why I am so silly and do silly things
20:42karolherbst: note to myself: do things right from the start
20:42jamm: hakzsam: regarding line 25 in https://pastebin.com/QKKGuKfL, how is ipa using $r2:$r3 together? Actually, I'm kinda stumped at understanding the syntax of ipa.. i'm looking at maxas gm107.c, still trying to make sense of the grammar there. (Sorry for the late response, been travelling a lot lately)
20:42Pie_Mage: you should make a time machine and go back in time and secretly stick that note to your monitor
20:43hakzsam: jamm: the envydis output just follows nvdisasm's syntax which is... unclear
20:43hakzsam: jamm: $r2 is 64-bit
20:44jamm: i do know that ipa is one of LINTERP/PINTERP ops, but which one's the source/dest is kinda unclear to me, hmm
20:44hakzsam: so you have to read it as $r2:$r3
20:44hakzsam: $r2:$r3 is the dest
20:46jamm: hakzsam: ah, i see.. so the GPR's are 32bit but the $r2 is being read as $r2:$r3 so as to refer to a 64bit chunk?
20:46hakzsam: so, it reads a 64-bit value at offset 0x90 in addr space a, $r0 is some sort of indirection I would say
20:47hakzsam: ipa $r2:$r3 a[0x90] $r0 0x0 0x1 --> this would be easier to read
20:48hakzsam: it's displayed like this for pre-maxwell ISA though
20:52imirkin_: that's wrong
20:52jamm: hakzsam: i see.. so ipa reads a 64bit value from the src and writes it into a 64bit dst, in this case $r2:$r3 (Written as $r2 here)
20:52imirkin_: ipa does not do multiple components at a time
20:52imirkin_: tex, on the other hand, consumes multiple components
20:52imirkin_: tex nodep $r1 $r2 0x0 0x1 t2d 0x8
20:52imirkin_: is really
20:52imirkin_: tex nodep $r1 $r2:$r3 0x0 0x1 t2d 0x8
20:53imirkin_: does that make sense?
20:53hakzsam: ah my bad, I misred
20:54hakzsam: "tex nodep $r1 $r2 0x0 0x1 t2d 0x8
20:54hakzsam: $r2 is actually $r2:r$3 (ie. a 64-bit addr). Make sure to wait for the two ipa bars."
20:54imirkin_: well, it's not a 64-bit addr
20:54imirkin_: $r2 is the x coord, and $r3 is the y coord
20:54imirkin_: it's a 2d texture sampling op
20:55jamm: ah, my bad too! i misread as well
20:55jamm: it's tex and not ipa
20:56jamm: imirkin_: by multiple components, you mean any consecutive set of registers?
20:56imirkin_: so ...
20:56imirkin_: IPA = InterPolate A (my personal guess)
20:56imirkin_: A is the shader input/output space
20:57imirkin_: some ops, like LDC can come in LDC.64 and LDC.128 varieties (actually iirc .128 doesn't work)
20:57imirkin_: which will read 64 bits worth of data and store it to sequential registers
20:57imirkin_: IPA has no such variants
20:58jamm: oh wow, now it makes sense
20:58jamm: thanks a lot :D
20:58imirkin_: each register ultimately holds a 32-bit quantity
20:58imirkin_: on nv50 there's functionality to address half-registers as well
20:59imirkin_: and on GM20B and pascal+, i understand that there's a way to perform fp16 math. i don't know how that's encoded however.
20:59jamm: right, so these GPR's are 32bit but they can be used in sequence to refer to bigger values for ops' that can handle them
20:59imirkin_: right - well the op does whatever it wants ultimately
20:59imirkin_: you don't pass a register to it, you pass it a register id
21:00imirkin_: and it does with that id whatever it pleases. normally that's reading from the relevant register
21:00imirkin_: but under certain circumstances, it can also read sequential registers
21:01hakzsam: jamm: except this, how about the other comments? makes sense?
21:02imirkin_: man, nouveau really sucks at dota2
21:03jamm: hakzsam: about the rd -> wr comment, i put that because i assumed $r0 is being read from or something
21:04jamm: imirkin_: hmm, maybe it's the source engine? gotta check if cs:go or day of infamy also sucks with nouveau XD
21:04jamm: i'll be trying em out this weekend
21:04hakzsam: jamm: yeah, but you already for $r0 in mufu rcp $r0 $r0
21:04jamm: hakzsam: right
21:05jamm: ah, i was looking the control codes wrong
21:05hakzsam: wr is for dst registers, rd for src registers
21:06jamm: okay, so these control codes, they set the read/write dep bars (for the consecutive 3 instructions) all at once via sched, right?
21:06jamm: i was looking at them procedurally, one by one
21:09jamm: hakzsam: thanks! i'll send another paste here with the changes, then begin with whatever i've learned on the other shaders :D
21:09jamm: after i get your LGTM that is
21:11jamm: fwiw, i'm currently on a pc with 980Ti which i'll have access to till next weekend after which i travel back to work
21:11jamm: at home i have a 1080 but it should work fine as well, i guess
21:15hakzsam: jamm: I don't understand your question, but basically:
21:16jamm: hakzsam: nvm, it was just me typing to myself (gotta keep it afk next time XD)
21:16hakzsam: for loads, like 'ld $r0 g[0x0]', ld has a variable latency, so you need to emit a write dep bar (wr) to prevent RaW hazards
21:16hakzsam: for stores, like 'st g[0x0] $r0', you need to emit a read dep bar (rd) to prevent RaW hazards (in case $r0 is used *after* of course)
21:17imirkin_: jamm: dota2 appears to be extra-suck
21:17hakzsam: jamm: there are many corner cases, but the basic idea is simple :)
21:18hakzsam: 44 vs 175, nice perf
21:18jamm: hakzsam: makes sense.. i'm also referring to your commits on mesa
21:18karolherbst: "nice" perf
21:19karolherbst: well compared to stock clocks, it's indeed nice
21:19hakzsam: yeah, 10fps is a joke
21:19karolherbst: those 44 fps are a joke as well though
21:19karolherbst: but maybe dboyan_ helps out here :p
21:20jamm: console gamers would be happy with >= 30fps :P
21:21RSpliet: yeah but consoles have AMD
21:21karolherbst: hakzsam: funny that we are better on maxwell....
21:22karolherbst: but yeah, 25% vs 29%....
21:22karolherbst: _big_ difference
21:31jamm: hakzsam: for waiting on wr 0x0 and wr 0x1, is wt 0x3 appropriate?
21:32imirkin_: should be an auto-response in our bugtracker...
21:33jamm: hakzsam: great! i asked coz i got a bit confused by the usage of wt 0x3 here https://cgit.freedesktop.org/~hakzsam/mesa/commit/?h=gm107_scheduler&id=6a4503026525246b9330da2b08e2caa71a963a5b
21:33jamm: see "sched (st 0x6 wr 0x0 wt 0x3) (st 0xd wt 0x1) (st 0x1)"
21:34jamm: here only 0x0 is set, but wt 0x3 is present as well
21:34jamm: could be one of those corner cases, i guess
21:35hakzsam: wt happens *before* the instruction
21:36hakzsam: in this case, we are waiting for $r0 and $r3
21:36hakzsam: err, $r0 and $r1
21:39hakzsam: dboyan_: jamm, btw, one other interesting task is to replace imul/imad by xmad on maxwell+
21:40hakzsam: the main advantage is that xmad doesn't require any dep bars
21:40hakzsam: and I have never seen blob using imul/imad on maxwell
21:40hakzsam: always xmad, but the hard part is to figure out the different flags :)
21:41imirkin_: the main advantage is that xmad is a lot faster too
21:41hakzsam: of course
21:41hakzsam: it needs 6 cycles and no dep bars
21:41hakzsam: way faster
21:41imirkin_: but needs figuring out of how it works
21:41imirkin_: at least enough to replace imul/imad
21:41karolherbst: and what problems does xmad have?
21:41imirkin_: we don't know how it works :)
21:42hakzsam: and the flags are tricky :)
21:43hakzsam: one approach is to write a very simple GLSL test with piglit, record a MMT with valgrind-mmt, extract the shaders and think :)
21:44hakzsam: jamm: does it make sense to use wt 0x3 there?
21:45jamm: i could definitely help with that.. sounds like a good opportunity for further improvements. Hopefully this sched code work would help me understand the existing instructions better :)
21:45jamm: hakzsam: i understood that $r0 and $r1 are being waited on, but where are their respective bars being set?
21:45hakzsam: ok so
21:45hakzsam: $r0 comes from imul u32 u32 hi $r0 $r0 $r2
21:46hakzsam: and it's emitting a wr 0x0, so wt 0x1
21:46hakzsam: $r1 comes from i2i u32 u32 $r2 neg $r1
21:46hakzsam: rd 0x1, so wt 0x3
21:46Lyude: oh, okay, imirkin_ so it looks like that I didn't actually completely waste my time here. I just noticed this multisampling test only breaks if I comment out the lines in the fragment shader that enable arb_post_depth_coverage… but if I break things from the actual GL driver it, doesn't break?
21:48imirkin_: probably becuase you're disabling early fragment tests?
21:48Lyude: i was just about to say i thought that was it
21:48Lyude: that is a relief :)
21:50hakzsam: jamm: you might want to say: but why do we use a read dep bar there because imad also reads $r1?
21:50mupuf: Lyude: ok, giving you access now
21:50jamm: hakzsam: oh, these are instructions above the sched containing wt 0x3
21:50mupuf: for some reason though, adding your name to wtrpm has been yielding surprising results
21:51mupuf: AKA: segfault :o
21:51hakzsam: jamm: sure. as I said 'wt' is before
21:51karolherbst: too short?
21:51hakzsam: mupuf: lol
21:51Lyude: mupuf: neat
21:51imirkin_: Lyude: i'd still recommend writing your own test
21:51jamm: hakzsam: ah, i see now
21:51imirkin_: i don't think that was a well-written test
21:51karolherbst: or too many names
21:51Lyude: good thing I didn't throw out the test I started!
21:52imirkin_: tbh i'm not entirely sure what that test does
21:52imirkin_: or how it works
21:52jamm: hakzsam: so the wt waits on rd/wr's set on the sched before it
21:53hakzsam: jamm: so, I use a read dep bar because imad writes *into* $r1 and maybe imad can be done before i2i (not the same unit)
21:53imirkin_: perhaps it's a perfectly fine test. i don't know :) in yours, try to add lots of comments about how it's meant to work.
21:53Lyude: yeah i am mostly sure it's a bogus test
21:53hakzsam: jamm: yes, wt applies for sources only
21:55hakzsam: jamm: https://hastebin.com/faraxivagu.pl
21:55hakzsam: maybe this will help
21:55hakzsam: it's not totally correct, just a different way to think of
21:57jamm: hakzsam: understood, so this explains for that particular unit
21:59jamm: and as you explained above, the wt 0x3 comes from the bars applied in the previous unit
22:00hakzsam: why unit? it's not appropriate
22:00jamm: err, by unit i mean, instruction triplets
22:00jamm: sorry, not sure what the correct term is
22:01hakzsam: I would say block of 3 instructions, but I never use that
22:01jamm: block, yeah that sounds better to me
22:02jamm: so the wt 0x3 basically waits on the two registers $r0 and $r1 being used by imul and i2i respectively
22:02jamm: from the previous block
22:02hakzsam: not sure if it's clear, but dep bars are not set per block (ie. you can emit a wr dep at instruction 0 and wait at instruction 1545)
22:02hakzsam: that's correct
22:02jamm: so they're global
22:03hakzsam: they are
22:03jamm: i mean, global wrt. to that particular asm
22:03hakzsam: global to a program
22:03hakzsam: but nouveau codegen doesn't support that for some reasons
22:03jamm: thanks for correcting me, i'll have to get used to some new jargon now ^^
22:04hakzsam: just noticed, but sched codes on maxwell can be improved in many ways
22:04hakzsam: like dual-issue
22:05jamm: you mean the ones on nouveau or in general?
22:06hakzsam: the code emitter
22:06hakzsam: in nouveau codegen
22:06jamm: ah, right
22:06hakzsam: few things I have in mind: dual-issue, use getReadLatency() and understand the yield flag
22:07hakzsam: you might be able to get, let's say +10-20% of perf
22:08hakzsam: (maybe more with shaders bound applications like piano, furmark etc)
22:08hakzsam: but not +200% :p
22:12karolherbst: oh no, now I have to fight with Lyude over reator :(
22:14jamm: hakzsam: yeah, sounds interesting.. doesn't feel like it'd give as much of a boost as replacing imul/imad, i guess
22:14jamm: but definitely worthwhile improvements
22:15hakzsam: well, integer multiplications are not really much used
22:15hakzsam: the yield flag is probably the best, but it's hard
22:16hakzsam: getReadLatency() is funny though, and should be simple :)
22:17hakzsam: and dual-issue will become useful with dboyan_'s gsoc
22:17jamm: cool! glad to see a gsoc project here
22:17jamm: i did one at wine myself, but that was way high up at API level
22:18jamm: i'm trying to discover lower levels now, see how it suits me
22:18jamm: so far, not tired, but time consuming
22:18jamm: getting there though, slowly
22:19karolherbst: there is only one way: work on the kernel :p
22:19jamm: yeah :d
22:19jamm: for me, anything graphics is really interesting
22:19karolherbst: have no fear, the kernel won't bite, only mess up your file systems
22:20jamm: whether it's high up in shader programs or low down here in asm
22:20karolherbst: well, asm is on its way out
22:20karolherbst: you won't do any asm in the kernel
22:20karolherbst: well, no, you won't
22:20jamm: well, that'd be nice i guess ;D
22:22jamm: ah, but nothing in kernel interests me atm, except dri/drm probably
22:23hakzsam: jamm: how may shaders need to be translated in the DDX?
22:24jamm: hakzsam: 8 i believe, *110*.fp/vp
22:24jamm: many are similar
22:24jamm: two of em are different
22:27karolherbst: huh, duh, who clears out the scratch register :/
22:28jamm: hakzsam: is this ok? https://hastebin.com/juturajelo.bash
22:30hakzsam: jamm: nope, wt 0x0 == no waits
22:30hakzsam: it's a bitfield
22:30hakzsam: if wr 0x0, you need wt 0x1
22:30hakzsam: (I know it's confusing)
22:31hakzsam: this is because wt 0x0 is "reserved", it's a no-op
22:31jamm: wt always starts from 0x1, then 0x3,0x7.. to 0x3f
22:33hakzsam: jamm: fmul doesn't need any dep bars
22:34jamm: hakzsam; yeah, just realized the fixed latency ops don't require any bars, am i right?
22:34jamm: iirc, it was mentioned in some of your comments
22:34jamm: i'll have to re-read them to understand better
22:35jamm: as well as the control codes article on maxas
22:35hakzsam: well, instructions which have a fixed latency don't need any bars yes
22:35hakzsam: after a quick look, except wt 0x0 and fmul it looks good
22:36jamm: thanks a lot! i know many of the questions i asked were redundant, but your help really kicked things up a notch for me :D cheers
22:36hakzsam: but I will need to think more on the morning to make sure there are no corner cases :)
22:36hakzsam: no worries
22:36hakzsam: feel free to send me an update version
22:37jamm: hakzsam: updated https://hastebin.com/giwiyipafa.bash
22:37jamm: i'll work on the other shaders with similar structure in the mean time
22:37jamm:goes to sleep, cya guys!
22:38hakzsam: okay, see you
22:38hakzsam: I will send you comments tomorrow
23:40phoenixz: Hi there, I was here a month or so ago with problems on linux mint 18 with three nvidia video cards.. Ended up using only two with two monitors because anything else simply didn't work. I've decided to buy a new video card with multiple outputs, so that I can connect 3 monitors on one card using HDMI (I don't want to use converter cables from DVI and that sort of stuff). I have budget of about 200 - 300 USD, but I'm located in Mexico.. Could
23:40phoenixz: anybody help me with recommending a video card?
23:40phoenixz: As in, I don't want to buy yet another video card (I'll have to sell these three for near nothing now anyway) and again get stuck with a system that doesn't work..
23:47gnarface: phoenixz: my recommendation is to drop your hard-line stance against adapters. you should be able to get a cheap adapter to convert HDMI to DVI or DVI to HDMI without any quality loss
23:48phoenixz: gnarface: Well its not a hard line stance.. I guess its more a "its 2017 why do I still need adapters??" kind of stand, I'd like to avoid it if possible.. If not possible, then adapters it is...
23:49phoenixz: Are there video cards which can control 3 monitors without problem?
23:49gnarface: phoenixz: well, it should not be necessary to replace the entire cables, and since HDMI and DVI are both digital, the converters won't cause echoes or anything like that you'd expect with older analog connections
23:50gnarface: phoenixz: there ARE video cards that can control 3 monitors without a problem, but i can't tell you if any of them currently do or ever will even work with nouveau
23:50phoenixz: gnarface: yeah, I know, just that ... I dunno, I guess this thing in my head :)
23:50phoenixz: gnarface: would they work with (ugh) nividia binary?
23:50phoenixz: Because so far, nvidia binary basically is a russian roulette fiesta on my computer...
23:51gnarface: phoenixz: yea, they should with the proprietary drivers, though xorg setup may not be super straightforward and #nvidia is likely to be hostile and useless
23:52gnarface: phoenixz: the adapters though... i've got these things just laying around. i've gotten a handful over the years for free
23:52gnarface: phoenixz: certainly it can't be that hard to get your hands on used ones?
23:52gnarface: seems to me to be the cheapest, sanest, least-intrusive option anyway
23:53phoenixz: gnarface: I already got me one adapter cable (haven't found "just" adapters here) but they were like 20USD.. Not hugely expensive, but still an anoyance I guess..
23:53phoenixz: gnarface: Any cards you might recommend on a personal level?
23:55gnarface: phoenixz: my gf just got one of those new GTX 1060 Ti cards, 6GB edition from ASUS. it's real nice and it has like 8 HDMI ports plus a DVI port. also ~300$ if you find one on sale. i'm almost certain it does not work with nouveau though currently, and if that's true i wouldn't hold my breath for it changing, ever
23:55gnarface: phoenixz: maybe check ebay for cheap adapters?
23:56phoenixz: gnarface: Aren't you a nouveau dev? I mean, if my gf ever got a new video card and the driver wouldn't support it.. ;)
23:56phoenixz: I will
23:56phoenixz: Well thanks very much, I'll take a look for that GTX 1060 card
23:56phoenixz: Other problem is that I'm in mexico, it can be a bit hard to get hardware here sometimes :D
23:57gnarface: phoenixz: heh, sorry no i'm no dev. i just hang out here to watch the progress. i have some older nvidia cards i hope will one day be supported by nouveau fully since the official drivers no longer do and the legacy driver is too old to work with Steam
23:58phoenixz: Someday hell will freeze over and nvidia will help out with great open source drivers.. oh well, one day..