04:32ilios: Hi. I heard that GPU instruction cache can be flushed by specific MMIO. But i couldn't find that in any nouveau documents. Where can i get the information about such specific MMIO address? My GPU is NVIDIA GTX480.
04:42karolherbst: ilios: check rnndb
04:45ilios: Thx for suggestion
04:56ilios: i found suspicious code from envytools/envydis/gf100.c. N("ivall") within struct insn tabcctlop. Does anyone know about this code piece? How is it related with flushing inst cache?
04:56ilios: What i want to do is just flushing instruction cache using MMIO.
04:57pmoreau: ilios: Have a look at rnndb, as Karol suggested
04:58pmoreau: rnndb is the database containing all RE'ed MMIO regs + some more stuff
04:58ilios: Could you give me a tip for looking at rnndb? Actually i tried that at before. grep any cache flush-related code in rnndb folder. but i couldn't grab any information..
05:01pmoreau: grep -rnI FLUSH returns a couple of results, just need to check which one might be related to instruction cache
05:03ilios: Oh thank you! Let me try them.
05:03pmoreau: docs/hw might contain some information as well
05:07RSpliet: ilios: I'd be surprised if you find stuff about flushing your icache in "envydis", given how I don't think you want the compute cores to do that
05:07RSpliet: gnurou: or were there intentions of self-modifying code? :-D
05:10mwk: ilios: you won't find anything in envydis, the ivall stuff is only for flushing global space
05:10mwk: and maybe surfaces
05:10ilios: My intention is little bit complex to explain (because of my poor english skill),but it is for the security reason. I'm working on research related to security of GPU. And i want to do something like "flush instruction cache and fetch everything newly" at right time.
05:11mwk: there are two ways to trigger a flush
05:11mwk: one is by using the command stream, the same one that was used to launch the compute kernel in the first place
05:11mwk: but that only works for flushing the cache in between kernels
05:11mwk: the second is, indeed, MMIO
05:12mwk: which is used eg. for cuda-gdb
05:12ilios: First option is not appropriate for me
05:12ilios: Yes, second one is really what i want.
05:12mwk: and for that, you need to poke some triggers in PGRAPH's register range
05:13mwk: I'm not certain if I've found all of them
05:13ilios: Ah! Thankyou so much. If i'm using GTX480, rnndb/graph/gf100_pgraph is right place to search?
05:13ilios: Thank you!
05:13mwk: look for flush triggers
05:14mwk: there are a few, you'll likely need to poke all of them to flush all levels of all caches
05:16ilios: Ah i see. another quick question. Do you know how harsh(?) is the flushing cache operation in terms of latency?
05:16ilios: i need to flush all levels of instruction cache.
05:19ilios: or Is there any way to know the exact time when the flushing operation finished?
05:22RSpliet: ilios: I'd expect the cost of a flush to be relatively low for icache (no writeback ops required), but refilling to take a lot of time
05:24ilios: I see. Is there any document about internal refilling process in GPUs? i mean there must be some kind of prefetching mechanism, but i'm curious how large the size of instructions prefetched at one time.
05:29pmoreau: I guess GPU manufacturers aren't really talkative about that kind of information? Try to search in the documentation released by Intel or AMD, or search for some papers that RE'ed that process.
05:32ilios: Ah okay, i think so. Thank you!
05:43ilios: mwk, can i get more information about first option?(trigger a flush using the command stream). What is the purpose of that mmio? is it only flush the cache or including the initiation of uploaded kernel, or even including the uploading process?
05:44ilios: Anyway, I want to test that MMIO too. where is the right place to find?