05:45 mlankhorst: imirkin_: you can use the debugfs patches for getting a dump of the state kernel sees vs state userspace sees
05:46 mlankhorst: I show flink name there too
05:47 mlankhorst: but I think what happens is the pushbuf has the same buffer twice on the pushbuf list with the same name and everything..
05:53 mlankhorst: imirkin_: could that be fixed by patching up the kernel perhaps? ignore duplicate items on the pushbuf list. :P
05:55 mlankhorst: I see no reason for it to be an error, tbh
08:50 imirkin_: mlankhorst: you greatly overestimate my willingness to reboot :)
09:01 mlankhorst: imirkin_: looks like it would work for any code without relocations
09:01 mlankhorst: which I guess is nv50+?
09:03 imirkin_: well
09:03 imirkin_: this is clearly related to external bo's
09:03 imirkin_: i bet you messed up the name copying somewhere or something
09:11 imirkin_: gnurou: out of curiousity, where are you guys at with the X1 on nouveau bringup? have you gotten to mesa?
09:16 mlankhorst: imirkin_: just for giggles remove the einval, and add it to previous write/read/valid domains. :P
09:17 imirkin_: skeggsb_ has been sadly silent on the issue =/
09:19 mlankhorst: have you tried dumping all the bo's on the list of the failing ioctl? see if something appears twice..
09:19 imirkin_: i dump the list both before and after ioctl (on userpsace end)
09:20 imirkin_: [and no, no dups]
09:20 mlankhorst: ok in that case you want to grab my old debugfs patches
09:20 imirkin_: it always complains about the last buffer in the list
09:20 mlankhorst: see what kernel thinks of the list
09:20 imirkin_: and it only happens when i move the vdpau window
09:20 imirkin_: (not when it is initially created, curiously enough)
09:20 imirkin_: which i assume means some sort of frontbuffer shenanigans
09:21 imirkin_: windowmaker also likes to do xpause or whatever when it moves windows around
09:22 mlankhorst: http://cgit.freedesktop.org/~mlankhorst/linux/log/ 'add guard pages' and 'nouveau debugfs stuff'
09:22 imirkin_: XGrabServer i think
09:23 mlankhorst: it will give the entire list of bo's for all currently running clients
09:23 mlankhorst: exactly what you would need here..
09:23 imirkin_: i'll think about it... should probably update too
09:23 imirkin_: i'm on 3.17 on that box
09:30 mlankhorst: ah right
09:31 imirkin_: this is my desktop, with a bunch of cheap-o spinning disks
09:31 imirkin_: so i try to avoid rebooting :)
09:31 imirkin_: i've already had to replace 3/4 disks, and now they're no longer under warranty
09:42 mlankhorst: kexec ;-)
09:43 imirkin_: a little too advanced for me... besides the #1 cause for reboot is some sort of gpu fail
09:44 imirkin_: i've come to like doing dev on the adreno boards -- with nfsroot, they're basically stateless
09:44 mlankhorst: yeah I like nfsroot
09:45 mlankhorst: 'enter v' (macro that sets up chroot), make some adjustments in the chroot, done!
09:46 imirkin_: also the gpu hang recovery in freedreno is way better ;)
09:46 imirkin_: only once was i able to destroy it
09:50 mlankhorst: heh :p
09:57 mlankhorst: literally destroy?
09:58 imirkin_: no
09:58 imirkin_: but required reboot
10:00 mlankhorst: too many things with nouveau tbh
10:00 imirkin_: hm?
10:01 mlankhorst: that can crash
10:01 mlankhorst: I think I tried a hack to make nouveau ddx with glamor work on the k1, no luck either..
10:02 imirkin_: there's an issue in the nouveau glamor integration
10:02 imirkin_: among other things, GLX_ARB_create_context_profile doesn't get exposed
10:03 mlankhorst: yeah but come on I would at least expect a different failure mode
10:03 mlankhorst: had the same type of error messages in dmesg
10:04 imirkin_: right
10:04 mlankhorst: so I guess running a full xserver exposed some bugs that would otherwise be a lot harder to trigger
10:05 imirkin_: i'm guessing you have a compositor though
10:05 imirkin_: i don't
12:13 mupuf: finally had a look at nvidia's reg dump
12:13 mupuf: looks like I found there the master enable bits for power and clock gating!
12:13 mupuf: finally!
12:13 mupuf: and I am also intriged by this PLL-based slowdown
12:27 mupuf: clock gating enabled: 11W, clock gating disabled: 20W
12:28 imirkin_: should keep it enabled then
12:28 mupuf: imirkin_: should enable on nouveau you mean?
12:28 imirkin_: yeah
12:28 imirkin_: it's all the JOE registers right?
12:29 mupuf: well, sure, but I was missing the one ENABLE bit
12:29 mupuf: and JOEs are gone
12:29 mupuf: I renamed them with their nvidia names
12:29 imirkin_: oh ok
12:29 mupuf: and added a ton of them
12:30 imirkin_: goodbye joe :(
12:30 mupuf: ELPG, SLCG, BLCG
12:30 mupuf: Not sure what SLCG means though
12:30 imirkin_: any thoughts on what they mean?
12:30 imirkin_: CG = clock gating
12:30 mupuf: Engine-level power gating
12:30 mupuf: S-level CG
12:30 mupuf: and Block-level
12:30 imirkin_: hm
12:30 imirkin_: is S under or above block?
12:31 mupuf: well, usually, blocks have ELPG, SLCG and BLCG
12:31 mupuf: so, not sure if the names are logical at all
12:31 imirkin_: ok :)
12:31 imirkin_: block is container for engine?
12:32 mupuf: unless they specify when to send a signal to ELPG and SLCG
12:32 mupuf: which is also very probable
12:32 imirkin_: could be
12:32 mupuf: nope, a block is a transistor block
12:32 mupuf: a unit that does work on its own
12:32 imirkin_: and an engine is...
12:32 mupuf: like, zculling
12:32 imirkin_: ok, so an engine has multiple blocks
12:33 mupuf: a freaking big block :D
12:33 imirkin_: that's what i sort of assumed
12:33 imirkin_: zculling is still pretty big
12:33 imirkin_: dunno
12:33 mupuf: it is!
12:33 mupuf: but it is not programmable
12:33 mupuf: wait, no
12:33 mupuf: it has no context
12:33 imirkin_: ok
12:34 mupuf: that's what we use to distinguish between a subdev and engine, in nouveau
12:48 mupuf: oh, seems like I had already documented this reg
12:49 mupuf: that's what 1 year do to your memory I guess
12:49 mupuf: anyway, let's go back to traces
12:49 imirkin_: weren't you going to look at the fan situation?
12:49 imirkin_: or is that fixed now?
12:56 mupuf: not fixed
12:57 mupuf: and it really is not motivating me,,,
12:57 imirkin_: :(
12:57 mupuf: I guess I should just fire an email to nvidia
12:57 imirkin_: so what's the right move? revert your patch?
12:57 mupuf: good question
12:58 mupuf: most GPUs work, it would seem
12:58 imirkin_: right
12:58 imirkin_: what did that patch fix?
12:58 mupuf: the right move is fixing it
12:59 imirkin_: well, given that you're not going to do it
12:59 mupuf: it added fan management :D
12:59 imirkin_: hrmph
12:59 imirkin_: is it easily disableable? e.g. NvFan=0 or something
12:59 mupuf: nope, could be an option
12:59 mupuf: or I could add a hack
12:59 imirkin_: hack sounds good
12:59 imirkin_: i like hack
13:00 mupuf: I mean, it is kind of easy to detect when there is this weird divider
13:00 mupuf: but I wonder if this divider is fixed or not
13:00 imirkin_: what's weird about it?
13:00 mupuf: I can't find it
13:00 imirkin_: is it negative perhaps? :)
13:00 mupuf: ?
13:00 imirkin_: [the divider]
13:00 mupuf: negative divider?
13:01 imirkin_: yes
13:01 imirkin_: isn't the issue that it's all inverted?
13:01 mupuf: not sure what it would mean ;D
13:01 mupuf: oh, no
13:01 mupuf: that;s not the issue
13:01 mupuf: that, we already know how to detect
13:01 imirkin_: oh ok
13:01 imirkin_: but that wasn't enough to fix people?
13:01 mupuf: we had support for that since day 0
13:02 mupuf: as in, 3 years ago
13:02 mupuf: the problem is the following
13:02 mupuf: do you remember that the fan is driven by a PWM controller?
13:03 mupuf: we can compute the number of cycles to reach the right PWM frequency
13:03 imirkin_: PWM has both frequency and duty cycle...
13:03 mupuf: and then, you are supposed to vary the duty between 0 and this value to vary the power to the fan between 0 and 100%
13:04 imirkin_: ok
13:04 imirkin_: that makes sense
13:04 imirkin_: the frequency on the pwm seems like it should just be fixed to whatever the fan wants
13:04 mupuf: on the weird fans, you are supposed to do it between 0 and frequency/20 or something like that
13:04 imirkin_: "it"?
13:05 mupuf: yep, and we do that well
13:05 mupuf: vary the duty between 0 and frequency/20 (or another abritrary constant)
13:05 imirkin_: uhm
13:05 mupuf: but one that does not make a lot of sense in hw because it is hard to do
13:05 imirkin_: that's dumb
13:05 imirkin_: frequency in what units
13:06 mupuf: clock cycles
13:06 imirkin_: i would actually expect it's something more like the you're expected to vary frequency as well
13:06 mupuf: I don't get why the fuck someone would want to not use the full range!
13:06 imirkin_: because the pwm actually drives the electromagnet directly or something
13:06 mupuf: nope, the frequency is fixed
13:06 imirkin_: hmm
13:06 mupuf: it has to be
13:06 mupuf: you can do everything with the duty
13:06 imirkin_: depends what it's driving :p
13:07 imirkin_: if it's driving power on/off -- sure
13:07 imirkin_: but think about how fans actually work
13:07 imirkin_: (or rather, motors)
13:07 mupuf: a dc motor works like that
13:07 mupuf: you just turn it on or off very fast
13:07 mupuf: a brushless motor cannot be driven with only one output
13:08 imirkin_: hm ok
13:08 imirkin_: reading up about it
13:08 imirkin_: i haven't thought about this since like elemetary school
13:08 mupuf: and all the fans have the driving circuit with them
13:08 mupuf: elementary school? WTH :D
13:08 imirkin_: i moved to software after that :p
13:09 mupuf: I only got interested about them when I moved to using electric motors for my models
13:09 imirkin_: so for brushless, wikipedia says: A motor controller converts DC to AC.
13:09 mupuf:had a 2.5cc IC engine :D
13:09 imirkin_: The motor controller can sense the rotor's position via Hall effect sensors or similar and precisely control the timing, phase, etc., of the current in the rotor coils to optimize torque, conserve power, regulate speed, and even apply some braking.
13:10 mupuf: exactly
13:10 imirkin_: so... if you're supposed to be the motor controller
13:10 imirkin_: then you have to be able to vary all that stuff :)
13:10 mupuf: there are 3 phases
13:11 mupuf: and the driver can't react fast enough to read the hall effect sensor
13:11 mupuf: well, nouveau does it on some cards, when someone asks for the RPM
13:11 imirkin_: hehe
13:11 mupuf: until a hw poller got introduced in nvd9 IIRC
13:12 mupuf: nva* actually
13:12 mupuf: yeah, pretty sure it was a3
13:12 mupuf: I do not believe it is the job of the chipset to do that anyway
13:13 mupuf: any speed regulator takes a pwm value as an input
13:13 mupuf: unless it is really fancy and it also supports i2c
13:14 mupuf: so, I really thought it was a parameter of the PWM controller that I missed, somewhere
13:14 mupuf: but first, why would it exist
13:14 mupuf: that only means castrating the accuracy
13:14 imirkin_: just send the question to the black hole
13:15 imirkin_: who knows, you might get some hawking radiation back out
13:15 mupuf: I was about to say that there was some info going out sometimes :D
13:15 mupuf: out of black holes, I meant
13:15 imirkin_: hehe
13:15 mupuf: nvidia too :D
13:16 mupuf: I would have loved to have a look at the actual waveform of the GPIO
13:16 mupuf: but ... I did not have enough room to bring back my osciloscope from france
13:16 imirkin_: you had a scope? how fast?
13:16 mupuf: 100 MHz
13:17 imirkin_: wow, not bad
13:17 mupuf: 10M samples
13:17 mupuf: I know!
13:17 imirkin_: a bit shy of the 20GHz scopes that the cool kids have, but wtvr
13:17 mupuf: have you seen the mixed domains ones?
13:17 mupuf: radio + electrical
13:18 mupuf: and the bw of the sw radio is incredible!
13:20 mupuf: http://www.tek.com/oscilloscope/mixed-signal-oscilloscope
13:21 imirkin_: heh
13:21 imirkin_: "so expensive that you have to request a quote in order for us to tell you the price"
13:22 mupuf: yep
13:22 buhman: wow
13:22 buhman: pci express
13:23 mupuf: buhman: hehe
13:24 imirkin_: DP is pretty nice too
13:24 mupuf: but how am I supposed to check the latency between the moment a transmission arrives at the antenna and when it is actually sent to the pcie bus
13:24 imirkin_: 5.4GHz lane speed or something like that...
13:24 imirkin_: maybe it was 5.4Gbit
13:24 mupuf: probably
13:24 mupuf: but still :)
14:27 mupuf: 100d78: cafebeef cafebeef cafebeef <-- that's unusual
19:33 imirkin: nouveau E[supertuxkart[6026]] push 1 buffer not in list
19:33 imirkin: thoughts?
19:33 imirkin: happens with both libdrm 2.4.60 and 2.4.59
19:33 imirkin: so mlankhorst is off the hook on this one
19:42 imirkin: this is the printed info: http://hastebin.com/raw/vuyowucizu
19:51 imirkin: p krec->push
19:51 imirkin: $11 = {{bo_index = 0, pad = 0, offset = 296900, length = 85584}, {bo_index = 1717533677, pad = 0, offset = 0, length = 8388628},
19:51 imirkin: and it goes on... weird