00:02 sarbes: If I had the time...
00:03 sarbes: But I have some coming up.
00:03 sarbes: Thanks for confirming.
00:13 anarsoul: OK, I'm bisecting it
00:13 anarsoul: shouldn't take longer than 15mins, it's only 11 steps
00:14 anarsoul: 40497ca3a907e734b2dab95c83540bb7bfec14dc is good
00:21 anarsoul: it sounds like it's a bug in printing the shader though, because it's compiled just fine
00:26 anarsoul: 7b70b419b5282fb01b7202e5ee1d391fcba15ef8 is the first bad commit
00:39 anarsoul: yeah, reindexing SSAs fucks up the registers :)
00:40 anarsoul: likely a bug in ppir_add_write_after_read_deps()
00:45 anarsoul: nah, it's a bug in translation
00:46 anarsoul: I vaguely remember that ppir expect regs indices to start after all SSA indices
01:15 anarsoul: sarbes: that should fix it: https://gist.github.com/anarsoul/4a46dde6033467951bfbeafca8dbb2a3
01:16 anarsoul: I only tested it with shaders/chromeos/24.shader_test
01:18 anarsoul: nah, it's actually wrong
01:18 anarsoul: we need to shift SSAs instead
01:19 anarsoul: well, you've got the idea, so I bet you can fix it :)
01:19 anarsoul: the problem is the way we are tracking writes to individual channels of the registers. There might be up to 4 nodes, while an SSA is always 1
01:21 anarsoul: so comp->var_nodes size is x4 of number of nir defs
01:22 anarsoul: we need to do the math properly when fetching a node for SSA or for the register
01:23 anarsoul: currently it's broken. It was kind of relying on nir defs indices for reg definitions to start after all the SSA indices
21:04 anarsoul: sarbes: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36206