09:48 joobei: sry got disconnected. I hope I didn't miss a reply.
11:53 memleak: is it possible someone can unflag my email as spam?
11:54 memleak: also the radeon driver makes my desktop act crazy so i have to use the amdgpu driver.
11:55 memleak: icons,menus and windows flicker
11:55 memleak: i honestly thought my gpu was dying for a second when i did a fresh install of fedora or even ran it off the live cd
18:19 karolherbst: do we have an opt that eliminates pointless `iands` around address offsets? Like 2 byte shared load having an `(iand offset 0xfffffffe)` offset?
18:24 glehmann: no, and it wouldn't be valid in NIR I think
18:25 glehmann: unless you do it for your backend intrinsics of course
18:34 karolherbst: mhh right...
18:35 karolherbst: glehmann: but what if it's aligned? Like iand %5043, %5045 (0xfffffffe) + @store_shared (%5044, %5046) (base=0, access=none, wrmask=x, align_mul=16, align_offset=0)
18:36 glehmann: then you cause UB when the alignment info is no longer correct
18:36 karolherbst: I have this weird shader where this iand is only on component 0, and then 1 has %5043 + 2
18:36 karolherbst: okay.. but doesn't align_mul mean that the address is 16 byte aligned here?
18:37 karolherbst: ohhh wait...
18:37 karolherbst: duh
18:37 karolherbst: mhhhhh
18:37 karolherbst: I hate this now
18:38 karolherbst: the shader does "32 %5048 = iadd %4466 (0x2), %5043 + @store_shared (%5081, %5048) (base=0, access=none, wrmask=abcde, align_mul=16, align_offset=2)" later so that's "fun"
18:38 karolherbst: and it messes up load store vectorization...
18:38 karolherbst: :'(
18:39 karolherbst: like due to the second store, I _know_ that %5043 is properly vectorized
18:39 karolherbst: ehh
18:39 karolherbst: aligned
18:39 karolherbst: because it has to be for the second store
18:39 karolherbst: ... I have a cursed idea for a pass, brb
18:40 karolherbst: I wonder if we can uub this...
18:40 karolherbst: or whatever would be appropiate here
18:42 karolherbst: and if I really should..
18:42 karolherbst: it feels illegal to make assumptions based on other stores on the alignment from a previous one, but that shader would hit UB later if it's invalid, so I _think_ it should be fine, no?
18:43 karolherbst: like on nvidia, if the second shared hits an unaligned address, then the first one's store would be overwritten anyway, mhhh
18:43 karolherbst: in either case it doesn't change the behavior except I can vectorize
18:49 karolherbst: I wonder where that `iand` is coming from... maybe I can get rid of it earlier
18:59 glehmann: karolherbst: does https://gitlab.freedesktop.org/DadSchoorse/mesa/-/commits/nir-skip-more-align help?
19:03 karolherbst: glehmann... yes, quite a lot
19:03 karolherbst: 4564 -> 3913 instructions in the shader I'm looking at
19:03 karolherbst: and yeah
19:03 karolherbst: it all gets properly vectorized now
19:04 karolherbst: glehmann: you should have access to the shader in case you want to take a deeper look
19:04 karolherbst: could tell which one it is
19:04 karolherbst: but not sure if radv hits the same issue or not
19:11 glehmann: the same case can probably happen on radv, but almost all IO is dword based so it doesn't hit anything in our shader collection
19:11 karolherbst: ahh...
19:12 karolherbst: yeah, let me run your MR on nvk, because I've had 39 shaders that were impacting by trying to fix up our vectorizer and I found this issue there
19:13 karolherbst: I was battling the vectorizer creating vec5s :')