03:32 mareko: karolherbst: any alignment requirements?
04:18 zzyiwei: Can anyone help review this win32 wsi fix? https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40557 This is to respect acquire timeout on non-DXGI sw wsi path. CI is passing and the fix has been verified by issue reporter already.
05:36 RAOF: Has anyone run into a weird problem when importing (linear) dmabufs from i915 to nvidia have the wrong stride unless the width is a multiple of 8?
05:55 zzyiwei: RAOF: this can be similar https://gitlab.freedesktop.org/virgl/virglrenderer/-/issues/651. In our case, the image stride in the prime blit buffer has to be aligned no more than 32bytes, otherwise distorted. The default 256 alignment isn't respected.
05:56 zzyiwei: Here's the NV side ticket filed by ifaigios: https://forums.developer.nvidia.com/t/egl-import-via-egl-ext-image-dma-buf-import-modifiers-ignores-explicit-stride-causes-image-distortion-in-virtio-gpu-venus/364360
05:57 RAOF: Interestingly this works for importing from amdgpu, but that _might_ just be because amdgpu allocates with a sufficiently aligned stride anyway?
06:42 MoeIcenowy: https://gitlab.freedesktop.org/imagination/mesa/-/issues/18 when testing Zink on PowerVR, many ES CTS failures disappeared when I set MESA_GLES_VERSION_OVERRIDE=3.0
06:43 MoeIcenowy: should I fix these situations in state tracker / Zink ?
08:28 MrCooper: RAOF: yeah, amdgpu aligns stride to a multiple of 256 bytes, Intel iGPUs have much lower constraints
10:23 mripard: tzimmermann: I'd like to merge https://lore.kernel.org/r/20260305-drm-rework-color-formats-v3-0-f3935f6db579@kernel.org today, ok for you?
10:24 tzimmermann: mripard, sure. np