10:01 Ermine: Venemo: are you talking about this: https://lore.kernel.org/amd-gfx/20180904010033.67611-1-bas@basnieuwenhuizen.nl/ ? Everything newer seems to refer to gfx9+ modifiers
14:36 Venemo: Ermine: yes, that
15:12 Ermine: thank you. It seems that most of the work is to come to an agreement which modifiers will make it into drm_fourcc.h and how they will relate to those tiling mode tables
15:24 soreau: Mangix: I think zink works without modifiers for the common client but they are needed to run (wayland) compositors with zink
15:32 MrCooper: yeah, Vulkan doesn't allow importing BOs without modifiers
16:11 soreau: MrCooper: it used to work, I could run wayfire with drm backend using invalid with zink
16:12 soreau: but then zmike and resons :P
16:13 MrCooper: I could only see it work by either using driver-specific kernel functionality to determine the actual modifier, or by just assuming a modifier
16:17 soreau: idk but the only trick was things like xwayland, and I patched mesa to make that work, but it was wrong apparently
16:17 soreau: glxgears
16:17 Venemo: Ermine: I am going to need to review the code again to see which tiling formats are actually used in practice, and then see if those are covered by Bas's patches, and if so, convince upstream to accept it
16:18 Venemo: in practice, there are only a handful of formats that are ever used and they are very unlikely to change
16:45 Ermine: I guess by used you mean "used on later generations"?
16:46 Venemo: Ermine: no, I mean used on those old generations
16:47 Venemo: Ermine: please read the summary here: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5882#note_3238178
16:49 Venemo: those chips can only use up to 48 different formats at a time. the actual formats are hardcoded in the kernel depending on the chip and the memory configuration
16:49 Ermine: I did read it multiple times
16:50 Venemo: right, then you can see that even though the amount of formats that can be encoded is astronomical, there is only a small handful of those which are used in practice
16:54 Ermine: I mean, if none of those are exposed to userspace (as per drm_info output, at least), userspace can't use them, right?
16:55 Venemo: wdym by "none of those", none of what?
16:59 Venemo: it works like this: the kernel configures the tiling table with up to 48 different tiling formats. then userspace queries what those are and selects which one is most optimal for any given use case
17:00 Venemo: what the 48 formats are, depend on the chip and memory config
17:00 Ermine: ah, so these formats are not exposed as DRM format modifiers currently (I meant them in "none of those")?
17:04 Venemo: DRM format modifiers are not supported on those gpus at all
17:05 Venemo: there is a uapi for querying the tiling table and the relevant registers
17:10 Ermine: I see now
17:22 Venemo: the main difficulty here is that because the available formats are different between each chip, that could cause problems when sharing buffers between different chips (or even, same chip with a different memory config)
18:43 Ermine: Okay, so do I understand correctly that userspace selects tiling format with DRM_IOCTL_AMDGPU_GEM_METADATA ioctl?
18:44 Ermine: I so, I can patch the ioctl to dump requested tiling format, and you'll have some data
18:57 Venemo: Ermine: like what data?
18:58 Venemo: I don't think you need to patch that or at least I don't see what you would achieve
18:59 Ermine: We could know which formats were requested by apps running on my system
19:35 Venemo: We already know which 32 or 48 formats are used for every chip