02:32 mareko: ac_surface_get_pitch_align also has the pitch alignment formula for gfx6-8, so the only missing thing is to figure out height alignment and you can allocate modifier images without addrlib in theory
03:07 kode54: neat
04:38 soreau: mareko: are you saying there are no changes that would need to be made to the kernel to implement modifier support for GFX6-8 and it's just in mesa?
04:41 soreau: I see drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c uses GB_TILE_MODE0, GB_MACROTILE_MODE0 and GB_ADDR_CONFIG at least
05:01 mareko: soreau: the kernel would have to expose modifiers for gfx6-8 and translate those to existing tiling modes for the display code
05:03 soreau: hence the fourcc bits..
05:03 soreau: mareko: where does i.e. gfx9 expose modifiers?
05:04 mareko: soreau: search for AMD_FMT_MOD_SET
05:04 mareko: somewhere in DAL
05:06 mareko: I don't think that is used by gfx6-7 though
05:06 mareko: calling it "gfx" isn't right because the display block isn't called gfx
05:11 soreau: so needs changes in drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c and drivers/gpu/drm/amd/amdgpu/amdgpu_display.c ?
05:12 mareko: most likely
05:12 mareko: you can probably pass GL/VK modifier tests without it
05:41 soreau: and I guess GFX8 supports up to 64bpp?
06:05 soreau: is this headed in a good direction? http://ix.io/4HCU
06:07 soreau: it's using the GFX9 paths where unsure of what needs to happen
15:18 mareko: soreau: all modifier bitfields should come from GB_TILE_MODE0, GB_MACROTILE_MODE0 and GB_ADDR_CONFIG other than TILE_VERSION
15:18 soreau: ok, let's see
15:20 soreau: so I need to set TILE, TILE_MODE, PIPE_XOR_BITS and BANK_XOR_BITS?
15:27 MrCooper: wasn't there an issue with older gens where they could end up using different tiling even with the same values for these, e.g. depending on the HW memory configuration?
15:27 mareko: soreau: I think TILE_VERSION is the only existing field that will be used
15:28 soreau: mareko: oh hm
15:28 agd5f: MrCooper, yeah, the alignment depends on the number of pipes IIRC
15:28 agd5f: or the number of memory channels
15:29 soreau: oh yea, I meant s/TILE_MODE/TILE_VERSION/
15:29 mareko: MrCooper: HW memory configuration is already expressed in those 3 registers
15:29 agd5f: The macro tile size varies based on the number of channels IIRC
15:30 agd5f: so even if the registers are set the same the layout may not be compatible across 2 GPUs with different memory configs
15:31 soreau: so I have add_gfx8_modifiers() {add_modifier(mods, size, capacity, AMD_FMT_MOD | AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX8));}
15:32 MrCooper: agd5f: and that difference isn't reflected in any other register(s)?
15:32 mareko: the layout is determined by those 3 registers
15:32 mareko: nothing else
15:36 mareko: they are different for each memory configuration
15:49 soreau: mareko: so do I need to call add_modifier(mods, size, capacity, AMD_FMT_MOD | AMD_FMT_MOD_SET(TILE_VERSION, with GB_TILE_MODE0, GB_MACROTILE_MODE0 and GB_ADDR_CONFIG or'ed together, or one on each call or what?
15:53 soreau: or AMD_FMT_MOD_TILE_VER_GFX8, and what would that value be? (I #defined it to 0 in drm_fourcc.h)
15:56 soreau: or, call add_modifier(mods, size, capacity, AMD_FMT_MOD | AMD_FMT_MOD_SET(GB_TILE_MODE0, AMD_FMT_MOD_TILE_VER_GFX8); for each you outlined
15:57 agd5f: you probably need a number of memory channel parameter as well
16:05 agd5f: mmMC_ARB_RAMCFG and mmMC_SHARED_CHMAP or adev->gmc.vram_width
16:05 agd5f: look at whatever addrlib does
18:13 mareko: addrlib consumes the value of MC_ARB_RAMCFG, but doesn't seem to use it
18:15 bnieuwenhuizen: yeah there are a whole bunch of bits consumed but not used
18:16 mareko: in gfx6-8, the memory channel config is actually set in the GB_TILE_MODEn itself
18:16 mareko: in gfx9 and later, it's set in GB_ADDR_CONFIG