08:02 fdobridge: <k​arolherbst🐧🦀> I need KHR_shader_float_controls in nvk now 😄
18:36 benjaminl: alright I have a weird sm50 puzzle
18:38 benjaminl: this works: `SHF.L.W R0, 0x2, RZ`, and this works: `MOV32I R1, 0x2; SHL.W R1, R2, R1`, but this does not: `MOV32I R1, 0x2; SHF.L.W R0, R0, R1, Rz`
18:39 benjaminl: the last version writes 0 to R0, no matter what the initial contents are
18:40 benjaminl: NAK always emits `SHF.L.W` with `RZ` in the last src, so I'm thinking of just sticking a translation to `SHL.W` in the SM50 legalization pass for now
19:02 karolherbst: benjaminl: might be that it works a bit different on sm50
19:05 benjaminl: yeah, I've validated the encoding I
19:05 benjaminl: *I'm using with nvdisasm
19:06 benjaminl: but haven't gotten ptxas to emit the instruction with register arguments
19:09 fdobridge: <m​henning> nvdisasm sometimes disassembles things that the hardware ignores
19:09 fdobridge: <m​henning> src/nouveau/codegen/nv50_ir_lowering_nvc0.cpp line 268 has the old compiler's lowering of 64-bit shifts, if that's useful
19:10 fdobridge: <m​henning> that lowering is used for kepler through pascal. volta+ can't use the same lowering (I think because instruction semantics are different?)
19:11 benjaminl: ooh, that's a good reference, thanks!
19:12 benjaminl: also, just got ptxas to emit the instruction with the same encoding (the only difference is register assignments)
19:14 benjaminl: does ptxas also sometimes emit non-working code?
19:21 fdobridge: <k​arolherbst🐧🦀> yes
19:21 fdobridge: <k​arolherbst🐧🦀> but only if you use deprecated features which might just not work anymore
19:31 fdobridge: <m​henning> I just realized the old compiler is a little confusing here - what it calls OP_SHL is emitted as SHF.L if the source is 64-bits. See src/nouveau/codegen/nv50_ir_emit_gm107.cpp line 3559
19:34 fdobridge: <m​henning> also if you want to just get things working for now, you could turn on the nir lowering, which uses normal shifts but will be a little less efficient