00:00 fdobridge: <k​arolherbst🐧🦀> and a pipe is essentially a fifo
00:00 fdobridge: <k​arolherbst🐧🦀> never really thought about how one could implement it, but that inc/dec nvidia has really would come in handy
00:01 fdobridge: <k​arolherbst🐧🦀> as it's essentially a ring buffer indeed
00:01 fdobridge: <k​arolherbst🐧🦀> wondering if cuda has something like that
00:02 fdobridge: <k​arolherbst🐧🦀> funky
00:22 fdobridge: <g​fxstrand> It still seems kinda pointless when you could just make it a power of two. 🤷🏻‍♀️
00:22 fdobridge: <k​arolherbst🐧🦀> sure, but CL pipes have custom sizes handed in by the application :3
00:25 fdobridge: <k​arolherbst🐧🦀> anyway.. at least it allows you to get rid of some and instructions even with pot values
00:28 fdobridge: <g​fxstrand> You should be able to round up to a power of two. But, yeah...
03:01 fdobridge: <g​fxstrand> `Pass: 307186, Fail: 4765, Crash: 1525, Skip: 1673845, Flake: 54, Duration: 1:22:59`
13:28 fdobridge: <g​fxstrand> @Mr Fall🐧 So, this reclocking stuff you were talking about last week with the firmware juggling... Is it all theoretical or do you have patches somewhere? I'd really like to be able to demo stuff at the meetup in 1.5 weeks. I don't need something clean, just something that works well enough.
13:29 fdobridge: <g​fxstrand> @Mr Fall🐧 So, this reclocking stuff you were talking about last week with the firmware juggling... Is it all theoretical or do you have patches somewhere? I'd really like to be able to demo stuff at the meetup in 1.5 weeks. I don't need something clean and upstreamable, just something that works well enough. (edited)
13:29 fdobridge: <k​arolherbst🐧🦀> let me figure it out on the weekend and I'll throw something at you
13:30 fdobridge: <g​fxstrand> Cool. Thanks!
13:42 fdobridge: <!​[NVK Whacker] Echo (she) 🇱🇹> Could it be possible to do it on Turing too? 😅
13:44 fdobridge: <k​arolherbst🐧🦀> with GSP
13:44 fdobridge: <k​arolherbst🐧🦀> though I'm not quite sure... does reclocking already work on the GSP branches?
13:49 fdobridge: <!​[NVK Whacker] Echo (she) 🇱🇹> `fail ttm_validate` is a big showstopper 🐸
13:50 fdobridge: <g​fxstrand> Then we need to fix that
13:50 fdobridge: <g​fxstrand> I mean, if the hacks work on turning, may as well, but long-term we want GSP.
13:51 fdobridge: <k​arolherbst🐧🦀> they don't
13:51 fdobridge: <k​arolherbst🐧🦀> 1. turing is different 2. turing has gddr6
13:52 fdobridge: <!​[NVK Whacker] Echo (she) 🇱🇹> Airlie said that GSP consumes a lot of memory (but I only use half of my VRAM when running a pretty intensive game with GSP on NVIDIA driver)
13:55 fdobridge: <!​[NVK Whacker] Echo (she) 🇱🇹> BTW why does the new nouveau kernel API require changes outside of drm/nouveau? 🍩
14:00 fdobridge: <g​fxstrand> I think it's because @airlied is also trying to build some common infrastructure for page table management so that other drivers can get competent uAPIs as well.
15:48 fdobridge: <g​fxstrand> I don't understand barriers....
15:49 fdobridge: <g​fxstrand> The good news is that it's no longer throwing ILLEGAL_PARAM
15:49 fdobridge: <k​arolherbst🐧🦀> what kind of barriers?
16:02 fdobridge: <g​fxstrand> barrier()
16:02 fdobridge: <g​fxstrand> I think I figured out what we were doing wrong
16:02 fdobridge: <g​fxstrand> Well, with that
16:03 fdobridge: <g​fxstrand> IDK why my shared memory tests still aren't passing
16:04 fdobridge: <k​arolherbst🐧🦀> soooo
16:04 fdobridge: <k​arolherbst🐧🦀> you probably know that, but I'll say it anyway: some instructions have to be executed with all threads converged
16:04 fdobridge: <k​arolherbst🐧🦀> barriers are one of those
16:04 fdobridge: <k​arolherbst🐧🦀> they don't work if not all threads aren't there yet
16:05 fdobridge: <k​arolherbst🐧🦀> if you have divergent control flow, you have to sync up the threads
16:06 fdobridge: <g​fxstrand> Yes
16:06 fdobridge: <g​fxstrand> Hrm...
16:06 fdobridge: <g​fxstrand> I"m not doing a warp sync
16:06 fdobridge: <g​fxstrand> Ugh
16:06 fdobridge: <k​arolherbst🐧🦀> not talking about warp sync tho
16:07 fdobridge: <k​arolherbst🐧🦀> well
16:07 fdobridge: <k​arolherbst🐧🦀> it's part of it
16:07 fdobridge: <k​arolherbst🐧🦀> but often not even needed
16:07 fdobridge: <k​arolherbst🐧🦀> have you wired up that barrier register file yet?
16:07 fdobridge: <k​arolherbst🐧🦀> B2R specifically
16:07 fdobridge: <g​fxstrand> no
16:07 fdobridge: <k​arolherbst🐧🦀> ehh not B2R
16:08 fdobridge: <k​arolherbst🐧🦀> BMOV
16:08 fdobridge: <k​arolherbst🐧🦀> `MACTIVE` is the mask of active threads and can be read from or written to
16:09 fdobridge: <k​arolherbst🐧🦀> otherwise you can only use warpsync outside of cfg
16:09 fdobridge: <k​arolherbst🐧🦀> as you wouldn't know what threads have to participate
16:11 fdobridge: <k​arolherbst🐧🦀> check `enum TSSemantic` for all the available things
16:12 fdobridge: <k​arolherbst🐧🦀> WARPSYNC will ignore exited threads tho
16:13 fdobridge: <g​fxstrand> This may be too big of a project for today. :0/
16:13 fdobridge: <g​fxstrand> This may be too big of a project for today. 😕 (edited)
16:18 fdobridge: <k​arolherbst🐧🦀> yeah.. I've still didn't done it fully for GL yet
16:18 fdobridge: <k​arolherbst🐧🦀> but I needed ti for some lowering partly
16:18 fdobridge: <k​arolherbst🐧🦀> texgrad on 3d
16:19 fdobridge: <g​fxstrand> As for the barrier register file, that shouldn't be hard. It's pretty easy to add files in NAK.
16:19 fdobridge: <g​fxstrand> The only real pain is that RegFile will go from 2 bits to 3 in a couple places.
16:19 fdobridge: <g​fxstrand> The only real pain is that `RegFile` will go from 2 bits to 3 in a couple places. (edited)
16:19 fdobridge: <k​arolherbst🐧🦀> https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11061
16:19 fdobridge:<g​fxstrand> wishes rust had bitfields some days
16:20 fdobridge: <k​arolherbst🐧🦀> anyway.. you have 16 general purpose barrier registers and 16 of those fixed ones and they live inside the same space
16:20 fdobridge: <g​fxstrand> kk
16:21 fdobridge: <g​fxstrand> That's a little anoying...
16:21 fdobridge: <g​fxstrand> But I think I can deal with it
16:21 fdobridge: <k​arolherbst🐧🦀> the special ones start at 16
16:21 fdobridge: <k​arolherbst🐧🦀> so 0-15: general purpose, 16-31: special ones
16:21 fdobridge: <g​fxstrand> That makes it a bit easier
16:25 fdobridge: <k​arolherbst🐧🦀> e.g. you force the shader to run in quads by doing a BMOV.PQUAD on MACTIVE with a value you usually read out from BMOV with MACTIVE
16:26 fdobridge: <k​arolherbst🐧🦀> BMOV B0, MACTIVE
16:26 fdobridge: <k​arolherbst🐧🦀> BMOV.PQUAD MACTIVE, B0
16:26 fdobridge: <k​arolherbst🐧🦀> ... code requiring quads
16:26 fdobridge: <k​arolherbst🐧🦀> BMOV MACTIVE, B0
16:27 fdobridge: <k​arolherbst🐧🦀> but I doubt you'll need this any time soon 🙂
16:28 fdobridge: <k​arolherbst🐧🦀> before volta the hardware managed the masks itself and you hade like QUADON/QUADPOP instructions doing it instead
16:28 fdobridge: <k​arolherbst🐧🦀> and other things to handle breaks/conts/whatever
16:31 fdobridge: <g​fxstrand> Are there docs on any of this?
16:31 fdobridge: <k​arolherbst🐧🦀> of course they aren't 🙂
16:31 fdobridge: <k​arolherbst🐧🦀> *there
16:31 fdobridge: <k​arolherbst🐧🦀> well
16:32 fdobridge: <k​arolherbst🐧🦀> at least nothing I could give to you 😄
16:32 fdobridge: <g​fxstrand> *grumble*
16:32 fdobridge: <k​arolherbst🐧🦀> but what I have isn't useful besides that anyway
16:32 fdobridge: <k​arolherbst🐧🦀> I know what PQUAD and MACTIVE does
16:32 fdobridge: <k​arolherbst🐧🦀> everything else I only got the names
16:33 fdobridge: <k​arolherbst🐧🦀> welll.. I know what WARPSYNC does and you can just use it with a 0xffffffff mask
16:33 fdobridge: <k​arolherbst🐧🦀> but... that won't work inside non uniform CFG
16:33 fdobridge: <k​arolherbst🐧🦀> if you sync the threads up outside of any CFG you'd be good for now
16:34 fdobridge: <k​arolherbst🐧🦀> @gfxstrand did you try using BAR.SYNC btw?
16:36 fdobridge: <k​arolherbst🐧🦀> though I have no idea if that works the same or differently.. mhh probably different
16:37 fdobridge: <k​arolherbst🐧🦀> there is also BSSY+BSYNC to set convergence points
16:37 fdobridge: <g​fxstrand> I'm using BAR.SYNC right now
16:38 fdobridge: <k​arolherbst🐧🦀> so you have a BSSY B0, $address_to_after_cfg, then some divergent control flow and then BSYNC B0
16:38 fdobridge: <k​arolherbst🐧🦀> and then the threads are converged
16:40 fdobridge: <k​arolherbst🐧🦀> the address argument on BSSY is ignored by the hardware tho, it's just useful for debuggers
16:40 fdobridge: <k​arolherbst🐧🦀> or general debugging
16:40 fdobridge: <g​fxstrand> Yeah, the trick is how to do it in uniform control-flow
16:41 fdobridge: <g​fxstrand> Seems like the Nvidia compiler falls back to just BAR.SYNC for that
16:41 fdobridge: <k​arolherbst🐧🦀> yeah.. probably
16:41 fdobridge: <g​fxstrand> I've been playing around with it a bit
16:41 fdobridge: <k​arolherbst🐧🦀> I'm not 100% on when it's actually needed and when BAR.SYNC is enough and stuff
16:41 fdobridge: <g​fxstrand> Yeah, I need to spend some time with it
16:41 fdobridge: <k​arolherbst🐧🦀> anyway, I tried to summarized on what I know on this and what we currently use it for
16:42 fdobridge: <g​fxstrand> Thanks
16:42 fdobridge: <k​arolherbst🐧🦀> that stuff is more solid pre volta and the general logic applies, it's just hardware stack managed instead of barrier registers
16:43 fdobridge: <k​arolherbst🐧🦀> funky is that you have an on-chip stack, but if that's not enough you can spill the stack to VRAM, but you have to know beforehand how much you need and stuff. Luckily Volta+ doesn't have that, but you have to deal with that barrier stuff 🙂
17:38 fdobridge: <m​henning> oh, that reminds me - I actually did some REing on kepler and I think I figured out how to size the hardware stack correctly... and then I never actually followed through with those patches to codegen
17:39 fdobridge: <m​henning> I forget if I broke something or just got distracted. maybe I should resurrect that branch
17:39 fdobridge: <k​arolherbst🐧🦀> the hardware stack is fixed in size
17:39 fdobridge: <k​arolherbst🐧🦀> what you can size is the software one
17:39 fdobridge: <k​arolherbst🐧🦀> and it's part of TLS
17:40 fdobridge: <m​henning> yeah I meant the spill space for the stack
17:40 fdobridge: <k​arolherbst🐧🦀> we actually have a game running out of space 😢
17:40 fdobridge: <k​arolherbst🐧🦀> so what nvidia does to combat the need of a big stack is to do loop merging
17:41 fdobridge: <m​henning> yeah I might have gone down a rabbit hole of trying to conserve stack slots
17:42 fdobridge: <k​arolherbst🐧🦀> I think I figured it out at some point as well, but codegen is annoying
17:42 fdobridge: <m​henning> eg. you only need one slot for a switch case, but nir lowers that to nested ifs that naively consume a bunch of slots, so I started dreaming up ways of backing that info out
17:43 fdobridge: <k​arolherbst🐧🦀> also being a multiple of 512b doesn't help
17:43 fdobridge: <k​arolherbst🐧🦀> or whatever the size was
17:43 fdobridge: <m​henning> yeah, codegen is super annoying
17:43 fdobridge: <k​arolherbst🐧🦀> could have an array with jump targets *hides*
17:44 fdobridge: <m​henning> haha you can implement that one on codegen, I'll watch
17:46 fdobridge: <k​arolherbst🐧🦀> I just spill those arrays to a constbuf
17:46 fdobridge: <k​arolherbst🐧🦀> that reminds me...
17:48 fdobridge: <k​arolherbst🐧🦀> https://gitlab.freedesktop.org/karolherbst/mesa/-/commit/ee35bee0c4ed55c5cce5615297847e3fa29d136e