00:23 fdobridge: <g​fxstrand> Merged!
00:34 fdobridge: <a​irlied> yay hopefully we can unblock cond render now
14:56 fdobridge: <k​arolherbst🐧🦀> so let's get this MME magic figured out
15:27 fdobridge: <k​arolherbst🐧🦀> interesting
15:27 fdobridge: <k​arolherbst🐧🦀> so I got something to write into `NVC597_SET_MME_SHADOW_SCRATCH(0)` :3
15:27 fdobridge: <k​arolherbst🐧🦀> and it's not me
15:28 fdobridge: <k​arolherbst🐧🦀> and it's indeed a delayed write
15:29 fdobridge: <k​arolherbst🐧🦀> ```
15:29 fdobridge: <k​arolherbst🐧🦀> TEST_F(mme_tu104_sim_test, gr_test)
15:29 fdobridge: <k​arolherbst🐧🦀> {
15:29 fdobridge: <k​arolherbst🐧🦀> static const uint32_t chunk_size = 32;
15:29 fdobridge: <k​arolherbst🐧🦀>
15:29 fdobridge: <k​arolherbst🐧🦀> mme_builder b;
15:29 fdobridge: <k​arolherbst🐧🦀> mme_builder_init(&b, devinfo);
15:29 fdobridge: <k​arolherbst🐧🦀>
15:29 fdobridge: <k​arolherbst🐧🦀> mme_value load0 = mme_load(&b);
15:29 fdobridge: <k​arolherbst🐧🦀> mme_mthd(&b, NVC597_WAIT_FOR_IDLE);
15:29 fdobridge: <k​arolherbst🐧🦀> mme_emit(&b, mme_zero());
15:29 fdobridge: <k​arolherbst🐧🦀>
15:29 fdobridge: <k​arolherbst🐧🦀> mme_mthd(&b, NVC597_SET_MME_SHADOW_SCRATCH(0));
15:29 fdobridge: <k​arolherbst🐧🦀> mme_emit(&b, mme_zero());
15:29 fdobridge: <k​arolherbst🐧🦀> mme_emit(&b, mme_zero());
15:29 fdobridge: <k​arolherbst🐧🦀> mme_emit(&b, mme_zero());
15:29 fdobridge: <k​arolherbst🐧🦀>
15:29 fdobridge: <k​arolherbst🐧🦀> mme_mthd(&b, NVC597_SET_FALCON09);
15:29 fdobridge: <k​arolherbst🐧🦀> mme_emit(&b, load0);
15:29 fdobridge: <k​arolherbst🐧🦀>
15:29 fdobridge: <k​arolherbst🐧🦀> mme_loop(&b, mme_imm(100)) {
15:29 fdobridge: <k​arolherbst🐧🦀> mme_value r0 = mme_state(&b, NVC597_SET_MME_SHADOW_SCRATCH(26));
15:29 fdobridge: <k​arolherbst🐧🦀> mme_value m1 = mme_merge(&b, mme_zero(), r0, 0, 8, 0);
15:29 fdobridge: <k​arolherbst🐧🦀> mme_store_imm_addr(&b, data_addr + 0, m1);
15:29 fdobridge: <k​arolherbst🐧🦀> }
15:29 fdobridge: <k​arolherbst🐧🦀>
15:29 fdobridge: <k​arolherbst🐧🦀> mme_value r0 = mme_state(&b, NVC597_SET_MME_SHADOW_SCRATCH(0));
15:29 fdobridge: <k​arolherbst🐧🦀> mme_store_imm_addr(&b, data_addr + 4, r0);
15:29 fdobridge: <k​arolherbst🐧🦀>
15:29 fdobridge: <k​arolherbst🐧🦀> auto macro = mme_builder_finish_vec(&b);
15:29 fdobridge: <k​arolherbst🐧🦀>
15:29 fdobridge: <k​arolherbst🐧🦀> but only if the loop runs long enough
15:29 fdobridge: <k​arolherbst🐧🦀> so the firmware is doing _something_
15:29 fdobridge: <m​arysaka> I think the original MME macro wait for ``NVC597_SET_MME_SHADOW_SCRATCH(0)`` to be 1 with some write to method NOP
15:30 fdobridge: <k​arolherbst🐧🦀> currently trying to figure out mme 34, because I suspect it's the read from priv reg function
15:30 fdobridge: <k​arolherbst🐧🦀> contrary to mme 33 being the setter
15:30 fdobridge: <m​arysaka> fun fact the FALCON04 write the value you send (or written?) to ``NVC597_SET_MME_SHADOW_SCRATCH(2)``
15:31 fdobridge: <k​arolherbst🐧🦀> heh
15:31 fdobridge: <m​arysaka> so maybe they do the same for FALCON09?
15:31 fdobridge: <k​arolherbst🐧🦀> not sure
15:31 fdobridge: <k​arolherbst🐧🦀> I mean..
15:31 fdobridge: <k​arolherbst🐧🦀> they do write it anyway
15:32 fdobridge: <k​arolherbst🐧🦀> ```
15:32 fdobridge: <k​arolherbst🐧🦀> mthd(0x3400, 1) /* NVC597_SET_MME_SHADOW_SCRATCH(0) */)
15:32 fdobridge: <k​arolherbst🐧🦀> emit(0x0)
15:32 fdobridge: <k​arolherbst🐧🦀> emit($load0)
15:32 fdobridge: <k​arolherbst🐧🦀> ```
15:32 fdobridge: <k​arolherbst🐧🦀>
15:32 fdobridge: <k​arolherbst🐧🦀> so it should be in `NVC597_SET_MME_SHADOW_SCRATCH(1)`
15:33 fdobridge: <k​arolherbst🐧🦀> but lemme give it access to all registers and see if I can actually read the mmio space out
16:01 fdobridge: <k​arolherbst🐧🦀> it's weird..
16:01 fdobridge: <k​arolherbst🐧🦀> FALCON09 kind of fills the entire scratch space with 1
16:02 fdobridge: <k​arolherbst🐧🦀> @gfxstrand also.. I think your parsed mme stuff is broken a bit? dunno..
16:05 fdobridge: <k​arolherbst🐧🦀> also what is this `JAL (0x8003)` part all about.. mhh
16:12 fdobridge: <g​fxstrand> That's entirely possible. I think it's a little unlikely but possible.
16:13 fdobridge: <g​fxstrand> As long as we're only using FALCON commands on context init, that's fine. We're using scratch registers some today for CS queries and we're likely to use them for other state going forward. That can all be trash on init. We just can't be trashing it mid-client-command-buffer
16:20 fdobridge: <k​arolherbst🐧🦀> any good doc on how `BEQ` works?
16:20 fdobridge: <k​arolherbst🐧🦀> and well.. `JAL` as well
16:37 fdobridge: <k​arolherbst🐧🦀> ohh wait.. figured out `BEQ`
16:44 fdobridge: <g​fxstrand> Yeah, those are weird.
16:44 fdobridge: <g​fxstrand> If you figure out more than I have, please write tests and fix the simulator.
16:44 fdobridge: <g​fxstrand> I wasn't able to get them figured out 100%. I got enough to make basic control-flow work and moved on.
16:44 fdobridge: <k​arolherbst🐧🦀> mhhh
16:44 fdobridge: <k​arolherbst🐧🦀> the annoying thing is, I have no idea what the nvidia stuff is doing
16:45 fdobridge: <k​arolherbst🐧🦀> also.. what's `JAL (0x8003)`...
16:46 fdobridge: <k​arolherbst🐧🦀> just a jump three instructions forward as it seems
16:46 fdobridge: <k​arolherbst🐧🦀> maybe I just copy nvidias macro and see how well it works in GL...
16:58 fdobridge: <k​arolherbst🐧🦀> well.. doesn't work
16:58 fdobridge: <k​arolherbst🐧🦀> I think I have to try that out with GSP running
16:59 fdobridge: <k​arolherbst🐧🦀> I even added a garbage buffer address and nothing bad happens.. maybe I should again set the allow all and see if it works now...
16:59 fdobridge: <k​arolherbst🐧🦀> but I suspect our firmware doesn't have it
17:06 fdobridge: <k​arolherbst🐧🦀> and I think I also know why...
17:07 fdobridge: <k​arolherbst🐧🦀> uhhh
17:19 fdobridge: <g​fxstrand> There's some control bits in the top. I don't know what they all do.
17:20 fdobridge: <k​arolherbst🐧🦀> right..
17:20 fdobridge: <k​arolherbst🐧🦀> but I mean.. I took nvidia's macro as it is (like the binary) and well.. that didn't do a thing either
17:21 fdobridge: <k​arolherbst🐧🦀> I think the firmware has this feature disabled
17:21 fdobridge: <k​arolherbst🐧🦀> anyway, I think I understand completely now what the macro is doing
17:30 fdobridge: <g​fxstrand> Cool
17:30 fdobridge: <g​fxstrand> I'm okay with needing separate code-paths for GSP vs. not, as long as we have it all sorted pre-merge and don't have any backwards compat issues.
17:32 fdobridge: <k​arolherbst🐧🦀> yep
17:32 fdobridge: <k​arolherbst🐧🦀> pre GSP we'll just do it on the kernel side
17:32 fdobridge: <k​arolherbst🐧🦀> and then the device info UAPI should be updated to indicate if GSP is used or not
17:38 fdobridge: <k​arolherbst🐧🦀> anyway, now I have to boot the GSP stuff. Where is the latest branch for that and which gsp binary do I have to use here?
20:33 fdobridge: <a​irlied> https://gitlab.freedesktop.org/skeggsb/nouveau/-/tree/01.02-gsp-rm was it I think, then you have to do lot of dancing, 525.89.02
20:34 fdobridge: <a​irlied> run scripts/extract-openrm-firmware.sh from that repo
20:35 fdobridge: <a​irlied> put the gsp-5258902.bin and the booters into /lib/firmware/nvidia/<family>/gsp
20:44 fdobridge: <E​sdras Tarsis> and choose the correct firmware for your gpu architecture, the driver comes with two iirc
20:55 fdobridge: <M​ohamexiety> theoretically the same steps should apply to ampere right?
21:19 fdobridge: <a​irlied> yup in theory, just making sure you have the right files
21:20 fdobridge: <M​ohamexiety> alight, thanks! I should have time to try this out tomorrow or sunday
21:20 fdobridge: <M​ohamexiety> alright, thanks! I should have time to try this out tomorrow or sunday (edited)
23:49 fdobridge: <k​arolherbst🐧🦀> as long as I'm not driving a display, I should be fine, right?
23:50 fdobridge: <k​arolherbst🐧🦀> or should I also avoid running anything using kms?
23:53 airlied: display can work