13:35platofff: Hello guys, latest 3D mesa driver for nouveau is very cool but I have a problem with pstate switching on Fermi GPU (it always on 270Mhz). I think it's because nouveau cannot load the firmware but it can be a mistake. Here's my bugreport: https://gitlab.freedesktop.org/xorg/driver/xf86-video-nouveau/-/issues/535 Can you help me? Thanks.
13:35karolherbst: platofff: not supported on fermi
13:36platofff: Completely?
13:36karolherbst: platofff: also, you don't need NvGrUseFW=1, this is just for loading the blob firmware in case the nouveau one doesn't work
13:37karolherbst: platofff: well.. there is some code which could be shared with kepler and changing the core clocks could work, but memory reclocking isn't supported at all
13:37karolherbst: some were working on it though
13:37karolherbst: but due to lack of time :/
13:37platofff: OK. I tried to edit my BIOS firmware but i can't change P3 state=L
13:38karolherbst: yeah.. the vbios doesn't implement the reclocking stuff either, so you can't just force higher perf levels and hope it works
13:38platofff: I can edit only P7 and P15
13:38karolherbst: doesn't change a thing really
13:38karolherbst: you might get higher clocks, but a crashing GPU
13:40karolherbst: that stuff is more complicated, otherwise we would have implemented it already
13:41platofff: I hope you can do it before EoL of proprietary driver for Fermi in 2022. In any case, thanks for your work!
13:43karolherbst: hopefully, but we need more devs for that :p
13:43karolherbst: really short on devs right now
13:45platofff: Sadly, but C programming is magic for me :]
14:31ajax: don't worry, it remains magic 20+ years after you learn it
17:12imirkin: Lyude: so it looks like the person with the GP10x is having trouble with DP even on v5.7-rc -- https://bugzilla.kernel.org/show_bug.cgi?id=207901 (retried with firmware)
17:12imirkin: some sort of auxch failure, it seems like
17:39Lyude: imirkin: alright, I'll take a look when I get a chance
17:39imirkin: thanks
17:48imirkin: skeggsb: you fixed hdmi2? thanks =]
18:00imirkin: i forget who had hdmi2 issues, but if you're still here, try applying https://github.com/skeggsb/nouveau/commit/a54efd4cebcdfe9eb4f51cd41e845ffa30146f16
23:30skeggsb: imirkin: i think i also might need to move setting all that stuff into the end of supervisor 2 handling
23:43imirkin: skeggsb: afaik we do stuff backwards from what intel does
23:43imirkin: not sure how it plays out wrt blob
23:43imirkin: basically the scdc write vs setting of the tmds divider logic
23:44skeggsb: i didn't actually look where nvidia do the i2c writes, but they appear to do the hdmi enable + scdc stuff at the end of the second supervisor
23:44imirkin: well, the current implementation was a stab in the dark by me :)
23:44imirkin: it worked on two GPUs with one TV.
23:45skeggsb: well, you implemented it in the "right" place for where we setup that stuff currently, so, it's no worse
23:47skeggsb: we do a few things differently to nvidia in all that, some of which i should probably fix one day as they do cause us some amount of pain
23:47skeggsb: ie. DP link training during the supervisor sequence
23:47skeggsb: it *does* allow us to do quicker modesets sometimes though
23:48skeggsb: whereas nvidia will shut everything down in one modeset, and turn it all back on in another
23:48skeggsb: we do it all in one supervisor sequence a lot more often than they do, just not sure it's "ok"
23:48imirkin: yeah, always hard to know if they do it that way because it was easier for them, or if there's some real reason
23:48imirkin: and we don't have a lab with hundreds of monitors to test with
23:49imirkin: (nor the time to do so, even if we did)
23:50skeggsb: yeah, wherever possible i generally try to copy what they do to avoid hitting random problems