01:14 HdkR: How often is it expected that applications actually don't use XFree for the return of glXChooseFBConfig?
01:16 HdkR: I don't trust applications /not/ messing this up
01:42 Kayden: alyssa, gfxstrand: looks like 7f6491b76d51f35e76715275124d4a8d2eaf8db1 broke the build with -Dintel-clc=enabled (spir-v shaders fail to compile)
01:42 Kayden: trying to read through that patch to find the spot...
01:43 alyssa: Kayden: hooray!
01:43 alyssa: broke the build how?
01:43 alyssa: I don't know if I could build with intel-clc if I wanted to
01:44 Kayden: we're now getting mov(16) vgrf23+0.0:UQ, f0.0<0>:UW instructions where the destination is only 2
01:44 Kayden: 64-bit destination where we're expecting it to be lowered to 32-bit I guess
01:45 alyssa: o_O
01:45 alyssa: I know some of those symbols
01:45 Kayden: flag register being moved to a 64-bit temp register
01:46 Kayden: but the temp register is only 32-bit
01:46 Kayden: so something with booleans maybe
01:47 alyssa: - if (list_is_singular(&load_const->def.uses) &&
01:47 alyssa: - list_is_empty(&load_const->def.if_uses)) {
01:47 alyssa: + if (list_is_singular(&load_const->def.uses))
01:47 alyssa: I guess strictly that should also have an `&& !nir_ssa_def_is_used_by_if(&load_const->def)`
01:47 alyssa: though it probably doesn't matter
01:47 alyssa: and also that's in an opt pass
01:48 alyssa: the other change to intel/compiler is completely mechanical so won't be the problem
01:48 alyssa: so.. either some issue in the NIR changes that somehow doesn't affect anything in CI, or preexisting bug or somthing
01:55 HdkR: Ah, DOTA underlords immediately hecks up this allocation. Got it, no one does memory allocations and freeing correctly.
02:01 Kayden: hm okay it's not a intel optimization issue, the code we generate after translating from NIR is now invalid
02:02 Kayden: but the NIR is identical...?
02:03 alyssa: Uh oh
02:03 alyssa: Memory unsafety doom?
02:17 Kayden: ooooooogh
02:17 Kayden: I found it
02:18 Kayden: our ballot handling is reading instr->dest.ssa.bit_size
02:18 Kayden: the destination is a register
02:19 Kayden: hello garbage reads
02:19 Kayden: also hello unrelated pre-existing bug that just never got hit
02:20 Kayden: 2017
02:20 Kayden: wow
02:30 Kayden:marging a fix via https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22374
02:53 jenatali: :O
03:22 daniels: dj-death: it’s definitely not normal, but it does happen sometimes and that’s actively being worked on
05:15 kode54: weird
05:16 kode54: my Arc card is showing Graphics Pipeline Library support
05:16 kode54: but the build of Mesa I'm using doesn't have that MR merged
05:24 kode54: disregard that
05:24 kode54: vulkaninfo is showing properties of swrast too
05:33 kode54: thanks again for pushing it closer to inclusion
06:25 mareko: tarceri: I wonder how much effort it would be to do UBO linking in NIR, i.e. gathering ubo variables from NIR rather than GLSL
07:44 mareko: does NIR have instruction-level dominance computation helpers?
07:45 mareko: I wouldn't like to reinvent the wheel, I'm mainly interested in instruction-level dominance and post-dominance
07:48 mareko: I'll probably start typing that after I'm finished with moving uniform blocks and UBO loads in shader outputs to the next shader stage
07:54 mareko: which mostly works
07:56 mareko: cwabbott: ^^
11:21 cwabbott: mareko: I think there's already instruction-level dominance but not post-dominance