00:52 airlied: MrCooper: pulling gcc from testing seems to have unblocked it
03:41 airlied: tarceri: hey, I'm seeing some meory leaks with gl_nir_link_uniform_blocks
03:41 airlied: the ralloc context seems to be leaked
03:42 airlied: though I'd only be slightly shocked if it was sometihgin llvmpipe was doing wrong
03:53 tarceri: airlied: hmm was probably me sorry. I pushed a new change this morning maybe I missed a free will check
03:54 airlied: tarceri: this might be a bit older
03:54 tarceri: oh wait link uniforms? or link uniform blocks ?
03:55 airlied: I'm not sure when I last rebased
03:55 tarceri: is this for spirv support?
03:56 airlied: yeah it was the cts spirv tests throwing the leak
03:57 airlied: I can rebase and retest later, once it finished churning this other set of tests
03:57 tarceri: ok I didn't write that code (I maybe reviewed it), and we dont use it yet for the glsl nir linker. It's not all that surprising that there is a leak
03:58 tarceri: IMO the gl spirv support is pretty buggy
03:59 tarceri: the testing offered by CTS and piglit seems pretty limited currently
03:59 airlied: tarceri: ah cool, I'll reproduce it a bit better and file an issue
03:59 airlied: tarceri: yeah I doubt anyone has ran cts under asan yet :-P
04:05 tarceri: :)
04:54 Yuti: Can we get the drm bridge state if we have access to the drm_bridge and drm_connector?
07:24 MrCooper: Lyude: do you really need depmod? The symbol checks performed by the kernel build system aren't enough?
07:26 MrCooper: mareko: e.g. the linear modifier doesn't imply anything about pitch alignment, but different GPUs have different requirements for it, so there's a pretty good chance of pixel jumble when sharing even linear buffers between e.g. AMD & Intel GPUs
07:30 emersion: i'd say it's perfectly fine to fail an import on invalid alignment, but i don't know how much that'd break
07:31 emersion: daniels, danvet: would be nice to write down whether a modifier can encode alignment/placement/etc in drm_fourcc.h
07:31 emersion: it seemed like there was a consensus
07:31 danvet: emersion, sounds like a good idea :-)
07:32 emersion: danvet: what's your take on this btw?
07:32 daniels: yeah, it seems like it. FWIW (for agd5f_ in particular), one of the reasons why we don't encode alignment constraints is because it a) explodes the search space, and b) makes modifiers suddenly ambiguous. for instance, if you have a buffer whose pitch is 1024-aligned, and you have modifiers to encode the requirement to align to (32, 64, 128, 256, 512, 1024) pixels, then suddenly your buffer now matches 6 separate
07:32 daniels: modifiers, because it's compatible with all of them.
07:33 emersion: ah, that makes a lot of sense
07:34 emersion: are there other good resons?
07:39 emersion: it seems like the driver could somehow cope with the multiple-modifiers issue, righjt?
07:39 emersion: right*
07:39 emersion: your buffer could advertise the 1024-pixel aligned modifier
07:51 daniels: well, it could, but the impedance mismatch is the real problem: modifiers by design are supposed to uniquely encode buffer layout, and the fact encoding constraints there makes them ambiguous suggests it's not quite the right hammer to use
07:52 daniels: then you start pushing out from there to encoding contiguous vs. non-contiguous memory, other placement like hidden-VRAM vs. GTT/BAR vs. system memory ...
07:52 daniels: soon we have 128-bit modifiers :P
07:53 HdkR: Only 128bit? I'm sure you could easily push it to 128byte instead :)
07:55 danvet: emersion, daniels yeah I think consensus is that modifier only encodes minimal alignment and stuff
07:55 danvet: e.g. for tiles
07:55 danvet: or for compression, where there's only one true way to do it for a given format because that's how the hw works
07:56 danvet: but if you have stricter alignment constraints on some blocks than others, then encoding that in modifiers is wrong
07:56 danvet: imo
07:56 danvet: ofc import/use needs to then check that
07:56 daniels: right, that's implicit in the definition - you can't have part tiles. we have the same restriction for linear as well, but given that linear has a tile granularity of 1x1px, no-one has yet managed to create buffers which don't satisfy that granularity requirement :P
07:56 danvet: daniels, well linear for macroblock fourcc has larger alignment constraints
07:57 danvet: yuv subsampling being the simplest example
07:57 Zeising: eric_engestrom: ?
07:57 daniels: danvet: conceptually the same if you ask me
07:58 daniels: HdkR: round up to a page
07:59 daniels: anyway, the core of modifiers is: they're opaque (to users) 64-bit tokens, you advertise a list of supported tokens, you intersect lists between different consumers to determine your acceptable set, you pass that set to a producer allocator who picks the locally 'best' one, and from then on in it only has a single modifier which is its modifier.
08:00 daniels: so your only operations are intersect & eq
08:00 daniels: if you have to go reasoning about their content, or if buffers now have multiple modifiers to them, that's something different
08:01 danvet: yeah I think long term we probably can't avoid some accidental aliasing
08:01 danvet: but really should try hard to avoid it
08:01 pq: daniels, what about buffer start address alignment? Sound like you have been thinking only about pitch aligment.
08:01 danvet: a modifier shouldn't be a subset of layouts of another modifier (like 64b aligned vs 128b aligned would be)
08:01 danvet: but entirely disjoint layouts
08:02 danvet: *describe entirely disjoint modifiers
08:03 danvet: it becomes fun together with fourcc, and afbc modifier spec has declared specific (fourcc, modifier) combos as the one and only canonical combo for that reason
08:07 daniels: pq: well quite, that's another thing, and placement, and protection, and ...
08:07 daniels: danvet: well yeah, technically Y_TILED can alias Y_TILED_CCS with the same colour plane, just as presumably AMD can alias between non-DCC and fully-resolved DCC
08:08 daniels: but that's not a fundamental property of the modifier itself, it's a transient property of the buffer content
08:08 pq: it seemed like there was some confusion between people about which alignment was implied by a modifier
08:08 danvet: daniels, I don't mean that kind of aliasing
08:08 danvet: but e.g. for afbc argb and abgr is the same layout
08:08 danvet: so there's only one combo for it that's considered canonical
08:09 daniels: ah, right
08:10 danvet: I think the Y-tiled CCS -> Y-tiled resolve operation is an entirely different thing
08:10 danvet: atm we don't express anywhere that hw can do in-place transitions between modifiers
08:10 danvet: I think that might also be useful for mareko for the CCS-for-rendering -> CCS-for-display transition
08:11 danvet: vk resolve pass sounds kinda like a neat abstraction for that
08:11 danvet: jekstrand, ^^ thoughts?
08:11 danvet: also compositors aren't even close to caring about that kind of stuff right now I think
08:11 daniels: I know lynxeye has previously typed up gbm_bo_copy for doing resolves outside the 3D engine
08:12 daniels: since etnaviv/imx has an attached blit engine which can transition from supertiled (only RT output) to linear (only DC input)
08:12 danvet: well not copies, but in-place
08:12 daniels: yeah
08:12 daniels: different realisation but at least a similar problem class
08:13 daniels: NV proposed an EGL (obviously) resolve API at XDC, but it was not enthusiastically received
08:13 danvet: gbm sounds a bit fun, since you'd need some execution context for this on many gpus
08:13 danvet: with priorities and all that
08:13 danvet: daniels, wasn't it a "no way modifiers" approach?
08:13 lynxeye: yea, GBM doesn't seem to be best place
08:14 danvet: daniels, hm where/when was that?
08:14 lynxeye: That EGL stuff seems useful if you want to do the transition in the compositor, but honestly I think we just want to provide feedback to the applciation
08:14 daniels: danvet: Montreal, October :P
08:14 daniels: tbf I've paged all the context out of my brain, I was pretty sick and rundown by the time XDC came around
08:14 emersion_: lynxeye: agreed
08:15 lynxeye: it will result in a few frames being suboptimal, but the steady state is what we mostly care about
08:15 danvet: daniels, I can't find it to page the stuff back in
08:15 daniels: lynxeye: yeah :) we've been going back and forth a lot on the Wayland protocol to do that this week, with emersion & ascent12 in particular working on it for protocol + Weston + Mesa
08:15 emersion_: i think ascent12 wroe something about it
08:15 danvet: lynxeye, yeah I think just getting to optimized steady state for compositors is almost all the win
08:15 lynxeye: There is just no good way for the compositor to answer the question if a resolve (or even copy) is less work than doing a full render composition
08:15 danvet: the in-place resolve can only help with some hiccup/dropped frames at best
08:16 daniels: danvet: https://xdc2019.x.org/event/5/contributions/335/
08:17 emersion_: also this: https://lists.freedesktop.org/archives/dri-devel/2019-October/239845.html
08:19 danvet: daniels, thx
08:19 daniels: ^ really good summary
08:21 danvet: yeah modifier hints is what we need first
08:21 danvet: then figure out the remaining bits if there's still a need
08:43 tarceri: airlied: a quick look at gl_nir_link_uniform_blocks() and I can see it creates a memory context and never destroys it
08:44 tarceri: airlied: allocate_uniform_blocks() should instead just pass NULL to rzalloc_array()
08:53 emersion_: alright, sent a proposal, hopefully this is a good start
09:49 danvet: hwentlan, agd5f_ [PATCH 2/2] drm/atomic-helper: reset vblank on crtc reset <- might be good if you can give this a spin on amd too
09:49 danvet: just to avoid surprises
10:11 bnieuwenhuizen: emersion: danvet: wrt uniqueness constraints, is the consensus that things also have to be unique for e.g. 1x1 textures?
10:12 danvet: bnieuwenhuizen, well maybe not for those
10:12 danvet: I mean eventually it probably gets a bit silly
10:12 danvet: I guess there's also tiling formats where the difference only matters past a certain size threshold
10:13 danvet: bnieuwenhuizen, fundamentally aliasing isn't a problem, as long as all drivers support all aliases
10:13 danvet: in practice achieving that is a lot easier if we reduce aliasing as much as feasible
14:09 mareko: MrCooper: we won't use the default linear modifier
14:10 MrCooper: then you won't be able to share buffers with other drivers which support modifiers
14:10 mareko: we shouldn't use it, or we should reject it if the alignment is wrong
14:10 mareko: MrCooper: that's fine
14:11 MrCooper: I don't think so :)
14:11 mareko: MrCooper: AMD hw can't use them
14:11 mareko: this is not a choice
14:13 MrCooper: pitch alignment is orthogonal to modifiers, as the Daniels have been explaining
14:14 bnieuwenhuizen: mareko: MrCooper: I think we should expose LINEAR and reject if pitch is too small, as modifier of last resort. When we select it, that means we'd have an empty modifier intersection anyway ...
14:15 daniels: right
14:15 daniels: exposing LINEAR doesn't mean that you support literally every buffer which is linear, regardless of dimensions/pitch/placement/etc
14:15 daniels: you can reject an import for any reason whatsoever
14:16 bnieuwenhuizen: and we can keep allocating linear with the right pitch for AMD, just like the pre-modifier code, so AMD<->AMD will keep working in roughly the same way
14:16 emersion: yeah, rejecting buffer import on bad pitch sounds like the better solution
14:17 emersion: aye
14:45 mareko: MrCooper: there is also BO alignment, which has to be queried from the kernel
14:46 MrCooper: same thing as pitch alignment WRT modifiers I'd say
14:48 kisak: poor Marge woke up on the wrong side of the bed and the scripting couldn't find the coffee pot ( https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5199#note_512426 )
14:49 bnieuwenhuizen: kisak: sounds like the problem is more Gitlab: "Merge failed: Something went wrong during merge: 4:Deadline Exceeded. Please try again. "
14:51 kisak: the commit is visible in cgit, so that's a plus at least
14:51 MrCooper: right, it's that GitLab issue where the changes are merged in Git, but the MR doesn't reflect it
14:55 daniels: yeah, I think some of the new services have created a load imbalance as well
14:58 mareko: daniels: the EGL API for "resolve" is kinda required for any buffer sharing, because it adds much needed acquire-release semantic that other APIs with interop such as OpenGL-OpenCL and OpenGL-Vulkan interop have. EGL is the only weird one here
14:59 mareko: daniels: before a shared buffer use withing the context, and acquire call is made, and after the use, a release call is made
15:00 mareko: *daniels: before a shared buffer use withing the context, an acquire call is made, and after the use, a release call is made
15:01 daniels: mareko: I agree shared FBOs do need an explicit flush/invalidate or acqrel, yeah
15:02 mareko: if that API is missing, it can lead to suboptimal driver behavior or modifier selection
15:03 mareko: and then all EGL apps would have to use it, such as the Chrome browser
15:22 daniels: sure
15:22 daniels: James's API proposal wasn't that though - it was an explicit 'transition from modifier A to modifier B'
15:23 daniels: rather than 'do whatever you need to do to resolve from your current internal state, to something that can be externally sampled as your defined modifier'
15:29 jekstrand: jenatali_: Can you pastebin (or gist or hastebin or whatever you prefer) the NIR you're seeing with extra 64-bit ALU in it?
15:30 jekstrand: jenatali_: I may be able to identify what pass you need to run post-lower_io to clean it up
15:36 bnieuwenhuizen: daniels: I interpreted that presentation very much as having groups of "closely related modifiers" that you may end up transitioning every frame (to switch between rendering and display?)
15:38 kisak: nice, kwin 5.18.5 fails to build against mesa git master, but is fine with mesa 20.0.7. looks like symbols like EGL_TEXTURE_Y_XUXV_WL couldn't be found (likely a linking issue on kde's side)
15:39 sravn: danvet: "drm/atomic-helper: reset vblank on crtc reset"
15:39 karolherbst: kisak: does it include eglmesaext.h?
15:39 sravn: Cannot reply, my ISP has marked the message as SPAM, likely due to too many receivers or such
15:39 sravn: atmel-hlcl parts are r-b
15:39 karolherbst: ehhh.. ufff
15:40 jenatali_: jekstrand: Yeah, one sec. It seems that there's a preference for lowering away (unpack, do 32bit math, pack) into (do 64bit math), even though there's an extra unpack at the end of that sequence
15:40 karolherbst: debugging stuff with libasan fails if the application uses SVM :/
15:40 karolherbst: sad
15:40 danvet: sravn, grab it from lore?
15:40 danvet: or patchwork
15:40 kisak: karolherbst: I don't know, just getting general updates done on a gentoo box ahead of mesa testing later today
15:40 sravn: r-b here is not good enough?
15:40 danvet: sravn, or do you mean your reply is caught by the isp?
15:41 karolherbst: kisak: wait.. it fails to link?
15:41 jekstrand: jenatali_: Weird.... That seems wrong.
15:41 sravn: It is my reply that I cannot send, I have seen it before
15:41 jenatali_: jekstrand: https://pastebin.com/YaWH0Vag
15:41 danvet: sravn, ok I'll forward it
15:42 kisak: karolherbst: yeah, died with "error: ‘EGL_TEXTURE_Y_XUXV_WL’ was not declared in this scope" and 3 others
15:42 karolherbst: that's not a linking issue :p
15:42 daniels: kisak: #include <EGL/eglext.h>
15:42 sravn: Using function named __foo really hurts my eyes. __ signals "internal stuff" or lack of good naming to me
15:42 karolherbst: daniels: it's in eglmesaext.h actually
15:42 daniels: kisak: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4953#note_512473
15:42 jenatali_: jekstrand: I haven't confirmed that that specific change was what caused 64bit ops to reappear after optimizations - I'm going to double-check
15:42 danvet: sravn, we don't have any better idea unfortunately
15:42 daniels: kisak: it's not
15:43 sravn: I know this patch did not introduce the naming, but it introduce the use of a function named __foo in more places. Sigh
15:43 danvet: sravn, the entire atomic state helpers work like this if you subclass a state
15:43 daniels: kisak: it was originally included in eglmesaext.h by Mesa - but eglext.h included eglmesaext.h so you still got it via eglext.h
15:43 daniels: kisak: when we upstreamed it, it moved into eglext.h
15:44 daniels: the scenario I know of where this breaks is where you have eglmesaext.h installed by Mesa (which has it), and you have eglext.h installed by GLVND (which does not have it, and which does not include eglmesaext.h)
15:44 daniels: the solution is to upgrade GLVND so it provides it
15:44 karolherbst: or use glvnd :p
15:44 kisak: daniels: thanks, that's it. I looked in the wrong place before mentioning it here
15:44 karolherbst: in gentoo it's still optional
15:46 jekstrand: jenatali_: It looks like something somewhere is replacing `u2u64(u2u32(x))` with `x & 0xffffffff`
15:46 jekstrand: jenatali_: It also looks like there's a 64-bit multiplication happening
15:49 jekstrand: jenatali_: I see what's happening now. It's the multiply for array offsets that's causing grief
15:49 jekstrand: jenatali_: We could add a couple algebraic opts to clean it up if we wanted
15:49 jenatali_: jekstrand: Yeah. Still seems like being explicit about what size the offsets should be is the simpler/safer thing
15:50 jekstrand: jenatali_: Yeah, I'm thinking that's true now. Feel free to go back to having an offset_bit_size
15:50 jenatali_: jekstrand: Thanks, working on it now :)
15:50 jekstrand: One day, I'd like to have something which can turn most down-cast-of-alu into alu-of-down-cast
15:50 jekstrand: Then this wouldn't be a problem
15:50 jenatali_: Yeah, that'd be nice
15:51 jekstrand: It wouldn't be hard to write, IMO
15:51 jekstrand: We could do it with a giant pile of rules in nir_opt_algebraic but I think this is something that probably wants its own pass.
15:51 mareko: I think it's too late for EGL, nothing can help it
15:51 jekstrand: mareko: It's been too late for EGL for 10 years
15:51 jenatali_: Currently WARP in our currently-released OS builds has a bug with 64bit shifts, which causes them to blow up, in addition to hardware out there with no 64bit support, so I'm trying to avoid 64bit as much as possible :)
15:52 karolherbst: which GPUs actually have a fully native 64 bit alu?
15:53 karolherbst: I think the only thing we've got on nv are 64 bit shifts and 32 bit adds with supports for carry bits
15:53 karolherbst: ....
15:53 karolherbst: and some bcsel stuff I think?
15:54 jekstrand: jenatali_: Oh, sure. I'd like to see it avoided as well
15:54 jenatali_: jekstrand: Opinions about the u2u64 on a 32bit constant for nir_deref_type_var, vs just using a 64bit constant?
15:54 jekstrand: Which is why I'd love to see such an ALU pass so we get rid of all of it. :-)
15:55 jekstrand: jenatali_: Just use a 64-bit constant
15:55 jenatali_: Mmkay
15:55 jekstrand: jenatali_: Actually... You probably want to make build_addr_add assert that it's 32-bit
15:55 jekstrand: So you probably want a 32-bit constant just so you can keep that assert.
15:55 jenatali_: I had that in the version that used addr_get_offset_bit_size
15:56 jenatali_: But the nir_deref_type_var produces an address, not an offset, so it doesn't run through build_addr_iadd
15:56 jekstrand: Right, that one can just build an immediate
15:56 jekstrand: Maybe assert(location <= UINT32_MAX)
15:56 jenatali_: Sure, that works
16:02 mareko: karolherbst: we have an instruction that does i64 = i32 * i32 + i64
16:02 karolherbst: mareko: we... don't
16:02 karolherbst: or.. maybe?
16:02 karolherbst: wait....
16:02 karolherbst: I think we do
16:02 karolherbst: well, kind of
16:03 karolherbst: you can get the high or low bits of the 32 * 32 mul
16:03 karolherbst: so you have two instructions and then merge the value...
16:10 jenatali_: I'm actually not sure who has native 64bit ops
16:10 imirkin: nvidia has native 64-bit atomic ops
16:10 mareko: imirkin: everybody has those I think
16:11 imirkin: nvidia has native 128-bit atomic ops :)
16:11 imirkin: well, more like "op"
16:16 bnieuwenhuizen: imirkin: which one? compare and exchange?
16:16 imirkin: bnieuwenhuizen: i don't remember. iirc add.
16:17 imirkin: i just remember being surprised
16:17 bnieuwenhuizen:is now wondering if the generic cache-skipping 128-bit writes are atomic on AMD
16:18 imirkin: actually looks like all atomics (or at least most) work with u128
16:18 imirkin: on maxwell+
16:19 imirkin: at least the ISA (decoder) supports it. the hw sometimes disagrees.
16:19 imirkin: i haven't personally tested it
16:20 imirkin: https://github.com/envytools/envytools/blob/master/envydis/gm107.c#L1894 -- and if you look up ed00sz, u128 is one of the options.
16:20 imirkin: but perhaps not all combinatiosn with ops work
16:20 karolherbst: imirkin: I think the 64 bit ones work at least
16:20 karolherbst: I tested them recently
16:20 imirkin: yes, those definitely do
16:20 imirkin: iirc the 128-bit one was more limited
16:20 karolherbst: might be
16:20 imirkin: tehre might be some asserts in the emitter that cover it
16:21 imirkin: i don't have the code handy
16:21 karolherbst: probably VRAM only and stuff like that
16:21 imirkin: well, gmem-only, obviously, no shared mem
16:21 imirkin: (and atomics on local are just pointless)
16:21 karolherbst: shared has working 64 bit cas though
16:22 imirkin: yeah, on maxwell
17:07 eric_engestrom: Zeising: I was just tagging you to show you that airlied did a libdrm release :)
17:10 hat|: hey, my GPU decided to reset itself while playing, any idea what went wrong? here's the journal http://paste.awesom.eu/qSTN
17:19 pepp: hat|: could be the same issue as the one reported here: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2647
17:26 sravn: danvet: was off for dinner. Yeah, so you say that if you subclass then the functions are named __foo. Not great that the recommended style force one to use the ill named functions. Maybe subclassing was not a thing in the past. Anyway, it is just the way it is and if I do not like it I could bite the bullet and post patches, which will not happen...
17:27 danvet: sravn, we had exactly this discussions when atomic landed
17:27 danvet: subclassing was part from day one
17:27 danvet: outcome was: no one likes it, no one had a better idea
17:27 danvet: definitely would be nice to have something
17:28 sravn: OK, I will let it slip now. But maybe if I one day touch this code I may try to be creative
17:29 danvet: sravn, yeah definitely
18:00 Zeising: eric_engestrom: Ok, thanks. :)
18:05 hanetzer: so. trying to get my 4k120hz monitor to work, amdgpu driver (foss on both sides), rx580 w/8gb ram
18:06 hanetzer: its the kind that uses two cables (dp; I'm using dp 1.4 cables) and uses the TILE property to stitch itself back together.
18:39 alyssa: does NIR pipe through GLES version (2 vs 3) to decide if NaNs should be flushed to zero / Inf clamped?
18:40 alyssa: I see FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP*, but that seems to be a SPIR-V thing
18:41 HdkR: Paging Dr. jekstrand for GL floating point behaviour rules :)
18:43 anholt_: does gles even have a flag for enabling flush to zero?
18:45 hanetzer: HdkR: hey, was that you who recommended those dp cables?
18:45 HdkR: hanetzer: Yea
18:45 hanetzer: got 'em.
18:45 hanetzer: now apparently there's an outstanding bug in the amdgpu driver to make tiled displays work properly :<
18:47 HdkR: huh
18:47 jekstrand: HdkR: Hah!
18:47 alyssa: anholt_: Er maybe not I think I misread the spec
18:48 alyssa: Looks like the impl can decided to saturate *or* use a real inf
18:48 alyssa: (For GLSL ES 1.0)
18:48 anholt_: es3 gives you isinf/isnan, and you should be preserving inf/nan at least by then
18:49 alyssa: yeah
18:49 alyssa: For context, the mali blob sets "suppress inf/nan" flags if the shader is GLSL ES 1.0, but not if it's ES3
18:49 alyssa: presumably to workaround GLES2 app bugs
18:50 HdkR: s/bugs/assumptions
18:50 alyssa: glmark2-es2 -bterrain is badly broken for us if fp16 is enabled without suppressing inf, but if we set the flag like the blob it's fine, and fp32 is fine
18:51 alyssa: poorly written app? sure. is our impl conformant here? yes. does it make sense to workaround anyway and still be conformant? not sure.
18:58 hanetzer: just patch the standard to make the bug conformant ;P
18:58 alyssa: hanetzer: the bug is conformatn :d
18:58 hanetzer: agd5f_: hey, aren't you the amdgpu dude?
19:00 imirkin: anholt_: my experience in GL is that ftz is required for regular fp32 ops
19:01 imirkin: (which is separate from the inf/nan discussion, whereby DX9-based things assume that 0 * x = 0, even if x is infinity -- this is "solved" in different ways on diff gpu's)
19:01 imirkin: wine wants to be able to control that, but i couldn't get amd/intel to sign on to implement the ext, so it never went anywhere.
19:02 hat|: pepp: I got the same graphics card so that could be it
19:09 HdkR: alyssa: I guess the question is more. Does NIR have this NaN definition (thus getting optimizations that can only occur one way or the other) or does each backend need to do magic around this and self-scope out which API is in use?
19:32 imirkin: mareko: i obviously don't really know the details, but this looks odd to me -- https://cgit.freedesktop.org/mesa/mesa/commit/?id=a91306677c613ba7511b764b3decc9db42b24de1 -- based on the description (and the next line of code), i would have expected to use cu_mask[i][j], with only the cu_bitmap indices changed
19:35 agd5f_: hanetzer, what's the question?
19:37 hanetzer: agd5f_: tiled display. borked on amdgpu
19:38 hanetzer: basically one half is where its supposed to be, the other is shifted half a screen upward (or downward, hard to tell), it all jitters, and each half sometimes swap the 'right position' 'shifted position' setup.
19:41 agd5f_: hanetzer, file a bug: https://gitlab.freedesktop.org/drm/amd/issues
19:43 hanetzer: I think it has been filed, and I think you're working on it?
19:44 agd5f_: hanetzer, got a link>
19:44 agd5f_: ?
19:44 hanetzer: https://bugs.freedesktop.org/show_bug.cgi?id=110671 maybe this. need to locate the url again.
19:46 hanetzer: also gitlab is hella laggy for me atm...
19:46 hanetzer: https://gitlab.freedesktop.org/drm/amd/issues/781 I think this was it, but again, hard to check as the link keeps timing out.
19:46 gitbot: drm issue 781 in amd "Regression: DP outputs out of sync on dual-DP tiled 5k screen" [Amdgpu, Bugzilla, Opened]
19:47 imirkin: hanetzer: i saw some recent stuff about preferring dispid to other parts of edid with tiles
19:47 imirkin: hanetzer: is this with recent kernels?
19:48 imirkin: oh, maybe i'm thinking of "drm/edid: Fix off-by-one in DispID DTD pixel clock"
19:49 imirkin: as well as a patch series from Ville in mid-march fixing DispID parsing
19:50 agd5f_: hanetzer, this patch may fix it: https://cgit.freedesktop.org/~agd5f/linux/commit/?h=drm-next&id=fd8f7c65a6c5438af474077cad5deb8652d116e1
19:50 agd5f_: but I've had a hard time getting it reviewed by the display team
19:51 hanetzer: yeah so I saw. I have already applied that, or does this require dc=1 ?
19:51 hanetzer: this is a rx5800 gpu, btw.
19:52 vsyrjala: + a few more dispid patches today
19:52 agd5f_: hanetzer, rx580 (polaris) or rx5700 (navi)?
19:52 imirkin: hanetzer: is that like 10 rx580's? :)
19:53 hanetzer: agd5f_: polaris, I think. VGA compatible controller [0300]: Advanced Micro Devices, Inc. [AMD/ATI] Ellesmere [Radeon RX 470/480/570/570X/580/580X/590] [1002:67df] (rev e7)
19:53 hanetzer: achk. mistyped :)
19:53 emersion: maybe try patch and add Tested-By?
19:53 agd5f_: yup
19:54 hanetzer: so dc=1 or dc=0?
19:54 agd5f_: dc=1 (the default)
19:54 hanetzer: amdgpu.dc=1 right now and same issue. kk. one sec. reboot.
20:02 hat|: pepp: how safe is it to build master and use it for the workaround? Should I wait the next release?
20:06 hanetzer: erm. I mean right now was dc=0. and yeah.
20:06 hanetzer: I'll give it my ack :)
20:08 hanetzer: now how do I properly scale this dual tile behemoth.
20:10 hanetzer: there we go.
20:11 hanetzer: agd5f_: emersion: WFM.
20:11 emersion: excellent
20:12 mareko: imirkin: thanks
20:13 emersion: ivyl: just FYI, it seemed like patchwork didn't understood this series https://patchwork.freedesktop.org/series/77361/#rev2
20:13 emersion: seems*
20:17 ivyl: emersion: https://lists.freedesktop.org/archives/dri-devel/2020-May/thread.html#266499 seems like it only got the second patch out of two
20:17 hanetzer: here's another question. my 'Screen 0' is too large (due to resizes with xrandr), is there a way to reduce it?
20:18 ivyl: that's why it got confused with rev1, and then for rev2 it took the v2 which was sent without any x/y as the 1/2
20:18 ivyl: cannot blame the robot, I would be baffled as a human too
20:18 emersion: ah, but what happened here
20:19 emersion: sorry for the fuss
20:19 ivyl: patches 1/2 and 2/2 were sent as a top level patches
20:19 emersion: ah, patch 1/2 is here https://lists.freedesktop.org/archives/dri-devel/2020-May/266498.html
20:19 emersion: yeah
20:19 ivyl: 2/2 should be In-Reply-To: 1/2, which is the default git send-email behavior
20:20 emersion: okay, i can see why this happens
20:20 emersion: thanks!
20:20 ivyl: no worries, thenks for letting me know
20:20 ivyl: more often than not it's the patchwork being too naive in it's assumptions
20:25 airlied: agd5f_: is that the fix 2 DPs on navi patch as well?
20:27 agd5f_: airlied, don't know. fixes an issue with sync groups for tiled displays
20:33 ivyl: emersion: now thinking about it, I'll write down all the patchwork's assumptions and expectations and I'll link to it in the incomplete/strange series message
20:34 emersion: ivyl: ah, that'd be pretty helpful :)
20:34 jekstrand: Oh, patchwork.....
20:34 jekstrand:doesn't miss patchwork for Mesa
20:34 hanetzer: agd5f_: what can I do to maybe help move that forward?
20:37 ivyl: jekstrand: yeah, I hope we'll move on too :-P
20:41 jekstrand: Patchwork: Simultaneously the worst tool imaginable and also the best there is at its job....
20:42 alyssa: jekstrand: That's basically how I feel about computers as a whole.
20:42 jekstrand: alyssa: touche
20:43 imirkin: i need a computer that does what i want it to do, not what i tell it to do
20:45 ivyl: wait till you get first DNN-generated HW
20:46 imirkin:is holding his breath
20:47 karolherbst: ivyl: nah.. those just execute "rm -rfv /" randomly
20:48 bnieuwenhuizen: karolherbst: so how well would you like a machine that solves your problem 99.99% of the time and does "rm -rfv /" otherwise?
20:48 bnieuwenhuizen:feels that that is how internet services are these days
20:48 alyssa: bnieuwenhuizen: 99.99 seems high
20:49 ivyl: karolherbst: I am fine with delete driven development - you keep removing stuff as long as all your tests pass
20:49 alyssa: ivyl: I think it's more efficient to just keep removing tests until none fail.
20:49 ivyl: deletion also happens on the test code though
20:49 ivyl: :>
20:50 bnieuwenhuizen: alyssa: if your events are minutes that is still ~1 hour a year
20:50 alyssa: Yeah, I spend much more than that fighting the machine
20:50 bnieuwenhuizen: alyssa: luckily most of the time it doesn't work it doesn't delete the world either
20:52 agd5f_: hanetzer, I'll try reviving the thread again
20:52 alyssa: bnieuwenhuizen: Just yesterday I lost commits because a BO leak led to an OOM which required a hard reboot which led to disk corruption which led to .git irrecovably corrupting
20:56 hanetzer: alyssa: :<
20:57 ivyl: oh, that's unlucky :(
20:58 alyssa: admittedly the commits were really bad, hence why they weren't pushed :p
21:08 imirkin: alyssa: normally one talks about self-modifying code, but this sounds like self-deleting code
21:17 alyssa: imirkin: >:
21:46 jekstrand: bnieuwenhuizen, hakzsam, tarceri: Why is radv still using lower_ubo_ssbo_access_to_offsets?
21:47 jekstrand: robclark, cwabbott: Same question for turnip ^^
21:48 robclark: non-zero chance it was copied from radv
21:49 airlied: jekstrand: is there a benefit in not using it?
21:49 jekstrand: NIR can optimize SSBO access
21:49 jekstrand: Also, it's a legacy path I'd very much like to delete from the SPIR-V parser
21:49 jekstrand: IIRC, someone tried turning it off for RADV and saw pipeline-db regressions.
21:50 anholt_: I've switched half the chezas in CI over to the new baremetal runner in prep for enabling pre-merge vulkan testing, let me know if you see a630 jobs get backed up.
21:50 jekstrand: But zero work has gone into dropping it AFAICT
21:50 jekstrand: We're carrying two different UBO/SSBO deref paths in spirv_to_nir right now because of it. :-(
23:06 glisse: robclark: you remember off hand who is the maintainer for the overall arm architecture (not arm64)
23:06 robclark: I doubt there is just one..
23:08 glisse: well it seems there is one for every single soc
23:08 glisse: i just do not want to spam bomb 20 people
23:09 robclark: https://www.irccloud.com/pastebin/zoTR1d6Q/
23:12 airlied: glisse: rmk for arm
23:39 Lyude: has anyone tried building igt with clang before?
23:41 airlied: that doesn't seem like something that would solve any problem I'd want :-P
23:42 Lyude: airlied: cross compiling with gcc is more like a long running joke\
23:43 airlied: Lyude: why are you cross compiling?
23:44 airlied:avoids cross compiling anything that isn't the kernel due to the pain, compilers are rarely the problem
23:45 airlied: Lyude: looks like it has a clang build in CI
23:45 Lyude: airlied: trying to fix igt building on fedora ppc64le so the package can start updating again, mainly so we can use it for the other thing i'm working on that I can't mention here
23:46 airlied: but why would that need cross compiling?
23:46 Lyude: and i did not expect to spend this much time on it :\
23:46 airlied: could probably do like we do for mesa with the igt CI
23:47 airlied: does some ppc64le/s390 in qemu builds I think
23:47 Lyude: airlied: i really don't like building stuff on other machines, because it either means I have to have my source files over nfs on the machine I'm building on, or send things back and forth, etc. and it just becomes kind of painful especially with how many scripts I have on my machine with hardcoded paths
23:48 Lyude: also, probably should note my beef with cross-compiling on gcc is mainly around the fact there's basically no reason it shouldn't just support cross compiling for every arch out of the box like clang :s
23:48 airlied: Lyude: in fedora I generally just pull the cross compilers from the distro
23:48 airlied: it never seems that much work
23:48 airlied: but I only really use them for the kernel
23:49 airlied: Lyude: can't you just git clone on the ppc64le machine and fix it, and push from there?
23:49 Lyude: airlied: yeah I just really would have liked to have this just, work in the future and not have to do that every time another arch breaks :\
23:50 airlied: Lyude: then I'd probably spend time on adding ppc64le/s390 to CI like mesa does
23:50 Lyude: mhm, if only I had time ;;. i am going to try doing that at some point
23:51 airlied: it also depends on whether the problems are distro related or cross compiling related
23:51 airlied: you can waste a lot of time fixing cross compiler issues that don't exist in the real world
23:51 Lyude: also btw - i'm fairly sure the reason the cross compiler from fedora doesn't work is because they strip a bunch of stuff from it that you need for cross compiling anything that isn't the kernel, I remember I ran into this same issue with aarch64 building when I was doing panfrost stuff and I ended up having to use https://copr.fedorainfracloud.org/coprs/lantw44/aarch64-linux-gnu-toolchain/
23:52 Lyude: apparently there is no ppc64le equivalent to that though
23:53 Lyude: i'm going to try forking that, but if that doesn't work I'll probably just go to rsync and grumble
23:53 airlied: it just seems like you aren't using git like "distributed" part of DVCS :-P
23:53 Lyude: airlied: pardon?
23:54 airlied: the mention of rsync
23:54 Lyude: i have a feeling i'm about to realize i've been overlooking something extremely obvious
23:55 airlied: I'm just not seeing what you are proposing I guess :-), whenever I deal with other architectures, I just git clone on the machine, do the work, and get out of there
23:59 airlied: I have never nfs mounted, rsynced anything, granted I'm also usually on the other side of the world from those machines