libGL: pci id for fd 4: 8086:0a16, driver i965
libGL: OpenDriver: trying /home/anholt/src/mesa/src/gallium/drivers/vc4/simulator/tls/i965_dri.so
libGL: OpenDriver: trying /home/anholt/src/mesa/src/gallium/drivers/vc4/simulator/i965_dri.so
libGL: Using DRI3 for screen 0
LOWERED
decl_var shader_in smooth vec4 in_0 (5, 0)
decl_var shader_out  vec4 out_0 (1, 0)
decl_overload main returning void

impl main {
	block block_0:
	/* preds: */
	vec4 ssa_0 = intrinsic load_input () () (0)
	vec4 ssa_1 = fmov ssa_0
	vec4 ssa_5 = fmov ssa_1
	vec4 ssa_2 = fmov ssa_5
	vec4 ssa_3 = fsat ssa_2
	vec4 ssa_6 = imov ssa_3
	vec4 ssa_4 = fmov ssa_6
	vec4 ssa_7 = fmov ssa_4
	vec1 ssa_8 = intrinsic load_input () () (268435456)
	vec4 ssa_9 = unpack_unorm_4x8 ssa_8
	vec1 ssa_10 = imov ssa_7
	vec1 ssa_11 = imov ssa_9
	vec1 ssa_12 = imov ssa_7.y
	vec1 ssa_13 = imov ssa_9.y
	vec1 ssa_14 = imov ssa_7.z
	vec1 ssa_15 = imov ssa_9.z
	vec1 ssa_16 = imov ssa_7.w
	vec1 ssa_17 = imov ssa_9.w
	vec1 ssa_18 = fsat ssa_10
	vec1 ssa_19 = fsat ssa_12
	vec1 ssa_20 = fsat ssa_14
	vec1 ssa_21 = fsat ssa_16
	vec1 ssa_22 = load_const (0x3f800000 /* 1.000000 */)
	vec1 ssa_23 = fmul ssa_18, ssa_22
	vec1 ssa_24 = load_const (0x3f800000 /* 1.000000 */)
	vec1 ssa_25 = fsub ssa_24, ssa_21
	vec1 ssa_26 = fmul ssa_11, ssa_25
	vec1 ssa_27 = load_const (0x3f800000 /* 1.000000 */)
	vec1 ssa_28 = fmul ssa_19, ssa_27
	vec1 ssa_29 = load_const (0x3f800000 /* 1.000000 */)
	vec1 ssa_30 = fsub ssa_29, ssa_21
	vec1 ssa_31 = fmul ssa_13, ssa_30
	vec1 ssa_32 = load_const (0x3f800000 /* 1.000000 */)
	vec1 ssa_33 = fmul ssa_20, ssa_32
	vec1 ssa_34 = load_const (0x3f800000 /* 1.000000 */)
	vec1 ssa_35 = fsub ssa_34, ssa_21
	vec1 ssa_36 = fmul ssa_15, ssa_35
	vec1 ssa_37 = load_const (0x3f800000 /* 1.000000 */)
	vec1 ssa_38 = fmul ssa_21, ssa_37
	vec1 ssa_39 = load_const (0x3f800000 /* 1.000000 */)
	vec1 ssa_40 = fsub ssa_39, ssa_21
	vec1 ssa_41 = fmul ssa_17, ssa_40
	vec1 ssa_42 = fadd ssa_23, ssa_26
	vec1 ssa_43 = fadd ssa_28, ssa_31
	vec1 ssa_44 = fadd ssa_33, ssa_36
	vec1 ssa_45 = fadd ssa_38, ssa_41
	vec4 ssa_46 = vec4 ssa_44, ssa_43, ssa_42, ssa_45
	vec1 ssa_47 = pack_unorm_4x8 ssa_46
	vec1 ssa_48 = load_const (0x00000000 /* 0.000000 */)
	vec1 ssa_49 = iand ssa_8, ssa_48
	vec1 ssa_50 = load_const (0xffffffff /* -nan */)
	vec1 ssa_51 = iand ssa_47, ssa_50
	vec1 ssa_52 = ior ssa_51, ssa_49
	intrinsic store_output (ssa_52) () (0)
	/* succs: block_1 */
	block block_1:
}

FS prog 0/0 NIR:
decl_var shader_in smooth vec4 in_0 (5, 0)
decl_var shader_out  vec4 out_0 (1, 0)
decl_overload main returning void

impl main {
	decl_reg vec1 r2
	decl_reg vec1 r3
	decl_reg vec1 r4
	decl_reg vec1 r5
	decl_reg vec1 r6
	decl_reg vec1 r7
	decl_reg vec1 r8
	decl_reg vec1 r9
	decl_reg vec1 r10
	decl_reg vec1 r11
	decl_reg vec1 r12
	decl_reg vec1 r13
	decl_reg vec1 r14
	decl_reg vec1 r15
	decl_reg vec1 r16
	decl_reg vec1 r17
	decl_reg vec1 r18
	decl_reg vec1 r19
	decl_reg vec1 r20
	decl_reg vec1 r21
	decl_reg vec4 r22
	decl_reg vec1 r23
	block block_0:
	/* preds: */
	r2 = intrinsic load_input () () (0)
	r3 = intrinsic load_input () () (1)
	r4 = intrinsic load_input () () (2)
	r5 = intrinsic load_input () () (3)
	/* 1.000000 */ vec1 ssa_100 = load_const (0x3f800000 /* 1.000000 */)
	r6 = intrinsic load_input () () (268435456)
	r7 = unpack_unorm_4x8 r6
	/* 0.000000 */ vec1 ssa_146 = load_const (0x00000000 /* 0.000000 */)
	r8 = fmax r2, /* 0.000000 */ ssa_146
	r9 = fmin r8, /* 1.000000 */ ssa_100
	r10 = fmax r3, /* 0.000000 */ ssa_146
	r11 = fmin r10, /* 1.000000 */ ssa_100
	r12 = fmax r4, /* 0.000000 */ ssa_146
	r13 = fmin r12, /* 1.000000 */ ssa_100
	r14 = fmax r5, /* 0.000000 */ ssa_146
	r15 = fmin r14, /* 1.000000 */ ssa_100
	r16 = fsub /* 1.000000 */ ssa_100, r15
	r17 = fmul r7, r16
	r18 = fadd r9, r17
	r19 = fadd r11, r17
	r20 = fadd r13, r17
	r21 = fadd r15, r17
	r22 = vec4 r20, r19, r18, r21
	r23 = pack_unorm_4x8 r22
	intrinsic store_output (r23) () (0)
	/* succs: block_1 */
	block block_1:
}

FS prog 0/0 pre-opt QIR:
frag_w t0
fmul t1, v0, t0
vary_add_c t2, t1
frag_w t3
fmul t4, v1, t3
vary_add_c t5, t4
frag_w t6
fmul t7, v2, t6
vary_add_c t8, t7
frag_w t9
fmul t10, v3, t9
vary_add_c t11, t10
tlb_color_read t12
unpack_8a_f t13, t12
fmax t14, t2, u0 (0x00000000 / 0.000000)
fmin t15, t14, u1 (0x3f800000 / 1.000000)
fmax t16, t5, u0 (0x00000000 / 0.000000)
fmin t17, t16, u1 (0x3f800000 / 1.000000)
fmax t18, t8, u0 (0x00000000 / 0.000000)
fmin t19, t18, u1 (0x3f800000 / 1.000000)
fmax t20, t11, u0 (0x00000000 / 0.000000)
fmin t21, t20, u1 (0x3f800000 / 1.000000)
fsub t22, u1 (0x3f800000 / 1.000000), t21
fmul t23, t13, t22
fadd t24, t15, t23
fadd t25, t17, t23
fadd t26, t19, t23
fadd t27, t21, t23
pack_8888_f t28, t26
pack_8b_f t29, t28, t25
pack_8c_f t30, t29, t24
pack_8d_f t31, t30, t27
mov t32, t31
tlb_color null, t32
FS prog 0/0 QIR:
frag_w t0
fmul t1, v0, t0
vary_add_c t2, t1
fmul t4, v1, t0
vary_add_c t5, t4
fmul t7, v2, t0
vary_add_c t8, t7
fmul t10, v3, t0
vary_add_c t11, t10
tlb_color_read t12
unpack_8a_f t13, t12
fmax t14, t2, 0
fmin t15, t14, 1.000000
fmax t16, t5, 0
fmin t17, t16, 1.000000
fmax t18, t8, 0
fmin t19, t18, 1.000000
fmax t20, t11, 0
fmin t21, t20, 1.000000
fsub t22, 1.000000, t21
fmul t23, t13, t22
fadd t24, t15, t23
fadd t25, t17, t23
fadd t26, t19, t23
fadd t27, t21, t23
pack_8888_f t28, t26
pack_8b_f t29, t28, t25
pack_8c_f t30, t29, t24
pack_8d_f t31, t30, t27
tlb_color null, t31
VS prog 1/0 NIR:
decl_var shader_in flat vec4 in_0 (0, 0)
decl_var shader_out  vec4 out_0 (0, 0)
decl_var shader_out  vec4 out_1 (5, 1)
decl_overload main returning void

impl main {
	decl_reg vec1 r4
	decl_reg vec1 r5
	decl_reg vec1 r6
	decl_reg vec1 r7
	decl_reg vec1 r8
	decl_reg vec1 r9
	decl_reg vec1 r10
	decl_reg vec1 r11
	decl_reg vec1 r12
	decl_reg vec1 r13
	block block_0:
	/* preds: */
	vec4 ssa_0 = load_const (0x00000000 /* 0.000000 */, 0x3fc00000 /* 1.500000 */, 0x3f800000 /* 1.000000 */, 0xbf800000 /* -1.000000 */)
	r4 = intrinsic load_input () () (1)
	r5 = fadd r4, ssa_0.z
	r6 = fmul ssa_0.y, r5
	r7 = fadd r6, ssa_0.w
	r8 = intrinsic load_input () () (0)
	r9 = fadd r8, ssa_0.z
	r10 = fmul ssa_0.y, r9
	r11 = fadd r10, ssa_0.w
	r12 = intrinsic load_input () () (2)
	r13 = intrinsic load_input () () (3)
	intrinsic store_output (r8) () (0)
	intrinsic store_output (r4) () (1)
	intrinsic store_output (r12) () (2)
	intrinsic store_output (r13) () (3)
	intrinsic store_output (ssa_0) () (4)
	intrinsic store_output (r7) () (5)
	intrinsic store_output (ssa_0) () (6)
	intrinsic store_output (r11) () (7)
	/* succs: block_1 */
	block block_1:
}

VS prog 1/0 pre-opt QIR:
mov t0, vpm0.0
mov t1, vpm0.1
mov t2, vpm0.2
mov t3, vpm0.3
fadd t4, t1, u2 (0x3f800000 / 1.000000)
fmul t5, u1 (0x3fc00000 / 1.500000), t4
fadd t6, t5, u3 (0xbf800000 / -1.000000)
fadd t7, t0, u2 (0x3f800000 / 1.000000)
fmul t8, u1 (0x3fc00000 / 1.500000), t7
fadd t9, t8, u3 (0xbf800000 / -1.000000)
mov t10, t0
mov t11, t1
mov t12, t2
mov t13, t3
mov t14, u0 (0x00000000 / 0.000000)
mov t15, t6
mov t16, u0 (0x00000000 / 0.000000)
mov t17, t9
rcp t18, t13
fmul t19, t10, u4
fmul t20, t19, t18
ftoi t21, t20
fmul t22, t11, u5
fmul t23, t22, t18
ftoi t24, t23
pack_scaled t25, t21, t24
mov vpm, t25
fmul t26, t12, u6
fmul t27, t26, t18
fadd t28, t27, u7
mov vpm, t28
mov vpm, t18
mov vpm, t14
mov vpm, t15
mov vpm, t16
mov vpm, t17
VS prog 1/0 QIR:
mov t0, vpm0.0
mov t1, vpm0.1
mov t2, vpm0.2
mov t3, vpm0.3
fadd t4, t1, 1.000000
fmul t5, u1 (0x3fc00000 / 1.500000), t4
fadd t7, t0, 1.000000
fmul t8, u1 (0x3fc00000 / 1.500000), t7
rcp t18, t3
fmul t19, t0, u4
fmul t20, t19, t18
ftoi t21, t20
fmul t22, t1, u5
fmul t23, t22, t18
ftoi t24, t23
pack_scaled t25, t21, t24
mov vpm, t25
fmul t26, t2, u6
fmul t27, t26, t18
fadd vpm, t27, u7
mov vpm, t18
mov vpm, 0
fadd vpm, t5, u3 (0xbf800000 / -1.000000)
mov vpm, 0
fadd vpm, t8, u3 (0xbf800000 / -1.000000)
CS prog 1/1 NIR:
decl_var shader_in flat vec4 in_0 (0, 0)
decl_var shader_out  vec4 out_0 (0, 0)
decl_var shader_out  vec4 out_1 (5, 1)
decl_overload main returning void

impl main {
	decl_reg vec1 r4
	decl_reg vec1 r5
	decl_reg vec1 r6
	decl_reg vec1 r7
	block block_0:
	/* preds: */
	r4 = intrinsic load_input () () (0)
	r5 = intrinsic load_input () () (1)
	r6 = intrinsic load_input () () (2)
	r7 = intrinsic load_input () () (3)
	intrinsic store_output (r4) () (0)
	intrinsic store_output (r5) () (1)
	intrinsic store_output (r6) () (2)
	intrinsic store_output (r7) () (3)
	/* succs: block_1 */
	block block_1:
}

CS prog 1/1 pre-opt QIR:
mov t0, vpm0.0
mov t1, vpm0.1
mov t2, vpm0.2
mov t3, vpm0.3
mov t4, t0
mov t5, t1
mov t6, t2
mov t7, t3
rcp t8, t7
mov vpm, t4
mov vpm, t5
mov vpm, t6
mov vpm, t7
fmul t9, t4, u1
fmul t10, t9, t8
ftoi t11, t10
fmul t12, t5, u2
fmul t13, t12, t8
ftoi t14, t13
pack_scaled t15, t11, t14
mov vpm, t15
fmul t16, t6, u3
fmul t17, t16, t8
fadd t18, t17, u4
mov vpm, t18
mov vpm, t8
CS prog 1/1 QIR:
mov t0, vpm0.0
mov t1, vpm0.1
mov t2, vpm0.2
mov t3, vpm0.3
rcp t8, t3
mov vpm, t0
mov vpm, t1
mov vpm, t2
mov vpm, t3
fmul t9, t0, u1
fmul t10, t9, t8
ftoi t11, t10
fmul t12, t1, u2
fmul t13, t12, t8
ftoi t14, t13
pack_scaled t15, t11, t14
mov vpm, t15
fmul t16, t2, u3
fmul t17, t16, t8
fadd vpm, t17, u4
mov vpm, t8
Probe color at (0,0)
  Expected: 0.000000 0.000000 0.500000 0.000000
  Observed: 0.501961 0.501961 0.501961 0.501961
PIGLIT: {"result": "fail" }