Reading /home/anholt/cheza-results/n5x/dEQP-GLES3.functional.multisample.fbo_4_samples.proportionality_alpha_to_coverage.rd.gz... test: gpu_id: 418 cmd: perfcounter_get: groupid=27, countable=0, off_lo=0x16e, off_hi=0x16f cmd: perfcounter_get: groupid=27, countable=0, off_lo=0x16e, off_hi=0x16f ############################################################ cmdstream: 48 dwords t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 0016b000: 0000: c0002600 00000000 t0 write UCHE_INVALIDATE0 (0e8a) UCHE_INVALIDATE0: 0 UCHE_INVALIDATE1: 0x12 0016b008: 0000: 00010e8a 00000000 00000012 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 0016b014: 0000: c0002600 00000000 t0 write RB_MODE_CONTROL (20a0) RB_MODE_CONTROL: { WIDTH = 64 | HEIGHT = 64 | ENABLE_GMEM } 0016b01c: 0000: 000020a0 00010202 t0 write RB_FRAME_BUFFER_DIMENSION (0ce0) RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } 0016b024: 0000: 00000ce0 00400040 t0 write 0xce1 (0ce1) 0xce1: 00000001 0016b02c: 0000: 00000ce1 00000001 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 0016b034: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0 0016b03c: 0000: 00000cc6 00000000 t3 opcode: (null) (1d) (2 dwords) 0016b044: 0000: c0001d00 00000000 t0 write GRAS_SC_WINDOW_SCISSOR_BR (209c) GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 0016b04c: 0000: 0001209c 003f003f 00000000 t0 write RB_BIN_OFFSET (210d) RB_BIN_OFFSET: { X = 0 | Y = 0 } 0016b058: 0000: 0000210d 00000000 t0 write GRAS_SC_WINDOW_SCISSOR_BR (209c) GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 0016b060: 0000: 0001209c 003f003f 00000000 t0 write UNKNOWN_2157 (2157) UNKNOWN_2157: 0x1 0016b06c: 0000: 00002157 00000001 t3 opcode: (null) (64) (2 dwords) 0016b074: 0000: c0006400 00000001 t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:00054994 ibsize:000000f6 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00054994: 0000: c0002600 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x4 0005499c: 0000: 00000ec3 00000004 t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x68 000549a4: 0000: 00000f03 00000068 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 000549ac: 0000: c0002600 00000000 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } 000549b4: 0000: 000023c0 080004f0 t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = 0x1d } event (null) 000549bc: 0000: c0004600 0000001d t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = FACENESS_FLUSH } event FACENESS_FLUSH 000549c4: 0000: c0004600 0000001c t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 000549cc: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0 000549d4: 0000: 00000cc6 00000000 t0 write UNKNOWN_0E42 (0e42) UNKNOWN_0E42: 0 000549dc: 0000: 00000e42 00000000 t0 write HLSQ_MODE_CONTROL (0e05) HLSQ_MODE_CONTROL: 0x2 000549e4: 0000: 00000e05 00000002 t0 write UNKNOWN_0CC5 (0cc5) UNKNOWN_0CC5: 0x4 000549ec: 0000: 00000cc5 00000004 t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x7 000549f4: 0000: 000023db 00000007 t0 write VFD_CONTROL_2 (2202) VFD_CONTROL_2: 0xfcfcfcfc 000549fc: 0000: 00002202 fcfcfcfc t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } 00054a04: 0000: 00002203 fcfcfc00 t0 write VFD_CONTROL_4 (2204) VFD_CONTROL_4: 0xfcfc 00054a0c: 0000: 00002204 0000fcfc t0 write VFD_INDEX_OFFSET (2208) VFD_INDEX_OFFSET: 0 00054a14: 0000: 00002208 00000000 t0 write UNKNOWN_2209 (2209) UNKNOWN_2209: 0 00054a1c: 0000: 00002209 00000000 t0 write UNKNOWN_2152 (2152) UNKNOWN_2152: 0 UNKNOWN_2153: 0 00054a24: 0000: 00012152 00000000 00000000 t0 write UNKNOWN_2156 (2156) UNKNOWN_2156: 0 00054a30: 0000: 00002156 00000000 t0 write UNKNOWN_2154 (2154) UNKNOWN_2154: 0 00054a38: 0000: 00002154 00000000 t0 write UNKNOWN_2155 (2155) UNKNOWN_2155: 0 00054a40: 0000: 00002155 00000000 t0 write UNKNOWN_21C3 (21c3) UNKNOWN_21C3: 0x1d 00054a48: 0000: 000021c3 0000001d t0 write PC_PRIM_VTX_CNTL2 (21c5) PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 00054a50: 0000: 000021c5 00000012 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 00054a58: 0000: 000021e5 00000000 t0 write GRAS_SU_MODE_CONTROL (2078) GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } 00054a60: 0000: 00002078 00000000 t0 write UNKNOWN_2001 (2001) UNKNOWN_2001: 0 00054a68: 0000: 00002001 00000000 t0 write GRAS_CNTL (2003) GRAS_CNTL: { IJ_PERSP } 00054a70: 0000: 00002003 00000001 t0 write GRAS_CL_CLIP_CNTL (2000) GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } 00054a78: 0000: 00002000 00188000 t0 write TPL1_TP_TEX_COUNT (2381) TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } 00054a80: 0000: 00002381 00000000 t0 write TPL1_TP_FS_TEX_COUNT (23a0) TPL1_TP_FS_TEX_COUNT: 0x3 00054a88: 0000: 000023a0 00000003 t0 write RB_ALPHA_CONTROL (20f8) RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } 00054a90: 0000: 000020f8 00000e00 t0 write RB_RENDER_COMPONENTS (20fb) RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } 00054a98: 0000: 000020fb 0000000f t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 00054aa0: 0000: c0014300 00040000 00000000 t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } 00054aac: 0000: 00002200 000a0000 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } 00054ab4: 0000: 00002201 fc030000 t0 write SP_INSTR_CACHE_CTRL (22c1) SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } 00054abc: 0000: 000022c1 000005c3 t0 write HLSQ_CONTROL_1_REG (23c1) HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } 00054ac4: 0000: 000023c1 fcfc0120 t0 write HLSQ_CONTROL_2_REG (23c2) HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 00054acc: 0000: 000023c2 27f3f3f0 t0 write HLSQ_VS_CONTROL_REG (23c5) HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } 00054ad4: 0000: 000023c5 02010042 t0 write HLSQ_FS_CONTROL_REG (23c6) HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00054adc: 0000: 000023c6 0041423e t0 write HLSQ_HS_CONTROL_REG (23c7) HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00054ae4: 0000: 000023c7 00404200 t0 write HLSQ_DS_CONTROL_REG (23c8) HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00054aec: 0000: 000023c8 00404200 t0 write HLSQ_GS_CONTROL_REG (23c9) HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00054af4: 0000: 000023c9 00404200 t0 write HLSQ_CS_CONTROL_REG (23ca) HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } 00054afc: 0000: 000023ca 00004200 t0 write SP_SP_CTRL_REG (22c0) SP_SP_CTRL_REG: { 0x60010 } 00054b04: 0000: 000022c0 00060010 t0 write UNKNOWN_21E6 (21e6) UNKNOWN_21E6: 0x1 00054b0c: 0000: 000021e6 00000001 t0 write SP_VS_CTRL_REG0 (22c4) SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 00054b14: 0000: 000022c4 00200c10 t0 write SP_VS_CTRL_REG1 (22c5) SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } 00054b1c: 0000: 000022c5 01000042 t0 write VPC_ATTR (2140) VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | 0x40000000 } 00054b24: 0000: 00002140 40001004 t0 write VPC_PACK (2141) VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } 00054b2c: 0000: 00002141 00040400 t0 write PC_PRIM_VTX_CNTL (21c4) PC_PRIM_VTX_CNTL: { VAROUT = 1 } 00054b34: 0000: 000021c4 00000001 t0 write SP_VS_PARAM_REG (22c6) SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } UNKNOWN_22D7: 0xfcfc00 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 00054b3c: 0000: 001922c6 0010fc03 00001e03 00000000 00000000 00000000 00000000 00000000 * 00054b7c: 0040: 00000000 00000000 00fcfc00 00000008 00000000 00000000 00000000 00000000 * t0 write SP_VS_OBJ_OFFSET_REG (22e0) SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 00054ba8: 0000: 000022e0 00000000 t0 write SP_VS_OBJ_START (22e1) SP_VS_OBJ_START: 0x1 00054bb0: 0000: 000022e1 00000001 t0 write SP_VS_LENGTH_REG (22e5) SP_VS_LENGTH_REG: 2 00054bb8: 0000: 000022e5 00000002 t3 opcode: CP_LOAD_STATE4 (30) (67 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } :2:0000:0000[56d81803x_20020003x] (sy)(ss)(nop3) shl.b r0.w, r0.w, 2 :1:0001:0004[20150000x_00000003x] cov.s32s16 hr0.x, r0.w :0:0002:0005[00000200x_00000000x] (rpt2)nop :1:0003:0008[201100f4x_00000000x] mova a0.x, hr0.x :0:0004:0009[00000500x_00000000x] (rpt5)nop :1:0005:0015[20154003x_00000c20x] mov.s32s32 r0.w, c :1:0006:0016[20154004x_00000c21x] mov.s32s32 r1.x, c :1:0007:0017[20154005x_00000c22x] mov.s32s32 r1.y, c :1:0008:0018[20156006x_00000c23x] (ul)mov.s32s32 r1.z, c :0:0009:0019[03000000x_00000000x] end :2:0010:0020[46f00007x_20050000x] shr.b r1.w, r0.x, 5 :2:0011:0021[43980008x_201f0000x] (nop2) and.b r2.x, r0.x, 31 :2:0012:0024[43980807x_201f0007x] (nop3) and.b r1.w, r1.w, 31 :2:0013:0028[46100807x_20100007x] (nop1) mul.u24 r1.w, r1.w, 16 :3:0014:0030[62040007x_00071014x] mad.u24 r1.w, c5.x, r2.x, r1.w :0:0015:0031[00000500x_00000000x] (rpt5)nop :6:0016:0037[c2c60f00x_04800006x] stlw.u32 l[r1.w], r0.w, 4 :0:0017:0038[04800000x_00000000x] chmask :0:0018:0039[05000000x_00000000x] chsh Stats: - shaderdb: 40 instr, 24 nops, 16 non-nops, 5 mov, 1 cov - shaderdb: 0 last-baryf, 0 half, 2 full, 5 constlen - shaderdb: 27 cat0, 6 cat1, 5 cat2, 1 cat3, 0 cat4, 0 cat5, 1 cat6, 0 cat7 - shaderdb: 0 sstall, 1 (ss), 1 (sy) 00054bc0: 0000: c0413000 00a00000 00000000 20020003 56d81803 00000003 20150000 00000000 00054be0: 0020: 00000200 00000000 201100f4 00000000 00000500 00000c20 20154003 00000c21 00054c00: 0040: 20154004 00000c22 20154005 00000c23 20156006 00000000 03000000 20050000 00054c20: 0060: 46f00007 201f0000 43980008 201f0007 43980807 20100007 46100807 00071014 00054c40: 0080: 62040007 00000000 00000500 04800006 c2c60f00 00000000 04800000 00000000 00054c60: 00a0: 05000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 * t0 write GRAS_ALPHA_CONTROL (2073) GRAS_ALPHA_CONTROL: { 0x2 } 00054ccc: 0000: 00002073 00000002 t0 write GRAS_SC_CONTROL (207b) GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = 4 | MSAA_DISABLE | RASTER_MODE = 0 } 00054cd4: 0000: 0000207b 00000a08 t0 write RB_MSAA_CONTROL (20a2) RB_MSAA_CONTROL: { DISABLE | SAMPLES = 4 } 00054cdc: 0000: 000020a2 00009000 t0 write RB_RENDER_CONTROL (20a1) RB_RENDER_CONTROL: { DISABLE_COLOR_PIPE | 0x2 } 00054ce4: 0000: 000020a1 00000022 t0 write RB_CLEAR_COLOR_DW0 (20cc) RB_CLEAR_COLOR_DW0: 0xff000000 RB_CLEAR_COLOR_DW1: 0 RB_CLEAR_COLOR_DW2: 0 RB_CLEAR_COLOR_DW3: 0 00054cec: 0000: 000320cc ff000000 00000000 00000000 00000000 t0 write RB_COPY_CONTROL (20fc) RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_FOUR | MODE = RB_COPY_CLEAR | FASTCLEAR = 0xf | GMEM_BASE = 0 } RB_COPY_DEST_BASE: { BASE = 0x4f000 } RB_COPY_DEST_PITCH: { PITCH = 256 } RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_IF_ALPHA_OFF | COMPONENT_ENABLE = 0 | ENDIAN = ENDIAN_NONE | TILE = TILE4_3 } 00054d00: 0000: 000320fc 00000f22 0004f000 00000008 03000868 t0 write GRAS_SC_SCREEN_SCISSOR_TL (207c) GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } 00054d14: 0000: 0001207c 00000000 003f003f t0 write RB_FRAME_BUFFER_DIMENSION (0ce0) RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } 00054d20: 0000: 00000ce0 00400040 t0 write 0xce1 (0ce1) 0xce1: 00000000 00054d28: 0000: 00000ce1 00000000 t3 opcode: CP_LOAD_STATE4 (30) (11 dwords) { DST_OFF = 8 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } 00054d3c: 0.000000 0.000000 1.000000 1.000000 64.000000 64.000000 1.000000 1.000000 00054d3c: 0000: 00000000 00000000 3f800000 3f800000 42800000 42800000 3f800000 3f800000 00054d30: 0000: c0093000 00a00008 00000001 00000000 00000000 3f800000 3f800000 42800000 00054d50: 0020: 42800000 3f800000 3f800000 t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x80000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 2 } draw[0] register values !+ 00000004 UNKNOWN_0CC5: 0x4 + 00000000 UNKNOWN_0CC6: 0 !+ 00400040 RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } + 00000000 0xce1: 00000000 !+ 00000002 HLSQ_MODE_CONTROL: 0x2 + 00000000 UNKNOWN_0E42: 0 + 00000000 UCHE_INVALIDATE0: 0 !+ 00000012 UCHE_INVALIDATE1: 0x12 !+ 00000004 SP_MODE_CONTROL: 0x4 !+ 00000068 TPL1_TP_MODE_CONTROL: 0x68 !+ 00188000 GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } + 00000000 UNKNOWN_2001: 0 !+ 00000001 GRAS_CNTL: { IJ_PERSP } !+ 00000002 GRAS_ALPHA_CONTROL: { 0x2 } + 00000000 GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } !+ 00000a08 GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = 4 | MSAA_DISABLE | RASTER_MODE = 0 } + 00000000 GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } !+ 003f003f GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } !+ 003f003f GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } + 00000000 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } !+ 00010202 RB_MODE_CONTROL: { WIDTH = 64 | HEIGHT = 64 | ENABLE_GMEM } !+ 00000022 RB_RENDER_CONTROL: { DISABLE_COLOR_PIPE | 0x2 } !+ 00009000 RB_MSAA_CONTROL: { DISABLE | SAMPLES = 4 } !+ ff000000 RB_CLEAR_COLOR_DW0: 0xff000000 + 00000000 RB_CLEAR_COLOR_DW1: 0 + 00000000 RB_CLEAR_COLOR_DW2: 0 + 00000000 RB_CLEAR_COLOR_DW3: 0 !+ 00000e00 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } !+ 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } !+ 00000f22 RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_FOUR | MODE = RB_COPY_CLEAR | FASTCLEAR = 0xf | GMEM_BASE = 0 } !+ 0004f000 RB_COPY_DEST_BASE: { BASE = 0x4f000 } !+ 00000008 RB_COPY_DEST_PITCH: { PITCH = 256 } !+ 03000868 RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_IF_ALPHA_OFF | COMPONENT_ENABLE = 0 | ENDIAN = ENDIAN_NONE | TILE = TILE4_3 } + 00000000 RB_BIN_OFFSET: { X = 0 | Y = 0 } !+ 40001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | 0x40000000 } !+ 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } + 00000000 UNKNOWN_2152: 0 + 00000000 UNKNOWN_2153: 0 + 00000000 UNKNOWN_2154: 0 + 00000000 UNKNOWN_2155: 0 + 00000000 UNKNOWN_2156: 0 !+ 00000001 UNKNOWN_2157: 0x1 !+ 0000001d UNKNOWN_21C3: 0x1d !+ 00000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 } !+ 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + 00000000 PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } !+ 00000001 UNKNOWN_21E6: 0x1 !+ 000a0000 VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } !+ fc030000 VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } !+ fcfcfcfc VFD_CONTROL_2: 0xfcfcfcfc !+ fcfcfc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } !+ 0000fcfc VFD_CONTROL_4: 0xfcfc + 00000000 VFD_INDEX_OFFSET: 0 + 00000000 UNKNOWN_2209: 0 !+ 00060010 SP_SP_CTRL_REG: { 0x60010 } !+ 000005c3 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } !+ 00200c10 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } !+ 01000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } !+ 0010fc03 SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } !+ 00001e03 SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } !+ 00fcfc00 UNKNOWN_22D7: 0xfcfc00 !+ 00000008 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } !+ 00000001 SP_VS_OBJ_START: 0x1 !+ 00000002 SP_VS_LENGTH_REG: 2 + 00000000 TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } !+ 00000003 TPL1_TP_FS_TEX_COUNT: 0x3 !+ 080004f0 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } !+ fcfc0120 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } !+ 27f3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } !+ 02010042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } !+ 0041423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } !+ 00404200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } !+ 00404200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } !+ 00404200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } !+ 00004200 HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } !+ 00000007 HLSQ_UPDATE_CONTROL: 0x7 00054d5c: 0000: c0023800 00080888 00000001 00000002 0016b07c: 0000: c0013f00 00054994 000000f6 t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:00054d6c ibsize:00000037 t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } 00054d6c: 0000: 00002200 000a0000 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00054d74: 0000: c0002600 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x1e 00054d7c: 0000: 00000ec3 0000001e t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x28 00054d84: 0000: 00000f03 00000028 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00054d8c: 0000: c0002600 00000000 t0 write HLSQ_MODE_CONTROL (0e05) HLSQ_MODE_CONTROL: 0x1 00054d94: 0000: 00000e05 00000001 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0x600a0 } 00054d9c: 0000: 000023c0 080604f0 t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x7 00054da4: 0000: 000023db 00000007 t0 write PC_RESTART_INDEX (21c6) PC_RESTART_INDEX: 0xffffffff 00054dac: 0000: 000021c6 ffffffff t0 write UNKNOWN_21E6 (21e6) UNKNOWN_21E6: 0x1 00054db4: 0000: 000021e6 00000001 t0 write UNKNOWN_21C3 (21c3) UNKNOWN_21C3: 0x1f 00054dbc: 0000: 000021c3 0000001f t0 write TPL1_TP_TEX_OFFSET (2380) TPL1_TP_TEX_OFFSET: 0x808 00054dc4: 0000: 00002380 00000808 t0 write GRAS_SU_POINT_MINMAX (2070) GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 4092.000000 } GRAS_SU_POINT_SIZE: 0.500000 00054dcc: 0000: 00012070 ffc00010 00000008 t0 write UNKNOWN_2152 (2152) UNKNOWN_2152: 0 UNKNOWN_2153: 0 00054dd8: 0000: 00012152 00000000 00000000 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00054de4: 0000: c0002600 00000000 t0 write UNKNOWN_0CC5 (0cc5) UNKNOWN_0CC5: 0x4 00054dec: 0000: 00000cc5 00000004 t0 write 0xcc4 (0cc4) 0xcc4: 00000000 00054df4: 0000: 00000cc4 00000000 t0 write 0xd03 (0d03) 0xd03: 80200000 00054dfc: 0000: 00000d03 80200000 t0 write UNKNOWN_0EC2 (0ec2) UNKNOWN_0EC2: 0x40000 00054e04: 0000: 00000ec2 00040000 t0 write VPC_DEBUG_ECO_CONTROL (0e64) VPC_DEBUG_ECO_CONTROL: 0x100 00054e0c: 0000: 00000e64 00000100 t0 write UNKNOWN_0E42 (0e42) UNKNOWN_0E42: 0 00054e14: 0000: 00000e42 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x1e 00054e1c: 0000: 00000ec3 0000001e t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x28 00054e24: 0000: 00000f03 00000028 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 00054e2c: 0000: c0014300 00040000 00000000 t0 write VFD_INDEX_OFFSET (2208) VFD_INDEX_OFFSET: 0 00054e38: 0000: 00002208 00000000 t0 write UNKNOWN_2209 (2209) UNKNOWN_2209: 0 00054e40: 0000: 00002209 00000000 0016b088: 0000: c0013f00 00054d6c 00000037 t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:00055328 ibsize:000000ac t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x3 00055328: 0000: 000023db 00000003 t0 write SP_INSTR_CACHE_CTRL (22c1) SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } 00055330: 0000: 000022c1 000005c3 t0 write HLSQ_CONTROL_1_REG (23c1) HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x1008 } 00055338: 0000: 000023c1 fcfc1108 t0 write HLSQ_CONTROL_2_REG (23c2) HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 00055340: 0000: 000023c2 fff3f3f0 t0 write HLSQ_VS_CONTROL_REG (23c5) HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 2 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 1 } 00055348: 0000: 000023c5 01010002 t0 write HLSQ_HS_CONTROL_REG (23c7) HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 00055350: 0000: 000023c7 007e0200 t0 write HLSQ_DS_CONTROL_REG (23c8) HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 00055358: 0000: 000023c8 007e0200 t0 write HLSQ_GS_CONTROL_REG (23c9) HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 00055360: 0000: 000023c9 007e0200 t0 write HLSQ_FS_CONTROL_REG (23c6) HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 2 | CONSTOBJECTOFFSET = 2 | ENABLED | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 } 00055368: 0000: 000023c6 017f0202 t0 write SP_VS_OBJ_OFFSET_REG (22e0) SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 00055370: 0000: 000022e0 00000000 t0 write SP_HS_OBJ_OFFSET_REG (230d) SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } 00055378: 0000: 0000230d 7e020000 t0 write SP_DS_OBJ_OFFSET_REG (2334) SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } 00055380: 0000: 00002334 7e020000 t0 write SP_GS_OBJ_OFFSET_REG (235b) SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } 00055388: 0000: 0000235b 7e020000 t0 write SP_FS_OBJ_OFFSET_REG (22ea) SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } 00055390: 0000: 000022ea 7e020000 t0 write SP_VS_OBJ_START (22e1) SP_VS_OBJ_START: 0x49000 00049000: 0000: 00000000 13000000 00000000 00000000 00000000 00000000 00000000 00000000 * :0:0000:0000[13000000x_00000000x] (sy)end :0:0001:0001[00000000x_00000000x] nop :0:0002:0002[00000000x_00000000x] nop :0:0003:0003[00000000x_00000000x] nop :0:0004:0004[00000000x_00000000x] nop Stats: - shaderdb: 5 instr, 4 nops, 1 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 0 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 0 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) 00055398: 0000: 000022e1 00049000 t0 write SP_HS_OBJ_START (230e) SP_HS_OBJ_START: 0 000553a0: 0000: 0000230e 00000000 t0 write SP_DS_OBJ_START (2335) SP_DS_OBJ_START: 0 000553a8: 0000: 00002335 00000000 t0 write SP_GS_OBJ_START (235c) SP_GS_OBJ_START: 0 000553b0: 0000: 0000235c 00000000 t0 write SP_VS_LENGTH_REG (22e5) SP_VS_LENGTH_REG: 1 000553b8: 0000: 000022e5 00000001 t3 opcode: CP_LOAD_STATE4 (30) (3 dwords) { DST_OFF = 0 | STATE_SRC = SS4_INDIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 1 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0x49000 } :0:0000:0000[13000000x_00000000x] (sy)end :0:0001:0001[00000000x_00000000x] nop :0:0002:0002[00000000x_00000000x] nop :0:0003:0003[00000000x_00000000x] nop :0:0004:0004[00000000x_00000000x] nop Stats: - shaderdb: 5 instr, 4 nops, 1 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 0 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 0 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) 000553c0: 0000: c0013000 00620000 00049000 t0 write 0x2072 (2072) 0x2072: 00000000 000553cc: 0000: 00002072 00000000 t0 write UNKNOWN_2155 (2155) UNKNOWN_2155: 0 000553d4: 0000: 00002155 00000000 t0 write GRAS_CNTL (2003) GRAS_CNTL: { IJ_PERSP } 000553dc: 0000: 00002003 00000001 t0 write VPC_VARYING_INTERP[0].MODE (2142) VPC_VARYING_INTERP[0].MODE: 0 000553e4: 0000: 00002142 00000000 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0x600a0 } 000553ec: 0000: 000023c0 080604f0 t0 write HLSQ_CONTROL_3_REG (23c3) HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } 000553f4: 0000: 000023c3 fcfcfc00 t0 write HLSQ_CONTROL_4_REG (23c4) HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r0.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } 000553fc: 0000: 000023c4 00fcfc00 t0 write SP_FS_CTRL_REG0 (22e8) SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE } SP_FS_CTRL_REG1: { CONSTLENGTH = 2 | VARYING | 0x80000000 } 00055404: 0000: 000122e8 00340412 80100002 t0 write SP_FS_OBJ_START (22eb) SP_FS_OBJ_START: 0x46000 00046000: 0000: 00002000 5730cb00 00000000 03000000 00000000 00000000 00000000 00000000 * :2:0000:0000[5730cb00x_00002000x] (sy)(rpt3)bary.f (ei)hr0.x, (r)0, r0.x :0:0001:0004[03000000x_00000000x] end :0:0002:0005[00000000x_00000000x] nop :0:0003:0006[00000000x_00000000x] nop :0:0004:0007[00000000x_00000000x] nop :0:0005:0008[00000000x_00000000x] nop Stats: - shaderdb: 9 instr, 4 nops, 5 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 1 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 4 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) 00055410: 0000: 000022eb 00046000 t0 write SP_FS_LENGTH_REG (22ef) SP_FS_LENGTH_REG: 1 00055418: 0000: 000022ef 00000001 t0 write RB_RENDER_COMPONENTS (20fb) RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } 00055420: 0000: 000020fb 0000000f t3 opcode: CP_LOAD_STATE4 (30) (3 dwords) { DST_OFF = 0 | STATE_SRC = SS4_INDIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 1 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0x46000 } :2:0000:0000[5730cb00x_00002000x] (sy)(rpt3)bary.f (ei)hr0.x, (r)0, r0.x :0:0001:0004[03000000x_00000000x] end :0:0002:0005[00000000x_00000000x] nop :0:0003:0006[00000000x_00000000x] nop :0:0004:0007[00000000x_00000000x] nop :0:0005:0008[00000000x_00000000x] nop Stats: - shaderdb: 9 instr, 4 nops, 5 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 1 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 4 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) 00055428: 0000: c0013000 00720000 00046000 t0 write SP_SP_CTRL_REG (22c0) SP_SP_CTRL_REG: { 0x60010 } 00055434: 0000: 000022c0 00060010 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 28 | GROUP_ID = 3 } { ADDR_LO = 0x99060 } 0005543c: 0000: c0014300 0300001c 00099060 t0 write RB_DEPTH_INFO (2103) RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTH4_NONE | DEPTH_BASE = 0 } RB_DEPTH_PITCH: 0 RB_DEPTH_PITCH2: 0 00055448: 0000: 00022103 00000000 00000000 00000000 t0 write GRAS_DEPTH_CONTROL (2077) GRAS_DEPTH_CONTROL: { FORMAT = DEPTH4_NONE } 00055458: 0000: 00002077 00000000 t0 write RB_STENCIL_INFO (2108) RB_STENCIL_INFO: { STENCIL_BASE = 0 } RB_STENCIL_PITCH: 0 0x210a: 00000000 00055460: 0000: 00022108 00000000 00000000 00000000 t0 write 0x2002 (2002) 0x2002: 00000000 00055470: 0000: 00002002 00000000 t0 write RB_ALPHA_CONTROL (20f8) RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } 00055478: 0000: 000020f8 00000e00 t0 write RB_MRT[0].CONTROL (20a4) RB_MRT[0].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0x7 } 00055480: 0000: 000020a4 07000c00 t0 write RB_MRT[0].BLEND_CONTROL (20a8) RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } 00055488: 0000: 000020a8 00000000 t0 write GRAS_CL_CLIP_CNTL (2000) GRAS_CL_CLIP_CNTL: { 0x80000 } 00055490: 0000: 00002000 00080000 t0 write GRAS_SU_POLY_OFFSET_SCALE (2074) GRAS_SU_POLY_OFFSET_SCALE: 0.000000 GRAS_SU_POLY_OFFSET_OFFSET: 0.000000 GRAS_SU_POLY_OFFSET_CLAMP: 0.000000 00055498: 0000: 00022074 00000000 00000000 00000000 t0 write GRAS_SU_MODE_CONTROL (2078) GRAS_SU_MODE_CONTROL: { FRONT_CW | LINEHALFWIDTH = 0.500000 | MSAA_ENABLE | RENDERING_PASS } 000554a8: 0000: 00002078 00102014 t0 write GRAS_SC_SCREEN_SCISSOR_TL (207c) GRAS_SC_SCREEN_SCISSOR_TL: { X = 2 | Y = 13 } GRAS_SC_SCREEN_SCISSOR_BR: { X = 33 | Y = 44 } 000554b0: 0000: 0001207c 000d0002 002c0021 t0 write GRAS_CL_VPORT_XOFFSET_0 (2008) GRAS_CL_VPORT_XOFFSET_0: 18.000000 GRAS_CL_VPORT_XSCALE_0: 16.000000 GRAS_CL_VPORT_YOFFSET_0: 29.000000 GRAS_CL_VPORT_YSCALE_0: 16.000000 GRAS_CL_VPORT_ZOFFSET_0: 0.500000 GRAS_CL_VPORT_ZSCALE_0: 0.500000 000554bc: 0000: 00052008 41900000 41800000 41e80000 41800000 3f000000 3f000000 t0 write GRAS_CL_GB_CLIP_ADJ (2004) GRAS_CL_GB_CLIP_ADJ: { HORZ = 511 | VERT = 511 } 000554d8: 0000: 00002004 0007fdff t0 write GRAS_SC_CONTROL (207b) GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 4 | RASTER_MODE = 0 } 000554e0: 0000: 0000207b 00000200 t0 write 0x2382 (2382) 0x2382: 00000002 000554e8: 0000: 00002382 00000002 t0 write RB_MSAA_CONTROL (20a2) RB_MSAA_CONTROL: { SAMPLES = 4 } 000554f0: 0000: 000020a2 00008000 t0 write RB_RENDER_CONTROL2 (20a3) RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 4 | IJ_PERSP_PIXEL } 000554f8: 0000: 000020a3 00001200 t0 write RB_MRT[0].BUF_INFO (20a5) RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB4_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_ALWAYS | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 1024 } RB_MRT[0].BASE: 0 RB_MRT[0].CONTROL3: { STRIDE = 64 } 00055500: 0000: 000220a5 0010029a 00000000 00000200 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 43 | GROUP_ID = 2 } { ADDR_LO = 0x990d0 } 00055510: 0000: c0014300 0200002b 000990d0 t0 write 0x215c (215c) 0x215c: 00000000 0x215d: 00000000 0005551c: 0000: 0001215c 00000000 00000000 t0 write 0x215f (215f) 0x215f: 00000000 00055528: 0000: 0000215f 00000000 t0 write 0x215e (215e) 0x215e: 00000000 00055530: 0000: 0000215e 00000000 t0 write 0x2161 (2161) 0x2161: 00000000 0x2162: 00000000 00055538: 0000: 00012161 00000000 00000000 t0 write 0x2164 (2164) 0x2164: 00000000 00055544: 0000: 00002164 00000000 t0 write 0x2163 (2163) 0x2163: 00000000 0005554c: 0000: 00002163 00000000 t0 write 0x2166 (2166) 0x2166: 00000000 0x2167: 00000000 00055554: 0000: 00012166 00000000 00000000 t0 write 0x2169 (2169) 0x2169: 00000000 00055560: 0000: 00002169 00000000 t0 write 0x2168 (2168) 0x2168: 00000000 00055568: 0000: 00002168 00000000 t0 write 0x216b (216b) 0x216b: 00000000 0x216c: 00000000 00055570: 0000: 0001216b 00000000 00000000 t0 write VPC_SO_FLUSH_WADDR_3 (216e) VPC_SO_FLUSH_WADDR_3: 0 0005557c: 0000: 0000216e 00000000 t0 write 0x216d (216d) 0x216d: 00000000 00055584: 0000: 0000216d 00000000 t0 write UNKNOWN_2156 (2156) UNKNOWN_2156: 0 0005558c: 0000: 00002156 00000000 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 18 | GROUP_ID = 1 } { ADDR_LO = 0x99180 } 00055594: 0000: c0014300 01000012 00099180 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 15 | GROUP_ID = 0 } { ADDR_LO = 0x991d0 } 000555a0: 0000: c0014300 0000000f 000991d0 group_id: 0 count: 15 addr: 00000000000991d0 flags: 0 000991d0: 0000: 00002073 00000000 00002101 00000000 00002106 00000000 000021e5 00000000 000991f0: 0020: 0001210b 00000000 00000000 00002381 00000000 000023a0 00000000 t0 write GRAS_ALPHA_CONTROL (2073) GRAS_ALPHA_CONTROL: { 0 } 000991d0: 0000: 00002073 00000000 t0 write RB_DEPTH_CONTROL (2101) RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } 000991d8: 0000: 00002101 00000000 t0 write RB_STENCIL_CONTROL (2106) RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } 000991e0: 0000: 00002106 00000000 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 000991e8: 0000: 000021e5 00000000 t0 write RB_STENCILREFMASK (210b) RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 000991f0: 0000: 0001210b 00000000 00000000 t0 write TPL1_TP_TEX_COUNT (2381) TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } 000991fc: 0000: 00002381 00000000 t0 write TPL1_TP_FS_TEX_COUNT (23a0) TPL1_TP_FS_TEX_COUNT: 0 00099204: 0000: 000023a0 00000000 group_id: 1 count: 18 addr: 0000000000099180 flags: 0 00099180: 0000: 00002200 082a0008 00002201 fcfc0081 00002203 0000fc00 0007220a 0008080f 000991a0: 0020: 00099000 00000060 00000001 0000080f 00099030 00000030 00000001 0001228a 000991c0: 0040: 7000411f 3000011f t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } 00099180: 0000: 00002200 082a0008 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } 00099188: 0000: 00002201 fcfc0081 t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } 00099190: 0000: 00002203 0000fc00 t0 write VFD_FETCH[0].INSTR_0 (220a) VFD_FETCH[0].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 | SWITCHNEXT } VFD_FETCH[0].INSTR_1: 0x99000 VFD_FETCH[0].INSTR_2: { SIZE = 0x60 } VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 } VFD_FETCH[0x1].INSTR_1: 0x99030 VFD_FETCH[0x1].INSTR_2: { SIZE = 0x30 } VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } 00099198: 0000: 0007220a 0008080f 00099000 00000060 00000001 0000080f 00099030 00000030 000991b8: 0020: 00000001 t0 write VFD_DECODE[0].INSTR (228a) VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID | SWITCHNEXT } VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID } 000991bc: 0000: 0001228a 7000411f 3000011f group_id: 2 count: 43 addr: 00000000000990d0 flags: 0 000990d0: 0000: 000020a1 00000000 000022f1 0001a100 000022f0 fc00fc01 00002100 00000001 000990f0: 0020: 000021e5 00000000 000020f9 ffff0501 0000214a 00000000 00002140 42001004 00099110: 0040: 001922c6 0010fc04 00001e00 00000000 00000000 00000000 00000000 00000000 * 00099150: 0080: 00000000 00000000 00fcfc00 00000008 00000000 00000000 00000000 00000000 * t0 write RB_RENDER_CONTROL (20a1) RB_RENDER_CONTROL: { 0 } 000990d0: 0000: 000020a1 00000000 t0 write SP_FS_MRT[0].REG (22f1) SP_FS_MRT[0].REG: { REGID = r0.x | HALF_PRECISION | MRTFORMAT = RB4_R8G8B8A8_UNORM } 000990d8: 0000: 000022f1 0001a100 t0 write SP_FS_OUTPUT_REG (22f0) SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 000990e0: 0000: 000022f0 fc00fc01 t0 write RB_FS_OUTPUT_REG (2100) RB_FS_OUTPUT_REG: { MRT = 1 } 000990e8: 0000: 00002100 00000001 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 000990f0: 0000: 000021e5 00000000 t0 write RB_FS_OUTPUT (20f9) RB_FS_OUTPUT: { ENABLE_BLEND = 0x1 | INDEPENDENT_BLEND | SAMPLE_MASK = 0xffff | 0x400 } 000990f8: 0000: 000020f9 ffff0501 t0 write VPC_VARYING_PS_REPL[0].MODE (214a) VPC_VARYING_PS_REPL[0].MODE: 0 00099100: 0000: 0000214a 00000000 t0 write VPC_ATTR (2140) VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 } 00099108: 0000: 00002140 42001004 t0 write SP_VS_PARAM_REG (22c6) SP_VS_PARAM_REG: { POSREGID = r1.x | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } SP_VS_OUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } UNKNOWN_22D7: 0xfcfc00 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 00099110: 0000: 001922c6 0010fc04 00001e00 00000000 00000000 00000000 00000000 00000000 * 00099150: 0040: 00000000 00000000 00fcfc00 00000008 00000000 00000000 00000000 00000000 * group_id: 3 count: 28 addr: 0000000000099060 flags: 0 00099060: 0000: 000021c4 02000001 00002141 00040400 00002001 00000000 000022c4 00200800 00099080: 0020: 000022c5 08000002 0000230c 00000000 00002318 00000000 00002319 00000000 000990a0: 0040: 00002340 00000000 00002202 fcfcfcfc 00002204 0000fcfc 00002154 00000000 000990c0: 0060: 000021e7 00000000 000021c5 00000012 t0 write PC_PRIM_VTX_CNTL (21c4) PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } 00099060: 0000: 000021c4 02000001 t0 write VPC_PACK (2141) VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } 00099068: 0000: 00002141 00040400 t0 write UNKNOWN_2001 (2001) UNKNOWN_2001: 0 00099070: 0000: 00002001 00000000 t0 write SP_VS_CTRL_REG0 (22c4) SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 2 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 00099078: 0000: 000022c4 00200800 t0 write SP_VS_CTRL_REG1 (22c5) SP_VS_CTRL_REG1: { CONSTLENGTH = 2 | INITIALOUTSTANDING = 8 } 00099080: 0000: 000022c5 08000002 t0 write 0x230c (230c) 0x230c: 00000000 00099088: 0000: 0000230c 00000000 t0 write 0x2318 (2318) 0x2318: 00000000 00099090: 0000: 00002318 00000000 t0 write 0x2319 (2319) 0x2319: 00000000 00099098: 0000: 00002319 00000000 t0 write 0x2340 (2340) 0x2340: 00000000 000990a0: 0000: 00002340 00000000 t0 write VFD_CONTROL_2 (2202) VFD_CONTROL_2: 0xfcfcfcfc 000990a8: 0000: 00002202 fcfcfcfc t0 write VFD_CONTROL_4 (2204) VFD_CONTROL_4: 0xfcfc 000990b0: 0000: 00002204 0000fcfc t0 write UNKNOWN_2154 (2154) UNKNOWN_2154: 0 000990b8: 0000: 00002154 00000000 t0 write PC_HS_PARAM (21e7) PC_HS_PARAM: { VERTICES_OUT = 0 | SPACING = EQUAL_SPACING } 000990c0: 0000: 000021e7 00000000 t0 write PC_PRIM_VTX_CNTL2 (21c5) PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 000990c8: 0000: 000021c5 00000012 t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = USE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x200000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 3 } draw[1] register values + 00000000 0xcc4: 00000000 + 00000004 UNKNOWN_0CC5: 0x4 !+ 80200000 0xd03: 80200000 !+ 00000001 HLSQ_MODE_CONTROL: 0x1 + 00000000 UNKNOWN_0E42: 0 !+ 00000100 VPC_DEBUG_ECO_CONTROL: 0x100 !+ 00040000 UNKNOWN_0EC2: 0x40000 !+ 0000001e SP_MODE_CONTROL: 0x1e !+ 00000028 TPL1_TP_MODE_CONTROL: 0x28 !+ 00080000 GRAS_CL_CLIP_CNTL: { 0x80000 } + 00000000 UNKNOWN_2001: 0 + 00000000 0x2002: 00000000 + 00000001 GRAS_CNTL: { IJ_PERSP } !+ 0007fdff GRAS_CL_GB_CLIP_ADJ: { HORZ = 511 | VERT = 511 } !+ 41900000 GRAS_CL_VPORT_XOFFSET_0: 18.000000 !+ 41800000 GRAS_CL_VPORT_XSCALE_0: 16.000000 !+ 41e80000 GRAS_CL_VPORT_YOFFSET_0: 29.000000 !+ 41800000 GRAS_CL_VPORT_YSCALE_0: 16.000000 !+ 3f000000 GRAS_CL_VPORT_ZOFFSET_0: 0.500000 !+ 3f000000 GRAS_CL_VPORT_ZSCALE_0: 0.500000 !+ ffc00010 GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 4092.000000 } !+ 00000008 GRAS_SU_POINT_SIZE: 0.500000 + 00000000 0x2072: 00000000 !+ 00000000 GRAS_ALPHA_CONTROL: { 0 } + 00000000 GRAS_SU_POLY_OFFSET_SCALE: 0.000000 + 00000000 GRAS_SU_POLY_OFFSET_OFFSET: 0.000000 + 00000000 GRAS_SU_POLY_OFFSET_CLAMP: 0.000000 + 00000000 GRAS_DEPTH_CONTROL: { FORMAT = DEPTH4_NONE } !+ 00102014 GRAS_SU_MODE_CONTROL: { FRONT_CW | LINEHALFWIDTH = 0.500000 | MSAA_ENABLE | RENDERING_PASS } !+ 00000200 GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 4 | RASTER_MODE = 0 } !+ 000d0002 GRAS_SC_SCREEN_SCISSOR_TL: { X = 2 | Y = 13 } !+ 002c0021 GRAS_SC_SCREEN_SCISSOR_BR: { X = 33 | Y = 44 } !+ 00000000 RB_RENDER_CONTROL: { 0 } !+ 00008000 RB_MSAA_CONTROL: { SAMPLES = 4 } !+ 00001200 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 4 | IJ_PERSP_PIXEL } !+ 07000c00 RB_MRT[0].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0x7 } !+ 0010029a RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB4_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_ALWAYS | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 1024 } + 00000000 RB_MRT[0].BASE: 0 !+ 00000200 RB_MRT[0].CONTROL3: { STRIDE = 64 } + 00000000 RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } + 00000e00 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } !+ ffff0501 RB_FS_OUTPUT: { ENABLE_BLEND = 0x1 | INDEPENDENT_BLEND | SAMPLE_MASK = 0xffff | 0x400 } + 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } !+ 00000001 RB_FS_OUTPUT_REG: { MRT = 1 } + 00000000 RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } + 00000000 RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTH4_NONE | DEPTH_BASE = 0 } + 00000000 RB_DEPTH_PITCH: 0 + 00000000 RB_DEPTH_PITCH2: 0 + 00000000 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } + 00000000 RB_STENCIL_INFO: { STENCIL_BASE = 0 } + 00000000 RB_STENCIL_PITCH: 0 + 00000000 0x210a: 00000000 + 00000000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } + 00000000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } !+ 42001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 } + 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } + 00000000 VPC_VARYING_INTERP[0].MODE: 0 + 00000000 VPC_VARYING_PS_REPL[0].MODE: 0 + 00000000 UNKNOWN_2152: 0 + 00000000 UNKNOWN_2153: 0 + 00000000 UNKNOWN_2154: 0 + 00000000 UNKNOWN_2155: 0 + 00000000 UNKNOWN_2156: 0 + 00000000 0x215c: 00000000 + 00000000 0x215d: 00000000 + 00000000 0x215e: 00000000 + 00000000 0x215f: 00000000 + 00000000 0x2161: 00000000 + 00000000 0x2162: 00000000 + 00000000 0x2163: 00000000 + 00000000 0x2164: 00000000 + 00000000 0x2166: 00000000 + 00000000 0x2167: 00000000 + 00000000 0x2168: 00000000 + 00000000 0x2169: 00000000 + 00000000 0x216b: 00000000 + 00000000 0x216c: 00000000 + 00000000 0x216d: 00000000 + 00000000 VPC_SO_FLUSH_WADDR_3: 0 !+ 0000001f UNKNOWN_21C3: 0x1f !+ 02000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } !+ ffffffff PC_RESTART_INDEX: 0xffffffff + 00000000 PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } + 00000001 UNKNOWN_21E6: 0x1 + 00000000 PC_HS_PARAM: { VERTICES_OUT = 0 | SPACING = EQUAL_SPACING } !+ 082a0008 VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } !+ fcfc0081 VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } + fcfcfcfc VFD_CONTROL_2: 0xfcfcfcfc !+ 0000fc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } + 0000fcfc VFD_CONTROL_4: 0xfcfc + 00000000 VFD_INDEX_OFFSET: 0 + 00000000 UNKNOWN_2209: 0 !+ 0008080f VFD_FETCH[0].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 | SWITCHNEXT } !+ 00099000 VFD_FETCH[0].INSTR_1: 0x99000 !+ 00000060 VFD_FETCH[0].INSTR_2: { SIZE = 0x60 } !+ 00000001 VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } !+ 0000080f VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 } !+ 00099030 VFD_FETCH[0x1].INSTR_1: 0x99030 !+ 00000030 VFD_FETCH[0x1].INSTR_2: { SIZE = 0x30 } !+ 00000001 VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } !+ 7000411f VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID | SWITCHNEXT } !+ 3000011f VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID } + 00060010 SP_SP_CTRL_REG: { 0x60010 } + 000005c3 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } !+ 00200800 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 2 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } !+ 08000002 SP_VS_CTRL_REG1: { CONSTLENGTH = 2 | INITIALOUTSTANDING = 8 } !+ 0010fc04 SP_VS_PARAM_REG: { POSREGID = r1.x | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } !+ 00001e00 SP_VS_OUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00fcfc00 UNKNOWN_22D7: 0xfcfc00 + 00000008 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } !+ 00049000 SP_VS_OBJ_START: 0x49000 00049000: 0000: 00000000 13000000 00000000 00000000 00000000 00000000 00000000 00000000 * :0:0000:0000[13000000x_00000000x] (sy)end :0:0001:0001[00000000x_00000000x] nop :0:0002:0002[00000000x_00000000x] nop :0:0003:0003[00000000x_00000000x] nop :0:0004:0004[00000000x_00000000x] nop Stats: - shaderdb: 5 instr, 4 nops, 1 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 0 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 0 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) !+ 00000001 SP_VS_LENGTH_REG: 1 !+ 00340412 SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE } !+ 80100002 SP_FS_CTRL_REG1: { CONSTLENGTH = 2 | VARYING | 0x80000000 } !+ 7e020000 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } !+ 00046000 SP_FS_OBJ_START: 0x46000 00046000: 0000: 00002000 5730cb00 00000000 03000000 00000000 00000000 00000000 00000000 * :2:0000:0000[5730cb00x_00002000x] (sy)(rpt3)bary.f (ei)hr0.x, (r)0, r0.x :0:0001:0004[03000000x_00000000x] end :0:0002:0005[00000000x_00000000x] nop :0:0003:0006[00000000x_00000000x] nop :0:0004:0007[00000000x_00000000x] nop :0:0005:0008[00000000x_00000000x] nop Stats: - shaderdb: 9 instr, 4 nops, 5 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 1 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 4 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) !+ 00000001 SP_FS_LENGTH_REG: 1 !+ fc00fc01 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r63.x } !+ 0001a100 SP_FS_MRT[0].REG: { REGID = r0.x | HALF_PRECISION | MRTFORMAT = RB4_R8G8B8A8_UNORM } + 00000000 0x230c: 00000000 !+ 7e020000 SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } + 00000000 SP_HS_OBJ_START: 0 + 00000000 0x2318: 00000000 + 00000000 0x2319: 00000000 !+ 7e020000 SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } + 00000000 SP_DS_OBJ_START: 0 + 00000000 0x2340: 00000000 !+ 7e020000 SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } + 00000000 SP_GS_OBJ_START: 0 !+ 00000808 TPL1_TP_TEX_OFFSET: 0x808 + 00000000 TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } !+ 00000002 0x2382: 00000002 !+ 00000000 TPL1_TP_FS_TEX_COUNT: 0 !+ 080604f0 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0x600a0 } !+ fcfc1108 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x1008 } !+ fff3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } !+ fcfcfc00 HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } !+ 00fcfc00 HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r0.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } !+ 01010002 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 2 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 1 } !+ 017f0202 HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 2 | CONSTOBJECTOFFSET = 2 | ENABLED | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 } !+ 007e0200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } !+ 007e0200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } !+ 007e0200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } !+ 00000003 HLSQ_UPDATE_CONTROL: 0x3 000555ac: 0000: c0023800 00200984 00000001 00000003 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 18 | GROUP_ID = 1 } { ADDR_LO = 0x99340 } 000555bc: 0000: c0014300 01000012 00099340 group_id: 1 count: 18 addr: 0000000000099340 flags: 0 00099340: 0000: 00002200 082a0008 00002201 fcfc0081 00002203 0000fc00 0007220a 0008080f 00099360: 0020: 000992e0 00000060 00000001 0000080f 00099310 00000030 00000001 0001228a 00099380: 0040: 7000411f 3000011f t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } 00099340: 0000: 00002200 082a0008 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } 00099348: 0000: 00002201 fcfc0081 t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } 00099350: 0000: 00002203 0000fc00 t0 write VFD_FETCH[0].INSTR_0 (220a) VFD_FETCH[0].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 | SWITCHNEXT } VFD_FETCH[0].INSTR_1: 0x992e0 VFD_FETCH[0].INSTR_2: { SIZE = 0x60 } VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 } VFD_FETCH[0x1].INSTR_1: 0x99310 VFD_FETCH[0x1].INSTR_2: { SIZE = 0x30 } VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } 00099358: 0000: 0007220a 0008080f 000992e0 00000060 00000001 0000080f 00099310 00000030 00099378: 0020: 00000001 t0 write VFD_DECODE[0].INSTR (228a) VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID | SWITCHNEXT } VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID } 0009937c: 0000: 0001228a 7000411f 3000011f t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = USE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x200000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 3 } draw[2] register values + 082a0008 VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } + fcfc0081 VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } + 0000fc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } + 0008080f VFD_FETCH[0].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 | SWITCHNEXT } !+ 000992e0 VFD_FETCH[0].INSTR_1: 0x992e0 + 00000060 VFD_FETCH[0].INSTR_2: { SIZE = 0x60 } + 00000001 VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } + 0000080f VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 } !+ 00099310 VFD_FETCH[0x1].INSTR_1: 0x99310 + 00000030 VFD_FETCH[0x1].INSTR_2: { SIZE = 0x30 } + 00000001 VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } + 7000411f VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID | SWITCHNEXT } + 3000011f VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID } 000555c8: 0000: c0023800 00200984 00000001 00000003 0016b094: 0000: c0013f00 00055328 000000ac t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 0016b0a0: 0000: c0014300 00040000 00000000 t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:00170000 ibsize:000000f7 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00170000: 0000: c0002600 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x4 00170008: 0000: 00000ec3 00000004 t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x68 00170010: 0000: 00000f03 00000068 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00170018: 0000: c0002600 00000000 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } 00170020: 0000: 000023c0 080004f0 t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = 0x1d } event (null) 00170028: 0000: c0004600 0000001d t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = FACENESS_FLUSH } event FACENESS_FLUSH 00170030: 0000: c0004600 0000001c t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00170038: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0 00170040: 0000: 00000cc6 00000000 t0 write UNKNOWN_0E42 (0e42) UNKNOWN_0E42: 0 00170048: 0000: 00000e42 00000000 t0 write HLSQ_MODE_CONTROL (0e05) HLSQ_MODE_CONTROL: 0x2 00170050: 0000: 00000e05 00000002 t0 write UNKNOWN_0CC5 (0cc5) UNKNOWN_0CC5: 0x4 00170058: 0000: 00000cc5 00000004 t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x7 00170060: 0000: 000023db 00000007 t0 write VFD_CONTROL_2 (2202) VFD_CONTROL_2: 0xfcfcfcfc 00170068: 0000: 00002202 fcfcfcfc t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } 00170070: 0000: 00002203 fcfcfc00 t0 write VFD_CONTROL_4 (2204) VFD_CONTROL_4: 0xfcfc 00170078: 0000: 00002204 0000fcfc t0 write VFD_INDEX_OFFSET (2208) VFD_INDEX_OFFSET: 0 00170080: 0000: 00002208 00000000 t0 write UNKNOWN_2209 (2209) UNKNOWN_2209: 0 00170088: 0000: 00002209 00000000 t0 write UNKNOWN_2152 (2152) UNKNOWN_2152: 0 UNKNOWN_2153: 0 00170090: 0000: 00012152 00000000 00000000 t0 write UNKNOWN_2156 (2156) UNKNOWN_2156: 0 0017009c: 0000: 00002156 00000000 t0 write UNKNOWN_2154 (2154) UNKNOWN_2154: 0 001700a4: 0000: 00002154 00000000 t0 write UNKNOWN_2155 (2155) UNKNOWN_2155: 0 001700ac: 0000: 00002155 00000000 t0 write UNKNOWN_21C3 (21c3) UNKNOWN_21C3: 0x1d 001700b4: 0000: 000021c3 0000001d t0 write PC_PRIM_VTX_CNTL2 (21c5) PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 001700bc: 0000: 000021c5 00000012 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 001700c4: 0000: 000021e5 00000000 t0 write GRAS_SU_MODE_CONTROL (2078) GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } 001700cc: 0000: 00002078 00000000 t0 write UNKNOWN_2001 (2001) UNKNOWN_2001: 0 001700d4: 0000: 00002001 00000000 t0 write GRAS_CNTL (2003) GRAS_CNTL: { IJ_PERSP } 001700dc: 0000: 00002003 00000001 t0 write GRAS_CL_CLIP_CNTL (2000) GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } 001700e4: 0000: 00002000 00188000 t0 write TPL1_TP_TEX_COUNT (2381) TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } 001700ec: 0000: 00002381 00000000 t0 write TPL1_TP_FS_TEX_COUNT (23a0) TPL1_TP_FS_TEX_COUNT: 0x3 001700f4: 0000: 000023a0 00000003 t0 write RB_ALPHA_CONTROL (20f8) RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } 001700fc: 0000: 000020f8 00000e00 t0 write RB_RENDER_COMPONENTS (20fb) RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } 00170104: 0000: 000020fb 0000000f t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 0017010c: 0000: c0014300 00040000 00000000 t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } 00170118: 0000: 00002200 000a0000 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } 00170120: 0000: 00002201 fc030000 t0 write SP_INSTR_CACHE_CTRL (22c1) SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } 00170128: 0000: 000022c1 000005c3 t0 write HLSQ_CONTROL_1_REG (23c1) HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } 00170130: 0000: 000023c1 fcfc0120 t0 write HLSQ_CONTROL_2_REG (23c2) HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 00170138: 0000: 000023c2 27f3f3f0 t0 write HLSQ_VS_CONTROL_REG (23c5) HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } 00170140: 0000: 000023c5 02010042 t0 write HLSQ_FS_CONTROL_REG (23c6) HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00170148: 0000: 000023c6 0041423e t0 write HLSQ_HS_CONTROL_REG (23c7) HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00170150: 0000: 000023c7 00404200 t0 write HLSQ_DS_CONTROL_REG (23c8) HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00170158: 0000: 000023c8 00404200 t0 write HLSQ_GS_CONTROL_REG (23c9) HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00170160: 0000: 000023c9 00404200 t0 write HLSQ_CS_CONTROL_REG (23ca) HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } 00170168: 0000: 000023ca 00004200 t0 write SP_SP_CTRL_REG (22c0) SP_SP_CTRL_REG: { 0x60010 } 00170170: 0000: 000022c0 00060010 t0 write UNKNOWN_21E6 (21e6) UNKNOWN_21E6: 0x1 00170178: 0000: 000021e6 00000001 t0 write SP_VS_CTRL_REG0 (22c4) SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 00170180: 0000: 000022c4 00200c10 t0 write SP_VS_CTRL_REG1 (22c5) SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } 00170188: 0000: 000022c5 01000042 t0 write VPC_ATTR (2140) VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | 0x40000000 } 00170190: 0000: 00002140 40001004 t0 write VPC_PACK (2141) VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } 00170198: 0000: 00002141 00040400 t0 write PC_PRIM_VTX_CNTL (21c4) PC_PRIM_VTX_CNTL: { VAROUT = 1 } 001701a0: 0000: 000021c4 00000001 t0 write SP_VS_PARAM_REG (22c6) SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } UNKNOWN_22D7: 0xfcfc00 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 001701a8: 0000: 001922c6 0010fc03 00001e03 00000000 00000000 00000000 00000000 00000000 * 001701e8: 0040: 00000000 00000000 00fcfc00 00000008 00000000 00000000 00000000 00000000 * t0 write SP_VS_OBJ_OFFSET_REG (22e0) SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 00170214: 0000: 000022e0 00000000 t0 write SP_VS_OBJ_START (22e1) SP_VS_OBJ_START: 0x1 0017021c: 0000: 000022e1 00000001 t0 write SP_VS_LENGTH_REG (22e5) SP_VS_LENGTH_REG: 2 00170224: 0000: 000022e5 00000002 t3 opcode: CP_LOAD_STATE4 (30) (67 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } :2:0000:0000[56d81803x_20020003x] (sy)(ss)(nop3) shl.b r0.w, r0.w, 2 :1:0001:0004[20150000x_00000003x] cov.s32s16 hr0.x, r0.w :0:0002:0005[00000200x_00000000x] (rpt2)nop :1:0003:0008[201100f4x_00000000x] mova a0.x, hr0.x :0:0004:0009[00000500x_00000000x] (rpt5)nop :1:0005:0015[20154003x_00000c20x] mov.s32s32 r0.w, c :1:0006:0016[20154004x_00000c21x] mov.s32s32 r1.x, c :1:0007:0017[20154005x_00000c22x] mov.s32s32 r1.y, c :1:0008:0018[20156006x_00000c23x] (ul)mov.s32s32 r1.z, c :0:0009:0019[03000000x_00000000x] end :2:0010:0020[46f00007x_20050000x] shr.b r1.w, r0.x, 5 :2:0011:0021[43980008x_201f0000x] (nop2) and.b r2.x, r0.x, 31 :2:0012:0024[43980807x_201f0007x] (nop3) and.b r1.w, r1.w, 31 :2:0013:0028[46100807x_20100007x] (nop1) mul.u24 r1.w, r1.w, 16 :3:0014:0030[62040007x_00071014x] mad.u24 r1.w, c5.x, r2.x, r1.w :0:0015:0031[00000500x_00000000x] (rpt5)nop :6:0016:0037[c2c60f00x_04800006x] stlw.u32 l[r1.w], r0.w, 4 :0:0017:0038[04800000x_00000000x] chmask :0:0018:0039[05000000x_00000000x] chsh Stats: - shaderdb: 40 instr, 24 nops, 16 non-nops, 5 mov, 1 cov - shaderdb: 0 last-baryf, 0 half, 2 full, 5 constlen - shaderdb: 27 cat0, 6 cat1, 5 cat2, 1 cat3, 0 cat4, 0 cat5, 1 cat6, 0 cat7 - shaderdb: 0 sstall, 1 (ss), 1 (sy) 0017022c: 0000: c0413000 00a00000 00000000 20020003 56d81803 00000003 20150000 00000000 0017024c: 0020: 00000200 00000000 201100f4 00000000 00000500 00000c20 20154003 00000c21 0017026c: 0040: 20154004 00000c22 20154005 00000c23 20156006 00000000 03000000 20050000 0017028c: 0060: 46f00007 201f0000 43980008 201f0007 43980807 20100007 46100807 00071014 001702ac: 0080: 62040007 00000000 00000500 04800006 c2c60f00 00000000 04800000 00000000 001702cc: 00a0: 05000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 * t0 write GRAS_SC_CONTROL (207b) GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = 0 | MSAA_DISABLE | RASTER_MODE = 0 } 00170338: 0000: 0000207b 00000808 t0 write RB_MSAA_CONTROL (20a2) RB_MSAA_CONTROL: { DISABLE | SAMPLES = 0 } 00170340: 0000: 000020a2 00001000 t0 write RB_RENDER_CONTROL (20a1) RB_RENDER_CONTROL: { DISABLE_COLOR_PIPE | 0x2 } 00170348: 0000: 000020a1 00000022 t0 write RB_DEPTH_CONTROL (2101) RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } 00170350: 0000: 00002101 00000000 t0 write GRAS_ALPHA_CONTROL (2073) GRAS_ALPHA_CONTROL: { 0x2 } 00170358: 0000: 00002073 00000002 t0 write RB_STENCIL_CONTROL (2106) RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } 00170360: 0000: 00002106 00000000 t0 write RB_COPY_CONTROL (20fc) RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_FOUR | MODE = RB_COPY_DEPTH_STENCIL | FASTCLEAR = 0 | GMEM_BASE = 0 } RB_COPY_DEST_BASE: { BASE = 0x4f000 } RB_COPY_DEST_PITCH: { PITCH = 256 } RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_DISABLE | COMPONENT_ENABLE = 0xf | ENDIAN = ENDIAN_NONE | TILE = TILE4_3 } 00170368: 0000: 000320fc 00000052 0004f000 00000008 0303c068 t0 write UNKNOWN_20EF (20ef) UNKNOWN_20EF: 0 0017037c: 0000: 000020ef 00000000 t0 write GRAS_SC_SCREEN_SCISSOR_TL (207c) GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } 00170384: 0000: 0001207c 00000000 003f003f t0 write RB_FRAME_BUFFER_DIMENSION (0ce0) RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } 00170390: 0000: 00000ce0 00400040 t0 write 0xce1 (0ce1) 0xce1: 00000000 00170398: 0000: 00000ce1 00000000 t3 opcode: CP_LOAD_STATE4 (30) (11 dwords) { DST_OFF = 8 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } 001703ac: 0.000000 0.000000 1.000000 1.000000 64.000000 64.000000 1.000000 1.000000 001703ac: 0000: 00000000 00000000 3f800000 3f800000 42800000 42800000 3f800000 3f800000 001703a0: 0000: c0093000 00a00008 00000001 00000000 00000000 3f800000 3f800000 42800000 001703c0: 0020: 42800000 3f800000 3f800000 t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x80000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 2 } draw[3] register values + 00000004 UNKNOWN_0CC5: 0x4 + 00000000 UNKNOWN_0CC6: 0 + 00400040 RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } + 00000000 0xce1: 00000000 !+ 00000002 HLSQ_MODE_CONTROL: 0x2 + 00000000 UNKNOWN_0E42: 0 !+ 00000004 SP_MODE_CONTROL: 0x4 !+ 00000068 TPL1_TP_MODE_CONTROL: 0x68 !+ 00188000 GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } + 00000000 UNKNOWN_2001: 0 + 00000001 GRAS_CNTL: { IJ_PERSP } !+ 00000002 GRAS_ALPHA_CONTROL: { 0x2 } !+ 00000000 GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } !+ 00000808 GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = 0 | MSAA_DISABLE | RASTER_MODE = 0 } !+ 00000000 GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } !+ 003f003f GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } !+ 00000022 RB_RENDER_CONTROL: { DISABLE_COLOR_PIPE | 0x2 } !+ 00001000 RB_MSAA_CONTROL: { DISABLE | SAMPLES = 0 } + 00000000 UNKNOWN_20EF: 0 + 00000e00 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } + 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } !+ 00000052 RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_FOUR | MODE = RB_COPY_DEPTH_STENCIL | FASTCLEAR = 0 | GMEM_BASE = 0 } + 0004f000 RB_COPY_DEST_BASE: { BASE = 0x4f000 } + 00000008 RB_COPY_DEST_PITCH: { PITCH = 256 } !+ 0303c068 RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_DISABLE | COMPONENT_ENABLE = 0xf | ENDIAN = ENDIAN_NONE | TILE = TILE4_3 } + 00000000 RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } + 00000000 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } !+ 40001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | 0x40000000 } + 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } + 00000000 UNKNOWN_2152: 0 + 00000000 UNKNOWN_2153: 0 + 00000000 UNKNOWN_2154: 0 + 00000000 UNKNOWN_2155: 0 + 00000000 UNKNOWN_2156: 0 !+ 0000001d UNKNOWN_21C3: 0x1d !+ 00000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 } + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + 00000000 PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } + 00000001 UNKNOWN_21E6: 0x1 !+ 000a0000 VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } !+ fc030000 VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } + fcfcfcfc VFD_CONTROL_2: 0xfcfcfcfc !+ fcfcfc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } + 0000fcfc VFD_CONTROL_4: 0xfcfc + 00000000 VFD_INDEX_OFFSET: 0 + 00000000 UNKNOWN_2209: 0 + 00060010 SP_SP_CTRL_REG: { 0x60010 } + 000005c3 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } !+ 00200c10 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } !+ 01000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } !+ 0010fc03 SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } !+ 00001e03 SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00fcfc00 UNKNOWN_22D7: 0xfcfc00 + 00000008 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } !+ 00000001 SP_VS_OBJ_START: 0x1 !+ 00000002 SP_VS_LENGTH_REG: 2 + 00000000 TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } !+ 00000003 TPL1_TP_FS_TEX_COUNT: 0x3 !+ 080004f0 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } !+ fcfc0120 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } !+ 27f3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } !+ 02010042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } !+ 0041423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } !+ 00404200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } !+ 00404200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } !+ 00404200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00004200 HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } !+ 00000007 HLSQ_UPDATE_CONTROL: 0x7 001703cc: 0000: c0023800 00080888 00000001 00000002 0016b0ac: 0000: c0013f00 00170000 000000f7 t3 opcode: (null) (1d) (2 dwords) 0016b0b8: 0000: c0001d00 00000000 ############################################################ vertices: 0 ############################################################ cmdstream: 8 dwords t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:000555d8 ibsize:00000155 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 000555d8: 0000: c0002600 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x4 000555e0: 0000: 00000ec3 00000004 t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x68 000555e8: 0000: 00000f03 00000068 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 000555f0: 0000: c0002600 00000000 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } 000555f8: 0000: 000023c0 080004f0 t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = 0x1d } event (null) 00055600: 0000: c0004600 0000001d t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = FACENESS_FLUSH } event FACENESS_FLUSH 00055608: 0000: c0004600 0000001c t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00055610: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0 00055618: 0000: 00000cc6 00000000 t0 write UNKNOWN_0E42 (0e42) UNKNOWN_0E42: 0 00055620: 0000: 00000e42 00000000 t0 write HLSQ_MODE_CONTROL (0e05) HLSQ_MODE_CONTROL: 0x2 00055628: 0000: 00000e05 00000002 t0 write UNKNOWN_0CC5 (0cc5) UNKNOWN_0CC5: 0x4 00055630: 0000: 00000cc5 00000004 t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x7 00055638: 0000: 000023db 00000007 t0 write VFD_CONTROL_2 (2202) VFD_CONTROL_2: 0xfcfcfcfc 00055640: 0000: 00002202 fcfcfcfc t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } 00055648: 0000: 00002203 fcfcfc00 t0 write VFD_CONTROL_4 (2204) VFD_CONTROL_4: 0xfcfc 00055650: 0000: 00002204 0000fcfc t0 write VFD_INDEX_OFFSET (2208) VFD_INDEX_OFFSET: 0 00055658: 0000: 00002208 00000000 t0 write UNKNOWN_2209 (2209) UNKNOWN_2209: 0 00055660: 0000: 00002209 00000000 t0 write UNKNOWN_2152 (2152) UNKNOWN_2152: 0 UNKNOWN_2153: 0 00055668: 0000: 00012152 00000000 00000000 t0 write UNKNOWN_2156 (2156) UNKNOWN_2156: 0 00055674: 0000: 00002156 00000000 t0 write UNKNOWN_2154 (2154) UNKNOWN_2154: 0 0005567c: 0000: 00002154 00000000 t0 write UNKNOWN_2155 (2155) UNKNOWN_2155: 0 00055684: 0000: 00002155 00000000 t0 write UNKNOWN_21C3 (21c3) UNKNOWN_21C3: 0x1d 0005568c: 0000: 000021c3 0000001d t0 write PC_PRIM_VTX_CNTL2 (21c5) PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 00055694: 0000: 000021c5 00000012 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 0005569c: 0000: 000021e5 00000000 t0 write GRAS_SU_MODE_CONTROL (2078) GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } 000556a4: 0000: 00002078 00000000 t0 write UNKNOWN_2001 (2001) UNKNOWN_2001: 0 000556ac: 0000: 00002001 00000000 t0 write GRAS_CNTL (2003) GRAS_CNTL: { IJ_PERSP } 000556b4: 0000: 00002003 00000001 t0 write GRAS_CL_CLIP_CNTL (2000) GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } 000556bc: 0000: 00002000 00188000 t0 write TPL1_TP_TEX_COUNT (2381) TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } 000556c4: 0000: 00002381 00000000 t0 write TPL1_TP_FS_TEX_COUNT (23a0) TPL1_TP_FS_TEX_COUNT: 0x3 000556cc: 0000: 000023a0 00000003 t0 write RB_ALPHA_CONTROL (20f8) RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } 000556d4: 0000: 000020f8 00000e00 t0 write RB_RENDER_COMPONENTS (20fb) RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } 000556dc: 0000: 000020fb 0000000f t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 000556e4: 0000: c0014300 00040000 00000000 t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } 000556f0: 0000: 00002200 000a0000 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } 000556f8: 0000: 00002201 fc030000 t0 write SP_INSTR_CACHE_CTRL (22c1) SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } 00055700: 0000: 000022c1 000005c3 t0 write HLSQ_CONTROL_1_REG (23c1) HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } 00055708: 0000: 000023c1 fcfc0120 t0 write HLSQ_CONTROL_2_REG (23c2) HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 00055710: 0000: 000023c2 27f3f3f0 t0 write HLSQ_VS_CONTROL_REG (23c5) HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } 00055718: 0000: 000023c5 02010042 t0 write HLSQ_FS_CONTROL_REG (23c6) HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 1 } 00055720: 0000: 000023c6 0141423e t0 write HLSQ_HS_CONTROL_REG (23c7) HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00055728: 0000: 000023c7 00404200 t0 write HLSQ_DS_CONTROL_REG (23c8) HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00055730: 0000: 000023c8 00404200 t0 write HLSQ_GS_CONTROL_REG (23c9) HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00055738: 0000: 000023c9 00404200 t0 write HLSQ_CS_CONTROL_REG (23ca) HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } 00055740: 0000: 000023ca 00004200 t0 write SP_SP_CTRL_REG (22c0) SP_SP_CTRL_REG: { 0x60010 } 00055748: 0000: 000022c0 00060010 t0 write UNKNOWN_21E6 (21e6) UNKNOWN_21E6: 0x1 00055750: 0000: 000021e6 00000001 t0 write SP_VS_CTRL_REG0 (22c4) SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 00055758: 0000: 000022c4 00200c10 t0 write SP_VS_CTRL_REG1 (22c5) SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } 00055760: 0000: 000022c5 01000042 t0 write VPC_ATTR (2140) VPC_ATTR: { TOTALATTR = 8 | THRDASSIGN = 1 | ENABLE | 0x40000000 } 00055768: 0000: 00002140 42001008 t0 write VPC_PACK (2141) VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 8 | NUMNONPOSVSVAR = 6 } 00055770: 0000: 00002141 00060800 t0 write PC_PRIM_VTX_CNTL (21c4) PC_PRIM_VTX_CNTL: { VAROUT = 1 } 00055778: 0000: 000021c4 00000001 t0 write SP_VS_PARAM_REG (22c6) SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 2 } SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r1.w | B_COMPMASK = 0x3 } SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } UNKNOWN_22D7: 0xfcfc00 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 12 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 00055780: 0000: 001922c6 0020fc03 06071e03 00000000 00000000 00000000 00000000 00000000 * 000557c0: 0040: 00000000 00000000 00fcfc00 00000c08 00000000 00000000 00000000 00000000 * t0 write SP_VS_OBJ_OFFSET_REG (22e0) SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 000557ec: 0000: 000022e0 00000000 t0 write SP_VS_OBJ_START (22e1) SP_VS_OBJ_START: 0x1 000557f4: 0000: 000022e1 00000001 t0 write SP_VS_LENGTH_REG (22e5) SP_VS_LENGTH_REG: 2 000557fc: 0000: 000022e5 00000002 t3 opcode: CP_LOAD_STATE4 (30) (67 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } :2:0000:0000[56d81803x_20020003x] (sy)(ss)(nop3) shl.b r0.w, r0.w, 2 :1:0001:0004[20150000x_00000003x] cov.s32s16 hr0.x, r0.w :0:0002:0005[00000200x_00000000x] (rpt2)nop :1:0003:0008[201100f4x_00000000x] mova a0.x, hr0.x :0:0004:0009[00000500x_00000000x] (rpt5)nop :1:0005:0015[20154003x_00000c20x] mov.s32s32 r0.w, c :1:0006:0016[20154004x_00000c21x] mov.s32s32 r1.x, c :1:0007:0017[20154007x_00000c22x] mov.s32s32 r1.w, c :1:0008:0018[20156008x_00000c23x] (ul)mov.s32s32 r2.x, c :1:0009:0019[20554005x_00000000x] mov.s32s32 r1.y, 0 :1:0010:0020[20554006x_3f800000x] mov.s32s32 r1.z, 1065353216 :0:0011:0021[03000000x_00000000x] end :2:0012:0022[46f00009x_20050000x] shr.b r2.y, r0.x, 5 :2:0013:0023[4398000ax_201f0000x] (nop2) and.b r2.z, r0.x, 31 :2:0014:0026[43980809x_201f0009x] (nop3) and.b r2.y, r2.y, 31 :2:0015:0030[46100809x_20180009x] (nop1) mul.u24 r2.y, r2.y, 24 :3:0016:0032[62050009x_00091014x] mad.u24 r2.y, c5.x, r2.z, r2.y :0:0017:0033[00000500x_00000000x] (rpt5)nop :6:0018:0039[c2c61300x_04800006x] stlw.u32 l[r2.y], r0.w, 4 :6:0019:0040[c2c61310x_0280000ex] stlw.u32 l[r2.y+16], r1.w, 2 :0:0020:0041[04800000x_00000000x] chmask :0:0021:0042[05000000x_00000000x] chsh Stats: - shaderdb: 43 instr, 24 nops, 19 non-nops, 7 mov, 1 cov - shaderdb: 0 last-baryf, 0 half, 3 full, 5 constlen - shaderdb: 27 cat0, 8 cat1, 5 cat2, 1 cat3, 0 cat4, 0 cat5, 2 cat6, 0 cat7 - shaderdb: 0 sstall, 1 (ss), 1 (sy) 00055804: 0000: c0413000 00a00000 00000000 20020003 56d81803 00000003 20150000 00000000 00055824: 0020: 00000200 00000000 201100f4 00000000 00000500 00000c20 20154003 00000c21 00055844: 0040: 20154004 00000c22 20154007 00000c23 20156008 00000000 20554005 3f800000 00055864: 0060: 20554006 00000000 03000000 20050000 46f00009 201f0000 4398000a 201f0009 00055884: 0080: 43980809 20180009 46100809 00091014 62050009 00000000 00000500 04800006 000558a4: 00a0: c2c61300 0280000e c2c61310 00000000 04800000 00000000 05000000 00000000 * t0 write HLSQ_CONTROL_3_REG (23c3) HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } 00055910: 0000: 000023c3 fcfcfc00 t0 write HLSQ_CONTROL_4_REG (23c4) HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } 00055918: 0000: 000023c4 00fcfcfc t0 write SP_FS_CTRL_REG0 (22e8) SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 0 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE | PIXLODENABLE } SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 } 00055920: 0000: 000122e8 00700402 8010003e t0 write SP_FS_OBJ_OFFSET_REG (22ea) SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 } 0005592c: 0000: 000022ea 40420000 t0 write SP_FS_OBJ_START (22eb) SP_FS_OBJ_START: 0x1 00055934: 0000: 000022eb 00000001 t0 write SP_FS_LENGTH_REG (22ef) SP_FS_LENGTH_REG: 1 0005593c: 0000: 000022ef 00000001 t0 write SP_FS_OUTPUT_REG (22f0) SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r0.x | SAMPLEMASK_REGID = r0.x } 00055944: 0000: 000022f0 00000001 t0 write VPC_VARYING_INTERP[0].MODE (2142) VPC_VARYING_INTERP[0].MODE: 0xe000 0005594c: 0000: 00002142 0000e000 t0 write RB_FS_OUTPUT_REG (2100) RB_FS_OUTPUT_REG: { MRT = 1 } 00055954: 0000: 00002100 00000001 t3 opcode: CP_LOAD_STATE4 (30) (35 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 1 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } :2:0000:0000[57309902x_00002004x] (sy)(ss)(rpt1)bary.f (ei)r0.z, (r)4, r0.x :0:0001:0002[00000500x_00000000x] (rpt5)nop :5:0002:0008[a0c01f00x_00000005x] sam (f32)(xyzw)r0.x, r0.z, s#0, t#0 :0:0003:0009[03000000x_00000000x] end :0:0004:0010[00000000x_00000000x] nop :0:0005:0011[00000000x_00000000x] nop :0:0006:0012[00000000x_00000000x] nop :0:0007:0013[00000000x_00000000x] nop Stats: - shaderdb: 14 instr, 10 nops, 4 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 0 half, 1 full, 0 constlen - shaderdb: 11 cat0, 0 cat1, 2 cat2, 0 cat3, 0 cat4, 1 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 1 (ss), 1 (sy) 0005595c: 0000: c0213000 00700000 00000000 00002004 57309902 00000000 00000500 00000005 0005597c: 0020: a0c01f00 00000000 03000000 00000000 00000000 00000000 00000000 00000000 * t0 write RB_FS_OUTPUT (20f9) RB_FS_OUTPUT: { ENABLE_BLEND = 0 | SAMPLE_MASK = 0xffff } 000559e8: 0000: 000020f9 ffff0000 t0 write RB_MRT[0].CONTROL (20a4) RB_MRT[0].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0xf } 000559f0: 0000: 000020a4 0f000000 t0 write RB_MRT[0x1].CONTROL (20a9) RB_MRT[0x1].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0xf } 000559f8: 0000: 000020a9 0f000000 t0 write RB_MRT[0].BLEND_CONTROL (20a8) RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } 00055a00: 0000: 000020a8 00000000 t3 opcode: CP_LOAD_STATE4 (30) (5 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_TEX | NUM_UNIT = 1 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } { XY_MAG = A4XX_TEX_NEAREST | XY_MIN = A4XX_TEX_NEAREST | WRAP_S = A4XX_TEX_CLAMP_TO_EDGE | WRAP_T = A4XX_TEX_CLAMP_TO_EDGE | WRAP_R = A4XX_TEX_CLAMP_TO_EDGE | ANISO = A4XX_TEX_ANISO_1 | LOD_BIAS = 0.000000 | 0x60000 } { COMPARE_FUNC = FUNC_LEQUAL | UNNORM_COORDS | MIPFILTER_LINEAR_FAR | MAX_LOD = 0.000000 | MIN_LOD = 0.000000 | 0x1 } 00055a14: 0000: 00060920 00000067 00055a08: 0000: c0033000 00500000 00000000 00060920 00000067 t0 write GRAS_SC_CONTROL (207b) GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 0 | RASTER_MODE = 0 } 00055a1c: 0000: 0000207b 00000000 t0 write RB_MSAA_CONTROL (20a2) RB_MSAA_CONTROL: { SAMPLES = 0 } 00055a24: 0000: 000020a2 00000000 t0 write RB_RENDER_CONTROL (20a1) RB_RENDER_CONTROL: { 0 } 00055a2c: 0000: 000020a1 00000000 t0 write 0x2382 (2382) 0x2382: 00000000 00055a34: 0000: 00002382 00000000 t0 write RB_DEPTH_CONTROL (2101) RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } 00055a3c: 0000: 00002101 00000000 t0 write GRAS_ALPHA_CONTROL (2073) GRAS_ALPHA_CONTROL: { 0 } 00055a44: 0000: 00002073 00000000 t0 write RB_STENCIL_CONTROL (2106) RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } 00055a4c: 0000: 00002106 00000000 t0 write SP_FS_MRT[0].REG (22f1) SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = RB4_R8G8B8A8_UNORM } 00055a54: 0000: 000022f1 0001a000 t0 write RB_MRT[0].BUF_INFO (20a5) RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB4_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE4_3 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 256 } RB_MRT[0].BASE: 0x166000 RB_MRT[0].CONTROL3: { STRIDE = 0 } 00055a5c: 0000: 000220a5 000400da 00166000 00000000 t3 opcode: CP_LOAD_STATE4 (30) (11 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_TEX | NUM_UNIT = 1 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } { TILED | SWIZ_X = A4XX_TEX_X | SWIZ_Y = A4XX_TEX_Y | SWIZ_Z = A4XX_TEX_Z | SWIZ_W = A4XX_TEX_W | MIPLVLS = 0 | FMT = TFMT4_8_8_8_8_UNORM | TYPE = A4XX_TEX_2D | 0x2 } { HEIGHT = 64 | WIDTH = 64 } { PITCHALIGN = 0 | PITCH = 256 | SWAP = WZYX } { LAYERSZ = 0 | DEPTH = 1 | 0x20000 } { LAYERSZ = 4096 | BASE = 0x4f000 } { 5 = 0 } { 6 = 0 } { 7 = 0 } 00055a78: 0000: 27006883 00200040 00020000 00060000 0004f001 00000000 00000000 00000000 00055a6c: 0000: c0093000 00500000 00000001 27006883 00200040 00020000 00060000 0004f001 * t0 write VPC_VARYING_PS_REPL[0].MODE (214a) VPC_VARYING_PS_REPL[0].MODE: 0x99999999 00055a98: 0000: 0000214a 99999999 t0 write GRAS_SC_SCREEN_SCISSOR_TL (207c) GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } 00055aa0: 0000: 0001207c 00000000 003f003f t0 write GRAS_SC_WINDOW_SCISSOR_BR (209c) GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 00055aac: 0000: 0001209c 003f003f 00000000 t0 write RB_FRAME_BUFFER_DIMENSION (0ce0) RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } 00055ab8: 0000: 00000ce0 00400040 t0 write 0xce1 (0ce1) 0xce1: 00000000 00055ac0: 0000: 00000ce1 00000000 t0 write RB_RENDER_CONTROL2 (20a3) RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 | IJ_PERSP_PIXEL } 00055ac8: 0000: 000020a3 00001000 t0 write RB_MODE_CONTROL (20a0) RB_MODE_CONTROL: { WIDTH = 0 | HEIGHT = 0 | 0xc00000 } 00055ad0: 0000: 000020a0 00c00000 t3 opcode: CP_LOAD_STATE4 (30) (11 dwords) { DST_OFF = 8 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } 00055ae4: 0.000000 0.000000 0.000000 0.000000 64.000000 64.000000 64.000000 64.000000 00055ae4: 0000: 00000000 00000000 00000000 00000000 42800000 42800000 42800000 42800000 00055ad8: 0000: c0093000 00a00008 00000001 00000000 00000000 00000000 00000000 42800000 00055af8: 0020: 42800000 42800000 42800000 t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x80000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 2 } draw[4] register values + 00000004 UNKNOWN_0CC5: 0x4 + 00000000 UNKNOWN_0CC6: 0 + 00400040 RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } + 00000000 0xce1: 00000000 + 00000002 HLSQ_MODE_CONTROL: 0x2 + 00000000 UNKNOWN_0E42: 0 + 00000004 SP_MODE_CONTROL: 0x4 + 00000068 TPL1_TP_MODE_CONTROL: 0x68 + 00188000 GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } + 00000000 UNKNOWN_2001: 0 + 00000001 GRAS_CNTL: { IJ_PERSP } !+ 00000000 GRAS_ALPHA_CONTROL: { 0 } + 00000000 GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } !+ 00000000 GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 0 | RASTER_MODE = 0 } + 00000000 GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } + 003f003f GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } + 003f003f GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } + 00000000 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } !+ 00c00000 RB_MODE_CONTROL: { WIDTH = 0 | HEIGHT = 0 | 0xc00000 } !+ 00000000 RB_RENDER_CONTROL: { 0 } !+ 00000000 RB_MSAA_CONTROL: { SAMPLES = 0 } !+ 00001000 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 | IJ_PERSP_PIXEL } !+ 0f000000 RB_MRT[0].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0xf } !+ 000400da RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB4_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE4_3 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 256 } !+ 00166000 RB_MRT[0].BASE: 0x166000 !+ 00000000 RB_MRT[0].CONTROL3: { STRIDE = 0 } + 00000000 RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } !+ 0f000000 RB_MRT[0x1].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0xf } + 00000e00 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } !+ ffff0000 RB_FS_OUTPUT: { ENABLE_BLEND = 0 | SAMPLE_MASK = 0xffff } + 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } + 00000001 RB_FS_OUTPUT_REG: { MRT = 1 } + 00000000 RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } + 00000000 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } !+ 42001008 VPC_ATTR: { TOTALATTR = 8 | THRDASSIGN = 1 | ENABLE | 0x40000000 } !+ 00060800 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 8 | NUMNONPOSVSVAR = 6 } !+ 0000e000 VPC_VARYING_INTERP[0].MODE: 0xe000 !+ 99999999 VPC_VARYING_PS_REPL[0].MODE: 0x99999999 + 00000000 UNKNOWN_2152: 0 + 00000000 UNKNOWN_2153: 0 + 00000000 UNKNOWN_2154: 0 + 00000000 UNKNOWN_2155: 0 + 00000000 UNKNOWN_2156: 0 + 0000001d UNKNOWN_21C3: 0x1d + 00000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 } + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + 00000000 PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } + 00000001 UNKNOWN_21E6: 0x1 + 000a0000 VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } + fc030000 VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } + fcfcfcfc VFD_CONTROL_2: 0xfcfcfcfc + fcfcfc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } + 0000fcfc VFD_CONTROL_4: 0xfcfc + 00000000 VFD_INDEX_OFFSET: 0 + 00000000 UNKNOWN_2209: 0 + 00060010 SP_SP_CTRL_REG: { 0x60010 } + 000005c3 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } + 00200c10 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } + 01000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } !+ 0020fc03 SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 2 } !+ 06071e03 SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r1.w | B_COMPMASK = 0x3 } + 00000000 SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00fcfc00 UNKNOWN_22D7: 0xfcfc00 !+ 00000c08 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 12 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } + 00000001 SP_VS_OBJ_START: 0x1 + 00000002 SP_VS_LENGTH_REG: 2 !+ 00700402 SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 0 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE | PIXLODENABLE } !+ 8010003e SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 } !+ 40420000 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 } !+ 00000001 SP_FS_OBJ_START: 0x1 + 00000001 SP_FS_LENGTH_REG: 1 !+ 00000001 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r0.x | SAMPLEMASK_REGID = r0.x } !+ 0001a000 SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = RB4_R8G8B8A8_UNORM } + 00000000 TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } !+ 00000000 0x2382: 00000000 + 00000003 TPL1_TP_FS_TEX_COUNT: 0x3 + 080004f0 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } + fcfc0120 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } + 27f3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } + fcfcfc00 HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } !+ 00fcfcfc HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } + 02010042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } !+ 0141423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 1 } + 00404200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00004200 HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } + 00000007 HLSQ_UPDATE_CONTROL: 0x7 00055b04: 0000: c0023800 00080888 00000001 00000002 t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = CACHE_FLUSH } event CACHE_FLUSH 00055b14: 0000: c0004600 00000006 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00055b1c: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0x8000012 00055b24: 0000: 00000cc6 08000012 00173000: 0000: c0013f00 000555d8 00000155 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 0017300c: 0000: c0014300 00040000 00000000 t3 opcode: (null) (1d) (2 dwords) 00173018: 0000: c0001d00 00000000 ############################################################ vertices: 0 ############################################################ cmdstream: 48 dwords t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 0016b000: 0000: c0002600 00000000 t0 write UCHE_INVALIDATE0 (0e8a) UCHE_INVALIDATE0: 0 UCHE_INVALIDATE1: 0x12 0016b008: 0000: 00010e8a 00000000 00000012 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 0016b014: 0000: c0002600 00000000 t0 write RB_MODE_CONTROL (20a0) RB_MODE_CONTROL: { WIDTH = 64 | HEIGHT = 64 | ENABLE_GMEM } 0016b01c: 0000: 000020a0 00010202 t0 write RB_FRAME_BUFFER_DIMENSION (0ce0) RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } 0016b024: 0000: 00000ce0 00400040 t0 write 0xce1 (0ce1) 0xce1: 00000001 0016b02c: 0000: 00000ce1 00000001 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 0016b034: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0 0016b03c: 0000: 00000cc6 00000000 t3 opcode: (null) (1d) (2 dwords) 0016b044: 0000: c0001d00 00000000 t0 write GRAS_SC_WINDOW_SCISSOR_BR (209c) GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 0016b04c: 0000: 0001209c 003f003f 00000000 t0 write RB_BIN_OFFSET (210d) RB_BIN_OFFSET: { X = 0 | Y = 0 } 0016b058: 0000: 0000210d 00000000 t0 write GRAS_SC_WINDOW_SCISSOR_BR (209c) GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 0016b060: 0000: 0001209c 003f003f 00000000 t0 write UNKNOWN_2157 (2157) UNKNOWN_2157: 0x1 0016b06c: 0000: 00002157 00000001 t3 opcode: (null) (64) (2 dwords) 0016b074: 0000: c0006400 00000001 t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:00054994 ibsize:000000f6 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00054994: 0000: c0002600 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x4 0005499c: 0000: 00000ec3 00000004 t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x68 000549a4: 0000: 00000f03 00000068 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 000549ac: 0000: c0002600 00000000 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } 000549b4: 0000: 000023c0 080004f0 t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = 0x1d } event (null) 000549bc: 0000: c0004600 0000001d t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = FACENESS_FLUSH } event FACENESS_FLUSH 000549c4: 0000: c0004600 0000001c t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 000549cc: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0 000549d4: 0000: 00000cc6 00000000 t0 write UNKNOWN_0E42 (0e42) UNKNOWN_0E42: 0 000549dc: 0000: 00000e42 00000000 t0 write HLSQ_MODE_CONTROL (0e05) HLSQ_MODE_CONTROL: 0x2 000549e4: 0000: 00000e05 00000002 t0 write UNKNOWN_0CC5 (0cc5) UNKNOWN_0CC5: 0x4 000549ec: 0000: 00000cc5 00000004 t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x7 000549f4: 0000: 000023db 00000007 t0 write VFD_CONTROL_2 (2202) VFD_CONTROL_2: 0xfcfcfcfc 000549fc: 0000: 00002202 fcfcfcfc t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } 00054a04: 0000: 00002203 fcfcfc00 t0 write VFD_CONTROL_4 (2204) VFD_CONTROL_4: 0xfcfc 00054a0c: 0000: 00002204 0000fcfc t0 write VFD_INDEX_OFFSET (2208) VFD_INDEX_OFFSET: 0 00054a14: 0000: 00002208 00000000 t0 write UNKNOWN_2209 (2209) UNKNOWN_2209: 0 00054a1c: 0000: 00002209 00000000 t0 write UNKNOWN_2152 (2152) UNKNOWN_2152: 0 UNKNOWN_2153: 0 00054a24: 0000: 00012152 00000000 00000000 t0 write UNKNOWN_2156 (2156) UNKNOWN_2156: 0 00054a30: 0000: 00002156 00000000 t0 write UNKNOWN_2154 (2154) UNKNOWN_2154: 0 00054a38: 0000: 00002154 00000000 t0 write UNKNOWN_2155 (2155) UNKNOWN_2155: 0 00054a40: 0000: 00002155 00000000 t0 write UNKNOWN_21C3 (21c3) UNKNOWN_21C3: 0x1d 00054a48: 0000: 000021c3 0000001d t0 write PC_PRIM_VTX_CNTL2 (21c5) PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 00054a50: 0000: 000021c5 00000012 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 00054a58: 0000: 000021e5 00000000 t0 write GRAS_SU_MODE_CONTROL (2078) GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } 00054a60: 0000: 00002078 00000000 t0 write UNKNOWN_2001 (2001) UNKNOWN_2001: 0 00054a68: 0000: 00002001 00000000 t0 write GRAS_CNTL (2003) GRAS_CNTL: { IJ_PERSP } 00054a70: 0000: 00002003 00000001 t0 write GRAS_CL_CLIP_CNTL (2000) GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } 00054a78: 0000: 00002000 00188000 t0 write TPL1_TP_TEX_COUNT (2381) TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } 00054a80: 0000: 00002381 00000000 t0 write TPL1_TP_FS_TEX_COUNT (23a0) TPL1_TP_FS_TEX_COUNT: 0x3 00054a88: 0000: 000023a0 00000003 t0 write RB_ALPHA_CONTROL (20f8) RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } 00054a90: 0000: 000020f8 00000e00 t0 write RB_RENDER_COMPONENTS (20fb) RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } 00054a98: 0000: 000020fb 0000000f t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 00054aa0: 0000: c0014300 00040000 00000000 t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } 00054aac: 0000: 00002200 000a0000 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } 00054ab4: 0000: 00002201 fc030000 t0 write SP_INSTR_CACHE_CTRL (22c1) SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } 00054abc: 0000: 000022c1 000005c3 t0 write HLSQ_CONTROL_1_REG (23c1) HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } 00054ac4: 0000: 000023c1 fcfc0120 t0 write HLSQ_CONTROL_2_REG (23c2) HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 00054acc: 0000: 000023c2 27f3f3f0 t0 write HLSQ_VS_CONTROL_REG (23c5) HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } 00054ad4: 0000: 000023c5 02010042 t0 write HLSQ_FS_CONTROL_REG (23c6) HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00054adc: 0000: 000023c6 0041423e t0 write HLSQ_HS_CONTROL_REG (23c7) HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00054ae4: 0000: 000023c7 00404200 t0 write HLSQ_DS_CONTROL_REG (23c8) HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00054aec: 0000: 000023c8 00404200 t0 write HLSQ_GS_CONTROL_REG (23c9) HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00054af4: 0000: 000023c9 00404200 t0 write HLSQ_CS_CONTROL_REG (23ca) HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } 00054afc: 0000: 000023ca 00004200 t0 write SP_SP_CTRL_REG (22c0) SP_SP_CTRL_REG: { 0x60010 } 00054b04: 0000: 000022c0 00060010 t0 write UNKNOWN_21E6 (21e6) UNKNOWN_21E6: 0x1 00054b0c: 0000: 000021e6 00000001 t0 write SP_VS_CTRL_REG0 (22c4) SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 00054b14: 0000: 000022c4 00200c10 t0 write SP_VS_CTRL_REG1 (22c5) SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } 00054b1c: 0000: 000022c5 01000042 t0 write VPC_ATTR (2140) VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | 0x40000000 } 00054b24: 0000: 00002140 40001004 t0 write VPC_PACK (2141) VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } 00054b2c: 0000: 00002141 00040400 t0 write PC_PRIM_VTX_CNTL (21c4) PC_PRIM_VTX_CNTL: { VAROUT = 1 } 00054b34: 0000: 000021c4 00000001 t0 write SP_VS_PARAM_REG (22c6) SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } UNKNOWN_22D7: 0xfcfc00 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 00054b3c: 0000: 001922c6 0010fc03 00001e03 00000000 00000000 00000000 00000000 00000000 * 00054b7c: 0040: 00000000 00000000 00fcfc00 00000008 00000000 00000000 00000000 00000000 * t0 write SP_VS_OBJ_OFFSET_REG (22e0) SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 00054ba8: 0000: 000022e0 00000000 t0 write SP_VS_OBJ_START (22e1) SP_VS_OBJ_START: 0x1 00054bb0: 0000: 000022e1 00000001 t0 write SP_VS_LENGTH_REG (22e5) SP_VS_LENGTH_REG: 2 00054bb8: 0000: 000022e5 00000002 t3 opcode: CP_LOAD_STATE4 (30) (67 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } :2:0000:0000[56d81803x_20020003x] (sy)(ss)(nop3) shl.b r0.w, r0.w, 2 :1:0001:0004[20150000x_00000003x] cov.s32s16 hr0.x, r0.w :0:0002:0005[00000200x_00000000x] (rpt2)nop :1:0003:0008[201100f4x_00000000x] mova a0.x, hr0.x :0:0004:0009[00000500x_00000000x] (rpt5)nop :1:0005:0015[20154003x_00000c20x] mov.s32s32 r0.w, c :1:0006:0016[20154004x_00000c21x] mov.s32s32 r1.x, c :1:0007:0017[20154005x_00000c22x] mov.s32s32 r1.y, c :1:0008:0018[20156006x_00000c23x] (ul)mov.s32s32 r1.z, c :0:0009:0019[03000000x_00000000x] end :2:0010:0020[46f00007x_20050000x] shr.b r1.w, r0.x, 5 :2:0011:0021[43980008x_201f0000x] (nop2) and.b r2.x, r0.x, 31 :2:0012:0024[43980807x_201f0007x] (nop3) and.b r1.w, r1.w, 31 :2:0013:0028[46100807x_20100007x] (nop1) mul.u24 r1.w, r1.w, 16 :3:0014:0030[62040007x_00071014x] mad.u24 r1.w, c5.x, r2.x, r1.w :0:0015:0031[00000500x_00000000x] (rpt5)nop :6:0016:0037[c2c60f00x_04800006x] stlw.u32 l[r1.w], r0.w, 4 :0:0017:0038[04800000x_00000000x] chmask :0:0018:0039[05000000x_00000000x] chsh Stats: - shaderdb: 40 instr, 24 nops, 16 non-nops, 5 mov, 1 cov - shaderdb: 0 last-baryf, 0 half, 2 full, 5 constlen - shaderdb: 27 cat0, 6 cat1, 5 cat2, 1 cat3, 0 cat4, 0 cat5, 1 cat6, 0 cat7 - shaderdb: 0 sstall, 1 (ss), 1 (sy) 00054bc0: 0000: c0413000 00a00000 00000000 20020003 56d81803 00000003 20150000 00000000 00054be0: 0020: 00000200 00000000 201100f4 00000000 00000500 00000c20 20154003 00000c21 00054c00: 0040: 20154004 00000c22 20154005 00000c23 20156006 00000000 03000000 20050000 00054c20: 0060: 46f00007 201f0000 43980008 201f0007 43980807 20100007 46100807 00071014 00054c40: 0080: 62040007 00000000 00000500 04800006 c2c60f00 00000000 04800000 00000000 00054c60: 00a0: 05000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 * t0 write GRAS_ALPHA_CONTROL (2073) GRAS_ALPHA_CONTROL: { 0x2 } 00054ccc: 0000: 00002073 00000002 t0 write GRAS_SC_CONTROL (207b) GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = 4 | MSAA_DISABLE | RASTER_MODE = 0 } 00054cd4: 0000: 0000207b 00000a08 t0 write RB_MSAA_CONTROL (20a2) RB_MSAA_CONTROL: { DISABLE | SAMPLES = 4 } 00054cdc: 0000: 000020a2 00009000 t0 write RB_RENDER_CONTROL (20a1) RB_RENDER_CONTROL: { DISABLE_COLOR_PIPE | 0x2 } 00054ce4: 0000: 000020a1 00000022 t0 write RB_CLEAR_COLOR_DW0 (20cc) RB_CLEAR_COLOR_DW0: 0xff000000 RB_CLEAR_COLOR_DW1: 0 RB_CLEAR_COLOR_DW2: 0 RB_CLEAR_COLOR_DW3: 0 00054cec: 0000: 000320cc ff000000 00000000 00000000 00000000 t0 write RB_COPY_CONTROL (20fc) RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_FOUR | MODE = RB_COPY_CLEAR | FASTCLEAR = 0xf | GMEM_BASE = 0 } RB_COPY_DEST_BASE: { BASE = 0x4f000 } RB_COPY_DEST_PITCH: { PITCH = 256 } RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_IF_ALPHA_OFF | COMPONENT_ENABLE = 0 | ENDIAN = ENDIAN_NONE | TILE = TILE4_3 } 00054d00: 0000: 000320fc 00000f22 0004f000 00000008 03000868 t0 write GRAS_SC_SCREEN_SCISSOR_TL (207c) GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } 00054d14: 0000: 0001207c 00000000 003f003f t0 write RB_FRAME_BUFFER_DIMENSION (0ce0) RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } 00054d20: 0000: 00000ce0 00400040 t0 write 0xce1 (0ce1) 0xce1: 00000000 00054d28: 0000: 00000ce1 00000000 t3 opcode: CP_LOAD_STATE4 (30) (11 dwords) { DST_OFF = 8 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } 00054d3c: 0.000000 0.000000 1.000000 1.000000 64.000000 64.000000 1.000000 1.000000 00054d3c: 0000: 00000000 00000000 3f800000 3f800000 42800000 42800000 3f800000 3f800000 00054d30: 0000: c0093000 00a00008 00000001 00000000 00000000 3f800000 3f800000 42800000 00054d50: 0020: 42800000 3f800000 3f800000 t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x80000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 2 } draw[5] register values + 00000004 UNKNOWN_0CC5: 0x4 + 00000000 UNKNOWN_0CC6: 0 + 00400040 RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } + 00000000 0xce1: 00000000 + 00000002 HLSQ_MODE_CONTROL: 0x2 + 00000000 UNKNOWN_0E42: 0 + 00000000 UCHE_INVALIDATE0: 0 + 00000012 UCHE_INVALIDATE1: 0x12 + 00000004 SP_MODE_CONTROL: 0x4 + 00000068 TPL1_TP_MODE_CONTROL: 0x68 + 00188000 GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } + 00000000 UNKNOWN_2001: 0 + 00000001 GRAS_CNTL: { IJ_PERSP } !+ 00000002 GRAS_ALPHA_CONTROL: { 0x2 } + 00000000 GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } !+ 00000a08 GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = 4 | MSAA_DISABLE | RASTER_MODE = 0 } + 00000000 GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } + 003f003f GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } + 003f003f GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } + 00000000 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } !+ 00010202 RB_MODE_CONTROL: { WIDTH = 64 | HEIGHT = 64 | ENABLE_GMEM } !+ 00000022 RB_RENDER_CONTROL: { DISABLE_COLOR_PIPE | 0x2 } !+ 00009000 RB_MSAA_CONTROL: { DISABLE | SAMPLES = 4 } + ff000000 RB_CLEAR_COLOR_DW0: 0xff000000 + 00000000 RB_CLEAR_COLOR_DW1: 0 + 00000000 RB_CLEAR_COLOR_DW2: 0 + 00000000 RB_CLEAR_COLOR_DW3: 0 + 00000e00 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } + 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } !+ 00000f22 RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_FOUR | MODE = RB_COPY_CLEAR | FASTCLEAR = 0xf | GMEM_BASE = 0 } + 0004f000 RB_COPY_DEST_BASE: { BASE = 0x4f000 } + 00000008 RB_COPY_DEST_PITCH: { PITCH = 256 } !+ 03000868 RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_IF_ALPHA_OFF | COMPONENT_ENABLE = 0 | ENDIAN = ENDIAN_NONE | TILE = TILE4_3 } + 00000000 RB_BIN_OFFSET: { X = 0 | Y = 0 } !+ 40001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | 0x40000000 } !+ 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } + 00000000 UNKNOWN_2152: 0 + 00000000 UNKNOWN_2153: 0 + 00000000 UNKNOWN_2154: 0 + 00000000 UNKNOWN_2155: 0 + 00000000 UNKNOWN_2156: 0 + 00000001 UNKNOWN_2157: 0x1 + 0000001d UNKNOWN_21C3: 0x1d + 00000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 } + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + 00000000 PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } + 00000001 UNKNOWN_21E6: 0x1 + 000a0000 VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } + fc030000 VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } + fcfcfcfc VFD_CONTROL_2: 0xfcfcfcfc + fcfcfc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } + 0000fcfc VFD_CONTROL_4: 0xfcfc + 00000000 VFD_INDEX_OFFSET: 0 + 00000000 UNKNOWN_2209: 0 + 00060010 SP_SP_CTRL_REG: { 0x60010 } + 000005c3 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } + 00200c10 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } + 01000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } !+ 0010fc03 SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } !+ 00001e03 SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00fcfc00 UNKNOWN_22D7: 0xfcfc00 !+ 00000008 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } + 00000001 SP_VS_OBJ_START: 0x1 + 00000002 SP_VS_LENGTH_REG: 2 + 00000000 TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } + 00000003 TPL1_TP_FS_TEX_COUNT: 0x3 + 080004f0 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } + fcfc0120 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } + 27f3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } + 02010042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } !+ 0041423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00004200 HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } + 00000007 HLSQ_UPDATE_CONTROL: 0x7 00054d5c: 0000: c0023800 00080888 00000001 00000002 0016b07c: 0000: c0013f00 00054994 000000f6 t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:00054d6c ibsize:00000037 t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } 00054d6c: 0000: 00002200 082a0008 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00054d74: 0000: c0002600 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x1e 00054d7c: 0000: 00000ec3 0000001e t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x28 00054d84: 0000: 00000f03 00000028 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00054d8c: 0000: c0002600 00000000 t0 write HLSQ_MODE_CONTROL (0e05) HLSQ_MODE_CONTROL: 0x1 00054d94: 0000: 00000e05 00000001 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0x600a0 } 00054d9c: 0000: 000023c0 080604f0 t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x7 00054da4: 0000: 000023db 00000007 t0 write PC_RESTART_INDEX (21c6) PC_RESTART_INDEX: 0xffffffff 00054dac: 0000: 000021c6 ffffffff t0 write UNKNOWN_21E6 (21e6) UNKNOWN_21E6: 0x1 00054db4: 0000: 000021e6 00000001 t0 write UNKNOWN_21C3 (21c3) UNKNOWN_21C3: 0x1f 00054dbc: 0000: 000021c3 0000001f t0 write TPL1_TP_TEX_OFFSET (2380) TPL1_TP_TEX_OFFSET: 0x808 00054dc4: 0000: 00002380 00000808 t0 write GRAS_SU_POINT_MINMAX (2070) GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 4092.000000 } GRAS_SU_POINT_SIZE: 0.500000 00054dcc: 0000: 00012070 ffc00010 00000008 t0 write UNKNOWN_2152 (2152) UNKNOWN_2152: 0 UNKNOWN_2153: 0 00054dd8: 0000: 00012152 00000000 00000000 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00054de4: 0000: c0002600 00000000 t0 write UNKNOWN_0CC5 (0cc5) UNKNOWN_0CC5: 0x4 00054dec: 0000: 00000cc5 00000004 t0 write 0xcc4 (0cc4) 0xcc4: 00000000 00054df4: 0000: 00000cc4 00000000 t0 write 0xd03 (0d03) 0xd03: 80200000 00054dfc: 0000: 00000d03 80200000 t0 write UNKNOWN_0EC2 (0ec2) UNKNOWN_0EC2: 0x40000 00054e04: 0000: 00000ec2 00040000 t0 write VPC_DEBUG_ECO_CONTROL (0e64) VPC_DEBUG_ECO_CONTROL: 0x100 00054e0c: 0000: 00000e64 00000100 t0 write UNKNOWN_0E42 (0e42) UNKNOWN_0E42: 0 00054e14: 0000: 00000e42 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x1e 00054e1c: 0000: 00000ec3 0000001e t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x28 00054e24: 0000: 00000f03 00000028 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 00054e2c: 0000: c0014300 00040000 00000000 t0 write VFD_INDEX_OFFSET (2208) VFD_INDEX_OFFSET: 0 00054e38: 0000: 00002208 00000000 t0 write UNKNOWN_2209 (2209) UNKNOWN_2209: 0 00054e40: 0000: 00002209 00000000 0016b088: 0000: c0013f00 00054d6c 00000037 t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:00055328 ibsize:000000ac t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x3 00055328: 0000: 000023db 00000003 t0 write SP_INSTR_CACHE_CTRL (22c1) SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } 00055330: 0000: 000022c1 000005c3 t0 write HLSQ_CONTROL_1_REG (23c1) HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x1008 } 00055338: 0000: 000023c1 fcfc1108 t0 write HLSQ_CONTROL_2_REG (23c2) HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 00055340: 0000: 000023c2 fff3f3f0 t0 write HLSQ_VS_CONTROL_REG (23c5) HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 2 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 1 } 00055348: 0000: 000023c5 01010002 t0 write HLSQ_HS_CONTROL_REG (23c7) HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 00055350: 0000: 000023c7 007e0200 t0 write HLSQ_DS_CONTROL_REG (23c8) HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 00055358: 0000: 000023c8 007e0200 t0 write HLSQ_GS_CONTROL_REG (23c9) HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 00055360: 0000: 000023c9 007e0200 t0 write HLSQ_FS_CONTROL_REG (23c6) HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 2 | CONSTOBJECTOFFSET = 2 | ENABLED | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 } 00055368: 0000: 000023c6 017f0202 t0 write SP_VS_OBJ_OFFSET_REG (22e0) SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 00055370: 0000: 000022e0 00000000 t0 write SP_HS_OBJ_OFFSET_REG (230d) SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } 00055378: 0000: 0000230d 7e020000 t0 write SP_DS_OBJ_OFFSET_REG (2334) SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } 00055380: 0000: 00002334 7e020000 t0 write SP_GS_OBJ_OFFSET_REG (235b) SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } 00055388: 0000: 0000235b 7e020000 t0 write SP_FS_OBJ_OFFSET_REG (22ea) SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } 00055390: 0000: 000022ea 7e020000 t0 write SP_VS_OBJ_START (22e1) SP_VS_OBJ_START: 0x49000 00049000: 0000: 00000000 13000000 00000000 00000000 00000000 00000000 00000000 00000000 * :0:0000:0000[13000000x_00000000x] (sy)end :0:0001:0001[00000000x_00000000x] nop :0:0002:0002[00000000x_00000000x] nop :0:0003:0003[00000000x_00000000x] nop :0:0004:0004[00000000x_00000000x] nop Stats: - shaderdb: 5 instr, 4 nops, 1 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 0 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 0 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) 00055398: 0000: 000022e1 00049000 t0 write SP_HS_OBJ_START (230e) SP_HS_OBJ_START: 0 000553a0: 0000: 0000230e 00000000 t0 write SP_DS_OBJ_START (2335) SP_DS_OBJ_START: 0 000553a8: 0000: 00002335 00000000 t0 write SP_GS_OBJ_START (235c) SP_GS_OBJ_START: 0 000553b0: 0000: 0000235c 00000000 t0 write SP_VS_LENGTH_REG (22e5) SP_VS_LENGTH_REG: 1 000553b8: 0000: 000022e5 00000001 t3 opcode: CP_LOAD_STATE4 (30) (3 dwords) { DST_OFF = 0 | STATE_SRC = SS4_INDIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 1 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0x49000 } :0:0000:0000[13000000x_00000000x] (sy)end :0:0001:0001[00000000x_00000000x] nop :0:0002:0002[00000000x_00000000x] nop :0:0003:0003[00000000x_00000000x] nop :0:0004:0004[00000000x_00000000x] nop Stats: - shaderdb: 5 instr, 4 nops, 1 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 0 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 0 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) 000553c0: 0000: c0013000 00620000 00049000 t0 write 0x2072 (2072) 0x2072: 00000000 000553cc: 0000: 00002072 00000000 t0 write UNKNOWN_2155 (2155) UNKNOWN_2155: 0 000553d4: 0000: 00002155 00000000 t0 write GRAS_CNTL (2003) GRAS_CNTL: { IJ_PERSP } 000553dc: 0000: 00002003 00000001 t0 write VPC_VARYING_INTERP[0].MODE (2142) VPC_VARYING_INTERP[0].MODE: 0 000553e4: 0000: 00002142 00000000 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0x600a0 } 000553ec: 0000: 000023c0 080604f0 t0 write HLSQ_CONTROL_3_REG (23c3) HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } 000553f4: 0000: 000023c3 fcfcfc00 t0 write HLSQ_CONTROL_4_REG (23c4) HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r0.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } 000553fc: 0000: 000023c4 00fcfc00 t0 write SP_FS_CTRL_REG0 (22e8) SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE } SP_FS_CTRL_REG1: { CONSTLENGTH = 2 | VARYING | 0x80000000 } 00055404: 0000: 000122e8 00340412 80100002 t0 write SP_FS_OBJ_START (22eb) SP_FS_OBJ_START: 0x46000 00046000: 0000: 00002000 5730cb00 00000000 03000000 00000000 00000000 00000000 00000000 * :2:0000:0000[5730cb00x_00002000x] (sy)(rpt3)bary.f (ei)hr0.x, (r)0, r0.x :0:0001:0004[03000000x_00000000x] end :0:0002:0005[00000000x_00000000x] nop :0:0003:0006[00000000x_00000000x] nop :0:0004:0007[00000000x_00000000x] nop :0:0005:0008[00000000x_00000000x] nop Stats: - shaderdb: 9 instr, 4 nops, 5 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 1 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 4 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) 00055410: 0000: 000022eb 00046000 t0 write SP_FS_LENGTH_REG (22ef) SP_FS_LENGTH_REG: 1 00055418: 0000: 000022ef 00000001 t0 write RB_RENDER_COMPONENTS (20fb) RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } 00055420: 0000: 000020fb 0000000f t3 opcode: CP_LOAD_STATE4 (30) (3 dwords) { DST_OFF = 0 | STATE_SRC = SS4_INDIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 1 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0x46000 } :2:0000:0000[5730cb00x_00002000x] (sy)(rpt3)bary.f (ei)hr0.x, (r)0, r0.x :0:0001:0004[03000000x_00000000x] end :0:0002:0005[00000000x_00000000x] nop :0:0003:0006[00000000x_00000000x] nop :0:0004:0007[00000000x_00000000x] nop :0:0005:0008[00000000x_00000000x] nop Stats: - shaderdb: 9 instr, 4 nops, 5 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 1 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 4 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) 00055428: 0000: c0013000 00720000 00046000 t0 write SP_SP_CTRL_REG (22c0) SP_SP_CTRL_REG: { 0x60010 } 00055434: 0000: 000022c0 00060010 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 28 | GROUP_ID = 3 } { ADDR_LO = 0x993f0 } 0005543c: 0000: c0014300 0300001c 000993f0 t0 write RB_DEPTH_INFO (2103) RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTH4_NONE | DEPTH_BASE = 0 } RB_DEPTH_PITCH: 0 RB_DEPTH_PITCH2: 0 00055448: 0000: 00022103 00000000 00000000 00000000 t0 write GRAS_DEPTH_CONTROL (2077) GRAS_DEPTH_CONTROL: { FORMAT = DEPTH4_NONE } 00055458: 0000: 00002077 00000000 t0 write RB_STENCIL_INFO (2108) RB_STENCIL_INFO: { STENCIL_BASE = 0 } RB_STENCIL_PITCH: 0 0x210a: 00000000 00055460: 0000: 00022108 00000000 00000000 00000000 t0 write 0x2002 (2002) 0x2002: 00000000 00055470: 0000: 00002002 00000000 t0 write RB_ALPHA_CONTROL (20f8) RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } 00055478: 0000: 000020f8 00000e00 t0 write RB_MRT[0].CONTROL (20a4) RB_MRT[0].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0x7 } 00055480: 0000: 000020a4 07000c00 t0 write RB_MRT[0].BLEND_CONTROL (20a8) RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } 00055488: 0000: 000020a8 00000000 t0 write GRAS_CL_CLIP_CNTL (2000) GRAS_CL_CLIP_CNTL: { 0x80000 } 00055490: 0000: 00002000 00080000 t0 write GRAS_SU_POLY_OFFSET_SCALE (2074) GRAS_SU_POLY_OFFSET_SCALE: 0.000000 GRAS_SU_POLY_OFFSET_OFFSET: 0.000000 GRAS_SU_POLY_OFFSET_CLAMP: 0.000000 00055498: 0000: 00022074 00000000 00000000 00000000 t0 write GRAS_SU_MODE_CONTROL (2078) GRAS_SU_MODE_CONTROL: { FRONT_CW | LINEHALFWIDTH = 0.500000 | MSAA_ENABLE | RENDERING_PASS } 000554a8: 0000: 00002078 00102014 t0 write GRAS_SC_SCREEN_SCISSOR_TL (207c) GRAS_SC_SCREEN_SCISSOR_TL: { X = 2 | Y = 13 } GRAS_SC_SCREEN_SCISSOR_BR: { X = 33 | Y = 44 } 000554b0: 0000: 0001207c 000d0002 002c0021 t0 write GRAS_CL_VPORT_XOFFSET_0 (2008) GRAS_CL_VPORT_XOFFSET_0: 18.000000 GRAS_CL_VPORT_XSCALE_0: 16.000000 GRAS_CL_VPORT_YOFFSET_0: 29.000000 GRAS_CL_VPORT_YSCALE_0: 16.000000 GRAS_CL_VPORT_ZOFFSET_0: 0.500000 GRAS_CL_VPORT_ZSCALE_0: 0.500000 000554bc: 0000: 00052008 41900000 41800000 41e80000 41800000 3f000000 3f000000 t0 write GRAS_CL_GB_CLIP_ADJ (2004) GRAS_CL_GB_CLIP_ADJ: { HORZ = 511 | VERT = 511 } 000554d8: 0000: 00002004 0007fdff t0 write GRAS_SC_CONTROL (207b) GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 4 | RASTER_MODE = 0 } 000554e0: 0000: 0000207b 00000200 t0 write 0x2382 (2382) 0x2382: 00000002 000554e8: 0000: 00002382 00000002 t0 write RB_MSAA_CONTROL (20a2) RB_MSAA_CONTROL: { SAMPLES = 4 } 000554f0: 0000: 000020a2 00008000 t0 write RB_RENDER_CONTROL2 (20a3) RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 4 | IJ_PERSP_PIXEL } 000554f8: 0000: 000020a3 00001200 t0 write RB_MRT[0].BUF_INFO (20a5) RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB4_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_ALWAYS | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 1024 } RB_MRT[0].BASE: 0 RB_MRT[0].CONTROL3: { STRIDE = 64 } 00055500: 0000: 000220a5 0010029a 00000000 00000200 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 43 | GROUP_ID = 2 } { ADDR_LO = 0x99460 } 00055510: 0000: c0014300 0200002b 00099460 t0 write 0x215c (215c) 0x215c: 00000000 0x215d: 00000000 0005551c: 0000: 0001215c 00000000 00000000 t0 write 0x215f (215f) 0x215f: 00000000 00055528: 0000: 0000215f 00000000 t0 write 0x215e (215e) 0x215e: 00000000 00055530: 0000: 0000215e 00000000 t0 write 0x2161 (2161) 0x2161: 00000000 0x2162: 00000000 00055538: 0000: 00012161 00000000 00000000 t0 write 0x2164 (2164) 0x2164: 00000000 00055544: 0000: 00002164 00000000 t0 write 0x2163 (2163) 0x2163: 00000000 0005554c: 0000: 00002163 00000000 t0 write 0x2166 (2166) 0x2166: 00000000 0x2167: 00000000 00055554: 0000: 00012166 00000000 00000000 t0 write 0x2169 (2169) 0x2169: 00000000 00055560: 0000: 00002169 00000000 t0 write 0x2168 (2168) 0x2168: 00000000 00055568: 0000: 00002168 00000000 t0 write 0x216b (216b) 0x216b: 00000000 0x216c: 00000000 00055570: 0000: 0001216b 00000000 00000000 t0 write VPC_SO_FLUSH_WADDR_3 (216e) VPC_SO_FLUSH_WADDR_3: 0 0005557c: 0000: 0000216e 00000000 t0 write 0x216d (216d) 0x216d: 00000000 00055584: 0000: 0000216d 00000000 t0 write UNKNOWN_2156 (2156) UNKNOWN_2156: 0 0005558c: 0000: 00002156 00000000 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 18 | GROUP_ID = 1 } { ADDR_LO = 0x99510 } 00055594: 0000: c0014300 01000012 00099510 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 15 | GROUP_ID = 0 } { ADDR_LO = 0x99560 } 000555a0: 0000: c0014300 0000000f 00099560 group_id: 0 count: 15 addr: 0000000000099560 flags: 0 00099560: 0000: 00002073 00000000 00002101 00000000 00002106 00000000 000021e5 00000000 00099580: 0020: 0001210b 00000000 00000000 00002381 00000000 000023a0 00000000 t0 write GRAS_ALPHA_CONTROL (2073) GRAS_ALPHA_CONTROL: { 0 } 00099560: 0000: 00002073 00000000 t0 write RB_DEPTH_CONTROL (2101) RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } 00099568: 0000: 00002101 00000000 t0 write RB_STENCIL_CONTROL (2106) RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } 00099570: 0000: 00002106 00000000 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 00099578: 0000: 000021e5 00000000 t0 write RB_STENCILREFMASK (210b) RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 00099580: 0000: 0001210b 00000000 00000000 t0 write TPL1_TP_TEX_COUNT (2381) TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } 0009958c: 0000: 00002381 00000000 t0 write TPL1_TP_FS_TEX_COUNT (23a0) TPL1_TP_FS_TEX_COUNT: 0 00099594: 0000: 000023a0 00000000 group_id: 1 count: 18 addr: 0000000000099510 flags: 0 00099510: 0000: 00002200 082a0008 00002201 fcfc0081 00002203 0000fc00 0007220a 0008080f 00099530: 0020: 00099390 00000060 00000001 0000080f 000993c0 00000030 00000001 0001228a 00099550: 0040: 7000411f 3000011f t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } 00099510: 0000: 00002200 082a0008 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } 00099518: 0000: 00002201 fcfc0081 t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } 00099520: 0000: 00002203 0000fc00 t0 write VFD_FETCH[0].INSTR_0 (220a) VFD_FETCH[0].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 | SWITCHNEXT } VFD_FETCH[0].INSTR_1: 0x99390 VFD_FETCH[0].INSTR_2: { SIZE = 0x60 } VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 } VFD_FETCH[0x1].INSTR_1: 0x993c0 VFD_FETCH[0x1].INSTR_2: { SIZE = 0x30 } VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } 00099528: 0000: 0007220a 0008080f 00099390 00000060 00000001 0000080f 000993c0 00000030 00099548: 0020: 00000001 t0 write VFD_DECODE[0].INSTR (228a) VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID | SWITCHNEXT } VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID } 0009954c: 0000: 0001228a 7000411f 3000011f group_id: 2 count: 43 addr: 0000000000099460 flags: 0 00099460: 0000: 000020a1 00000000 000022f1 0001a100 000022f0 fc00fc01 00002100 00000001 00099480: 0020: 000021e5 00000000 000020f9 ffff0501 0000214a 00000000 00002140 42001004 000994a0: 0040: 001922c6 0010fc04 00001e00 00000000 00000000 00000000 00000000 00000000 * 000994e0: 0080: 00000000 00000000 00fcfc00 00000008 00000000 00000000 00000000 00000000 * t0 write RB_RENDER_CONTROL (20a1) RB_RENDER_CONTROL: { 0 } 00099460: 0000: 000020a1 00000000 t0 write SP_FS_MRT[0].REG (22f1) SP_FS_MRT[0].REG: { REGID = r0.x | HALF_PRECISION | MRTFORMAT = RB4_R8G8B8A8_UNORM } 00099468: 0000: 000022f1 0001a100 t0 write SP_FS_OUTPUT_REG (22f0) SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 00099470: 0000: 000022f0 fc00fc01 t0 write RB_FS_OUTPUT_REG (2100) RB_FS_OUTPUT_REG: { MRT = 1 } 00099478: 0000: 00002100 00000001 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 00099480: 0000: 000021e5 00000000 t0 write RB_FS_OUTPUT (20f9) RB_FS_OUTPUT: { ENABLE_BLEND = 0x1 | INDEPENDENT_BLEND | SAMPLE_MASK = 0xffff | 0x400 } 00099488: 0000: 000020f9 ffff0501 t0 write VPC_VARYING_PS_REPL[0].MODE (214a) VPC_VARYING_PS_REPL[0].MODE: 0 00099490: 0000: 0000214a 00000000 t0 write VPC_ATTR (2140) VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 } 00099498: 0000: 00002140 42001004 t0 write SP_VS_PARAM_REG (22c6) SP_VS_PARAM_REG: { POSREGID = r1.x | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } SP_VS_OUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } UNKNOWN_22D7: 0xfcfc00 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 000994a0: 0000: 001922c6 0010fc04 00001e00 00000000 00000000 00000000 00000000 00000000 * 000994e0: 0040: 00000000 00000000 00fcfc00 00000008 00000000 00000000 00000000 00000000 * group_id: 3 count: 28 addr: 00000000000993f0 flags: 0 000993f0: 0000: 000021c4 02000001 00002141 00040400 00002001 00000000 000022c4 00200800 00099410: 0020: 000022c5 08000002 0000230c 00000000 00002318 00000000 00002319 00000000 00099430: 0040: 00002340 00000000 00002202 fcfcfcfc 00002204 0000fcfc 00002154 00000000 00099450: 0060: 000021e7 00000000 000021c5 00000012 t0 write PC_PRIM_VTX_CNTL (21c4) PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } 000993f0: 0000: 000021c4 02000001 t0 write VPC_PACK (2141) VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } 000993f8: 0000: 00002141 00040400 t0 write UNKNOWN_2001 (2001) UNKNOWN_2001: 0 00099400: 0000: 00002001 00000000 t0 write SP_VS_CTRL_REG0 (22c4) SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 2 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 00099408: 0000: 000022c4 00200800 t0 write SP_VS_CTRL_REG1 (22c5) SP_VS_CTRL_REG1: { CONSTLENGTH = 2 | INITIALOUTSTANDING = 8 } 00099410: 0000: 000022c5 08000002 t0 write 0x230c (230c) 0x230c: 00000000 00099418: 0000: 0000230c 00000000 t0 write 0x2318 (2318) 0x2318: 00000000 00099420: 0000: 00002318 00000000 t0 write 0x2319 (2319) 0x2319: 00000000 00099428: 0000: 00002319 00000000 t0 write 0x2340 (2340) 0x2340: 00000000 00099430: 0000: 00002340 00000000 t0 write VFD_CONTROL_2 (2202) VFD_CONTROL_2: 0xfcfcfcfc 00099438: 0000: 00002202 fcfcfcfc t0 write VFD_CONTROL_4 (2204) VFD_CONTROL_4: 0xfcfc 00099440: 0000: 00002204 0000fcfc t0 write UNKNOWN_2154 (2154) UNKNOWN_2154: 0 00099448: 0000: 00002154 00000000 t0 write PC_HS_PARAM (21e7) PC_HS_PARAM: { VERTICES_OUT = 0 | SPACING = EQUAL_SPACING } 00099450: 0000: 000021e7 00000000 t0 write PC_PRIM_VTX_CNTL2 (21c5) PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 00099458: 0000: 000021c5 00000012 t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = USE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x200000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 3 } draw[6] register values + 00000000 0xcc4: 00000000 + 00000004 UNKNOWN_0CC5: 0x4 + 80200000 0xd03: 80200000 !+ 00000001 HLSQ_MODE_CONTROL: 0x1 + 00000000 UNKNOWN_0E42: 0 + 00000100 VPC_DEBUG_ECO_CONTROL: 0x100 + 00040000 UNKNOWN_0EC2: 0x40000 !+ 0000001e SP_MODE_CONTROL: 0x1e !+ 00000028 TPL1_TP_MODE_CONTROL: 0x28 !+ 00080000 GRAS_CL_CLIP_CNTL: { 0x80000 } + 00000000 UNKNOWN_2001: 0 + 00000000 0x2002: 00000000 + 00000001 GRAS_CNTL: { IJ_PERSP } + 0007fdff GRAS_CL_GB_CLIP_ADJ: { HORZ = 511 | VERT = 511 } + 41900000 GRAS_CL_VPORT_XOFFSET_0: 18.000000 + 41800000 GRAS_CL_VPORT_XSCALE_0: 16.000000 + 41e80000 GRAS_CL_VPORT_YOFFSET_0: 29.000000 + 41800000 GRAS_CL_VPORT_YSCALE_0: 16.000000 + 3f000000 GRAS_CL_VPORT_ZOFFSET_0: 0.500000 + 3f000000 GRAS_CL_VPORT_ZSCALE_0: 0.500000 + ffc00010 GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 4092.000000 } + 00000008 GRAS_SU_POINT_SIZE: 0.500000 + 00000000 0x2072: 00000000 !+ 00000000 GRAS_ALPHA_CONTROL: { 0 } + 00000000 GRAS_SU_POLY_OFFSET_SCALE: 0.000000 + 00000000 GRAS_SU_POLY_OFFSET_OFFSET: 0.000000 + 00000000 GRAS_SU_POLY_OFFSET_CLAMP: 0.000000 + 00000000 GRAS_DEPTH_CONTROL: { FORMAT = DEPTH4_NONE } !+ 00102014 GRAS_SU_MODE_CONTROL: { FRONT_CW | LINEHALFWIDTH = 0.500000 | MSAA_ENABLE | RENDERING_PASS } !+ 00000200 GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 4 | RASTER_MODE = 0 } !+ 000d0002 GRAS_SC_SCREEN_SCISSOR_TL: { X = 2 | Y = 13 } !+ 002c0021 GRAS_SC_SCREEN_SCISSOR_BR: { X = 33 | Y = 44 } !+ 00000000 RB_RENDER_CONTROL: { 0 } !+ 00008000 RB_MSAA_CONTROL: { SAMPLES = 4 } !+ 00001200 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 4 | IJ_PERSP_PIXEL } !+ 07000c00 RB_MRT[0].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0x7 } !+ 0010029a RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB4_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_ALWAYS | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 1024 } !+ 00000000 RB_MRT[0].BASE: 0 !+ 00000200 RB_MRT[0].CONTROL3: { STRIDE = 64 } + 00000000 RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } + 00000e00 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } !+ ffff0501 RB_FS_OUTPUT: { ENABLE_BLEND = 0x1 | INDEPENDENT_BLEND | SAMPLE_MASK = 0xffff | 0x400 } + 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } + 00000001 RB_FS_OUTPUT_REG: { MRT = 1 } + 00000000 RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } + 00000000 RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTH4_NONE | DEPTH_BASE = 0 } + 00000000 RB_DEPTH_PITCH: 0 + 00000000 RB_DEPTH_PITCH2: 0 + 00000000 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } + 00000000 RB_STENCIL_INFO: { STENCIL_BASE = 0 } + 00000000 RB_STENCIL_PITCH: 0 + 00000000 0x210a: 00000000 + 00000000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } + 00000000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } !+ 42001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 } + 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } !+ 00000000 VPC_VARYING_INTERP[0].MODE: 0 !+ 00000000 VPC_VARYING_PS_REPL[0].MODE: 0 + 00000000 UNKNOWN_2152: 0 + 00000000 UNKNOWN_2153: 0 + 00000000 UNKNOWN_2154: 0 + 00000000 UNKNOWN_2155: 0 + 00000000 UNKNOWN_2156: 0 + 00000000 0x215c: 00000000 + 00000000 0x215d: 00000000 + 00000000 0x215e: 00000000 + 00000000 0x215f: 00000000 + 00000000 0x2161: 00000000 + 00000000 0x2162: 00000000 + 00000000 0x2163: 00000000 + 00000000 0x2164: 00000000 + 00000000 0x2166: 00000000 + 00000000 0x2167: 00000000 + 00000000 0x2168: 00000000 + 00000000 0x2169: 00000000 + 00000000 0x216b: 00000000 + 00000000 0x216c: 00000000 + 00000000 0x216d: 00000000 + 00000000 VPC_SO_FLUSH_WADDR_3: 0 !+ 0000001f UNKNOWN_21C3: 0x1f !+ 02000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + ffffffff PC_RESTART_INDEX: 0xffffffff + 00000000 PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } + 00000001 UNKNOWN_21E6: 0x1 + 00000000 PC_HS_PARAM: { VERTICES_OUT = 0 | SPACING = EQUAL_SPACING } !+ 082a0008 VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } !+ fcfc0081 VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } + fcfcfcfc VFD_CONTROL_2: 0xfcfcfcfc !+ 0000fc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } + 0000fcfc VFD_CONTROL_4: 0xfcfc + 00000000 VFD_INDEX_OFFSET: 0 + 00000000 UNKNOWN_2209: 0 + 0008080f VFD_FETCH[0].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 | SWITCHNEXT } !+ 00099390 VFD_FETCH[0].INSTR_1: 0x99390 + 00000060 VFD_FETCH[0].INSTR_2: { SIZE = 0x60 } + 00000001 VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } + 0000080f VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 } !+ 000993c0 VFD_FETCH[0x1].INSTR_1: 0x993c0 + 00000030 VFD_FETCH[0x1].INSTR_2: { SIZE = 0x30 } + 00000001 VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } + 7000411f VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID | SWITCHNEXT } + 3000011f VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID } + 00060010 SP_SP_CTRL_REG: { 0x60010 } + 000005c3 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } !+ 00200800 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 2 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } !+ 08000002 SP_VS_CTRL_REG1: { CONSTLENGTH = 2 | INITIALOUTSTANDING = 8 } !+ 0010fc04 SP_VS_PARAM_REG: { POSREGID = r1.x | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } !+ 00001e00 SP_VS_OUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00fcfc00 UNKNOWN_22D7: 0xfcfc00 + 00000008 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } !+ 00049000 SP_VS_OBJ_START: 0x49000 00049000: 0000: 00000000 13000000 00000000 00000000 00000000 00000000 00000000 00000000 * :0:0000:0000[13000000x_00000000x] (sy)end :0:0001:0001[00000000x_00000000x] nop :0:0002:0002[00000000x_00000000x] nop :0:0003:0003[00000000x_00000000x] nop :0:0004:0004[00000000x_00000000x] nop Stats: - shaderdb: 5 instr, 4 nops, 1 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 0 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 0 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) !+ 00000001 SP_VS_LENGTH_REG: 1 !+ 00340412 SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE } !+ 80100002 SP_FS_CTRL_REG1: { CONSTLENGTH = 2 | VARYING | 0x80000000 } !+ 7e020000 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } !+ 00046000 SP_FS_OBJ_START: 0x46000 00046000: 0000: 00002000 5730cb00 00000000 03000000 00000000 00000000 00000000 00000000 * :2:0000:0000[5730cb00x_00002000x] (sy)(rpt3)bary.f (ei)hr0.x, (r)0, r0.x :0:0001:0004[03000000x_00000000x] end :0:0002:0005[00000000x_00000000x] nop :0:0003:0006[00000000x_00000000x] nop :0:0004:0007[00000000x_00000000x] nop :0:0005:0008[00000000x_00000000x] nop Stats: - shaderdb: 9 instr, 4 nops, 5 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 1 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 4 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) + 00000001 SP_FS_LENGTH_REG: 1 !+ fc00fc01 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r63.x } !+ 0001a100 SP_FS_MRT[0].REG: { REGID = r0.x | HALF_PRECISION | MRTFORMAT = RB4_R8G8B8A8_UNORM } + 00000000 0x230c: 00000000 + 7e020000 SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } + 00000000 SP_HS_OBJ_START: 0 + 00000000 0x2318: 00000000 + 00000000 0x2319: 00000000 + 7e020000 SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } + 00000000 SP_DS_OBJ_START: 0 + 00000000 0x2340: 00000000 + 7e020000 SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } + 00000000 SP_GS_OBJ_START: 0 + 00000808 TPL1_TP_TEX_OFFSET: 0x808 + 00000000 TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } !+ 00000002 0x2382: 00000002 !+ 00000000 TPL1_TP_FS_TEX_COUNT: 0 !+ 080604f0 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0x600a0 } !+ fcfc1108 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x1008 } !+ fff3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } + fcfcfc00 HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } !+ 00fcfc00 HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r0.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } !+ 01010002 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 2 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 1 } !+ 017f0202 HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 2 | CONSTOBJECTOFFSET = 2 | ENABLED | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 } !+ 007e0200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } !+ 007e0200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } !+ 007e0200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } !+ 00000003 HLSQ_UPDATE_CONTROL: 0x3 000555ac: 0000: c0023800 00200984 00000001 00000003 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 18 | GROUP_ID = 1 } { ADDR_LO = 0x996d0 } 000555bc: 0000: c0014300 01000012 000996d0 group_id: 1 count: 18 addr: 00000000000996d0 flags: 0 000996d0: 0000: 00002200 082a0008 00002201 fcfc0081 00002203 0000fc00 0007220a 0008080f 000996f0: 0020: 00099670 00000060 00000001 0000080f 000996a0 00000030 00000001 0001228a 00099710: 0040: 7000411f 3000011f t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } 000996d0: 0000: 00002200 082a0008 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } 000996d8: 0000: 00002201 fcfc0081 t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } 000996e0: 0000: 00002203 0000fc00 t0 write VFD_FETCH[0].INSTR_0 (220a) VFD_FETCH[0].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 | SWITCHNEXT } VFD_FETCH[0].INSTR_1: 0x99670 VFD_FETCH[0].INSTR_2: { SIZE = 0x60 } VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 } VFD_FETCH[0x1].INSTR_1: 0x996a0 VFD_FETCH[0x1].INSTR_2: { SIZE = 0x30 } VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } 000996e8: 0000: 0007220a 0008080f 00099670 00000060 00000001 0000080f 000996a0 00000030 00099708: 0020: 00000001 t0 write VFD_DECODE[0].INSTR (228a) VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID | SWITCHNEXT } VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID } 0009970c: 0000: 0001228a 7000411f 3000011f t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = USE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x200000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 3 } draw[7] register values + 082a0008 VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } + fcfc0081 VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } + 0000fc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } + 0008080f VFD_FETCH[0].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 | SWITCHNEXT } !+ 00099670 VFD_FETCH[0].INSTR_1: 0x99670 + 00000060 VFD_FETCH[0].INSTR_2: { SIZE = 0x60 } + 00000001 VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } + 0000080f VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 } !+ 000996a0 VFD_FETCH[0x1].INSTR_1: 0x996a0 + 00000030 VFD_FETCH[0x1].INSTR_2: { SIZE = 0x30 } + 00000001 VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } + 7000411f VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID | SWITCHNEXT } + 3000011f VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID } 000555c8: 0000: c0023800 00200984 00000001 00000003 0016b094: 0000: c0013f00 00055328 000000ac t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 0016b0a0: 0000: c0014300 00040000 00000000 t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:001703dc ibsize:000000f7 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 001703dc: 0000: c0002600 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x4 001703e4: 0000: 00000ec3 00000004 t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x68 001703ec: 0000: 00000f03 00000068 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 001703f4: 0000: c0002600 00000000 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } 001703fc: 0000: 000023c0 080004f0 t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = 0x1d } event (null) 00170404: 0000: c0004600 0000001d t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = FACENESS_FLUSH } event FACENESS_FLUSH 0017040c: 0000: c0004600 0000001c t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00170414: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0 0017041c: 0000: 00000cc6 00000000 t0 write UNKNOWN_0E42 (0e42) UNKNOWN_0E42: 0 00170424: 0000: 00000e42 00000000 t0 write HLSQ_MODE_CONTROL (0e05) HLSQ_MODE_CONTROL: 0x2 0017042c: 0000: 00000e05 00000002 t0 write UNKNOWN_0CC5 (0cc5) UNKNOWN_0CC5: 0x4 00170434: 0000: 00000cc5 00000004 t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x7 0017043c: 0000: 000023db 00000007 t0 write VFD_CONTROL_2 (2202) VFD_CONTROL_2: 0xfcfcfcfc 00170444: 0000: 00002202 fcfcfcfc t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } 0017044c: 0000: 00002203 fcfcfc00 t0 write VFD_CONTROL_4 (2204) VFD_CONTROL_4: 0xfcfc 00170454: 0000: 00002204 0000fcfc t0 write VFD_INDEX_OFFSET (2208) VFD_INDEX_OFFSET: 0 0017045c: 0000: 00002208 00000000 t0 write UNKNOWN_2209 (2209) UNKNOWN_2209: 0 00170464: 0000: 00002209 00000000 t0 write UNKNOWN_2152 (2152) UNKNOWN_2152: 0 UNKNOWN_2153: 0 0017046c: 0000: 00012152 00000000 00000000 t0 write UNKNOWN_2156 (2156) UNKNOWN_2156: 0 00170478: 0000: 00002156 00000000 t0 write UNKNOWN_2154 (2154) UNKNOWN_2154: 0 00170480: 0000: 00002154 00000000 t0 write UNKNOWN_2155 (2155) UNKNOWN_2155: 0 00170488: 0000: 00002155 00000000 t0 write UNKNOWN_21C3 (21c3) UNKNOWN_21C3: 0x1d 00170490: 0000: 000021c3 0000001d t0 write PC_PRIM_VTX_CNTL2 (21c5) PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 00170498: 0000: 000021c5 00000012 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 001704a0: 0000: 000021e5 00000000 t0 write GRAS_SU_MODE_CONTROL (2078) GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } 001704a8: 0000: 00002078 00000000 t0 write UNKNOWN_2001 (2001) UNKNOWN_2001: 0 001704b0: 0000: 00002001 00000000 t0 write GRAS_CNTL (2003) GRAS_CNTL: { IJ_PERSP } 001704b8: 0000: 00002003 00000001 t0 write GRAS_CL_CLIP_CNTL (2000) GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } 001704c0: 0000: 00002000 00188000 t0 write TPL1_TP_TEX_COUNT (2381) TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } 001704c8: 0000: 00002381 00000000 t0 write TPL1_TP_FS_TEX_COUNT (23a0) TPL1_TP_FS_TEX_COUNT: 0x3 001704d0: 0000: 000023a0 00000003 t0 write RB_ALPHA_CONTROL (20f8) RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } 001704d8: 0000: 000020f8 00000e00 t0 write RB_RENDER_COMPONENTS (20fb) RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } 001704e0: 0000: 000020fb 0000000f t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 001704e8: 0000: c0014300 00040000 00000000 t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } 001704f4: 0000: 00002200 000a0000 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } 001704fc: 0000: 00002201 fc030000 t0 write SP_INSTR_CACHE_CTRL (22c1) SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } 00170504: 0000: 000022c1 000005c3 t0 write HLSQ_CONTROL_1_REG (23c1) HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } 0017050c: 0000: 000023c1 fcfc0120 t0 write HLSQ_CONTROL_2_REG (23c2) HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 00170514: 0000: 000023c2 27f3f3f0 t0 write HLSQ_VS_CONTROL_REG (23c5) HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } 0017051c: 0000: 000023c5 02010042 t0 write HLSQ_FS_CONTROL_REG (23c6) HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00170524: 0000: 000023c6 0041423e t0 write HLSQ_HS_CONTROL_REG (23c7) HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 0017052c: 0000: 000023c7 00404200 t0 write HLSQ_DS_CONTROL_REG (23c8) HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00170534: 0000: 000023c8 00404200 t0 write HLSQ_GS_CONTROL_REG (23c9) HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 0017053c: 0000: 000023c9 00404200 t0 write HLSQ_CS_CONTROL_REG (23ca) HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } 00170544: 0000: 000023ca 00004200 t0 write SP_SP_CTRL_REG (22c0) SP_SP_CTRL_REG: { 0x60010 } 0017054c: 0000: 000022c0 00060010 t0 write UNKNOWN_21E6 (21e6) UNKNOWN_21E6: 0x1 00170554: 0000: 000021e6 00000001 t0 write SP_VS_CTRL_REG0 (22c4) SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 0017055c: 0000: 000022c4 00200c10 t0 write SP_VS_CTRL_REG1 (22c5) SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } 00170564: 0000: 000022c5 01000042 t0 write VPC_ATTR (2140) VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | 0x40000000 } 0017056c: 0000: 00002140 40001004 t0 write VPC_PACK (2141) VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } 00170574: 0000: 00002141 00040400 t0 write PC_PRIM_VTX_CNTL (21c4) PC_PRIM_VTX_CNTL: { VAROUT = 1 } 0017057c: 0000: 000021c4 00000001 t0 write SP_VS_PARAM_REG (22c6) SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } UNKNOWN_22D7: 0xfcfc00 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 00170584: 0000: 001922c6 0010fc03 00001e03 00000000 00000000 00000000 00000000 00000000 * 001705c4: 0040: 00000000 00000000 00fcfc00 00000008 00000000 00000000 00000000 00000000 * t0 write SP_VS_OBJ_OFFSET_REG (22e0) SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 001705f0: 0000: 000022e0 00000000 t0 write SP_VS_OBJ_START (22e1) SP_VS_OBJ_START: 0x1 001705f8: 0000: 000022e1 00000001 t0 write SP_VS_LENGTH_REG (22e5) SP_VS_LENGTH_REG: 2 00170600: 0000: 000022e5 00000002 t3 opcode: CP_LOAD_STATE4 (30) (67 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } :2:0000:0000[56d81803x_20020003x] (sy)(ss)(nop3) shl.b r0.w, r0.w, 2 :1:0001:0004[20150000x_00000003x] cov.s32s16 hr0.x, r0.w :0:0002:0005[00000200x_00000000x] (rpt2)nop :1:0003:0008[201100f4x_00000000x] mova a0.x, hr0.x :0:0004:0009[00000500x_00000000x] (rpt5)nop :1:0005:0015[20154003x_00000c20x] mov.s32s32 r0.w, c :1:0006:0016[20154004x_00000c21x] mov.s32s32 r1.x, c :1:0007:0017[20154005x_00000c22x] mov.s32s32 r1.y, c :1:0008:0018[20156006x_00000c23x] (ul)mov.s32s32 r1.z, c :0:0009:0019[03000000x_00000000x] end :2:0010:0020[46f00007x_20050000x] shr.b r1.w, r0.x, 5 :2:0011:0021[43980008x_201f0000x] (nop2) and.b r2.x, r0.x, 31 :2:0012:0024[43980807x_201f0007x] (nop3) and.b r1.w, r1.w, 31 :2:0013:0028[46100807x_20100007x] (nop1) mul.u24 r1.w, r1.w, 16 :3:0014:0030[62040007x_00071014x] mad.u24 r1.w, c5.x, r2.x, r1.w :0:0015:0031[00000500x_00000000x] (rpt5)nop :6:0016:0037[c2c60f00x_04800006x] stlw.u32 l[r1.w], r0.w, 4 :0:0017:0038[04800000x_00000000x] chmask :0:0018:0039[05000000x_00000000x] chsh Stats: - shaderdb: 40 instr, 24 nops, 16 non-nops, 5 mov, 1 cov - shaderdb: 0 last-baryf, 0 half, 2 full, 5 constlen - shaderdb: 27 cat0, 6 cat1, 5 cat2, 1 cat3, 0 cat4, 0 cat5, 1 cat6, 0 cat7 - shaderdb: 0 sstall, 1 (ss), 1 (sy) 00170608: 0000: c0413000 00a00000 00000000 20020003 56d81803 00000003 20150000 00000000 00170628: 0020: 00000200 00000000 201100f4 00000000 00000500 00000c20 20154003 00000c21 00170648: 0040: 20154004 00000c22 20154005 00000c23 20156006 00000000 03000000 20050000 00170668: 0060: 46f00007 201f0000 43980008 201f0007 43980807 20100007 46100807 00071014 00170688: 0080: 62040007 00000000 00000500 04800006 c2c60f00 00000000 04800000 00000000 001706a8: 00a0: 05000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 * t0 write GRAS_SC_CONTROL (207b) GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = 0 | MSAA_DISABLE | RASTER_MODE = 0 } 00170714: 0000: 0000207b 00000808 t0 write RB_MSAA_CONTROL (20a2) RB_MSAA_CONTROL: { DISABLE | SAMPLES = 0 } 0017071c: 0000: 000020a2 00001000 t0 write RB_RENDER_CONTROL (20a1) RB_RENDER_CONTROL: { DISABLE_COLOR_PIPE | 0x2 } 00170724: 0000: 000020a1 00000022 t0 write RB_DEPTH_CONTROL (2101) RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } 0017072c: 0000: 00002101 00000000 t0 write GRAS_ALPHA_CONTROL (2073) GRAS_ALPHA_CONTROL: { 0x2 } 00170734: 0000: 00002073 00000002 t0 write RB_STENCIL_CONTROL (2106) RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } 0017073c: 0000: 00002106 00000000 t0 write RB_COPY_CONTROL (20fc) RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_FOUR | MODE = RB_COPY_DEPTH_STENCIL | FASTCLEAR = 0 | GMEM_BASE = 0 } RB_COPY_DEST_BASE: { BASE = 0x4f000 } RB_COPY_DEST_PITCH: { PITCH = 256 } RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_DISABLE | COMPONENT_ENABLE = 0xf | ENDIAN = ENDIAN_NONE | TILE = TILE4_3 } 00170744: 0000: 000320fc 00000052 0004f000 00000008 0303c068 t0 write UNKNOWN_20EF (20ef) UNKNOWN_20EF: 0 00170758: 0000: 000020ef 00000000 t0 write GRAS_SC_SCREEN_SCISSOR_TL (207c) GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } 00170760: 0000: 0001207c 00000000 003f003f t0 write RB_FRAME_BUFFER_DIMENSION (0ce0) RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } 0017076c: 0000: 00000ce0 00400040 t0 write 0xce1 (0ce1) 0xce1: 00000000 00170774: 0000: 00000ce1 00000000 t3 opcode: CP_LOAD_STATE4 (30) (11 dwords) { DST_OFF = 8 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } 00170788: 0.000000 0.000000 1.000000 1.000000 64.000000 64.000000 1.000000 1.000000 00170788: 0000: 00000000 00000000 3f800000 3f800000 42800000 42800000 3f800000 3f800000 0017077c: 0000: c0093000 00a00008 00000001 00000000 00000000 3f800000 3f800000 42800000 0017079c: 0020: 42800000 3f800000 3f800000 t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x80000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 2 } draw[8] register values + 00000004 UNKNOWN_0CC5: 0x4 + 00000000 UNKNOWN_0CC6: 0 + 00400040 RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } + 00000000 0xce1: 00000000 !+ 00000002 HLSQ_MODE_CONTROL: 0x2 + 00000000 UNKNOWN_0E42: 0 !+ 00000004 SP_MODE_CONTROL: 0x4 !+ 00000068 TPL1_TP_MODE_CONTROL: 0x68 !+ 00188000 GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } + 00000000 UNKNOWN_2001: 0 + 00000001 GRAS_CNTL: { IJ_PERSP } !+ 00000002 GRAS_ALPHA_CONTROL: { 0x2 } !+ 00000000 GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } !+ 00000808 GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = 0 | MSAA_DISABLE | RASTER_MODE = 0 } !+ 00000000 GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } !+ 003f003f GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } !+ 00000022 RB_RENDER_CONTROL: { DISABLE_COLOR_PIPE | 0x2 } !+ 00001000 RB_MSAA_CONTROL: { DISABLE | SAMPLES = 0 } + 00000000 UNKNOWN_20EF: 0 + 00000e00 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } + 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } !+ 00000052 RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_FOUR | MODE = RB_COPY_DEPTH_STENCIL | FASTCLEAR = 0 | GMEM_BASE = 0 } + 0004f000 RB_COPY_DEST_BASE: { BASE = 0x4f000 } + 00000008 RB_COPY_DEST_PITCH: { PITCH = 256 } !+ 0303c068 RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_DISABLE | COMPONENT_ENABLE = 0xf | ENDIAN = ENDIAN_NONE | TILE = TILE4_3 } + 00000000 RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } + 00000000 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } !+ 40001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | 0x40000000 } + 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } + 00000000 UNKNOWN_2152: 0 + 00000000 UNKNOWN_2153: 0 + 00000000 UNKNOWN_2154: 0 + 00000000 UNKNOWN_2155: 0 + 00000000 UNKNOWN_2156: 0 !+ 0000001d UNKNOWN_21C3: 0x1d !+ 00000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 } + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + 00000000 PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } + 00000001 UNKNOWN_21E6: 0x1 !+ 000a0000 VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } !+ fc030000 VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } + fcfcfcfc VFD_CONTROL_2: 0xfcfcfcfc !+ fcfcfc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } + 0000fcfc VFD_CONTROL_4: 0xfcfc + 00000000 VFD_INDEX_OFFSET: 0 + 00000000 UNKNOWN_2209: 0 + 00060010 SP_SP_CTRL_REG: { 0x60010 } + 000005c3 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } !+ 00200c10 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } !+ 01000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } !+ 0010fc03 SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } !+ 00001e03 SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00fcfc00 UNKNOWN_22D7: 0xfcfc00 + 00000008 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } !+ 00000001 SP_VS_OBJ_START: 0x1 !+ 00000002 SP_VS_LENGTH_REG: 2 + 00000000 TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } !+ 00000003 TPL1_TP_FS_TEX_COUNT: 0x3 !+ 080004f0 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } !+ fcfc0120 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } !+ 27f3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } !+ 02010042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } !+ 0041423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } !+ 00404200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } !+ 00404200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } !+ 00404200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00004200 HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } !+ 00000007 HLSQ_UPDATE_CONTROL: 0x7 001707a8: 0000: c0023800 00080888 00000001 00000002 0016b0ac: 0000: c0013f00 001703dc 000000f7 t3 opcode: (null) (1d) (2 dwords) 0016b0b8: 0000: c0001d00 00000000 ############################################################ vertices: 0 ############################################################ cmdstream: 8 dwords t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:000555d8 ibsize:00000155 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 000555d8: 0000: c0002600 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x4 000555e0: 0000: 00000ec3 00000004 t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x68 000555e8: 0000: 00000f03 00000068 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 000555f0: 0000: c0002600 00000000 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } 000555f8: 0000: 000023c0 080004f0 t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = 0x1d } event (null) 00055600: 0000: c0004600 0000001d t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = FACENESS_FLUSH } event FACENESS_FLUSH 00055608: 0000: c0004600 0000001c t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00055610: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0 00055618: 0000: 00000cc6 00000000 t0 write UNKNOWN_0E42 (0e42) UNKNOWN_0E42: 0 00055620: 0000: 00000e42 00000000 t0 write HLSQ_MODE_CONTROL (0e05) HLSQ_MODE_CONTROL: 0x2 00055628: 0000: 00000e05 00000002 t0 write UNKNOWN_0CC5 (0cc5) UNKNOWN_0CC5: 0x4 00055630: 0000: 00000cc5 00000004 t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x7 00055638: 0000: 000023db 00000007 t0 write VFD_CONTROL_2 (2202) VFD_CONTROL_2: 0xfcfcfcfc 00055640: 0000: 00002202 fcfcfcfc t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } 00055648: 0000: 00002203 fcfcfc00 t0 write VFD_CONTROL_4 (2204) VFD_CONTROL_4: 0xfcfc 00055650: 0000: 00002204 0000fcfc t0 write VFD_INDEX_OFFSET (2208) VFD_INDEX_OFFSET: 0 00055658: 0000: 00002208 00000000 t0 write UNKNOWN_2209 (2209) UNKNOWN_2209: 0 00055660: 0000: 00002209 00000000 t0 write UNKNOWN_2152 (2152) UNKNOWN_2152: 0 UNKNOWN_2153: 0 00055668: 0000: 00012152 00000000 00000000 t0 write UNKNOWN_2156 (2156) UNKNOWN_2156: 0 00055674: 0000: 00002156 00000000 t0 write UNKNOWN_2154 (2154) UNKNOWN_2154: 0 0005567c: 0000: 00002154 00000000 t0 write UNKNOWN_2155 (2155) UNKNOWN_2155: 0 00055684: 0000: 00002155 00000000 t0 write UNKNOWN_21C3 (21c3) UNKNOWN_21C3: 0x1d 0005568c: 0000: 000021c3 0000001d t0 write PC_PRIM_VTX_CNTL2 (21c5) PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 00055694: 0000: 000021c5 00000012 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 0005569c: 0000: 000021e5 00000000 t0 write GRAS_SU_MODE_CONTROL (2078) GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } 000556a4: 0000: 00002078 00000000 t0 write UNKNOWN_2001 (2001) UNKNOWN_2001: 0 000556ac: 0000: 00002001 00000000 t0 write GRAS_CNTL (2003) GRAS_CNTL: { IJ_PERSP } 000556b4: 0000: 00002003 00000001 t0 write GRAS_CL_CLIP_CNTL (2000) GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } 000556bc: 0000: 00002000 00188000 t0 write TPL1_TP_TEX_COUNT (2381) TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } 000556c4: 0000: 00002381 00000000 t0 write TPL1_TP_FS_TEX_COUNT (23a0) TPL1_TP_FS_TEX_COUNT: 0x3 000556cc: 0000: 000023a0 00000003 t0 write RB_ALPHA_CONTROL (20f8) RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } 000556d4: 0000: 000020f8 00000e00 t0 write RB_RENDER_COMPONENTS (20fb) RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } 000556dc: 0000: 000020fb 0000000f t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 000556e4: 0000: c0014300 00040000 00000000 t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } 000556f0: 0000: 00002200 000a0000 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } 000556f8: 0000: 00002201 fc030000 t0 write SP_INSTR_CACHE_CTRL (22c1) SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } 00055700: 0000: 000022c1 000005c3 t0 write HLSQ_CONTROL_1_REG (23c1) HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } 00055708: 0000: 000023c1 fcfc0120 t0 write HLSQ_CONTROL_2_REG (23c2) HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 00055710: 0000: 000023c2 27f3f3f0 t0 write HLSQ_VS_CONTROL_REG (23c5) HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } 00055718: 0000: 000023c5 02010042 t0 write HLSQ_FS_CONTROL_REG (23c6) HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 1 } 00055720: 0000: 000023c6 0141423e t0 write HLSQ_HS_CONTROL_REG (23c7) HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00055728: 0000: 000023c7 00404200 t0 write HLSQ_DS_CONTROL_REG (23c8) HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00055730: 0000: 000023c8 00404200 t0 write HLSQ_GS_CONTROL_REG (23c9) HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00055738: 0000: 000023c9 00404200 t0 write HLSQ_CS_CONTROL_REG (23ca) HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } 00055740: 0000: 000023ca 00004200 t0 write SP_SP_CTRL_REG (22c0) SP_SP_CTRL_REG: { 0x60010 } 00055748: 0000: 000022c0 00060010 t0 write UNKNOWN_21E6 (21e6) UNKNOWN_21E6: 0x1 00055750: 0000: 000021e6 00000001 t0 write SP_VS_CTRL_REG0 (22c4) SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 00055758: 0000: 000022c4 00200c10 t0 write SP_VS_CTRL_REG1 (22c5) SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } 00055760: 0000: 000022c5 01000042 t0 write VPC_ATTR (2140) VPC_ATTR: { TOTALATTR = 8 | THRDASSIGN = 1 | ENABLE | 0x40000000 } 00055768: 0000: 00002140 42001008 t0 write VPC_PACK (2141) VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 8 | NUMNONPOSVSVAR = 6 } 00055770: 0000: 00002141 00060800 t0 write PC_PRIM_VTX_CNTL (21c4) PC_PRIM_VTX_CNTL: { VAROUT = 1 } 00055778: 0000: 000021c4 00000001 t0 write SP_VS_PARAM_REG (22c6) SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 2 } SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r1.w | B_COMPMASK = 0x3 } SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } UNKNOWN_22D7: 0xfcfc00 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 12 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 00055780: 0000: 001922c6 0020fc03 06071e03 00000000 00000000 00000000 00000000 00000000 * 000557c0: 0040: 00000000 00000000 00fcfc00 00000c08 00000000 00000000 00000000 00000000 * t0 write SP_VS_OBJ_OFFSET_REG (22e0) SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 000557ec: 0000: 000022e0 00000000 t0 write SP_VS_OBJ_START (22e1) SP_VS_OBJ_START: 0x1 000557f4: 0000: 000022e1 00000001 t0 write SP_VS_LENGTH_REG (22e5) SP_VS_LENGTH_REG: 2 000557fc: 0000: 000022e5 00000002 t3 opcode: CP_LOAD_STATE4 (30) (67 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } :2:0000:0000[56d81803x_20020003x] (sy)(ss)(nop3) shl.b r0.w, r0.w, 2 :1:0001:0004[20150000x_00000003x] cov.s32s16 hr0.x, r0.w :0:0002:0005[00000200x_00000000x] (rpt2)nop :1:0003:0008[201100f4x_00000000x] mova a0.x, hr0.x :0:0004:0009[00000500x_00000000x] (rpt5)nop :1:0005:0015[20154003x_00000c20x] mov.s32s32 r0.w, c :1:0006:0016[20154004x_00000c21x] mov.s32s32 r1.x, c :1:0007:0017[20154007x_00000c22x] mov.s32s32 r1.w, c :1:0008:0018[20156008x_00000c23x] (ul)mov.s32s32 r2.x, c :1:0009:0019[20554005x_00000000x] mov.s32s32 r1.y, 0 :1:0010:0020[20554006x_3f800000x] mov.s32s32 r1.z, 1065353216 :0:0011:0021[03000000x_00000000x] end :2:0012:0022[46f00009x_20050000x] shr.b r2.y, r0.x, 5 :2:0013:0023[4398000ax_201f0000x] (nop2) and.b r2.z, r0.x, 31 :2:0014:0026[43980809x_201f0009x] (nop3) and.b r2.y, r2.y, 31 :2:0015:0030[46100809x_20180009x] (nop1) mul.u24 r2.y, r2.y, 24 :3:0016:0032[62050009x_00091014x] mad.u24 r2.y, c5.x, r2.z, r2.y :0:0017:0033[00000500x_00000000x] (rpt5)nop :6:0018:0039[c2c61300x_04800006x] stlw.u32 l[r2.y], r0.w, 4 :6:0019:0040[c2c61310x_0280000ex] stlw.u32 l[r2.y+16], r1.w, 2 :0:0020:0041[04800000x_00000000x] chmask :0:0021:0042[05000000x_00000000x] chsh Stats: - shaderdb: 43 instr, 24 nops, 19 non-nops, 7 mov, 1 cov - shaderdb: 0 last-baryf, 0 half, 3 full, 5 constlen - shaderdb: 27 cat0, 8 cat1, 5 cat2, 1 cat3, 0 cat4, 0 cat5, 2 cat6, 0 cat7 - shaderdb: 0 sstall, 1 (ss), 1 (sy) 00055804: 0000: c0413000 00a00000 00000000 20020003 56d81803 00000003 20150000 00000000 00055824: 0020: 00000200 00000000 201100f4 00000000 00000500 00000c20 20154003 00000c21 00055844: 0040: 20154004 00000c22 20154007 00000c23 20156008 00000000 20554005 3f800000 00055864: 0060: 20554006 00000000 03000000 20050000 46f00009 201f0000 4398000a 201f0009 00055884: 0080: 43980809 20180009 46100809 00091014 62050009 00000000 00000500 04800006 000558a4: 00a0: c2c61300 0280000e c2c61310 00000000 04800000 00000000 05000000 00000000 * t0 write HLSQ_CONTROL_3_REG (23c3) HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } 00055910: 0000: 000023c3 fcfcfc00 t0 write HLSQ_CONTROL_4_REG (23c4) HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } 00055918: 0000: 000023c4 00fcfcfc t0 write SP_FS_CTRL_REG0 (22e8) SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 0 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE | PIXLODENABLE } SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 } 00055920: 0000: 000122e8 00700402 8010003e t0 write SP_FS_OBJ_OFFSET_REG (22ea) SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 } 0005592c: 0000: 000022ea 40420000 t0 write SP_FS_OBJ_START (22eb) SP_FS_OBJ_START: 0x1 00055934: 0000: 000022eb 00000001 t0 write SP_FS_LENGTH_REG (22ef) SP_FS_LENGTH_REG: 1 0005593c: 0000: 000022ef 00000001 t0 write SP_FS_OUTPUT_REG (22f0) SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r0.x | SAMPLEMASK_REGID = r0.x } 00055944: 0000: 000022f0 00000001 t0 write VPC_VARYING_INTERP[0].MODE (2142) VPC_VARYING_INTERP[0].MODE: 0xe000 0005594c: 0000: 00002142 0000e000 t0 write RB_FS_OUTPUT_REG (2100) RB_FS_OUTPUT_REG: { MRT = 1 } 00055954: 0000: 00002100 00000001 t3 opcode: CP_LOAD_STATE4 (30) (35 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 1 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } :2:0000:0000[57309902x_00002004x] (sy)(ss)(rpt1)bary.f (ei)r0.z, (r)4, r0.x :0:0001:0002[00000500x_00000000x] (rpt5)nop :5:0002:0008[a0c01f00x_00000005x] sam (f32)(xyzw)r0.x, r0.z, s#0, t#0 :0:0003:0009[03000000x_00000000x] end :0:0004:0010[00000000x_00000000x] nop :0:0005:0011[00000000x_00000000x] nop :0:0006:0012[00000000x_00000000x] nop :0:0007:0013[00000000x_00000000x] nop Stats: - shaderdb: 14 instr, 10 nops, 4 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 0 half, 1 full, 0 constlen - shaderdb: 11 cat0, 0 cat1, 2 cat2, 0 cat3, 0 cat4, 1 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 1 (ss), 1 (sy) 0005595c: 0000: c0213000 00700000 00000000 00002004 57309902 00000000 00000500 00000005 0005597c: 0020: a0c01f00 00000000 03000000 00000000 00000000 00000000 00000000 00000000 * t0 write RB_FS_OUTPUT (20f9) RB_FS_OUTPUT: { ENABLE_BLEND = 0 | SAMPLE_MASK = 0xffff } 000559e8: 0000: 000020f9 ffff0000 t0 write RB_MRT[0].CONTROL (20a4) RB_MRT[0].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0xf } 000559f0: 0000: 000020a4 0f000000 t0 write RB_MRT[0x1].CONTROL (20a9) RB_MRT[0x1].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0xf } 000559f8: 0000: 000020a9 0f000000 t0 write RB_MRT[0].BLEND_CONTROL (20a8) RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } 00055a00: 0000: 000020a8 00000000 t3 opcode: CP_LOAD_STATE4 (30) (5 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_TEX | NUM_UNIT = 1 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } { XY_MAG = A4XX_TEX_NEAREST | XY_MIN = A4XX_TEX_NEAREST | WRAP_S = A4XX_TEX_CLAMP_TO_EDGE | WRAP_T = A4XX_TEX_CLAMP_TO_EDGE | WRAP_R = A4XX_TEX_CLAMP_TO_EDGE | ANISO = A4XX_TEX_ANISO_1 | LOD_BIAS = 0.000000 | 0x60000 } { COMPARE_FUNC = FUNC_LEQUAL | UNNORM_COORDS | MIPFILTER_LINEAR_FAR | MAX_LOD = 0.000000 | MIN_LOD = 0.000000 | 0x1 } 00055a14: 0000: 00060920 00000067 00055a08: 0000: c0033000 00500000 00000000 00060920 00000067 t0 write GRAS_SC_CONTROL (207b) GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 0 | RASTER_MODE = 0 } 00055a1c: 0000: 0000207b 00000000 t0 write RB_MSAA_CONTROL (20a2) RB_MSAA_CONTROL: { SAMPLES = 0 } 00055a24: 0000: 000020a2 00000000 t0 write RB_RENDER_CONTROL (20a1) RB_RENDER_CONTROL: { 0 } 00055a2c: 0000: 000020a1 00000000 t0 write 0x2382 (2382) 0x2382: 00000000 00055a34: 0000: 00002382 00000000 t0 write RB_DEPTH_CONTROL (2101) RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } 00055a3c: 0000: 00002101 00000000 t0 write GRAS_ALPHA_CONTROL (2073) GRAS_ALPHA_CONTROL: { 0 } 00055a44: 0000: 00002073 00000000 t0 write RB_STENCIL_CONTROL (2106) RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } 00055a4c: 0000: 00002106 00000000 t0 write SP_FS_MRT[0].REG (22f1) SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = RB4_R8G8B8A8_UNORM } 00055a54: 0000: 000022f1 0001a000 t0 write RB_MRT[0].BUF_INFO (20a5) RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB4_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE4_3 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 256 } RB_MRT[0].BASE: 0x166000 RB_MRT[0].CONTROL3: { STRIDE = 0 } 00055a5c: 0000: 000220a5 000400da 00166000 00000000 t3 opcode: CP_LOAD_STATE4 (30) (11 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_TEX | NUM_UNIT = 1 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } { TILED | SWIZ_X = A4XX_TEX_X | SWIZ_Y = A4XX_TEX_Y | SWIZ_Z = A4XX_TEX_Z | SWIZ_W = A4XX_TEX_W | MIPLVLS = 0 | FMT = TFMT4_8_8_8_8_UNORM | TYPE = A4XX_TEX_2D | 0x2 } { HEIGHT = 64 | WIDTH = 64 } { PITCHALIGN = 0 | PITCH = 256 | SWAP = WZYX } { LAYERSZ = 0 | DEPTH = 1 | 0x20000 } { LAYERSZ = 4096 | BASE = 0x4f000 } { 5 = 0 } { 6 = 0 } { 7 = 0 } 00055a78: 0000: 27006883 00200040 00020000 00060000 0004f001 00000000 00000000 00000000 00055a6c: 0000: c0093000 00500000 00000001 27006883 00200040 00020000 00060000 0004f001 * t0 write VPC_VARYING_PS_REPL[0].MODE (214a) VPC_VARYING_PS_REPL[0].MODE: 0x99999999 00055a98: 0000: 0000214a 99999999 t0 write GRAS_SC_SCREEN_SCISSOR_TL (207c) GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } 00055aa0: 0000: 0001207c 00000000 003f003f t0 write GRAS_SC_WINDOW_SCISSOR_BR (209c) GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 00055aac: 0000: 0001209c 003f003f 00000000 t0 write RB_FRAME_BUFFER_DIMENSION (0ce0) RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } 00055ab8: 0000: 00000ce0 00400040 t0 write 0xce1 (0ce1) 0xce1: 00000000 00055ac0: 0000: 00000ce1 00000000 t0 write RB_RENDER_CONTROL2 (20a3) RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 | IJ_PERSP_PIXEL } 00055ac8: 0000: 000020a3 00001000 t0 write RB_MODE_CONTROL (20a0) RB_MODE_CONTROL: { WIDTH = 0 | HEIGHT = 0 | 0xc00000 } 00055ad0: 0000: 000020a0 00c00000 t3 opcode: CP_LOAD_STATE4 (30) (11 dwords) { DST_OFF = 8 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } 00055ae4: 0.000000 0.000000 0.000000 0.000000 64.000000 64.000000 64.000000 64.000000 00055ae4: 0000: 00000000 00000000 00000000 00000000 42800000 42800000 42800000 42800000 00055ad8: 0000: c0093000 00a00008 00000001 00000000 00000000 00000000 00000000 42800000 00055af8: 0020: 42800000 42800000 42800000 t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x80000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 2 } draw[9] register values + 00000004 UNKNOWN_0CC5: 0x4 + 00000000 UNKNOWN_0CC6: 0 + 00400040 RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } + 00000000 0xce1: 00000000 + 00000002 HLSQ_MODE_CONTROL: 0x2 + 00000000 UNKNOWN_0E42: 0 + 00000004 SP_MODE_CONTROL: 0x4 + 00000068 TPL1_TP_MODE_CONTROL: 0x68 + 00188000 GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } + 00000000 UNKNOWN_2001: 0 + 00000001 GRAS_CNTL: { IJ_PERSP } !+ 00000000 GRAS_ALPHA_CONTROL: { 0 } + 00000000 GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } !+ 00000000 GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 0 | RASTER_MODE = 0 } + 00000000 GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } + 003f003f GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } + 003f003f GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } + 00000000 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } !+ 00c00000 RB_MODE_CONTROL: { WIDTH = 0 | HEIGHT = 0 | 0xc00000 } !+ 00000000 RB_RENDER_CONTROL: { 0 } !+ 00000000 RB_MSAA_CONTROL: { SAMPLES = 0 } !+ 00001000 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 | IJ_PERSP_PIXEL } !+ 0f000000 RB_MRT[0].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0xf } !+ 000400da RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB4_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE4_3 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 256 } !+ 00166000 RB_MRT[0].BASE: 0x166000 !+ 00000000 RB_MRT[0].CONTROL3: { STRIDE = 0 } + 00000000 RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } + 0f000000 RB_MRT[0x1].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0xf } + 00000e00 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } !+ ffff0000 RB_FS_OUTPUT: { ENABLE_BLEND = 0 | SAMPLE_MASK = 0xffff } + 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } + 00000001 RB_FS_OUTPUT_REG: { MRT = 1 } + 00000000 RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } + 00000000 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } !+ 42001008 VPC_ATTR: { TOTALATTR = 8 | THRDASSIGN = 1 | ENABLE | 0x40000000 } !+ 00060800 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 8 | NUMNONPOSVSVAR = 6 } !+ 0000e000 VPC_VARYING_INTERP[0].MODE: 0xe000 !+ 99999999 VPC_VARYING_PS_REPL[0].MODE: 0x99999999 + 00000000 UNKNOWN_2152: 0 + 00000000 UNKNOWN_2153: 0 + 00000000 UNKNOWN_2154: 0 + 00000000 UNKNOWN_2155: 0 + 00000000 UNKNOWN_2156: 0 + 0000001d UNKNOWN_21C3: 0x1d + 00000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 } + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + 00000000 PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } + 00000001 UNKNOWN_21E6: 0x1 + 000a0000 VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } + fc030000 VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } + fcfcfcfc VFD_CONTROL_2: 0xfcfcfcfc + fcfcfc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } + 0000fcfc VFD_CONTROL_4: 0xfcfc + 00000000 VFD_INDEX_OFFSET: 0 + 00000000 UNKNOWN_2209: 0 + 00060010 SP_SP_CTRL_REG: { 0x60010 } + 000005c3 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } + 00200c10 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } + 01000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } !+ 0020fc03 SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 2 } !+ 06071e03 SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r1.w | B_COMPMASK = 0x3 } + 00000000 SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00fcfc00 UNKNOWN_22D7: 0xfcfc00 !+ 00000c08 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 12 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } + 00000001 SP_VS_OBJ_START: 0x1 + 00000002 SP_VS_LENGTH_REG: 2 !+ 00700402 SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 0 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE | PIXLODENABLE } !+ 8010003e SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 } !+ 40420000 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 } !+ 00000001 SP_FS_OBJ_START: 0x1 + 00000001 SP_FS_LENGTH_REG: 1 !+ 00000001 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r0.x | SAMPLEMASK_REGID = r0.x } !+ 0001a000 SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = RB4_R8G8B8A8_UNORM } + 00000000 TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } !+ 00000000 0x2382: 00000000 + 00000003 TPL1_TP_FS_TEX_COUNT: 0x3 + 080004f0 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } + fcfc0120 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } + 27f3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } + fcfcfc00 HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } !+ 00fcfcfc HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } + 02010042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } !+ 0141423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 1 } + 00404200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00004200 HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } + 00000007 HLSQ_UPDATE_CONTROL: 0x7 00055b04: 0000: c0023800 00080888 00000001 00000002 t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = CACHE_FLUSH } event CACHE_FLUSH 00055b14: 0000: c0004600 00000006 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00055b1c: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0x8000012 00055b24: 0000: 00000cc6 08000012 00173000: 0000: c0013f00 000555d8 00000155 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 0017300c: 0000: c0014300 00040000 00000000 t3 opcode: (null) (1d) (2 dwords) 00173018: 0000: c0001d00 00000000 ############################################################ vertices: 0 ############################################################ cmdstream: 48 dwords t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 0016b000: 0000: c0002600 00000000 t0 write UCHE_INVALIDATE0 (0e8a) UCHE_INVALIDATE0: 0 UCHE_INVALIDATE1: 0x12 0016b008: 0000: 00010e8a 00000000 00000012 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 0016b014: 0000: c0002600 00000000 t0 write RB_MODE_CONTROL (20a0) RB_MODE_CONTROL: { WIDTH = 64 | HEIGHT = 64 | ENABLE_GMEM } 0016b01c: 0000: 000020a0 00010202 t0 write RB_FRAME_BUFFER_DIMENSION (0ce0) RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } 0016b024: 0000: 00000ce0 00400040 t0 write 0xce1 (0ce1) 0xce1: 00000001 0016b02c: 0000: 00000ce1 00000001 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 0016b034: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0 0016b03c: 0000: 00000cc6 00000000 t3 opcode: (null) (1d) (2 dwords) 0016b044: 0000: c0001d00 00000000 t0 write GRAS_SC_WINDOW_SCISSOR_BR (209c) GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 0016b04c: 0000: 0001209c 003f003f 00000000 t0 write RB_BIN_OFFSET (210d) RB_BIN_OFFSET: { X = 0 | Y = 0 } 0016b058: 0000: 0000210d 00000000 t0 write GRAS_SC_WINDOW_SCISSOR_BR (209c) GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 0016b060: 0000: 0001209c 003f003f 00000000 t0 write UNKNOWN_2157 (2157) UNKNOWN_2157: 0x1 0016b06c: 0000: 00002157 00000001 t3 opcode: (null) (64) (2 dwords) 0016b074: 0000: c0006400 00000001 t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:00054994 ibsize:000000f6 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00054994: 0000: c0002600 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x4 0005499c: 0000: 00000ec3 00000004 t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x68 000549a4: 0000: 00000f03 00000068 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 000549ac: 0000: c0002600 00000000 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } 000549b4: 0000: 000023c0 080004f0 t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = 0x1d } event (null) 000549bc: 0000: c0004600 0000001d t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = FACENESS_FLUSH } event FACENESS_FLUSH 000549c4: 0000: c0004600 0000001c t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 000549cc: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0 000549d4: 0000: 00000cc6 00000000 t0 write UNKNOWN_0E42 (0e42) UNKNOWN_0E42: 0 000549dc: 0000: 00000e42 00000000 t0 write HLSQ_MODE_CONTROL (0e05) HLSQ_MODE_CONTROL: 0x2 000549e4: 0000: 00000e05 00000002 t0 write UNKNOWN_0CC5 (0cc5) UNKNOWN_0CC5: 0x4 000549ec: 0000: 00000cc5 00000004 t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x7 000549f4: 0000: 000023db 00000007 t0 write VFD_CONTROL_2 (2202) VFD_CONTROL_2: 0xfcfcfcfc 000549fc: 0000: 00002202 fcfcfcfc t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } 00054a04: 0000: 00002203 fcfcfc00 t0 write VFD_CONTROL_4 (2204) VFD_CONTROL_4: 0xfcfc 00054a0c: 0000: 00002204 0000fcfc t0 write VFD_INDEX_OFFSET (2208) VFD_INDEX_OFFSET: 0 00054a14: 0000: 00002208 00000000 t0 write UNKNOWN_2209 (2209) UNKNOWN_2209: 0 00054a1c: 0000: 00002209 00000000 t0 write UNKNOWN_2152 (2152) UNKNOWN_2152: 0 UNKNOWN_2153: 0 00054a24: 0000: 00012152 00000000 00000000 t0 write UNKNOWN_2156 (2156) UNKNOWN_2156: 0 00054a30: 0000: 00002156 00000000 t0 write UNKNOWN_2154 (2154) UNKNOWN_2154: 0 00054a38: 0000: 00002154 00000000 t0 write UNKNOWN_2155 (2155) UNKNOWN_2155: 0 00054a40: 0000: 00002155 00000000 t0 write UNKNOWN_21C3 (21c3) UNKNOWN_21C3: 0x1d 00054a48: 0000: 000021c3 0000001d t0 write PC_PRIM_VTX_CNTL2 (21c5) PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 00054a50: 0000: 000021c5 00000012 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 00054a58: 0000: 000021e5 00000000 t0 write GRAS_SU_MODE_CONTROL (2078) GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } 00054a60: 0000: 00002078 00000000 t0 write UNKNOWN_2001 (2001) UNKNOWN_2001: 0 00054a68: 0000: 00002001 00000000 t0 write GRAS_CNTL (2003) GRAS_CNTL: { IJ_PERSP } 00054a70: 0000: 00002003 00000001 t0 write GRAS_CL_CLIP_CNTL (2000) GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } 00054a78: 0000: 00002000 00188000 t0 write TPL1_TP_TEX_COUNT (2381) TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } 00054a80: 0000: 00002381 00000000 t0 write TPL1_TP_FS_TEX_COUNT (23a0) TPL1_TP_FS_TEX_COUNT: 0x3 00054a88: 0000: 000023a0 00000003 t0 write RB_ALPHA_CONTROL (20f8) RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } 00054a90: 0000: 000020f8 00000e00 t0 write RB_RENDER_COMPONENTS (20fb) RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } 00054a98: 0000: 000020fb 0000000f t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 00054aa0: 0000: c0014300 00040000 00000000 t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } 00054aac: 0000: 00002200 000a0000 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } 00054ab4: 0000: 00002201 fc030000 t0 write SP_INSTR_CACHE_CTRL (22c1) SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } 00054abc: 0000: 000022c1 000005c3 t0 write HLSQ_CONTROL_1_REG (23c1) HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } 00054ac4: 0000: 000023c1 fcfc0120 t0 write HLSQ_CONTROL_2_REG (23c2) HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 00054acc: 0000: 000023c2 27f3f3f0 t0 write HLSQ_VS_CONTROL_REG (23c5) HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } 00054ad4: 0000: 000023c5 02010042 t0 write HLSQ_FS_CONTROL_REG (23c6) HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00054adc: 0000: 000023c6 0041423e t0 write HLSQ_HS_CONTROL_REG (23c7) HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00054ae4: 0000: 000023c7 00404200 t0 write HLSQ_DS_CONTROL_REG (23c8) HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00054aec: 0000: 000023c8 00404200 t0 write HLSQ_GS_CONTROL_REG (23c9) HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00054af4: 0000: 000023c9 00404200 t0 write HLSQ_CS_CONTROL_REG (23ca) HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } 00054afc: 0000: 000023ca 00004200 t0 write SP_SP_CTRL_REG (22c0) SP_SP_CTRL_REG: { 0x60010 } 00054b04: 0000: 000022c0 00060010 t0 write UNKNOWN_21E6 (21e6) UNKNOWN_21E6: 0x1 00054b0c: 0000: 000021e6 00000001 t0 write SP_VS_CTRL_REG0 (22c4) SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 00054b14: 0000: 000022c4 00200c10 t0 write SP_VS_CTRL_REG1 (22c5) SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } 00054b1c: 0000: 000022c5 01000042 t0 write VPC_ATTR (2140) VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | 0x40000000 } 00054b24: 0000: 00002140 40001004 t0 write VPC_PACK (2141) VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } 00054b2c: 0000: 00002141 00040400 t0 write PC_PRIM_VTX_CNTL (21c4) PC_PRIM_VTX_CNTL: { VAROUT = 1 } 00054b34: 0000: 000021c4 00000001 t0 write SP_VS_PARAM_REG (22c6) SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } UNKNOWN_22D7: 0xfcfc00 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 00054b3c: 0000: 001922c6 0010fc03 00001e03 00000000 00000000 00000000 00000000 00000000 * 00054b7c: 0040: 00000000 00000000 00fcfc00 00000008 00000000 00000000 00000000 00000000 * t0 write SP_VS_OBJ_OFFSET_REG (22e0) SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 00054ba8: 0000: 000022e0 00000000 t0 write SP_VS_OBJ_START (22e1) SP_VS_OBJ_START: 0x1 00054bb0: 0000: 000022e1 00000001 t0 write SP_VS_LENGTH_REG (22e5) SP_VS_LENGTH_REG: 2 00054bb8: 0000: 000022e5 00000002 t3 opcode: CP_LOAD_STATE4 (30) (67 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } :2:0000:0000[56d81803x_20020003x] (sy)(ss)(nop3) shl.b r0.w, r0.w, 2 :1:0001:0004[20150000x_00000003x] cov.s32s16 hr0.x, r0.w :0:0002:0005[00000200x_00000000x] (rpt2)nop :1:0003:0008[201100f4x_00000000x] mova a0.x, hr0.x :0:0004:0009[00000500x_00000000x] (rpt5)nop :1:0005:0015[20154003x_00000c20x] mov.s32s32 r0.w, c :1:0006:0016[20154004x_00000c21x] mov.s32s32 r1.x, c :1:0007:0017[20154005x_00000c22x] mov.s32s32 r1.y, c :1:0008:0018[20156006x_00000c23x] (ul)mov.s32s32 r1.z, c :0:0009:0019[03000000x_00000000x] end :2:0010:0020[46f00007x_20050000x] shr.b r1.w, r0.x, 5 :2:0011:0021[43980008x_201f0000x] (nop2) and.b r2.x, r0.x, 31 :2:0012:0024[43980807x_201f0007x] (nop3) and.b r1.w, r1.w, 31 :2:0013:0028[46100807x_20100007x] (nop1) mul.u24 r1.w, r1.w, 16 :3:0014:0030[62040007x_00071014x] mad.u24 r1.w, c5.x, r2.x, r1.w :0:0015:0031[00000500x_00000000x] (rpt5)nop :6:0016:0037[c2c60f00x_04800006x] stlw.u32 l[r1.w], r0.w, 4 :0:0017:0038[04800000x_00000000x] chmask :0:0018:0039[05000000x_00000000x] chsh Stats: - shaderdb: 40 instr, 24 nops, 16 non-nops, 5 mov, 1 cov - shaderdb: 0 last-baryf, 0 half, 2 full, 5 constlen - shaderdb: 27 cat0, 6 cat1, 5 cat2, 1 cat3, 0 cat4, 0 cat5, 1 cat6, 0 cat7 - shaderdb: 0 sstall, 1 (ss), 1 (sy) 00054bc0: 0000: c0413000 00a00000 00000000 20020003 56d81803 00000003 20150000 00000000 00054be0: 0020: 00000200 00000000 201100f4 00000000 00000500 00000c20 20154003 00000c21 00054c00: 0040: 20154004 00000c22 20154005 00000c23 20156006 00000000 03000000 20050000 00054c20: 0060: 46f00007 201f0000 43980008 201f0007 43980807 20100007 46100807 00071014 00054c40: 0080: 62040007 00000000 00000500 04800006 c2c60f00 00000000 04800000 00000000 00054c60: 00a0: 05000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 * t0 write GRAS_ALPHA_CONTROL (2073) GRAS_ALPHA_CONTROL: { 0x2 } 00054ccc: 0000: 00002073 00000002 t0 write GRAS_SC_CONTROL (207b) GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = 4 | MSAA_DISABLE | RASTER_MODE = 0 } 00054cd4: 0000: 0000207b 00000a08 t0 write RB_MSAA_CONTROL (20a2) RB_MSAA_CONTROL: { DISABLE | SAMPLES = 4 } 00054cdc: 0000: 000020a2 00009000 t0 write RB_RENDER_CONTROL (20a1) RB_RENDER_CONTROL: { DISABLE_COLOR_PIPE | 0x2 } 00054ce4: 0000: 000020a1 00000022 t0 write RB_CLEAR_COLOR_DW0 (20cc) RB_CLEAR_COLOR_DW0: 0xff000000 RB_CLEAR_COLOR_DW1: 0 RB_CLEAR_COLOR_DW2: 0 RB_CLEAR_COLOR_DW3: 0 00054cec: 0000: 000320cc ff000000 00000000 00000000 00000000 t0 write RB_COPY_CONTROL (20fc) RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_FOUR | MODE = RB_COPY_CLEAR | FASTCLEAR = 0xf | GMEM_BASE = 0 } RB_COPY_DEST_BASE: { BASE = 0x4f000 } RB_COPY_DEST_PITCH: { PITCH = 256 } RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_IF_ALPHA_OFF | COMPONENT_ENABLE = 0 | ENDIAN = ENDIAN_NONE | TILE = TILE4_3 } 00054d00: 0000: 000320fc 00000f22 0004f000 00000008 03000868 t0 write GRAS_SC_SCREEN_SCISSOR_TL (207c) GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } 00054d14: 0000: 0001207c 00000000 003f003f t0 write RB_FRAME_BUFFER_DIMENSION (0ce0) RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } 00054d20: 0000: 00000ce0 00400040 t0 write 0xce1 (0ce1) 0xce1: 00000000 00054d28: 0000: 00000ce1 00000000 t3 opcode: CP_LOAD_STATE4 (30) (11 dwords) { DST_OFF = 8 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } 00054d3c: 0.000000 0.000000 1.000000 1.000000 64.000000 64.000000 1.000000 1.000000 00054d3c: 0000: 00000000 00000000 3f800000 3f800000 42800000 42800000 3f800000 3f800000 00054d30: 0000: c0093000 00a00008 00000001 00000000 00000000 3f800000 3f800000 42800000 00054d50: 0020: 42800000 3f800000 3f800000 t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x80000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 2 } draw[10] register values + 00000004 UNKNOWN_0CC5: 0x4 + 00000000 UNKNOWN_0CC6: 0 + 00400040 RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } + 00000000 0xce1: 00000000 + 00000002 HLSQ_MODE_CONTROL: 0x2 + 00000000 UNKNOWN_0E42: 0 + 00000000 UCHE_INVALIDATE0: 0 + 00000012 UCHE_INVALIDATE1: 0x12 + 00000004 SP_MODE_CONTROL: 0x4 + 00000068 TPL1_TP_MODE_CONTROL: 0x68 + 00188000 GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } + 00000000 UNKNOWN_2001: 0 + 00000001 GRAS_CNTL: { IJ_PERSP } !+ 00000002 GRAS_ALPHA_CONTROL: { 0x2 } + 00000000 GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } !+ 00000a08 GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = 4 | MSAA_DISABLE | RASTER_MODE = 0 } + 00000000 GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } + 003f003f GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } + 003f003f GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } + 00000000 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } !+ 00010202 RB_MODE_CONTROL: { WIDTH = 64 | HEIGHT = 64 | ENABLE_GMEM } !+ 00000022 RB_RENDER_CONTROL: { DISABLE_COLOR_PIPE | 0x2 } !+ 00009000 RB_MSAA_CONTROL: { DISABLE | SAMPLES = 4 } + ff000000 RB_CLEAR_COLOR_DW0: 0xff000000 + 00000000 RB_CLEAR_COLOR_DW1: 0 + 00000000 RB_CLEAR_COLOR_DW2: 0 + 00000000 RB_CLEAR_COLOR_DW3: 0 + 00000e00 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } + 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } !+ 00000f22 RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_FOUR | MODE = RB_COPY_CLEAR | FASTCLEAR = 0xf | GMEM_BASE = 0 } + 0004f000 RB_COPY_DEST_BASE: { BASE = 0x4f000 } + 00000008 RB_COPY_DEST_PITCH: { PITCH = 256 } !+ 03000868 RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_IF_ALPHA_OFF | COMPONENT_ENABLE = 0 | ENDIAN = ENDIAN_NONE | TILE = TILE4_3 } + 00000000 RB_BIN_OFFSET: { X = 0 | Y = 0 } !+ 40001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | 0x40000000 } !+ 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } + 00000000 UNKNOWN_2152: 0 + 00000000 UNKNOWN_2153: 0 + 00000000 UNKNOWN_2154: 0 + 00000000 UNKNOWN_2155: 0 + 00000000 UNKNOWN_2156: 0 + 00000001 UNKNOWN_2157: 0x1 + 0000001d UNKNOWN_21C3: 0x1d + 00000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 } + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + 00000000 PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } + 00000001 UNKNOWN_21E6: 0x1 + 000a0000 VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } + fc030000 VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } + fcfcfcfc VFD_CONTROL_2: 0xfcfcfcfc + fcfcfc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } + 0000fcfc VFD_CONTROL_4: 0xfcfc + 00000000 VFD_INDEX_OFFSET: 0 + 00000000 UNKNOWN_2209: 0 + 00060010 SP_SP_CTRL_REG: { 0x60010 } + 000005c3 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } + 00200c10 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } + 01000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } !+ 0010fc03 SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } !+ 00001e03 SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00fcfc00 UNKNOWN_22D7: 0xfcfc00 !+ 00000008 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } + 00000001 SP_VS_OBJ_START: 0x1 + 00000002 SP_VS_LENGTH_REG: 2 + 00000000 TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } + 00000003 TPL1_TP_FS_TEX_COUNT: 0x3 + 080004f0 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } + fcfc0120 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } + 27f3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } + 02010042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } !+ 0041423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00004200 HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } + 00000007 HLSQ_UPDATE_CONTROL: 0x7 00054d5c: 0000: c0023800 00080888 00000001 00000002 0016b07c: 0000: c0013f00 00054994 000000f6 t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:00054d6c ibsize:00000037 t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } 00054d6c: 0000: 00002200 082a0008 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00054d74: 0000: c0002600 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x1e 00054d7c: 0000: 00000ec3 0000001e t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x28 00054d84: 0000: 00000f03 00000028 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00054d8c: 0000: c0002600 00000000 t0 write HLSQ_MODE_CONTROL (0e05) HLSQ_MODE_CONTROL: 0x1 00054d94: 0000: 00000e05 00000001 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0x600a0 } 00054d9c: 0000: 000023c0 080604f0 t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x7 00054da4: 0000: 000023db 00000007 t0 write PC_RESTART_INDEX (21c6) PC_RESTART_INDEX: 0xffffffff 00054dac: 0000: 000021c6 ffffffff t0 write UNKNOWN_21E6 (21e6) UNKNOWN_21E6: 0x1 00054db4: 0000: 000021e6 00000001 t0 write UNKNOWN_21C3 (21c3) UNKNOWN_21C3: 0x1f 00054dbc: 0000: 000021c3 0000001f t0 write TPL1_TP_TEX_OFFSET (2380) TPL1_TP_TEX_OFFSET: 0x808 00054dc4: 0000: 00002380 00000808 t0 write GRAS_SU_POINT_MINMAX (2070) GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 4092.000000 } GRAS_SU_POINT_SIZE: 0.500000 00054dcc: 0000: 00012070 ffc00010 00000008 t0 write UNKNOWN_2152 (2152) UNKNOWN_2152: 0 UNKNOWN_2153: 0 00054dd8: 0000: 00012152 00000000 00000000 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00054de4: 0000: c0002600 00000000 t0 write UNKNOWN_0CC5 (0cc5) UNKNOWN_0CC5: 0x4 00054dec: 0000: 00000cc5 00000004 t0 write 0xcc4 (0cc4) 0xcc4: 00000000 00054df4: 0000: 00000cc4 00000000 t0 write 0xd03 (0d03) 0xd03: 80200000 00054dfc: 0000: 00000d03 80200000 t0 write UNKNOWN_0EC2 (0ec2) UNKNOWN_0EC2: 0x40000 00054e04: 0000: 00000ec2 00040000 t0 write VPC_DEBUG_ECO_CONTROL (0e64) VPC_DEBUG_ECO_CONTROL: 0x100 00054e0c: 0000: 00000e64 00000100 t0 write UNKNOWN_0E42 (0e42) UNKNOWN_0E42: 0 00054e14: 0000: 00000e42 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x1e 00054e1c: 0000: 00000ec3 0000001e t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x28 00054e24: 0000: 00000f03 00000028 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 00054e2c: 0000: c0014300 00040000 00000000 t0 write VFD_INDEX_OFFSET (2208) VFD_INDEX_OFFSET: 0 00054e38: 0000: 00002208 00000000 t0 write UNKNOWN_2209 (2209) UNKNOWN_2209: 0 00054e40: 0000: 00002209 00000000 0016b088: 0000: c0013f00 00054d6c 00000037 t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:00055328 ibsize:000000ac t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x3 00055328: 0000: 000023db 00000003 t0 write SP_INSTR_CACHE_CTRL (22c1) SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } 00055330: 0000: 000022c1 000005c3 t0 write HLSQ_CONTROL_1_REG (23c1) HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x1008 } 00055338: 0000: 000023c1 fcfc1108 t0 write HLSQ_CONTROL_2_REG (23c2) HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 00055340: 0000: 000023c2 fff3f3f0 t0 write HLSQ_VS_CONTROL_REG (23c5) HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 2 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 1 } 00055348: 0000: 000023c5 01010002 t0 write HLSQ_HS_CONTROL_REG (23c7) HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 00055350: 0000: 000023c7 007e0200 t0 write HLSQ_DS_CONTROL_REG (23c8) HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 00055358: 0000: 000023c8 007e0200 t0 write HLSQ_GS_CONTROL_REG (23c9) HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 00055360: 0000: 000023c9 007e0200 t0 write HLSQ_FS_CONTROL_REG (23c6) HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 2 | CONSTOBJECTOFFSET = 2 | ENABLED | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 } 00055368: 0000: 000023c6 017f0202 t0 write SP_VS_OBJ_OFFSET_REG (22e0) SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 00055370: 0000: 000022e0 00000000 t0 write SP_HS_OBJ_OFFSET_REG (230d) SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } 00055378: 0000: 0000230d 7e020000 t0 write SP_DS_OBJ_OFFSET_REG (2334) SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } 00055380: 0000: 00002334 7e020000 t0 write SP_GS_OBJ_OFFSET_REG (235b) SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } 00055388: 0000: 0000235b 7e020000 t0 write SP_FS_OBJ_OFFSET_REG (22ea) SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } 00055390: 0000: 000022ea 7e020000 t0 write SP_VS_OBJ_START (22e1) SP_VS_OBJ_START: 0x49000 00049000: 0000: 00000000 13000000 00000000 00000000 00000000 00000000 00000000 00000000 * :0:0000:0000[13000000x_00000000x] (sy)end :0:0001:0001[00000000x_00000000x] nop :0:0002:0002[00000000x_00000000x] nop :0:0003:0003[00000000x_00000000x] nop :0:0004:0004[00000000x_00000000x] nop Stats: - shaderdb: 5 instr, 4 nops, 1 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 0 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 0 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) 00055398: 0000: 000022e1 00049000 t0 write SP_HS_OBJ_START (230e) SP_HS_OBJ_START: 0 000553a0: 0000: 0000230e 00000000 t0 write SP_DS_OBJ_START (2335) SP_DS_OBJ_START: 0 000553a8: 0000: 00002335 00000000 t0 write SP_GS_OBJ_START (235c) SP_GS_OBJ_START: 0 000553b0: 0000: 0000235c 00000000 t0 write SP_VS_LENGTH_REG (22e5) SP_VS_LENGTH_REG: 1 000553b8: 0000: 000022e5 00000001 t3 opcode: CP_LOAD_STATE4 (30) (3 dwords) { DST_OFF = 0 | STATE_SRC = SS4_INDIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 1 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0x49000 } :0:0000:0000[13000000x_00000000x] (sy)end :0:0001:0001[00000000x_00000000x] nop :0:0002:0002[00000000x_00000000x] nop :0:0003:0003[00000000x_00000000x] nop :0:0004:0004[00000000x_00000000x] nop Stats: - shaderdb: 5 instr, 4 nops, 1 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 0 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 0 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) 000553c0: 0000: c0013000 00620000 00049000 t0 write 0x2072 (2072) 0x2072: 00000000 000553cc: 0000: 00002072 00000000 t0 write UNKNOWN_2155 (2155) UNKNOWN_2155: 0 000553d4: 0000: 00002155 00000000 t0 write GRAS_CNTL (2003) GRAS_CNTL: { IJ_PERSP } 000553dc: 0000: 00002003 00000001 t0 write VPC_VARYING_INTERP[0].MODE (2142) VPC_VARYING_INTERP[0].MODE: 0 000553e4: 0000: 00002142 00000000 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0x600a0 } 000553ec: 0000: 000023c0 080604f0 t0 write HLSQ_CONTROL_3_REG (23c3) HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } 000553f4: 0000: 000023c3 fcfcfc00 t0 write HLSQ_CONTROL_4_REG (23c4) HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r0.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } 000553fc: 0000: 000023c4 00fcfc00 t0 write SP_FS_CTRL_REG0 (22e8) SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE } SP_FS_CTRL_REG1: { CONSTLENGTH = 2 | VARYING | 0x80000000 } 00055404: 0000: 000122e8 00340412 80100002 t0 write SP_FS_OBJ_START (22eb) SP_FS_OBJ_START: 0x46000 00046000: 0000: 00002000 5730cb00 00000000 03000000 00000000 00000000 00000000 00000000 * :2:0000:0000[5730cb00x_00002000x] (sy)(rpt3)bary.f (ei)hr0.x, (r)0, r0.x :0:0001:0004[03000000x_00000000x] end :0:0002:0005[00000000x_00000000x] nop :0:0003:0006[00000000x_00000000x] nop :0:0004:0007[00000000x_00000000x] nop :0:0005:0008[00000000x_00000000x] nop Stats: - shaderdb: 9 instr, 4 nops, 5 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 1 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 4 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) 00055410: 0000: 000022eb 00046000 t0 write SP_FS_LENGTH_REG (22ef) SP_FS_LENGTH_REG: 1 00055418: 0000: 000022ef 00000001 t0 write RB_RENDER_COMPONENTS (20fb) RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } 00055420: 0000: 000020fb 0000000f t3 opcode: CP_LOAD_STATE4 (30) (3 dwords) { DST_OFF = 0 | STATE_SRC = SS4_INDIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 1 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0x46000 } :2:0000:0000[5730cb00x_00002000x] (sy)(rpt3)bary.f (ei)hr0.x, (r)0, r0.x :0:0001:0004[03000000x_00000000x] end :0:0002:0005[00000000x_00000000x] nop :0:0003:0006[00000000x_00000000x] nop :0:0004:0007[00000000x_00000000x] nop :0:0005:0008[00000000x_00000000x] nop Stats: - shaderdb: 9 instr, 4 nops, 5 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 1 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 4 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) 00055428: 0000: c0013000 00720000 00046000 t0 write SP_SP_CTRL_REG (22c0) SP_SP_CTRL_REG: { 0x60010 } 00055434: 0000: 000022c0 00060010 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 28 | GROUP_ID = 3 } { ADDR_LO = 0x99780 } 0005543c: 0000: c0014300 0300001c 00099780 t0 write RB_DEPTH_INFO (2103) RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTH4_NONE | DEPTH_BASE = 0 } RB_DEPTH_PITCH: 0 RB_DEPTH_PITCH2: 0 00055448: 0000: 00022103 00000000 00000000 00000000 t0 write GRAS_DEPTH_CONTROL (2077) GRAS_DEPTH_CONTROL: { FORMAT = DEPTH4_NONE } 00055458: 0000: 00002077 00000000 t0 write RB_STENCIL_INFO (2108) RB_STENCIL_INFO: { STENCIL_BASE = 0 } RB_STENCIL_PITCH: 0 0x210a: 00000000 00055460: 0000: 00022108 00000000 00000000 00000000 t0 write 0x2002 (2002) 0x2002: 00000000 00055470: 0000: 00002002 00000000 t0 write RB_ALPHA_CONTROL (20f8) RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } 00055478: 0000: 000020f8 00000e00 t0 write RB_MRT[0].CONTROL (20a4) RB_MRT[0].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0x7 } 00055480: 0000: 000020a4 07000c00 t0 write RB_MRT[0].BLEND_CONTROL (20a8) RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } 00055488: 0000: 000020a8 00000000 t0 write GRAS_CL_CLIP_CNTL (2000) GRAS_CL_CLIP_CNTL: { 0x80000 } 00055490: 0000: 00002000 00080000 t0 write GRAS_SU_POLY_OFFSET_SCALE (2074) GRAS_SU_POLY_OFFSET_SCALE: 0.000000 GRAS_SU_POLY_OFFSET_OFFSET: 0.000000 GRAS_SU_POLY_OFFSET_CLAMP: 0.000000 00055498: 0000: 00022074 00000000 00000000 00000000 t0 write GRAS_SU_MODE_CONTROL (2078) GRAS_SU_MODE_CONTROL: { FRONT_CW | LINEHALFWIDTH = 0.500000 | MSAA_ENABLE | RENDERING_PASS } 000554a8: 0000: 00002078 00102014 t0 write GRAS_SC_SCREEN_SCISSOR_TL (207c) GRAS_SC_SCREEN_SCISSOR_TL: { X = 2 | Y = 13 } GRAS_SC_SCREEN_SCISSOR_BR: { X = 33 | Y = 44 } 000554b0: 0000: 0001207c 000d0002 002c0021 t0 write GRAS_CL_VPORT_XOFFSET_0 (2008) GRAS_CL_VPORT_XOFFSET_0: 18.000000 GRAS_CL_VPORT_XSCALE_0: 16.000000 GRAS_CL_VPORT_YOFFSET_0: 29.000000 GRAS_CL_VPORT_YSCALE_0: 16.000000 GRAS_CL_VPORT_ZOFFSET_0: 0.500000 GRAS_CL_VPORT_ZSCALE_0: 0.500000 000554bc: 0000: 00052008 41900000 41800000 41e80000 41800000 3f000000 3f000000 t0 write GRAS_CL_GB_CLIP_ADJ (2004) GRAS_CL_GB_CLIP_ADJ: { HORZ = 511 | VERT = 511 } 000554d8: 0000: 00002004 0007fdff t0 write GRAS_SC_CONTROL (207b) GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 4 | RASTER_MODE = 0 } 000554e0: 0000: 0000207b 00000200 t0 write 0x2382 (2382) 0x2382: 00000002 000554e8: 0000: 00002382 00000002 t0 write RB_MSAA_CONTROL (20a2) RB_MSAA_CONTROL: { SAMPLES = 4 } 000554f0: 0000: 000020a2 00008000 t0 write RB_RENDER_CONTROL2 (20a3) RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 4 | IJ_PERSP_PIXEL } 000554f8: 0000: 000020a3 00001200 t0 write RB_MRT[0].BUF_INFO (20a5) RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB4_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_ALWAYS | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 1024 } RB_MRT[0].BASE: 0 RB_MRT[0].CONTROL3: { STRIDE = 64 } 00055500: 0000: 000220a5 0010029a 00000000 00000200 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 43 | GROUP_ID = 2 } { ADDR_LO = 0x997f0 } 00055510: 0000: c0014300 0200002b 000997f0 t0 write 0x215c (215c) 0x215c: 00000000 0x215d: 00000000 0005551c: 0000: 0001215c 00000000 00000000 t0 write 0x215f (215f) 0x215f: 00000000 00055528: 0000: 0000215f 00000000 t0 write 0x215e (215e) 0x215e: 00000000 00055530: 0000: 0000215e 00000000 t0 write 0x2161 (2161) 0x2161: 00000000 0x2162: 00000000 00055538: 0000: 00012161 00000000 00000000 t0 write 0x2164 (2164) 0x2164: 00000000 00055544: 0000: 00002164 00000000 t0 write 0x2163 (2163) 0x2163: 00000000 0005554c: 0000: 00002163 00000000 t0 write 0x2166 (2166) 0x2166: 00000000 0x2167: 00000000 00055554: 0000: 00012166 00000000 00000000 t0 write 0x2169 (2169) 0x2169: 00000000 00055560: 0000: 00002169 00000000 t0 write 0x2168 (2168) 0x2168: 00000000 00055568: 0000: 00002168 00000000 t0 write 0x216b (216b) 0x216b: 00000000 0x216c: 00000000 00055570: 0000: 0001216b 00000000 00000000 t0 write VPC_SO_FLUSH_WADDR_3 (216e) VPC_SO_FLUSH_WADDR_3: 0 0005557c: 0000: 0000216e 00000000 t0 write 0x216d (216d) 0x216d: 00000000 00055584: 0000: 0000216d 00000000 t0 write UNKNOWN_2156 (2156) UNKNOWN_2156: 0 0005558c: 0000: 00002156 00000000 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 18 | GROUP_ID = 1 } { ADDR_LO = 0x998a0 } 00055594: 0000: c0014300 01000012 000998a0 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 15 | GROUP_ID = 0 } { ADDR_LO = 0x998f0 } 000555a0: 0000: c0014300 0000000f 000998f0 group_id: 0 count: 15 addr: 00000000000998f0 flags: 0 000998f0: 0000: 00002073 00000000 00002101 00000000 00002106 00000000 000021e5 00000000 00099910: 0020: 0001210b 00000000 00000000 00002381 00000000 000023a0 00000000 t0 write GRAS_ALPHA_CONTROL (2073) GRAS_ALPHA_CONTROL: { 0 } 000998f0: 0000: 00002073 00000000 t0 write RB_DEPTH_CONTROL (2101) RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } 000998f8: 0000: 00002101 00000000 t0 write RB_STENCIL_CONTROL (2106) RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } 00099900: 0000: 00002106 00000000 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 00099908: 0000: 000021e5 00000000 t0 write RB_STENCILREFMASK (210b) RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 00099910: 0000: 0001210b 00000000 00000000 t0 write TPL1_TP_TEX_COUNT (2381) TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } 0009991c: 0000: 00002381 00000000 t0 write TPL1_TP_FS_TEX_COUNT (23a0) TPL1_TP_FS_TEX_COUNT: 0 00099924: 0000: 000023a0 00000000 group_id: 1 count: 18 addr: 00000000000998a0 flags: 0 000998a0: 0000: 00002200 082a0008 00002201 fcfc0081 00002203 0000fc00 0007220a 0008080f 000998c0: 0020: 00099720 00000060 00000001 0000080f 00099750 00000030 00000001 0001228a 000998e0: 0040: 7000411f 3000011f t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } 000998a0: 0000: 00002200 082a0008 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } 000998a8: 0000: 00002201 fcfc0081 t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } 000998b0: 0000: 00002203 0000fc00 t0 write VFD_FETCH[0].INSTR_0 (220a) VFD_FETCH[0].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 | SWITCHNEXT } VFD_FETCH[0].INSTR_1: 0x99720 VFD_FETCH[0].INSTR_2: { SIZE = 0x60 } VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 } VFD_FETCH[0x1].INSTR_1: 0x99750 VFD_FETCH[0x1].INSTR_2: { SIZE = 0x30 } VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } 000998b8: 0000: 0007220a 0008080f 00099720 00000060 00000001 0000080f 00099750 00000030 000998d8: 0020: 00000001 t0 write VFD_DECODE[0].INSTR (228a) VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID | SWITCHNEXT } VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID } 000998dc: 0000: 0001228a 7000411f 3000011f group_id: 2 count: 43 addr: 00000000000997f0 flags: 0 000997f0: 0000: 000020a1 00000000 000022f1 0001a100 000022f0 fc00fc01 00002100 00000001 00099810: 0020: 000021e5 00000000 000020f9 ffff0501 0000214a 00000000 00002140 42001004 00099830: 0040: 001922c6 0010fc04 00001e00 00000000 00000000 00000000 00000000 00000000 * 00099870: 0080: 00000000 00000000 00fcfc00 00000008 00000000 00000000 00000000 00000000 * t0 write RB_RENDER_CONTROL (20a1) RB_RENDER_CONTROL: { 0 } 000997f0: 0000: 000020a1 00000000 t0 write SP_FS_MRT[0].REG (22f1) SP_FS_MRT[0].REG: { REGID = r0.x | HALF_PRECISION | MRTFORMAT = RB4_R8G8B8A8_UNORM } 000997f8: 0000: 000022f1 0001a100 t0 write SP_FS_OUTPUT_REG (22f0) SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 00099800: 0000: 000022f0 fc00fc01 t0 write RB_FS_OUTPUT_REG (2100) RB_FS_OUTPUT_REG: { MRT = 1 } 00099808: 0000: 00002100 00000001 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 00099810: 0000: 000021e5 00000000 t0 write RB_FS_OUTPUT (20f9) RB_FS_OUTPUT: { ENABLE_BLEND = 0x1 | INDEPENDENT_BLEND | SAMPLE_MASK = 0xffff | 0x400 } 00099818: 0000: 000020f9 ffff0501 t0 write VPC_VARYING_PS_REPL[0].MODE (214a) VPC_VARYING_PS_REPL[0].MODE: 0 00099820: 0000: 0000214a 00000000 t0 write VPC_ATTR (2140) VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 } 00099828: 0000: 00002140 42001004 t0 write SP_VS_PARAM_REG (22c6) SP_VS_PARAM_REG: { POSREGID = r1.x | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } SP_VS_OUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } UNKNOWN_22D7: 0xfcfc00 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 00099830: 0000: 001922c6 0010fc04 00001e00 00000000 00000000 00000000 00000000 00000000 * 00099870: 0040: 00000000 00000000 00fcfc00 00000008 00000000 00000000 00000000 00000000 * group_id: 3 count: 28 addr: 0000000000099780 flags: 0 00099780: 0000: 000021c4 02000001 00002141 00040400 00002001 00000000 000022c4 00200800 000997a0: 0020: 000022c5 08000002 0000230c 00000000 00002318 00000000 00002319 00000000 000997c0: 0040: 00002340 00000000 00002202 fcfcfcfc 00002204 0000fcfc 00002154 00000000 000997e0: 0060: 000021e7 00000000 000021c5 00000012 t0 write PC_PRIM_VTX_CNTL (21c4) PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } 00099780: 0000: 000021c4 02000001 t0 write VPC_PACK (2141) VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } 00099788: 0000: 00002141 00040400 t0 write UNKNOWN_2001 (2001) UNKNOWN_2001: 0 00099790: 0000: 00002001 00000000 t0 write SP_VS_CTRL_REG0 (22c4) SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 2 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 00099798: 0000: 000022c4 00200800 t0 write SP_VS_CTRL_REG1 (22c5) SP_VS_CTRL_REG1: { CONSTLENGTH = 2 | INITIALOUTSTANDING = 8 } 000997a0: 0000: 000022c5 08000002 t0 write 0x230c (230c) 0x230c: 00000000 000997a8: 0000: 0000230c 00000000 t0 write 0x2318 (2318) 0x2318: 00000000 000997b0: 0000: 00002318 00000000 t0 write 0x2319 (2319) 0x2319: 00000000 000997b8: 0000: 00002319 00000000 t0 write 0x2340 (2340) 0x2340: 00000000 000997c0: 0000: 00002340 00000000 t0 write VFD_CONTROL_2 (2202) VFD_CONTROL_2: 0xfcfcfcfc 000997c8: 0000: 00002202 fcfcfcfc t0 write VFD_CONTROL_4 (2204) VFD_CONTROL_4: 0xfcfc 000997d0: 0000: 00002204 0000fcfc t0 write UNKNOWN_2154 (2154) UNKNOWN_2154: 0 000997d8: 0000: 00002154 00000000 t0 write PC_HS_PARAM (21e7) PC_HS_PARAM: { VERTICES_OUT = 0 | SPACING = EQUAL_SPACING } 000997e0: 0000: 000021e7 00000000 t0 write PC_PRIM_VTX_CNTL2 (21c5) PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 000997e8: 0000: 000021c5 00000012 t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = USE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x200000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 3 } draw[11] register values + 00000000 0xcc4: 00000000 + 00000004 UNKNOWN_0CC5: 0x4 + 80200000 0xd03: 80200000 !+ 00000001 HLSQ_MODE_CONTROL: 0x1 + 00000000 UNKNOWN_0E42: 0 + 00000100 VPC_DEBUG_ECO_CONTROL: 0x100 + 00040000 UNKNOWN_0EC2: 0x40000 !+ 0000001e SP_MODE_CONTROL: 0x1e !+ 00000028 TPL1_TP_MODE_CONTROL: 0x28 !+ 00080000 GRAS_CL_CLIP_CNTL: { 0x80000 } + 00000000 UNKNOWN_2001: 0 + 00000000 0x2002: 00000000 + 00000001 GRAS_CNTL: { IJ_PERSP } + 0007fdff GRAS_CL_GB_CLIP_ADJ: { HORZ = 511 | VERT = 511 } + 41900000 GRAS_CL_VPORT_XOFFSET_0: 18.000000 + 41800000 GRAS_CL_VPORT_XSCALE_0: 16.000000 + 41e80000 GRAS_CL_VPORT_YOFFSET_0: 29.000000 + 41800000 GRAS_CL_VPORT_YSCALE_0: 16.000000 + 3f000000 GRAS_CL_VPORT_ZOFFSET_0: 0.500000 + 3f000000 GRAS_CL_VPORT_ZSCALE_0: 0.500000 + ffc00010 GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 4092.000000 } + 00000008 GRAS_SU_POINT_SIZE: 0.500000 + 00000000 0x2072: 00000000 !+ 00000000 GRAS_ALPHA_CONTROL: { 0 } + 00000000 GRAS_SU_POLY_OFFSET_SCALE: 0.000000 + 00000000 GRAS_SU_POLY_OFFSET_OFFSET: 0.000000 + 00000000 GRAS_SU_POLY_OFFSET_CLAMP: 0.000000 + 00000000 GRAS_DEPTH_CONTROL: { FORMAT = DEPTH4_NONE } !+ 00102014 GRAS_SU_MODE_CONTROL: { FRONT_CW | LINEHALFWIDTH = 0.500000 | MSAA_ENABLE | RENDERING_PASS } !+ 00000200 GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 4 | RASTER_MODE = 0 } !+ 000d0002 GRAS_SC_SCREEN_SCISSOR_TL: { X = 2 | Y = 13 } !+ 002c0021 GRAS_SC_SCREEN_SCISSOR_BR: { X = 33 | Y = 44 } !+ 00000000 RB_RENDER_CONTROL: { 0 } !+ 00008000 RB_MSAA_CONTROL: { SAMPLES = 4 } !+ 00001200 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 4 | IJ_PERSP_PIXEL } !+ 07000c00 RB_MRT[0].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0x7 } !+ 0010029a RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB4_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_ALWAYS | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 1024 } !+ 00000000 RB_MRT[0].BASE: 0 !+ 00000200 RB_MRT[0].CONTROL3: { STRIDE = 64 } + 00000000 RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } + 00000e00 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } !+ ffff0501 RB_FS_OUTPUT: { ENABLE_BLEND = 0x1 | INDEPENDENT_BLEND | SAMPLE_MASK = 0xffff | 0x400 } + 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } + 00000001 RB_FS_OUTPUT_REG: { MRT = 1 } + 00000000 RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } + 00000000 RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTH4_NONE | DEPTH_BASE = 0 } + 00000000 RB_DEPTH_PITCH: 0 + 00000000 RB_DEPTH_PITCH2: 0 + 00000000 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } + 00000000 RB_STENCIL_INFO: { STENCIL_BASE = 0 } + 00000000 RB_STENCIL_PITCH: 0 + 00000000 0x210a: 00000000 + 00000000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } + 00000000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } !+ 42001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 } + 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } !+ 00000000 VPC_VARYING_INTERP[0].MODE: 0 !+ 00000000 VPC_VARYING_PS_REPL[0].MODE: 0 + 00000000 UNKNOWN_2152: 0 + 00000000 UNKNOWN_2153: 0 + 00000000 UNKNOWN_2154: 0 + 00000000 UNKNOWN_2155: 0 + 00000000 UNKNOWN_2156: 0 + 00000000 0x215c: 00000000 + 00000000 0x215d: 00000000 + 00000000 0x215e: 00000000 + 00000000 0x215f: 00000000 + 00000000 0x2161: 00000000 + 00000000 0x2162: 00000000 + 00000000 0x2163: 00000000 + 00000000 0x2164: 00000000 + 00000000 0x2166: 00000000 + 00000000 0x2167: 00000000 + 00000000 0x2168: 00000000 + 00000000 0x2169: 00000000 + 00000000 0x216b: 00000000 + 00000000 0x216c: 00000000 + 00000000 0x216d: 00000000 + 00000000 VPC_SO_FLUSH_WADDR_3: 0 !+ 0000001f UNKNOWN_21C3: 0x1f !+ 02000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + ffffffff PC_RESTART_INDEX: 0xffffffff + 00000000 PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } + 00000001 UNKNOWN_21E6: 0x1 + 00000000 PC_HS_PARAM: { VERTICES_OUT = 0 | SPACING = EQUAL_SPACING } !+ 082a0008 VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } !+ fcfc0081 VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } + fcfcfcfc VFD_CONTROL_2: 0xfcfcfcfc !+ 0000fc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } + 0000fcfc VFD_CONTROL_4: 0xfcfc + 00000000 VFD_INDEX_OFFSET: 0 + 00000000 UNKNOWN_2209: 0 + 0008080f VFD_FETCH[0].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 | SWITCHNEXT } !+ 00099720 VFD_FETCH[0].INSTR_1: 0x99720 + 00000060 VFD_FETCH[0].INSTR_2: { SIZE = 0x60 } + 00000001 VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } + 0000080f VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 } !+ 00099750 VFD_FETCH[0x1].INSTR_1: 0x99750 + 00000030 VFD_FETCH[0x1].INSTR_2: { SIZE = 0x30 } + 00000001 VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } + 7000411f VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID | SWITCHNEXT } + 3000011f VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID } + 00060010 SP_SP_CTRL_REG: { 0x60010 } + 000005c3 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } !+ 00200800 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 2 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } !+ 08000002 SP_VS_CTRL_REG1: { CONSTLENGTH = 2 | INITIALOUTSTANDING = 8 } !+ 0010fc04 SP_VS_PARAM_REG: { POSREGID = r1.x | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } !+ 00001e00 SP_VS_OUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00fcfc00 UNKNOWN_22D7: 0xfcfc00 + 00000008 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } !+ 00049000 SP_VS_OBJ_START: 0x49000 00049000: 0000: 00000000 13000000 00000000 00000000 00000000 00000000 00000000 00000000 * :0:0000:0000[13000000x_00000000x] (sy)end :0:0001:0001[00000000x_00000000x] nop :0:0002:0002[00000000x_00000000x] nop :0:0003:0003[00000000x_00000000x] nop :0:0004:0004[00000000x_00000000x] nop Stats: - shaderdb: 5 instr, 4 nops, 1 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 0 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 0 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) !+ 00000001 SP_VS_LENGTH_REG: 1 !+ 00340412 SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE } !+ 80100002 SP_FS_CTRL_REG1: { CONSTLENGTH = 2 | VARYING | 0x80000000 } !+ 7e020000 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } !+ 00046000 SP_FS_OBJ_START: 0x46000 00046000: 0000: 00002000 5730cb00 00000000 03000000 00000000 00000000 00000000 00000000 * :2:0000:0000[5730cb00x_00002000x] (sy)(rpt3)bary.f (ei)hr0.x, (r)0, r0.x :0:0001:0004[03000000x_00000000x] end :0:0002:0005[00000000x_00000000x] nop :0:0003:0006[00000000x_00000000x] nop :0:0004:0007[00000000x_00000000x] nop :0:0005:0008[00000000x_00000000x] nop Stats: - shaderdb: 9 instr, 4 nops, 5 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 1 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 4 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) + 00000001 SP_FS_LENGTH_REG: 1 !+ fc00fc01 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r63.x } !+ 0001a100 SP_FS_MRT[0].REG: { REGID = r0.x | HALF_PRECISION | MRTFORMAT = RB4_R8G8B8A8_UNORM } + 00000000 0x230c: 00000000 + 7e020000 SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } + 00000000 SP_HS_OBJ_START: 0 + 00000000 0x2318: 00000000 + 00000000 0x2319: 00000000 + 7e020000 SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } + 00000000 SP_DS_OBJ_START: 0 + 00000000 0x2340: 00000000 + 7e020000 SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } + 00000000 SP_GS_OBJ_START: 0 + 00000808 TPL1_TP_TEX_OFFSET: 0x808 + 00000000 TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } !+ 00000002 0x2382: 00000002 !+ 00000000 TPL1_TP_FS_TEX_COUNT: 0 !+ 080604f0 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0x600a0 } !+ fcfc1108 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x1008 } !+ fff3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } + fcfcfc00 HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } !+ 00fcfc00 HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r0.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } !+ 01010002 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 2 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 1 } !+ 017f0202 HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 2 | CONSTOBJECTOFFSET = 2 | ENABLED | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 } !+ 007e0200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } !+ 007e0200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } !+ 007e0200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } !+ 00000003 HLSQ_UPDATE_CONTROL: 0x3 000555ac: 0000: c0023800 00200984 00000001 00000003 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 18 | GROUP_ID = 1 } { ADDR_LO = 0x99a60 } 000555bc: 0000: c0014300 01000012 00099a60 group_id: 1 count: 18 addr: 0000000000099a60 flags: 0 00099a60: 0000: 00002200 082a0008 00002201 fcfc0081 00002203 0000fc00 0007220a 0008080f 00099a80: 0020: 00099a00 00000060 00000001 0000080f 00099a30 00000030 00000001 0001228a 00099aa0: 0040: 7000411f 3000011f t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } 00099a60: 0000: 00002200 082a0008 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } 00099a68: 0000: 00002201 fcfc0081 t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } 00099a70: 0000: 00002203 0000fc00 t0 write VFD_FETCH[0].INSTR_0 (220a) VFD_FETCH[0].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 | SWITCHNEXT } VFD_FETCH[0].INSTR_1: 0x99a00 VFD_FETCH[0].INSTR_2: { SIZE = 0x60 } VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 } VFD_FETCH[0x1].INSTR_1: 0x99a30 VFD_FETCH[0x1].INSTR_2: { SIZE = 0x30 } VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } 00099a78: 0000: 0007220a 0008080f 00099a00 00000060 00000001 0000080f 00099a30 00000030 00099a98: 0020: 00000001 t0 write VFD_DECODE[0].INSTR (228a) VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID | SWITCHNEXT } VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID } 00099a9c: 0000: 0001228a 7000411f 3000011f t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = USE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x200000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 3 } draw[12] register values + 082a0008 VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } + fcfc0081 VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } + 0000fc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } + 0008080f VFD_FETCH[0].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 | SWITCHNEXT } !+ 00099a00 VFD_FETCH[0].INSTR_1: 0x99a00 + 00000060 VFD_FETCH[0].INSTR_2: { SIZE = 0x60 } + 00000001 VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } + 0000080f VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 } !+ 00099a30 VFD_FETCH[0x1].INSTR_1: 0x99a30 + 00000030 VFD_FETCH[0x1].INSTR_2: { SIZE = 0x30 } + 00000001 VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } + 7000411f VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID | SWITCHNEXT } + 3000011f VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID } 000555c8: 0000: c0023800 00200984 00000001 00000003 0016b094: 0000: c0013f00 00055328 000000ac t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 0016b0a0: 0000: c0014300 00040000 00000000 t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:001707b8 ibsize:000000f7 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 001707b8: 0000: c0002600 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x4 001707c0: 0000: 00000ec3 00000004 t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x68 001707c8: 0000: 00000f03 00000068 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 001707d0: 0000: c0002600 00000000 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } 001707d8: 0000: 000023c0 080004f0 t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = 0x1d } event (null) 001707e0: 0000: c0004600 0000001d t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = FACENESS_FLUSH } event FACENESS_FLUSH 001707e8: 0000: c0004600 0000001c t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 001707f0: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0 001707f8: 0000: 00000cc6 00000000 t0 write UNKNOWN_0E42 (0e42) UNKNOWN_0E42: 0 00170800: 0000: 00000e42 00000000 t0 write HLSQ_MODE_CONTROL (0e05) HLSQ_MODE_CONTROL: 0x2 00170808: 0000: 00000e05 00000002 t0 write UNKNOWN_0CC5 (0cc5) UNKNOWN_0CC5: 0x4 00170810: 0000: 00000cc5 00000004 t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x7 00170818: 0000: 000023db 00000007 t0 write VFD_CONTROL_2 (2202) VFD_CONTROL_2: 0xfcfcfcfc 00170820: 0000: 00002202 fcfcfcfc t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } 00170828: 0000: 00002203 fcfcfc00 t0 write VFD_CONTROL_4 (2204) VFD_CONTROL_4: 0xfcfc 00170830: 0000: 00002204 0000fcfc t0 write VFD_INDEX_OFFSET (2208) VFD_INDEX_OFFSET: 0 00170838: 0000: 00002208 00000000 t0 write UNKNOWN_2209 (2209) UNKNOWN_2209: 0 00170840: 0000: 00002209 00000000 t0 write UNKNOWN_2152 (2152) UNKNOWN_2152: 0 UNKNOWN_2153: 0 00170848: 0000: 00012152 00000000 00000000 t0 write UNKNOWN_2156 (2156) UNKNOWN_2156: 0 00170854: 0000: 00002156 00000000 t0 write UNKNOWN_2154 (2154) UNKNOWN_2154: 0 0017085c: 0000: 00002154 00000000 t0 write UNKNOWN_2155 (2155) UNKNOWN_2155: 0 00170864: 0000: 00002155 00000000 t0 write UNKNOWN_21C3 (21c3) UNKNOWN_21C3: 0x1d 0017086c: 0000: 000021c3 0000001d t0 write PC_PRIM_VTX_CNTL2 (21c5) PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 00170874: 0000: 000021c5 00000012 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 0017087c: 0000: 000021e5 00000000 t0 write GRAS_SU_MODE_CONTROL (2078) GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } 00170884: 0000: 00002078 00000000 t0 write UNKNOWN_2001 (2001) UNKNOWN_2001: 0 0017088c: 0000: 00002001 00000000 t0 write GRAS_CNTL (2003) GRAS_CNTL: { IJ_PERSP } 00170894: 0000: 00002003 00000001 t0 write GRAS_CL_CLIP_CNTL (2000) GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } 0017089c: 0000: 00002000 00188000 t0 write TPL1_TP_TEX_COUNT (2381) TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } 001708a4: 0000: 00002381 00000000 t0 write TPL1_TP_FS_TEX_COUNT (23a0) TPL1_TP_FS_TEX_COUNT: 0x3 001708ac: 0000: 000023a0 00000003 t0 write RB_ALPHA_CONTROL (20f8) RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } 001708b4: 0000: 000020f8 00000e00 t0 write RB_RENDER_COMPONENTS (20fb) RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } 001708bc: 0000: 000020fb 0000000f t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 001708c4: 0000: c0014300 00040000 00000000 t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } 001708d0: 0000: 00002200 000a0000 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } 001708d8: 0000: 00002201 fc030000 t0 write SP_INSTR_CACHE_CTRL (22c1) SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } 001708e0: 0000: 000022c1 000005c3 t0 write HLSQ_CONTROL_1_REG (23c1) HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } 001708e8: 0000: 000023c1 fcfc0120 t0 write HLSQ_CONTROL_2_REG (23c2) HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 001708f0: 0000: 000023c2 27f3f3f0 t0 write HLSQ_VS_CONTROL_REG (23c5) HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } 001708f8: 0000: 000023c5 02010042 t0 write HLSQ_FS_CONTROL_REG (23c6) HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00170900: 0000: 000023c6 0041423e t0 write HLSQ_HS_CONTROL_REG (23c7) HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00170908: 0000: 000023c7 00404200 t0 write HLSQ_DS_CONTROL_REG (23c8) HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00170910: 0000: 000023c8 00404200 t0 write HLSQ_GS_CONTROL_REG (23c9) HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00170918: 0000: 000023c9 00404200 t0 write HLSQ_CS_CONTROL_REG (23ca) HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } 00170920: 0000: 000023ca 00004200 t0 write SP_SP_CTRL_REG (22c0) SP_SP_CTRL_REG: { 0x60010 } 00170928: 0000: 000022c0 00060010 t0 write UNKNOWN_21E6 (21e6) UNKNOWN_21E6: 0x1 00170930: 0000: 000021e6 00000001 t0 write SP_VS_CTRL_REG0 (22c4) SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 00170938: 0000: 000022c4 00200c10 t0 write SP_VS_CTRL_REG1 (22c5) SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } 00170940: 0000: 000022c5 01000042 t0 write VPC_ATTR (2140) VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | 0x40000000 } 00170948: 0000: 00002140 40001004 t0 write VPC_PACK (2141) VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } 00170950: 0000: 00002141 00040400 t0 write PC_PRIM_VTX_CNTL (21c4) PC_PRIM_VTX_CNTL: { VAROUT = 1 } 00170958: 0000: 000021c4 00000001 t0 write SP_VS_PARAM_REG (22c6) SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } UNKNOWN_22D7: 0xfcfc00 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 00170960: 0000: 001922c6 0010fc03 00001e03 00000000 00000000 00000000 00000000 00000000 * 001709a0: 0040: 00000000 00000000 00fcfc00 00000008 00000000 00000000 00000000 00000000 * t0 write SP_VS_OBJ_OFFSET_REG (22e0) SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 001709cc: 0000: 000022e0 00000000 t0 write SP_VS_OBJ_START (22e1) SP_VS_OBJ_START: 0x1 001709d4: 0000: 000022e1 00000001 t0 write SP_VS_LENGTH_REG (22e5) SP_VS_LENGTH_REG: 2 001709dc: 0000: 000022e5 00000002 t3 opcode: CP_LOAD_STATE4 (30) (67 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } :2:0000:0000[56d81803x_20020003x] (sy)(ss)(nop3) shl.b r0.w, r0.w, 2 :1:0001:0004[20150000x_00000003x] cov.s32s16 hr0.x, r0.w :0:0002:0005[00000200x_00000000x] (rpt2)nop :1:0003:0008[201100f4x_00000000x] mova a0.x, hr0.x :0:0004:0009[00000500x_00000000x] (rpt5)nop :1:0005:0015[20154003x_00000c20x] mov.s32s32 r0.w, c :1:0006:0016[20154004x_00000c21x] mov.s32s32 r1.x, c :1:0007:0017[20154005x_00000c22x] mov.s32s32 r1.y, c :1:0008:0018[20156006x_00000c23x] (ul)mov.s32s32 r1.z, c :0:0009:0019[03000000x_00000000x] end :2:0010:0020[46f00007x_20050000x] shr.b r1.w, r0.x, 5 :2:0011:0021[43980008x_201f0000x] (nop2) and.b r2.x, r0.x, 31 :2:0012:0024[43980807x_201f0007x] (nop3) and.b r1.w, r1.w, 31 :2:0013:0028[46100807x_20100007x] (nop1) mul.u24 r1.w, r1.w, 16 :3:0014:0030[62040007x_00071014x] mad.u24 r1.w, c5.x, r2.x, r1.w :0:0015:0031[00000500x_00000000x] (rpt5)nop :6:0016:0037[c2c60f00x_04800006x] stlw.u32 l[r1.w], r0.w, 4 :0:0017:0038[04800000x_00000000x] chmask :0:0018:0039[05000000x_00000000x] chsh Stats: - shaderdb: 40 instr, 24 nops, 16 non-nops, 5 mov, 1 cov - shaderdb: 0 last-baryf, 0 half, 2 full, 5 constlen - shaderdb: 27 cat0, 6 cat1, 5 cat2, 1 cat3, 0 cat4, 0 cat5, 1 cat6, 0 cat7 - shaderdb: 0 sstall, 1 (ss), 1 (sy) 001709e4: 0000: c0413000 00a00000 00000000 20020003 56d81803 00000003 20150000 00000000 00170a04: 0020: 00000200 00000000 201100f4 00000000 00000500 00000c20 20154003 00000c21 00170a24: 0040: 20154004 00000c22 20154005 00000c23 20156006 00000000 03000000 20050000 00170a44: 0060: 46f00007 201f0000 43980008 201f0007 43980807 20100007 46100807 00071014 00170a64: 0080: 62040007 00000000 00000500 04800006 c2c60f00 00000000 04800000 00000000 00170a84: 00a0: 05000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 * t0 write GRAS_SC_CONTROL (207b) GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = 0 | MSAA_DISABLE | RASTER_MODE = 0 } 00170af0: 0000: 0000207b 00000808 t0 write RB_MSAA_CONTROL (20a2) RB_MSAA_CONTROL: { DISABLE | SAMPLES = 0 } 00170af8: 0000: 000020a2 00001000 t0 write RB_RENDER_CONTROL (20a1) RB_RENDER_CONTROL: { DISABLE_COLOR_PIPE | 0x2 } 00170b00: 0000: 000020a1 00000022 t0 write RB_DEPTH_CONTROL (2101) RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } 00170b08: 0000: 00002101 00000000 t0 write GRAS_ALPHA_CONTROL (2073) GRAS_ALPHA_CONTROL: { 0x2 } 00170b10: 0000: 00002073 00000002 t0 write RB_STENCIL_CONTROL (2106) RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } 00170b18: 0000: 00002106 00000000 t0 write RB_COPY_CONTROL (20fc) RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_FOUR | MODE = RB_COPY_DEPTH_STENCIL | FASTCLEAR = 0 | GMEM_BASE = 0 } RB_COPY_DEST_BASE: { BASE = 0x4f000 } RB_COPY_DEST_PITCH: { PITCH = 256 } RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_DISABLE | COMPONENT_ENABLE = 0xf | ENDIAN = ENDIAN_NONE | TILE = TILE4_3 } 00170b20: 0000: 000320fc 00000052 0004f000 00000008 0303c068 t0 write UNKNOWN_20EF (20ef) UNKNOWN_20EF: 0 00170b34: 0000: 000020ef 00000000 t0 write GRAS_SC_SCREEN_SCISSOR_TL (207c) GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } 00170b3c: 0000: 0001207c 00000000 003f003f t0 write RB_FRAME_BUFFER_DIMENSION (0ce0) RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } 00170b48: 0000: 00000ce0 00400040 t0 write 0xce1 (0ce1) 0xce1: 00000000 00170b50: 0000: 00000ce1 00000000 t3 opcode: CP_LOAD_STATE4 (30) (11 dwords) { DST_OFF = 8 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } 00170b64: 0.000000 0.000000 1.000000 1.000000 64.000000 64.000000 1.000000 1.000000 00170b64: 0000: 00000000 00000000 3f800000 3f800000 42800000 42800000 3f800000 3f800000 00170b58: 0000: c0093000 00a00008 00000001 00000000 00000000 3f800000 3f800000 42800000 00170b78: 0020: 42800000 3f800000 3f800000 t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x80000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 2 } draw[13] register values + 00000004 UNKNOWN_0CC5: 0x4 + 00000000 UNKNOWN_0CC6: 0 + 00400040 RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } + 00000000 0xce1: 00000000 !+ 00000002 HLSQ_MODE_CONTROL: 0x2 + 00000000 UNKNOWN_0E42: 0 !+ 00000004 SP_MODE_CONTROL: 0x4 !+ 00000068 TPL1_TP_MODE_CONTROL: 0x68 !+ 00188000 GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } + 00000000 UNKNOWN_2001: 0 + 00000001 GRAS_CNTL: { IJ_PERSP } !+ 00000002 GRAS_ALPHA_CONTROL: { 0x2 } !+ 00000000 GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } !+ 00000808 GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = 0 | MSAA_DISABLE | RASTER_MODE = 0 } !+ 00000000 GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } !+ 003f003f GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } !+ 00000022 RB_RENDER_CONTROL: { DISABLE_COLOR_PIPE | 0x2 } !+ 00001000 RB_MSAA_CONTROL: { DISABLE | SAMPLES = 0 } + 00000000 UNKNOWN_20EF: 0 + 00000e00 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } + 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } !+ 00000052 RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_FOUR | MODE = RB_COPY_DEPTH_STENCIL | FASTCLEAR = 0 | GMEM_BASE = 0 } + 0004f000 RB_COPY_DEST_BASE: { BASE = 0x4f000 } + 00000008 RB_COPY_DEST_PITCH: { PITCH = 256 } !+ 0303c068 RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_DISABLE | COMPONENT_ENABLE = 0xf | ENDIAN = ENDIAN_NONE | TILE = TILE4_3 } + 00000000 RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } + 00000000 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } !+ 40001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | 0x40000000 } + 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } + 00000000 UNKNOWN_2152: 0 + 00000000 UNKNOWN_2153: 0 + 00000000 UNKNOWN_2154: 0 + 00000000 UNKNOWN_2155: 0 + 00000000 UNKNOWN_2156: 0 !+ 0000001d UNKNOWN_21C3: 0x1d !+ 00000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 } + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + 00000000 PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } + 00000001 UNKNOWN_21E6: 0x1 !+ 000a0000 VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } !+ fc030000 VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } + fcfcfcfc VFD_CONTROL_2: 0xfcfcfcfc !+ fcfcfc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } + 0000fcfc VFD_CONTROL_4: 0xfcfc + 00000000 VFD_INDEX_OFFSET: 0 + 00000000 UNKNOWN_2209: 0 + 00060010 SP_SP_CTRL_REG: { 0x60010 } + 000005c3 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } !+ 00200c10 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } !+ 01000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } !+ 0010fc03 SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } !+ 00001e03 SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00fcfc00 UNKNOWN_22D7: 0xfcfc00 + 00000008 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } !+ 00000001 SP_VS_OBJ_START: 0x1 !+ 00000002 SP_VS_LENGTH_REG: 2 + 00000000 TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } !+ 00000003 TPL1_TP_FS_TEX_COUNT: 0x3 !+ 080004f0 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } !+ fcfc0120 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } !+ 27f3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } !+ 02010042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } !+ 0041423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } !+ 00404200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } !+ 00404200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } !+ 00404200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00004200 HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } !+ 00000007 HLSQ_UPDATE_CONTROL: 0x7 00170b84: 0000: c0023800 00080888 00000001 00000002 0016b0ac: 0000: c0013f00 001707b8 000000f7 t3 opcode: (null) (1d) (2 dwords) 0016b0b8: 0000: c0001d00 00000000 ############################################################ vertices: 0 ############################################################ cmdstream: 8 dwords t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:000555d8 ibsize:00000155 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 000555d8: 0000: c0002600 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x4 000555e0: 0000: 00000ec3 00000004 t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x68 000555e8: 0000: 00000f03 00000068 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 000555f0: 0000: c0002600 00000000 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } 000555f8: 0000: 000023c0 080004f0 t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = 0x1d } event (null) 00055600: 0000: c0004600 0000001d t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = FACENESS_FLUSH } event FACENESS_FLUSH 00055608: 0000: c0004600 0000001c t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00055610: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0 00055618: 0000: 00000cc6 00000000 t0 write UNKNOWN_0E42 (0e42) UNKNOWN_0E42: 0 00055620: 0000: 00000e42 00000000 t0 write HLSQ_MODE_CONTROL (0e05) HLSQ_MODE_CONTROL: 0x2 00055628: 0000: 00000e05 00000002 t0 write UNKNOWN_0CC5 (0cc5) UNKNOWN_0CC5: 0x4 00055630: 0000: 00000cc5 00000004 t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x7 00055638: 0000: 000023db 00000007 t0 write VFD_CONTROL_2 (2202) VFD_CONTROL_2: 0xfcfcfcfc 00055640: 0000: 00002202 fcfcfcfc t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } 00055648: 0000: 00002203 fcfcfc00 t0 write VFD_CONTROL_4 (2204) VFD_CONTROL_4: 0xfcfc 00055650: 0000: 00002204 0000fcfc t0 write VFD_INDEX_OFFSET (2208) VFD_INDEX_OFFSET: 0 00055658: 0000: 00002208 00000000 t0 write UNKNOWN_2209 (2209) UNKNOWN_2209: 0 00055660: 0000: 00002209 00000000 t0 write UNKNOWN_2152 (2152) UNKNOWN_2152: 0 UNKNOWN_2153: 0 00055668: 0000: 00012152 00000000 00000000 t0 write UNKNOWN_2156 (2156) UNKNOWN_2156: 0 00055674: 0000: 00002156 00000000 t0 write UNKNOWN_2154 (2154) UNKNOWN_2154: 0 0005567c: 0000: 00002154 00000000 t0 write UNKNOWN_2155 (2155) UNKNOWN_2155: 0 00055684: 0000: 00002155 00000000 t0 write UNKNOWN_21C3 (21c3) UNKNOWN_21C3: 0x1d 0005568c: 0000: 000021c3 0000001d t0 write PC_PRIM_VTX_CNTL2 (21c5) PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 00055694: 0000: 000021c5 00000012 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 0005569c: 0000: 000021e5 00000000 t0 write GRAS_SU_MODE_CONTROL (2078) GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } 000556a4: 0000: 00002078 00000000 t0 write UNKNOWN_2001 (2001) UNKNOWN_2001: 0 000556ac: 0000: 00002001 00000000 t0 write GRAS_CNTL (2003) GRAS_CNTL: { IJ_PERSP } 000556b4: 0000: 00002003 00000001 t0 write GRAS_CL_CLIP_CNTL (2000) GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } 000556bc: 0000: 00002000 00188000 t0 write TPL1_TP_TEX_COUNT (2381) TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } 000556c4: 0000: 00002381 00000000 t0 write TPL1_TP_FS_TEX_COUNT (23a0) TPL1_TP_FS_TEX_COUNT: 0x3 000556cc: 0000: 000023a0 00000003 t0 write RB_ALPHA_CONTROL (20f8) RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } 000556d4: 0000: 000020f8 00000e00 t0 write RB_RENDER_COMPONENTS (20fb) RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } 000556dc: 0000: 000020fb 0000000f t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 000556e4: 0000: c0014300 00040000 00000000 t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } 000556f0: 0000: 00002200 000a0000 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } 000556f8: 0000: 00002201 fc030000 t0 write SP_INSTR_CACHE_CTRL (22c1) SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } 00055700: 0000: 000022c1 000005c3 t0 write HLSQ_CONTROL_1_REG (23c1) HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } 00055708: 0000: 000023c1 fcfc0120 t0 write HLSQ_CONTROL_2_REG (23c2) HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 00055710: 0000: 000023c2 27f3f3f0 t0 write HLSQ_VS_CONTROL_REG (23c5) HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } 00055718: 0000: 000023c5 02010042 t0 write HLSQ_FS_CONTROL_REG (23c6) HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 1 } 00055720: 0000: 000023c6 0141423e t0 write HLSQ_HS_CONTROL_REG (23c7) HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00055728: 0000: 000023c7 00404200 t0 write HLSQ_DS_CONTROL_REG (23c8) HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00055730: 0000: 000023c8 00404200 t0 write HLSQ_GS_CONTROL_REG (23c9) HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00055738: 0000: 000023c9 00404200 t0 write HLSQ_CS_CONTROL_REG (23ca) HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } 00055740: 0000: 000023ca 00004200 t0 write SP_SP_CTRL_REG (22c0) SP_SP_CTRL_REG: { 0x60010 } 00055748: 0000: 000022c0 00060010 t0 write UNKNOWN_21E6 (21e6) UNKNOWN_21E6: 0x1 00055750: 0000: 000021e6 00000001 t0 write SP_VS_CTRL_REG0 (22c4) SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 00055758: 0000: 000022c4 00200c10 t0 write SP_VS_CTRL_REG1 (22c5) SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } 00055760: 0000: 000022c5 01000042 t0 write VPC_ATTR (2140) VPC_ATTR: { TOTALATTR = 8 | THRDASSIGN = 1 | ENABLE | 0x40000000 } 00055768: 0000: 00002140 42001008 t0 write VPC_PACK (2141) VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 8 | NUMNONPOSVSVAR = 6 } 00055770: 0000: 00002141 00060800 t0 write PC_PRIM_VTX_CNTL (21c4) PC_PRIM_VTX_CNTL: { VAROUT = 1 } 00055778: 0000: 000021c4 00000001 t0 write SP_VS_PARAM_REG (22c6) SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 2 } SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r1.w | B_COMPMASK = 0x3 } SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } UNKNOWN_22D7: 0xfcfc00 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 12 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 00055780: 0000: 001922c6 0020fc03 06071e03 00000000 00000000 00000000 00000000 00000000 * 000557c0: 0040: 00000000 00000000 00fcfc00 00000c08 00000000 00000000 00000000 00000000 * t0 write SP_VS_OBJ_OFFSET_REG (22e0) SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 000557ec: 0000: 000022e0 00000000 t0 write SP_VS_OBJ_START (22e1) SP_VS_OBJ_START: 0x1 000557f4: 0000: 000022e1 00000001 t0 write SP_VS_LENGTH_REG (22e5) SP_VS_LENGTH_REG: 2 000557fc: 0000: 000022e5 00000002 t3 opcode: CP_LOAD_STATE4 (30) (67 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } :2:0000:0000[56d81803x_20020003x] (sy)(ss)(nop3) shl.b r0.w, r0.w, 2 :1:0001:0004[20150000x_00000003x] cov.s32s16 hr0.x, r0.w :0:0002:0005[00000200x_00000000x] (rpt2)nop :1:0003:0008[201100f4x_00000000x] mova a0.x, hr0.x :0:0004:0009[00000500x_00000000x] (rpt5)nop :1:0005:0015[20154003x_00000c20x] mov.s32s32 r0.w, c :1:0006:0016[20154004x_00000c21x] mov.s32s32 r1.x, c :1:0007:0017[20154007x_00000c22x] mov.s32s32 r1.w, c :1:0008:0018[20156008x_00000c23x] (ul)mov.s32s32 r2.x, c :1:0009:0019[20554005x_00000000x] mov.s32s32 r1.y, 0 :1:0010:0020[20554006x_3f800000x] mov.s32s32 r1.z, 1065353216 :0:0011:0021[03000000x_00000000x] end :2:0012:0022[46f00009x_20050000x] shr.b r2.y, r0.x, 5 :2:0013:0023[4398000ax_201f0000x] (nop2) and.b r2.z, r0.x, 31 :2:0014:0026[43980809x_201f0009x] (nop3) and.b r2.y, r2.y, 31 :2:0015:0030[46100809x_20180009x] (nop1) mul.u24 r2.y, r2.y, 24 :3:0016:0032[62050009x_00091014x] mad.u24 r2.y, c5.x, r2.z, r2.y :0:0017:0033[00000500x_00000000x] (rpt5)nop :6:0018:0039[c2c61300x_04800006x] stlw.u32 l[r2.y], r0.w, 4 :6:0019:0040[c2c61310x_0280000ex] stlw.u32 l[r2.y+16], r1.w, 2 :0:0020:0041[04800000x_00000000x] chmask :0:0021:0042[05000000x_00000000x] chsh Stats: - shaderdb: 43 instr, 24 nops, 19 non-nops, 7 mov, 1 cov - shaderdb: 0 last-baryf, 0 half, 3 full, 5 constlen - shaderdb: 27 cat0, 8 cat1, 5 cat2, 1 cat3, 0 cat4, 0 cat5, 2 cat6, 0 cat7 - shaderdb: 0 sstall, 1 (ss), 1 (sy) 00055804: 0000: c0413000 00a00000 00000000 20020003 56d81803 00000003 20150000 00000000 00055824: 0020: 00000200 00000000 201100f4 00000000 00000500 00000c20 20154003 00000c21 00055844: 0040: 20154004 00000c22 20154007 00000c23 20156008 00000000 20554005 3f800000 00055864: 0060: 20554006 00000000 03000000 20050000 46f00009 201f0000 4398000a 201f0009 00055884: 0080: 43980809 20180009 46100809 00091014 62050009 00000000 00000500 04800006 000558a4: 00a0: c2c61300 0280000e c2c61310 00000000 04800000 00000000 05000000 00000000 * t0 write HLSQ_CONTROL_3_REG (23c3) HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } 00055910: 0000: 000023c3 fcfcfc00 t0 write HLSQ_CONTROL_4_REG (23c4) HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } 00055918: 0000: 000023c4 00fcfcfc t0 write SP_FS_CTRL_REG0 (22e8) SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 0 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE | PIXLODENABLE } SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 } 00055920: 0000: 000122e8 00700402 8010003e t0 write SP_FS_OBJ_OFFSET_REG (22ea) SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 } 0005592c: 0000: 000022ea 40420000 t0 write SP_FS_OBJ_START (22eb) SP_FS_OBJ_START: 0x1 00055934: 0000: 000022eb 00000001 t0 write SP_FS_LENGTH_REG (22ef) SP_FS_LENGTH_REG: 1 0005593c: 0000: 000022ef 00000001 t0 write SP_FS_OUTPUT_REG (22f0) SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r0.x | SAMPLEMASK_REGID = r0.x } 00055944: 0000: 000022f0 00000001 t0 write VPC_VARYING_INTERP[0].MODE (2142) VPC_VARYING_INTERP[0].MODE: 0xe000 0005594c: 0000: 00002142 0000e000 t0 write RB_FS_OUTPUT_REG (2100) RB_FS_OUTPUT_REG: { MRT = 1 } 00055954: 0000: 00002100 00000001 t3 opcode: CP_LOAD_STATE4 (30) (35 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 1 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } :2:0000:0000[57309902x_00002004x] (sy)(ss)(rpt1)bary.f (ei)r0.z, (r)4, r0.x :0:0001:0002[00000500x_00000000x] (rpt5)nop :5:0002:0008[a0c01f00x_00000005x] sam (f32)(xyzw)r0.x, r0.z, s#0, t#0 :0:0003:0009[03000000x_00000000x] end :0:0004:0010[00000000x_00000000x] nop :0:0005:0011[00000000x_00000000x] nop :0:0006:0012[00000000x_00000000x] nop :0:0007:0013[00000000x_00000000x] nop Stats: - shaderdb: 14 instr, 10 nops, 4 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 0 half, 1 full, 0 constlen - shaderdb: 11 cat0, 0 cat1, 2 cat2, 0 cat3, 0 cat4, 1 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 1 (ss), 1 (sy) 0005595c: 0000: c0213000 00700000 00000000 00002004 57309902 00000000 00000500 00000005 0005597c: 0020: a0c01f00 00000000 03000000 00000000 00000000 00000000 00000000 00000000 * t0 write RB_FS_OUTPUT (20f9) RB_FS_OUTPUT: { ENABLE_BLEND = 0 | SAMPLE_MASK = 0xffff } 000559e8: 0000: 000020f9 ffff0000 t0 write RB_MRT[0].CONTROL (20a4) RB_MRT[0].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0xf } 000559f0: 0000: 000020a4 0f000000 t0 write RB_MRT[0x1].CONTROL (20a9) RB_MRT[0x1].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0xf } 000559f8: 0000: 000020a9 0f000000 t0 write RB_MRT[0].BLEND_CONTROL (20a8) RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } 00055a00: 0000: 000020a8 00000000 t3 opcode: CP_LOAD_STATE4 (30) (5 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_TEX | NUM_UNIT = 1 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } { XY_MAG = A4XX_TEX_NEAREST | XY_MIN = A4XX_TEX_NEAREST | WRAP_S = A4XX_TEX_CLAMP_TO_EDGE | WRAP_T = A4XX_TEX_CLAMP_TO_EDGE | WRAP_R = A4XX_TEX_CLAMP_TO_EDGE | ANISO = A4XX_TEX_ANISO_1 | LOD_BIAS = 0.000000 | 0x60000 } { COMPARE_FUNC = FUNC_LEQUAL | UNNORM_COORDS | MIPFILTER_LINEAR_FAR | MAX_LOD = 0.000000 | MIN_LOD = 0.000000 | 0x1 } 00055a14: 0000: 00060920 00000067 00055a08: 0000: c0033000 00500000 00000000 00060920 00000067 t0 write GRAS_SC_CONTROL (207b) GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 0 | RASTER_MODE = 0 } 00055a1c: 0000: 0000207b 00000000 t0 write RB_MSAA_CONTROL (20a2) RB_MSAA_CONTROL: { SAMPLES = 0 } 00055a24: 0000: 000020a2 00000000 t0 write RB_RENDER_CONTROL (20a1) RB_RENDER_CONTROL: { 0 } 00055a2c: 0000: 000020a1 00000000 t0 write 0x2382 (2382) 0x2382: 00000000 00055a34: 0000: 00002382 00000000 t0 write RB_DEPTH_CONTROL (2101) RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } 00055a3c: 0000: 00002101 00000000 t0 write GRAS_ALPHA_CONTROL (2073) GRAS_ALPHA_CONTROL: { 0 } 00055a44: 0000: 00002073 00000000 t0 write RB_STENCIL_CONTROL (2106) RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } 00055a4c: 0000: 00002106 00000000 t0 write SP_FS_MRT[0].REG (22f1) SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = RB4_R8G8B8A8_UNORM } 00055a54: 0000: 000022f1 0001a000 t0 write RB_MRT[0].BUF_INFO (20a5) RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB4_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE4_3 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 256 } RB_MRT[0].BASE: 0x166000 RB_MRT[0].CONTROL3: { STRIDE = 0 } 00055a5c: 0000: 000220a5 000400da 00166000 00000000 t3 opcode: CP_LOAD_STATE4 (30) (11 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_TEX | NUM_UNIT = 1 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } { TILED | SWIZ_X = A4XX_TEX_X | SWIZ_Y = A4XX_TEX_Y | SWIZ_Z = A4XX_TEX_Z | SWIZ_W = A4XX_TEX_W | MIPLVLS = 0 | FMT = TFMT4_8_8_8_8_UNORM | TYPE = A4XX_TEX_2D | 0x2 } { HEIGHT = 64 | WIDTH = 64 } { PITCHALIGN = 0 | PITCH = 256 | SWAP = WZYX } { LAYERSZ = 0 | DEPTH = 1 | 0x20000 } { LAYERSZ = 4096 | BASE = 0x4f000 } { 5 = 0 } { 6 = 0 } { 7 = 0 } 00055a78: 0000: 27006883 00200040 00020000 00060000 0004f001 00000000 00000000 00000000 00055a6c: 0000: c0093000 00500000 00000001 27006883 00200040 00020000 00060000 0004f001 * t0 write VPC_VARYING_PS_REPL[0].MODE (214a) VPC_VARYING_PS_REPL[0].MODE: 0x99999999 00055a98: 0000: 0000214a 99999999 t0 write GRAS_SC_SCREEN_SCISSOR_TL (207c) GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } 00055aa0: 0000: 0001207c 00000000 003f003f t0 write GRAS_SC_WINDOW_SCISSOR_BR (209c) GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 00055aac: 0000: 0001209c 003f003f 00000000 t0 write RB_FRAME_BUFFER_DIMENSION (0ce0) RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } 00055ab8: 0000: 00000ce0 00400040 t0 write 0xce1 (0ce1) 0xce1: 00000000 00055ac0: 0000: 00000ce1 00000000 t0 write RB_RENDER_CONTROL2 (20a3) RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 | IJ_PERSP_PIXEL } 00055ac8: 0000: 000020a3 00001000 t0 write RB_MODE_CONTROL (20a0) RB_MODE_CONTROL: { WIDTH = 0 | HEIGHT = 0 | 0xc00000 } 00055ad0: 0000: 000020a0 00c00000 t3 opcode: CP_LOAD_STATE4 (30) (11 dwords) { DST_OFF = 8 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } 00055ae4: 0.000000 0.000000 0.000000 0.000000 64.000000 64.000000 64.000000 64.000000 00055ae4: 0000: 00000000 00000000 00000000 00000000 42800000 42800000 42800000 42800000 00055ad8: 0000: c0093000 00a00008 00000001 00000000 00000000 00000000 00000000 42800000 00055af8: 0020: 42800000 42800000 42800000 t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x80000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 2 } draw[14] register values + 00000004 UNKNOWN_0CC5: 0x4 + 00000000 UNKNOWN_0CC6: 0 + 00400040 RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } + 00000000 0xce1: 00000000 + 00000002 HLSQ_MODE_CONTROL: 0x2 + 00000000 UNKNOWN_0E42: 0 + 00000004 SP_MODE_CONTROL: 0x4 + 00000068 TPL1_TP_MODE_CONTROL: 0x68 + 00188000 GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } + 00000000 UNKNOWN_2001: 0 + 00000001 GRAS_CNTL: { IJ_PERSP } !+ 00000000 GRAS_ALPHA_CONTROL: { 0 } + 00000000 GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } !+ 00000000 GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 0 | RASTER_MODE = 0 } + 00000000 GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } + 003f003f GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } + 003f003f GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } + 00000000 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } !+ 00c00000 RB_MODE_CONTROL: { WIDTH = 0 | HEIGHT = 0 | 0xc00000 } !+ 00000000 RB_RENDER_CONTROL: { 0 } !+ 00000000 RB_MSAA_CONTROL: { SAMPLES = 0 } !+ 00001000 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 | IJ_PERSP_PIXEL } !+ 0f000000 RB_MRT[0].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0xf } !+ 000400da RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB4_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE4_3 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 256 } !+ 00166000 RB_MRT[0].BASE: 0x166000 !+ 00000000 RB_MRT[0].CONTROL3: { STRIDE = 0 } + 00000000 RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } + 0f000000 RB_MRT[0x1].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0xf } + 00000e00 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } !+ ffff0000 RB_FS_OUTPUT: { ENABLE_BLEND = 0 | SAMPLE_MASK = 0xffff } + 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } + 00000001 RB_FS_OUTPUT_REG: { MRT = 1 } + 00000000 RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } + 00000000 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } !+ 42001008 VPC_ATTR: { TOTALATTR = 8 | THRDASSIGN = 1 | ENABLE | 0x40000000 } !+ 00060800 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 8 | NUMNONPOSVSVAR = 6 } !+ 0000e000 VPC_VARYING_INTERP[0].MODE: 0xe000 !+ 99999999 VPC_VARYING_PS_REPL[0].MODE: 0x99999999 + 00000000 UNKNOWN_2152: 0 + 00000000 UNKNOWN_2153: 0 + 00000000 UNKNOWN_2154: 0 + 00000000 UNKNOWN_2155: 0 + 00000000 UNKNOWN_2156: 0 + 0000001d UNKNOWN_21C3: 0x1d + 00000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 } + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + 00000000 PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } + 00000001 UNKNOWN_21E6: 0x1 + 000a0000 VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } + fc030000 VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } + fcfcfcfc VFD_CONTROL_2: 0xfcfcfcfc + fcfcfc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } + 0000fcfc VFD_CONTROL_4: 0xfcfc + 00000000 VFD_INDEX_OFFSET: 0 + 00000000 UNKNOWN_2209: 0 + 00060010 SP_SP_CTRL_REG: { 0x60010 } + 000005c3 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } + 00200c10 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } + 01000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } !+ 0020fc03 SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 2 } !+ 06071e03 SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r1.w | B_COMPMASK = 0x3 } + 00000000 SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00fcfc00 UNKNOWN_22D7: 0xfcfc00 !+ 00000c08 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 12 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } + 00000001 SP_VS_OBJ_START: 0x1 + 00000002 SP_VS_LENGTH_REG: 2 !+ 00700402 SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 0 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE | PIXLODENABLE } !+ 8010003e SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 } !+ 40420000 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 } !+ 00000001 SP_FS_OBJ_START: 0x1 + 00000001 SP_FS_LENGTH_REG: 1 !+ 00000001 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r0.x | SAMPLEMASK_REGID = r0.x } !+ 0001a000 SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = RB4_R8G8B8A8_UNORM } + 00000000 TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } !+ 00000000 0x2382: 00000000 + 00000003 TPL1_TP_FS_TEX_COUNT: 0x3 + 080004f0 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } + fcfc0120 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } + 27f3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } + fcfcfc00 HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } !+ 00fcfcfc HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } + 02010042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } !+ 0141423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 1 } + 00404200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00004200 HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } + 00000007 HLSQ_UPDATE_CONTROL: 0x7 00055b04: 0000: c0023800 00080888 00000001 00000002 t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = CACHE_FLUSH } event CACHE_FLUSH 00055b14: 0000: c0004600 00000006 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00055b1c: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0x8000012 00055b24: 0000: 00000cc6 08000012 00173000: 0000: c0013f00 000555d8 00000155 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 0017300c: 0000: c0014300 00040000 00000000 t3 opcode: (null) (1d) (2 dwords) 00173018: 0000: c0001d00 00000000 ############################################################ vertices: 0 ############################################################ cmdstream: 48 dwords t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 0016b000: 0000: c0002600 00000000 t0 write UCHE_INVALIDATE0 (0e8a) UCHE_INVALIDATE0: 0 UCHE_INVALIDATE1: 0x12 0016b008: 0000: 00010e8a 00000000 00000012 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 0016b014: 0000: c0002600 00000000 t0 write RB_MODE_CONTROL (20a0) RB_MODE_CONTROL: { WIDTH = 64 | HEIGHT = 64 | ENABLE_GMEM } 0016b01c: 0000: 000020a0 00010202 t0 write RB_FRAME_BUFFER_DIMENSION (0ce0) RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } 0016b024: 0000: 00000ce0 00400040 t0 write 0xce1 (0ce1) 0xce1: 00000001 0016b02c: 0000: 00000ce1 00000001 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 0016b034: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0 0016b03c: 0000: 00000cc6 00000000 t3 opcode: (null) (1d) (2 dwords) 0016b044: 0000: c0001d00 00000000 t0 write GRAS_SC_WINDOW_SCISSOR_BR (209c) GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 0016b04c: 0000: 0001209c 003f003f 00000000 t0 write RB_BIN_OFFSET (210d) RB_BIN_OFFSET: { X = 0 | Y = 0 } 0016b058: 0000: 0000210d 00000000 t0 write GRAS_SC_WINDOW_SCISSOR_BR (209c) GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 0016b060: 0000: 0001209c 003f003f 00000000 t0 write UNKNOWN_2157 (2157) UNKNOWN_2157: 0x1 0016b06c: 0000: 00002157 00000001 t3 opcode: (null) (64) (2 dwords) 0016b074: 0000: c0006400 00000001 t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:00054994 ibsize:000000f6 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00054994: 0000: c0002600 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x4 0005499c: 0000: 00000ec3 00000004 t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x68 000549a4: 0000: 00000f03 00000068 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 000549ac: 0000: c0002600 00000000 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } 000549b4: 0000: 000023c0 080004f0 t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = 0x1d } event (null) 000549bc: 0000: c0004600 0000001d t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = FACENESS_FLUSH } event FACENESS_FLUSH 000549c4: 0000: c0004600 0000001c t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 000549cc: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0 000549d4: 0000: 00000cc6 00000000 t0 write UNKNOWN_0E42 (0e42) UNKNOWN_0E42: 0 000549dc: 0000: 00000e42 00000000 t0 write HLSQ_MODE_CONTROL (0e05) HLSQ_MODE_CONTROL: 0x2 000549e4: 0000: 00000e05 00000002 t0 write UNKNOWN_0CC5 (0cc5) UNKNOWN_0CC5: 0x4 000549ec: 0000: 00000cc5 00000004 t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x7 000549f4: 0000: 000023db 00000007 t0 write VFD_CONTROL_2 (2202) VFD_CONTROL_2: 0xfcfcfcfc 000549fc: 0000: 00002202 fcfcfcfc t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } 00054a04: 0000: 00002203 fcfcfc00 t0 write VFD_CONTROL_4 (2204) VFD_CONTROL_4: 0xfcfc 00054a0c: 0000: 00002204 0000fcfc t0 write VFD_INDEX_OFFSET (2208) VFD_INDEX_OFFSET: 0 00054a14: 0000: 00002208 00000000 t0 write UNKNOWN_2209 (2209) UNKNOWN_2209: 0 00054a1c: 0000: 00002209 00000000 t0 write UNKNOWN_2152 (2152) UNKNOWN_2152: 0 UNKNOWN_2153: 0 00054a24: 0000: 00012152 00000000 00000000 t0 write UNKNOWN_2156 (2156) UNKNOWN_2156: 0 00054a30: 0000: 00002156 00000000 t0 write UNKNOWN_2154 (2154) UNKNOWN_2154: 0 00054a38: 0000: 00002154 00000000 t0 write UNKNOWN_2155 (2155) UNKNOWN_2155: 0 00054a40: 0000: 00002155 00000000 t0 write UNKNOWN_21C3 (21c3) UNKNOWN_21C3: 0x1d 00054a48: 0000: 000021c3 0000001d t0 write PC_PRIM_VTX_CNTL2 (21c5) PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 00054a50: 0000: 000021c5 00000012 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 00054a58: 0000: 000021e5 00000000 t0 write GRAS_SU_MODE_CONTROL (2078) GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } 00054a60: 0000: 00002078 00000000 t0 write UNKNOWN_2001 (2001) UNKNOWN_2001: 0 00054a68: 0000: 00002001 00000000 t0 write GRAS_CNTL (2003) GRAS_CNTL: { IJ_PERSP } 00054a70: 0000: 00002003 00000001 t0 write GRAS_CL_CLIP_CNTL (2000) GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } 00054a78: 0000: 00002000 00188000 t0 write TPL1_TP_TEX_COUNT (2381) TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } 00054a80: 0000: 00002381 00000000 t0 write TPL1_TP_FS_TEX_COUNT (23a0) TPL1_TP_FS_TEX_COUNT: 0x3 00054a88: 0000: 000023a0 00000003 t0 write RB_ALPHA_CONTROL (20f8) RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } 00054a90: 0000: 000020f8 00000e00 t0 write RB_RENDER_COMPONENTS (20fb) RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } 00054a98: 0000: 000020fb 0000000f t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 00054aa0: 0000: c0014300 00040000 00000000 t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } 00054aac: 0000: 00002200 000a0000 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } 00054ab4: 0000: 00002201 fc030000 t0 write SP_INSTR_CACHE_CTRL (22c1) SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } 00054abc: 0000: 000022c1 000005c3 t0 write HLSQ_CONTROL_1_REG (23c1) HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } 00054ac4: 0000: 000023c1 fcfc0120 t0 write HLSQ_CONTROL_2_REG (23c2) HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 00054acc: 0000: 000023c2 27f3f3f0 t0 write HLSQ_VS_CONTROL_REG (23c5) HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } 00054ad4: 0000: 000023c5 02010042 t0 write HLSQ_FS_CONTROL_REG (23c6) HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00054adc: 0000: 000023c6 0041423e t0 write HLSQ_HS_CONTROL_REG (23c7) HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00054ae4: 0000: 000023c7 00404200 t0 write HLSQ_DS_CONTROL_REG (23c8) HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00054aec: 0000: 000023c8 00404200 t0 write HLSQ_GS_CONTROL_REG (23c9) HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00054af4: 0000: 000023c9 00404200 t0 write HLSQ_CS_CONTROL_REG (23ca) HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } 00054afc: 0000: 000023ca 00004200 t0 write SP_SP_CTRL_REG (22c0) SP_SP_CTRL_REG: { 0x60010 } 00054b04: 0000: 000022c0 00060010 t0 write UNKNOWN_21E6 (21e6) UNKNOWN_21E6: 0x1 00054b0c: 0000: 000021e6 00000001 t0 write SP_VS_CTRL_REG0 (22c4) SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 00054b14: 0000: 000022c4 00200c10 t0 write SP_VS_CTRL_REG1 (22c5) SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } 00054b1c: 0000: 000022c5 01000042 t0 write VPC_ATTR (2140) VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | 0x40000000 } 00054b24: 0000: 00002140 40001004 t0 write VPC_PACK (2141) VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } 00054b2c: 0000: 00002141 00040400 t0 write PC_PRIM_VTX_CNTL (21c4) PC_PRIM_VTX_CNTL: { VAROUT = 1 } 00054b34: 0000: 000021c4 00000001 t0 write SP_VS_PARAM_REG (22c6) SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } UNKNOWN_22D7: 0xfcfc00 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 00054b3c: 0000: 001922c6 0010fc03 00001e03 00000000 00000000 00000000 00000000 00000000 * 00054b7c: 0040: 00000000 00000000 00fcfc00 00000008 00000000 00000000 00000000 00000000 * t0 write SP_VS_OBJ_OFFSET_REG (22e0) SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 00054ba8: 0000: 000022e0 00000000 t0 write SP_VS_OBJ_START (22e1) SP_VS_OBJ_START: 0x1 00054bb0: 0000: 000022e1 00000001 t0 write SP_VS_LENGTH_REG (22e5) SP_VS_LENGTH_REG: 2 00054bb8: 0000: 000022e5 00000002 t3 opcode: CP_LOAD_STATE4 (30) (67 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } :2:0000:0000[56d81803x_20020003x] (sy)(ss)(nop3) shl.b r0.w, r0.w, 2 :1:0001:0004[20150000x_00000003x] cov.s32s16 hr0.x, r0.w :0:0002:0005[00000200x_00000000x] (rpt2)nop :1:0003:0008[201100f4x_00000000x] mova a0.x, hr0.x :0:0004:0009[00000500x_00000000x] (rpt5)nop :1:0005:0015[20154003x_00000c20x] mov.s32s32 r0.w, c :1:0006:0016[20154004x_00000c21x] mov.s32s32 r1.x, c :1:0007:0017[20154005x_00000c22x] mov.s32s32 r1.y, c :1:0008:0018[20156006x_00000c23x] (ul)mov.s32s32 r1.z, c :0:0009:0019[03000000x_00000000x] end :2:0010:0020[46f00007x_20050000x] shr.b r1.w, r0.x, 5 :2:0011:0021[43980008x_201f0000x] (nop2) and.b r2.x, r0.x, 31 :2:0012:0024[43980807x_201f0007x] (nop3) and.b r1.w, r1.w, 31 :2:0013:0028[46100807x_20100007x] (nop1) mul.u24 r1.w, r1.w, 16 :3:0014:0030[62040007x_00071014x] mad.u24 r1.w, c5.x, r2.x, r1.w :0:0015:0031[00000500x_00000000x] (rpt5)nop :6:0016:0037[c2c60f00x_04800006x] stlw.u32 l[r1.w], r0.w, 4 :0:0017:0038[04800000x_00000000x] chmask :0:0018:0039[05000000x_00000000x] chsh Stats: - shaderdb: 40 instr, 24 nops, 16 non-nops, 5 mov, 1 cov - shaderdb: 0 last-baryf, 0 half, 2 full, 5 constlen - shaderdb: 27 cat0, 6 cat1, 5 cat2, 1 cat3, 0 cat4, 0 cat5, 1 cat6, 0 cat7 - shaderdb: 0 sstall, 1 (ss), 1 (sy) 00054bc0: 0000: c0413000 00a00000 00000000 20020003 56d81803 00000003 20150000 00000000 00054be0: 0020: 00000200 00000000 201100f4 00000000 00000500 00000c20 20154003 00000c21 00054c00: 0040: 20154004 00000c22 20154005 00000c23 20156006 00000000 03000000 20050000 00054c20: 0060: 46f00007 201f0000 43980008 201f0007 43980807 20100007 46100807 00071014 00054c40: 0080: 62040007 00000000 00000500 04800006 c2c60f00 00000000 04800000 00000000 00054c60: 00a0: 05000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 * t0 write GRAS_ALPHA_CONTROL (2073) GRAS_ALPHA_CONTROL: { 0x2 } 00054ccc: 0000: 00002073 00000002 t0 write GRAS_SC_CONTROL (207b) GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = 4 | MSAA_DISABLE | RASTER_MODE = 0 } 00054cd4: 0000: 0000207b 00000a08 t0 write RB_MSAA_CONTROL (20a2) RB_MSAA_CONTROL: { DISABLE | SAMPLES = 4 } 00054cdc: 0000: 000020a2 00009000 t0 write RB_RENDER_CONTROL (20a1) RB_RENDER_CONTROL: { DISABLE_COLOR_PIPE | 0x2 } 00054ce4: 0000: 000020a1 00000022 t0 write RB_CLEAR_COLOR_DW0 (20cc) RB_CLEAR_COLOR_DW0: 0xff000000 RB_CLEAR_COLOR_DW1: 0 RB_CLEAR_COLOR_DW2: 0 RB_CLEAR_COLOR_DW3: 0 00054cec: 0000: 000320cc ff000000 00000000 00000000 00000000 t0 write RB_COPY_CONTROL (20fc) RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_FOUR | MODE = RB_COPY_CLEAR | FASTCLEAR = 0xf | GMEM_BASE = 0 } RB_COPY_DEST_BASE: { BASE = 0x4f000 } RB_COPY_DEST_PITCH: { PITCH = 256 } RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_IF_ALPHA_OFF | COMPONENT_ENABLE = 0 | ENDIAN = ENDIAN_NONE | TILE = TILE4_3 } 00054d00: 0000: 000320fc 00000f22 0004f000 00000008 03000868 t0 write GRAS_SC_SCREEN_SCISSOR_TL (207c) GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } 00054d14: 0000: 0001207c 00000000 003f003f t0 write RB_FRAME_BUFFER_DIMENSION (0ce0) RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } 00054d20: 0000: 00000ce0 00400040 t0 write 0xce1 (0ce1) 0xce1: 00000000 00054d28: 0000: 00000ce1 00000000 t3 opcode: CP_LOAD_STATE4 (30) (11 dwords) { DST_OFF = 8 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } 00054d3c: 0.000000 0.000000 1.000000 1.000000 64.000000 64.000000 1.000000 1.000000 00054d3c: 0000: 00000000 00000000 3f800000 3f800000 42800000 42800000 3f800000 3f800000 00054d30: 0000: c0093000 00a00008 00000001 00000000 00000000 3f800000 3f800000 42800000 00054d50: 0020: 42800000 3f800000 3f800000 t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x80000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 2 } draw[15] register values + 00000004 UNKNOWN_0CC5: 0x4 + 00000000 UNKNOWN_0CC6: 0 + 00400040 RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } + 00000000 0xce1: 00000000 + 00000002 HLSQ_MODE_CONTROL: 0x2 + 00000000 UNKNOWN_0E42: 0 + 00000000 UCHE_INVALIDATE0: 0 + 00000012 UCHE_INVALIDATE1: 0x12 + 00000004 SP_MODE_CONTROL: 0x4 + 00000068 TPL1_TP_MODE_CONTROL: 0x68 + 00188000 GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } + 00000000 UNKNOWN_2001: 0 + 00000001 GRAS_CNTL: { IJ_PERSP } !+ 00000002 GRAS_ALPHA_CONTROL: { 0x2 } + 00000000 GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } !+ 00000a08 GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = 4 | MSAA_DISABLE | RASTER_MODE = 0 } + 00000000 GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } + 003f003f GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } + 003f003f GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } + 00000000 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } !+ 00010202 RB_MODE_CONTROL: { WIDTH = 64 | HEIGHT = 64 | ENABLE_GMEM } !+ 00000022 RB_RENDER_CONTROL: { DISABLE_COLOR_PIPE | 0x2 } !+ 00009000 RB_MSAA_CONTROL: { DISABLE | SAMPLES = 4 } + ff000000 RB_CLEAR_COLOR_DW0: 0xff000000 + 00000000 RB_CLEAR_COLOR_DW1: 0 + 00000000 RB_CLEAR_COLOR_DW2: 0 + 00000000 RB_CLEAR_COLOR_DW3: 0 + 00000e00 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } + 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } !+ 00000f22 RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_FOUR | MODE = RB_COPY_CLEAR | FASTCLEAR = 0xf | GMEM_BASE = 0 } + 0004f000 RB_COPY_DEST_BASE: { BASE = 0x4f000 } + 00000008 RB_COPY_DEST_PITCH: { PITCH = 256 } !+ 03000868 RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_IF_ALPHA_OFF | COMPONENT_ENABLE = 0 | ENDIAN = ENDIAN_NONE | TILE = TILE4_3 } + 00000000 RB_BIN_OFFSET: { X = 0 | Y = 0 } !+ 40001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | 0x40000000 } !+ 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } + 00000000 UNKNOWN_2152: 0 + 00000000 UNKNOWN_2153: 0 + 00000000 UNKNOWN_2154: 0 + 00000000 UNKNOWN_2155: 0 + 00000000 UNKNOWN_2156: 0 + 00000001 UNKNOWN_2157: 0x1 + 0000001d UNKNOWN_21C3: 0x1d + 00000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 } + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + 00000000 PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } + 00000001 UNKNOWN_21E6: 0x1 + 000a0000 VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } + fc030000 VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } + fcfcfcfc VFD_CONTROL_2: 0xfcfcfcfc + fcfcfc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } + 0000fcfc VFD_CONTROL_4: 0xfcfc + 00000000 VFD_INDEX_OFFSET: 0 + 00000000 UNKNOWN_2209: 0 + 00060010 SP_SP_CTRL_REG: { 0x60010 } + 000005c3 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } + 00200c10 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } + 01000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } !+ 0010fc03 SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } !+ 00001e03 SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00fcfc00 UNKNOWN_22D7: 0xfcfc00 !+ 00000008 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } + 00000001 SP_VS_OBJ_START: 0x1 + 00000002 SP_VS_LENGTH_REG: 2 + 00000000 TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } + 00000003 TPL1_TP_FS_TEX_COUNT: 0x3 + 080004f0 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } + fcfc0120 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } + 27f3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } + 02010042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } !+ 0041423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00004200 HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } + 00000007 HLSQ_UPDATE_CONTROL: 0x7 00054d5c: 0000: c0023800 00080888 00000001 00000002 0016b07c: 0000: c0013f00 00054994 000000f6 t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:00054d6c ibsize:00000037 t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } 00054d6c: 0000: 00002200 082a0008 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00054d74: 0000: c0002600 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x1e 00054d7c: 0000: 00000ec3 0000001e t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x28 00054d84: 0000: 00000f03 00000028 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00054d8c: 0000: c0002600 00000000 t0 write HLSQ_MODE_CONTROL (0e05) HLSQ_MODE_CONTROL: 0x1 00054d94: 0000: 00000e05 00000001 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0x600a0 } 00054d9c: 0000: 000023c0 080604f0 t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x7 00054da4: 0000: 000023db 00000007 t0 write PC_RESTART_INDEX (21c6) PC_RESTART_INDEX: 0xffffffff 00054dac: 0000: 000021c6 ffffffff t0 write UNKNOWN_21E6 (21e6) UNKNOWN_21E6: 0x1 00054db4: 0000: 000021e6 00000001 t0 write UNKNOWN_21C3 (21c3) UNKNOWN_21C3: 0x1f 00054dbc: 0000: 000021c3 0000001f t0 write TPL1_TP_TEX_OFFSET (2380) TPL1_TP_TEX_OFFSET: 0x808 00054dc4: 0000: 00002380 00000808 t0 write GRAS_SU_POINT_MINMAX (2070) GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 4092.000000 } GRAS_SU_POINT_SIZE: 0.500000 00054dcc: 0000: 00012070 ffc00010 00000008 t0 write UNKNOWN_2152 (2152) UNKNOWN_2152: 0 UNKNOWN_2153: 0 00054dd8: 0000: 00012152 00000000 00000000 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00054de4: 0000: c0002600 00000000 t0 write UNKNOWN_0CC5 (0cc5) UNKNOWN_0CC5: 0x4 00054dec: 0000: 00000cc5 00000004 t0 write 0xcc4 (0cc4) 0xcc4: 00000000 00054df4: 0000: 00000cc4 00000000 t0 write 0xd03 (0d03) 0xd03: 80200000 00054dfc: 0000: 00000d03 80200000 t0 write UNKNOWN_0EC2 (0ec2) UNKNOWN_0EC2: 0x40000 00054e04: 0000: 00000ec2 00040000 t0 write VPC_DEBUG_ECO_CONTROL (0e64) VPC_DEBUG_ECO_CONTROL: 0x100 00054e0c: 0000: 00000e64 00000100 t0 write UNKNOWN_0E42 (0e42) UNKNOWN_0E42: 0 00054e14: 0000: 00000e42 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x1e 00054e1c: 0000: 00000ec3 0000001e t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x28 00054e24: 0000: 00000f03 00000028 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 00054e2c: 0000: c0014300 00040000 00000000 t0 write VFD_INDEX_OFFSET (2208) VFD_INDEX_OFFSET: 0 00054e38: 0000: 00002208 00000000 t0 write UNKNOWN_2209 (2209) UNKNOWN_2209: 0 00054e40: 0000: 00002209 00000000 0016b088: 0000: c0013f00 00054d6c 00000037 t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:00055328 ibsize:000000ac t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x3 00055328: 0000: 000023db 00000003 t0 write SP_INSTR_CACHE_CTRL (22c1) SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } 00055330: 0000: 000022c1 000005c3 t0 write HLSQ_CONTROL_1_REG (23c1) HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x1008 } 00055338: 0000: 000023c1 fcfc1108 t0 write HLSQ_CONTROL_2_REG (23c2) HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 00055340: 0000: 000023c2 fff3f3f0 t0 write HLSQ_VS_CONTROL_REG (23c5) HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 2 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 1 } 00055348: 0000: 000023c5 01010002 t0 write HLSQ_HS_CONTROL_REG (23c7) HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 00055350: 0000: 000023c7 007e0200 t0 write HLSQ_DS_CONTROL_REG (23c8) HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 00055358: 0000: 000023c8 007e0200 t0 write HLSQ_GS_CONTROL_REG (23c9) HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 00055360: 0000: 000023c9 007e0200 t0 write HLSQ_FS_CONTROL_REG (23c6) HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 2 | CONSTOBJECTOFFSET = 2 | ENABLED | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 } 00055368: 0000: 000023c6 017f0202 t0 write SP_VS_OBJ_OFFSET_REG (22e0) SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 00055370: 0000: 000022e0 00000000 t0 write SP_HS_OBJ_OFFSET_REG (230d) SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } 00055378: 0000: 0000230d 7e020000 t0 write SP_DS_OBJ_OFFSET_REG (2334) SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } 00055380: 0000: 00002334 7e020000 t0 write SP_GS_OBJ_OFFSET_REG (235b) SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } 00055388: 0000: 0000235b 7e020000 t0 write SP_FS_OBJ_OFFSET_REG (22ea) SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } 00055390: 0000: 000022ea 7e020000 t0 write SP_VS_OBJ_START (22e1) SP_VS_OBJ_START: 0x49000 00049000: 0000: 00000000 13000000 00000000 00000000 00000000 00000000 00000000 00000000 * :0:0000:0000[13000000x_00000000x] (sy)end :0:0001:0001[00000000x_00000000x] nop :0:0002:0002[00000000x_00000000x] nop :0:0003:0003[00000000x_00000000x] nop :0:0004:0004[00000000x_00000000x] nop Stats: - shaderdb: 5 instr, 4 nops, 1 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 0 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 0 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) 00055398: 0000: 000022e1 00049000 t0 write SP_HS_OBJ_START (230e) SP_HS_OBJ_START: 0 000553a0: 0000: 0000230e 00000000 t0 write SP_DS_OBJ_START (2335) SP_DS_OBJ_START: 0 000553a8: 0000: 00002335 00000000 t0 write SP_GS_OBJ_START (235c) SP_GS_OBJ_START: 0 000553b0: 0000: 0000235c 00000000 t0 write SP_VS_LENGTH_REG (22e5) SP_VS_LENGTH_REG: 1 000553b8: 0000: 000022e5 00000001 t3 opcode: CP_LOAD_STATE4 (30) (3 dwords) { DST_OFF = 0 | STATE_SRC = SS4_INDIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 1 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0x49000 } :0:0000:0000[13000000x_00000000x] (sy)end :0:0001:0001[00000000x_00000000x] nop :0:0002:0002[00000000x_00000000x] nop :0:0003:0003[00000000x_00000000x] nop :0:0004:0004[00000000x_00000000x] nop Stats: - shaderdb: 5 instr, 4 nops, 1 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 0 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 0 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) 000553c0: 0000: c0013000 00620000 00049000 t0 write 0x2072 (2072) 0x2072: 00000000 000553cc: 0000: 00002072 00000000 t0 write UNKNOWN_2155 (2155) UNKNOWN_2155: 0 000553d4: 0000: 00002155 00000000 t0 write GRAS_CNTL (2003) GRAS_CNTL: { IJ_PERSP } 000553dc: 0000: 00002003 00000001 t0 write VPC_VARYING_INTERP[0].MODE (2142) VPC_VARYING_INTERP[0].MODE: 0 000553e4: 0000: 00002142 00000000 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0x600a0 } 000553ec: 0000: 000023c0 080604f0 t0 write HLSQ_CONTROL_3_REG (23c3) HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } 000553f4: 0000: 000023c3 fcfcfc00 t0 write HLSQ_CONTROL_4_REG (23c4) HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r0.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } 000553fc: 0000: 000023c4 00fcfc00 t0 write SP_FS_CTRL_REG0 (22e8) SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE } SP_FS_CTRL_REG1: { CONSTLENGTH = 2 | VARYING | 0x80000000 } 00055404: 0000: 000122e8 00340412 80100002 t0 write SP_FS_OBJ_START (22eb) SP_FS_OBJ_START: 0x46000 00046000: 0000: 00002000 5730cb00 00000000 03000000 00000000 00000000 00000000 00000000 * :2:0000:0000[5730cb00x_00002000x] (sy)(rpt3)bary.f (ei)hr0.x, (r)0, r0.x :0:0001:0004[03000000x_00000000x] end :0:0002:0005[00000000x_00000000x] nop :0:0003:0006[00000000x_00000000x] nop :0:0004:0007[00000000x_00000000x] nop :0:0005:0008[00000000x_00000000x] nop Stats: - shaderdb: 9 instr, 4 nops, 5 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 1 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 4 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) 00055410: 0000: 000022eb 00046000 t0 write SP_FS_LENGTH_REG (22ef) SP_FS_LENGTH_REG: 1 00055418: 0000: 000022ef 00000001 t0 write RB_RENDER_COMPONENTS (20fb) RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } 00055420: 0000: 000020fb 0000000f t3 opcode: CP_LOAD_STATE4 (30) (3 dwords) { DST_OFF = 0 | STATE_SRC = SS4_INDIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 1 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0x46000 } :2:0000:0000[5730cb00x_00002000x] (sy)(rpt3)bary.f (ei)hr0.x, (r)0, r0.x :0:0001:0004[03000000x_00000000x] end :0:0002:0005[00000000x_00000000x] nop :0:0003:0006[00000000x_00000000x] nop :0:0004:0007[00000000x_00000000x] nop :0:0005:0008[00000000x_00000000x] nop Stats: - shaderdb: 9 instr, 4 nops, 5 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 1 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 4 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) 00055428: 0000: c0013000 00720000 00046000 t0 write SP_SP_CTRL_REG (22c0) SP_SP_CTRL_REG: { 0x60010 } 00055434: 0000: 000022c0 00060010 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 28 | GROUP_ID = 3 } { ADDR_LO = 0x99b10 } 0005543c: 0000: c0014300 0300001c 00099b10 t0 write RB_DEPTH_INFO (2103) RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTH4_NONE | DEPTH_BASE = 0 } RB_DEPTH_PITCH: 0 RB_DEPTH_PITCH2: 0 00055448: 0000: 00022103 00000000 00000000 00000000 t0 write GRAS_DEPTH_CONTROL (2077) GRAS_DEPTH_CONTROL: { FORMAT = DEPTH4_NONE } 00055458: 0000: 00002077 00000000 t0 write RB_STENCIL_INFO (2108) RB_STENCIL_INFO: { STENCIL_BASE = 0 } RB_STENCIL_PITCH: 0 0x210a: 00000000 00055460: 0000: 00022108 00000000 00000000 00000000 t0 write 0x2002 (2002) 0x2002: 00000000 00055470: 0000: 00002002 00000000 t0 write RB_ALPHA_CONTROL (20f8) RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } 00055478: 0000: 000020f8 00000e00 t0 write RB_MRT[0].CONTROL (20a4) RB_MRT[0].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0x7 } 00055480: 0000: 000020a4 07000c00 t0 write RB_MRT[0].BLEND_CONTROL (20a8) RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } 00055488: 0000: 000020a8 00000000 t0 write GRAS_CL_CLIP_CNTL (2000) GRAS_CL_CLIP_CNTL: { 0x80000 } 00055490: 0000: 00002000 00080000 t0 write GRAS_SU_POLY_OFFSET_SCALE (2074) GRAS_SU_POLY_OFFSET_SCALE: 0.000000 GRAS_SU_POLY_OFFSET_OFFSET: 0.000000 GRAS_SU_POLY_OFFSET_CLAMP: 0.000000 00055498: 0000: 00022074 00000000 00000000 00000000 t0 write GRAS_SU_MODE_CONTROL (2078) GRAS_SU_MODE_CONTROL: { FRONT_CW | LINEHALFWIDTH = 0.500000 | MSAA_ENABLE | RENDERING_PASS } 000554a8: 0000: 00002078 00102014 t0 write GRAS_SC_SCREEN_SCISSOR_TL (207c) GRAS_SC_SCREEN_SCISSOR_TL: { X = 2 | Y = 13 } GRAS_SC_SCREEN_SCISSOR_BR: { X = 33 | Y = 44 } 000554b0: 0000: 0001207c 000d0002 002c0021 t0 write GRAS_CL_VPORT_XOFFSET_0 (2008) GRAS_CL_VPORT_XOFFSET_0: 18.000000 GRAS_CL_VPORT_XSCALE_0: 16.000000 GRAS_CL_VPORT_YOFFSET_0: 29.000000 GRAS_CL_VPORT_YSCALE_0: 16.000000 GRAS_CL_VPORT_ZOFFSET_0: 0.500000 GRAS_CL_VPORT_ZSCALE_0: 0.500000 000554bc: 0000: 00052008 41900000 41800000 41e80000 41800000 3f000000 3f000000 t0 write GRAS_CL_GB_CLIP_ADJ (2004) GRAS_CL_GB_CLIP_ADJ: { HORZ = 511 | VERT = 511 } 000554d8: 0000: 00002004 0007fdff t0 write GRAS_SC_CONTROL (207b) GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 4 | RASTER_MODE = 0 } 000554e0: 0000: 0000207b 00000200 t0 write 0x2382 (2382) 0x2382: 00000002 000554e8: 0000: 00002382 00000002 t0 write RB_MSAA_CONTROL (20a2) RB_MSAA_CONTROL: { SAMPLES = 4 } 000554f0: 0000: 000020a2 00008000 t0 write RB_RENDER_CONTROL2 (20a3) RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 4 | IJ_PERSP_PIXEL } 000554f8: 0000: 000020a3 00001200 t0 write RB_MRT[0].BUF_INFO (20a5) RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB4_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_ALWAYS | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 1024 } RB_MRT[0].BASE: 0 RB_MRT[0].CONTROL3: { STRIDE = 64 } 00055500: 0000: 000220a5 0010029a 00000000 00000200 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 43 | GROUP_ID = 2 } { ADDR_LO = 0x99b80 } 00055510: 0000: c0014300 0200002b 00099b80 t0 write 0x215c (215c) 0x215c: 00000000 0x215d: 00000000 0005551c: 0000: 0001215c 00000000 00000000 t0 write 0x215f (215f) 0x215f: 00000000 00055528: 0000: 0000215f 00000000 t0 write 0x215e (215e) 0x215e: 00000000 00055530: 0000: 0000215e 00000000 t0 write 0x2161 (2161) 0x2161: 00000000 0x2162: 00000000 00055538: 0000: 00012161 00000000 00000000 t0 write 0x2164 (2164) 0x2164: 00000000 00055544: 0000: 00002164 00000000 t0 write 0x2163 (2163) 0x2163: 00000000 0005554c: 0000: 00002163 00000000 t0 write 0x2166 (2166) 0x2166: 00000000 0x2167: 00000000 00055554: 0000: 00012166 00000000 00000000 t0 write 0x2169 (2169) 0x2169: 00000000 00055560: 0000: 00002169 00000000 t0 write 0x2168 (2168) 0x2168: 00000000 00055568: 0000: 00002168 00000000 t0 write 0x216b (216b) 0x216b: 00000000 0x216c: 00000000 00055570: 0000: 0001216b 00000000 00000000 t0 write VPC_SO_FLUSH_WADDR_3 (216e) VPC_SO_FLUSH_WADDR_3: 0 0005557c: 0000: 0000216e 00000000 t0 write 0x216d (216d) 0x216d: 00000000 00055584: 0000: 0000216d 00000000 t0 write UNKNOWN_2156 (2156) UNKNOWN_2156: 0 0005558c: 0000: 00002156 00000000 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 18 | GROUP_ID = 1 } { ADDR_LO = 0x99c30 } 00055594: 0000: c0014300 01000012 00099c30 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 15 | GROUP_ID = 0 } { ADDR_LO = 0x99c80 } 000555a0: 0000: c0014300 0000000f 00099c80 group_id: 0 count: 15 addr: 0000000000099c80 flags: 0 00099c80: 0000: 00002073 00000000 00002101 00000000 00002106 00000000 000021e5 00000000 00099ca0: 0020: 0001210b 00000000 00000000 00002381 00000000 000023a0 00000000 t0 write GRAS_ALPHA_CONTROL (2073) GRAS_ALPHA_CONTROL: { 0 } 00099c80: 0000: 00002073 00000000 t0 write RB_DEPTH_CONTROL (2101) RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } 00099c88: 0000: 00002101 00000000 t0 write RB_STENCIL_CONTROL (2106) RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } 00099c90: 0000: 00002106 00000000 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 00099c98: 0000: 000021e5 00000000 t0 write RB_STENCILREFMASK (210b) RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 00099ca0: 0000: 0001210b 00000000 00000000 t0 write TPL1_TP_TEX_COUNT (2381) TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } 00099cac: 0000: 00002381 00000000 t0 write TPL1_TP_FS_TEX_COUNT (23a0) TPL1_TP_FS_TEX_COUNT: 0 00099cb4: 0000: 000023a0 00000000 group_id: 1 count: 18 addr: 0000000000099c30 flags: 0 00099c30: 0000: 00002200 082a0008 00002201 fcfc0081 00002203 0000fc00 0007220a 0008080f 00099c50: 0020: 00099ab0 00000060 00000001 0000080f 00099ae0 00000030 00000001 0001228a 00099c70: 0040: 7000411f 3000011f t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } 00099c30: 0000: 00002200 082a0008 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } 00099c38: 0000: 00002201 fcfc0081 t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } 00099c40: 0000: 00002203 0000fc00 t0 write VFD_FETCH[0].INSTR_0 (220a) VFD_FETCH[0].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 | SWITCHNEXT } VFD_FETCH[0].INSTR_1: 0x99ab0 VFD_FETCH[0].INSTR_2: { SIZE = 0x60 } VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 } VFD_FETCH[0x1].INSTR_1: 0x99ae0 VFD_FETCH[0x1].INSTR_2: { SIZE = 0x30 } VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } 00099c48: 0000: 0007220a 0008080f 00099ab0 00000060 00000001 0000080f 00099ae0 00000030 00099c68: 0020: 00000001 t0 write VFD_DECODE[0].INSTR (228a) VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID | SWITCHNEXT } VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID } 00099c6c: 0000: 0001228a 7000411f 3000011f group_id: 2 count: 43 addr: 0000000000099b80 flags: 0 00099b80: 0000: 000020a1 00000000 000022f1 0001a100 000022f0 fc00fc01 00002100 00000001 00099ba0: 0020: 000021e5 00000000 000020f9 ffff0501 0000214a 00000000 00002140 42001004 00099bc0: 0040: 001922c6 0010fc04 00001e00 00000000 00000000 00000000 00000000 00000000 * 00099c00: 0080: 00000000 00000000 00fcfc00 00000008 00000000 00000000 00000000 00000000 * t0 write RB_RENDER_CONTROL (20a1) RB_RENDER_CONTROL: { 0 } 00099b80: 0000: 000020a1 00000000 t0 write SP_FS_MRT[0].REG (22f1) SP_FS_MRT[0].REG: { REGID = r0.x | HALF_PRECISION | MRTFORMAT = RB4_R8G8B8A8_UNORM } 00099b88: 0000: 000022f1 0001a100 t0 write SP_FS_OUTPUT_REG (22f0) SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 00099b90: 0000: 000022f0 fc00fc01 t0 write RB_FS_OUTPUT_REG (2100) RB_FS_OUTPUT_REG: { MRT = 1 } 00099b98: 0000: 00002100 00000001 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 00099ba0: 0000: 000021e5 00000000 t0 write RB_FS_OUTPUT (20f9) RB_FS_OUTPUT: { ENABLE_BLEND = 0x1 | INDEPENDENT_BLEND | SAMPLE_MASK = 0xffff | 0x400 } 00099ba8: 0000: 000020f9 ffff0501 t0 write VPC_VARYING_PS_REPL[0].MODE (214a) VPC_VARYING_PS_REPL[0].MODE: 0 00099bb0: 0000: 0000214a 00000000 t0 write VPC_ATTR (2140) VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 } 00099bb8: 0000: 00002140 42001004 t0 write SP_VS_PARAM_REG (22c6) SP_VS_PARAM_REG: { POSREGID = r1.x | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } SP_VS_OUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } UNKNOWN_22D7: 0xfcfc00 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 00099bc0: 0000: 001922c6 0010fc04 00001e00 00000000 00000000 00000000 00000000 00000000 * 00099c00: 0040: 00000000 00000000 00fcfc00 00000008 00000000 00000000 00000000 00000000 * group_id: 3 count: 28 addr: 0000000000099b10 flags: 0 00099b10: 0000: 000021c4 02000001 00002141 00040400 00002001 00000000 000022c4 00200800 00099b30: 0020: 000022c5 08000002 0000230c 00000000 00002318 00000000 00002319 00000000 00099b50: 0040: 00002340 00000000 00002202 fcfcfcfc 00002204 0000fcfc 00002154 00000000 00099b70: 0060: 000021e7 00000000 000021c5 00000012 t0 write PC_PRIM_VTX_CNTL (21c4) PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } 00099b10: 0000: 000021c4 02000001 t0 write VPC_PACK (2141) VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } 00099b18: 0000: 00002141 00040400 t0 write UNKNOWN_2001 (2001) UNKNOWN_2001: 0 00099b20: 0000: 00002001 00000000 t0 write SP_VS_CTRL_REG0 (22c4) SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 2 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 00099b28: 0000: 000022c4 00200800 t0 write SP_VS_CTRL_REG1 (22c5) SP_VS_CTRL_REG1: { CONSTLENGTH = 2 | INITIALOUTSTANDING = 8 } 00099b30: 0000: 000022c5 08000002 t0 write 0x230c (230c) 0x230c: 00000000 00099b38: 0000: 0000230c 00000000 t0 write 0x2318 (2318) 0x2318: 00000000 00099b40: 0000: 00002318 00000000 t0 write 0x2319 (2319) 0x2319: 00000000 00099b48: 0000: 00002319 00000000 t0 write 0x2340 (2340) 0x2340: 00000000 00099b50: 0000: 00002340 00000000 t0 write VFD_CONTROL_2 (2202) VFD_CONTROL_2: 0xfcfcfcfc 00099b58: 0000: 00002202 fcfcfcfc t0 write VFD_CONTROL_4 (2204) VFD_CONTROL_4: 0xfcfc 00099b60: 0000: 00002204 0000fcfc t0 write UNKNOWN_2154 (2154) UNKNOWN_2154: 0 00099b68: 0000: 00002154 00000000 t0 write PC_HS_PARAM (21e7) PC_HS_PARAM: { VERTICES_OUT = 0 | SPACING = EQUAL_SPACING } 00099b70: 0000: 000021e7 00000000 t0 write PC_PRIM_VTX_CNTL2 (21c5) PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 00099b78: 0000: 000021c5 00000012 t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = USE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x200000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 3 } draw[16] register values + 00000000 0xcc4: 00000000 + 00000004 UNKNOWN_0CC5: 0x4 + 80200000 0xd03: 80200000 !+ 00000001 HLSQ_MODE_CONTROL: 0x1 + 00000000 UNKNOWN_0E42: 0 + 00000100 VPC_DEBUG_ECO_CONTROL: 0x100 + 00040000 UNKNOWN_0EC2: 0x40000 !+ 0000001e SP_MODE_CONTROL: 0x1e !+ 00000028 TPL1_TP_MODE_CONTROL: 0x28 !+ 00080000 GRAS_CL_CLIP_CNTL: { 0x80000 } + 00000000 UNKNOWN_2001: 0 + 00000000 0x2002: 00000000 + 00000001 GRAS_CNTL: { IJ_PERSP } + 0007fdff GRAS_CL_GB_CLIP_ADJ: { HORZ = 511 | VERT = 511 } + 41900000 GRAS_CL_VPORT_XOFFSET_0: 18.000000 + 41800000 GRAS_CL_VPORT_XSCALE_0: 16.000000 + 41e80000 GRAS_CL_VPORT_YOFFSET_0: 29.000000 + 41800000 GRAS_CL_VPORT_YSCALE_0: 16.000000 + 3f000000 GRAS_CL_VPORT_ZOFFSET_0: 0.500000 + 3f000000 GRAS_CL_VPORT_ZSCALE_0: 0.500000 + ffc00010 GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 4092.000000 } + 00000008 GRAS_SU_POINT_SIZE: 0.500000 + 00000000 0x2072: 00000000 !+ 00000000 GRAS_ALPHA_CONTROL: { 0 } + 00000000 GRAS_SU_POLY_OFFSET_SCALE: 0.000000 + 00000000 GRAS_SU_POLY_OFFSET_OFFSET: 0.000000 + 00000000 GRAS_SU_POLY_OFFSET_CLAMP: 0.000000 + 00000000 GRAS_DEPTH_CONTROL: { FORMAT = DEPTH4_NONE } !+ 00102014 GRAS_SU_MODE_CONTROL: { FRONT_CW | LINEHALFWIDTH = 0.500000 | MSAA_ENABLE | RENDERING_PASS } !+ 00000200 GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 4 | RASTER_MODE = 0 } !+ 000d0002 GRAS_SC_SCREEN_SCISSOR_TL: { X = 2 | Y = 13 } !+ 002c0021 GRAS_SC_SCREEN_SCISSOR_BR: { X = 33 | Y = 44 } !+ 00000000 RB_RENDER_CONTROL: { 0 } !+ 00008000 RB_MSAA_CONTROL: { SAMPLES = 4 } !+ 00001200 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 4 | IJ_PERSP_PIXEL } !+ 07000c00 RB_MRT[0].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0x7 } !+ 0010029a RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB4_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_ALWAYS | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 1024 } !+ 00000000 RB_MRT[0].BASE: 0 !+ 00000200 RB_MRT[0].CONTROL3: { STRIDE = 64 } + 00000000 RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } + 00000e00 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } !+ ffff0501 RB_FS_OUTPUT: { ENABLE_BLEND = 0x1 | INDEPENDENT_BLEND | SAMPLE_MASK = 0xffff | 0x400 } + 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } + 00000001 RB_FS_OUTPUT_REG: { MRT = 1 } + 00000000 RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } + 00000000 RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTH4_NONE | DEPTH_BASE = 0 } + 00000000 RB_DEPTH_PITCH: 0 + 00000000 RB_DEPTH_PITCH2: 0 + 00000000 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } + 00000000 RB_STENCIL_INFO: { STENCIL_BASE = 0 } + 00000000 RB_STENCIL_PITCH: 0 + 00000000 0x210a: 00000000 + 00000000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } + 00000000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } !+ 42001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 } + 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } !+ 00000000 VPC_VARYING_INTERP[0].MODE: 0 !+ 00000000 VPC_VARYING_PS_REPL[0].MODE: 0 + 00000000 UNKNOWN_2152: 0 + 00000000 UNKNOWN_2153: 0 + 00000000 UNKNOWN_2154: 0 + 00000000 UNKNOWN_2155: 0 + 00000000 UNKNOWN_2156: 0 + 00000000 0x215c: 00000000 + 00000000 0x215d: 00000000 + 00000000 0x215e: 00000000 + 00000000 0x215f: 00000000 + 00000000 0x2161: 00000000 + 00000000 0x2162: 00000000 + 00000000 0x2163: 00000000 + 00000000 0x2164: 00000000 + 00000000 0x2166: 00000000 + 00000000 0x2167: 00000000 + 00000000 0x2168: 00000000 + 00000000 0x2169: 00000000 + 00000000 0x216b: 00000000 + 00000000 0x216c: 00000000 + 00000000 0x216d: 00000000 + 00000000 VPC_SO_FLUSH_WADDR_3: 0 !+ 0000001f UNKNOWN_21C3: 0x1f !+ 02000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + ffffffff PC_RESTART_INDEX: 0xffffffff + 00000000 PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } + 00000001 UNKNOWN_21E6: 0x1 + 00000000 PC_HS_PARAM: { VERTICES_OUT = 0 | SPACING = EQUAL_SPACING } !+ 082a0008 VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } !+ fcfc0081 VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } + fcfcfcfc VFD_CONTROL_2: 0xfcfcfcfc !+ 0000fc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } + 0000fcfc VFD_CONTROL_4: 0xfcfc + 00000000 VFD_INDEX_OFFSET: 0 + 00000000 UNKNOWN_2209: 0 + 0008080f VFD_FETCH[0].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 | SWITCHNEXT } !+ 00099ab0 VFD_FETCH[0].INSTR_1: 0x99ab0 + 00000060 VFD_FETCH[0].INSTR_2: { SIZE = 0x60 } + 00000001 VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } + 0000080f VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 } !+ 00099ae0 VFD_FETCH[0x1].INSTR_1: 0x99ae0 + 00000030 VFD_FETCH[0x1].INSTR_2: { SIZE = 0x30 } + 00000001 VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } + 7000411f VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID | SWITCHNEXT } + 3000011f VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID } + 00060010 SP_SP_CTRL_REG: { 0x60010 } + 000005c3 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } !+ 00200800 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 2 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } !+ 08000002 SP_VS_CTRL_REG1: { CONSTLENGTH = 2 | INITIALOUTSTANDING = 8 } !+ 0010fc04 SP_VS_PARAM_REG: { POSREGID = r1.x | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } !+ 00001e00 SP_VS_OUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00fcfc00 UNKNOWN_22D7: 0xfcfc00 + 00000008 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } !+ 00049000 SP_VS_OBJ_START: 0x49000 00049000: 0000: 00000000 13000000 00000000 00000000 00000000 00000000 00000000 00000000 * :0:0000:0000[13000000x_00000000x] (sy)end :0:0001:0001[00000000x_00000000x] nop :0:0002:0002[00000000x_00000000x] nop :0:0003:0003[00000000x_00000000x] nop :0:0004:0004[00000000x_00000000x] nop Stats: - shaderdb: 5 instr, 4 nops, 1 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 0 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 0 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) !+ 00000001 SP_VS_LENGTH_REG: 1 !+ 00340412 SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE } !+ 80100002 SP_FS_CTRL_REG1: { CONSTLENGTH = 2 | VARYING | 0x80000000 } !+ 7e020000 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } !+ 00046000 SP_FS_OBJ_START: 0x46000 00046000: 0000: 00002000 5730cb00 00000000 03000000 00000000 00000000 00000000 00000000 * :2:0000:0000[5730cb00x_00002000x] (sy)(rpt3)bary.f (ei)hr0.x, (r)0, r0.x :0:0001:0004[03000000x_00000000x] end :0:0002:0005[00000000x_00000000x] nop :0:0003:0006[00000000x_00000000x] nop :0:0004:0007[00000000x_00000000x] nop :0:0005:0008[00000000x_00000000x] nop Stats: - shaderdb: 9 instr, 4 nops, 5 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 1 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 4 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) + 00000001 SP_FS_LENGTH_REG: 1 !+ fc00fc01 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r63.x } !+ 0001a100 SP_FS_MRT[0].REG: { REGID = r0.x | HALF_PRECISION | MRTFORMAT = RB4_R8G8B8A8_UNORM } + 00000000 0x230c: 00000000 + 7e020000 SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } + 00000000 SP_HS_OBJ_START: 0 + 00000000 0x2318: 00000000 + 00000000 0x2319: 00000000 + 7e020000 SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } + 00000000 SP_DS_OBJ_START: 0 + 00000000 0x2340: 00000000 + 7e020000 SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } + 00000000 SP_GS_OBJ_START: 0 + 00000808 TPL1_TP_TEX_OFFSET: 0x808 + 00000000 TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } !+ 00000002 0x2382: 00000002 !+ 00000000 TPL1_TP_FS_TEX_COUNT: 0 !+ 080604f0 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0x600a0 } !+ fcfc1108 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x1008 } !+ fff3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } + fcfcfc00 HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } !+ 00fcfc00 HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r0.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } !+ 01010002 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 2 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 1 } !+ 017f0202 HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 2 | CONSTOBJECTOFFSET = 2 | ENABLED | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 } !+ 007e0200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } !+ 007e0200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } !+ 007e0200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } !+ 00000003 HLSQ_UPDATE_CONTROL: 0x3 000555ac: 0000: c0023800 00200984 00000001 00000003 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 18 | GROUP_ID = 1 } { ADDR_LO = 0x99df0 } 000555bc: 0000: c0014300 01000012 00099df0 group_id: 1 count: 18 addr: 0000000000099df0 flags: 0 00099df0: 0000: 00002200 082a0008 00002201 fcfc0081 00002203 0000fc00 0007220a 0008080f 00099e10: 0020: 00099d90 00000060 00000001 0000080f 00099dc0 00000030 00000001 0001228a 00099e30: 0040: 7000411f 3000011f t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } 00099df0: 0000: 00002200 082a0008 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } 00099df8: 0000: 00002201 fcfc0081 t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } 00099e00: 0000: 00002203 0000fc00 t0 write VFD_FETCH[0].INSTR_0 (220a) VFD_FETCH[0].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 | SWITCHNEXT } VFD_FETCH[0].INSTR_1: 0x99d90 VFD_FETCH[0].INSTR_2: { SIZE = 0x60 } VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 } VFD_FETCH[0x1].INSTR_1: 0x99dc0 VFD_FETCH[0x1].INSTR_2: { SIZE = 0x30 } VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } 00099e08: 0000: 0007220a 0008080f 00099d90 00000060 00000001 0000080f 00099dc0 00000030 00099e28: 0020: 00000001 t0 write VFD_DECODE[0].INSTR (228a) VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID | SWITCHNEXT } VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID } 00099e2c: 0000: 0001228a 7000411f 3000011f t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = USE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x200000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 3 } draw[17] register values + 082a0008 VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } + fcfc0081 VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } + 0000fc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } + 0008080f VFD_FETCH[0].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 | SWITCHNEXT } !+ 00099d90 VFD_FETCH[0].INSTR_1: 0x99d90 + 00000060 VFD_FETCH[0].INSTR_2: { SIZE = 0x60 } + 00000001 VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } + 0000080f VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 } !+ 00099dc0 VFD_FETCH[0x1].INSTR_1: 0x99dc0 + 00000030 VFD_FETCH[0x1].INSTR_2: { SIZE = 0x30 } + 00000001 VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } + 7000411f VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID | SWITCHNEXT } + 3000011f VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID } 000555c8: 0000: c0023800 00200984 00000001 00000003 0016b094: 0000: c0013f00 00055328 000000ac t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 0016b0a0: 0000: c0014300 00040000 00000000 t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:00170b94 ibsize:000000f7 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00170b94: 0000: c0002600 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x4 00170b9c: 0000: 00000ec3 00000004 t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x68 00170ba4: 0000: 00000f03 00000068 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00170bac: 0000: c0002600 00000000 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } 00170bb4: 0000: 000023c0 080004f0 t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = 0x1d } event (null) 00170bbc: 0000: c0004600 0000001d t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = FACENESS_FLUSH } event FACENESS_FLUSH 00170bc4: 0000: c0004600 0000001c t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00170bcc: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0 00170bd4: 0000: 00000cc6 00000000 t0 write UNKNOWN_0E42 (0e42) UNKNOWN_0E42: 0 00170bdc: 0000: 00000e42 00000000 t0 write HLSQ_MODE_CONTROL (0e05) HLSQ_MODE_CONTROL: 0x2 00170be4: 0000: 00000e05 00000002 t0 write UNKNOWN_0CC5 (0cc5) UNKNOWN_0CC5: 0x4 00170bec: 0000: 00000cc5 00000004 t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x7 00170bf4: 0000: 000023db 00000007 t0 write VFD_CONTROL_2 (2202) VFD_CONTROL_2: 0xfcfcfcfc 00170bfc: 0000: 00002202 fcfcfcfc t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } 00170c04: 0000: 00002203 fcfcfc00 t0 write VFD_CONTROL_4 (2204) VFD_CONTROL_4: 0xfcfc 00170c0c: 0000: 00002204 0000fcfc t0 write VFD_INDEX_OFFSET (2208) VFD_INDEX_OFFSET: 0 00170c14: 0000: 00002208 00000000 t0 write UNKNOWN_2209 (2209) UNKNOWN_2209: 0 00170c1c: 0000: 00002209 00000000 t0 write UNKNOWN_2152 (2152) UNKNOWN_2152: 0 UNKNOWN_2153: 0 00170c24: 0000: 00012152 00000000 00000000 t0 write UNKNOWN_2156 (2156) UNKNOWN_2156: 0 00170c30: 0000: 00002156 00000000 t0 write UNKNOWN_2154 (2154) UNKNOWN_2154: 0 00170c38: 0000: 00002154 00000000 t0 write UNKNOWN_2155 (2155) UNKNOWN_2155: 0 00170c40: 0000: 00002155 00000000 t0 write UNKNOWN_21C3 (21c3) UNKNOWN_21C3: 0x1d 00170c48: 0000: 000021c3 0000001d t0 write PC_PRIM_VTX_CNTL2 (21c5) PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 00170c50: 0000: 000021c5 00000012 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 00170c58: 0000: 000021e5 00000000 t0 write GRAS_SU_MODE_CONTROL (2078) GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } 00170c60: 0000: 00002078 00000000 t0 write UNKNOWN_2001 (2001) UNKNOWN_2001: 0 00170c68: 0000: 00002001 00000000 t0 write GRAS_CNTL (2003) GRAS_CNTL: { IJ_PERSP } 00170c70: 0000: 00002003 00000001 t0 write GRAS_CL_CLIP_CNTL (2000) GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } 00170c78: 0000: 00002000 00188000 t0 write TPL1_TP_TEX_COUNT (2381) TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } 00170c80: 0000: 00002381 00000000 t0 write TPL1_TP_FS_TEX_COUNT (23a0) TPL1_TP_FS_TEX_COUNT: 0x3 00170c88: 0000: 000023a0 00000003 t0 write RB_ALPHA_CONTROL (20f8) RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } 00170c90: 0000: 000020f8 00000e00 t0 write RB_RENDER_COMPONENTS (20fb) RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } 00170c98: 0000: 000020fb 0000000f t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 00170ca0: 0000: c0014300 00040000 00000000 t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } 00170cac: 0000: 00002200 000a0000 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } 00170cb4: 0000: 00002201 fc030000 t0 write SP_INSTR_CACHE_CTRL (22c1) SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } 00170cbc: 0000: 000022c1 000005c3 t0 write HLSQ_CONTROL_1_REG (23c1) HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } 00170cc4: 0000: 000023c1 fcfc0120 t0 write HLSQ_CONTROL_2_REG (23c2) HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 00170ccc: 0000: 000023c2 27f3f3f0 t0 write HLSQ_VS_CONTROL_REG (23c5) HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } 00170cd4: 0000: 000023c5 02010042 t0 write HLSQ_FS_CONTROL_REG (23c6) HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00170cdc: 0000: 000023c6 0041423e t0 write HLSQ_HS_CONTROL_REG (23c7) HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00170ce4: 0000: 000023c7 00404200 t0 write HLSQ_DS_CONTROL_REG (23c8) HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00170cec: 0000: 000023c8 00404200 t0 write HLSQ_GS_CONTROL_REG (23c9) HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00170cf4: 0000: 000023c9 00404200 t0 write HLSQ_CS_CONTROL_REG (23ca) HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } 00170cfc: 0000: 000023ca 00004200 t0 write SP_SP_CTRL_REG (22c0) SP_SP_CTRL_REG: { 0x60010 } 00170d04: 0000: 000022c0 00060010 t0 write UNKNOWN_21E6 (21e6) UNKNOWN_21E6: 0x1 00170d0c: 0000: 000021e6 00000001 t0 write SP_VS_CTRL_REG0 (22c4) SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 00170d14: 0000: 000022c4 00200c10 t0 write SP_VS_CTRL_REG1 (22c5) SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } 00170d1c: 0000: 000022c5 01000042 t0 write VPC_ATTR (2140) VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | 0x40000000 } 00170d24: 0000: 00002140 40001004 t0 write VPC_PACK (2141) VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } 00170d2c: 0000: 00002141 00040400 t0 write PC_PRIM_VTX_CNTL (21c4) PC_PRIM_VTX_CNTL: { VAROUT = 1 } 00170d34: 0000: 000021c4 00000001 t0 write SP_VS_PARAM_REG (22c6) SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } UNKNOWN_22D7: 0xfcfc00 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 00170d3c: 0000: 001922c6 0010fc03 00001e03 00000000 00000000 00000000 00000000 00000000 * 00170d7c: 0040: 00000000 00000000 00fcfc00 00000008 00000000 00000000 00000000 00000000 * t0 write SP_VS_OBJ_OFFSET_REG (22e0) SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 00170da8: 0000: 000022e0 00000000 t0 write SP_VS_OBJ_START (22e1) SP_VS_OBJ_START: 0x1 00170db0: 0000: 000022e1 00000001 t0 write SP_VS_LENGTH_REG (22e5) SP_VS_LENGTH_REG: 2 00170db8: 0000: 000022e5 00000002 t3 opcode: CP_LOAD_STATE4 (30) (67 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } :2:0000:0000[56d81803x_20020003x] (sy)(ss)(nop3) shl.b r0.w, r0.w, 2 :1:0001:0004[20150000x_00000003x] cov.s32s16 hr0.x, r0.w :0:0002:0005[00000200x_00000000x] (rpt2)nop :1:0003:0008[201100f4x_00000000x] mova a0.x, hr0.x :0:0004:0009[00000500x_00000000x] (rpt5)nop :1:0005:0015[20154003x_00000c20x] mov.s32s32 r0.w, c :1:0006:0016[20154004x_00000c21x] mov.s32s32 r1.x, c :1:0007:0017[20154005x_00000c22x] mov.s32s32 r1.y, c :1:0008:0018[20156006x_00000c23x] (ul)mov.s32s32 r1.z, c :0:0009:0019[03000000x_00000000x] end :2:0010:0020[46f00007x_20050000x] shr.b r1.w, r0.x, 5 :2:0011:0021[43980008x_201f0000x] (nop2) and.b r2.x, r0.x, 31 :2:0012:0024[43980807x_201f0007x] (nop3) and.b r1.w, r1.w, 31 :2:0013:0028[46100807x_20100007x] (nop1) mul.u24 r1.w, r1.w, 16 :3:0014:0030[62040007x_00071014x] mad.u24 r1.w, c5.x, r2.x, r1.w :0:0015:0031[00000500x_00000000x] (rpt5)nop :6:0016:0037[c2c60f00x_04800006x] stlw.u32 l[r1.w], r0.w, 4 :0:0017:0038[04800000x_00000000x] chmask :0:0018:0039[05000000x_00000000x] chsh Stats: - shaderdb: 40 instr, 24 nops, 16 non-nops, 5 mov, 1 cov - shaderdb: 0 last-baryf, 0 half, 2 full, 5 constlen - shaderdb: 27 cat0, 6 cat1, 5 cat2, 1 cat3, 0 cat4, 0 cat5, 1 cat6, 0 cat7 - shaderdb: 0 sstall, 1 (ss), 1 (sy) 00170dc0: 0000: c0413000 00a00000 00000000 20020003 56d81803 00000003 20150000 00000000 00170de0: 0020: 00000200 00000000 201100f4 00000000 00000500 00000c20 20154003 00000c21 00170e00: 0040: 20154004 00000c22 20154005 00000c23 20156006 00000000 03000000 20050000 00170e20: 0060: 46f00007 201f0000 43980008 201f0007 43980807 20100007 46100807 00071014 00170e40: 0080: 62040007 00000000 00000500 04800006 c2c60f00 00000000 04800000 00000000 00170e60: 00a0: 05000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 * t0 write GRAS_SC_CONTROL (207b) GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = 0 | MSAA_DISABLE | RASTER_MODE = 0 } 00170ecc: 0000: 0000207b 00000808 t0 write RB_MSAA_CONTROL (20a2) RB_MSAA_CONTROL: { DISABLE | SAMPLES = 0 } 00170ed4: 0000: 000020a2 00001000 t0 write RB_RENDER_CONTROL (20a1) RB_RENDER_CONTROL: { DISABLE_COLOR_PIPE | 0x2 } 00170edc: 0000: 000020a1 00000022 t0 write RB_DEPTH_CONTROL (2101) RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } 00170ee4: 0000: 00002101 00000000 t0 write GRAS_ALPHA_CONTROL (2073) GRAS_ALPHA_CONTROL: { 0x2 } 00170eec: 0000: 00002073 00000002 t0 write RB_STENCIL_CONTROL (2106) RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } 00170ef4: 0000: 00002106 00000000 t0 write RB_COPY_CONTROL (20fc) RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_FOUR | MODE = RB_COPY_DEPTH_STENCIL | FASTCLEAR = 0 | GMEM_BASE = 0 } RB_COPY_DEST_BASE: { BASE = 0x4f000 } RB_COPY_DEST_PITCH: { PITCH = 256 } RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_DISABLE | COMPONENT_ENABLE = 0xf | ENDIAN = ENDIAN_NONE | TILE = TILE4_3 } 00170efc: 0000: 000320fc 00000052 0004f000 00000008 0303c068 t0 write UNKNOWN_20EF (20ef) UNKNOWN_20EF: 0 00170f10: 0000: 000020ef 00000000 t0 write GRAS_SC_SCREEN_SCISSOR_TL (207c) GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } 00170f18: 0000: 0001207c 00000000 003f003f t0 write RB_FRAME_BUFFER_DIMENSION (0ce0) RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } 00170f24: 0000: 00000ce0 00400040 t0 write 0xce1 (0ce1) 0xce1: 00000000 00170f2c: 0000: 00000ce1 00000000 t3 opcode: CP_LOAD_STATE4 (30) (11 dwords) { DST_OFF = 8 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } 00170f40: 0.000000 0.000000 1.000000 1.000000 64.000000 64.000000 1.000000 1.000000 00170f40: 0000: 00000000 00000000 3f800000 3f800000 42800000 42800000 3f800000 3f800000 00170f34: 0000: c0093000 00a00008 00000001 00000000 00000000 3f800000 3f800000 42800000 00170f54: 0020: 42800000 3f800000 3f800000 t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x80000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 2 } draw[18] register values + 00000004 UNKNOWN_0CC5: 0x4 + 00000000 UNKNOWN_0CC6: 0 + 00400040 RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } + 00000000 0xce1: 00000000 !+ 00000002 HLSQ_MODE_CONTROL: 0x2 + 00000000 UNKNOWN_0E42: 0 !+ 00000004 SP_MODE_CONTROL: 0x4 !+ 00000068 TPL1_TP_MODE_CONTROL: 0x68 !+ 00188000 GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } + 00000000 UNKNOWN_2001: 0 + 00000001 GRAS_CNTL: { IJ_PERSP } !+ 00000002 GRAS_ALPHA_CONTROL: { 0x2 } !+ 00000000 GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } !+ 00000808 GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = 0 | MSAA_DISABLE | RASTER_MODE = 0 } !+ 00000000 GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } !+ 003f003f GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } !+ 00000022 RB_RENDER_CONTROL: { DISABLE_COLOR_PIPE | 0x2 } !+ 00001000 RB_MSAA_CONTROL: { DISABLE | SAMPLES = 0 } + 00000000 UNKNOWN_20EF: 0 + 00000e00 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } + 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } !+ 00000052 RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_FOUR | MODE = RB_COPY_DEPTH_STENCIL | FASTCLEAR = 0 | GMEM_BASE = 0 } + 0004f000 RB_COPY_DEST_BASE: { BASE = 0x4f000 } + 00000008 RB_COPY_DEST_PITCH: { PITCH = 256 } !+ 0303c068 RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_DISABLE | COMPONENT_ENABLE = 0xf | ENDIAN = ENDIAN_NONE | TILE = TILE4_3 } + 00000000 RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } + 00000000 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } !+ 40001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | 0x40000000 } + 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } + 00000000 UNKNOWN_2152: 0 + 00000000 UNKNOWN_2153: 0 + 00000000 UNKNOWN_2154: 0 + 00000000 UNKNOWN_2155: 0 + 00000000 UNKNOWN_2156: 0 !+ 0000001d UNKNOWN_21C3: 0x1d !+ 00000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 } + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + 00000000 PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } + 00000001 UNKNOWN_21E6: 0x1 !+ 000a0000 VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } !+ fc030000 VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } + fcfcfcfc VFD_CONTROL_2: 0xfcfcfcfc !+ fcfcfc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } + 0000fcfc VFD_CONTROL_4: 0xfcfc + 00000000 VFD_INDEX_OFFSET: 0 + 00000000 UNKNOWN_2209: 0 + 00060010 SP_SP_CTRL_REG: { 0x60010 } + 000005c3 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } !+ 00200c10 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } !+ 01000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } !+ 0010fc03 SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } !+ 00001e03 SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00fcfc00 UNKNOWN_22D7: 0xfcfc00 + 00000008 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } !+ 00000001 SP_VS_OBJ_START: 0x1 !+ 00000002 SP_VS_LENGTH_REG: 2 + 00000000 TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } !+ 00000003 TPL1_TP_FS_TEX_COUNT: 0x3 !+ 080004f0 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } !+ fcfc0120 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } !+ 27f3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } !+ 02010042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } !+ 0041423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } !+ 00404200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } !+ 00404200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } !+ 00404200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00004200 HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } !+ 00000007 HLSQ_UPDATE_CONTROL: 0x7 00170f60: 0000: c0023800 00080888 00000001 00000002 0016b0ac: 0000: c0013f00 00170b94 000000f7 t3 opcode: (null) (1d) (2 dwords) 0016b0b8: 0000: c0001d00 00000000 ############################################################ vertices: 0 ############################################################ cmdstream: 8 dwords t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:000555d8 ibsize:00000155 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 000555d8: 0000: c0002600 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x4 000555e0: 0000: 00000ec3 00000004 t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x68 000555e8: 0000: 00000f03 00000068 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 000555f0: 0000: c0002600 00000000 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } 000555f8: 0000: 000023c0 080004f0 t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = 0x1d } event (null) 00055600: 0000: c0004600 0000001d t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = FACENESS_FLUSH } event FACENESS_FLUSH 00055608: 0000: c0004600 0000001c t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00055610: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0 00055618: 0000: 00000cc6 00000000 t0 write UNKNOWN_0E42 (0e42) UNKNOWN_0E42: 0 00055620: 0000: 00000e42 00000000 t0 write HLSQ_MODE_CONTROL (0e05) HLSQ_MODE_CONTROL: 0x2 00055628: 0000: 00000e05 00000002 t0 write UNKNOWN_0CC5 (0cc5) UNKNOWN_0CC5: 0x4 00055630: 0000: 00000cc5 00000004 t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x7 00055638: 0000: 000023db 00000007 t0 write VFD_CONTROL_2 (2202) VFD_CONTROL_2: 0xfcfcfcfc 00055640: 0000: 00002202 fcfcfcfc t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } 00055648: 0000: 00002203 fcfcfc00 t0 write VFD_CONTROL_4 (2204) VFD_CONTROL_4: 0xfcfc 00055650: 0000: 00002204 0000fcfc t0 write VFD_INDEX_OFFSET (2208) VFD_INDEX_OFFSET: 0 00055658: 0000: 00002208 00000000 t0 write UNKNOWN_2209 (2209) UNKNOWN_2209: 0 00055660: 0000: 00002209 00000000 t0 write UNKNOWN_2152 (2152) UNKNOWN_2152: 0 UNKNOWN_2153: 0 00055668: 0000: 00012152 00000000 00000000 t0 write UNKNOWN_2156 (2156) UNKNOWN_2156: 0 00055674: 0000: 00002156 00000000 t0 write UNKNOWN_2154 (2154) UNKNOWN_2154: 0 0005567c: 0000: 00002154 00000000 t0 write UNKNOWN_2155 (2155) UNKNOWN_2155: 0 00055684: 0000: 00002155 00000000 t0 write UNKNOWN_21C3 (21c3) UNKNOWN_21C3: 0x1d 0005568c: 0000: 000021c3 0000001d t0 write PC_PRIM_VTX_CNTL2 (21c5) PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 00055694: 0000: 000021c5 00000012 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 0005569c: 0000: 000021e5 00000000 t0 write GRAS_SU_MODE_CONTROL (2078) GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } 000556a4: 0000: 00002078 00000000 t0 write UNKNOWN_2001 (2001) UNKNOWN_2001: 0 000556ac: 0000: 00002001 00000000 t0 write GRAS_CNTL (2003) GRAS_CNTL: { IJ_PERSP } 000556b4: 0000: 00002003 00000001 t0 write GRAS_CL_CLIP_CNTL (2000) GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } 000556bc: 0000: 00002000 00188000 t0 write TPL1_TP_TEX_COUNT (2381) TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } 000556c4: 0000: 00002381 00000000 t0 write TPL1_TP_FS_TEX_COUNT (23a0) TPL1_TP_FS_TEX_COUNT: 0x3 000556cc: 0000: 000023a0 00000003 t0 write RB_ALPHA_CONTROL (20f8) RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } 000556d4: 0000: 000020f8 00000e00 t0 write RB_RENDER_COMPONENTS (20fb) RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } 000556dc: 0000: 000020fb 0000000f t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 000556e4: 0000: c0014300 00040000 00000000 t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } 000556f0: 0000: 00002200 000a0000 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } 000556f8: 0000: 00002201 fc030000 t0 write SP_INSTR_CACHE_CTRL (22c1) SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } 00055700: 0000: 000022c1 000005c3 t0 write HLSQ_CONTROL_1_REG (23c1) HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } 00055708: 0000: 000023c1 fcfc0120 t0 write HLSQ_CONTROL_2_REG (23c2) HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 00055710: 0000: 000023c2 27f3f3f0 t0 write HLSQ_VS_CONTROL_REG (23c5) HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } 00055718: 0000: 000023c5 02010042 t0 write HLSQ_FS_CONTROL_REG (23c6) HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 1 } 00055720: 0000: 000023c6 0141423e t0 write HLSQ_HS_CONTROL_REG (23c7) HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00055728: 0000: 000023c7 00404200 t0 write HLSQ_DS_CONTROL_REG (23c8) HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00055730: 0000: 000023c8 00404200 t0 write HLSQ_GS_CONTROL_REG (23c9) HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00055738: 0000: 000023c9 00404200 t0 write HLSQ_CS_CONTROL_REG (23ca) HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } 00055740: 0000: 000023ca 00004200 t0 write SP_SP_CTRL_REG (22c0) SP_SP_CTRL_REG: { 0x60010 } 00055748: 0000: 000022c0 00060010 t0 write UNKNOWN_21E6 (21e6) UNKNOWN_21E6: 0x1 00055750: 0000: 000021e6 00000001 t0 write SP_VS_CTRL_REG0 (22c4) SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 00055758: 0000: 000022c4 00200c10 t0 write SP_VS_CTRL_REG1 (22c5) SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } 00055760: 0000: 000022c5 01000042 t0 write VPC_ATTR (2140) VPC_ATTR: { TOTALATTR = 8 | THRDASSIGN = 1 | ENABLE | 0x40000000 } 00055768: 0000: 00002140 42001008 t0 write VPC_PACK (2141) VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 8 | NUMNONPOSVSVAR = 6 } 00055770: 0000: 00002141 00060800 t0 write PC_PRIM_VTX_CNTL (21c4) PC_PRIM_VTX_CNTL: { VAROUT = 1 } 00055778: 0000: 000021c4 00000001 t0 write SP_VS_PARAM_REG (22c6) SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 2 } SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r1.w | B_COMPMASK = 0x3 } SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } UNKNOWN_22D7: 0xfcfc00 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 12 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 00055780: 0000: 001922c6 0020fc03 06071e03 00000000 00000000 00000000 00000000 00000000 * 000557c0: 0040: 00000000 00000000 00fcfc00 00000c08 00000000 00000000 00000000 00000000 * t0 write SP_VS_OBJ_OFFSET_REG (22e0) SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 000557ec: 0000: 000022e0 00000000 t0 write SP_VS_OBJ_START (22e1) SP_VS_OBJ_START: 0x1 000557f4: 0000: 000022e1 00000001 t0 write SP_VS_LENGTH_REG (22e5) SP_VS_LENGTH_REG: 2 000557fc: 0000: 000022e5 00000002 t3 opcode: CP_LOAD_STATE4 (30) (67 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } :2:0000:0000[56d81803x_20020003x] (sy)(ss)(nop3) shl.b r0.w, r0.w, 2 :1:0001:0004[20150000x_00000003x] cov.s32s16 hr0.x, r0.w :0:0002:0005[00000200x_00000000x] (rpt2)nop :1:0003:0008[201100f4x_00000000x] mova a0.x, hr0.x :0:0004:0009[00000500x_00000000x] (rpt5)nop :1:0005:0015[20154003x_00000c20x] mov.s32s32 r0.w, c :1:0006:0016[20154004x_00000c21x] mov.s32s32 r1.x, c :1:0007:0017[20154007x_00000c22x] mov.s32s32 r1.w, c :1:0008:0018[20156008x_00000c23x] (ul)mov.s32s32 r2.x, c :1:0009:0019[20554005x_00000000x] mov.s32s32 r1.y, 0 :1:0010:0020[20554006x_3f800000x] mov.s32s32 r1.z, 1065353216 :0:0011:0021[03000000x_00000000x] end :2:0012:0022[46f00009x_20050000x] shr.b r2.y, r0.x, 5 :2:0013:0023[4398000ax_201f0000x] (nop2) and.b r2.z, r0.x, 31 :2:0014:0026[43980809x_201f0009x] (nop3) and.b r2.y, r2.y, 31 :2:0015:0030[46100809x_20180009x] (nop1) mul.u24 r2.y, r2.y, 24 :3:0016:0032[62050009x_00091014x] mad.u24 r2.y, c5.x, r2.z, r2.y :0:0017:0033[00000500x_00000000x] (rpt5)nop :6:0018:0039[c2c61300x_04800006x] stlw.u32 l[r2.y], r0.w, 4 :6:0019:0040[c2c61310x_0280000ex] stlw.u32 l[r2.y+16], r1.w, 2 :0:0020:0041[04800000x_00000000x] chmask :0:0021:0042[05000000x_00000000x] chsh Stats: - shaderdb: 43 instr, 24 nops, 19 non-nops, 7 mov, 1 cov - shaderdb: 0 last-baryf, 0 half, 3 full, 5 constlen - shaderdb: 27 cat0, 8 cat1, 5 cat2, 1 cat3, 0 cat4, 0 cat5, 2 cat6, 0 cat7 - shaderdb: 0 sstall, 1 (ss), 1 (sy) 00055804: 0000: c0413000 00a00000 00000000 20020003 56d81803 00000003 20150000 00000000 00055824: 0020: 00000200 00000000 201100f4 00000000 00000500 00000c20 20154003 00000c21 00055844: 0040: 20154004 00000c22 20154007 00000c23 20156008 00000000 20554005 3f800000 00055864: 0060: 20554006 00000000 03000000 20050000 46f00009 201f0000 4398000a 201f0009 00055884: 0080: 43980809 20180009 46100809 00091014 62050009 00000000 00000500 04800006 000558a4: 00a0: c2c61300 0280000e c2c61310 00000000 04800000 00000000 05000000 00000000 * t0 write HLSQ_CONTROL_3_REG (23c3) HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } 00055910: 0000: 000023c3 fcfcfc00 t0 write HLSQ_CONTROL_4_REG (23c4) HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } 00055918: 0000: 000023c4 00fcfcfc t0 write SP_FS_CTRL_REG0 (22e8) SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 0 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE | PIXLODENABLE } SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 } 00055920: 0000: 000122e8 00700402 8010003e t0 write SP_FS_OBJ_OFFSET_REG (22ea) SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 } 0005592c: 0000: 000022ea 40420000 t0 write SP_FS_OBJ_START (22eb) SP_FS_OBJ_START: 0x1 00055934: 0000: 000022eb 00000001 t0 write SP_FS_LENGTH_REG (22ef) SP_FS_LENGTH_REG: 1 0005593c: 0000: 000022ef 00000001 t0 write SP_FS_OUTPUT_REG (22f0) SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r0.x | SAMPLEMASK_REGID = r0.x } 00055944: 0000: 000022f0 00000001 t0 write VPC_VARYING_INTERP[0].MODE (2142) VPC_VARYING_INTERP[0].MODE: 0xe000 0005594c: 0000: 00002142 0000e000 t0 write RB_FS_OUTPUT_REG (2100) RB_FS_OUTPUT_REG: { MRT = 1 } 00055954: 0000: 00002100 00000001 t3 opcode: CP_LOAD_STATE4 (30) (35 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 1 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } :2:0000:0000[57309902x_00002004x] (sy)(ss)(rpt1)bary.f (ei)r0.z, (r)4, r0.x :0:0001:0002[00000500x_00000000x] (rpt5)nop :5:0002:0008[a0c01f00x_00000005x] sam (f32)(xyzw)r0.x, r0.z, s#0, t#0 :0:0003:0009[03000000x_00000000x] end :0:0004:0010[00000000x_00000000x] nop :0:0005:0011[00000000x_00000000x] nop :0:0006:0012[00000000x_00000000x] nop :0:0007:0013[00000000x_00000000x] nop Stats: - shaderdb: 14 instr, 10 nops, 4 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 0 half, 1 full, 0 constlen - shaderdb: 11 cat0, 0 cat1, 2 cat2, 0 cat3, 0 cat4, 1 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 1 (ss), 1 (sy) 0005595c: 0000: c0213000 00700000 00000000 00002004 57309902 00000000 00000500 00000005 0005597c: 0020: a0c01f00 00000000 03000000 00000000 00000000 00000000 00000000 00000000 * t0 write RB_FS_OUTPUT (20f9) RB_FS_OUTPUT: { ENABLE_BLEND = 0 | SAMPLE_MASK = 0xffff } 000559e8: 0000: 000020f9 ffff0000 t0 write RB_MRT[0].CONTROL (20a4) RB_MRT[0].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0xf } 000559f0: 0000: 000020a4 0f000000 t0 write RB_MRT[0x1].CONTROL (20a9) RB_MRT[0x1].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0xf } 000559f8: 0000: 000020a9 0f000000 t0 write RB_MRT[0].BLEND_CONTROL (20a8) RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } 00055a00: 0000: 000020a8 00000000 t3 opcode: CP_LOAD_STATE4 (30) (5 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_TEX | NUM_UNIT = 1 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } { XY_MAG = A4XX_TEX_NEAREST | XY_MIN = A4XX_TEX_NEAREST | WRAP_S = A4XX_TEX_CLAMP_TO_EDGE | WRAP_T = A4XX_TEX_CLAMP_TO_EDGE | WRAP_R = A4XX_TEX_CLAMP_TO_EDGE | ANISO = A4XX_TEX_ANISO_1 | LOD_BIAS = 0.000000 | 0x60000 } { COMPARE_FUNC = FUNC_LEQUAL | UNNORM_COORDS | MIPFILTER_LINEAR_FAR | MAX_LOD = 0.000000 | MIN_LOD = 0.000000 | 0x1 } 00055a14: 0000: 00060920 00000067 00055a08: 0000: c0033000 00500000 00000000 00060920 00000067 t0 write GRAS_SC_CONTROL (207b) GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 0 | RASTER_MODE = 0 } 00055a1c: 0000: 0000207b 00000000 t0 write RB_MSAA_CONTROL (20a2) RB_MSAA_CONTROL: { SAMPLES = 0 } 00055a24: 0000: 000020a2 00000000 t0 write RB_RENDER_CONTROL (20a1) RB_RENDER_CONTROL: { 0 } 00055a2c: 0000: 000020a1 00000000 t0 write 0x2382 (2382) 0x2382: 00000000 00055a34: 0000: 00002382 00000000 t0 write RB_DEPTH_CONTROL (2101) RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } 00055a3c: 0000: 00002101 00000000 t0 write GRAS_ALPHA_CONTROL (2073) GRAS_ALPHA_CONTROL: { 0 } 00055a44: 0000: 00002073 00000000 t0 write RB_STENCIL_CONTROL (2106) RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } 00055a4c: 0000: 00002106 00000000 t0 write SP_FS_MRT[0].REG (22f1) SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = RB4_R8G8B8A8_UNORM } 00055a54: 0000: 000022f1 0001a000 t0 write RB_MRT[0].BUF_INFO (20a5) RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB4_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE4_3 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 256 } RB_MRT[0].BASE: 0x166000 RB_MRT[0].CONTROL3: { STRIDE = 0 } 00055a5c: 0000: 000220a5 000400da 00166000 00000000 t3 opcode: CP_LOAD_STATE4 (30) (11 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_TEX | NUM_UNIT = 1 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } { TILED | SWIZ_X = A4XX_TEX_X | SWIZ_Y = A4XX_TEX_Y | SWIZ_Z = A4XX_TEX_Z | SWIZ_W = A4XX_TEX_W | MIPLVLS = 0 | FMT = TFMT4_8_8_8_8_UNORM | TYPE = A4XX_TEX_2D | 0x2 } { HEIGHT = 64 | WIDTH = 64 } { PITCHALIGN = 0 | PITCH = 256 | SWAP = WZYX } { LAYERSZ = 0 | DEPTH = 1 | 0x20000 } { LAYERSZ = 4096 | BASE = 0x4f000 } { 5 = 0 } { 6 = 0 } { 7 = 0 } 00055a78: 0000: 27006883 00200040 00020000 00060000 0004f001 00000000 00000000 00000000 00055a6c: 0000: c0093000 00500000 00000001 27006883 00200040 00020000 00060000 0004f001 * t0 write VPC_VARYING_PS_REPL[0].MODE (214a) VPC_VARYING_PS_REPL[0].MODE: 0x99999999 00055a98: 0000: 0000214a 99999999 t0 write GRAS_SC_SCREEN_SCISSOR_TL (207c) GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } 00055aa0: 0000: 0001207c 00000000 003f003f t0 write GRAS_SC_WINDOW_SCISSOR_BR (209c) GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 00055aac: 0000: 0001209c 003f003f 00000000 t0 write RB_FRAME_BUFFER_DIMENSION (0ce0) RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } 00055ab8: 0000: 00000ce0 00400040 t0 write 0xce1 (0ce1) 0xce1: 00000000 00055ac0: 0000: 00000ce1 00000000 t0 write RB_RENDER_CONTROL2 (20a3) RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 | IJ_PERSP_PIXEL } 00055ac8: 0000: 000020a3 00001000 t0 write RB_MODE_CONTROL (20a0) RB_MODE_CONTROL: { WIDTH = 0 | HEIGHT = 0 | 0xc00000 } 00055ad0: 0000: 000020a0 00c00000 t3 opcode: CP_LOAD_STATE4 (30) (11 dwords) { DST_OFF = 8 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } 00055ae4: 0.000000 0.000000 0.000000 0.000000 64.000000 64.000000 64.000000 64.000000 00055ae4: 0000: 00000000 00000000 00000000 00000000 42800000 42800000 42800000 42800000 00055ad8: 0000: c0093000 00a00008 00000001 00000000 00000000 00000000 00000000 42800000 00055af8: 0020: 42800000 42800000 42800000 t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x80000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 2 } draw[19] register values + 00000004 UNKNOWN_0CC5: 0x4 + 00000000 UNKNOWN_0CC6: 0 + 00400040 RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } + 00000000 0xce1: 00000000 + 00000002 HLSQ_MODE_CONTROL: 0x2 + 00000000 UNKNOWN_0E42: 0 + 00000004 SP_MODE_CONTROL: 0x4 + 00000068 TPL1_TP_MODE_CONTROL: 0x68 + 00188000 GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } + 00000000 UNKNOWN_2001: 0 + 00000001 GRAS_CNTL: { IJ_PERSP } !+ 00000000 GRAS_ALPHA_CONTROL: { 0 } + 00000000 GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } !+ 00000000 GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 0 | RASTER_MODE = 0 } + 00000000 GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } + 003f003f GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } + 003f003f GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } + 00000000 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } !+ 00c00000 RB_MODE_CONTROL: { WIDTH = 0 | HEIGHT = 0 | 0xc00000 } !+ 00000000 RB_RENDER_CONTROL: { 0 } !+ 00000000 RB_MSAA_CONTROL: { SAMPLES = 0 } !+ 00001000 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 | IJ_PERSP_PIXEL } !+ 0f000000 RB_MRT[0].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0xf } !+ 000400da RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB4_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE4_3 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 256 } !+ 00166000 RB_MRT[0].BASE: 0x166000 !+ 00000000 RB_MRT[0].CONTROL3: { STRIDE = 0 } + 00000000 RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } + 0f000000 RB_MRT[0x1].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0xf } + 00000e00 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } !+ ffff0000 RB_FS_OUTPUT: { ENABLE_BLEND = 0 | SAMPLE_MASK = 0xffff } + 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } + 00000001 RB_FS_OUTPUT_REG: { MRT = 1 } + 00000000 RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } + 00000000 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } !+ 42001008 VPC_ATTR: { TOTALATTR = 8 | THRDASSIGN = 1 | ENABLE | 0x40000000 } !+ 00060800 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 8 | NUMNONPOSVSVAR = 6 } !+ 0000e000 VPC_VARYING_INTERP[0].MODE: 0xe000 !+ 99999999 VPC_VARYING_PS_REPL[0].MODE: 0x99999999 + 00000000 UNKNOWN_2152: 0 + 00000000 UNKNOWN_2153: 0 + 00000000 UNKNOWN_2154: 0 + 00000000 UNKNOWN_2155: 0 + 00000000 UNKNOWN_2156: 0 + 0000001d UNKNOWN_21C3: 0x1d + 00000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 } + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + 00000000 PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } + 00000001 UNKNOWN_21E6: 0x1 + 000a0000 VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } + fc030000 VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } + fcfcfcfc VFD_CONTROL_2: 0xfcfcfcfc + fcfcfc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } + 0000fcfc VFD_CONTROL_4: 0xfcfc + 00000000 VFD_INDEX_OFFSET: 0 + 00000000 UNKNOWN_2209: 0 + 00060010 SP_SP_CTRL_REG: { 0x60010 } + 000005c3 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } + 00200c10 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } + 01000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } !+ 0020fc03 SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 2 } !+ 06071e03 SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r1.w | B_COMPMASK = 0x3 } + 00000000 SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00fcfc00 UNKNOWN_22D7: 0xfcfc00 !+ 00000c08 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 12 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } + 00000001 SP_VS_OBJ_START: 0x1 + 00000002 SP_VS_LENGTH_REG: 2 !+ 00700402 SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 0 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE | PIXLODENABLE } !+ 8010003e SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 } !+ 40420000 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 } !+ 00000001 SP_FS_OBJ_START: 0x1 + 00000001 SP_FS_LENGTH_REG: 1 !+ 00000001 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r0.x | SAMPLEMASK_REGID = r0.x } !+ 0001a000 SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = RB4_R8G8B8A8_UNORM } + 00000000 TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } !+ 00000000 0x2382: 00000000 + 00000003 TPL1_TP_FS_TEX_COUNT: 0x3 + 080004f0 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } + fcfc0120 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } + 27f3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } + fcfcfc00 HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } !+ 00fcfcfc HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } + 02010042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } !+ 0141423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 1 } + 00404200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00004200 HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } + 00000007 HLSQ_UPDATE_CONTROL: 0x7 00055b04: 0000: c0023800 00080888 00000001 00000002 t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = CACHE_FLUSH } event CACHE_FLUSH 00055b14: 0000: c0004600 00000006 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00055b1c: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0x8000012 00055b24: 0000: 00000cc6 08000012 00173000: 0000: c0013f00 000555d8 00000155 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 0017300c: 0000: c0014300 00040000 00000000 t3 opcode: (null) (1d) (2 dwords) 00173018: 0000: c0001d00 00000000 ############################################################ vertices: 0 ############################################################ cmdstream: 48 dwords t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 0016b000: 0000: c0002600 00000000 t0 write UCHE_INVALIDATE0 (0e8a) UCHE_INVALIDATE0: 0 UCHE_INVALIDATE1: 0x12 0016b008: 0000: 00010e8a 00000000 00000012 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 0016b014: 0000: c0002600 00000000 t0 write RB_MODE_CONTROL (20a0) RB_MODE_CONTROL: { WIDTH = 64 | HEIGHT = 64 | ENABLE_GMEM } 0016b01c: 0000: 000020a0 00010202 t0 write RB_FRAME_BUFFER_DIMENSION (0ce0) RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } 0016b024: 0000: 00000ce0 00400040 t0 write 0xce1 (0ce1) 0xce1: 00000001 0016b02c: 0000: 00000ce1 00000001 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 0016b034: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0 0016b03c: 0000: 00000cc6 00000000 t3 opcode: (null) (1d) (2 dwords) 0016b044: 0000: c0001d00 00000000 t0 write GRAS_SC_WINDOW_SCISSOR_BR (209c) GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 0016b04c: 0000: 0001209c 003f003f 00000000 t0 write RB_BIN_OFFSET (210d) RB_BIN_OFFSET: { X = 0 | Y = 0 } 0016b058: 0000: 0000210d 00000000 t0 write GRAS_SC_WINDOW_SCISSOR_BR (209c) GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 0016b060: 0000: 0001209c 003f003f 00000000 t0 write UNKNOWN_2157 (2157) UNKNOWN_2157: 0x1 0016b06c: 0000: 00002157 00000001 t3 opcode: (null) (64) (2 dwords) 0016b074: 0000: c0006400 00000001 t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:00054994 ibsize:000000f6 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00054994: 0000: c0002600 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x4 0005499c: 0000: 00000ec3 00000004 t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x68 000549a4: 0000: 00000f03 00000068 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 000549ac: 0000: c0002600 00000000 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } 000549b4: 0000: 000023c0 080004f0 t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = 0x1d } event (null) 000549bc: 0000: c0004600 0000001d t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = FACENESS_FLUSH } event FACENESS_FLUSH 000549c4: 0000: c0004600 0000001c t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 000549cc: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0 000549d4: 0000: 00000cc6 00000000 t0 write UNKNOWN_0E42 (0e42) UNKNOWN_0E42: 0 000549dc: 0000: 00000e42 00000000 t0 write HLSQ_MODE_CONTROL (0e05) HLSQ_MODE_CONTROL: 0x2 000549e4: 0000: 00000e05 00000002 t0 write UNKNOWN_0CC5 (0cc5) UNKNOWN_0CC5: 0x4 000549ec: 0000: 00000cc5 00000004 t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x7 000549f4: 0000: 000023db 00000007 t0 write VFD_CONTROL_2 (2202) VFD_CONTROL_2: 0xfcfcfcfc 000549fc: 0000: 00002202 fcfcfcfc t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } 00054a04: 0000: 00002203 fcfcfc00 t0 write VFD_CONTROL_4 (2204) VFD_CONTROL_4: 0xfcfc 00054a0c: 0000: 00002204 0000fcfc t0 write VFD_INDEX_OFFSET (2208) VFD_INDEX_OFFSET: 0 00054a14: 0000: 00002208 00000000 t0 write UNKNOWN_2209 (2209) UNKNOWN_2209: 0 00054a1c: 0000: 00002209 00000000 t0 write UNKNOWN_2152 (2152) UNKNOWN_2152: 0 UNKNOWN_2153: 0 00054a24: 0000: 00012152 00000000 00000000 t0 write UNKNOWN_2156 (2156) UNKNOWN_2156: 0 00054a30: 0000: 00002156 00000000 t0 write UNKNOWN_2154 (2154) UNKNOWN_2154: 0 00054a38: 0000: 00002154 00000000 t0 write UNKNOWN_2155 (2155) UNKNOWN_2155: 0 00054a40: 0000: 00002155 00000000 t0 write UNKNOWN_21C3 (21c3) UNKNOWN_21C3: 0x1d 00054a48: 0000: 000021c3 0000001d t0 write PC_PRIM_VTX_CNTL2 (21c5) PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 00054a50: 0000: 000021c5 00000012 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 00054a58: 0000: 000021e5 00000000 t0 write GRAS_SU_MODE_CONTROL (2078) GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } 00054a60: 0000: 00002078 00000000 t0 write UNKNOWN_2001 (2001) UNKNOWN_2001: 0 00054a68: 0000: 00002001 00000000 t0 write GRAS_CNTL (2003) GRAS_CNTL: { IJ_PERSP } 00054a70: 0000: 00002003 00000001 t0 write GRAS_CL_CLIP_CNTL (2000) GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } 00054a78: 0000: 00002000 00188000 t0 write TPL1_TP_TEX_COUNT (2381) TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } 00054a80: 0000: 00002381 00000000 t0 write TPL1_TP_FS_TEX_COUNT (23a0) TPL1_TP_FS_TEX_COUNT: 0x3 00054a88: 0000: 000023a0 00000003 t0 write RB_ALPHA_CONTROL (20f8) RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } 00054a90: 0000: 000020f8 00000e00 t0 write RB_RENDER_COMPONENTS (20fb) RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } 00054a98: 0000: 000020fb 0000000f t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 00054aa0: 0000: c0014300 00040000 00000000 t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } 00054aac: 0000: 00002200 000a0000 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } 00054ab4: 0000: 00002201 fc030000 t0 write SP_INSTR_CACHE_CTRL (22c1) SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } 00054abc: 0000: 000022c1 000005c3 t0 write HLSQ_CONTROL_1_REG (23c1) HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } 00054ac4: 0000: 000023c1 fcfc0120 t0 write HLSQ_CONTROL_2_REG (23c2) HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 00054acc: 0000: 000023c2 27f3f3f0 t0 write HLSQ_VS_CONTROL_REG (23c5) HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } 00054ad4: 0000: 000023c5 02010042 t0 write HLSQ_FS_CONTROL_REG (23c6) HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00054adc: 0000: 000023c6 0041423e t0 write HLSQ_HS_CONTROL_REG (23c7) HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00054ae4: 0000: 000023c7 00404200 t0 write HLSQ_DS_CONTROL_REG (23c8) HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00054aec: 0000: 000023c8 00404200 t0 write HLSQ_GS_CONTROL_REG (23c9) HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00054af4: 0000: 000023c9 00404200 t0 write HLSQ_CS_CONTROL_REG (23ca) HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } 00054afc: 0000: 000023ca 00004200 t0 write SP_SP_CTRL_REG (22c0) SP_SP_CTRL_REG: { 0x60010 } 00054b04: 0000: 000022c0 00060010 t0 write UNKNOWN_21E6 (21e6) UNKNOWN_21E6: 0x1 00054b0c: 0000: 000021e6 00000001 t0 write SP_VS_CTRL_REG0 (22c4) SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 00054b14: 0000: 000022c4 00200c10 t0 write SP_VS_CTRL_REG1 (22c5) SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } 00054b1c: 0000: 000022c5 01000042 t0 write VPC_ATTR (2140) VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | 0x40000000 } 00054b24: 0000: 00002140 40001004 t0 write VPC_PACK (2141) VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } 00054b2c: 0000: 00002141 00040400 t0 write PC_PRIM_VTX_CNTL (21c4) PC_PRIM_VTX_CNTL: { VAROUT = 1 } 00054b34: 0000: 000021c4 00000001 t0 write SP_VS_PARAM_REG (22c6) SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } UNKNOWN_22D7: 0xfcfc00 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 00054b3c: 0000: 001922c6 0010fc03 00001e03 00000000 00000000 00000000 00000000 00000000 * 00054b7c: 0040: 00000000 00000000 00fcfc00 00000008 00000000 00000000 00000000 00000000 * t0 write SP_VS_OBJ_OFFSET_REG (22e0) SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 00054ba8: 0000: 000022e0 00000000 t0 write SP_VS_OBJ_START (22e1) SP_VS_OBJ_START: 0x1 00054bb0: 0000: 000022e1 00000001 t0 write SP_VS_LENGTH_REG (22e5) SP_VS_LENGTH_REG: 2 00054bb8: 0000: 000022e5 00000002 t3 opcode: CP_LOAD_STATE4 (30) (67 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } :2:0000:0000[56d81803x_20020003x] (sy)(ss)(nop3) shl.b r0.w, r0.w, 2 :1:0001:0004[20150000x_00000003x] cov.s32s16 hr0.x, r0.w :0:0002:0005[00000200x_00000000x] (rpt2)nop :1:0003:0008[201100f4x_00000000x] mova a0.x, hr0.x :0:0004:0009[00000500x_00000000x] (rpt5)nop :1:0005:0015[20154003x_00000c20x] mov.s32s32 r0.w, c :1:0006:0016[20154004x_00000c21x] mov.s32s32 r1.x, c :1:0007:0017[20154005x_00000c22x] mov.s32s32 r1.y, c :1:0008:0018[20156006x_00000c23x] (ul)mov.s32s32 r1.z, c :0:0009:0019[03000000x_00000000x] end :2:0010:0020[46f00007x_20050000x] shr.b r1.w, r0.x, 5 :2:0011:0021[43980008x_201f0000x] (nop2) and.b r2.x, r0.x, 31 :2:0012:0024[43980807x_201f0007x] (nop3) and.b r1.w, r1.w, 31 :2:0013:0028[46100807x_20100007x] (nop1) mul.u24 r1.w, r1.w, 16 :3:0014:0030[62040007x_00071014x] mad.u24 r1.w, c5.x, r2.x, r1.w :0:0015:0031[00000500x_00000000x] (rpt5)nop :6:0016:0037[c2c60f00x_04800006x] stlw.u32 l[r1.w], r0.w, 4 :0:0017:0038[04800000x_00000000x] chmask :0:0018:0039[05000000x_00000000x] chsh Stats: - shaderdb: 40 instr, 24 nops, 16 non-nops, 5 mov, 1 cov - shaderdb: 0 last-baryf, 0 half, 2 full, 5 constlen - shaderdb: 27 cat0, 6 cat1, 5 cat2, 1 cat3, 0 cat4, 0 cat5, 1 cat6, 0 cat7 - shaderdb: 0 sstall, 1 (ss), 1 (sy) 00054bc0: 0000: c0413000 00a00000 00000000 20020003 56d81803 00000003 20150000 00000000 00054be0: 0020: 00000200 00000000 201100f4 00000000 00000500 00000c20 20154003 00000c21 00054c00: 0040: 20154004 00000c22 20154005 00000c23 20156006 00000000 03000000 20050000 00054c20: 0060: 46f00007 201f0000 43980008 201f0007 43980807 20100007 46100807 00071014 00054c40: 0080: 62040007 00000000 00000500 04800006 c2c60f00 00000000 04800000 00000000 00054c60: 00a0: 05000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 * t0 write GRAS_ALPHA_CONTROL (2073) GRAS_ALPHA_CONTROL: { 0x2 } 00054ccc: 0000: 00002073 00000002 t0 write GRAS_SC_CONTROL (207b) GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = 4 | MSAA_DISABLE | RASTER_MODE = 0 } 00054cd4: 0000: 0000207b 00000a08 t0 write RB_MSAA_CONTROL (20a2) RB_MSAA_CONTROL: { DISABLE | SAMPLES = 4 } 00054cdc: 0000: 000020a2 00009000 t0 write RB_RENDER_CONTROL (20a1) RB_RENDER_CONTROL: { DISABLE_COLOR_PIPE | 0x2 } 00054ce4: 0000: 000020a1 00000022 t0 write RB_CLEAR_COLOR_DW0 (20cc) RB_CLEAR_COLOR_DW0: 0xff000000 RB_CLEAR_COLOR_DW1: 0 RB_CLEAR_COLOR_DW2: 0 RB_CLEAR_COLOR_DW3: 0 00054cec: 0000: 000320cc ff000000 00000000 00000000 00000000 t0 write RB_COPY_CONTROL (20fc) RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_FOUR | MODE = RB_COPY_CLEAR | FASTCLEAR = 0xf | GMEM_BASE = 0 } RB_COPY_DEST_BASE: { BASE = 0x4f000 } RB_COPY_DEST_PITCH: { PITCH = 256 } RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_IF_ALPHA_OFF | COMPONENT_ENABLE = 0 | ENDIAN = ENDIAN_NONE | TILE = TILE4_3 } 00054d00: 0000: 000320fc 00000f22 0004f000 00000008 03000868 t0 write GRAS_SC_SCREEN_SCISSOR_TL (207c) GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } 00054d14: 0000: 0001207c 00000000 003f003f t0 write RB_FRAME_BUFFER_DIMENSION (0ce0) RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } 00054d20: 0000: 00000ce0 00400040 t0 write 0xce1 (0ce1) 0xce1: 00000000 00054d28: 0000: 00000ce1 00000000 t3 opcode: CP_LOAD_STATE4 (30) (11 dwords) { DST_OFF = 8 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } 00054d3c: 0.000000 0.000000 1.000000 1.000000 64.000000 64.000000 1.000000 1.000000 00054d3c: 0000: 00000000 00000000 3f800000 3f800000 42800000 42800000 3f800000 3f800000 00054d30: 0000: c0093000 00a00008 00000001 00000000 00000000 3f800000 3f800000 42800000 00054d50: 0020: 42800000 3f800000 3f800000 t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x80000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 2 } draw[20] register values + 00000004 UNKNOWN_0CC5: 0x4 + 00000000 UNKNOWN_0CC6: 0 + 00400040 RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } + 00000000 0xce1: 00000000 + 00000002 HLSQ_MODE_CONTROL: 0x2 + 00000000 UNKNOWN_0E42: 0 + 00000000 UCHE_INVALIDATE0: 0 + 00000012 UCHE_INVALIDATE1: 0x12 + 00000004 SP_MODE_CONTROL: 0x4 + 00000068 TPL1_TP_MODE_CONTROL: 0x68 + 00188000 GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } + 00000000 UNKNOWN_2001: 0 + 00000001 GRAS_CNTL: { IJ_PERSP } !+ 00000002 GRAS_ALPHA_CONTROL: { 0x2 } + 00000000 GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } !+ 00000a08 GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = 4 | MSAA_DISABLE | RASTER_MODE = 0 } + 00000000 GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } + 003f003f GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } + 003f003f GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } + 00000000 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } !+ 00010202 RB_MODE_CONTROL: { WIDTH = 64 | HEIGHT = 64 | ENABLE_GMEM } !+ 00000022 RB_RENDER_CONTROL: { DISABLE_COLOR_PIPE | 0x2 } !+ 00009000 RB_MSAA_CONTROL: { DISABLE | SAMPLES = 4 } + ff000000 RB_CLEAR_COLOR_DW0: 0xff000000 + 00000000 RB_CLEAR_COLOR_DW1: 0 + 00000000 RB_CLEAR_COLOR_DW2: 0 + 00000000 RB_CLEAR_COLOR_DW3: 0 + 00000e00 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } + 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } !+ 00000f22 RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_FOUR | MODE = RB_COPY_CLEAR | FASTCLEAR = 0xf | GMEM_BASE = 0 } + 0004f000 RB_COPY_DEST_BASE: { BASE = 0x4f000 } + 00000008 RB_COPY_DEST_PITCH: { PITCH = 256 } !+ 03000868 RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_IF_ALPHA_OFF | COMPONENT_ENABLE = 0 | ENDIAN = ENDIAN_NONE | TILE = TILE4_3 } + 00000000 RB_BIN_OFFSET: { X = 0 | Y = 0 } !+ 40001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | 0x40000000 } !+ 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } + 00000000 UNKNOWN_2152: 0 + 00000000 UNKNOWN_2153: 0 + 00000000 UNKNOWN_2154: 0 + 00000000 UNKNOWN_2155: 0 + 00000000 UNKNOWN_2156: 0 + 00000001 UNKNOWN_2157: 0x1 + 0000001d UNKNOWN_21C3: 0x1d + 00000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 } + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + 00000000 PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } + 00000001 UNKNOWN_21E6: 0x1 + 000a0000 VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } + fc030000 VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } + fcfcfcfc VFD_CONTROL_2: 0xfcfcfcfc + fcfcfc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } + 0000fcfc VFD_CONTROL_4: 0xfcfc + 00000000 VFD_INDEX_OFFSET: 0 + 00000000 UNKNOWN_2209: 0 + 00060010 SP_SP_CTRL_REG: { 0x60010 } + 000005c3 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } + 00200c10 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } + 01000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } !+ 0010fc03 SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } !+ 00001e03 SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00fcfc00 UNKNOWN_22D7: 0xfcfc00 !+ 00000008 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } + 00000001 SP_VS_OBJ_START: 0x1 + 00000002 SP_VS_LENGTH_REG: 2 + 00000000 TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } + 00000003 TPL1_TP_FS_TEX_COUNT: 0x3 + 080004f0 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } + fcfc0120 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } + 27f3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } + 02010042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } !+ 0041423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00004200 HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } + 00000007 HLSQ_UPDATE_CONTROL: 0x7 00054d5c: 0000: c0023800 00080888 00000001 00000002 0016b07c: 0000: c0013f00 00054994 000000f6 t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:00054d6c ibsize:00000037 t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } 00054d6c: 0000: 00002200 082a0008 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00054d74: 0000: c0002600 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x1e 00054d7c: 0000: 00000ec3 0000001e t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x28 00054d84: 0000: 00000f03 00000028 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00054d8c: 0000: c0002600 00000000 t0 write HLSQ_MODE_CONTROL (0e05) HLSQ_MODE_CONTROL: 0x1 00054d94: 0000: 00000e05 00000001 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0x600a0 } 00054d9c: 0000: 000023c0 080604f0 t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x7 00054da4: 0000: 000023db 00000007 t0 write PC_RESTART_INDEX (21c6) PC_RESTART_INDEX: 0xffffffff 00054dac: 0000: 000021c6 ffffffff t0 write UNKNOWN_21E6 (21e6) UNKNOWN_21E6: 0x1 00054db4: 0000: 000021e6 00000001 t0 write UNKNOWN_21C3 (21c3) UNKNOWN_21C3: 0x1f 00054dbc: 0000: 000021c3 0000001f t0 write TPL1_TP_TEX_OFFSET (2380) TPL1_TP_TEX_OFFSET: 0x808 00054dc4: 0000: 00002380 00000808 t0 write GRAS_SU_POINT_MINMAX (2070) GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 4092.000000 } GRAS_SU_POINT_SIZE: 0.500000 00054dcc: 0000: 00012070 ffc00010 00000008 t0 write UNKNOWN_2152 (2152) UNKNOWN_2152: 0 UNKNOWN_2153: 0 00054dd8: 0000: 00012152 00000000 00000000 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00054de4: 0000: c0002600 00000000 t0 write UNKNOWN_0CC5 (0cc5) UNKNOWN_0CC5: 0x4 00054dec: 0000: 00000cc5 00000004 t0 write 0xcc4 (0cc4) 0xcc4: 00000000 00054df4: 0000: 00000cc4 00000000 t0 write 0xd03 (0d03) 0xd03: 80200000 00054dfc: 0000: 00000d03 80200000 t0 write UNKNOWN_0EC2 (0ec2) UNKNOWN_0EC2: 0x40000 00054e04: 0000: 00000ec2 00040000 t0 write VPC_DEBUG_ECO_CONTROL (0e64) VPC_DEBUG_ECO_CONTROL: 0x100 00054e0c: 0000: 00000e64 00000100 t0 write UNKNOWN_0E42 (0e42) UNKNOWN_0E42: 0 00054e14: 0000: 00000e42 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x1e 00054e1c: 0000: 00000ec3 0000001e t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x28 00054e24: 0000: 00000f03 00000028 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 00054e2c: 0000: c0014300 00040000 00000000 t0 write VFD_INDEX_OFFSET (2208) VFD_INDEX_OFFSET: 0 00054e38: 0000: 00002208 00000000 t0 write UNKNOWN_2209 (2209) UNKNOWN_2209: 0 00054e40: 0000: 00002209 00000000 0016b088: 0000: c0013f00 00054d6c 00000037 t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:00055328 ibsize:000000ac t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x3 00055328: 0000: 000023db 00000003 t0 write SP_INSTR_CACHE_CTRL (22c1) SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } 00055330: 0000: 000022c1 000005c3 t0 write HLSQ_CONTROL_1_REG (23c1) HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x1008 } 00055338: 0000: 000023c1 fcfc1108 t0 write HLSQ_CONTROL_2_REG (23c2) HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 00055340: 0000: 000023c2 fff3f3f0 t0 write HLSQ_VS_CONTROL_REG (23c5) HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 2 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 1 } 00055348: 0000: 000023c5 01010002 t0 write HLSQ_HS_CONTROL_REG (23c7) HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 00055350: 0000: 000023c7 007e0200 t0 write HLSQ_DS_CONTROL_REG (23c8) HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 00055358: 0000: 000023c8 007e0200 t0 write HLSQ_GS_CONTROL_REG (23c9) HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 00055360: 0000: 000023c9 007e0200 t0 write HLSQ_FS_CONTROL_REG (23c6) HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 2 | CONSTOBJECTOFFSET = 2 | ENABLED | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 } 00055368: 0000: 000023c6 017f0202 t0 write SP_VS_OBJ_OFFSET_REG (22e0) SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 00055370: 0000: 000022e0 00000000 t0 write SP_HS_OBJ_OFFSET_REG (230d) SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } 00055378: 0000: 0000230d 7e020000 t0 write SP_DS_OBJ_OFFSET_REG (2334) SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } 00055380: 0000: 00002334 7e020000 t0 write SP_GS_OBJ_OFFSET_REG (235b) SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } 00055388: 0000: 0000235b 7e020000 t0 write SP_FS_OBJ_OFFSET_REG (22ea) SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } 00055390: 0000: 000022ea 7e020000 t0 write SP_VS_OBJ_START (22e1) SP_VS_OBJ_START: 0x49000 00049000: 0000: 00000000 13000000 00000000 00000000 00000000 00000000 00000000 00000000 * :0:0000:0000[13000000x_00000000x] (sy)end :0:0001:0001[00000000x_00000000x] nop :0:0002:0002[00000000x_00000000x] nop :0:0003:0003[00000000x_00000000x] nop :0:0004:0004[00000000x_00000000x] nop Stats: - shaderdb: 5 instr, 4 nops, 1 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 0 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 0 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) 00055398: 0000: 000022e1 00049000 t0 write SP_HS_OBJ_START (230e) SP_HS_OBJ_START: 0 000553a0: 0000: 0000230e 00000000 t0 write SP_DS_OBJ_START (2335) SP_DS_OBJ_START: 0 000553a8: 0000: 00002335 00000000 t0 write SP_GS_OBJ_START (235c) SP_GS_OBJ_START: 0 000553b0: 0000: 0000235c 00000000 t0 write SP_VS_LENGTH_REG (22e5) SP_VS_LENGTH_REG: 1 000553b8: 0000: 000022e5 00000001 t3 opcode: CP_LOAD_STATE4 (30) (3 dwords) { DST_OFF = 0 | STATE_SRC = SS4_INDIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 1 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0x49000 } :0:0000:0000[13000000x_00000000x] (sy)end :0:0001:0001[00000000x_00000000x] nop :0:0002:0002[00000000x_00000000x] nop :0:0003:0003[00000000x_00000000x] nop :0:0004:0004[00000000x_00000000x] nop Stats: - shaderdb: 5 instr, 4 nops, 1 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 0 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 0 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) 000553c0: 0000: c0013000 00620000 00049000 t0 write 0x2072 (2072) 0x2072: 00000000 000553cc: 0000: 00002072 00000000 t0 write UNKNOWN_2155 (2155) UNKNOWN_2155: 0 000553d4: 0000: 00002155 00000000 t0 write GRAS_CNTL (2003) GRAS_CNTL: { IJ_PERSP } 000553dc: 0000: 00002003 00000001 t0 write VPC_VARYING_INTERP[0].MODE (2142) VPC_VARYING_INTERP[0].MODE: 0 000553e4: 0000: 00002142 00000000 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0x600a0 } 000553ec: 0000: 000023c0 080604f0 t0 write HLSQ_CONTROL_3_REG (23c3) HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } 000553f4: 0000: 000023c3 fcfcfc00 t0 write HLSQ_CONTROL_4_REG (23c4) HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r0.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } 000553fc: 0000: 000023c4 00fcfc00 t0 write SP_FS_CTRL_REG0 (22e8) SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE } SP_FS_CTRL_REG1: { CONSTLENGTH = 2 | VARYING | 0x80000000 } 00055404: 0000: 000122e8 00340412 80100002 t0 write SP_FS_OBJ_START (22eb) SP_FS_OBJ_START: 0x46000 00046000: 0000: 00002000 5730cb00 00000000 03000000 00000000 00000000 00000000 00000000 * :2:0000:0000[5730cb00x_00002000x] (sy)(rpt3)bary.f (ei)hr0.x, (r)0, r0.x :0:0001:0004[03000000x_00000000x] end :0:0002:0005[00000000x_00000000x] nop :0:0003:0006[00000000x_00000000x] nop :0:0004:0007[00000000x_00000000x] nop :0:0005:0008[00000000x_00000000x] nop Stats: - shaderdb: 9 instr, 4 nops, 5 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 1 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 4 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) 00055410: 0000: 000022eb 00046000 t0 write SP_FS_LENGTH_REG (22ef) SP_FS_LENGTH_REG: 1 00055418: 0000: 000022ef 00000001 t0 write RB_RENDER_COMPONENTS (20fb) RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } 00055420: 0000: 000020fb 0000000f t3 opcode: CP_LOAD_STATE4 (30) (3 dwords) { DST_OFF = 0 | STATE_SRC = SS4_INDIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 1 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0x46000 } :2:0000:0000[5730cb00x_00002000x] (sy)(rpt3)bary.f (ei)hr0.x, (r)0, r0.x :0:0001:0004[03000000x_00000000x] end :0:0002:0005[00000000x_00000000x] nop :0:0003:0006[00000000x_00000000x] nop :0:0004:0007[00000000x_00000000x] nop :0:0005:0008[00000000x_00000000x] nop Stats: - shaderdb: 9 instr, 4 nops, 5 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 1 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 4 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) 00055428: 0000: c0013000 00720000 00046000 t0 write SP_SP_CTRL_REG (22c0) SP_SP_CTRL_REG: { 0x60010 } 00055434: 0000: 000022c0 00060010 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 28 | GROUP_ID = 3 } { ADDR_LO = 0x99ea0 } 0005543c: 0000: c0014300 0300001c 00099ea0 t0 write RB_DEPTH_INFO (2103) RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTH4_NONE | DEPTH_BASE = 0 } RB_DEPTH_PITCH: 0 RB_DEPTH_PITCH2: 0 00055448: 0000: 00022103 00000000 00000000 00000000 t0 write GRAS_DEPTH_CONTROL (2077) GRAS_DEPTH_CONTROL: { FORMAT = DEPTH4_NONE } 00055458: 0000: 00002077 00000000 t0 write RB_STENCIL_INFO (2108) RB_STENCIL_INFO: { STENCIL_BASE = 0 } RB_STENCIL_PITCH: 0 0x210a: 00000000 00055460: 0000: 00022108 00000000 00000000 00000000 t0 write 0x2002 (2002) 0x2002: 00000000 00055470: 0000: 00002002 00000000 t0 write RB_ALPHA_CONTROL (20f8) RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } 00055478: 0000: 000020f8 00000e00 t0 write RB_MRT[0].CONTROL (20a4) RB_MRT[0].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0x7 } 00055480: 0000: 000020a4 07000c00 t0 write RB_MRT[0].BLEND_CONTROL (20a8) RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } 00055488: 0000: 000020a8 00000000 t0 write GRAS_CL_CLIP_CNTL (2000) GRAS_CL_CLIP_CNTL: { 0x80000 } 00055490: 0000: 00002000 00080000 t0 write GRAS_SU_POLY_OFFSET_SCALE (2074) GRAS_SU_POLY_OFFSET_SCALE: 0.000000 GRAS_SU_POLY_OFFSET_OFFSET: 0.000000 GRAS_SU_POLY_OFFSET_CLAMP: 0.000000 00055498: 0000: 00022074 00000000 00000000 00000000 t0 write GRAS_SU_MODE_CONTROL (2078) GRAS_SU_MODE_CONTROL: { FRONT_CW | LINEHALFWIDTH = 0.500000 | MSAA_ENABLE | RENDERING_PASS } 000554a8: 0000: 00002078 00102014 t0 write GRAS_SC_SCREEN_SCISSOR_TL (207c) GRAS_SC_SCREEN_SCISSOR_TL: { X = 2 | Y = 13 } GRAS_SC_SCREEN_SCISSOR_BR: { X = 33 | Y = 44 } 000554b0: 0000: 0001207c 000d0002 002c0021 t0 write GRAS_CL_VPORT_XOFFSET_0 (2008) GRAS_CL_VPORT_XOFFSET_0: 18.000000 GRAS_CL_VPORT_XSCALE_0: 16.000000 GRAS_CL_VPORT_YOFFSET_0: 29.000000 GRAS_CL_VPORT_YSCALE_0: 16.000000 GRAS_CL_VPORT_ZOFFSET_0: 0.500000 GRAS_CL_VPORT_ZSCALE_0: 0.500000 000554bc: 0000: 00052008 41900000 41800000 41e80000 41800000 3f000000 3f000000 t0 write GRAS_CL_GB_CLIP_ADJ (2004) GRAS_CL_GB_CLIP_ADJ: { HORZ = 511 | VERT = 511 } 000554d8: 0000: 00002004 0007fdff t0 write GRAS_SC_CONTROL (207b) GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 4 | RASTER_MODE = 0 } 000554e0: 0000: 0000207b 00000200 t0 write 0x2382 (2382) 0x2382: 00000002 000554e8: 0000: 00002382 00000002 t0 write RB_MSAA_CONTROL (20a2) RB_MSAA_CONTROL: { SAMPLES = 4 } 000554f0: 0000: 000020a2 00008000 t0 write RB_RENDER_CONTROL2 (20a3) RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 4 | IJ_PERSP_PIXEL } 000554f8: 0000: 000020a3 00001200 t0 write RB_MRT[0].BUF_INFO (20a5) RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB4_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_ALWAYS | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 1024 } RB_MRT[0].BASE: 0 RB_MRT[0].CONTROL3: { STRIDE = 64 } 00055500: 0000: 000220a5 0010029a 00000000 00000200 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 43 | GROUP_ID = 2 } { ADDR_LO = 0x99f10 } 00055510: 0000: c0014300 0200002b 00099f10 t0 write 0x215c (215c) 0x215c: 00000000 0x215d: 00000000 0005551c: 0000: 0001215c 00000000 00000000 t0 write 0x215f (215f) 0x215f: 00000000 00055528: 0000: 0000215f 00000000 t0 write 0x215e (215e) 0x215e: 00000000 00055530: 0000: 0000215e 00000000 t0 write 0x2161 (2161) 0x2161: 00000000 0x2162: 00000000 00055538: 0000: 00012161 00000000 00000000 t0 write 0x2164 (2164) 0x2164: 00000000 00055544: 0000: 00002164 00000000 t0 write 0x2163 (2163) 0x2163: 00000000 0005554c: 0000: 00002163 00000000 t0 write 0x2166 (2166) 0x2166: 00000000 0x2167: 00000000 00055554: 0000: 00012166 00000000 00000000 t0 write 0x2169 (2169) 0x2169: 00000000 00055560: 0000: 00002169 00000000 t0 write 0x2168 (2168) 0x2168: 00000000 00055568: 0000: 00002168 00000000 t0 write 0x216b (216b) 0x216b: 00000000 0x216c: 00000000 00055570: 0000: 0001216b 00000000 00000000 t0 write VPC_SO_FLUSH_WADDR_3 (216e) VPC_SO_FLUSH_WADDR_3: 0 0005557c: 0000: 0000216e 00000000 t0 write 0x216d (216d) 0x216d: 00000000 00055584: 0000: 0000216d 00000000 t0 write UNKNOWN_2156 (2156) UNKNOWN_2156: 0 0005558c: 0000: 00002156 00000000 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 18 | GROUP_ID = 1 } { ADDR_LO = 0x99fc0 } 00055594: 0000: c0014300 01000012 00099fc0 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 15 | GROUP_ID = 0 } { ADDR_LO = 0x9a010 } 000555a0: 0000: c0014300 0000000f 0009a010 group_id: 0 count: 15 addr: 000000000009a010 flags: 0 0009a010: 0000: 00002073 00000000 00002101 00000000 00002106 00000000 000021e5 00000000 0009a030: 0020: 0001210b 00000000 00000000 00002381 00000000 000023a0 00000000 t0 write GRAS_ALPHA_CONTROL (2073) GRAS_ALPHA_CONTROL: { 0 } 0009a010: 0000: 00002073 00000000 t0 write RB_DEPTH_CONTROL (2101) RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } 0009a018: 0000: 00002101 00000000 t0 write RB_STENCIL_CONTROL (2106) RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } 0009a020: 0000: 00002106 00000000 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 0009a028: 0000: 000021e5 00000000 t0 write RB_STENCILREFMASK (210b) RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 0009a030: 0000: 0001210b 00000000 00000000 t0 write TPL1_TP_TEX_COUNT (2381) TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } 0009a03c: 0000: 00002381 00000000 t0 write TPL1_TP_FS_TEX_COUNT (23a0) TPL1_TP_FS_TEX_COUNT: 0 0009a044: 0000: 000023a0 00000000 group_id: 1 count: 18 addr: 0000000000099fc0 flags: 0 00099fc0: 0000: 00002200 082a0008 00002201 fcfc0081 00002203 0000fc00 0007220a 0008080f 00099fe0: 0020: 00099e40 00000060 00000001 0000080f 00099e70 00000030 00000001 0001228a 0009a000: 0040: 7000411f 3000011f t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } 00099fc0: 0000: 00002200 082a0008 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } 00099fc8: 0000: 00002201 fcfc0081 t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } 00099fd0: 0000: 00002203 0000fc00 t0 write VFD_FETCH[0].INSTR_0 (220a) VFD_FETCH[0].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 | SWITCHNEXT } VFD_FETCH[0].INSTR_1: 0x99e40 VFD_FETCH[0].INSTR_2: { SIZE = 0x60 } VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 } VFD_FETCH[0x1].INSTR_1: 0x99e70 VFD_FETCH[0x1].INSTR_2: { SIZE = 0x30 } VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } 00099fd8: 0000: 0007220a 0008080f 00099e40 00000060 00000001 0000080f 00099e70 00000030 00099ff8: 0020: 00000001 t0 write VFD_DECODE[0].INSTR (228a) VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID | SWITCHNEXT } VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID } 00099ffc: 0000: 0001228a 7000411f 3000011f group_id: 2 count: 43 addr: 0000000000099f10 flags: 0 00099f10: 0000: 000020a1 00000000 000022f1 0001a100 000022f0 fc00fc01 00002100 00000001 00099f30: 0020: 000021e5 00000000 000020f9 ffff0501 0000214a 00000000 00002140 42001004 00099f50: 0040: 001922c6 0010fc04 00001e00 00000000 00000000 00000000 00000000 00000000 * 00099f90: 0080: 00000000 00000000 00fcfc00 00000008 00000000 00000000 00000000 00000000 * t0 write RB_RENDER_CONTROL (20a1) RB_RENDER_CONTROL: { 0 } 00099f10: 0000: 000020a1 00000000 t0 write SP_FS_MRT[0].REG (22f1) SP_FS_MRT[0].REG: { REGID = r0.x | HALF_PRECISION | MRTFORMAT = RB4_R8G8B8A8_UNORM } 00099f18: 0000: 000022f1 0001a100 t0 write SP_FS_OUTPUT_REG (22f0) SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 00099f20: 0000: 000022f0 fc00fc01 t0 write RB_FS_OUTPUT_REG (2100) RB_FS_OUTPUT_REG: { MRT = 1 } 00099f28: 0000: 00002100 00000001 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 00099f30: 0000: 000021e5 00000000 t0 write RB_FS_OUTPUT (20f9) RB_FS_OUTPUT: { ENABLE_BLEND = 0x1 | INDEPENDENT_BLEND | SAMPLE_MASK = 0xffff | 0x400 } 00099f38: 0000: 000020f9 ffff0501 t0 write VPC_VARYING_PS_REPL[0].MODE (214a) VPC_VARYING_PS_REPL[0].MODE: 0 00099f40: 0000: 0000214a 00000000 t0 write VPC_ATTR (2140) VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 } 00099f48: 0000: 00002140 42001004 t0 write SP_VS_PARAM_REG (22c6) SP_VS_PARAM_REG: { POSREGID = r1.x | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } SP_VS_OUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } UNKNOWN_22D7: 0xfcfc00 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 00099f50: 0000: 001922c6 0010fc04 00001e00 00000000 00000000 00000000 00000000 00000000 * 00099f90: 0040: 00000000 00000000 00fcfc00 00000008 00000000 00000000 00000000 00000000 * group_id: 3 count: 28 addr: 0000000000099ea0 flags: 0 00099ea0: 0000: 000021c4 02000001 00002141 00040400 00002001 00000000 000022c4 00200800 00099ec0: 0020: 000022c5 08000002 0000230c 00000000 00002318 00000000 00002319 00000000 00099ee0: 0040: 00002340 00000000 00002202 fcfcfcfc 00002204 0000fcfc 00002154 00000000 00099f00: 0060: 000021e7 00000000 000021c5 00000012 t0 write PC_PRIM_VTX_CNTL (21c4) PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } 00099ea0: 0000: 000021c4 02000001 t0 write VPC_PACK (2141) VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } 00099ea8: 0000: 00002141 00040400 t0 write UNKNOWN_2001 (2001) UNKNOWN_2001: 0 00099eb0: 0000: 00002001 00000000 t0 write SP_VS_CTRL_REG0 (22c4) SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 2 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 00099eb8: 0000: 000022c4 00200800 t0 write SP_VS_CTRL_REG1 (22c5) SP_VS_CTRL_REG1: { CONSTLENGTH = 2 | INITIALOUTSTANDING = 8 } 00099ec0: 0000: 000022c5 08000002 t0 write 0x230c (230c) 0x230c: 00000000 00099ec8: 0000: 0000230c 00000000 t0 write 0x2318 (2318) 0x2318: 00000000 00099ed0: 0000: 00002318 00000000 t0 write 0x2319 (2319) 0x2319: 00000000 00099ed8: 0000: 00002319 00000000 t0 write 0x2340 (2340) 0x2340: 00000000 00099ee0: 0000: 00002340 00000000 t0 write VFD_CONTROL_2 (2202) VFD_CONTROL_2: 0xfcfcfcfc 00099ee8: 0000: 00002202 fcfcfcfc t0 write VFD_CONTROL_4 (2204) VFD_CONTROL_4: 0xfcfc 00099ef0: 0000: 00002204 0000fcfc t0 write UNKNOWN_2154 (2154) UNKNOWN_2154: 0 00099ef8: 0000: 00002154 00000000 t0 write PC_HS_PARAM (21e7) PC_HS_PARAM: { VERTICES_OUT = 0 | SPACING = EQUAL_SPACING } 00099f00: 0000: 000021e7 00000000 t0 write PC_PRIM_VTX_CNTL2 (21c5) PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 00099f08: 0000: 000021c5 00000012 t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = USE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x200000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 3 } draw[21] register values + 00000000 0xcc4: 00000000 + 00000004 UNKNOWN_0CC5: 0x4 + 80200000 0xd03: 80200000 !+ 00000001 HLSQ_MODE_CONTROL: 0x1 + 00000000 UNKNOWN_0E42: 0 + 00000100 VPC_DEBUG_ECO_CONTROL: 0x100 + 00040000 UNKNOWN_0EC2: 0x40000 !+ 0000001e SP_MODE_CONTROL: 0x1e !+ 00000028 TPL1_TP_MODE_CONTROL: 0x28 !+ 00080000 GRAS_CL_CLIP_CNTL: { 0x80000 } + 00000000 UNKNOWN_2001: 0 + 00000000 0x2002: 00000000 + 00000001 GRAS_CNTL: { IJ_PERSP } + 0007fdff GRAS_CL_GB_CLIP_ADJ: { HORZ = 511 | VERT = 511 } + 41900000 GRAS_CL_VPORT_XOFFSET_0: 18.000000 + 41800000 GRAS_CL_VPORT_XSCALE_0: 16.000000 + 41e80000 GRAS_CL_VPORT_YOFFSET_0: 29.000000 + 41800000 GRAS_CL_VPORT_YSCALE_0: 16.000000 + 3f000000 GRAS_CL_VPORT_ZOFFSET_0: 0.500000 + 3f000000 GRAS_CL_VPORT_ZSCALE_0: 0.500000 + ffc00010 GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 4092.000000 } + 00000008 GRAS_SU_POINT_SIZE: 0.500000 + 00000000 0x2072: 00000000 !+ 00000000 GRAS_ALPHA_CONTROL: { 0 } + 00000000 GRAS_SU_POLY_OFFSET_SCALE: 0.000000 + 00000000 GRAS_SU_POLY_OFFSET_OFFSET: 0.000000 + 00000000 GRAS_SU_POLY_OFFSET_CLAMP: 0.000000 + 00000000 GRAS_DEPTH_CONTROL: { FORMAT = DEPTH4_NONE } !+ 00102014 GRAS_SU_MODE_CONTROL: { FRONT_CW | LINEHALFWIDTH = 0.500000 | MSAA_ENABLE | RENDERING_PASS } !+ 00000200 GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 4 | RASTER_MODE = 0 } !+ 000d0002 GRAS_SC_SCREEN_SCISSOR_TL: { X = 2 | Y = 13 } !+ 002c0021 GRAS_SC_SCREEN_SCISSOR_BR: { X = 33 | Y = 44 } !+ 00000000 RB_RENDER_CONTROL: { 0 } !+ 00008000 RB_MSAA_CONTROL: { SAMPLES = 4 } !+ 00001200 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 4 | IJ_PERSP_PIXEL } !+ 07000c00 RB_MRT[0].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0x7 } !+ 0010029a RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB4_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_ALWAYS | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 1024 } !+ 00000000 RB_MRT[0].BASE: 0 !+ 00000200 RB_MRT[0].CONTROL3: { STRIDE = 64 } + 00000000 RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } + 00000e00 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } !+ ffff0501 RB_FS_OUTPUT: { ENABLE_BLEND = 0x1 | INDEPENDENT_BLEND | SAMPLE_MASK = 0xffff | 0x400 } + 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } + 00000001 RB_FS_OUTPUT_REG: { MRT = 1 } + 00000000 RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } + 00000000 RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTH4_NONE | DEPTH_BASE = 0 } + 00000000 RB_DEPTH_PITCH: 0 + 00000000 RB_DEPTH_PITCH2: 0 + 00000000 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } + 00000000 RB_STENCIL_INFO: { STENCIL_BASE = 0 } + 00000000 RB_STENCIL_PITCH: 0 + 00000000 0x210a: 00000000 + 00000000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } + 00000000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } !+ 42001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 } + 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } !+ 00000000 VPC_VARYING_INTERP[0].MODE: 0 !+ 00000000 VPC_VARYING_PS_REPL[0].MODE: 0 + 00000000 UNKNOWN_2152: 0 + 00000000 UNKNOWN_2153: 0 + 00000000 UNKNOWN_2154: 0 + 00000000 UNKNOWN_2155: 0 + 00000000 UNKNOWN_2156: 0 + 00000000 0x215c: 00000000 + 00000000 0x215d: 00000000 + 00000000 0x215e: 00000000 + 00000000 0x215f: 00000000 + 00000000 0x2161: 00000000 + 00000000 0x2162: 00000000 + 00000000 0x2163: 00000000 + 00000000 0x2164: 00000000 + 00000000 0x2166: 00000000 + 00000000 0x2167: 00000000 + 00000000 0x2168: 00000000 + 00000000 0x2169: 00000000 + 00000000 0x216b: 00000000 + 00000000 0x216c: 00000000 + 00000000 0x216d: 00000000 + 00000000 VPC_SO_FLUSH_WADDR_3: 0 !+ 0000001f UNKNOWN_21C3: 0x1f !+ 02000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + ffffffff PC_RESTART_INDEX: 0xffffffff + 00000000 PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } + 00000001 UNKNOWN_21E6: 0x1 + 00000000 PC_HS_PARAM: { VERTICES_OUT = 0 | SPACING = EQUAL_SPACING } !+ 082a0008 VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } !+ fcfc0081 VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } + fcfcfcfc VFD_CONTROL_2: 0xfcfcfcfc !+ 0000fc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } + 0000fcfc VFD_CONTROL_4: 0xfcfc + 00000000 VFD_INDEX_OFFSET: 0 + 00000000 UNKNOWN_2209: 0 + 0008080f VFD_FETCH[0].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 | SWITCHNEXT } !+ 00099e40 VFD_FETCH[0].INSTR_1: 0x99e40 + 00000060 VFD_FETCH[0].INSTR_2: { SIZE = 0x60 } + 00000001 VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } + 0000080f VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 } !+ 00099e70 VFD_FETCH[0x1].INSTR_1: 0x99e70 + 00000030 VFD_FETCH[0x1].INSTR_2: { SIZE = 0x30 } + 00000001 VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } + 7000411f VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID | SWITCHNEXT } + 3000011f VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID } + 00060010 SP_SP_CTRL_REG: { 0x60010 } + 000005c3 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } !+ 00200800 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 2 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } !+ 08000002 SP_VS_CTRL_REG1: { CONSTLENGTH = 2 | INITIALOUTSTANDING = 8 } !+ 0010fc04 SP_VS_PARAM_REG: { POSREGID = r1.x | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } !+ 00001e00 SP_VS_OUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00fcfc00 UNKNOWN_22D7: 0xfcfc00 + 00000008 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } !+ 00049000 SP_VS_OBJ_START: 0x49000 00049000: 0000: 00000000 13000000 00000000 00000000 00000000 00000000 00000000 00000000 * :0:0000:0000[13000000x_00000000x] (sy)end :0:0001:0001[00000000x_00000000x] nop :0:0002:0002[00000000x_00000000x] nop :0:0003:0003[00000000x_00000000x] nop :0:0004:0004[00000000x_00000000x] nop Stats: - shaderdb: 5 instr, 4 nops, 1 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 0 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 0 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) !+ 00000001 SP_VS_LENGTH_REG: 1 !+ 00340412 SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE } !+ 80100002 SP_FS_CTRL_REG1: { CONSTLENGTH = 2 | VARYING | 0x80000000 } !+ 7e020000 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } !+ 00046000 SP_FS_OBJ_START: 0x46000 00046000: 0000: 00002000 5730cb00 00000000 03000000 00000000 00000000 00000000 00000000 * :2:0000:0000[5730cb00x_00002000x] (sy)(rpt3)bary.f (ei)hr0.x, (r)0, r0.x :0:0001:0004[03000000x_00000000x] end :0:0002:0005[00000000x_00000000x] nop :0:0003:0006[00000000x_00000000x] nop :0:0004:0007[00000000x_00000000x] nop :0:0005:0008[00000000x_00000000x] nop Stats: - shaderdb: 9 instr, 4 nops, 5 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 1 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 4 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) + 00000001 SP_FS_LENGTH_REG: 1 !+ fc00fc01 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r63.x } !+ 0001a100 SP_FS_MRT[0].REG: { REGID = r0.x | HALF_PRECISION | MRTFORMAT = RB4_R8G8B8A8_UNORM } + 00000000 0x230c: 00000000 + 7e020000 SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } + 00000000 SP_HS_OBJ_START: 0 + 00000000 0x2318: 00000000 + 00000000 0x2319: 00000000 + 7e020000 SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } + 00000000 SP_DS_OBJ_START: 0 + 00000000 0x2340: 00000000 + 7e020000 SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } + 00000000 SP_GS_OBJ_START: 0 + 00000808 TPL1_TP_TEX_OFFSET: 0x808 + 00000000 TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } !+ 00000002 0x2382: 00000002 !+ 00000000 TPL1_TP_FS_TEX_COUNT: 0 !+ 080604f0 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0x600a0 } !+ fcfc1108 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x1008 } !+ fff3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } + fcfcfc00 HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } !+ 00fcfc00 HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r0.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } !+ 01010002 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 2 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 1 } !+ 017f0202 HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 2 | CONSTOBJECTOFFSET = 2 | ENABLED | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 } !+ 007e0200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } !+ 007e0200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } !+ 007e0200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } !+ 00000003 HLSQ_UPDATE_CONTROL: 0x3 000555ac: 0000: c0023800 00200984 00000001 00000003 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 18 | GROUP_ID = 1 } { ADDR_LO = 0x9a180 } 000555bc: 0000: c0014300 01000012 0009a180 group_id: 1 count: 18 addr: 000000000009a180 flags: 0 0009a180: 0000: 00002200 082a0008 00002201 fcfc0081 00002203 0000fc00 0007220a 0008080f 0009a1a0: 0020: 0009a120 00000060 00000001 0000080f 0009a150 00000030 00000001 0001228a 0009a1c0: 0040: 7000411f 3000011f t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } 0009a180: 0000: 00002200 082a0008 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } 0009a188: 0000: 00002201 fcfc0081 t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } 0009a190: 0000: 00002203 0000fc00 t0 write VFD_FETCH[0].INSTR_0 (220a) VFD_FETCH[0].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 | SWITCHNEXT } VFD_FETCH[0].INSTR_1: 0x9a120 VFD_FETCH[0].INSTR_2: { SIZE = 0x60 } VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 } VFD_FETCH[0x1].INSTR_1: 0x9a150 VFD_FETCH[0x1].INSTR_2: { SIZE = 0x30 } VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } 0009a198: 0000: 0007220a 0008080f 0009a120 00000060 00000001 0000080f 0009a150 00000030 0009a1b8: 0020: 00000001 t0 write VFD_DECODE[0].INSTR (228a) VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID | SWITCHNEXT } VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID } 0009a1bc: 0000: 0001228a 7000411f 3000011f t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = USE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x200000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 3 } draw[22] register values + 082a0008 VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } + fcfc0081 VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } + 0000fc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } + 0008080f VFD_FETCH[0].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 | SWITCHNEXT } !+ 0009a120 VFD_FETCH[0].INSTR_1: 0x9a120 + 00000060 VFD_FETCH[0].INSTR_2: { SIZE = 0x60 } + 00000001 VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } + 0000080f VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 } !+ 0009a150 VFD_FETCH[0x1].INSTR_1: 0x9a150 + 00000030 VFD_FETCH[0x1].INSTR_2: { SIZE = 0x30 } + 00000001 VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } + 7000411f VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID | SWITCHNEXT } + 3000011f VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID } 000555c8: 0000: c0023800 00200984 00000001 00000003 0016b094: 0000: c0013f00 00055328 000000ac t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 0016b0a0: 0000: c0014300 00040000 00000000 t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:00170f70 ibsize:000000f7 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00170f70: 0000: c0002600 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x4 00170f78: 0000: 00000ec3 00000004 t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x68 00170f80: 0000: 00000f03 00000068 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00170f88: 0000: c0002600 00000000 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } 00170f90: 0000: 000023c0 080004f0 t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = 0x1d } event (null) 00170f98: 0000: c0004600 0000001d t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = FACENESS_FLUSH } event FACENESS_FLUSH 00170fa0: 0000: c0004600 0000001c t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00170fa8: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0 00170fb0: 0000: 00000cc6 00000000 t0 write UNKNOWN_0E42 (0e42) UNKNOWN_0E42: 0 00170fb8: 0000: 00000e42 00000000 t0 write HLSQ_MODE_CONTROL (0e05) HLSQ_MODE_CONTROL: 0x2 00170fc0: 0000: 00000e05 00000002 t0 write UNKNOWN_0CC5 (0cc5) UNKNOWN_0CC5: 0x4 00170fc8: 0000: 00000cc5 00000004 t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x7 00170fd0: 0000: 000023db 00000007 t0 write VFD_CONTROL_2 (2202) VFD_CONTROL_2: 0xfcfcfcfc 00170fd8: 0000: 00002202 fcfcfcfc t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } 00170fe0: 0000: 00002203 fcfcfc00 t0 write VFD_CONTROL_4 (2204) VFD_CONTROL_4: 0xfcfc 00170fe8: 0000: 00002204 0000fcfc t0 write VFD_INDEX_OFFSET (2208) VFD_INDEX_OFFSET: 0 00170ff0: 0000: 00002208 00000000 t0 write UNKNOWN_2209 (2209) UNKNOWN_2209: 0 00170ff8: 0000: 00002209 00000000 t0 write UNKNOWN_2152 (2152) UNKNOWN_2152: 0 UNKNOWN_2153: 0 00171000: 0000: 00012152 00000000 00000000 t0 write UNKNOWN_2156 (2156) UNKNOWN_2156: 0 0017100c: 0000: 00002156 00000000 t0 write UNKNOWN_2154 (2154) UNKNOWN_2154: 0 00171014: 0000: 00002154 00000000 t0 write UNKNOWN_2155 (2155) UNKNOWN_2155: 0 0017101c: 0000: 00002155 00000000 t0 write UNKNOWN_21C3 (21c3) UNKNOWN_21C3: 0x1d 00171024: 0000: 000021c3 0000001d t0 write PC_PRIM_VTX_CNTL2 (21c5) PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 0017102c: 0000: 000021c5 00000012 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 00171034: 0000: 000021e5 00000000 t0 write GRAS_SU_MODE_CONTROL (2078) GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } 0017103c: 0000: 00002078 00000000 t0 write UNKNOWN_2001 (2001) UNKNOWN_2001: 0 00171044: 0000: 00002001 00000000 t0 write GRAS_CNTL (2003) GRAS_CNTL: { IJ_PERSP } 0017104c: 0000: 00002003 00000001 t0 write GRAS_CL_CLIP_CNTL (2000) GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } 00171054: 0000: 00002000 00188000 t0 write TPL1_TP_TEX_COUNT (2381) TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } 0017105c: 0000: 00002381 00000000 t0 write TPL1_TP_FS_TEX_COUNT (23a0) TPL1_TP_FS_TEX_COUNT: 0x3 00171064: 0000: 000023a0 00000003 t0 write RB_ALPHA_CONTROL (20f8) RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } 0017106c: 0000: 000020f8 00000e00 t0 write RB_RENDER_COMPONENTS (20fb) RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } 00171074: 0000: 000020fb 0000000f t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 0017107c: 0000: c0014300 00040000 00000000 t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } 00171088: 0000: 00002200 000a0000 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } 00171090: 0000: 00002201 fc030000 t0 write SP_INSTR_CACHE_CTRL (22c1) SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } 00171098: 0000: 000022c1 000005c3 t0 write HLSQ_CONTROL_1_REG (23c1) HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } 001710a0: 0000: 000023c1 fcfc0120 t0 write HLSQ_CONTROL_2_REG (23c2) HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 001710a8: 0000: 000023c2 27f3f3f0 t0 write HLSQ_VS_CONTROL_REG (23c5) HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } 001710b0: 0000: 000023c5 02010042 t0 write HLSQ_FS_CONTROL_REG (23c6) HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 001710b8: 0000: 000023c6 0041423e t0 write HLSQ_HS_CONTROL_REG (23c7) HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 001710c0: 0000: 000023c7 00404200 t0 write HLSQ_DS_CONTROL_REG (23c8) HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 001710c8: 0000: 000023c8 00404200 t0 write HLSQ_GS_CONTROL_REG (23c9) HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 001710d0: 0000: 000023c9 00404200 t0 write HLSQ_CS_CONTROL_REG (23ca) HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } 001710d8: 0000: 000023ca 00004200 t0 write SP_SP_CTRL_REG (22c0) SP_SP_CTRL_REG: { 0x60010 } 001710e0: 0000: 000022c0 00060010 t0 write UNKNOWN_21E6 (21e6) UNKNOWN_21E6: 0x1 001710e8: 0000: 000021e6 00000001 t0 write SP_VS_CTRL_REG0 (22c4) SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 001710f0: 0000: 000022c4 00200c10 t0 write SP_VS_CTRL_REG1 (22c5) SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } 001710f8: 0000: 000022c5 01000042 t0 write VPC_ATTR (2140) VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | 0x40000000 } 00171100: 0000: 00002140 40001004 t0 write VPC_PACK (2141) VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } 00171108: 0000: 00002141 00040400 t0 write PC_PRIM_VTX_CNTL (21c4) PC_PRIM_VTX_CNTL: { VAROUT = 1 } 00171110: 0000: 000021c4 00000001 t0 write SP_VS_PARAM_REG (22c6) SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } UNKNOWN_22D7: 0xfcfc00 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 00171118: 0000: 001922c6 0010fc03 00001e03 00000000 00000000 00000000 00000000 00000000 * 00171158: 0040: 00000000 00000000 00fcfc00 00000008 00000000 00000000 00000000 00000000 * t0 write SP_VS_OBJ_OFFSET_REG (22e0) SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 00171184: 0000: 000022e0 00000000 t0 write SP_VS_OBJ_START (22e1) SP_VS_OBJ_START: 0x1 0017118c: 0000: 000022e1 00000001 t0 write SP_VS_LENGTH_REG (22e5) SP_VS_LENGTH_REG: 2 00171194: 0000: 000022e5 00000002 t3 opcode: CP_LOAD_STATE4 (30) (67 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } :2:0000:0000[56d81803x_20020003x] (sy)(ss)(nop3) shl.b r0.w, r0.w, 2 :1:0001:0004[20150000x_00000003x] cov.s32s16 hr0.x, r0.w :0:0002:0005[00000200x_00000000x] (rpt2)nop :1:0003:0008[201100f4x_00000000x] mova a0.x, hr0.x :0:0004:0009[00000500x_00000000x] (rpt5)nop :1:0005:0015[20154003x_00000c20x] mov.s32s32 r0.w, c :1:0006:0016[20154004x_00000c21x] mov.s32s32 r1.x, c :1:0007:0017[20154005x_00000c22x] mov.s32s32 r1.y, c :1:0008:0018[20156006x_00000c23x] (ul)mov.s32s32 r1.z, c :0:0009:0019[03000000x_00000000x] end :2:0010:0020[46f00007x_20050000x] shr.b r1.w, r0.x, 5 :2:0011:0021[43980008x_201f0000x] (nop2) and.b r2.x, r0.x, 31 :2:0012:0024[43980807x_201f0007x] (nop3) and.b r1.w, r1.w, 31 :2:0013:0028[46100807x_20100007x] (nop1) mul.u24 r1.w, r1.w, 16 :3:0014:0030[62040007x_00071014x] mad.u24 r1.w, c5.x, r2.x, r1.w :0:0015:0031[00000500x_00000000x] (rpt5)nop :6:0016:0037[c2c60f00x_04800006x] stlw.u32 l[r1.w], r0.w, 4 :0:0017:0038[04800000x_00000000x] chmask :0:0018:0039[05000000x_00000000x] chsh Stats: - shaderdb: 40 instr, 24 nops, 16 non-nops, 5 mov, 1 cov - shaderdb: 0 last-baryf, 0 half, 2 full, 5 constlen - shaderdb: 27 cat0, 6 cat1, 5 cat2, 1 cat3, 0 cat4, 0 cat5, 1 cat6, 0 cat7 - shaderdb: 0 sstall, 1 (ss), 1 (sy) 0017119c: 0000: c0413000 00a00000 00000000 20020003 56d81803 00000003 20150000 00000000 001711bc: 0020: 00000200 00000000 201100f4 00000000 00000500 00000c20 20154003 00000c21 001711dc: 0040: 20154004 00000c22 20154005 00000c23 20156006 00000000 03000000 20050000 001711fc: 0060: 46f00007 201f0000 43980008 201f0007 43980807 20100007 46100807 00071014 0017121c: 0080: 62040007 00000000 00000500 04800006 c2c60f00 00000000 04800000 00000000 0017123c: 00a0: 05000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 * t0 write GRAS_SC_CONTROL (207b) GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = 0 | MSAA_DISABLE | RASTER_MODE = 0 } 001712a8: 0000: 0000207b 00000808 t0 write RB_MSAA_CONTROL (20a2) RB_MSAA_CONTROL: { DISABLE | SAMPLES = 0 } 001712b0: 0000: 000020a2 00001000 t0 write RB_RENDER_CONTROL (20a1) RB_RENDER_CONTROL: { DISABLE_COLOR_PIPE | 0x2 } 001712b8: 0000: 000020a1 00000022 t0 write RB_DEPTH_CONTROL (2101) RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } 001712c0: 0000: 00002101 00000000 t0 write GRAS_ALPHA_CONTROL (2073) GRAS_ALPHA_CONTROL: { 0x2 } 001712c8: 0000: 00002073 00000002 t0 write RB_STENCIL_CONTROL (2106) RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } 001712d0: 0000: 00002106 00000000 t0 write RB_COPY_CONTROL (20fc) RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_FOUR | MODE = RB_COPY_DEPTH_STENCIL | FASTCLEAR = 0 | GMEM_BASE = 0 } RB_COPY_DEST_BASE: { BASE = 0x4f000 } RB_COPY_DEST_PITCH: { PITCH = 256 } RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_DISABLE | COMPONENT_ENABLE = 0xf | ENDIAN = ENDIAN_NONE | TILE = TILE4_3 } 001712d8: 0000: 000320fc 00000052 0004f000 00000008 0303c068 t0 write UNKNOWN_20EF (20ef) UNKNOWN_20EF: 0 001712ec: 0000: 000020ef 00000000 t0 write GRAS_SC_SCREEN_SCISSOR_TL (207c) GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } 001712f4: 0000: 0001207c 00000000 003f003f t0 write RB_FRAME_BUFFER_DIMENSION (0ce0) RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } 00171300: 0000: 00000ce0 00400040 t0 write 0xce1 (0ce1) 0xce1: 00000000 00171308: 0000: 00000ce1 00000000 t3 opcode: CP_LOAD_STATE4 (30) (11 dwords) { DST_OFF = 8 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } 0017131c: 0.000000 0.000000 1.000000 1.000000 64.000000 64.000000 1.000000 1.000000 0017131c: 0000: 00000000 00000000 3f800000 3f800000 42800000 42800000 3f800000 3f800000 00171310: 0000: c0093000 00a00008 00000001 00000000 00000000 3f800000 3f800000 42800000 00171330: 0020: 42800000 3f800000 3f800000 t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x80000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 2 } draw[23] register values + 00000004 UNKNOWN_0CC5: 0x4 + 00000000 UNKNOWN_0CC6: 0 + 00400040 RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } + 00000000 0xce1: 00000000 !+ 00000002 HLSQ_MODE_CONTROL: 0x2 + 00000000 UNKNOWN_0E42: 0 !+ 00000004 SP_MODE_CONTROL: 0x4 !+ 00000068 TPL1_TP_MODE_CONTROL: 0x68 !+ 00188000 GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } + 00000000 UNKNOWN_2001: 0 + 00000001 GRAS_CNTL: { IJ_PERSP } !+ 00000002 GRAS_ALPHA_CONTROL: { 0x2 } !+ 00000000 GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } !+ 00000808 GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = 0 | MSAA_DISABLE | RASTER_MODE = 0 } !+ 00000000 GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } !+ 003f003f GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } !+ 00000022 RB_RENDER_CONTROL: { DISABLE_COLOR_PIPE | 0x2 } !+ 00001000 RB_MSAA_CONTROL: { DISABLE | SAMPLES = 0 } + 00000000 UNKNOWN_20EF: 0 + 00000e00 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } + 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } !+ 00000052 RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_FOUR | MODE = RB_COPY_DEPTH_STENCIL | FASTCLEAR = 0 | GMEM_BASE = 0 } + 0004f000 RB_COPY_DEST_BASE: { BASE = 0x4f000 } + 00000008 RB_COPY_DEST_PITCH: { PITCH = 256 } !+ 0303c068 RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_DISABLE | COMPONENT_ENABLE = 0xf | ENDIAN = ENDIAN_NONE | TILE = TILE4_3 } + 00000000 RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } + 00000000 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } !+ 40001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | 0x40000000 } + 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } + 00000000 UNKNOWN_2152: 0 + 00000000 UNKNOWN_2153: 0 + 00000000 UNKNOWN_2154: 0 + 00000000 UNKNOWN_2155: 0 + 00000000 UNKNOWN_2156: 0 !+ 0000001d UNKNOWN_21C3: 0x1d !+ 00000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 } + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + 00000000 PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } + 00000001 UNKNOWN_21E6: 0x1 !+ 000a0000 VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } !+ fc030000 VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } + fcfcfcfc VFD_CONTROL_2: 0xfcfcfcfc !+ fcfcfc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } + 0000fcfc VFD_CONTROL_4: 0xfcfc + 00000000 VFD_INDEX_OFFSET: 0 + 00000000 UNKNOWN_2209: 0 + 00060010 SP_SP_CTRL_REG: { 0x60010 } + 000005c3 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } !+ 00200c10 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } !+ 01000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } !+ 0010fc03 SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } !+ 00001e03 SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00fcfc00 UNKNOWN_22D7: 0xfcfc00 + 00000008 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } !+ 00000001 SP_VS_OBJ_START: 0x1 !+ 00000002 SP_VS_LENGTH_REG: 2 + 00000000 TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } !+ 00000003 TPL1_TP_FS_TEX_COUNT: 0x3 !+ 080004f0 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } !+ fcfc0120 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } !+ 27f3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } !+ 02010042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } !+ 0041423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } !+ 00404200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } !+ 00404200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } !+ 00404200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00004200 HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } !+ 00000007 HLSQ_UPDATE_CONTROL: 0x7 0017133c: 0000: c0023800 00080888 00000001 00000002 0016b0ac: 0000: c0013f00 00170f70 000000f7 t3 opcode: (null) (1d) (2 dwords) 0016b0b8: 0000: c0001d00 00000000 ############################################################ vertices: 0 ############################################################ cmdstream: 8 dwords t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:000555d8 ibsize:00000155 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 000555d8: 0000: c0002600 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x4 000555e0: 0000: 00000ec3 00000004 t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x68 000555e8: 0000: 00000f03 00000068 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 000555f0: 0000: c0002600 00000000 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } 000555f8: 0000: 000023c0 080004f0 t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = 0x1d } event (null) 00055600: 0000: c0004600 0000001d t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = FACENESS_FLUSH } event FACENESS_FLUSH 00055608: 0000: c0004600 0000001c t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00055610: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0 00055618: 0000: 00000cc6 00000000 t0 write UNKNOWN_0E42 (0e42) UNKNOWN_0E42: 0 00055620: 0000: 00000e42 00000000 t0 write HLSQ_MODE_CONTROL (0e05) HLSQ_MODE_CONTROL: 0x2 00055628: 0000: 00000e05 00000002 t0 write UNKNOWN_0CC5 (0cc5) UNKNOWN_0CC5: 0x4 00055630: 0000: 00000cc5 00000004 t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x7 00055638: 0000: 000023db 00000007 t0 write VFD_CONTROL_2 (2202) VFD_CONTROL_2: 0xfcfcfcfc 00055640: 0000: 00002202 fcfcfcfc t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } 00055648: 0000: 00002203 fcfcfc00 t0 write VFD_CONTROL_4 (2204) VFD_CONTROL_4: 0xfcfc 00055650: 0000: 00002204 0000fcfc t0 write VFD_INDEX_OFFSET (2208) VFD_INDEX_OFFSET: 0 00055658: 0000: 00002208 00000000 t0 write UNKNOWN_2209 (2209) UNKNOWN_2209: 0 00055660: 0000: 00002209 00000000 t0 write UNKNOWN_2152 (2152) UNKNOWN_2152: 0 UNKNOWN_2153: 0 00055668: 0000: 00012152 00000000 00000000 t0 write UNKNOWN_2156 (2156) UNKNOWN_2156: 0 00055674: 0000: 00002156 00000000 t0 write UNKNOWN_2154 (2154) UNKNOWN_2154: 0 0005567c: 0000: 00002154 00000000 t0 write UNKNOWN_2155 (2155) UNKNOWN_2155: 0 00055684: 0000: 00002155 00000000 t0 write UNKNOWN_21C3 (21c3) UNKNOWN_21C3: 0x1d 0005568c: 0000: 000021c3 0000001d t0 write PC_PRIM_VTX_CNTL2 (21c5) PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 00055694: 0000: 000021c5 00000012 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 0005569c: 0000: 000021e5 00000000 t0 write GRAS_SU_MODE_CONTROL (2078) GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } 000556a4: 0000: 00002078 00000000 t0 write UNKNOWN_2001 (2001) UNKNOWN_2001: 0 000556ac: 0000: 00002001 00000000 t0 write GRAS_CNTL (2003) GRAS_CNTL: { IJ_PERSP } 000556b4: 0000: 00002003 00000001 t0 write GRAS_CL_CLIP_CNTL (2000) GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } 000556bc: 0000: 00002000 00188000 t0 write TPL1_TP_TEX_COUNT (2381) TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } 000556c4: 0000: 00002381 00000000 t0 write TPL1_TP_FS_TEX_COUNT (23a0) TPL1_TP_FS_TEX_COUNT: 0x3 000556cc: 0000: 000023a0 00000003 t0 write RB_ALPHA_CONTROL (20f8) RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } 000556d4: 0000: 000020f8 00000e00 t0 write RB_RENDER_COMPONENTS (20fb) RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } 000556dc: 0000: 000020fb 0000000f t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 000556e4: 0000: c0014300 00040000 00000000 t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } 000556f0: 0000: 00002200 000a0000 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } 000556f8: 0000: 00002201 fc030000 t0 write SP_INSTR_CACHE_CTRL (22c1) SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } 00055700: 0000: 000022c1 000005c3 t0 write HLSQ_CONTROL_1_REG (23c1) HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } 00055708: 0000: 000023c1 fcfc0120 t0 write HLSQ_CONTROL_2_REG (23c2) HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 00055710: 0000: 000023c2 27f3f3f0 t0 write HLSQ_VS_CONTROL_REG (23c5) HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } 00055718: 0000: 000023c5 02010042 t0 write HLSQ_FS_CONTROL_REG (23c6) HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 1 } 00055720: 0000: 000023c6 0141423e t0 write HLSQ_HS_CONTROL_REG (23c7) HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00055728: 0000: 000023c7 00404200 t0 write HLSQ_DS_CONTROL_REG (23c8) HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00055730: 0000: 000023c8 00404200 t0 write HLSQ_GS_CONTROL_REG (23c9) HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00055738: 0000: 000023c9 00404200 t0 write HLSQ_CS_CONTROL_REG (23ca) HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } 00055740: 0000: 000023ca 00004200 t0 write SP_SP_CTRL_REG (22c0) SP_SP_CTRL_REG: { 0x60010 } 00055748: 0000: 000022c0 00060010 t0 write UNKNOWN_21E6 (21e6) UNKNOWN_21E6: 0x1 00055750: 0000: 000021e6 00000001 t0 write SP_VS_CTRL_REG0 (22c4) SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 00055758: 0000: 000022c4 00200c10 t0 write SP_VS_CTRL_REG1 (22c5) SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } 00055760: 0000: 000022c5 01000042 t0 write VPC_ATTR (2140) VPC_ATTR: { TOTALATTR = 8 | THRDASSIGN = 1 | ENABLE | 0x40000000 } 00055768: 0000: 00002140 42001008 t0 write VPC_PACK (2141) VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 8 | NUMNONPOSVSVAR = 6 } 00055770: 0000: 00002141 00060800 t0 write PC_PRIM_VTX_CNTL (21c4) PC_PRIM_VTX_CNTL: { VAROUT = 1 } 00055778: 0000: 000021c4 00000001 t0 write SP_VS_PARAM_REG (22c6) SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 2 } SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r1.w | B_COMPMASK = 0x3 } SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } UNKNOWN_22D7: 0xfcfc00 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 12 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 00055780: 0000: 001922c6 0020fc03 06071e03 00000000 00000000 00000000 00000000 00000000 * 000557c0: 0040: 00000000 00000000 00fcfc00 00000c08 00000000 00000000 00000000 00000000 * t0 write SP_VS_OBJ_OFFSET_REG (22e0) SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 000557ec: 0000: 000022e0 00000000 t0 write SP_VS_OBJ_START (22e1) SP_VS_OBJ_START: 0x1 000557f4: 0000: 000022e1 00000001 t0 write SP_VS_LENGTH_REG (22e5) SP_VS_LENGTH_REG: 2 000557fc: 0000: 000022e5 00000002 t3 opcode: CP_LOAD_STATE4 (30) (67 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } :2:0000:0000[56d81803x_20020003x] (sy)(ss)(nop3) shl.b r0.w, r0.w, 2 :1:0001:0004[20150000x_00000003x] cov.s32s16 hr0.x, r0.w :0:0002:0005[00000200x_00000000x] (rpt2)nop :1:0003:0008[201100f4x_00000000x] mova a0.x, hr0.x :0:0004:0009[00000500x_00000000x] (rpt5)nop :1:0005:0015[20154003x_00000c20x] mov.s32s32 r0.w, c :1:0006:0016[20154004x_00000c21x] mov.s32s32 r1.x, c :1:0007:0017[20154007x_00000c22x] mov.s32s32 r1.w, c :1:0008:0018[20156008x_00000c23x] (ul)mov.s32s32 r2.x, c :1:0009:0019[20554005x_00000000x] mov.s32s32 r1.y, 0 :1:0010:0020[20554006x_3f800000x] mov.s32s32 r1.z, 1065353216 :0:0011:0021[03000000x_00000000x] end :2:0012:0022[46f00009x_20050000x] shr.b r2.y, r0.x, 5 :2:0013:0023[4398000ax_201f0000x] (nop2) and.b r2.z, r0.x, 31 :2:0014:0026[43980809x_201f0009x] (nop3) and.b r2.y, r2.y, 31 :2:0015:0030[46100809x_20180009x] (nop1) mul.u24 r2.y, r2.y, 24 :3:0016:0032[62050009x_00091014x] mad.u24 r2.y, c5.x, r2.z, r2.y :0:0017:0033[00000500x_00000000x] (rpt5)nop :6:0018:0039[c2c61300x_04800006x] stlw.u32 l[r2.y], r0.w, 4 :6:0019:0040[c2c61310x_0280000ex] stlw.u32 l[r2.y+16], r1.w, 2 :0:0020:0041[04800000x_00000000x] chmask :0:0021:0042[05000000x_00000000x] chsh Stats: - shaderdb: 43 instr, 24 nops, 19 non-nops, 7 mov, 1 cov - shaderdb: 0 last-baryf, 0 half, 3 full, 5 constlen - shaderdb: 27 cat0, 8 cat1, 5 cat2, 1 cat3, 0 cat4, 0 cat5, 2 cat6, 0 cat7 - shaderdb: 0 sstall, 1 (ss), 1 (sy) 00055804: 0000: c0413000 00a00000 00000000 20020003 56d81803 00000003 20150000 00000000 00055824: 0020: 00000200 00000000 201100f4 00000000 00000500 00000c20 20154003 00000c21 00055844: 0040: 20154004 00000c22 20154007 00000c23 20156008 00000000 20554005 3f800000 00055864: 0060: 20554006 00000000 03000000 20050000 46f00009 201f0000 4398000a 201f0009 00055884: 0080: 43980809 20180009 46100809 00091014 62050009 00000000 00000500 04800006 000558a4: 00a0: c2c61300 0280000e c2c61310 00000000 04800000 00000000 05000000 00000000 * t0 write HLSQ_CONTROL_3_REG (23c3) HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } 00055910: 0000: 000023c3 fcfcfc00 t0 write HLSQ_CONTROL_4_REG (23c4) HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } 00055918: 0000: 000023c4 00fcfcfc t0 write SP_FS_CTRL_REG0 (22e8) SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 0 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE | PIXLODENABLE } SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 } 00055920: 0000: 000122e8 00700402 8010003e t0 write SP_FS_OBJ_OFFSET_REG (22ea) SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 } 0005592c: 0000: 000022ea 40420000 t0 write SP_FS_OBJ_START (22eb) SP_FS_OBJ_START: 0x1 00055934: 0000: 000022eb 00000001 t0 write SP_FS_LENGTH_REG (22ef) SP_FS_LENGTH_REG: 1 0005593c: 0000: 000022ef 00000001 t0 write SP_FS_OUTPUT_REG (22f0) SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r0.x | SAMPLEMASK_REGID = r0.x } 00055944: 0000: 000022f0 00000001 t0 write VPC_VARYING_INTERP[0].MODE (2142) VPC_VARYING_INTERP[0].MODE: 0xe000 0005594c: 0000: 00002142 0000e000 t0 write RB_FS_OUTPUT_REG (2100) RB_FS_OUTPUT_REG: { MRT = 1 } 00055954: 0000: 00002100 00000001 t3 opcode: CP_LOAD_STATE4 (30) (35 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 1 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } :2:0000:0000[57309902x_00002004x] (sy)(ss)(rpt1)bary.f (ei)r0.z, (r)4, r0.x :0:0001:0002[00000500x_00000000x] (rpt5)nop :5:0002:0008[a0c01f00x_00000005x] sam (f32)(xyzw)r0.x, r0.z, s#0, t#0 :0:0003:0009[03000000x_00000000x] end :0:0004:0010[00000000x_00000000x] nop :0:0005:0011[00000000x_00000000x] nop :0:0006:0012[00000000x_00000000x] nop :0:0007:0013[00000000x_00000000x] nop Stats: - shaderdb: 14 instr, 10 nops, 4 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 0 half, 1 full, 0 constlen - shaderdb: 11 cat0, 0 cat1, 2 cat2, 0 cat3, 0 cat4, 1 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 1 (ss), 1 (sy) 0005595c: 0000: c0213000 00700000 00000000 00002004 57309902 00000000 00000500 00000005 0005597c: 0020: a0c01f00 00000000 03000000 00000000 00000000 00000000 00000000 00000000 * t0 write RB_FS_OUTPUT (20f9) RB_FS_OUTPUT: { ENABLE_BLEND = 0 | SAMPLE_MASK = 0xffff } 000559e8: 0000: 000020f9 ffff0000 t0 write RB_MRT[0].CONTROL (20a4) RB_MRT[0].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0xf } 000559f0: 0000: 000020a4 0f000000 t0 write RB_MRT[0x1].CONTROL (20a9) RB_MRT[0x1].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0xf } 000559f8: 0000: 000020a9 0f000000 t0 write RB_MRT[0].BLEND_CONTROL (20a8) RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } 00055a00: 0000: 000020a8 00000000 t3 opcode: CP_LOAD_STATE4 (30) (5 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_TEX | NUM_UNIT = 1 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } { XY_MAG = A4XX_TEX_NEAREST | XY_MIN = A4XX_TEX_NEAREST | WRAP_S = A4XX_TEX_CLAMP_TO_EDGE | WRAP_T = A4XX_TEX_CLAMP_TO_EDGE | WRAP_R = A4XX_TEX_CLAMP_TO_EDGE | ANISO = A4XX_TEX_ANISO_1 | LOD_BIAS = 0.000000 | 0x60000 } { COMPARE_FUNC = FUNC_LEQUAL | UNNORM_COORDS | MIPFILTER_LINEAR_FAR | MAX_LOD = 0.000000 | MIN_LOD = 0.000000 | 0x1 } 00055a14: 0000: 00060920 00000067 00055a08: 0000: c0033000 00500000 00000000 00060920 00000067 t0 write GRAS_SC_CONTROL (207b) GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 0 | RASTER_MODE = 0 } 00055a1c: 0000: 0000207b 00000000 t0 write RB_MSAA_CONTROL (20a2) RB_MSAA_CONTROL: { SAMPLES = 0 } 00055a24: 0000: 000020a2 00000000 t0 write RB_RENDER_CONTROL (20a1) RB_RENDER_CONTROL: { 0 } 00055a2c: 0000: 000020a1 00000000 t0 write 0x2382 (2382) 0x2382: 00000000 00055a34: 0000: 00002382 00000000 t0 write RB_DEPTH_CONTROL (2101) RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } 00055a3c: 0000: 00002101 00000000 t0 write GRAS_ALPHA_CONTROL (2073) GRAS_ALPHA_CONTROL: { 0 } 00055a44: 0000: 00002073 00000000 t0 write RB_STENCIL_CONTROL (2106) RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } 00055a4c: 0000: 00002106 00000000 t0 write SP_FS_MRT[0].REG (22f1) SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = RB4_R8G8B8A8_UNORM } 00055a54: 0000: 000022f1 0001a000 t0 write RB_MRT[0].BUF_INFO (20a5) RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB4_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE4_3 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 256 } RB_MRT[0].BASE: 0x166000 RB_MRT[0].CONTROL3: { STRIDE = 0 } 00055a5c: 0000: 000220a5 000400da 00166000 00000000 t3 opcode: CP_LOAD_STATE4 (30) (11 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_TEX | NUM_UNIT = 1 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } { TILED | SWIZ_X = A4XX_TEX_X | SWIZ_Y = A4XX_TEX_Y | SWIZ_Z = A4XX_TEX_Z | SWIZ_W = A4XX_TEX_W | MIPLVLS = 0 | FMT = TFMT4_8_8_8_8_UNORM | TYPE = A4XX_TEX_2D | 0x2 } { HEIGHT = 64 | WIDTH = 64 } { PITCHALIGN = 0 | PITCH = 256 | SWAP = WZYX } { LAYERSZ = 0 | DEPTH = 1 | 0x20000 } { LAYERSZ = 4096 | BASE = 0x4f000 } { 5 = 0 } { 6 = 0 } { 7 = 0 } 00055a78: 0000: 27006883 00200040 00020000 00060000 0004f001 00000000 00000000 00000000 00055a6c: 0000: c0093000 00500000 00000001 27006883 00200040 00020000 00060000 0004f001 * t0 write VPC_VARYING_PS_REPL[0].MODE (214a) VPC_VARYING_PS_REPL[0].MODE: 0x99999999 00055a98: 0000: 0000214a 99999999 t0 write GRAS_SC_SCREEN_SCISSOR_TL (207c) GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } 00055aa0: 0000: 0001207c 00000000 003f003f t0 write GRAS_SC_WINDOW_SCISSOR_BR (209c) GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 00055aac: 0000: 0001209c 003f003f 00000000 t0 write RB_FRAME_BUFFER_DIMENSION (0ce0) RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } 00055ab8: 0000: 00000ce0 00400040 t0 write 0xce1 (0ce1) 0xce1: 00000000 00055ac0: 0000: 00000ce1 00000000 t0 write RB_RENDER_CONTROL2 (20a3) RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 | IJ_PERSP_PIXEL } 00055ac8: 0000: 000020a3 00001000 t0 write RB_MODE_CONTROL (20a0) RB_MODE_CONTROL: { WIDTH = 0 | HEIGHT = 0 | 0xc00000 } 00055ad0: 0000: 000020a0 00c00000 t3 opcode: CP_LOAD_STATE4 (30) (11 dwords) { DST_OFF = 8 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } 00055ae4: 0.000000 0.000000 0.000000 0.000000 64.000000 64.000000 64.000000 64.000000 00055ae4: 0000: 00000000 00000000 00000000 00000000 42800000 42800000 42800000 42800000 00055ad8: 0000: c0093000 00a00008 00000001 00000000 00000000 00000000 00000000 42800000 00055af8: 0020: 42800000 42800000 42800000 t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x80000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 2 } draw[24] register values + 00000004 UNKNOWN_0CC5: 0x4 + 00000000 UNKNOWN_0CC6: 0 + 00400040 RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } + 00000000 0xce1: 00000000 + 00000002 HLSQ_MODE_CONTROL: 0x2 + 00000000 UNKNOWN_0E42: 0 + 00000004 SP_MODE_CONTROL: 0x4 + 00000068 TPL1_TP_MODE_CONTROL: 0x68 + 00188000 GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } + 00000000 UNKNOWN_2001: 0 + 00000001 GRAS_CNTL: { IJ_PERSP } !+ 00000000 GRAS_ALPHA_CONTROL: { 0 } + 00000000 GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } !+ 00000000 GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 0 | RASTER_MODE = 0 } + 00000000 GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } + 003f003f GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } + 003f003f GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } + 00000000 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } !+ 00c00000 RB_MODE_CONTROL: { WIDTH = 0 | HEIGHT = 0 | 0xc00000 } !+ 00000000 RB_RENDER_CONTROL: { 0 } !+ 00000000 RB_MSAA_CONTROL: { SAMPLES = 0 } !+ 00001000 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 | IJ_PERSP_PIXEL } !+ 0f000000 RB_MRT[0].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0xf } !+ 000400da RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB4_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE4_3 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 256 } !+ 00166000 RB_MRT[0].BASE: 0x166000 !+ 00000000 RB_MRT[0].CONTROL3: { STRIDE = 0 } + 00000000 RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } + 0f000000 RB_MRT[0x1].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0xf } + 00000e00 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } !+ ffff0000 RB_FS_OUTPUT: { ENABLE_BLEND = 0 | SAMPLE_MASK = 0xffff } + 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } + 00000001 RB_FS_OUTPUT_REG: { MRT = 1 } + 00000000 RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } + 00000000 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } !+ 42001008 VPC_ATTR: { TOTALATTR = 8 | THRDASSIGN = 1 | ENABLE | 0x40000000 } !+ 00060800 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 8 | NUMNONPOSVSVAR = 6 } !+ 0000e000 VPC_VARYING_INTERP[0].MODE: 0xe000 !+ 99999999 VPC_VARYING_PS_REPL[0].MODE: 0x99999999 + 00000000 UNKNOWN_2152: 0 + 00000000 UNKNOWN_2153: 0 + 00000000 UNKNOWN_2154: 0 + 00000000 UNKNOWN_2155: 0 + 00000000 UNKNOWN_2156: 0 + 0000001d UNKNOWN_21C3: 0x1d + 00000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 } + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + 00000000 PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } + 00000001 UNKNOWN_21E6: 0x1 + 000a0000 VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } + fc030000 VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } + fcfcfcfc VFD_CONTROL_2: 0xfcfcfcfc + fcfcfc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } + 0000fcfc VFD_CONTROL_4: 0xfcfc + 00000000 VFD_INDEX_OFFSET: 0 + 00000000 UNKNOWN_2209: 0 + 00060010 SP_SP_CTRL_REG: { 0x60010 } + 000005c3 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } + 00200c10 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } + 01000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } !+ 0020fc03 SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 2 } !+ 06071e03 SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r1.w | B_COMPMASK = 0x3 } + 00000000 SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00fcfc00 UNKNOWN_22D7: 0xfcfc00 !+ 00000c08 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 12 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } + 00000001 SP_VS_OBJ_START: 0x1 + 00000002 SP_VS_LENGTH_REG: 2 !+ 00700402 SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 0 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE | PIXLODENABLE } !+ 8010003e SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 } !+ 40420000 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 } !+ 00000001 SP_FS_OBJ_START: 0x1 + 00000001 SP_FS_LENGTH_REG: 1 !+ 00000001 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r0.x | SAMPLEMASK_REGID = r0.x } !+ 0001a000 SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = RB4_R8G8B8A8_UNORM } + 00000000 TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } !+ 00000000 0x2382: 00000000 + 00000003 TPL1_TP_FS_TEX_COUNT: 0x3 + 080004f0 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } + fcfc0120 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } + 27f3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } + fcfcfc00 HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } !+ 00fcfcfc HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } + 02010042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } !+ 0141423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 1 } + 00404200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00004200 HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } + 00000007 HLSQ_UPDATE_CONTROL: 0x7 00055b04: 0000: c0023800 00080888 00000001 00000002 t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = CACHE_FLUSH } event CACHE_FLUSH 00055b14: 0000: c0004600 00000006 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00055b1c: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0x8000012 00055b24: 0000: 00000cc6 08000012 00173000: 0000: c0013f00 000555d8 00000155 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 0017300c: 0000: c0014300 00040000 00000000 t3 opcode: (null) (1d) (2 dwords) 00173018: 0000: c0001d00 00000000 ############################################################ vertices: 0 ############################################################ cmdstream: 48 dwords t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 0016b000: 0000: c0002600 00000000 t0 write UCHE_INVALIDATE0 (0e8a) UCHE_INVALIDATE0: 0 UCHE_INVALIDATE1: 0x12 0016b008: 0000: 00010e8a 00000000 00000012 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 0016b014: 0000: c0002600 00000000 t0 write RB_MODE_CONTROL (20a0) RB_MODE_CONTROL: { WIDTH = 64 | HEIGHT = 64 | ENABLE_GMEM } 0016b01c: 0000: 000020a0 00010202 t0 write RB_FRAME_BUFFER_DIMENSION (0ce0) RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } 0016b024: 0000: 00000ce0 00400040 t0 write 0xce1 (0ce1) 0xce1: 00000001 0016b02c: 0000: 00000ce1 00000001 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 0016b034: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0 0016b03c: 0000: 00000cc6 00000000 t3 opcode: (null) (1d) (2 dwords) 0016b044: 0000: c0001d00 00000000 t0 write GRAS_SC_WINDOW_SCISSOR_BR (209c) GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 0016b04c: 0000: 0001209c 003f003f 00000000 t0 write RB_BIN_OFFSET (210d) RB_BIN_OFFSET: { X = 0 | Y = 0 } 0016b058: 0000: 0000210d 00000000 t0 write GRAS_SC_WINDOW_SCISSOR_BR (209c) GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 0016b060: 0000: 0001209c 003f003f 00000000 t0 write UNKNOWN_2157 (2157) UNKNOWN_2157: 0x1 0016b06c: 0000: 00002157 00000001 t3 opcode: (null) (64) (2 dwords) 0016b074: 0000: c0006400 00000001 t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:00054994 ibsize:000000f6 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00054994: 0000: c0002600 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x4 0005499c: 0000: 00000ec3 00000004 t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x68 000549a4: 0000: 00000f03 00000068 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 000549ac: 0000: c0002600 00000000 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } 000549b4: 0000: 000023c0 080004f0 t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = 0x1d } event (null) 000549bc: 0000: c0004600 0000001d t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = FACENESS_FLUSH } event FACENESS_FLUSH 000549c4: 0000: c0004600 0000001c t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 000549cc: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0 000549d4: 0000: 00000cc6 00000000 t0 write UNKNOWN_0E42 (0e42) UNKNOWN_0E42: 0 000549dc: 0000: 00000e42 00000000 t0 write HLSQ_MODE_CONTROL (0e05) HLSQ_MODE_CONTROL: 0x2 000549e4: 0000: 00000e05 00000002 t0 write UNKNOWN_0CC5 (0cc5) UNKNOWN_0CC5: 0x4 000549ec: 0000: 00000cc5 00000004 t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x7 000549f4: 0000: 000023db 00000007 t0 write VFD_CONTROL_2 (2202) VFD_CONTROL_2: 0xfcfcfcfc 000549fc: 0000: 00002202 fcfcfcfc t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } 00054a04: 0000: 00002203 fcfcfc00 t0 write VFD_CONTROL_4 (2204) VFD_CONTROL_4: 0xfcfc 00054a0c: 0000: 00002204 0000fcfc t0 write VFD_INDEX_OFFSET (2208) VFD_INDEX_OFFSET: 0 00054a14: 0000: 00002208 00000000 t0 write UNKNOWN_2209 (2209) UNKNOWN_2209: 0 00054a1c: 0000: 00002209 00000000 t0 write UNKNOWN_2152 (2152) UNKNOWN_2152: 0 UNKNOWN_2153: 0 00054a24: 0000: 00012152 00000000 00000000 t0 write UNKNOWN_2156 (2156) UNKNOWN_2156: 0 00054a30: 0000: 00002156 00000000 t0 write UNKNOWN_2154 (2154) UNKNOWN_2154: 0 00054a38: 0000: 00002154 00000000 t0 write UNKNOWN_2155 (2155) UNKNOWN_2155: 0 00054a40: 0000: 00002155 00000000 t0 write UNKNOWN_21C3 (21c3) UNKNOWN_21C3: 0x1d 00054a48: 0000: 000021c3 0000001d t0 write PC_PRIM_VTX_CNTL2 (21c5) PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 00054a50: 0000: 000021c5 00000012 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 00054a58: 0000: 000021e5 00000000 t0 write GRAS_SU_MODE_CONTROL (2078) GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } 00054a60: 0000: 00002078 00000000 t0 write UNKNOWN_2001 (2001) UNKNOWN_2001: 0 00054a68: 0000: 00002001 00000000 t0 write GRAS_CNTL (2003) GRAS_CNTL: { IJ_PERSP } 00054a70: 0000: 00002003 00000001 t0 write GRAS_CL_CLIP_CNTL (2000) GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } 00054a78: 0000: 00002000 00188000 t0 write TPL1_TP_TEX_COUNT (2381) TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } 00054a80: 0000: 00002381 00000000 t0 write TPL1_TP_FS_TEX_COUNT (23a0) TPL1_TP_FS_TEX_COUNT: 0x3 00054a88: 0000: 000023a0 00000003 t0 write RB_ALPHA_CONTROL (20f8) RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } 00054a90: 0000: 000020f8 00000e00 t0 write RB_RENDER_COMPONENTS (20fb) RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } 00054a98: 0000: 000020fb 0000000f t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 00054aa0: 0000: c0014300 00040000 00000000 t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } 00054aac: 0000: 00002200 000a0000 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } 00054ab4: 0000: 00002201 fc030000 t0 write SP_INSTR_CACHE_CTRL (22c1) SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } 00054abc: 0000: 000022c1 000005c3 t0 write HLSQ_CONTROL_1_REG (23c1) HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } 00054ac4: 0000: 000023c1 fcfc0120 t0 write HLSQ_CONTROL_2_REG (23c2) HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 00054acc: 0000: 000023c2 27f3f3f0 t0 write HLSQ_VS_CONTROL_REG (23c5) HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } 00054ad4: 0000: 000023c5 02010042 t0 write HLSQ_FS_CONTROL_REG (23c6) HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00054adc: 0000: 000023c6 0041423e t0 write HLSQ_HS_CONTROL_REG (23c7) HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00054ae4: 0000: 000023c7 00404200 t0 write HLSQ_DS_CONTROL_REG (23c8) HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00054aec: 0000: 000023c8 00404200 t0 write HLSQ_GS_CONTROL_REG (23c9) HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00054af4: 0000: 000023c9 00404200 t0 write HLSQ_CS_CONTROL_REG (23ca) HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } 00054afc: 0000: 000023ca 00004200 t0 write SP_SP_CTRL_REG (22c0) SP_SP_CTRL_REG: { 0x60010 } 00054b04: 0000: 000022c0 00060010 t0 write UNKNOWN_21E6 (21e6) UNKNOWN_21E6: 0x1 00054b0c: 0000: 000021e6 00000001 t0 write SP_VS_CTRL_REG0 (22c4) SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 00054b14: 0000: 000022c4 00200c10 t0 write SP_VS_CTRL_REG1 (22c5) SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } 00054b1c: 0000: 000022c5 01000042 t0 write VPC_ATTR (2140) VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | 0x40000000 } 00054b24: 0000: 00002140 40001004 t0 write VPC_PACK (2141) VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } 00054b2c: 0000: 00002141 00040400 t0 write PC_PRIM_VTX_CNTL (21c4) PC_PRIM_VTX_CNTL: { VAROUT = 1 } 00054b34: 0000: 000021c4 00000001 t0 write SP_VS_PARAM_REG (22c6) SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } UNKNOWN_22D7: 0xfcfc00 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 00054b3c: 0000: 001922c6 0010fc03 00001e03 00000000 00000000 00000000 00000000 00000000 * 00054b7c: 0040: 00000000 00000000 00fcfc00 00000008 00000000 00000000 00000000 00000000 * t0 write SP_VS_OBJ_OFFSET_REG (22e0) SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 00054ba8: 0000: 000022e0 00000000 t0 write SP_VS_OBJ_START (22e1) SP_VS_OBJ_START: 0x1 00054bb0: 0000: 000022e1 00000001 t0 write SP_VS_LENGTH_REG (22e5) SP_VS_LENGTH_REG: 2 00054bb8: 0000: 000022e5 00000002 t3 opcode: CP_LOAD_STATE4 (30) (67 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } :2:0000:0000[56d81803x_20020003x] (sy)(ss)(nop3) shl.b r0.w, r0.w, 2 :1:0001:0004[20150000x_00000003x] cov.s32s16 hr0.x, r0.w :0:0002:0005[00000200x_00000000x] (rpt2)nop :1:0003:0008[201100f4x_00000000x] mova a0.x, hr0.x :0:0004:0009[00000500x_00000000x] (rpt5)nop :1:0005:0015[20154003x_00000c20x] mov.s32s32 r0.w, c :1:0006:0016[20154004x_00000c21x] mov.s32s32 r1.x, c :1:0007:0017[20154005x_00000c22x] mov.s32s32 r1.y, c :1:0008:0018[20156006x_00000c23x] (ul)mov.s32s32 r1.z, c :0:0009:0019[03000000x_00000000x] end :2:0010:0020[46f00007x_20050000x] shr.b r1.w, r0.x, 5 :2:0011:0021[43980008x_201f0000x] (nop2) and.b r2.x, r0.x, 31 :2:0012:0024[43980807x_201f0007x] (nop3) and.b r1.w, r1.w, 31 :2:0013:0028[46100807x_20100007x] (nop1) mul.u24 r1.w, r1.w, 16 :3:0014:0030[62040007x_00071014x] mad.u24 r1.w, c5.x, r2.x, r1.w :0:0015:0031[00000500x_00000000x] (rpt5)nop :6:0016:0037[c2c60f00x_04800006x] stlw.u32 l[r1.w], r0.w, 4 :0:0017:0038[04800000x_00000000x] chmask :0:0018:0039[05000000x_00000000x] chsh Stats: - shaderdb: 40 instr, 24 nops, 16 non-nops, 5 mov, 1 cov - shaderdb: 0 last-baryf, 0 half, 2 full, 5 constlen - shaderdb: 27 cat0, 6 cat1, 5 cat2, 1 cat3, 0 cat4, 0 cat5, 1 cat6, 0 cat7 - shaderdb: 0 sstall, 1 (ss), 1 (sy) 00054bc0: 0000: c0413000 00a00000 00000000 20020003 56d81803 00000003 20150000 00000000 00054be0: 0020: 00000200 00000000 201100f4 00000000 00000500 00000c20 20154003 00000c21 00054c00: 0040: 20154004 00000c22 20154005 00000c23 20156006 00000000 03000000 20050000 00054c20: 0060: 46f00007 201f0000 43980008 201f0007 43980807 20100007 46100807 00071014 00054c40: 0080: 62040007 00000000 00000500 04800006 c2c60f00 00000000 04800000 00000000 00054c60: 00a0: 05000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 * t0 write GRAS_ALPHA_CONTROL (2073) GRAS_ALPHA_CONTROL: { 0x2 } 00054ccc: 0000: 00002073 00000002 t0 write GRAS_SC_CONTROL (207b) GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = 4 | MSAA_DISABLE | RASTER_MODE = 0 } 00054cd4: 0000: 0000207b 00000a08 t0 write RB_MSAA_CONTROL (20a2) RB_MSAA_CONTROL: { DISABLE | SAMPLES = 4 } 00054cdc: 0000: 000020a2 00009000 t0 write RB_RENDER_CONTROL (20a1) RB_RENDER_CONTROL: { DISABLE_COLOR_PIPE | 0x2 } 00054ce4: 0000: 000020a1 00000022 t0 write RB_CLEAR_COLOR_DW0 (20cc) RB_CLEAR_COLOR_DW0: 0xff000000 RB_CLEAR_COLOR_DW1: 0 RB_CLEAR_COLOR_DW2: 0 RB_CLEAR_COLOR_DW3: 0 00054cec: 0000: 000320cc ff000000 00000000 00000000 00000000 t0 write RB_COPY_CONTROL (20fc) RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_FOUR | MODE = RB_COPY_CLEAR | FASTCLEAR = 0xf | GMEM_BASE = 0 } RB_COPY_DEST_BASE: { BASE = 0x4f000 } RB_COPY_DEST_PITCH: { PITCH = 256 } RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_IF_ALPHA_OFF | COMPONENT_ENABLE = 0 | ENDIAN = ENDIAN_NONE | TILE = TILE4_3 } 00054d00: 0000: 000320fc 00000f22 0004f000 00000008 03000868 t0 write GRAS_SC_SCREEN_SCISSOR_TL (207c) GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } 00054d14: 0000: 0001207c 00000000 003f003f t0 write RB_FRAME_BUFFER_DIMENSION (0ce0) RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } 00054d20: 0000: 00000ce0 00400040 t0 write 0xce1 (0ce1) 0xce1: 00000000 00054d28: 0000: 00000ce1 00000000 t3 opcode: CP_LOAD_STATE4 (30) (11 dwords) { DST_OFF = 8 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } 00054d3c: 0.000000 0.000000 1.000000 1.000000 64.000000 64.000000 1.000000 1.000000 00054d3c: 0000: 00000000 00000000 3f800000 3f800000 42800000 42800000 3f800000 3f800000 00054d30: 0000: c0093000 00a00008 00000001 00000000 00000000 3f800000 3f800000 42800000 00054d50: 0020: 42800000 3f800000 3f800000 t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x80000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 2 } draw[25] register values + 00000004 UNKNOWN_0CC5: 0x4 + 00000000 UNKNOWN_0CC6: 0 + 00400040 RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } + 00000000 0xce1: 00000000 + 00000002 HLSQ_MODE_CONTROL: 0x2 + 00000000 UNKNOWN_0E42: 0 + 00000000 UCHE_INVALIDATE0: 0 + 00000012 UCHE_INVALIDATE1: 0x12 + 00000004 SP_MODE_CONTROL: 0x4 + 00000068 TPL1_TP_MODE_CONTROL: 0x68 + 00188000 GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } + 00000000 UNKNOWN_2001: 0 + 00000001 GRAS_CNTL: { IJ_PERSP } !+ 00000002 GRAS_ALPHA_CONTROL: { 0x2 } + 00000000 GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } !+ 00000a08 GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = 4 | MSAA_DISABLE | RASTER_MODE = 0 } + 00000000 GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } + 003f003f GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } + 003f003f GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } + 00000000 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } !+ 00010202 RB_MODE_CONTROL: { WIDTH = 64 | HEIGHT = 64 | ENABLE_GMEM } !+ 00000022 RB_RENDER_CONTROL: { DISABLE_COLOR_PIPE | 0x2 } !+ 00009000 RB_MSAA_CONTROL: { DISABLE | SAMPLES = 4 } + ff000000 RB_CLEAR_COLOR_DW0: 0xff000000 + 00000000 RB_CLEAR_COLOR_DW1: 0 + 00000000 RB_CLEAR_COLOR_DW2: 0 + 00000000 RB_CLEAR_COLOR_DW3: 0 + 00000e00 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } + 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } !+ 00000f22 RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_FOUR | MODE = RB_COPY_CLEAR | FASTCLEAR = 0xf | GMEM_BASE = 0 } + 0004f000 RB_COPY_DEST_BASE: { BASE = 0x4f000 } + 00000008 RB_COPY_DEST_PITCH: { PITCH = 256 } !+ 03000868 RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_IF_ALPHA_OFF | COMPONENT_ENABLE = 0 | ENDIAN = ENDIAN_NONE | TILE = TILE4_3 } + 00000000 RB_BIN_OFFSET: { X = 0 | Y = 0 } !+ 40001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | 0x40000000 } !+ 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } + 00000000 UNKNOWN_2152: 0 + 00000000 UNKNOWN_2153: 0 + 00000000 UNKNOWN_2154: 0 + 00000000 UNKNOWN_2155: 0 + 00000000 UNKNOWN_2156: 0 + 00000001 UNKNOWN_2157: 0x1 + 0000001d UNKNOWN_21C3: 0x1d + 00000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 } + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + 00000000 PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } + 00000001 UNKNOWN_21E6: 0x1 + 000a0000 VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } + fc030000 VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } + fcfcfcfc VFD_CONTROL_2: 0xfcfcfcfc + fcfcfc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } + 0000fcfc VFD_CONTROL_4: 0xfcfc + 00000000 VFD_INDEX_OFFSET: 0 + 00000000 UNKNOWN_2209: 0 + 00060010 SP_SP_CTRL_REG: { 0x60010 } + 000005c3 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } + 00200c10 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } + 01000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } !+ 0010fc03 SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } !+ 00001e03 SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00fcfc00 UNKNOWN_22D7: 0xfcfc00 !+ 00000008 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } + 00000001 SP_VS_OBJ_START: 0x1 + 00000002 SP_VS_LENGTH_REG: 2 + 00000000 TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } + 00000003 TPL1_TP_FS_TEX_COUNT: 0x3 + 080004f0 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } + fcfc0120 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } + 27f3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } + 02010042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } !+ 0041423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00004200 HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } + 00000007 HLSQ_UPDATE_CONTROL: 0x7 00054d5c: 0000: c0023800 00080888 00000001 00000002 0016b07c: 0000: c0013f00 00054994 000000f6 t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:00054d6c ibsize:00000037 t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } 00054d6c: 0000: 00002200 082a0008 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00054d74: 0000: c0002600 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x1e 00054d7c: 0000: 00000ec3 0000001e t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x28 00054d84: 0000: 00000f03 00000028 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00054d8c: 0000: c0002600 00000000 t0 write HLSQ_MODE_CONTROL (0e05) HLSQ_MODE_CONTROL: 0x1 00054d94: 0000: 00000e05 00000001 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0x600a0 } 00054d9c: 0000: 000023c0 080604f0 t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x7 00054da4: 0000: 000023db 00000007 t0 write PC_RESTART_INDEX (21c6) PC_RESTART_INDEX: 0xffffffff 00054dac: 0000: 000021c6 ffffffff t0 write UNKNOWN_21E6 (21e6) UNKNOWN_21E6: 0x1 00054db4: 0000: 000021e6 00000001 t0 write UNKNOWN_21C3 (21c3) UNKNOWN_21C3: 0x1f 00054dbc: 0000: 000021c3 0000001f t0 write TPL1_TP_TEX_OFFSET (2380) TPL1_TP_TEX_OFFSET: 0x808 00054dc4: 0000: 00002380 00000808 t0 write GRAS_SU_POINT_MINMAX (2070) GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 4092.000000 } GRAS_SU_POINT_SIZE: 0.500000 00054dcc: 0000: 00012070 ffc00010 00000008 t0 write UNKNOWN_2152 (2152) UNKNOWN_2152: 0 UNKNOWN_2153: 0 00054dd8: 0000: 00012152 00000000 00000000 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00054de4: 0000: c0002600 00000000 t0 write UNKNOWN_0CC5 (0cc5) UNKNOWN_0CC5: 0x4 00054dec: 0000: 00000cc5 00000004 t0 write 0xcc4 (0cc4) 0xcc4: 00000000 00054df4: 0000: 00000cc4 00000000 t0 write 0xd03 (0d03) 0xd03: 80200000 00054dfc: 0000: 00000d03 80200000 t0 write UNKNOWN_0EC2 (0ec2) UNKNOWN_0EC2: 0x40000 00054e04: 0000: 00000ec2 00040000 t0 write VPC_DEBUG_ECO_CONTROL (0e64) VPC_DEBUG_ECO_CONTROL: 0x100 00054e0c: 0000: 00000e64 00000100 t0 write UNKNOWN_0E42 (0e42) UNKNOWN_0E42: 0 00054e14: 0000: 00000e42 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x1e 00054e1c: 0000: 00000ec3 0000001e t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x28 00054e24: 0000: 00000f03 00000028 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 00054e2c: 0000: c0014300 00040000 00000000 t0 write VFD_INDEX_OFFSET (2208) VFD_INDEX_OFFSET: 0 00054e38: 0000: 00002208 00000000 t0 write UNKNOWN_2209 (2209) UNKNOWN_2209: 0 00054e40: 0000: 00002209 00000000 0016b088: 0000: c0013f00 00054d6c 00000037 t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:00055328 ibsize:000000ac t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x3 00055328: 0000: 000023db 00000003 t0 write SP_INSTR_CACHE_CTRL (22c1) SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } 00055330: 0000: 000022c1 000005c3 t0 write HLSQ_CONTROL_1_REG (23c1) HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x1008 } 00055338: 0000: 000023c1 fcfc1108 t0 write HLSQ_CONTROL_2_REG (23c2) HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 00055340: 0000: 000023c2 fff3f3f0 t0 write HLSQ_VS_CONTROL_REG (23c5) HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 2 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 1 } 00055348: 0000: 000023c5 01010002 t0 write HLSQ_HS_CONTROL_REG (23c7) HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 00055350: 0000: 000023c7 007e0200 t0 write HLSQ_DS_CONTROL_REG (23c8) HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 00055358: 0000: 000023c8 007e0200 t0 write HLSQ_GS_CONTROL_REG (23c9) HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 00055360: 0000: 000023c9 007e0200 t0 write HLSQ_FS_CONTROL_REG (23c6) HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 2 | CONSTOBJECTOFFSET = 2 | ENABLED | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 } 00055368: 0000: 000023c6 017f0202 t0 write SP_VS_OBJ_OFFSET_REG (22e0) SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 00055370: 0000: 000022e0 00000000 t0 write SP_HS_OBJ_OFFSET_REG (230d) SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } 00055378: 0000: 0000230d 7e020000 t0 write SP_DS_OBJ_OFFSET_REG (2334) SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } 00055380: 0000: 00002334 7e020000 t0 write SP_GS_OBJ_OFFSET_REG (235b) SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } 00055388: 0000: 0000235b 7e020000 t0 write SP_FS_OBJ_OFFSET_REG (22ea) SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } 00055390: 0000: 000022ea 7e020000 t0 write SP_VS_OBJ_START (22e1) SP_VS_OBJ_START: 0x49000 00049000: 0000: 00000000 13000000 00000000 00000000 00000000 00000000 00000000 00000000 * :0:0000:0000[13000000x_00000000x] (sy)end :0:0001:0001[00000000x_00000000x] nop :0:0002:0002[00000000x_00000000x] nop :0:0003:0003[00000000x_00000000x] nop :0:0004:0004[00000000x_00000000x] nop Stats: - shaderdb: 5 instr, 4 nops, 1 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 0 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 0 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) 00055398: 0000: 000022e1 00049000 t0 write SP_HS_OBJ_START (230e) SP_HS_OBJ_START: 0 000553a0: 0000: 0000230e 00000000 t0 write SP_DS_OBJ_START (2335) SP_DS_OBJ_START: 0 000553a8: 0000: 00002335 00000000 t0 write SP_GS_OBJ_START (235c) SP_GS_OBJ_START: 0 000553b0: 0000: 0000235c 00000000 t0 write SP_VS_LENGTH_REG (22e5) SP_VS_LENGTH_REG: 1 000553b8: 0000: 000022e5 00000001 t3 opcode: CP_LOAD_STATE4 (30) (3 dwords) { DST_OFF = 0 | STATE_SRC = SS4_INDIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 1 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0x49000 } :0:0000:0000[13000000x_00000000x] (sy)end :0:0001:0001[00000000x_00000000x] nop :0:0002:0002[00000000x_00000000x] nop :0:0003:0003[00000000x_00000000x] nop :0:0004:0004[00000000x_00000000x] nop Stats: - shaderdb: 5 instr, 4 nops, 1 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 0 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 0 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) 000553c0: 0000: c0013000 00620000 00049000 t0 write 0x2072 (2072) 0x2072: 00000000 000553cc: 0000: 00002072 00000000 t0 write UNKNOWN_2155 (2155) UNKNOWN_2155: 0 000553d4: 0000: 00002155 00000000 t0 write GRAS_CNTL (2003) GRAS_CNTL: { IJ_PERSP } 000553dc: 0000: 00002003 00000001 t0 write VPC_VARYING_INTERP[0].MODE (2142) VPC_VARYING_INTERP[0].MODE: 0 000553e4: 0000: 00002142 00000000 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0x600a0 } 000553ec: 0000: 000023c0 080604f0 t0 write HLSQ_CONTROL_3_REG (23c3) HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } 000553f4: 0000: 000023c3 fcfcfc00 t0 write HLSQ_CONTROL_4_REG (23c4) HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r0.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } 000553fc: 0000: 000023c4 00fcfc00 t0 write SP_FS_CTRL_REG0 (22e8) SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE } SP_FS_CTRL_REG1: { CONSTLENGTH = 2 | VARYING | 0x80000000 } 00055404: 0000: 000122e8 00340412 80100002 t0 write SP_FS_OBJ_START (22eb) SP_FS_OBJ_START: 0x46000 00046000: 0000: 00002000 5730cb00 00000000 03000000 00000000 00000000 00000000 00000000 * :2:0000:0000[5730cb00x_00002000x] (sy)(rpt3)bary.f (ei)hr0.x, (r)0, r0.x :0:0001:0004[03000000x_00000000x] end :0:0002:0005[00000000x_00000000x] nop :0:0003:0006[00000000x_00000000x] nop :0:0004:0007[00000000x_00000000x] nop :0:0005:0008[00000000x_00000000x] nop Stats: - shaderdb: 9 instr, 4 nops, 5 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 1 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 4 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) 00055410: 0000: 000022eb 00046000 t0 write SP_FS_LENGTH_REG (22ef) SP_FS_LENGTH_REG: 1 00055418: 0000: 000022ef 00000001 t0 write RB_RENDER_COMPONENTS (20fb) RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } 00055420: 0000: 000020fb 0000000f t3 opcode: CP_LOAD_STATE4 (30) (3 dwords) { DST_OFF = 0 | STATE_SRC = SS4_INDIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 1 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0x46000 } :2:0000:0000[5730cb00x_00002000x] (sy)(rpt3)bary.f (ei)hr0.x, (r)0, r0.x :0:0001:0004[03000000x_00000000x] end :0:0002:0005[00000000x_00000000x] nop :0:0003:0006[00000000x_00000000x] nop :0:0004:0007[00000000x_00000000x] nop :0:0005:0008[00000000x_00000000x] nop Stats: - shaderdb: 9 instr, 4 nops, 5 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 1 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 4 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) 00055428: 0000: c0013000 00720000 00046000 t0 write SP_SP_CTRL_REG (22c0) SP_SP_CTRL_REG: { 0x60010 } 00055434: 0000: 000022c0 00060010 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 28 | GROUP_ID = 3 } { ADDR_LO = 0x9a230 } 0005543c: 0000: c0014300 0300001c 0009a230 t0 write RB_DEPTH_INFO (2103) RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTH4_NONE | DEPTH_BASE = 0 } RB_DEPTH_PITCH: 0 RB_DEPTH_PITCH2: 0 00055448: 0000: 00022103 00000000 00000000 00000000 t0 write GRAS_DEPTH_CONTROL (2077) GRAS_DEPTH_CONTROL: { FORMAT = DEPTH4_NONE } 00055458: 0000: 00002077 00000000 t0 write RB_STENCIL_INFO (2108) RB_STENCIL_INFO: { STENCIL_BASE = 0 } RB_STENCIL_PITCH: 0 0x210a: 00000000 00055460: 0000: 00022108 00000000 00000000 00000000 t0 write 0x2002 (2002) 0x2002: 00000000 00055470: 0000: 00002002 00000000 t0 write RB_ALPHA_CONTROL (20f8) RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } 00055478: 0000: 000020f8 00000e00 t0 write RB_MRT[0].CONTROL (20a4) RB_MRT[0].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0x7 } 00055480: 0000: 000020a4 07000c00 t0 write RB_MRT[0].BLEND_CONTROL (20a8) RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } 00055488: 0000: 000020a8 00000000 t0 write GRAS_CL_CLIP_CNTL (2000) GRAS_CL_CLIP_CNTL: { 0x80000 } 00055490: 0000: 00002000 00080000 t0 write GRAS_SU_POLY_OFFSET_SCALE (2074) GRAS_SU_POLY_OFFSET_SCALE: 0.000000 GRAS_SU_POLY_OFFSET_OFFSET: 0.000000 GRAS_SU_POLY_OFFSET_CLAMP: 0.000000 00055498: 0000: 00022074 00000000 00000000 00000000 t0 write GRAS_SU_MODE_CONTROL (2078) GRAS_SU_MODE_CONTROL: { FRONT_CW | LINEHALFWIDTH = 0.500000 | MSAA_ENABLE | RENDERING_PASS } 000554a8: 0000: 00002078 00102014 t0 write GRAS_SC_SCREEN_SCISSOR_TL (207c) GRAS_SC_SCREEN_SCISSOR_TL: { X = 2 | Y = 13 } GRAS_SC_SCREEN_SCISSOR_BR: { X = 33 | Y = 44 } 000554b0: 0000: 0001207c 000d0002 002c0021 t0 write GRAS_CL_VPORT_XOFFSET_0 (2008) GRAS_CL_VPORT_XOFFSET_0: 18.000000 GRAS_CL_VPORT_XSCALE_0: 16.000000 GRAS_CL_VPORT_YOFFSET_0: 29.000000 GRAS_CL_VPORT_YSCALE_0: 16.000000 GRAS_CL_VPORT_ZOFFSET_0: 0.500000 GRAS_CL_VPORT_ZSCALE_0: 0.500000 000554bc: 0000: 00052008 41900000 41800000 41e80000 41800000 3f000000 3f000000 t0 write GRAS_CL_GB_CLIP_ADJ (2004) GRAS_CL_GB_CLIP_ADJ: { HORZ = 511 | VERT = 511 } 000554d8: 0000: 00002004 0007fdff t0 write GRAS_SC_CONTROL (207b) GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 4 | RASTER_MODE = 0 } 000554e0: 0000: 0000207b 00000200 t0 write 0x2382 (2382) 0x2382: 00000002 000554e8: 0000: 00002382 00000002 t0 write RB_MSAA_CONTROL (20a2) RB_MSAA_CONTROL: { SAMPLES = 4 } 000554f0: 0000: 000020a2 00008000 t0 write RB_RENDER_CONTROL2 (20a3) RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 4 | IJ_PERSP_PIXEL } 000554f8: 0000: 000020a3 00001200 t0 write RB_MRT[0].BUF_INFO (20a5) RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB4_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_ALWAYS | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 1024 } RB_MRT[0].BASE: 0 RB_MRT[0].CONTROL3: { STRIDE = 64 } 00055500: 0000: 000220a5 0010029a 00000000 00000200 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 43 | GROUP_ID = 2 } { ADDR_LO = 0x9a2a0 } 00055510: 0000: c0014300 0200002b 0009a2a0 t0 write 0x215c (215c) 0x215c: 00000000 0x215d: 00000000 0005551c: 0000: 0001215c 00000000 00000000 t0 write 0x215f (215f) 0x215f: 00000000 00055528: 0000: 0000215f 00000000 t0 write 0x215e (215e) 0x215e: 00000000 00055530: 0000: 0000215e 00000000 t0 write 0x2161 (2161) 0x2161: 00000000 0x2162: 00000000 00055538: 0000: 00012161 00000000 00000000 t0 write 0x2164 (2164) 0x2164: 00000000 00055544: 0000: 00002164 00000000 t0 write 0x2163 (2163) 0x2163: 00000000 0005554c: 0000: 00002163 00000000 t0 write 0x2166 (2166) 0x2166: 00000000 0x2167: 00000000 00055554: 0000: 00012166 00000000 00000000 t0 write 0x2169 (2169) 0x2169: 00000000 00055560: 0000: 00002169 00000000 t0 write 0x2168 (2168) 0x2168: 00000000 00055568: 0000: 00002168 00000000 t0 write 0x216b (216b) 0x216b: 00000000 0x216c: 00000000 00055570: 0000: 0001216b 00000000 00000000 t0 write VPC_SO_FLUSH_WADDR_3 (216e) VPC_SO_FLUSH_WADDR_3: 0 0005557c: 0000: 0000216e 00000000 t0 write 0x216d (216d) 0x216d: 00000000 00055584: 0000: 0000216d 00000000 t0 write UNKNOWN_2156 (2156) UNKNOWN_2156: 0 0005558c: 0000: 00002156 00000000 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 18 | GROUP_ID = 1 } { ADDR_LO = 0x9a350 } 00055594: 0000: c0014300 01000012 0009a350 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 15 | GROUP_ID = 0 } { ADDR_LO = 0x9a3a0 } 000555a0: 0000: c0014300 0000000f 0009a3a0 group_id: 0 count: 15 addr: 000000000009a3a0 flags: 0 0009a3a0: 0000: 00002073 00000000 00002101 00000000 00002106 00000000 000021e5 00000000 0009a3c0: 0020: 0001210b 00000000 00000000 00002381 00000000 000023a0 00000000 t0 write GRAS_ALPHA_CONTROL (2073) GRAS_ALPHA_CONTROL: { 0 } 0009a3a0: 0000: 00002073 00000000 t0 write RB_DEPTH_CONTROL (2101) RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } 0009a3a8: 0000: 00002101 00000000 t0 write RB_STENCIL_CONTROL (2106) RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } 0009a3b0: 0000: 00002106 00000000 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 0009a3b8: 0000: 000021e5 00000000 t0 write RB_STENCILREFMASK (210b) RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 0009a3c0: 0000: 0001210b 00000000 00000000 t0 write TPL1_TP_TEX_COUNT (2381) TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } 0009a3cc: 0000: 00002381 00000000 t0 write TPL1_TP_FS_TEX_COUNT (23a0) TPL1_TP_FS_TEX_COUNT: 0 0009a3d4: 0000: 000023a0 00000000 group_id: 1 count: 18 addr: 000000000009a350 flags: 0 0009a350: 0000: 00002200 082a0008 00002201 fcfc0081 00002203 0000fc00 0007220a 0008080f 0009a370: 0020: 0009a1d0 00000060 00000001 0000080f 0009a200 00000030 00000001 0001228a 0009a390: 0040: 7000411f 3000011f t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } 0009a350: 0000: 00002200 082a0008 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } 0009a358: 0000: 00002201 fcfc0081 t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } 0009a360: 0000: 00002203 0000fc00 t0 write VFD_FETCH[0].INSTR_0 (220a) VFD_FETCH[0].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 | SWITCHNEXT } VFD_FETCH[0].INSTR_1: 0x9a1d0 VFD_FETCH[0].INSTR_2: { SIZE = 0x60 } VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 } VFD_FETCH[0x1].INSTR_1: 0x9a200 VFD_FETCH[0x1].INSTR_2: { SIZE = 0x30 } VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } 0009a368: 0000: 0007220a 0008080f 0009a1d0 00000060 00000001 0000080f 0009a200 00000030 0009a388: 0020: 00000001 t0 write VFD_DECODE[0].INSTR (228a) VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID | SWITCHNEXT } VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID } 0009a38c: 0000: 0001228a 7000411f 3000011f group_id: 2 count: 43 addr: 000000000009a2a0 flags: 0 0009a2a0: 0000: 000020a1 00000000 000022f1 0001a100 000022f0 fc00fc01 00002100 00000001 0009a2c0: 0020: 000021e5 00000000 000020f9 ffff0501 0000214a 00000000 00002140 42001004 0009a2e0: 0040: 001922c6 0010fc04 00001e00 00000000 00000000 00000000 00000000 00000000 * 0009a320: 0080: 00000000 00000000 00fcfc00 00000008 00000000 00000000 00000000 00000000 * t0 write RB_RENDER_CONTROL (20a1) RB_RENDER_CONTROL: { 0 } 0009a2a0: 0000: 000020a1 00000000 t0 write SP_FS_MRT[0].REG (22f1) SP_FS_MRT[0].REG: { REGID = r0.x | HALF_PRECISION | MRTFORMAT = RB4_R8G8B8A8_UNORM } 0009a2a8: 0000: 000022f1 0001a100 t0 write SP_FS_OUTPUT_REG (22f0) SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 0009a2b0: 0000: 000022f0 fc00fc01 t0 write RB_FS_OUTPUT_REG (2100) RB_FS_OUTPUT_REG: { MRT = 1 } 0009a2b8: 0000: 00002100 00000001 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 0009a2c0: 0000: 000021e5 00000000 t0 write RB_FS_OUTPUT (20f9) RB_FS_OUTPUT: { ENABLE_BLEND = 0x1 | INDEPENDENT_BLEND | SAMPLE_MASK = 0xffff | 0x400 } 0009a2c8: 0000: 000020f9 ffff0501 t0 write VPC_VARYING_PS_REPL[0].MODE (214a) VPC_VARYING_PS_REPL[0].MODE: 0 0009a2d0: 0000: 0000214a 00000000 t0 write VPC_ATTR (2140) VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 } 0009a2d8: 0000: 00002140 42001004 t0 write SP_VS_PARAM_REG (22c6) SP_VS_PARAM_REG: { POSREGID = r1.x | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } SP_VS_OUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } UNKNOWN_22D7: 0xfcfc00 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 0009a2e0: 0000: 001922c6 0010fc04 00001e00 00000000 00000000 00000000 00000000 00000000 * 0009a320: 0040: 00000000 00000000 00fcfc00 00000008 00000000 00000000 00000000 00000000 * group_id: 3 count: 28 addr: 000000000009a230 flags: 0 0009a230: 0000: 000021c4 02000001 00002141 00040400 00002001 00000000 000022c4 00200800 0009a250: 0020: 000022c5 08000002 0000230c 00000000 00002318 00000000 00002319 00000000 0009a270: 0040: 00002340 00000000 00002202 fcfcfcfc 00002204 0000fcfc 00002154 00000000 0009a290: 0060: 000021e7 00000000 000021c5 00000012 t0 write PC_PRIM_VTX_CNTL (21c4) PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } 0009a230: 0000: 000021c4 02000001 t0 write VPC_PACK (2141) VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } 0009a238: 0000: 00002141 00040400 t0 write UNKNOWN_2001 (2001) UNKNOWN_2001: 0 0009a240: 0000: 00002001 00000000 t0 write SP_VS_CTRL_REG0 (22c4) SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 2 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 0009a248: 0000: 000022c4 00200800 t0 write SP_VS_CTRL_REG1 (22c5) SP_VS_CTRL_REG1: { CONSTLENGTH = 2 | INITIALOUTSTANDING = 8 } 0009a250: 0000: 000022c5 08000002 t0 write 0x230c (230c) 0x230c: 00000000 0009a258: 0000: 0000230c 00000000 t0 write 0x2318 (2318) 0x2318: 00000000 0009a260: 0000: 00002318 00000000 t0 write 0x2319 (2319) 0x2319: 00000000 0009a268: 0000: 00002319 00000000 t0 write 0x2340 (2340) 0x2340: 00000000 0009a270: 0000: 00002340 00000000 t0 write VFD_CONTROL_2 (2202) VFD_CONTROL_2: 0xfcfcfcfc 0009a278: 0000: 00002202 fcfcfcfc t0 write VFD_CONTROL_4 (2204) VFD_CONTROL_4: 0xfcfc 0009a280: 0000: 00002204 0000fcfc t0 write UNKNOWN_2154 (2154) UNKNOWN_2154: 0 0009a288: 0000: 00002154 00000000 t0 write PC_HS_PARAM (21e7) PC_HS_PARAM: { VERTICES_OUT = 0 | SPACING = EQUAL_SPACING } 0009a290: 0000: 000021e7 00000000 t0 write PC_PRIM_VTX_CNTL2 (21c5) PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 0009a298: 0000: 000021c5 00000012 t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = USE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x200000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 3 } draw[26] register values + 00000000 0xcc4: 00000000 + 00000004 UNKNOWN_0CC5: 0x4 + 80200000 0xd03: 80200000 !+ 00000001 HLSQ_MODE_CONTROL: 0x1 + 00000000 UNKNOWN_0E42: 0 + 00000100 VPC_DEBUG_ECO_CONTROL: 0x100 + 00040000 UNKNOWN_0EC2: 0x40000 !+ 0000001e SP_MODE_CONTROL: 0x1e !+ 00000028 TPL1_TP_MODE_CONTROL: 0x28 !+ 00080000 GRAS_CL_CLIP_CNTL: { 0x80000 } + 00000000 UNKNOWN_2001: 0 + 00000000 0x2002: 00000000 + 00000001 GRAS_CNTL: { IJ_PERSP } + 0007fdff GRAS_CL_GB_CLIP_ADJ: { HORZ = 511 | VERT = 511 } + 41900000 GRAS_CL_VPORT_XOFFSET_0: 18.000000 + 41800000 GRAS_CL_VPORT_XSCALE_0: 16.000000 + 41e80000 GRAS_CL_VPORT_YOFFSET_0: 29.000000 + 41800000 GRAS_CL_VPORT_YSCALE_0: 16.000000 + 3f000000 GRAS_CL_VPORT_ZOFFSET_0: 0.500000 + 3f000000 GRAS_CL_VPORT_ZSCALE_0: 0.500000 + ffc00010 GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 4092.000000 } + 00000008 GRAS_SU_POINT_SIZE: 0.500000 + 00000000 0x2072: 00000000 !+ 00000000 GRAS_ALPHA_CONTROL: { 0 } + 00000000 GRAS_SU_POLY_OFFSET_SCALE: 0.000000 + 00000000 GRAS_SU_POLY_OFFSET_OFFSET: 0.000000 + 00000000 GRAS_SU_POLY_OFFSET_CLAMP: 0.000000 + 00000000 GRAS_DEPTH_CONTROL: { FORMAT = DEPTH4_NONE } !+ 00102014 GRAS_SU_MODE_CONTROL: { FRONT_CW | LINEHALFWIDTH = 0.500000 | MSAA_ENABLE | RENDERING_PASS } !+ 00000200 GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 4 | RASTER_MODE = 0 } !+ 000d0002 GRAS_SC_SCREEN_SCISSOR_TL: { X = 2 | Y = 13 } !+ 002c0021 GRAS_SC_SCREEN_SCISSOR_BR: { X = 33 | Y = 44 } !+ 00000000 RB_RENDER_CONTROL: { 0 } !+ 00008000 RB_MSAA_CONTROL: { SAMPLES = 4 } !+ 00001200 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 4 | IJ_PERSP_PIXEL } !+ 07000c00 RB_MRT[0].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0x7 } !+ 0010029a RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB4_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_ALWAYS | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 1024 } !+ 00000000 RB_MRT[0].BASE: 0 !+ 00000200 RB_MRT[0].CONTROL3: { STRIDE = 64 } + 00000000 RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } + 00000e00 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } !+ ffff0501 RB_FS_OUTPUT: { ENABLE_BLEND = 0x1 | INDEPENDENT_BLEND | SAMPLE_MASK = 0xffff | 0x400 } + 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } + 00000001 RB_FS_OUTPUT_REG: { MRT = 1 } + 00000000 RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } + 00000000 RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTH4_NONE | DEPTH_BASE = 0 } + 00000000 RB_DEPTH_PITCH: 0 + 00000000 RB_DEPTH_PITCH2: 0 + 00000000 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } + 00000000 RB_STENCIL_INFO: { STENCIL_BASE = 0 } + 00000000 RB_STENCIL_PITCH: 0 + 00000000 0x210a: 00000000 + 00000000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } + 00000000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } !+ 42001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 } + 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } !+ 00000000 VPC_VARYING_INTERP[0].MODE: 0 !+ 00000000 VPC_VARYING_PS_REPL[0].MODE: 0 + 00000000 UNKNOWN_2152: 0 + 00000000 UNKNOWN_2153: 0 + 00000000 UNKNOWN_2154: 0 + 00000000 UNKNOWN_2155: 0 + 00000000 UNKNOWN_2156: 0 + 00000000 0x215c: 00000000 + 00000000 0x215d: 00000000 + 00000000 0x215e: 00000000 + 00000000 0x215f: 00000000 + 00000000 0x2161: 00000000 + 00000000 0x2162: 00000000 + 00000000 0x2163: 00000000 + 00000000 0x2164: 00000000 + 00000000 0x2166: 00000000 + 00000000 0x2167: 00000000 + 00000000 0x2168: 00000000 + 00000000 0x2169: 00000000 + 00000000 0x216b: 00000000 + 00000000 0x216c: 00000000 + 00000000 0x216d: 00000000 + 00000000 VPC_SO_FLUSH_WADDR_3: 0 !+ 0000001f UNKNOWN_21C3: 0x1f !+ 02000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + ffffffff PC_RESTART_INDEX: 0xffffffff + 00000000 PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } + 00000001 UNKNOWN_21E6: 0x1 + 00000000 PC_HS_PARAM: { VERTICES_OUT = 0 | SPACING = EQUAL_SPACING } !+ 082a0008 VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } !+ fcfc0081 VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } + fcfcfcfc VFD_CONTROL_2: 0xfcfcfcfc !+ 0000fc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } + 0000fcfc VFD_CONTROL_4: 0xfcfc + 00000000 VFD_INDEX_OFFSET: 0 + 00000000 UNKNOWN_2209: 0 + 0008080f VFD_FETCH[0].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 | SWITCHNEXT } !+ 0009a1d0 VFD_FETCH[0].INSTR_1: 0x9a1d0 + 00000060 VFD_FETCH[0].INSTR_2: { SIZE = 0x60 } + 00000001 VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } + 0000080f VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 } !+ 0009a200 VFD_FETCH[0x1].INSTR_1: 0x9a200 + 00000030 VFD_FETCH[0x1].INSTR_2: { SIZE = 0x30 } + 00000001 VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } + 7000411f VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID | SWITCHNEXT } + 3000011f VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID } + 00060010 SP_SP_CTRL_REG: { 0x60010 } + 000005c3 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } !+ 00200800 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 2 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } !+ 08000002 SP_VS_CTRL_REG1: { CONSTLENGTH = 2 | INITIALOUTSTANDING = 8 } !+ 0010fc04 SP_VS_PARAM_REG: { POSREGID = r1.x | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } !+ 00001e00 SP_VS_OUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00fcfc00 UNKNOWN_22D7: 0xfcfc00 + 00000008 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } !+ 00049000 SP_VS_OBJ_START: 0x49000 00049000: 0000: 00000000 13000000 00000000 00000000 00000000 00000000 00000000 00000000 * :0:0000:0000[13000000x_00000000x] (sy)end :0:0001:0001[00000000x_00000000x] nop :0:0002:0002[00000000x_00000000x] nop :0:0003:0003[00000000x_00000000x] nop :0:0004:0004[00000000x_00000000x] nop Stats: - shaderdb: 5 instr, 4 nops, 1 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 0 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 0 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) !+ 00000001 SP_VS_LENGTH_REG: 1 !+ 00340412 SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE } !+ 80100002 SP_FS_CTRL_REG1: { CONSTLENGTH = 2 | VARYING | 0x80000000 } !+ 7e020000 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } !+ 00046000 SP_FS_OBJ_START: 0x46000 00046000: 0000: 00002000 5730cb00 00000000 03000000 00000000 00000000 00000000 00000000 * :2:0000:0000[5730cb00x_00002000x] (sy)(rpt3)bary.f (ei)hr0.x, (r)0, r0.x :0:0001:0004[03000000x_00000000x] end :0:0002:0005[00000000x_00000000x] nop :0:0003:0006[00000000x_00000000x] nop :0:0004:0007[00000000x_00000000x] nop :0:0005:0008[00000000x_00000000x] nop Stats: - shaderdb: 9 instr, 4 nops, 5 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 1 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 4 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) + 00000001 SP_FS_LENGTH_REG: 1 !+ fc00fc01 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r63.x } !+ 0001a100 SP_FS_MRT[0].REG: { REGID = r0.x | HALF_PRECISION | MRTFORMAT = RB4_R8G8B8A8_UNORM } + 00000000 0x230c: 00000000 + 7e020000 SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } + 00000000 SP_HS_OBJ_START: 0 + 00000000 0x2318: 00000000 + 00000000 0x2319: 00000000 + 7e020000 SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } + 00000000 SP_DS_OBJ_START: 0 + 00000000 0x2340: 00000000 + 7e020000 SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } + 00000000 SP_GS_OBJ_START: 0 + 00000808 TPL1_TP_TEX_OFFSET: 0x808 + 00000000 TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } !+ 00000002 0x2382: 00000002 !+ 00000000 TPL1_TP_FS_TEX_COUNT: 0 !+ 080604f0 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0x600a0 } !+ fcfc1108 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x1008 } !+ fff3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } + fcfcfc00 HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } !+ 00fcfc00 HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r0.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } !+ 01010002 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 2 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 1 } !+ 017f0202 HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 2 | CONSTOBJECTOFFSET = 2 | ENABLED | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 } !+ 007e0200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } !+ 007e0200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } !+ 007e0200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } !+ 00000003 HLSQ_UPDATE_CONTROL: 0x3 000555ac: 0000: c0023800 00200984 00000001 00000003 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 18 | GROUP_ID = 1 } { ADDR_LO = 0x9a510 } 000555bc: 0000: c0014300 01000012 0009a510 group_id: 1 count: 18 addr: 000000000009a510 flags: 0 0009a510: 0000: 00002200 082a0008 00002201 fcfc0081 00002203 0000fc00 0007220a 0008080f 0009a530: 0020: 0009a4b0 00000060 00000001 0000080f 0009a4e0 00000030 00000001 0001228a 0009a550: 0040: 7000411f 3000011f t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } 0009a510: 0000: 00002200 082a0008 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } 0009a518: 0000: 00002201 fcfc0081 t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } 0009a520: 0000: 00002203 0000fc00 t0 write VFD_FETCH[0].INSTR_0 (220a) VFD_FETCH[0].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 | SWITCHNEXT } VFD_FETCH[0].INSTR_1: 0x9a4b0 VFD_FETCH[0].INSTR_2: { SIZE = 0x60 } VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 } VFD_FETCH[0x1].INSTR_1: 0x9a4e0 VFD_FETCH[0x1].INSTR_2: { SIZE = 0x30 } VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } 0009a528: 0000: 0007220a 0008080f 0009a4b0 00000060 00000001 0000080f 0009a4e0 00000030 0009a548: 0020: 00000001 t0 write VFD_DECODE[0].INSTR (228a) VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID | SWITCHNEXT } VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID } 0009a54c: 0000: 0001228a 7000411f 3000011f t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = USE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x200000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 3 } draw[27] register values + 082a0008 VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } + fcfc0081 VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } + 0000fc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } + 0008080f VFD_FETCH[0].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 | SWITCHNEXT } !+ 0009a4b0 VFD_FETCH[0].INSTR_1: 0x9a4b0 + 00000060 VFD_FETCH[0].INSTR_2: { SIZE = 0x60 } + 00000001 VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } + 0000080f VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 } !+ 0009a4e0 VFD_FETCH[0x1].INSTR_1: 0x9a4e0 + 00000030 VFD_FETCH[0x1].INSTR_2: { SIZE = 0x30 } + 00000001 VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } + 7000411f VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID | SWITCHNEXT } + 3000011f VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID } 000555c8: 0000: c0023800 00200984 00000001 00000003 0016b094: 0000: c0013f00 00055328 000000ac t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 0016b0a0: 0000: c0014300 00040000 00000000 t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:0017134c ibsize:000000f7 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 0017134c: 0000: c0002600 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x4 00171354: 0000: 00000ec3 00000004 t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x68 0017135c: 0000: 00000f03 00000068 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00171364: 0000: c0002600 00000000 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } 0017136c: 0000: 000023c0 080004f0 t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = 0x1d } event (null) 00171374: 0000: c0004600 0000001d t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = FACENESS_FLUSH } event FACENESS_FLUSH 0017137c: 0000: c0004600 0000001c t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00171384: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0 0017138c: 0000: 00000cc6 00000000 t0 write UNKNOWN_0E42 (0e42) UNKNOWN_0E42: 0 00171394: 0000: 00000e42 00000000 t0 write HLSQ_MODE_CONTROL (0e05) HLSQ_MODE_CONTROL: 0x2 0017139c: 0000: 00000e05 00000002 t0 write UNKNOWN_0CC5 (0cc5) UNKNOWN_0CC5: 0x4 001713a4: 0000: 00000cc5 00000004 t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x7 001713ac: 0000: 000023db 00000007 t0 write VFD_CONTROL_2 (2202) VFD_CONTROL_2: 0xfcfcfcfc 001713b4: 0000: 00002202 fcfcfcfc t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } 001713bc: 0000: 00002203 fcfcfc00 t0 write VFD_CONTROL_4 (2204) VFD_CONTROL_4: 0xfcfc 001713c4: 0000: 00002204 0000fcfc t0 write VFD_INDEX_OFFSET (2208) VFD_INDEX_OFFSET: 0 001713cc: 0000: 00002208 00000000 t0 write UNKNOWN_2209 (2209) UNKNOWN_2209: 0 001713d4: 0000: 00002209 00000000 t0 write UNKNOWN_2152 (2152) UNKNOWN_2152: 0 UNKNOWN_2153: 0 001713dc: 0000: 00012152 00000000 00000000 t0 write UNKNOWN_2156 (2156) UNKNOWN_2156: 0 001713e8: 0000: 00002156 00000000 t0 write UNKNOWN_2154 (2154) UNKNOWN_2154: 0 001713f0: 0000: 00002154 00000000 t0 write UNKNOWN_2155 (2155) UNKNOWN_2155: 0 001713f8: 0000: 00002155 00000000 t0 write UNKNOWN_21C3 (21c3) UNKNOWN_21C3: 0x1d 00171400: 0000: 000021c3 0000001d t0 write PC_PRIM_VTX_CNTL2 (21c5) PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 00171408: 0000: 000021c5 00000012 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 00171410: 0000: 000021e5 00000000 t0 write GRAS_SU_MODE_CONTROL (2078) GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } 00171418: 0000: 00002078 00000000 t0 write UNKNOWN_2001 (2001) UNKNOWN_2001: 0 00171420: 0000: 00002001 00000000 t0 write GRAS_CNTL (2003) GRAS_CNTL: { IJ_PERSP } 00171428: 0000: 00002003 00000001 t0 write GRAS_CL_CLIP_CNTL (2000) GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } 00171430: 0000: 00002000 00188000 t0 write TPL1_TP_TEX_COUNT (2381) TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } 00171438: 0000: 00002381 00000000 t0 write TPL1_TP_FS_TEX_COUNT (23a0) TPL1_TP_FS_TEX_COUNT: 0x3 00171440: 0000: 000023a0 00000003 t0 write RB_ALPHA_CONTROL (20f8) RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } 00171448: 0000: 000020f8 00000e00 t0 write RB_RENDER_COMPONENTS (20fb) RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } 00171450: 0000: 000020fb 0000000f t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 00171458: 0000: c0014300 00040000 00000000 t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } 00171464: 0000: 00002200 000a0000 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } 0017146c: 0000: 00002201 fc030000 t0 write SP_INSTR_CACHE_CTRL (22c1) SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } 00171474: 0000: 000022c1 000005c3 t0 write HLSQ_CONTROL_1_REG (23c1) HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } 0017147c: 0000: 000023c1 fcfc0120 t0 write HLSQ_CONTROL_2_REG (23c2) HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 00171484: 0000: 000023c2 27f3f3f0 t0 write HLSQ_VS_CONTROL_REG (23c5) HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } 0017148c: 0000: 000023c5 02010042 t0 write HLSQ_FS_CONTROL_REG (23c6) HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00171494: 0000: 000023c6 0041423e t0 write HLSQ_HS_CONTROL_REG (23c7) HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 0017149c: 0000: 000023c7 00404200 t0 write HLSQ_DS_CONTROL_REG (23c8) HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 001714a4: 0000: 000023c8 00404200 t0 write HLSQ_GS_CONTROL_REG (23c9) HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 001714ac: 0000: 000023c9 00404200 t0 write HLSQ_CS_CONTROL_REG (23ca) HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } 001714b4: 0000: 000023ca 00004200 t0 write SP_SP_CTRL_REG (22c0) SP_SP_CTRL_REG: { 0x60010 } 001714bc: 0000: 000022c0 00060010 t0 write UNKNOWN_21E6 (21e6) UNKNOWN_21E6: 0x1 001714c4: 0000: 000021e6 00000001 t0 write SP_VS_CTRL_REG0 (22c4) SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 001714cc: 0000: 000022c4 00200c10 t0 write SP_VS_CTRL_REG1 (22c5) SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } 001714d4: 0000: 000022c5 01000042 t0 write VPC_ATTR (2140) VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | 0x40000000 } 001714dc: 0000: 00002140 40001004 t0 write VPC_PACK (2141) VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } 001714e4: 0000: 00002141 00040400 t0 write PC_PRIM_VTX_CNTL (21c4) PC_PRIM_VTX_CNTL: { VAROUT = 1 } 001714ec: 0000: 000021c4 00000001 t0 write SP_VS_PARAM_REG (22c6) SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } UNKNOWN_22D7: 0xfcfc00 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 001714f4: 0000: 001922c6 0010fc03 00001e03 00000000 00000000 00000000 00000000 00000000 * 00171534: 0040: 00000000 00000000 00fcfc00 00000008 00000000 00000000 00000000 00000000 * t0 write SP_VS_OBJ_OFFSET_REG (22e0) SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 00171560: 0000: 000022e0 00000000 t0 write SP_VS_OBJ_START (22e1) SP_VS_OBJ_START: 0x1 00171568: 0000: 000022e1 00000001 t0 write SP_VS_LENGTH_REG (22e5) SP_VS_LENGTH_REG: 2 00171570: 0000: 000022e5 00000002 t3 opcode: CP_LOAD_STATE4 (30) (67 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } :2:0000:0000[56d81803x_20020003x] (sy)(ss)(nop3) shl.b r0.w, r0.w, 2 :1:0001:0004[20150000x_00000003x] cov.s32s16 hr0.x, r0.w :0:0002:0005[00000200x_00000000x] (rpt2)nop :1:0003:0008[201100f4x_00000000x] mova a0.x, hr0.x :0:0004:0009[00000500x_00000000x] (rpt5)nop :1:0005:0015[20154003x_00000c20x] mov.s32s32 r0.w, c :1:0006:0016[20154004x_00000c21x] mov.s32s32 r1.x, c :1:0007:0017[20154005x_00000c22x] mov.s32s32 r1.y, c :1:0008:0018[20156006x_00000c23x] (ul)mov.s32s32 r1.z, c :0:0009:0019[03000000x_00000000x] end :2:0010:0020[46f00007x_20050000x] shr.b r1.w, r0.x, 5 :2:0011:0021[43980008x_201f0000x] (nop2) and.b r2.x, r0.x, 31 :2:0012:0024[43980807x_201f0007x] (nop3) and.b r1.w, r1.w, 31 :2:0013:0028[46100807x_20100007x] (nop1) mul.u24 r1.w, r1.w, 16 :3:0014:0030[62040007x_00071014x] mad.u24 r1.w, c5.x, r2.x, r1.w :0:0015:0031[00000500x_00000000x] (rpt5)nop :6:0016:0037[c2c60f00x_04800006x] stlw.u32 l[r1.w], r0.w, 4 :0:0017:0038[04800000x_00000000x] chmask :0:0018:0039[05000000x_00000000x] chsh Stats: - shaderdb: 40 instr, 24 nops, 16 non-nops, 5 mov, 1 cov - shaderdb: 0 last-baryf, 0 half, 2 full, 5 constlen - shaderdb: 27 cat0, 6 cat1, 5 cat2, 1 cat3, 0 cat4, 0 cat5, 1 cat6, 0 cat7 - shaderdb: 0 sstall, 1 (ss), 1 (sy) 00171578: 0000: c0413000 00a00000 00000000 20020003 56d81803 00000003 20150000 00000000 00171598: 0020: 00000200 00000000 201100f4 00000000 00000500 00000c20 20154003 00000c21 001715b8: 0040: 20154004 00000c22 20154005 00000c23 20156006 00000000 03000000 20050000 001715d8: 0060: 46f00007 201f0000 43980008 201f0007 43980807 20100007 46100807 00071014 001715f8: 0080: 62040007 00000000 00000500 04800006 c2c60f00 00000000 04800000 00000000 00171618: 00a0: 05000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 * t0 write GRAS_SC_CONTROL (207b) GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = 0 | MSAA_DISABLE | RASTER_MODE = 0 } 00171684: 0000: 0000207b 00000808 t0 write RB_MSAA_CONTROL (20a2) RB_MSAA_CONTROL: { DISABLE | SAMPLES = 0 } 0017168c: 0000: 000020a2 00001000 t0 write RB_RENDER_CONTROL (20a1) RB_RENDER_CONTROL: { DISABLE_COLOR_PIPE | 0x2 } 00171694: 0000: 000020a1 00000022 t0 write RB_DEPTH_CONTROL (2101) RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } 0017169c: 0000: 00002101 00000000 t0 write GRAS_ALPHA_CONTROL (2073) GRAS_ALPHA_CONTROL: { 0x2 } 001716a4: 0000: 00002073 00000002 t0 write RB_STENCIL_CONTROL (2106) RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } 001716ac: 0000: 00002106 00000000 t0 write RB_COPY_CONTROL (20fc) RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_FOUR | MODE = RB_COPY_DEPTH_STENCIL | FASTCLEAR = 0 | GMEM_BASE = 0 } RB_COPY_DEST_BASE: { BASE = 0x4f000 } RB_COPY_DEST_PITCH: { PITCH = 256 } RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_DISABLE | COMPONENT_ENABLE = 0xf | ENDIAN = ENDIAN_NONE | TILE = TILE4_3 } 001716b4: 0000: 000320fc 00000052 0004f000 00000008 0303c068 t0 write UNKNOWN_20EF (20ef) UNKNOWN_20EF: 0 001716c8: 0000: 000020ef 00000000 t0 write GRAS_SC_SCREEN_SCISSOR_TL (207c) GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } 001716d0: 0000: 0001207c 00000000 003f003f t0 write RB_FRAME_BUFFER_DIMENSION (0ce0) RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } 001716dc: 0000: 00000ce0 00400040 t0 write 0xce1 (0ce1) 0xce1: 00000000 001716e4: 0000: 00000ce1 00000000 t3 opcode: CP_LOAD_STATE4 (30) (11 dwords) { DST_OFF = 8 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } 001716f8: 0.000000 0.000000 1.000000 1.000000 64.000000 64.000000 1.000000 1.000000 001716f8: 0000: 00000000 00000000 3f800000 3f800000 42800000 42800000 3f800000 3f800000 001716ec: 0000: c0093000 00a00008 00000001 00000000 00000000 3f800000 3f800000 42800000 0017170c: 0020: 42800000 3f800000 3f800000 t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x80000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 2 } draw[28] register values + 00000004 UNKNOWN_0CC5: 0x4 + 00000000 UNKNOWN_0CC6: 0 + 00400040 RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } + 00000000 0xce1: 00000000 !+ 00000002 HLSQ_MODE_CONTROL: 0x2 + 00000000 UNKNOWN_0E42: 0 !+ 00000004 SP_MODE_CONTROL: 0x4 !+ 00000068 TPL1_TP_MODE_CONTROL: 0x68 !+ 00188000 GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } + 00000000 UNKNOWN_2001: 0 + 00000001 GRAS_CNTL: { IJ_PERSP } !+ 00000002 GRAS_ALPHA_CONTROL: { 0x2 } !+ 00000000 GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } !+ 00000808 GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = 0 | MSAA_DISABLE | RASTER_MODE = 0 } !+ 00000000 GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } !+ 003f003f GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } !+ 00000022 RB_RENDER_CONTROL: { DISABLE_COLOR_PIPE | 0x2 } !+ 00001000 RB_MSAA_CONTROL: { DISABLE | SAMPLES = 0 } + 00000000 UNKNOWN_20EF: 0 + 00000e00 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } + 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } !+ 00000052 RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_FOUR | MODE = RB_COPY_DEPTH_STENCIL | FASTCLEAR = 0 | GMEM_BASE = 0 } + 0004f000 RB_COPY_DEST_BASE: { BASE = 0x4f000 } + 00000008 RB_COPY_DEST_PITCH: { PITCH = 256 } !+ 0303c068 RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_DISABLE | COMPONENT_ENABLE = 0xf | ENDIAN = ENDIAN_NONE | TILE = TILE4_3 } + 00000000 RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } + 00000000 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } !+ 40001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | 0x40000000 } + 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } + 00000000 UNKNOWN_2152: 0 + 00000000 UNKNOWN_2153: 0 + 00000000 UNKNOWN_2154: 0 + 00000000 UNKNOWN_2155: 0 + 00000000 UNKNOWN_2156: 0 !+ 0000001d UNKNOWN_21C3: 0x1d !+ 00000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 } + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + 00000000 PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } + 00000001 UNKNOWN_21E6: 0x1 !+ 000a0000 VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } !+ fc030000 VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } + fcfcfcfc VFD_CONTROL_2: 0xfcfcfcfc !+ fcfcfc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } + 0000fcfc VFD_CONTROL_4: 0xfcfc + 00000000 VFD_INDEX_OFFSET: 0 + 00000000 UNKNOWN_2209: 0 + 00060010 SP_SP_CTRL_REG: { 0x60010 } + 000005c3 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } !+ 00200c10 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } !+ 01000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } !+ 0010fc03 SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } !+ 00001e03 SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00fcfc00 UNKNOWN_22D7: 0xfcfc00 + 00000008 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } !+ 00000001 SP_VS_OBJ_START: 0x1 !+ 00000002 SP_VS_LENGTH_REG: 2 + 00000000 TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } !+ 00000003 TPL1_TP_FS_TEX_COUNT: 0x3 !+ 080004f0 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } !+ fcfc0120 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } !+ 27f3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } !+ 02010042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } !+ 0041423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } !+ 00404200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } !+ 00404200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } !+ 00404200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00004200 HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } !+ 00000007 HLSQ_UPDATE_CONTROL: 0x7 00171718: 0000: c0023800 00080888 00000001 00000002 0016b0ac: 0000: c0013f00 0017134c 000000f7 t3 opcode: (null) (1d) (2 dwords) 0016b0b8: 0000: c0001d00 00000000 ############################################################ vertices: 0 ############################################################ cmdstream: 8 dwords t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:000555d8 ibsize:00000155 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 000555d8: 0000: c0002600 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x4 000555e0: 0000: 00000ec3 00000004 t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x68 000555e8: 0000: 00000f03 00000068 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 000555f0: 0000: c0002600 00000000 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } 000555f8: 0000: 000023c0 080004f0 t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = 0x1d } event (null) 00055600: 0000: c0004600 0000001d t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = FACENESS_FLUSH } event FACENESS_FLUSH 00055608: 0000: c0004600 0000001c t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00055610: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0 00055618: 0000: 00000cc6 00000000 t0 write UNKNOWN_0E42 (0e42) UNKNOWN_0E42: 0 00055620: 0000: 00000e42 00000000 t0 write HLSQ_MODE_CONTROL (0e05) HLSQ_MODE_CONTROL: 0x2 00055628: 0000: 00000e05 00000002 t0 write UNKNOWN_0CC5 (0cc5) UNKNOWN_0CC5: 0x4 00055630: 0000: 00000cc5 00000004 t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x7 00055638: 0000: 000023db 00000007 t0 write VFD_CONTROL_2 (2202) VFD_CONTROL_2: 0xfcfcfcfc 00055640: 0000: 00002202 fcfcfcfc t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } 00055648: 0000: 00002203 fcfcfc00 t0 write VFD_CONTROL_4 (2204) VFD_CONTROL_4: 0xfcfc 00055650: 0000: 00002204 0000fcfc t0 write VFD_INDEX_OFFSET (2208) VFD_INDEX_OFFSET: 0 00055658: 0000: 00002208 00000000 t0 write UNKNOWN_2209 (2209) UNKNOWN_2209: 0 00055660: 0000: 00002209 00000000 t0 write UNKNOWN_2152 (2152) UNKNOWN_2152: 0 UNKNOWN_2153: 0 00055668: 0000: 00012152 00000000 00000000 t0 write UNKNOWN_2156 (2156) UNKNOWN_2156: 0 00055674: 0000: 00002156 00000000 t0 write UNKNOWN_2154 (2154) UNKNOWN_2154: 0 0005567c: 0000: 00002154 00000000 t0 write UNKNOWN_2155 (2155) UNKNOWN_2155: 0 00055684: 0000: 00002155 00000000 t0 write UNKNOWN_21C3 (21c3) UNKNOWN_21C3: 0x1d 0005568c: 0000: 000021c3 0000001d t0 write PC_PRIM_VTX_CNTL2 (21c5) PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 00055694: 0000: 000021c5 00000012 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 0005569c: 0000: 000021e5 00000000 t0 write GRAS_SU_MODE_CONTROL (2078) GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } 000556a4: 0000: 00002078 00000000 t0 write UNKNOWN_2001 (2001) UNKNOWN_2001: 0 000556ac: 0000: 00002001 00000000 t0 write GRAS_CNTL (2003) GRAS_CNTL: { IJ_PERSP } 000556b4: 0000: 00002003 00000001 t0 write GRAS_CL_CLIP_CNTL (2000) GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } 000556bc: 0000: 00002000 00188000 t0 write TPL1_TP_TEX_COUNT (2381) TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } 000556c4: 0000: 00002381 00000000 t0 write TPL1_TP_FS_TEX_COUNT (23a0) TPL1_TP_FS_TEX_COUNT: 0x3 000556cc: 0000: 000023a0 00000003 t0 write RB_ALPHA_CONTROL (20f8) RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } 000556d4: 0000: 000020f8 00000e00 t0 write RB_RENDER_COMPONENTS (20fb) RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } 000556dc: 0000: 000020fb 0000000f t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 000556e4: 0000: c0014300 00040000 00000000 t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } 000556f0: 0000: 00002200 000a0000 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } 000556f8: 0000: 00002201 fc030000 t0 write SP_INSTR_CACHE_CTRL (22c1) SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } 00055700: 0000: 000022c1 000005c3 t0 write HLSQ_CONTROL_1_REG (23c1) HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } 00055708: 0000: 000023c1 fcfc0120 t0 write HLSQ_CONTROL_2_REG (23c2) HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 00055710: 0000: 000023c2 27f3f3f0 t0 write HLSQ_VS_CONTROL_REG (23c5) HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } 00055718: 0000: 000023c5 02010042 t0 write HLSQ_FS_CONTROL_REG (23c6) HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 1 } 00055720: 0000: 000023c6 0141423e t0 write HLSQ_HS_CONTROL_REG (23c7) HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00055728: 0000: 000023c7 00404200 t0 write HLSQ_DS_CONTROL_REG (23c8) HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00055730: 0000: 000023c8 00404200 t0 write HLSQ_GS_CONTROL_REG (23c9) HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00055738: 0000: 000023c9 00404200 t0 write HLSQ_CS_CONTROL_REG (23ca) HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } 00055740: 0000: 000023ca 00004200 t0 write SP_SP_CTRL_REG (22c0) SP_SP_CTRL_REG: { 0x60010 } 00055748: 0000: 000022c0 00060010 t0 write UNKNOWN_21E6 (21e6) UNKNOWN_21E6: 0x1 00055750: 0000: 000021e6 00000001 t0 write SP_VS_CTRL_REG0 (22c4) SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 00055758: 0000: 000022c4 00200c10 t0 write SP_VS_CTRL_REG1 (22c5) SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } 00055760: 0000: 000022c5 01000042 t0 write VPC_ATTR (2140) VPC_ATTR: { TOTALATTR = 8 | THRDASSIGN = 1 | ENABLE | 0x40000000 } 00055768: 0000: 00002140 42001008 t0 write VPC_PACK (2141) VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 8 | NUMNONPOSVSVAR = 6 } 00055770: 0000: 00002141 00060800 t0 write PC_PRIM_VTX_CNTL (21c4) PC_PRIM_VTX_CNTL: { VAROUT = 1 } 00055778: 0000: 000021c4 00000001 t0 write SP_VS_PARAM_REG (22c6) SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 2 } SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r1.w | B_COMPMASK = 0x3 } SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } UNKNOWN_22D7: 0xfcfc00 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 12 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 00055780: 0000: 001922c6 0020fc03 06071e03 00000000 00000000 00000000 00000000 00000000 * 000557c0: 0040: 00000000 00000000 00fcfc00 00000c08 00000000 00000000 00000000 00000000 * t0 write SP_VS_OBJ_OFFSET_REG (22e0) SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 000557ec: 0000: 000022e0 00000000 t0 write SP_VS_OBJ_START (22e1) SP_VS_OBJ_START: 0x1 000557f4: 0000: 000022e1 00000001 t0 write SP_VS_LENGTH_REG (22e5) SP_VS_LENGTH_REG: 2 000557fc: 0000: 000022e5 00000002 t3 opcode: CP_LOAD_STATE4 (30) (67 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } :2:0000:0000[56d81803x_20020003x] (sy)(ss)(nop3) shl.b r0.w, r0.w, 2 :1:0001:0004[20150000x_00000003x] cov.s32s16 hr0.x, r0.w :0:0002:0005[00000200x_00000000x] (rpt2)nop :1:0003:0008[201100f4x_00000000x] mova a0.x, hr0.x :0:0004:0009[00000500x_00000000x] (rpt5)nop :1:0005:0015[20154003x_00000c20x] mov.s32s32 r0.w, c :1:0006:0016[20154004x_00000c21x] mov.s32s32 r1.x, c :1:0007:0017[20154007x_00000c22x] mov.s32s32 r1.w, c :1:0008:0018[20156008x_00000c23x] (ul)mov.s32s32 r2.x, c :1:0009:0019[20554005x_00000000x] mov.s32s32 r1.y, 0 :1:0010:0020[20554006x_3f800000x] mov.s32s32 r1.z, 1065353216 :0:0011:0021[03000000x_00000000x] end :2:0012:0022[46f00009x_20050000x] shr.b r2.y, r0.x, 5 :2:0013:0023[4398000ax_201f0000x] (nop2) and.b r2.z, r0.x, 31 :2:0014:0026[43980809x_201f0009x] (nop3) and.b r2.y, r2.y, 31 :2:0015:0030[46100809x_20180009x] (nop1) mul.u24 r2.y, r2.y, 24 :3:0016:0032[62050009x_00091014x] mad.u24 r2.y, c5.x, r2.z, r2.y :0:0017:0033[00000500x_00000000x] (rpt5)nop :6:0018:0039[c2c61300x_04800006x] stlw.u32 l[r2.y], r0.w, 4 :6:0019:0040[c2c61310x_0280000ex] stlw.u32 l[r2.y+16], r1.w, 2 :0:0020:0041[04800000x_00000000x] chmask :0:0021:0042[05000000x_00000000x] chsh Stats: - shaderdb: 43 instr, 24 nops, 19 non-nops, 7 mov, 1 cov - shaderdb: 0 last-baryf, 0 half, 3 full, 5 constlen - shaderdb: 27 cat0, 8 cat1, 5 cat2, 1 cat3, 0 cat4, 0 cat5, 2 cat6, 0 cat7 - shaderdb: 0 sstall, 1 (ss), 1 (sy) 00055804: 0000: c0413000 00a00000 00000000 20020003 56d81803 00000003 20150000 00000000 00055824: 0020: 00000200 00000000 201100f4 00000000 00000500 00000c20 20154003 00000c21 00055844: 0040: 20154004 00000c22 20154007 00000c23 20156008 00000000 20554005 3f800000 00055864: 0060: 20554006 00000000 03000000 20050000 46f00009 201f0000 4398000a 201f0009 00055884: 0080: 43980809 20180009 46100809 00091014 62050009 00000000 00000500 04800006 000558a4: 00a0: c2c61300 0280000e c2c61310 00000000 04800000 00000000 05000000 00000000 * t0 write HLSQ_CONTROL_3_REG (23c3) HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } 00055910: 0000: 000023c3 fcfcfc00 t0 write HLSQ_CONTROL_4_REG (23c4) HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } 00055918: 0000: 000023c4 00fcfcfc t0 write SP_FS_CTRL_REG0 (22e8) SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 0 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE | PIXLODENABLE } SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 } 00055920: 0000: 000122e8 00700402 8010003e t0 write SP_FS_OBJ_OFFSET_REG (22ea) SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 } 0005592c: 0000: 000022ea 40420000 t0 write SP_FS_OBJ_START (22eb) SP_FS_OBJ_START: 0x1 00055934: 0000: 000022eb 00000001 t0 write SP_FS_LENGTH_REG (22ef) SP_FS_LENGTH_REG: 1 0005593c: 0000: 000022ef 00000001 t0 write SP_FS_OUTPUT_REG (22f0) SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r0.x | SAMPLEMASK_REGID = r0.x } 00055944: 0000: 000022f0 00000001 t0 write VPC_VARYING_INTERP[0].MODE (2142) VPC_VARYING_INTERP[0].MODE: 0xe000 0005594c: 0000: 00002142 0000e000 t0 write RB_FS_OUTPUT_REG (2100) RB_FS_OUTPUT_REG: { MRT = 1 } 00055954: 0000: 00002100 00000001 t3 opcode: CP_LOAD_STATE4 (30) (35 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 1 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } :2:0000:0000[57309902x_00002004x] (sy)(ss)(rpt1)bary.f (ei)r0.z, (r)4, r0.x :0:0001:0002[00000500x_00000000x] (rpt5)nop :5:0002:0008[a0c01f00x_00000005x] sam (f32)(xyzw)r0.x, r0.z, s#0, t#0 :0:0003:0009[03000000x_00000000x] end :0:0004:0010[00000000x_00000000x] nop :0:0005:0011[00000000x_00000000x] nop :0:0006:0012[00000000x_00000000x] nop :0:0007:0013[00000000x_00000000x] nop Stats: - shaderdb: 14 instr, 10 nops, 4 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 0 half, 1 full, 0 constlen - shaderdb: 11 cat0, 0 cat1, 2 cat2, 0 cat3, 0 cat4, 1 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 1 (ss), 1 (sy) 0005595c: 0000: c0213000 00700000 00000000 00002004 57309902 00000000 00000500 00000005 0005597c: 0020: a0c01f00 00000000 03000000 00000000 00000000 00000000 00000000 00000000 * t0 write RB_FS_OUTPUT (20f9) RB_FS_OUTPUT: { ENABLE_BLEND = 0 | SAMPLE_MASK = 0xffff } 000559e8: 0000: 000020f9 ffff0000 t0 write RB_MRT[0].CONTROL (20a4) RB_MRT[0].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0xf } 000559f0: 0000: 000020a4 0f000000 t0 write RB_MRT[0x1].CONTROL (20a9) RB_MRT[0x1].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0xf } 000559f8: 0000: 000020a9 0f000000 t0 write RB_MRT[0].BLEND_CONTROL (20a8) RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } 00055a00: 0000: 000020a8 00000000 t3 opcode: CP_LOAD_STATE4 (30) (5 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_TEX | NUM_UNIT = 1 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } { XY_MAG = A4XX_TEX_NEAREST | XY_MIN = A4XX_TEX_NEAREST | WRAP_S = A4XX_TEX_CLAMP_TO_EDGE | WRAP_T = A4XX_TEX_CLAMP_TO_EDGE | WRAP_R = A4XX_TEX_CLAMP_TO_EDGE | ANISO = A4XX_TEX_ANISO_1 | LOD_BIAS = 0.000000 | 0x60000 } { COMPARE_FUNC = FUNC_LEQUAL | UNNORM_COORDS | MIPFILTER_LINEAR_FAR | MAX_LOD = 0.000000 | MIN_LOD = 0.000000 | 0x1 } 00055a14: 0000: 00060920 00000067 00055a08: 0000: c0033000 00500000 00000000 00060920 00000067 t0 write GRAS_SC_CONTROL (207b) GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 0 | RASTER_MODE = 0 } 00055a1c: 0000: 0000207b 00000000 t0 write RB_MSAA_CONTROL (20a2) RB_MSAA_CONTROL: { SAMPLES = 0 } 00055a24: 0000: 000020a2 00000000 t0 write RB_RENDER_CONTROL (20a1) RB_RENDER_CONTROL: { 0 } 00055a2c: 0000: 000020a1 00000000 t0 write 0x2382 (2382) 0x2382: 00000000 00055a34: 0000: 00002382 00000000 t0 write RB_DEPTH_CONTROL (2101) RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } 00055a3c: 0000: 00002101 00000000 t0 write GRAS_ALPHA_CONTROL (2073) GRAS_ALPHA_CONTROL: { 0 } 00055a44: 0000: 00002073 00000000 t0 write RB_STENCIL_CONTROL (2106) RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } 00055a4c: 0000: 00002106 00000000 t0 write SP_FS_MRT[0].REG (22f1) SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = RB4_R8G8B8A8_UNORM } 00055a54: 0000: 000022f1 0001a000 t0 write RB_MRT[0].BUF_INFO (20a5) RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB4_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE4_3 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 256 } RB_MRT[0].BASE: 0x166000 RB_MRT[0].CONTROL3: { STRIDE = 0 } 00055a5c: 0000: 000220a5 000400da 00166000 00000000 t3 opcode: CP_LOAD_STATE4 (30) (11 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_TEX | NUM_UNIT = 1 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } { TILED | SWIZ_X = A4XX_TEX_X | SWIZ_Y = A4XX_TEX_Y | SWIZ_Z = A4XX_TEX_Z | SWIZ_W = A4XX_TEX_W | MIPLVLS = 0 | FMT = TFMT4_8_8_8_8_UNORM | TYPE = A4XX_TEX_2D | 0x2 } { HEIGHT = 64 | WIDTH = 64 } { PITCHALIGN = 0 | PITCH = 256 | SWAP = WZYX } { LAYERSZ = 0 | DEPTH = 1 | 0x20000 } { LAYERSZ = 4096 | BASE = 0x4f000 } { 5 = 0 } { 6 = 0 } { 7 = 0 } 00055a78: 0000: 27006883 00200040 00020000 00060000 0004f001 00000000 00000000 00000000 00055a6c: 0000: c0093000 00500000 00000001 27006883 00200040 00020000 00060000 0004f001 * t0 write VPC_VARYING_PS_REPL[0].MODE (214a) VPC_VARYING_PS_REPL[0].MODE: 0x99999999 00055a98: 0000: 0000214a 99999999 t0 write GRAS_SC_SCREEN_SCISSOR_TL (207c) GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } 00055aa0: 0000: 0001207c 00000000 003f003f t0 write GRAS_SC_WINDOW_SCISSOR_BR (209c) GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 00055aac: 0000: 0001209c 003f003f 00000000 t0 write RB_FRAME_BUFFER_DIMENSION (0ce0) RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } 00055ab8: 0000: 00000ce0 00400040 t0 write 0xce1 (0ce1) 0xce1: 00000000 00055ac0: 0000: 00000ce1 00000000 t0 write RB_RENDER_CONTROL2 (20a3) RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 | IJ_PERSP_PIXEL } 00055ac8: 0000: 000020a3 00001000 t0 write RB_MODE_CONTROL (20a0) RB_MODE_CONTROL: { WIDTH = 0 | HEIGHT = 0 | 0xc00000 } 00055ad0: 0000: 000020a0 00c00000 t3 opcode: CP_LOAD_STATE4 (30) (11 dwords) { DST_OFF = 8 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } 00055ae4: 0.000000 0.000000 0.000000 0.000000 64.000000 64.000000 64.000000 64.000000 00055ae4: 0000: 00000000 00000000 00000000 00000000 42800000 42800000 42800000 42800000 00055ad8: 0000: c0093000 00a00008 00000001 00000000 00000000 00000000 00000000 42800000 00055af8: 0020: 42800000 42800000 42800000 t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x80000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 2 } draw[29] register values + 00000004 UNKNOWN_0CC5: 0x4 + 00000000 UNKNOWN_0CC6: 0 + 00400040 RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } + 00000000 0xce1: 00000000 + 00000002 HLSQ_MODE_CONTROL: 0x2 + 00000000 UNKNOWN_0E42: 0 + 00000004 SP_MODE_CONTROL: 0x4 + 00000068 TPL1_TP_MODE_CONTROL: 0x68 + 00188000 GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } + 00000000 UNKNOWN_2001: 0 + 00000001 GRAS_CNTL: { IJ_PERSP } !+ 00000000 GRAS_ALPHA_CONTROL: { 0 } + 00000000 GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } !+ 00000000 GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 0 | RASTER_MODE = 0 } + 00000000 GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } + 003f003f GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } + 003f003f GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } + 00000000 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } !+ 00c00000 RB_MODE_CONTROL: { WIDTH = 0 | HEIGHT = 0 | 0xc00000 } !+ 00000000 RB_RENDER_CONTROL: { 0 } !+ 00000000 RB_MSAA_CONTROL: { SAMPLES = 0 } !+ 00001000 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 | IJ_PERSP_PIXEL } !+ 0f000000 RB_MRT[0].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0xf } !+ 000400da RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB4_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE4_3 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 256 } !+ 00166000 RB_MRT[0].BASE: 0x166000 !+ 00000000 RB_MRT[0].CONTROL3: { STRIDE = 0 } + 00000000 RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } + 0f000000 RB_MRT[0x1].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0xf } + 00000e00 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } !+ ffff0000 RB_FS_OUTPUT: { ENABLE_BLEND = 0 | SAMPLE_MASK = 0xffff } + 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } + 00000001 RB_FS_OUTPUT_REG: { MRT = 1 } + 00000000 RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } + 00000000 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } !+ 42001008 VPC_ATTR: { TOTALATTR = 8 | THRDASSIGN = 1 | ENABLE | 0x40000000 } !+ 00060800 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 8 | NUMNONPOSVSVAR = 6 } !+ 0000e000 VPC_VARYING_INTERP[0].MODE: 0xe000 !+ 99999999 VPC_VARYING_PS_REPL[0].MODE: 0x99999999 + 00000000 UNKNOWN_2152: 0 + 00000000 UNKNOWN_2153: 0 + 00000000 UNKNOWN_2154: 0 + 00000000 UNKNOWN_2155: 0 + 00000000 UNKNOWN_2156: 0 + 0000001d UNKNOWN_21C3: 0x1d + 00000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 } + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + 00000000 PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } + 00000001 UNKNOWN_21E6: 0x1 + 000a0000 VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } + fc030000 VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } + fcfcfcfc VFD_CONTROL_2: 0xfcfcfcfc + fcfcfc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } + 0000fcfc VFD_CONTROL_4: 0xfcfc + 00000000 VFD_INDEX_OFFSET: 0 + 00000000 UNKNOWN_2209: 0 + 00060010 SP_SP_CTRL_REG: { 0x60010 } + 000005c3 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } + 00200c10 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } + 01000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } !+ 0020fc03 SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 2 } !+ 06071e03 SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r1.w | B_COMPMASK = 0x3 } + 00000000 SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00fcfc00 UNKNOWN_22D7: 0xfcfc00 !+ 00000c08 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 12 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } + 00000001 SP_VS_OBJ_START: 0x1 + 00000002 SP_VS_LENGTH_REG: 2 !+ 00700402 SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 0 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE | PIXLODENABLE } !+ 8010003e SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 } !+ 40420000 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 } !+ 00000001 SP_FS_OBJ_START: 0x1 + 00000001 SP_FS_LENGTH_REG: 1 !+ 00000001 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r0.x | SAMPLEMASK_REGID = r0.x } !+ 0001a000 SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = RB4_R8G8B8A8_UNORM } + 00000000 TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } !+ 00000000 0x2382: 00000000 + 00000003 TPL1_TP_FS_TEX_COUNT: 0x3 + 080004f0 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } + fcfc0120 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } + 27f3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } + fcfcfc00 HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } !+ 00fcfcfc HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } + 02010042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } !+ 0141423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 1 } + 00404200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00004200 HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } + 00000007 HLSQ_UPDATE_CONTROL: 0x7 00055b04: 0000: c0023800 00080888 00000001 00000002 t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = CACHE_FLUSH } event CACHE_FLUSH 00055b14: 0000: c0004600 00000006 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00055b1c: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0x8000012 00055b24: 0000: 00000cc6 08000012 00173000: 0000: c0013f00 000555d8 00000155 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 0017300c: 0000: c0014300 00040000 00000000 t3 opcode: (null) (1d) (2 dwords) 00173018: 0000: c0001d00 00000000 ############################################################ vertices: 0 ############################################################ cmdstream: 48 dwords t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 0016b000: 0000: c0002600 00000000 t0 write UCHE_INVALIDATE0 (0e8a) UCHE_INVALIDATE0: 0 UCHE_INVALIDATE1: 0x12 0016b008: 0000: 00010e8a 00000000 00000012 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 0016b014: 0000: c0002600 00000000 t0 write RB_MODE_CONTROL (20a0) RB_MODE_CONTROL: { WIDTH = 64 | HEIGHT = 64 | ENABLE_GMEM } 0016b01c: 0000: 000020a0 00010202 t0 write RB_FRAME_BUFFER_DIMENSION (0ce0) RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } 0016b024: 0000: 00000ce0 00400040 t0 write 0xce1 (0ce1) 0xce1: 00000001 0016b02c: 0000: 00000ce1 00000001 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 0016b034: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0 0016b03c: 0000: 00000cc6 00000000 t3 opcode: (null) (1d) (2 dwords) 0016b044: 0000: c0001d00 00000000 t0 write GRAS_SC_WINDOW_SCISSOR_BR (209c) GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 0016b04c: 0000: 0001209c 003f003f 00000000 t0 write RB_BIN_OFFSET (210d) RB_BIN_OFFSET: { X = 0 | Y = 0 } 0016b058: 0000: 0000210d 00000000 t0 write GRAS_SC_WINDOW_SCISSOR_BR (209c) GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 0016b060: 0000: 0001209c 003f003f 00000000 t0 write UNKNOWN_2157 (2157) UNKNOWN_2157: 0x1 0016b06c: 0000: 00002157 00000001 t3 opcode: (null) (64) (2 dwords) 0016b074: 0000: c0006400 00000001 t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:00054994 ibsize:000000f6 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00054994: 0000: c0002600 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x4 0005499c: 0000: 00000ec3 00000004 t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x68 000549a4: 0000: 00000f03 00000068 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 000549ac: 0000: c0002600 00000000 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } 000549b4: 0000: 000023c0 080004f0 t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = 0x1d } event (null) 000549bc: 0000: c0004600 0000001d t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = FACENESS_FLUSH } event FACENESS_FLUSH 000549c4: 0000: c0004600 0000001c t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 000549cc: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0 000549d4: 0000: 00000cc6 00000000 t0 write UNKNOWN_0E42 (0e42) UNKNOWN_0E42: 0 000549dc: 0000: 00000e42 00000000 t0 write HLSQ_MODE_CONTROL (0e05) HLSQ_MODE_CONTROL: 0x2 000549e4: 0000: 00000e05 00000002 t0 write UNKNOWN_0CC5 (0cc5) UNKNOWN_0CC5: 0x4 000549ec: 0000: 00000cc5 00000004 t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x7 000549f4: 0000: 000023db 00000007 t0 write VFD_CONTROL_2 (2202) VFD_CONTROL_2: 0xfcfcfcfc 000549fc: 0000: 00002202 fcfcfcfc t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } 00054a04: 0000: 00002203 fcfcfc00 t0 write VFD_CONTROL_4 (2204) VFD_CONTROL_4: 0xfcfc 00054a0c: 0000: 00002204 0000fcfc t0 write VFD_INDEX_OFFSET (2208) VFD_INDEX_OFFSET: 0 00054a14: 0000: 00002208 00000000 t0 write UNKNOWN_2209 (2209) UNKNOWN_2209: 0 00054a1c: 0000: 00002209 00000000 t0 write UNKNOWN_2152 (2152) UNKNOWN_2152: 0 UNKNOWN_2153: 0 00054a24: 0000: 00012152 00000000 00000000 t0 write UNKNOWN_2156 (2156) UNKNOWN_2156: 0 00054a30: 0000: 00002156 00000000 t0 write UNKNOWN_2154 (2154) UNKNOWN_2154: 0 00054a38: 0000: 00002154 00000000 t0 write UNKNOWN_2155 (2155) UNKNOWN_2155: 0 00054a40: 0000: 00002155 00000000 t0 write UNKNOWN_21C3 (21c3) UNKNOWN_21C3: 0x1d 00054a48: 0000: 000021c3 0000001d t0 write PC_PRIM_VTX_CNTL2 (21c5) PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 00054a50: 0000: 000021c5 00000012 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 00054a58: 0000: 000021e5 00000000 t0 write GRAS_SU_MODE_CONTROL (2078) GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } 00054a60: 0000: 00002078 00000000 t0 write UNKNOWN_2001 (2001) UNKNOWN_2001: 0 00054a68: 0000: 00002001 00000000 t0 write GRAS_CNTL (2003) GRAS_CNTL: { IJ_PERSP } 00054a70: 0000: 00002003 00000001 t0 write GRAS_CL_CLIP_CNTL (2000) GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } 00054a78: 0000: 00002000 00188000 t0 write TPL1_TP_TEX_COUNT (2381) TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } 00054a80: 0000: 00002381 00000000 t0 write TPL1_TP_FS_TEX_COUNT (23a0) TPL1_TP_FS_TEX_COUNT: 0x3 00054a88: 0000: 000023a0 00000003 t0 write RB_ALPHA_CONTROL (20f8) RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } 00054a90: 0000: 000020f8 00000e00 t0 write RB_RENDER_COMPONENTS (20fb) RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } 00054a98: 0000: 000020fb 0000000f t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 00054aa0: 0000: c0014300 00040000 00000000 t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } 00054aac: 0000: 00002200 000a0000 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } 00054ab4: 0000: 00002201 fc030000 t0 write SP_INSTR_CACHE_CTRL (22c1) SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } 00054abc: 0000: 000022c1 000005c3 t0 write HLSQ_CONTROL_1_REG (23c1) HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } 00054ac4: 0000: 000023c1 fcfc0120 t0 write HLSQ_CONTROL_2_REG (23c2) HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 00054acc: 0000: 000023c2 27f3f3f0 t0 write HLSQ_VS_CONTROL_REG (23c5) HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } 00054ad4: 0000: 000023c5 02010042 t0 write HLSQ_FS_CONTROL_REG (23c6) HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00054adc: 0000: 000023c6 0041423e t0 write HLSQ_HS_CONTROL_REG (23c7) HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00054ae4: 0000: 000023c7 00404200 t0 write HLSQ_DS_CONTROL_REG (23c8) HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00054aec: 0000: 000023c8 00404200 t0 write HLSQ_GS_CONTROL_REG (23c9) HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00054af4: 0000: 000023c9 00404200 t0 write HLSQ_CS_CONTROL_REG (23ca) HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } 00054afc: 0000: 000023ca 00004200 t0 write SP_SP_CTRL_REG (22c0) SP_SP_CTRL_REG: { 0x60010 } 00054b04: 0000: 000022c0 00060010 t0 write UNKNOWN_21E6 (21e6) UNKNOWN_21E6: 0x1 00054b0c: 0000: 000021e6 00000001 t0 write SP_VS_CTRL_REG0 (22c4) SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 00054b14: 0000: 000022c4 00200c10 t0 write SP_VS_CTRL_REG1 (22c5) SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } 00054b1c: 0000: 000022c5 01000042 t0 write VPC_ATTR (2140) VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | 0x40000000 } 00054b24: 0000: 00002140 40001004 t0 write VPC_PACK (2141) VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } 00054b2c: 0000: 00002141 00040400 t0 write PC_PRIM_VTX_CNTL (21c4) PC_PRIM_VTX_CNTL: { VAROUT = 1 } 00054b34: 0000: 000021c4 00000001 t0 write SP_VS_PARAM_REG (22c6) SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } UNKNOWN_22D7: 0xfcfc00 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 00054b3c: 0000: 001922c6 0010fc03 00001e03 00000000 00000000 00000000 00000000 00000000 * 00054b7c: 0040: 00000000 00000000 00fcfc00 00000008 00000000 00000000 00000000 00000000 * t0 write SP_VS_OBJ_OFFSET_REG (22e0) SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 00054ba8: 0000: 000022e0 00000000 t0 write SP_VS_OBJ_START (22e1) SP_VS_OBJ_START: 0x1 00054bb0: 0000: 000022e1 00000001 t0 write SP_VS_LENGTH_REG (22e5) SP_VS_LENGTH_REG: 2 00054bb8: 0000: 000022e5 00000002 t3 opcode: CP_LOAD_STATE4 (30) (67 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } :2:0000:0000[56d81803x_20020003x] (sy)(ss)(nop3) shl.b r0.w, r0.w, 2 :1:0001:0004[20150000x_00000003x] cov.s32s16 hr0.x, r0.w :0:0002:0005[00000200x_00000000x] (rpt2)nop :1:0003:0008[201100f4x_00000000x] mova a0.x, hr0.x :0:0004:0009[00000500x_00000000x] (rpt5)nop :1:0005:0015[20154003x_00000c20x] mov.s32s32 r0.w, c :1:0006:0016[20154004x_00000c21x] mov.s32s32 r1.x, c :1:0007:0017[20154005x_00000c22x] mov.s32s32 r1.y, c :1:0008:0018[20156006x_00000c23x] (ul)mov.s32s32 r1.z, c :0:0009:0019[03000000x_00000000x] end :2:0010:0020[46f00007x_20050000x] shr.b r1.w, r0.x, 5 :2:0011:0021[43980008x_201f0000x] (nop2) and.b r2.x, r0.x, 31 :2:0012:0024[43980807x_201f0007x] (nop3) and.b r1.w, r1.w, 31 :2:0013:0028[46100807x_20100007x] (nop1) mul.u24 r1.w, r1.w, 16 :3:0014:0030[62040007x_00071014x] mad.u24 r1.w, c5.x, r2.x, r1.w :0:0015:0031[00000500x_00000000x] (rpt5)nop :6:0016:0037[c2c60f00x_04800006x] stlw.u32 l[r1.w], r0.w, 4 :0:0017:0038[04800000x_00000000x] chmask :0:0018:0039[05000000x_00000000x] chsh Stats: - shaderdb: 40 instr, 24 nops, 16 non-nops, 5 mov, 1 cov - shaderdb: 0 last-baryf, 0 half, 2 full, 5 constlen - shaderdb: 27 cat0, 6 cat1, 5 cat2, 1 cat3, 0 cat4, 0 cat5, 1 cat6, 0 cat7 - shaderdb: 0 sstall, 1 (ss), 1 (sy) 00054bc0: 0000: c0413000 00a00000 00000000 20020003 56d81803 00000003 20150000 00000000 00054be0: 0020: 00000200 00000000 201100f4 00000000 00000500 00000c20 20154003 00000c21 00054c00: 0040: 20154004 00000c22 20154005 00000c23 20156006 00000000 03000000 20050000 00054c20: 0060: 46f00007 201f0000 43980008 201f0007 43980807 20100007 46100807 00071014 00054c40: 0080: 62040007 00000000 00000500 04800006 c2c60f00 00000000 04800000 00000000 00054c60: 00a0: 05000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 * t0 write GRAS_ALPHA_CONTROL (2073) GRAS_ALPHA_CONTROL: { 0x2 } 00054ccc: 0000: 00002073 00000002 t0 write GRAS_SC_CONTROL (207b) GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = 4 | MSAA_DISABLE | RASTER_MODE = 0 } 00054cd4: 0000: 0000207b 00000a08 t0 write RB_MSAA_CONTROL (20a2) RB_MSAA_CONTROL: { DISABLE | SAMPLES = 4 } 00054cdc: 0000: 000020a2 00009000 t0 write RB_RENDER_CONTROL (20a1) RB_RENDER_CONTROL: { DISABLE_COLOR_PIPE | 0x2 } 00054ce4: 0000: 000020a1 00000022 t0 write RB_CLEAR_COLOR_DW0 (20cc) RB_CLEAR_COLOR_DW0: 0xff000000 RB_CLEAR_COLOR_DW1: 0 RB_CLEAR_COLOR_DW2: 0 RB_CLEAR_COLOR_DW3: 0 00054cec: 0000: 000320cc ff000000 00000000 00000000 00000000 t0 write RB_COPY_CONTROL (20fc) RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_FOUR | MODE = RB_COPY_CLEAR | FASTCLEAR = 0xf | GMEM_BASE = 0 } RB_COPY_DEST_BASE: { BASE = 0x4f000 } RB_COPY_DEST_PITCH: { PITCH = 256 } RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_IF_ALPHA_OFF | COMPONENT_ENABLE = 0 | ENDIAN = ENDIAN_NONE | TILE = TILE4_3 } 00054d00: 0000: 000320fc 00000f22 0004f000 00000008 03000868 t0 write GRAS_SC_SCREEN_SCISSOR_TL (207c) GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } 00054d14: 0000: 0001207c 00000000 003f003f t0 write RB_FRAME_BUFFER_DIMENSION (0ce0) RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } 00054d20: 0000: 00000ce0 00400040 t0 write 0xce1 (0ce1) 0xce1: 00000000 00054d28: 0000: 00000ce1 00000000 t3 opcode: CP_LOAD_STATE4 (30) (11 dwords) { DST_OFF = 8 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } 00054d3c: 0.000000 0.000000 1.000000 1.000000 64.000000 64.000000 1.000000 1.000000 00054d3c: 0000: 00000000 00000000 3f800000 3f800000 42800000 42800000 3f800000 3f800000 00054d30: 0000: c0093000 00a00008 00000001 00000000 00000000 3f800000 3f800000 42800000 00054d50: 0020: 42800000 3f800000 3f800000 t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x80000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 2 } draw[30] register values + 00000004 UNKNOWN_0CC5: 0x4 + 00000000 UNKNOWN_0CC6: 0 + 00400040 RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } + 00000000 0xce1: 00000000 + 00000002 HLSQ_MODE_CONTROL: 0x2 + 00000000 UNKNOWN_0E42: 0 + 00000000 UCHE_INVALIDATE0: 0 + 00000012 UCHE_INVALIDATE1: 0x12 + 00000004 SP_MODE_CONTROL: 0x4 + 00000068 TPL1_TP_MODE_CONTROL: 0x68 + 00188000 GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } + 00000000 UNKNOWN_2001: 0 + 00000001 GRAS_CNTL: { IJ_PERSP } !+ 00000002 GRAS_ALPHA_CONTROL: { 0x2 } + 00000000 GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } !+ 00000a08 GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = 4 | MSAA_DISABLE | RASTER_MODE = 0 } + 00000000 GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } + 003f003f GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } + 003f003f GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } + 00000000 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } !+ 00010202 RB_MODE_CONTROL: { WIDTH = 64 | HEIGHT = 64 | ENABLE_GMEM } !+ 00000022 RB_RENDER_CONTROL: { DISABLE_COLOR_PIPE | 0x2 } !+ 00009000 RB_MSAA_CONTROL: { DISABLE | SAMPLES = 4 } + ff000000 RB_CLEAR_COLOR_DW0: 0xff000000 + 00000000 RB_CLEAR_COLOR_DW1: 0 + 00000000 RB_CLEAR_COLOR_DW2: 0 + 00000000 RB_CLEAR_COLOR_DW3: 0 + 00000e00 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } + 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } !+ 00000f22 RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_FOUR | MODE = RB_COPY_CLEAR | FASTCLEAR = 0xf | GMEM_BASE = 0 } + 0004f000 RB_COPY_DEST_BASE: { BASE = 0x4f000 } + 00000008 RB_COPY_DEST_PITCH: { PITCH = 256 } !+ 03000868 RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_IF_ALPHA_OFF | COMPONENT_ENABLE = 0 | ENDIAN = ENDIAN_NONE | TILE = TILE4_3 } + 00000000 RB_BIN_OFFSET: { X = 0 | Y = 0 } !+ 40001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | 0x40000000 } !+ 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } + 00000000 UNKNOWN_2152: 0 + 00000000 UNKNOWN_2153: 0 + 00000000 UNKNOWN_2154: 0 + 00000000 UNKNOWN_2155: 0 + 00000000 UNKNOWN_2156: 0 + 00000001 UNKNOWN_2157: 0x1 + 0000001d UNKNOWN_21C3: 0x1d + 00000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 } + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + 00000000 PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } + 00000001 UNKNOWN_21E6: 0x1 + 000a0000 VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } + fc030000 VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } + fcfcfcfc VFD_CONTROL_2: 0xfcfcfcfc + fcfcfc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } + 0000fcfc VFD_CONTROL_4: 0xfcfc + 00000000 VFD_INDEX_OFFSET: 0 + 00000000 UNKNOWN_2209: 0 + 00060010 SP_SP_CTRL_REG: { 0x60010 } + 000005c3 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } + 00200c10 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } + 01000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } !+ 0010fc03 SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } !+ 00001e03 SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00fcfc00 UNKNOWN_22D7: 0xfcfc00 !+ 00000008 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } + 00000001 SP_VS_OBJ_START: 0x1 + 00000002 SP_VS_LENGTH_REG: 2 + 00000000 TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } + 00000003 TPL1_TP_FS_TEX_COUNT: 0x3 + 080004f0 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } + fcfc0120 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } + 27f3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } + 02010042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } !+ 0041423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00004200 HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } + 00000007 HLSQ_UPDATE_CONTROL: 0x7 00054d5c: 0000: c0023800 00080888 00000001 00000002 0016b07c: 0000: c0013f00 00054994 000000f6 t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:00054d6c ibsize:00000037 t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } 00054d6c: 0000: 00002200 082a0008 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00054d74: 0000: c0002600 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x1e 00054d7c: 0000: 00000ec3 0000001e t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x28 00054d84: 0000: 00000f03 00000028 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00054d8c: 0000: c0002600 00000000 t0 write HLSQ_MODE_CONTROL (0e05) HLSQ_MODE_CONTROL: 0x1 00054d94: 0000: 00000e05 00000001 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0x600a0 } 00054d9c: 0000: 000023c0 080604f0 t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x7 00054da4: 0000: 000023db 00000007 t0 write PC_RESTART_INDEX (21c6) PC_RESTART_INDEX: 0xffffffff 00054dac: 0000: 000021c6 ffffffff t0 write UNKNOWN_21E6 (21e6) UNKNOWN_21E6: 0x1 00054db4: 0000: 000021e6 00000001 t0 write UNKNOWN_21C3 (21c3) UNKNOWN_21C3: 0x1f 00054dbc: 0000: 000021c3 0000001f t0 write TPL1_TP_TEX_OFFSET (2380) TPL1_TP_TEX_OFFSET: 0x808 00054dc4: 0000: 00002380 00000808 t0 write GRAS_SU_POINT_MINMAX (2070) GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 4092.000000 } GRAS_SU_POINT_SIZE: 0.500000 00054dcc: 0000: 00012070 ffc00010 00000008 t0 write UNKNOWN_2152 (2152) UNKNOWN_2152: 0 UNKNOWN_2153: 0 00054dd8: 0000: 00012152 00000000 00000000 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00054de4: 0000: c0002600 00000000 t0 write UNKNOWN_0CC5 (0cc5) UNKNOWN_0CC5: 0x4 00054dec: 0000: 00000cc5 00000004 t0 write 0xcc4 (0cc4) 0xcc4: 00000000 00054df4: 0000: 00000cc4 00000000 t0 write 0xd03 (0d03) 0xd03: 80200000 00054dfc: 0000: 00000d03 80200000 t0 write UNKNOWN_0EC2 (0ec2) UNKNOWN_0EC2: 0x40000 00054e04: 0000: 00000ec2 00040000 t0 write VPC_DEBUG_ECO_CONTROL (0e64) VPC_DEBUG_ECO_CONTROL: 0x100 00054e0c: 0000: 00000e64 00000100 t0 write UNKNOWN_0E42 (0e42) UNKNOWN_0E42: 0 00054e14: 0000: 00000e42 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x1e 00054e1c: 0000: 00000ec3 0000001e t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x28 00054e24: 0000: 00000f03 00000028 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 00054e2c: 0000: c0014300 00040000 00000000 t0 write VFD_INDEX_OFFSET (2208) VFD_INDEX_OFFSET: 0 00054e38: 0000: 00002208 00000000 t0 write UNKNOWN_2209 (2209) UNKNOWN_2209: 0 00054e40: 0000: 00002209 00000000 0016b088: 0000: c0013f00 00054d6c 00000037 t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:00055328 ibsize:000000ac t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x3 00055328: 0000: 000023db 00000003 t0 write SP_INSTR_CACHE_CTRL (22c1) SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } 00055330: 0000: 000022c1 000005c3 t0 write HLSQ_CONTROL_1_REG (23c1) HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x1008 } 00055338: 0000: 000023c1 fcfc1108 t0 write HLSQ_CONTROL_2_REG (23c2) HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 00055340: 0000: 000023c2 fff3f3f0 t0 write HLSQ_VS_CONTROL_REG (23c5) HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 2 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 1 } 00055348: 0000: 000023c5 01010002 t0 write HLSQ_HS_CONTROL_REG (23c7) HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 00055350: 0000: 000023c7 007e0200 t0 write HLSQ_DS_CONTROL_REG (23c8) HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 00055358: 0000: 000023c8 007e0200 t0 write HLSQ_GS_CONTROL_REG (23c9) HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 00055360: 0000: 000023c9 007e0200 t0 write HLSQ_FS_CONTROL_REG (23c6) HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 2 | CONSTOBJECTOFFSET = 2 | ENABLED | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 } 00055368: 0000: 000023c6 017f0202 t0 write SP_VS_OBJ_OFFSET_REG (22e0) SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 00055370: 0000: 000022e0 00000000 t0 write SP_HS_OBJ_OFFSET_REG (230d) SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } 00055378: 0000: 0000230d 7e020000 t0 write SP_DS_OBJ_OFFSET_REG (2334) SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } 00055380: 0000: 00002334 7e020000 t0 write SP_GS_OBJ_OFFSET_REG (235b) SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } 00055388: 0000: 0000235b 7e020000 t0 write SP_FS_OBJ_OFFSET_REG (22ea) SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } 00055390: 0000: 000022ea 7e020000 t0 write SP_VS_OBJ_START (22e1) SP_VS_OBJ_START: 0x49000 00049000: 0000: 00000000 13000000 00000000 00000000 00000000 00000000 00000000 00000000 * :0:0000:0000[13000000x_00000000x] (sy)end :0:0001:0001[00000000x_00000000x] nop :0:0002:0002[00000000x_00000000x] nop :0:0003:0003[00000000x_00000000x] nop :0:0004:0004[00000000x_00000000x] nop Stats: - shaderdb: 5 instr, 4 nops, 1 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 0 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 0 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) 00055398: 0000: 000022e1 00049000 t0 write SP_HS_OBJ_START (230e) SP_HS_OBJ_START: 0 000553a0: 0000: 0000230e 00000000 t0 write SP_DS_OBJ_START (2335) SP_DS_OBJ_START: 0 000553a8: 0000: 00002335 00000000 t0 write SP_GS_OBJ_START (235c) SP_GS_OBJ_START: 0 000553b0: 0000: 0000235c 00000000 t0 write SP_VS_LENGTH_REG (22e5) SP_VS_LENGTH_REG: 1 000553b8: 0000: 000022e5 00000001 t3 opcode: CP_LOAD_STATE4 (30) (3 dwords) { DST_OFF = 0 | STATE_SRC = SS4_INDIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 1 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0x49000 } :0:0000:0000[13000000x_00000000x] (sy)end :0:0001:0001[00000000x_00000000x] nop :0:0002:0002[00000000x_00000000x] nop :0:0003:0003[00000000x_00000000x] nop :0:0004:0004[00000000x_00000000x] nop Stats: - shaderdb: 5 instr, 4 nops, 1 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 0 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 0 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) 000553c0: 0000: c0013000 00620000 00049000 t0 write 0x2072 (2072) 0x2072: 00000000 000553cc: 0000: 00002072 00000000 t0 write UNKNOWN_2155 (2155) UNKNOWN_2155: 0 000553d4: 0000: 00002155 00000000 t0 write GRAS_CNTL (2003) GRAS_CNTL: { IJ_PERSP } 000553dc: 0000: 00002003 00000001 t0 write VPC_VARYING_INTERP[0].MODE (2142) VPC_VARYING_INTERP[0].MODE: 0 000553e4: 0000: 00002142 00000000 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0x600a0 } 000553ec: 0000: 000023c0 080604f0 t0 write HLSQ_CONTROL_3_REG (23c3) HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } 000553f4: 0000: 000023c3 fcfcfc00 t0 write HLSQ_CONTROL_4_REG (23c4) HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r0.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } 000553fc: 0000: 000023c4 00fcfc00 t0 write SP_FS_CTRL_REG0 (22e8) SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE } SP_FS_CTRL_REG1: { CONSTLENGTH = 2 | VARYING | 0x80000000 } 00055404: 0000: 000122e8 00340412 80100002 t0 write SP_FS_OBJ_START (22eb) SP_FS_OBJ_START: 0x46000 00046000: 0000: 00002000 5730cb00 00000000 03000000 00000000 00000000 00000000 00000000 * :2:0000:0000[5730cb00x_00002000x] (sy)(rpt3)bary.f (ei)hr0.x, (r)0, r0.x :0:0001:0004[03000000x_00000000x] end :0:0002:0005[00000000x_00000000x] nop :0:0003:0006[00000000x_00000000x] nop :0:0004:0007[00000000x_00000000x] nop :0:0005:0008[00000000x_00000000x] nop Stats: - shaderdb: 9 instr, 4 nops, 5 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 1 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 4 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) 00055410: 0000: 000022eb 00046000 t0 write SP_FS_LENGTH_REG (22ef) SP_FS_LENGTH_REG: 1 00055418: 0000: 000022ef 00000001 t0 write RB_RENDER_COMPONENTS (20fb) RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } 00055420: 0000: 000020fb 0000000f t3 opcode: CP_LOAD_STATE4 (30) (3 dwords) { DST_OFF = 0 | STATE_SRC = SS4_INDIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 1 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0x46000 } :2:0000:0000[5730cb00x_00002000x] (sy)(rpt3)bary.f (ei)hr0.x, (r)0, r0.x :0:0001:0004[03000000x_00000000x] end :0:0002:0005[00000000x_00000000x] nop :0:0003:0006[00000000x_00000000x] nop :0:0004:0007[00000000x_00000000x] nop :0:0005:0008[00000000x_00000000x] nop Stats: - shaderdb: 9 instr, 4 nops, 5 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 1 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 4 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) 00055428: 0000: c0013000 00720000 00046000 t0 write SP_SP_CTRL_REG (22c0) SP_SP_CTRL_REG: { 0x60010 } 00055434: 0000: 000022c0 00060010 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 28 | GROUP_ID = 3 } { ADDR_LO = 0x9a5c0 } 0005543c: 0000: c0014300 0300001c 0009a5c0 t0 write RB_DEPTH_INFO (2103) RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTH4_NONE | DEPTH_BASE = 0 } RB_DEPTH_PITCH: 0 RB_DEPTH_PITCH2: 0 00055448: 0000: 00022103 00000000 00000000 00000000 t0 write GRAS_DEPTH_CONTROL (2077) GRAS_DEPTH_CONTROL: { FORMAT = DEPTH4_NONE } 00055458: 0000: 00002077 00000000 t0 write RB_STENCIL_INFO (2108) RB_STENCIL_INFO: { STENCIL_BASE = 0 } RB_STENCIL_PITCH: 0 0x210a: 00000000 00055460: 0000: 00022108 00000000 00000000 00000000 t0 write 0x2002 (2002) 0x2002: 00000000 00055470: 0000: 00002002 00000000 t0 write RB_ALPHA_CONTROL (20f8) RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } 00055478: 0000: 000020f8 00000e00 t0 write RB_MRT[0].CONTROL (20a4) RB_MRT[0].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0x7 } 00055480: 0000: 000020a4 07000c00 t0 write RB_MRT[0].BLEND_CONTROL (20a8) RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } 00055488: 0000: 000020a8 00000000 t0 write GRAS_CL_CLIP_CNTL (2000) GRAS_CL_CLIP_CNTL: { 0x80000 } 00055490: 0000: 00002000 00080000 t0 write GRAS_SU_POLY_OFFSET_SCALE (2074) GRAS_SU_POLY_OFFSET_SCALE: 0.000000 GRAS_SU_POLY_OFFSET_OFFSET: 0.000000 GRAS_SU_POLY_OFFSET_CLAMP: 0.000000 00055498: 0000: 00022074 00000000 00000000 00000000 t0 write GRAS_SU_MODE_CONTROL (2078) GRAS_SU_MODE_CONTROL: { FRONT_CW | LINEHALFWIDTH = 0.500000 | MSAA_ENABLE | RENDERING_PASS } 000554a8: 0000: 00002078 00102014 t0 write GRAS_SC_SCREEN_SCISSOR_TL (207c) GRAS_SC_SCREEN_SCISSOR_TL: { X = 2 | Y = 13 } GRAS_SC_SCREEN_SCISSOR_BR: { X = 33 | Y = 44 } 000554b0: 0000: 0001207c 000d0002 002c0021 t0 write GRAS_CL_VPORT_XOFFSET_0 (2008) GRAS_CL_VPORT_XOFFSET_0: 18.000000 GRAS_CL_VPORT_XSCALE_0: 16.000000 GRAS_CL_VPORT_YOFFSET_0: 29.000000 GRAS_CL_VPORT_YSCALE_0: 16.000000 GRAS_CL_VPORT_ZOFFSET_0: 0.500000 GRAS_CL_VPORT_ZSCALE_0: 0.500000 000554bc: 0000: 00052008 41900000 41800000 41e80000 41800000 3f000000 3f000000 t0 write GRAS_CL_GB_CLIP_ADJ (2004) GRAS_CL_GB_CLIP_ADJ: { HORZ = 511 | VERT = 511 } 000554d8: 0000: 00002004 0007fdff t0 write GRAS_SC_CONTROL (207b) GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 4 | RASTER_MODE = 0 } 000554e0: 0000: 0000207b 00000200 t0 write 0x2382 (2382) 0x2382: 00000002 000554e8: 0000: 00002382 00000002 t0 write RB_MSAA_CONTROL (20a2) RB_MSAA_CONTROL: { SAMPLES = 4 } 000554f0: 0000: 000020a2 00008000 t0 write RB_RENDER_CONTROL2 (20a3) RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 4 | IJ_PERSP_PIXEL } 000554f8: 0000: 000020a3 00001200 t0 write RB_MRT[0].BUF_INFO (20a5) RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB4_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_ALWAYS | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 1024 } RB_MRT[0].BASE: 0 RB_MRT[0].CONTROL3: { STRIDE = 64 } 00055500: 0000: 000220a5 0010029a 00000000 00000200 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 43 | GROUP_ID = 2 } { ADDR_LO = 0x9a630 } 00055510: 0000: c0014300 0200002b 0009a630 t0 write 0x215c (215c) 0x215c: 00000000 0x215d: 00000000 0005551c: 0000: 0001215c 00000000 00000000 t0 write 0x215f (215f) 0x215f: 00000000 00055528: 0000: 0000215f 00000000 t0 write 0x215e (215e) 0x215e: 00000000 00055530: 0000: 0000215e 00000000 t0 write 0x2161 (2161) 0x2161: 00000000 0x2162: 00000000 00055538: 0000: 00012161 00000000 00000000 t0 write 0x2164 (2164) 0x2164: 00000000 00055544: 0000: 00002164 00000000 t0 write 0x2163 (2163) 0x2163: 00000000 0005554c: 0000: 00002163 00000000 t0 write 0x2166 (2166) 0x2166: 00000000 0x2167: 00000000 00055554: 0000: 00012166 00000000 00000000 t0 write 0x2169 (2169) 0x2169: 00000000 00055560: 0000: 00002169 00000000 t0 write 0x2168 (2168) 0x2168: 00000000 00055568: 0000: 00002168 00000000 t0 write 0x216b (216b) 0x216b: 00000000 0x216c: 00000000 00055570: 0000: 0001216b 00000000 00000000 t0 write VPC_SO_FLUSH_WADDR_3 (216e) VPC_SO_FLUSH_WADDR_3: 0 0005557c: 0000: 0000216e 00000000 t0 write 0x216d (216d) 0x216d: 00000000 00055584: 0000: 0000216d 00000000 t0 write UNKNOWN_2156 (2156) UNKNOWN_2156: 0 0005558c: 0000: 00002156 00000000 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 18 | GROUP_ID = 1 } { ADDR_LO = 0x9a6e0 } 00055594: 0000: c0014300 01000012 0009a6e0 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 15 | GROUP_ID = 0 } { ADDR_LO = 0x9a730 } 000555a0: 0000: c0014300 0000000f 0009a730 group_id: 0 count: 15 addr: 000000000009a730 flags: 0 0009a730: 0000: 00002073 00000000 00002101 00000000 00002106 00000000 000021e5 00000000 0009a750: 0020: 0001210b 00000000 00000000 00002381 00000000 000023a0 00000000 t0 write GRAS_ALPHA_CONTROL (2073) GRAS_ALPHA_CONTROL: { 0 } 0009a730: 0000: 00002073 00000000 t0 write RB_DEPTH_CONTROL (2101) RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } 0009a738: 0000: 00002101 00000000 t0 write RB_STENCIL_CONTROL (2106) RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } 0009a740: 0000: 00002106 00000000 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 0009a748: 0000: 000021e5 00000000 t0 write RB_STENCILREFMASK (210b) RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 0009a750: 0000: 0001210b 00000000 00000000 t0 write TPL1_TP_TEX_COUNT (2381) TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } 0009a75c: 0000: 00002381 00000000 t0 write TPL1_TP_FS_TEX_COUNT (23a0) TPL1_TP_FS_TEX_COUNT: 0 0009a764: 0000: 000023a0 00000000 group_id: 1 count: 18 addr: 000000000009a6e0 flags: 0 0009a6e0: 0000: 00002200 082a0008 00002201 fcfc0081 00002203 0000fc00 0007220a 0008080f 0009a700: 0020: 0009a560 00000060 00000001 0000080f 0009a590 00000030 00000001 0001228a 0009a720: 0040: 7000411f 3000011f t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } 0009a6e0: 0000: 00002200 082a0008 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } 0009a6e8: 0000: 00002201 fcfc0081 t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } 0009a6f0: 0000: 00002203 0000fc00 t0 write VFD_FETCH[0].INSTR_0 (220a) VFD_FETCH[0].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 | SWITCHNEXT } VFD_FETCH[0].INSTR_1: 0x9a560 VFD_FETCH[0].INSTR_2: { SIZE = 0x60 } VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 } VFD_FETCH[0x1].INSTR_1: 0x9a590 VFD_FETCH[0x1].INSTR_2: { SIZE = 0x30 } VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } 0009a6f8: 0000: 0007220a 0008080f 0009a560 00000060 00000001 0000080f 0009a590 00000030 0009a718: 0020: 00000001 t0 write VFD_DECODE[0].INSTR (228a) VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID | SWITCHNEXT } VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID } 0009a71c: 0000: 0001228a 7000411f 3000011f group_id: 2 count: 43 addr: 000000000009a630 flags: 0 0009a630: 0000: 000020a1 00000000 000022f1 0001a100 000022f0 fc00fc01 00002100 00000001 0009a650: 0020: 000021e5 00000000 000020f9 ffff0501 0000214a 00000000 00002140 42001004 0009a670: 0040: 001922c6 0010fc04 00001e00 00000000 00000000 00000000 00000000 00000000 * 0009a6b0: 0080: 00000000 00000000 00fcfc00 00000008 00000000 00000000 00000000 00000000 * t0 write RB_RENDER_CONTROL (20a1) RB_RENDER_CONTROL: { 0 } 0009a630: 0000: 000020a1 00000000 t0 write SP_FS_MRT[0].REG (22f1) SP_FS_MRT[0].REG: { REGID = r0.x | HALF_PRECISION | MRTFORMAT = RB4_R8G8B8A8_UNORM } 0009a638: 0000: 000022f1 0001a100 t0 write SP_FS_OUTPUT_REG (22f0) SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 0009a640: 0000: 000022f0 fc00fc01 t0 write RB_FS_OUTPUT_REG (2100) RB_FS_OUTPUT_REG: { MRT = 1 } 0009a648: 0000: 00002100 00000001 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 0009a650: 0000: 000021e5 00000000 t0 write RB_FS_OUTPUT (20f9) RB_FS_OUTPUT: { ENABLE_BLEND = 0x1 | INDEPENDENT_BLEND | SAMPLE_MASK = 0xffff | 0x400 } 0009a658: 0000: 000020f9 ffff0501 t0 write VPC_VARYING_PS_REPL[0].MODE (214a) VPC_VARYING_PS_REPL[0].MODE: 0 0009a660: 0000: 0000214a 00000000 t0 write VPC_ATTR (2140) VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 } 0009a668: 0000: 00002140 42001004 t0 write SP_VS_PARAM_REG (22c6) SP_VS_PARAM_REG: { POSREGID = r1.x | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } SP_VS_OUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } UNKNOWN_22D7: 0xfcfc00 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 0009a670: 0000: 001922c6 0010fc04 00001e00 00000000 00000000 00000000 00000000 00000000 * 0009a6b0: 0040: 00000000 00000000 00fcfc00 00000008 00000000 00000000 00000000 00000000 * group_id: 3 count: 28 addr: 000000000009a5c0 flags: 0 0009a5c0: 0000: 000021c4 02000001 00002141 00040400 00002001 00000000 000022c4 00200800 0009a5e0: 0020: 000022c5 08000002 0000230c 00000000 00002318 00000000 00002319 00000000 0009a600: 0040: 00002340 00000000 00002202 fcfcfcfc 00002204 0000fcfc 00002154 00000000 0009a620: 0060: 000021e7 00000000 000021c5 00000012 t0 write PC_PRIM_VTX_CNTL (21c4) PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } 0009a5c0: 0000: 000021c4 02000001 t0 write VPC_PACK (2141) VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } 0009a5c8: 0000: 00002141 00040400 t0 write UNKNOWN_2001 (2001) UNKNOWN_2001: 0 0009a5d0: 0000: 00002001 00000000 t0 write SP_VS_CTRL_REG0 (22c4) SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 2 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 0009a5d8: 0000: 000022c4 00200800 t0 write SP_VS_CTRL_REG1 (22c5) SP_VS_CTRL_REG1: { CONSTLENGTH = 2 | INITIALOUTSTANDING = 8 } 0009a5e0: 0000: 000022c5 08000002 t0 write 0x230c (230c) 0x230c: 00000000 0009a5e8: 0000: 0000230c 00000000 t0 write 0x2318 (2318) 0x2318: 00000000 0009a5f0: 0000: 00002318 00000000 t0 write 0x2319 (2319) 0x2319: 00000000 0009a5f8: 0000: 00002319 00000000 t0 write 0x2340 (2340) 0x2340: 00000000 0009a600: 0000: 00002340 00000000 t0 write VFD_CONTROL_2 (2202) VFD_CONTROL_2: 0xfcfcfcfc 0009a608: 0000: 00002202 fcfcfcfc t0 write VFD_CONTROL_4 (2204) VFD_CONTROL_4: 0xfcfc 0009a610: 0000: 00002204 0000fcfc t0 write UNKNOWN_2154 (2154) UNKNOWN_2154: 0 0009a618: 0000: 00002154 00000000 t0 write PC_HS_PARAM (21e7) PC_HS_PARAM: { VERTICES_OUT = 0 | SPACING = EQUAL_SPACING } 0009a620: 0000: 000021e7 00000000 t0 write PC_PRIM_VTX_CNTL2 (21c5) PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 0009a628: 0000: 000021c5 00000012 t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = USE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x200000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 3 } draw[31] register values + 00000000 0xcc4: 00000000 + 00000004 UNKNOWN_0CC5: 0x4 + 80200000 0xd03: 80200000 !+ 00000001 HLSQ_MODE_CONTROL: 0x1 + 00000000 UNKNOWN_0E42: 0 + 00000100 VPC_DEBUG_ECO_CONTROL: 0x100 + 00040000 UNKNOWN_0EC2: 0x40000 !+ 0000001e SP_MODE_CONTROL: 0x1e !+ 00000028 TPL1_TP_MODE_CONTROL: 0x28 !+ 00080000 GRAS_CL_CLIP_CNTL: { 0x80000 } + 00000000 UNKNOWN_2001: 0 + 00000000 0x2002: 00000000 + 00000001 GRAS_CNTL: { IJ_PERSP } + 0007fdff GRAS_CL_GB_CLIP_ADJ: { HORZ = 511 | VERT = 511 } + 41900000 GRAS_CL_VPORT_XOFFSET_0: 18.000000 + 41800000 GRAS_CL_VPORT_XSCALE_0: 16.000000 + 41e80000 GRAS_CL_VPORT_YOFFSET_0: 29.000000 + 41800000 GRAS_CL_VPORT_YSCALE_0: 16.000000 + 3f000000 GRAS_CL_VPORT_ZOFFSET_0: 0.500000 + 3f000000 GRAS_CL_VPORT_ZSCALE_0: 0.500000 + ffc00010 GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 4092.000000 } + 00000008 GRAS_SU_POINT_SIZE: 0.500000 + 00000000 0x2072: 00000000 !+ 00000000 GRAS_ALPHA_CONTROL: { 0 } + 00000000 GRAS_SU_POLY_OFFSET_SCALE: 0.000000 + 00000000 GRAS_SU_POLY_OFFSET_OFFSET: 0.000000 + 00000000 GRAS_SU_POLY_OFFSET_CLAMP: 0.000000 + 00000000 GRAS_DEPTH_CONTROL: { FORMAT = DEPTH4_NONE } !+ 00102014 GRAS_SU_MODE_CONTROL: { FRONT_CW | LINEHALFWIDTH = 0.500000 | MSAA_ENABLE | RENDERING_PASS } !+ 00000200 GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 4 | RASTER_MODE = 0 } !+ 000d0002 GRAS_SC_SCREEN_SCISSOR_TL: { X = 2 | Y = 13 } !+ 002c0021 GRAS_SC_SCREEN_SCISSOR_BR: { X = 33 | Y = 44 } !+ 00000000 RB_RENDER_CONTROL: { 0 } !+ 00008000 RB_MSAA_CONTROL: { SAMPLES = 4 } !+ 00001200 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 4 | IJ_PERSP_PIXEL } !+ 07000c00 RB_MRT[0].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0x7 } !+ 0010029a RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB4_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_ALWAYS | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 1024 } !+ 00000000 RB_MRT[0].BASE: 0 !+ 00000200 RB_MRT[0].CONTROL3: { STRIDE = 64 } + 00000000 RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } + 00000e00 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } !+ ffff0501 RB_FS_OUTPUT: { ENABLE_BLEND = 0x1 | INDEPENDENT_BLEND | SAMPLE_MASK = 0xffff | 0x400 } + 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } + 00000001 RB_FS_OUTPUT_REG: { MRT = 1 } + 00000000 RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } + 00000000 RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTH4_NONE | DEPTH_BASE = 0 } + 00000000 RB_DEPTH_PITCH: 0 + 00000000 RB_DEPTH_PITCH2: 0 + 00000000 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } + 00000000 RB_STENCIL_INFO: { STENCIL_BASE = 0 } + 00000000 RB_STENCIL_PITCH: 0 + 00000000 0x210a: 00000000 + 00000000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } + 00000000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } !+ 42001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 } + 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } !+ 00000000 VPC_VARYING_INTERP[0].MODE: 0 !+ 00000000 VPC_VARYING_PS_REPL[0].MODE: 0 + 00000000 UNKNOWN_2152: 0 + 00000000 UNKNOWN_2153: 0 + 00000000 UNKNOWN_2154: 0 + 00000000 UNKNOWN_2155: 0 + 00000000 UNKNOWN_2156: 0 + 00000000 0x215c: 00000000 + 00000000 0x215d: 00000000 + 00000000 0x215e: 00000000 + 00000000 0x215f: 00000000 + 00000000 0x2161: 00000000 + 00000000 0x2162: 00000000 + 00000000 0x2163: 00000000 + 00000000 0x2164: 00000000 + 00000000 0x2166: 00000000 + 00000000 0x2167: 00000000 + 00000000 0x2168: 00000000 + 00000000 0x2169: 00000000 + 00000000 0x216b: 00000000 + 00000000 0x216c: 00000000 + 00000000 0x216d: 00000000 + 00000000 VPC_SO_FLUSH_WADDR_3: 0 !+ 0000001f UNKNOWN_21C3: 0x1f !+ 02000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + ffffffff PC_RESTART_INDEX: 0xffffffff + 00000000 PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } + 00000001 UNKNOWN_21E6: 0x1 + 00000000 PC_HS_PARAM: { VERTICES_OUT = 0 | SPACING = EQUAL_SPACING } !+ 082a0008 VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } !+ fcfc0081 VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } + fcfcfcfc VFD_CONTROL_2: 0xfcfcfcfc !+ 0000fc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } + 0000fcfc VFD_CONTROL_4: 0xfcfc + 00000000 VFD_INDEX_OFFSET: 0 + 00000000 UNKNOWN_2209: 0 + 0008080f VFD_FETCH[0].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 | SWITCHNEXT } !+ 0009a560 VFD_FETCH[0].INSTR_1: 0x9a560 + 00000060 VFD_FETCH[0].INSTR_2: { SIZE = 0x60 } + 00000001 VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } + 0000080f VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 } !+ 0009a590 VFD_FETCH[0x1].INSTR_1: 0x9a590 + 00000030 VFD_FETCH[0x1].INSTR_2: { SIZE = 0x30 } + 00000001 VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } + 7000411f VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID | SWITCHNEXT } + 3000011f VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID } + 00060010 SP_SP_CTRL_REG: { 0x60010 } + 000005c3 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } !+ 00200800 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 2 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } !+ 08000002 SP_VS_CTRL_REG1: { CONSTLENGTH = 2 | INITIALOUTSTANDING = 8 } !+ 0010fc04 SP_VS_PARAM_REG: { POSREGID = r1.x | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } !+ 00001e00 SP_VS_OUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00fcfc00 UNKNOWN_22D7: 0xfcfc00 + 00000008 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } !+ 00049000 SP_VS_OBJ_START: 0x49000 00049000: 0000: 00000000 13000000 00000000 00000000 00000000 00000000 00000000 00000000 * :0:0000:0000[13000000x_00000000x] (sy)end :0:0001:0001[00000000x_00000000x] nop :0:0002:0002[00000000x_00000000x] nop :0:0003:0003[00000000x_00000000x] nop :0:0004:0004[00000000x_00000000x] nop Stats: - shaderdb: 5 instr, 4 nops, 1 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 0 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 0 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) !+ 00000001 SP_VS_LENGTH_REG: 1 !+ 00340412 SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE } !+ 80100002 SP_FS_CTRL_REG1: { CONSTLENGTH = 2 | VARYING | 0x80000000 } !+ 7e020000 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } !+ 00046000 SP_FS_OBJ_START: 0x46000 00046000: 0000: 00002000 5730cb00 00000000 03000000 00000000 00000000 00000000 00000000 * :2:0000:0000[5730cb00x_00002000x] (sy)(rpt3)bary.f (ei)hr0.x, (r)0, r0.x :0:0001:0004[03000000x_00000000x] end :0:0002:0005[00000000x_00000000x] nop :0:0003:0006[00000000x_00000000x] nop :0:0004:0007[00000000x_00000000x] nop :0:0005:0008[00000000x_00000000x] nop Stats: - shaderdb: 9 instr, 4 nops, 5 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 1 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 4 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) + 00000001 SP_FS_LENGTH_REG: 1 !+ fc00fc01 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r63.x } !+ 0001a100 SP_FS_MRT[0].REG: { REGID = r0.x | HALF_PRECISION | MRTFORMAT = RB4_R8G8B8A8_UNORM } + 00000000 0x230c: 00000000 + 7e020000 SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } + 00000000 SP_HS_OBJ_START: 0 + 00000000 0x2318: 00000000 + 00000000 0x2319: 00000000 + 7e020000 SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } + 00000000 SP_DS_OBJ_START: 0 + 00000000 0x2340: 00000000 + 7e020000 SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } + 00000000 SP_GS_OBJ_START: 0 + 00000808 TPL1_TP_TEX_OFFSET: 0x808 + 00000000 TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } !+ 00000002 0x2382: 00000002 !+ 00000000 TPL1_TP_FS_TEX_COUNT: 0 !+ 080604f0 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0x600a0 } !+ fcfc1108 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x1008 } !+ fff3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } + fcfcfc00 HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } !+ 00fcfc00 HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r0.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } !+ 01010002 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 2 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 1 } !+ 017f0202 HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 2 | CONSTOBJECTOFFSET = 2 | ENABLED | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 } !+ 007e0200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } !+ 007e0200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } !+ 007e0200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } !+ 00000003 HLSQ_UPDATE_CONTROL: 0x3 000555ac: 0000: c0023800 00200984 00000001 00000003 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 18 | GROUP_ID = 1 } { ADDR_LO = 0x9a8a0 } 000555bc: 0000: c0014300 01000012 0009a8a0 group_id: 1 count: 18 addr: 000000000009a8a0 flags: 0 0009a8a0: 0000: 00002200 082a0008 00002201 fcfc0081 00002203 0000fc00 0007220a 0008080f 0009a8c0: 0020: 0009a840 00000060 00000001 0000080f 0009a870 00000030 00000001 0001228a 0009a8e0: 0040: 7000411f 3000011f t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } 0009a8a0: 0000: 00002200 082a0008 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } 0009a8a8: 0000: 00002201 fcfc0081 t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } 0009a8b0: 0000: 00002203 0000fc00 t0 write VFD_FETCH[0].INSTR_0 (220a) VFD_FETCH[0].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 | SWITCHNEXT } VFD_FETCH[0].INSTR_1: 0x9a840 VFD_FETCH[0].INSTR_2: { SIZE = 0x60 } VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 } VFD_FETCH[0x1].INSTR_1: 0x9a870 VFD_FETCH[0x1].INSTR_2: { SIZE = 0x30 } VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } 0009a8b8: 0000: 0007220a 0008080f 0009a840 00000060 00000001 0000080f 0009a870 00000030 0009a8d8: 0020: 00000001 t0 write VFD_DECODE[0].INSTR (228a) VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID | SWITCHNEXT } VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID } 0009a8dc: 0000: 0001228a 7000411f 3000011f t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = USE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x200000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 3 } draw[32] register values + 082a0008 VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } + fcfc0081 VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } + 0000fc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } + 0008080f VFD_FETCH[0].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 | SWITCHNEXT } !+ 0009a840 VFD_FETCH[0].INSTR_1: 0x9a840 + 00000060 VFD_FETCH[0].INSTR_2: { SIZE = 0x60 } + 00000001 VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } + 0000080f VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 } !+ 0009a870 VFD_FETCH[0x1].INSTR_1: 0x9a870 + 00000030 VFD_FETCH[0x1].INSTR_2: { SIZE = 0x30 } + 00000001 VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } + 7000411f VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID | SWITCHNEXT } + 3000011f VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID } 000555c8: 0000: c0023800 00200984 00000001 00000003 0016b094: 0000: c0013f00 00055328 000000ac t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 0016b0a0: 0000: c0014300 00040000 00000000 t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:00171728 ibsize:000000f7 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00171728: 0000: c0002600 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x4 00171730: 0000: 00000ec3 00000004 t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x68 00171738: 0000: 00000f03 00000068 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00171740: 0000: c0002600 00000000 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } 00171748: 0000: 000023c0 080004f0 t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = 0x1d } event (null) 00171750: 0000: c0004600 0000001d t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = FACENESS_FLUSH } event FACENESS_FLUSH 00171758: 0000: c0004600 0000001c t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00171760: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0 00171768: 0000: 00000cc6 00000000 t0 write UNKNOWN_0E42 (0e42) UNKNOWN_0E42: 0 00171770: 0000: 00000e42 00000000 t0 write HLSQ_MODE_CONTROL (0e05) HLSQ_MODE_CONTROL: 0x2 00171778: 0000: 00000e05 00000002 t0 write UNKNOWN_0CC5 (0cc5) UNKNOWN_0CC5: 0x4 00171780: 0000: 00000cc5 00000004 t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x7 00171788: 0000: 000023db 00000007 t0 write VFD_CONTROL_2 (2202) VFD_CONTROL_2: 0xfcfcfcfc 00171790: 0000: 00002202 fcfcfcfc t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } 00171798: 0000: 00002203 fcfcfc00 t0 write VFD_CONTROL_4 (2204) VFD_CONTROL_4: 0xfcfc 001717a0: 0000: 00002204 0000fcfc t0 write VFD_INDEX_OFFSET (2208) VFD_INDEX_OFFSET: 0 001717a8: 0000: 00002208 00000000 t0 write UNKNOWN_2209 (2209) UNKNOWN_2209: 0 001717b0: 0000: 00002209 00000000 t0 write UNKNOWN_2152 (2152) UNKNOWN_2152: 0 UNKNOWN_2153: 0 001717b8: 0000: 00012152 00000000 00000000 t0 write UNKNOWN_2156 (2156) UNKNOWN_2156: 0 001717c4: 0000: 00002156 00000000 t0 write UNKNOWN_2154 (2154) UNKNOWN_2154: 0 001717cc: 0000: 00002154 00000000 t0 write UNKNOWN_2155 (2155) UNKNOWN_2155: 0 001717d4: 0000: 00002155 00000000 t0 write UNKNOWN_21C3 (21c3) UNKNOWN_21C3: 0x1d 001717dc: 0000: 000021c3 0000001d t0 write PC_PRIM_VTX_CNTL2 (21c5) PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 001717e4: 0000: 000021c5 00000012 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 001717ec: 0000: 000021e5 00000000 t0 write GRAS_SU_MODE_CONTROL (2078) GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } 001717f4: 0000: 00002078 00000000 t0 write UNKNOWN_2001 (2001) UNKNOWN_2001: 0 001717fc: 0000: 00002001 00000000 t0 write GRAS_CNTL (2003) GRAS_CNTL: { IJ_PERSP } 00171804: 0000: 00002003 00000001 t0 write GRAS_CL_CLIP_CNTL (2000) GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } 0017180c: 0000: 00002000 00188000 t0 write TPL1_TP_TEX_COUNT (2381) TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } 00171814: 0000: 00002381 00000000 t0 write TPL1_TP_FS_TEX_COUNT (23a0) TPL1_TP_FS_TEX_COUNT: 0x3 0017181c: 0000: 000023a0 00000003 t0 write RB_ALPHA_CONTROL (20f8) RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } 00171824: 0000: 000020f8 00000e00 t0 write RB_RENDER_COMPONENTS (20fb) RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } 0017182c: 0000: 000020fb 0000000f t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 00171834: 0000: c0014300 00040000 00000000 t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } 00171840: 0000: 00002200 000a0000 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } 00171848: 0000: 00002201 fc030000 t0 write SP_INSTR_CACHE_CTRL (22c1) SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } 00171850: 0000: 000022c1 000005c3 t0 write HLSQ_CONTROL_1_REG (23c1) HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } 00171858: 0000: 000023c1 fcfc0120 t0 write HLSQ_CONTROL_2_REG (23c2) HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 00171860: 0000: 000023c2 27f3f3f0 t0 write HLSQ_VS_CONTROL_REG (23c5) HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } 00171868: 0000: 000023c5 02010042 t0 write HLSQ_FS_CONTROL_REG (23c6) HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00171870: 0000: 000023c6 0041423e t0 write HLSQ_HS_CONTROL_REG (23c7) HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00171878: 0000: 000023c7 00404200 t0 write HLSQ_DS_CONTROL_REG (23c8) HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00171880: 0000: 000023c8 00404200 t0 write HLSQ_GS_CONTROL_REG (23c9) HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00171888: 0000: 000023c9 00404200 t0 write HLSQ_CS_CONTROL_REG (23ca) HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } 00171890: 0000: 000023ca 00004200 t0 write SP_SP_CTRL_REG (22c0) SP_SP_CTRL_REG: { 0x60010 } 00171898: 0000: 000022c0 00060010 t0 write UNKNOWN_21E6 (21e6) UNKNOWN_21E6: 0x1 001718a0: 0000: 000021e6 00000001 t0 write SP_VS_CTRL_REG0 (22c4) SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 001718a8: 0000: 000022c4 00200c10 t0 write SP_VS_CTRL_REG1 (22c5) SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } 001718b0: 0000: 000022c5 01000042 t0 write VPC_ATTR (2140) VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | 0x40000000 } 001718b8: 0000: 00002140 40001004 t0 write VPC_PACK (2141) VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } 001718c0: 0000: 00002141 00040400 t0 write PC_PRIM_VTX_CNTL (21c4) PC_PRIM_VTX_CNTL: { VAROUT = 1 } 001718c8: 0000: 000021c4 00000001 t0 write SP_VS_PARAM_REG (22c6) SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } UNKNOWN_22D7: 0xfcfc00 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 001718d0: 0000: 001922c6 0010fc03 00001e03 00000000 00000000 00000000 00000000 00000000 * 00171910: 0040: 00000000 00000000 00fcfc00 00000008 00000000 00000000 00000000 00000000 * t0 write SP_VS_OBJ_OFFSET_REG (22e0) SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 0017193c: 0000: 000022e0 00000000 t0 write SP_VS_OBJ_START (22e1) SP_VS_OBJ_START: 0x1 00171944: 0000: 000022e1 00000001 t0 write SP_VS_LENGTH_REG (22e5) SP_VS_LENGTH_REG: 2 0017194c: 0000: 000022e5 00000002 t3 opcode: CP_LOAD_STATE4 (30) (67 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } :2:0000:0000[56d81803x_20020003x] (sy)(ss)(nop3) shl.b r0.w, r0.w, 2 :1:0001:0004[20150000x_00000003x] cov.s32s16 hr0.x, r0.w :0:0002:0005[00000200x_00000000x] (rpt2)nop :1:0003:0008[201100f4x_00000000x] mova a0.x, hr0.x :0:0004:0009[00000500x_00000000x] (rpt5)nop :1:0005:0015[20154003x_00000c20x] mov.s32s32 r0.w, c :1:0006:0016[20154004x_00000c21x] mov.s32s32 r1.x, c :1:0007:0017[20154005x_00000c22x] mov.s32s32 r1.y, c :1:0008:0018[20156006x_00000c23x] (ul)mov.s32s32 r1.z, c :0:0009:0019[03000000x_00000000x] end :2:0010:0020[46f00007x_20050000x] shr.b r1.w, r0.x, 5 :2:0011:0021[43980008x_201f0000x] (nop2) and.b r2.x, r0.x, 31 :2:0012:0024[43980807x_201f0007x] (nop3) and.b r1.w, r1.w, 31 :2:0013:0028[46100807x_20100007x] (nop1) mul.u24 r1.w, r1.w, 16 :3:0014:0030[62040007x_00071014x] mad.u24 r1.w, c5.x, r2.x, r1.w :0:0015:0031[00000500x_00000000x] (rpt5)nop :6:0016:0037[c2c60f00x_04800006x] stlw.u32 l[r1.w], r0.w, 4 :0:0017:0038[04800000x_00000000x] chmask :0:0018:0039[05000000x_00000000x] chsh Stats: - shaderdb: 40 instr, 24 nops, 16 non-nops, 5 mov, 1 cov - shaderdb: 0 last-baryf, 0 half, 2 full, 5 constlen - shaderdb: 27 cat0, 6 cat1, 5 cat2, 1 cat3, 0 cat4, 0 cat5, 1 cat6, 0 cat7 - shaderdb: 0 sstall, 1 (ss), 1 (sy) 00171954: 0000: c0413000 00a00000 00000000 20020003 56d81803 00000003 20150000 00000000 00171974: 0020: 00000200 00000000 201100f4 00000000 00000500 00000c20 20154003 00000c21 00171994: 0040: 20154004 00000c22 20154005 00000c23 20156006 00000000 03000000 20050000 001719b4: 0060: 46f00007 201f0000 43980008 201f0007 43980807 20100007 46100807 00071014 001719d4: 0080: 62040007 00000000 00000500 04800006 c2c60f00 00000000 04800000 00000000 001719f4: 00a0: 05000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 * t0 write GRAS_SC_CONTROL (207b) GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = 0 | MSAA_DISABLE | RASTER_MODE = 0 } 00171a60: 0000: 0000207b 00000808 t0 write RB_MSAA_CONTROL (20a2) RB_MSAA_CONTROL: { DISABLE | SAMPLES = 0 } 00171a68: 0000: 000020a2 00001000 t0 write RB_RENDER_CONTROL (20a1) RB_RENDER_CONTROL: { DISABLE_COLOR_PIPE | 0x2 } 00171a70: 0000: 000020a1 00000022 t0 write RB_DEPTH_CONTROL (2101) RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } 00171a78: 0000: 00002101 00000000 t0 write GRAS_ALPHA_CONTROL (2073) GRAS_ALPHA_CONTROL: { 0x2 } 00171a80: 0000: 00002073 00000002 t0 write RB_STENCIL_CONTROL (2106) RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } 00171a88: 0000: 00002106 00000000 t0 write RB_COPY_CONTROL (20fc) RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_FOUR | MODE = RB_COPY_DEPTH_STENCIL | FASTCLEAR = 0 | GMEM_BASE = 0 } RB_COPY_DEST_BASE: { BASE = 0x4f000 } RB_COPY_DEST_PITCH: { PITCH = 256 } RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_DISABLE | COMPONENT_ENABLE = 0xf | ENDIAN = ENDIAN_NONE | TILE = TILE4_3 } 00171a90: 0000: 000320fc 00000052 0004f000 00000008 0303c068 t0 write UNKNOWN_20EF (20ef) UNKNOWN_20EF: 0 00171aa4: 0000: 000020ef 00000000 t0 write GRAS_SC_SCREEN_SCISSOR_TL (207c) GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } 00171aac: 0000: 0001207c 00000000 003f003f t0 write RB_FRAME_BUFFER_DIMENSION (0ce0) RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } 00171ab8: 0000: 00000ce0 00400040 t0 write 0xce1 (0ce1) 0xce1: 00000000 00171ac0: 0000: 00000ce1 00000000 t3 opcode: CP_LOAD_STATE4 (30) (11 dwords) { DST_OFF = 8 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } 00171ad4: 0.000000 0.000000 1.000000 1.000000 64.000000 64.000000 1.000000 1.000000 00171ad4: 0000: 00000000 00000000 3f800000 3f800000 42800000 42800000 3f800000 3f800000 00171ac8: 0000: c0093000 00a00008 00000001 00000000 00000000 3f800000 3f800000 42800000 00171ae8: 0020: 42800000 3f800000 3f800000 t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x80000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 2 } draw[33] register values + 00000004 UNKNOWN_0CC5: 0x4 + 00000000 UNKNOWN_0CC6: 0 + 00400040 RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } + 00000000 0xce1: 00000000 !+ 00000002 HLSQ_MODE_CONTROL: 0x2 + 00000000 UNKNOWN_0E42: 0 !+ 00000004 SP_MODE_CONTROL: 0x4 !+ 00000068 TPL1_TP_MODE_CONTROL: 0x68 !+ 00188000 GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } + 00000000 UNKNOWN_2001: 0 + 00000001 GRAS_CNTL: { IJ_PERSP } !+ 00000002 GRAS_ALPHA_CONTROL: { 0x2 } !+ 00000000 GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } !+ 00000808 GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = 0 | MSAA_DISABLE | RASTER_MODE = 0 } !+ 00000000 GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } !+ 003f003f GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } !+ 00000022 RB_RENDER_CONTROL: { DISABLE_COLOR_PIPE | 0x2 } !+ 00001000 RB_MSAA_CONTROL: { DISABLE | SAMPLES = 0 } + 00000000 UNKNOWN_20EF: 0 + 00000e00 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } + 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } !+ 00000052 RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_FOUR | MODE = RB_COPY_DEPTH_STENCIL | FASTCLEAR = 0 | GMEM_BASE = 0 } + 0004f000 RB_COPY_DEST_BASE: { BASE = 0x4f000 } + 00000008 RB_COPY_DEST_PITCH: { PITCH = 256 } !+ 0303c068 RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_DISABLE | COMPONENT_ENABLE = 0xf | ENDIAN = ENDIAN_NONE | TILE = TILE4_3 } + 00000000 RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } + 00000000 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } !+ 40001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | 0x40000000 } + 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } + 00000000 UNKNOWN_2152: 0 + 00000000 UNKNOWN_2153: 0 + 00000000 UNKNOWN_2154: 0 + 00000000 UNKNOWN_2155: 0 + 00000000 UNKNOWN_2156: 0 !+ 0000001d UNKNOWN_21C3: 0x1d !+ 00000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 } + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + 00000000 PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } + 00000001 UNKNOWN_21E6: 0x1 !+ 000a0000 VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } !+ fc030000 VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } + fcfcfcfc VFD_CONTROL_2: 0xfcfcfcfc !+ fcfcfc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } + 0000fcfc VFD_CONTROL_4: 0xfcfc + 00000000 VFD_INDEX_OFFSET: 0 + 00000000 UNKNOWN_2209: 0 + 00060010 SP_SP_CTRL_REG: { 0x60010 } + 000005c3 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } !+ 00200c10 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } !+ 01000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } !+ 0010fc03 SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } !+ 00001e03 SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00fcfc00 UNKNOWN_22D7: 0xfcfc00 + 00000008 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } !+ 00000001 SP_VS_OBJ_START: 0x1 !+ 00000002 SP_VS_LENGTH_REG: 2 + 00000000 TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } !+ 00000003 TPL1_TP_FS_TEX_COUNT: 0x3 !+ 080004f0 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } !+ fcfc0120 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } !+ 27f3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } !+ 02010042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } !+ 0041423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } !+ 00404200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } !+ 00404200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } !+ 00404200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00004200 HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } !+ 00000007 HLSQ_UPDATE_CONTROL: 0x7 00171af4: 0000: c0023800 00080888 00000001 00000002 0016b0ac: 0000: c0013f00 00171728 000000f7 t3 opcode: (null) (1d) (2 dwords) 0016b0b8: 0000: c0001d00 00000000 ############################################################ vertices: 0 ############################################################ cmdstream: 8 dwords t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:000555d8 ibsize:00000155 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 000555d8: 0000: c0002600 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x4 000555e0: 0000: 00000ec3 00000004 t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x68 000555e8: 0000: 00000f03 00000068 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 000555f0: 0000: c0002600 00000000 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } 000555f8: 0000: 000023c0 080004f0 t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = 0x1d } event (null) 00055600: 0000: c0004600 0000001d t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = FACENESS_FLUSH } event FACENESS_FLUSH 00055608: 0000: c0004600 0000001c t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00055610: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0 00055618: 0000: 00000cc6 00000000 t0 write UNKNOWN_0E42 (0e42) UNKNOWN_0E42: 0 00055620: 0000: 00000e42 00000000 t0 write HLSQ_MODE_CONTROL (0e05) HLSQ_MODE_CONTROL: 0x2 00055628: 0000: 00000e05 00000002 t0 write UNKNOWN_0CC5 (0cc5) UNKNOWN_0CC5: 0x4 00055630: 0000: 00000cc5 00000004 t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x7 00055638: 0000: 000023db 00000007 t0 write VFD_CONTROL_2 (2202) VFD_CONTROL_2: 0xfcfcfcfc 00055640: 0000: 00002202 fcfcfcfc t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } 00055648: 0000: 00002203 fcfcfc00 t0 write VFD_CONTROL_4 (2204) VFD_CONTROL_4: 0xfcfc 00055650: 0000: 00002204 0000fcfc t0 write VFD_INDEX_OFFSET (2208) VFD_INDEX_OFFSET: 0 00055658: 0000: 00002208 00000000 t0 write UNKNOWN_2209 (2209) UNKNOWN_2209: 0 00055660: 0000: 00002209 00000000 t0 write UNKNOWN_2152 (2152) UNKNOWN_2152: 0 UNKNOWN_2153: 0 00055668: 0000: 00012152 00000000 00000000 t0 write UNKNOWN_2156 (2156) UNKNOWN_2156: 0 00055674: 0000: 00002156 00000000 t0 write UNKNOWN_2154 (2154) UNKNOWN_2154: 0 0005567c: 0000: 00002154 00000000 t0 write UNKNOWN_2155 (2155) UNKNOWN_2155: 0 00055684: 0000: 00002155 00000000 t0 write UNKNOWN_21C3 (21c3) UNKNOWN_21C3: 0x1d 0005568c: 0000: 000021c3 0000001d t0 write PC_PRIM_VTX_CNTL2 (21c5) PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 00055694: 0000: 000021c5 00000012 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 0005569c: 0000: 000021e5 00000000 t0 write GRAS_SU_MODE_CONTROL (2078) GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } 000556a4: 0000: 00002078 00000000 t0 write UNKNOWN_2001 (2001) UNKNOWN_2001: 0 000556ac: 0000: 00002001 00000000 t0 write GRAS_CNTL (2003) GRAS_CNTL: { IJ_PERSP } 000556b4: 0000: 00002003 00000001 t0 write GRAS_CL_CLIP_CNTL (2000) GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } 000556bc: 0000: 00002000 00188000 t0 write TPL1_TP_TEX_COUNT (2381) TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } 000556c4: 0000: 00002381 00000000 t0 write TPL1_TP_FS_TEX_COUNT (23a0) TPL1_TP_FS_TEX_COUNT: 0x3 000556cc: 0000: 000023a0 00000003 t0 write RB_ALPHA_CONTROL (20f8) RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } 000556d4: 0000: 000020f8 00000e00 t0 write RB_RENDER_COMPONENTS (20fb) RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } 000556dc: 0000: 000020fb 0000000f t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 000556e4: 0000: c0014300 00040000 00000000 t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } 000556f0: 0000: 00002200 000a0000 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } 000556f8: 0000: 00002201 fc030000 t0 write SP_INSTR_CACHE_CTRL (22c1) SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } 00055700: 0000: 000022c1 000005c3 t0 write HLSQ_CONTROL_1_REG (23c1) HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } 00055708: 0000: 000023c1 fcfc0120 t0 write HLSQ_CONTROL_2_REG (23c2) HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 00055710: 0000: 000023c2 27f3f3f0 t0 write HLSQ_VS_CONTROL_REG (23c5) HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } 00055718: 0000: 000023c5 02010042 t0 write HLSQ_FS_CONTROL_REG (23c6) HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 1 } 00055720: 0000: 000023c6 0141423e t0 write HLSQ_HS_CONTROL_REG (23c7) HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00055728: 0000: 000023c7 00404200 t0 write HLSQ_DS_CONTROL_REG (23c8) HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00055730: 0000: 000023c8 00404200 t0 write HLSQ_GS_CONTROL_REG (23c9) HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00055738: 0000: 000023c9 00404200 t0 write HLSQ_CS_CONTROL_REG (23ca) HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } 00055740: 0000: 000023ca 00004200 t0 write SP_SP_CTRL_REG (22c0) SP_SP_CTRL_REG: { 0x60010 } 00055748: 0000: 000022c0 00060010 t0 write UNKNOWN_21E6 (21e6) UNKNOWN_21E6: 0x1 00055750: 0000: 000021e6 00000001 t0 write SP_VS_CTRL_REG0 (22c4) SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 00055758: 0000: 000022c4 00200c10 t0 write SP_VS_CTRL_REG1 (22c5) SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } 00055760: 0000: 000022c5 01000042 t0 write VPC_ATTR (2140) VPC_ATTR: { TOTALATTR = 8 | THRDASSIGN = 1 | ENABLE | 0x40000000 } 00055768: 0000: 00002140 42001008 t0 write VPC_PACK (2141) VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 8 | NUMNONPOSVSVAR = 6 } 00055770: 0000: 00002141 00060800 t0 write PC_PRIM_VTX_CNTL (21c4) PC_PRIM_VTX_CNTL: { VAROUT = 1 } 00055778: 0000: 000021c4 00000001 t0 write SP_VS_PARAM_REG (22c6) SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 2 } SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r1.w | B_COMPMASK = 0x3 } SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } UNKNOWN_22D7: 0xfcfc00 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 12 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 00055780: 0000: 001922c6 0020fc03 06071e03 00000000 00000000 00000000 00000000 00000000 * 000557c0: 0040: 00000000 00000000 00fcfc00 00000c08 00000000 00000000 00000000 00000000 * t0 write SP_VS_OBJ_OFFSET_REG (22e0) SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 000557ec: 0000: 000022e0 00000000 t0 write SP_VS_OBJ_START (22e1) SP_VS_OBJ_START: 0x1 000557f4: 0000: 000022e1 00000001 t0 write SP_VS_LENGTH_REG (22e5) SP_VS_LENGTH_REG: 2 000557fc: 0000: 000022e5 00000002 t3 opcode: CP_LOAD_STATE4 (30) (67 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } :2:0000:0000[56d81803x_20020003x] (sy)(ss)(nop3) shl.b r0.w, r0.w, 2 :1:0001:0004[20150000x_00000003x] cov.s32s16 hr0.x, r0.w :0:0002:0005[00000200x_00000000x] (rpt2)nop :1:0003:0008[201100f4x_00000000x] mova a0.x, hr0.x :0:0004:0009[00000500x_00000000x] (rpt5)nop :1:0005:0015[20154003x_00000c20x] mov.s32s32 r0.w, c :1:0006:0016[20154004x_00000c21x] mov.s32s32 r1.x, c :1:0007:0017[20154007x_00000c22x] mov.s32s32 r1.w, c :1:0008:0018[20156008x_00000c23x] (ul)mov.s32s32 r2.x, c :1:0009:0019[20554005x_00000000x] mov.s32s32 r1.y, 0 :1:0010:0020[20554006x_3f800000x] mov.s32s32 r1.z, 1065353216 :0:0011:0021[03000000x_00000000x] end :2:0012:0022[46f00009x_20050000x] shr.b r2.y, r0.x, 5 :2:0013:0023[4398000ax_201f0000x] (nop2) and.b r2.z, r0.x, 31 :2:0014:0026[43980809x_201f0009x] (nop3) and.b r2.y, r2.y, 31 :2:0015:0030[46100809x_20180009x] (nop1) mul.u24 r2.y, r2.y, 24 :3:0016:0032[62050009x_00091014x] mad.u24 r2.y, c5.x, r2.z, r2.y :0:0017:0033[00000500x_00000000x] (rpt5)nop :6:0018:0039[c2c61300x_04800006x] stlw.u32 l[r2.y], r0.w, 4 :6:0019:0040[c2c61310x_0280000ex] stlw.u32 l[r2.y+16], r1.w, 2 :0:0020:0041[04800000x_00000000x] chmask :0:0021:0042[05000000x_00000000x] chsh Stats: - shaderdb: 43 instr, 24 nops, 19 non-nops, 7 mov, 1 cov - shaderdb: 0 last-baryf, 0 half, 3 full, 5 constlen - shaderdb: 27 cat0, 8 cat1, 5 cat2, 1 cat3, 0 cat4, 0 cat5, 2 cat6, 0 cat7 - shaderdb: 0 sstall, 1 (ss), 1 (sy) 00055804: 0000: c0413000 00a00000 00000000 20020003 56d81803 00000003 20150000 00000000 00055824: 0020: 00000200 00000000 201100f4 00000000 00000500 00000c20 20154003 00000c21 00055844: 0040: 20154004 00000c22 20154007 00000c23 20156008 00000000 20554005 3f800000 00055864: 0060: 20554006 00000000 03000000 20050000 46f00009 201f0000 4398000a 201f0009 00055884: 0080: 43980809 20180009 46100809 00091014 62050009 00000000 00000500 04800006 000558a4: 00a0: c2c61300 0280000e c2c61310 00000000 04800000 00000000 05000000 00000000 * t0 write HLSQ_CONTROL_3_REG (23c3) HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } 00055910: 0000: 000023c3 fcfcfc00 t0 write HLSQ_CONTROL_4_REG (23c4) HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } 00055918: 0000: 000023c4 00fcfcfc t0 write SP_FS_CTRL_REG0 (22e8) SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 0 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE | PIXLODENABLE } SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 } 00055920: 0000: 000122e8 00700402 8010003e t0 write SP_FS_OBJ_OFFSET_REG (22ea) SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 } 0005592c: 0000: 000022ea 40420000 t0 write SP_FS_OBJ_START (22eb) SP_FS_OBJ_START: 0x1 00055934: 0000: 000022eb 00000001 t0 write SP_FS_LENGTH_REG (22ef) SP_FS_LENGTH_REG: 1 0005593c: 0000: 000022ef 00000001 t0 write SP_FS_OUTPUT_REG (22f0) SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r0.x | SAMPLEMASK_REGID = r0.x } 00055944: 0000: 000022f0 00000001 t0 write VPC_VARYING_INTERP[0].MODE (2142) VPC_VARYING_INTERP[0].MODE: 0xe000 0005594c: 0000: 00002142 0000e000 t0 write RB_FS_OUTPUT_REG (2100) RB_FS_OUTPUT_REG: { MRT = 1 } 00055954: 0000: 00002100 00000001 t3 opcode: CP_LOAD_STATE4 (30) (35 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 1 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } :2:0000:0000[57309902x_00002004x] (sy)(ss)(rpt1)bary.f (ei)r0.z, (r)4, r0.x :0:0001:0002[00000500x_00000000x] (rpt5)nop :5:0002:0008[a0c01f00x_00000005x] sam (f32)(xyzw)r0.x, r0.z, s#0, t#0 :0:0003:0009[03000000x_00000000x] end :0:0004:0010[00000000x_00000000x] nop :0:0005:0011[00000000x_00000000x] nop :0:0006:0012[00000000x_00000000x] nop :0:0007:0013[00000000x_00000000x] nop Stats: - shaderdb: 14 instr, 10 nops, 4 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 0 half, 1 full, 0 constlen - shaderdb: 11 cat0, 0 cat1, 2 cat2, 0 cat3, 0 cat4, 1 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 1 (ss), 1 (sy) 0005595c: 0000: c0213000 00700000 00000000 00002004 57309902 00000000 00000500 00000005 0005597c: 0020: a0c01f00 00000000 03000000 00000000 00000000 00000000 00000000 00000000 * t0 write RB_FS_OUTPUT (20f9) RB_FS_OUTPUT: { ENABLE_BLEND = 0 | SAMPLE_MASK = 0xffff } 000559e8: 0000: 000020f9 ffff0000 t0 write RB_MRT[0].CONTROL (20a4) RB_MRT[0].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0xf } 000559f0: 0000: 000020a4 0f000000 t0 write RB_MRT[0x1].CONTROL (20a9) RB_MRT[0x1].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0xf } 000559f8: 0000: 000020a9 0f000000 t0 write RB_MRT[0].BLEND_CONTROL (20a8) RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } 00055a00: 0000: 000020a8 00000000 t3 opcode: CP_LOAD_STATE4 (30) (5 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_TEX | NUM_UNIT = 1 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } { XY_MAG = A4XX_TEX_NEAREST | XY_MIN = A4XX_TEX_NEAREST | WRAP_S = A4XX_TEX_CLAMP_TO_EDGE | WRAP_T = A4XX_TEX_CLAMP_TO_EDGE | WRAP_R = A4XX_TEX_CLAMP_TO_EDGE | ANISO = A4XX_TEX_ANISO_1 | LOD_BIAS = 0.000000 | 0x60000 } { COMPARE_FUNC = FUNC_LEQUAL | UNNORM_COORDS | MIPFILTER_LINEAR_FAR | MAX_LOD = 0.000000 | MIN_LOD = 0.000000 | 0x1 } 00055a14: 0000: 00060920 00000067 00055a08: 0000: c0033000 00500000 00000000 00060920 00000067 t0 write GRAS_SC_CONTROL (207b) GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 0 | RASTER_MODE = 0 } 00055a1c: 0000: 0000207b 00000000 t0 write RB_MSAA_CONTROL (20a2) RB_MSAA_CONTROL: { SAMPLES = 0 } 00055a24: 0000: 000020a2 00000000 t0 write RB_RENDER_CONTROL (20a1) RB_RENDER_CONTROL: { 0 } 00055a2c: 0000: 000020a1 00000000 t0 write 0x2382 (2382) 0x2382: 00000000 00055a34: 0000: 00002382 00000000 t0 write RB_DEPTH_CONTROL (2101) RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } 00055a3c: 0000: 00002101 00000000 t0 write GRAS_ALPHA_CONTROL (2073) GRAS_ALPHA_CONTROL: { 0 } 00055a44: 0000: 00002073 00000000 t0 write RB_STENCIL_CONTROL (2106) RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } 00055a4c: 0000: 00002106 00000000 t0 write SP_FS_MRT[0].REG (22f1) SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = RB4_R8G8B8A8_UNORM } 00055a54: 0000: 000022f1 0001a000 t0 write RB_MRT[0].BUF_INFO (20a5) RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB4_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE4_3 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 256 } RB_MRT[0].BASE: 0x166000 RB_MRT[0].CONTROL3: { STRIDE = 0 } 00055a5c: 0000: 000220a5 000400da 00166000 00000000 t3 opcode: CP_LOAD_STATE4 (30) (11 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_TEX | NUM_UNIT = 1 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } { TILED | SWIZ_X = A4XX_TEX_X | SWIZ_Y = A4XX_TEX_Y | SWIZ_Z = A4XX_TEX_Z | SWIZ_W = A4XX_TEX_W | MIPLVLS = 0 | FMT = TFMT4_8_8_8_8_UNORM | TYPE = A4XX_TEX_2D | 0x2 } { HEIGHT = 64 | WIDTH = 64 } { PITCHALIGN = 0 | PITCH = 256 | SWAP = WZYX } { LAYERSZ = 0 | DEPTH = 1 | 0x20000 } { LAYERSZ = 4096 | BASE = 0x4f000 } { 5 = 0 } { 6 = 0 } { 7 = 0 } 00055a78: 0000: 27006883 00200040 00020000 00060000 0004f001 00000000 00000000 00000000 00055a6c: 0000: c0093000 00500000 00000001 27006883 00200040 00020000 00060000 0004f001 * t0 write VPC_VARYING_PS_REPL[0].MODE (214a) VPC_VARYING_PS_REPL[0].MODE: 0x99999999 00055a98: 0000: 0000214a 99999999 t0 write GRAS_SC_SCREEN_SCISSOR_TL (207c) GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } 00055aa0: 0000: 0001207c 00000000 003f003f t0 write GRAS_SC_WINDOW_SCISSOR_BR (209c) GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 00055aac: 0000: 0001209c 003f003f 00000000 t0 write RB_FRAME_BUFFER_DIMENSION (0ce0) RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } 00055ab8: 0000: 00000ce0 00400040 t0 write 0xce1 (0ce1) 0xce1: 00000000 00055ac0: 0000: 00000ce1 00000000 t0 write RB_RENDER_CONTROL2 (20a3) RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 | IJ_PERSP_PIXEL } 00055ac8: 0000: 000020a3 00001000 t0 write RB_MODE_CONTROL (20a0) RB_MODE_CONTROL: { WIDTH = 0 | HEIGHT = 0 | 0xc00000 } 00055ad0: 0000: 000020a0 00c00000 t3 opcode: CP_LOAD_STATE4 (30) (11 dwords) { DST_OFF = 8 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } 00055ae4: 0.000000 0.000000 0.000000 0.000000 64.000000 64.000000 64.000000 64.000000 00055ae4: 0000: 00000000 00000000 00000000 00000000 42800000 42800000 42800000 42800000 00055ad8: 0000: c0093000 00a00008 00000001 00000000 00000000 00000000 00000000 42800000 00055af8: 0020: 42800000 42800000 42800000 t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x80000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 2 } draw[34] register values + 00000004 UNKNOWN_0CC5: 0x4 + 00000000 UNKNOWN_0CC6: 0 + 00400040 RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } + 00000000 0xce1: 00000000 + 00000002 HLSQ_MODE_CONTROL: 0x2 + 00000000 UNKNOWN_0E42: 0 + 00000004 SP_MODE_CONTROL: 0x4 + 00000068 TPL1_TP_MODE_CONTROL: 0x68 + 00188000 GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } + 00000000 UNKNOWN_2001: 0 + 00000001 GRAS_CNTL: { IJ_PERSP } !+ 00000000 GRAS_ALPHA_CONTROL: { 0 } + 00000000 GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } !+ 00000000 GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 0 | RASTER_MODE = 0 } + 00000000 GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } + 003f003f GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } + 003f003f GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } + 00000000 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } !+ 00c00000 RB_MODE_CONTROL: { WIDTH = 0 | HEIGHT = 0 | 0xc00000 } !+ 00000000 RB_RENDER_CONTROL: { 0 } !+ 00000000 RB_MSAA_CONTROL: { SAMPLES = 0 } !+ 00001000 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 | IJ_PERSP_PIXEL } !+ 0f000000 RB_MRT[0].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0xf } !+ 000400da RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB4_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE4_3 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 256 } !+ 00166000 RB_MRT[0].BASE: 0x166000 !+ 00000000 RB_MRT[0].CONTROL3: { STRIDE = 0 } + 00000000 RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } + 0f000000 RB_MRT[0x1].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0xf } + 00000e00 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } !+ ffff0000 RB_FS_OUTPUT: { ENABLE_BLEND = 0 | SAMPLE_MASK = 0xffff } + 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } + 00000001 RB_FS_OUTPUT_REG: { MRT = 1 } + 00000000 RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } + 00000000 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } !+ 42001008 VPC_ATTR: { TOTALATTR = 8 | THRDASSIGN = 1 | ENABLE | 0x40000000 } !+ 00060800 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 8 | NUMNONPOSVSVAR = 6 } !+ 0000e000 VPC_VARYING_INTERP[0].MODE: 0xe000 !+ 99999999 VPC_VARYING_PS_REPL[0].MODE: 0x99999999 + 00000000 UNKNOWN_2152: 0 + 00000000 UNKNOWN_2153: 0 + 00000000 UNKNOWN_2154: 0 + 00000000 UNKNOWN_2155: 0 + 00000000 UNKNOWN_2156: 0 + 0000001d UNKNOWN_21C3: 0x1d + 00000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 } + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + 00000000 PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } + 00000001 UNKNOWN_21E6: 0x1 + 000a0000 VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } + fc030000 VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } + fcfcfcfc VFD_CONTROL_2: 0xfcfcfcfc + fcfcfc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } + 0000fcfc VFD_CONTROL_4: 0xfcfc + 00000000 VFD_INDEX_OFFSET: 0 + 00000000 UNKNOWN_2209: 0 + 00060010 SP_SP_CTRL_REG: { 0x60010 } + 000005c3 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } + 00200c10 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } + 01000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } !+ 0020fc03 SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 2 } !+ 06071e03 SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r1.w | B_COMPMASK = 0x3 } + 00000000 SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00fcfc00 UNKNOWN_22D7: 0xfcfc00 !+ 00000c08 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 12 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } + 00000001 SP_VS_OBJ_START: 0x1 + 00000002 SP_VS_LENGTH_REG: 2 !+ 00700402 SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 0 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE | PIXLODENABLE } !+ 8010003e SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 } !+ 40420000 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 } !+ 00000001 SP_FS_OBJ_START: 0x1 + 00000001 SP_FS_LENGTH_REG: 1 !+ 00000001 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r0.x | SAMPLEMASK_REGID = r0.x } !+ 0001a000 SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = RB4_R8G8B8A8_UNORM } + 00000000 TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } !+ 00000000 0x2382: 00000000 + 00000003 TPL1_TP_FS_TEX_COUNT: 0x3 + 080004f0 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } + fcfc0120 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } + 27f3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } + fcfcfc00 HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } !+ 00fcfcfc HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } + 02010042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } !+ 0141423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 1 } + 00404200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00004200 HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } + 00000007 HLSQ_UPDATE_CONTROL: 0x7 00055b04: 0000: c0023800 00080888 00000001 00000002 t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = CACHE_FLUSH } event CACHE_FLUSH 00055b14: 0000: c0004600 00000006 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00055b1c: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0x8000012 00055b24: 0000: 00000cc6 08000012 00173000: 0000: c0013f00 000555d8 00000155 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 0017300c: 0000: c0014300 00040000 00000000 t3 opcode: (null) (1d) (2 dwords) 00173018: 0000: c0001d00 00000000 ############################################################ vertices: 0 ############################################################ cmdstream: 48 dwords t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 0016b000: 0000: c0002600 00000000 t0 write UCHE_INVALIDATE0 (0e8a) UCHE_INVALIDATE0: 0 UCHE_INVALIDATE1: 0x12 0016b008: 0000: 00010e8a 00000000 00000012 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 0016b014: 0000: c0002600 00000000 t0 write RB_MODE_CONTROL (20a0) RB_MODE_CONTROL: { WIDTH = 64 | HEIGHT = 64 | ENABLE_GMEM } 0016b01c: 0000: 000020a0 00010202 t0 write RB_FRAME_BUFFER_DIMENSION (0ce0) RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } 0016b024: 0000: 00000ce0 00400040 t0 write 0xce1 (0ce1) 0xce1: 00000001 0016b02c: 0000: 00000ce1 00000001 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 0016b034: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0 0016b03c: 0000: 00000cc6 00000000 t3 opcode: (null) (1d) (2 dwords) 0016b044: 0000: c0001d00 00000000 t0 write GRAS_SC_WINDOW_SCISSOR_BR (209c) GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 0016b04c: 0000: 0001209c 003f003f 00000000 t0 write RB_BIN_OFFSET (210d) RB_BIN_OFFSET: { X = 0 | Y = 0 } 0016b058: 0000: 0000210d 00000000 t0 write GRAS_SC_WINDOW_SCISSOR_BR (209c) GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 0016b060: 0000: 0001209c 003f003f 00000000 t0 write UNKNOWN_2157 (2157) UNKNOWN_2157: 0x1 0016b06c: 0000: 00002157 00000001 t3 opcode: (null) (64) (2 dwords) 0016b074: 0000: c0006400 00000001 t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:00054994 ibsize:000000f6 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00054994: 0000: c0002600 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x4 0005499c: 0000: 00000ec3 00000004 t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x68 000549a4: 0000: 00000f03 00000068 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 000549ac: 0000: c0002600 00000000 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } 000549b4: 0000: 000023c0 080004f0 t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = 0x1d } event (null) 000549bc: 0000: c0004600 0000001d t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = FACENESS_FLUSH } event FACENESS_FLUSH 000549c4: 0000: c0004600 0000001c t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 000549cc: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0 000549d4: 0000: 00000cc6 00000000 t0 write UNKNOWN_0E42 (0e42) UNKNOWN_0E42: 0 000549dc: 0000: 00000e42 00000000 t0 write HLSQ_MODE_CONTROL (0e05) HLSQ_MODE_CONTROL: 0x2 000549e4: 0000: 00000e05 00000002 t0 write UNKNOWN_0CC5 (0cc5) UNKNOWN_0CC5: 0x4 000549ec: 0000: 00000cc5 00000004 t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x7 000549f4: 0000: 000023db 00000007 t0 write VFD_CONTROL_2 (2202) VFD_CONTROL_2: 0xfcfcfcfc 000549fc: 0000: 00002202 fcfcfcfc t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } 00054a04: 0000: 00002203 fcfcfc00 t0 write VFD_CONTROL_4 (2204) VFD_CONTROL_4: 0xfcfc 00054a0c: 0000: 00002204 0000fcfc t0 write VFD_INDEX_OFFSET (2208) VFD_INDEX_OFFSET: 0 00054a14: 0000: 00002208 00000000 t0 write UNKNOWN_2209 (2209) UNKNOWN_2209: 0 00054a1c: 0000: 00002209 00000000 t0 write UNKNOWN_2152 (2152) UNKNOWN_2152: 0 UNKNOWN_2153: 0 00054a24: 0000: 00012152 00000000 00000000 t0 write UNKNOWN_2156 (2156) UNKNOWN_2156: 0 00054a30: 0000: 00002156 00000000 t0 write UNKNOWN_2154 (2154) UNKNOWN_2154: 0 00054a38: 0000: 00002154 00000000 t0 write UNKNOWN_2155 (2155) UNKNOWN_2155: 0 00054a40: 0000: 00002155 00000000 t0 write UNKNOWN_21C3 (21c3) UNKNOWN_21C3: 0x1d 00054a48: 0000: 000021c3 0000001d t0 write PC_PRIM_VTX_CNTL2 (21c5) PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 00054a50: 0000: 000021c5 00000012 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 00054a58: 0000: 000021e5 00000000 t0 write GRAS_SU_MODE_CONTROL (2078) GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } 00054a60: 0000: 00002078 00000000 t0 write UNKNOWN_2001 (2001) UNKNOWN_2001: 0 00054a68: 0000: 00002001 00000000 t0 write GRAS_CNTL (2003) GRAS_CNTL: { IJ_PERSP } 00054a70: 0000: 00002003 00000001 t0 write GRAS_CL_CLIP_CNTL (2000) GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } 00054a78: 0000: 00002000 00188000 t0 write TPL1_TP_TEX_COUNT (2381) TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } 00054a80: 0000: 00002381 00000000 t0 write TPL1_TP_FS_TEX_COUNT (23a0) TPL1_TP_FS_TEX_COUNT: 0x3 00054a88: 0000: 000023a0 00000003 t0 write RB_ALPHA_CONTROL (20f8) RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } 00054a90: 0000: 000020f8 00000e00 t0 write RB_RENDER_COMPONENTS (20fb) RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } 00054a98: 0000: 000020fb 0000000f t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 00054aa0: 0000: c0014300 00040000 00000000 t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } 00054aac: 0000: 00002200 000a0000 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } 00054ab4: 0000: 00002201 fc030000 t0 write SP_INSTR_CACHE_CTRL (22c1) SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } 00054abc: 0000: 000022c1 000005c3 t0 write HLSQ_CONTROL_1_REG (23c1) HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } 00054ac4: 0000: 000023c1 fcfc0120 t0 write HLSQ_CONTROL_2_REG (23c2) HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 00054acc: 0000: 000023c2 27f3f3f0 t0 write HLSQ_VS_CONTROL_REG (23c5) HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } 00054ad4: 0000: 000023c5 02010042 t0 write HLSQ_FS_CONTROL_REG (23c6) HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00054adc: 0000: 000023c6 0041423e t0 write HLSQ_HS_CONTROL_REG (23c7) HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00054ae4: 0000: 000023c7 00404200 t0 write HLSQ_DS_CONTROL_REG (23c8) HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00054aec: 0000: 000023c8 00404200 t0 write HLSQ_GS_CONTROL_REG (23c9) HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00054af4: 0000: 000023c9 00404200 t0 write HLSQ_CS_CONTROL_REG (23ca) HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } 00054afc: 0000: 000023ca 00004200 t0 write SP_SP_CTRL_REG (22c0) SP_SP_CTRL_REG: { 0x60010 } 00054b04: 0000: 000022c0 00060010 t0 write UNKNOWN_21E6 (21e6) UNKNOWN_21E6: 0x1 00054b0c: 0000: 000021e6 00000001 t0 write SP_VS_CTRL_REG0 (22c4) SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 00054b14: 0000: 000022c4 00200c10 t0 write SP_VS_CTRL_REG1 (22c5) SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } 00054b1c: 0000: 000022c5 01000042 t0 write VPC_ATTR (2140) VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | 0x40000000 } 00054b24: 0000: 00002140 40001004 t0 write VPC_PACK (2141) VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } 00054b2c: 0000: 00002141 00040400 t0 write PC_PRIM_VTX_CNTL (21c4) PC_PRIM_VTX_CNTL: { VAROUT = 1 } 00054b34: 0000: 000021c4 00000001 t0 write SP_VS_PARAM_REG (22c6) SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } UNKNOWN_22D7: 0xfcfc00 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 00054b3c: 0000: 001922c6 0010fc03 00001e03 00000000 00000000 00000000 00000000 00000000 * 00054b7c: 0040: 00000000 00000000 00fcfc00 00000008 00000000 00000000 00000000 00000000 * t0 write SP_VS_OBJ_OFFSET_REG (22e0) SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 00054ba8: 0000: 000022e0 00000000 t0 write SP_VS_OBJ_START (22e1) SP_VS_OBJ_START: 0x1 00054bb0: 0000: 000022e1 00000001 t0 write SP_VS_LENGTH_REG (22e5) SP_VS_LENGTH_REG: 2 00054bb8: 0000: 000022e5 00000002 t3 opcode: CP_LOAD_STATE4 (30) (67 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } :2:0000:0000[56d81803x_20020003x] (sy)(ss)(nop3) shl.b r0.w, r0.w, 2 :1:0001:0004[20150000x_00000003x] cov.s32s16 hr0.x, r0.w :0:0002:0005[00000200x_00000000x] (rpt2)nop :1:0003:0008[201100f4x_00000000x] mova a0.x, hr0.x :0:0004:0009[00000500x_00000000x] (rpt5)nop :1:0005:0015[20154003x_00000c20x] mov.s32s32 r0.w, c :1:0006:0016[20154004x_00000c21x] mov.s32s32 r1.x, c :1:0007:0017[20154005x_00000c22x] mov.s32s32 r1.y, c :1:0008:0018[20156006x_00000c23x] (ul)mov.s32s32 r1.z, c :0:0009:0019[03000000x_00000000x] end :2:0010:0020[46f00007x_20050000x] shr.b r1.w, r0.x, 5 :2:0011:0021[43980008x_201f0000x] (nop2) and.b r2.x, r0.x, 31 :2:0012:0024[43980807x_201f0007x] (nop3) and.b r1.w, r1.w, 31 :2:0013:0028[46100807x_20100007x] (nop1) mul.u24 r1.w, r1.w, 16 :3:0014:0030[62040007x_00071014x] mad.u24 r1.w, c5.x, r2.x, r1.w :0:0015:0031[00000500x_00000000x] (rpt5)nop :6:0016:0037[c2c60f00x_04800006x] stlw.u32 l[r1.w], r0.w, 4 :0:0017:0038[04800000x_00000000x] chmask :0:0018:0039[05000000x_00000000x] chsh Stats: - shaderdb: 40 instr, 24 nops, 16 non-nops, 5 mov, 1 cov - shaderdb: 0 last-baryf, 0 half, 2 full, 5 constlen - shaderdb: 27 cat0, 6 cat1, 5 cat2, 1 cat3, 0 cat4, 0 cat5, 1 cat6, 0 cat7 - shaderdb: 0 sstall, 1 (ss), 1 (sy) 00054bc0: 0000: c0413000 00a00000 00000000 20020003 56d81803 00000003 20150000 00000000 00054be0: 0020: 00000200 00000000 201100f4 00000000 00000500 00000c20 20154003 00000c21 00054c00: 0040: 20154004 00000c22 20154005 00000c23 20156006 00000000 03000000 20050000 00054c20: 0060: 46f00007 201f0000 43980008 201f0007 43980807 20100007 46100807 00071014 00054c40: 0080: 62040007 00000000 00000500 04800006 c2c60f00 00000000 04800000 00000000 00054c60: 00a0: 05000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 * t0 write GRAS_ALPHA_CONTROL (2073) GRAS_ALPHA_CONTROL: { 0x2 } 00054ccc: 0000: 00002073 00000002 t0 write GRAS_SC_CONTROL (207b) GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = 4 | MSAA_DISABLE | RASTER_MODE = 0 } 00054cd4: 0000: 0000207b 00000a08 t0 write RB_MSAA_CONTROL (20a2) RB_MSAA_CONTROL: { DISABLE | SAMPLES = 4 } 00054cdc: 0000: 000020a2 00009000 t0 write RB_RENDER_CONTROL (20a1) RB_RENDER_CONTROL: { DISABLE_COLOR_PIPE | 0x2 } 00054ce4: 0000: 000020a1 00000022 t0 write RB_CLEAR_COLOR_DW0 (20cc) RB_CLEAR_COLOR_DW0: 0xff000000 RB_CLEAR_COLOR_DW1: 0 RB_CLEAR_COLOR_DW2: 0 RB_CLEAR_COLOR_DW3: 0 00054cec: 0000: 000320cc ff000000 00000000 00000000 00000000 t0 write RB_COPY_CONTROL (20fc) RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_FOUR | MODE = RB_COPY_CLEAR | FASTCLEAR = 0xf | GMEM_BASE = 0 } RB_COPY_DEST_BASE: { BASE = 0x4f000 } RB_COPY_DEST_PITCH: { PITCH = 256 } RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_IF_ALPHA_OFF | COMPONENT_ENABLE = 0 | ENDIAN = ENDIAN_NONE | TILE = TILE4_3 } 00054d00: 0000: 000320fc 00000f22 0004f000 00000008 03000868 t0 write GRAS_SC_SCREEN_SCISSOR_TL (207c) GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } 00054d14: 0000: 0001207c 00000000 003f003f t0 write RB_FRAME_BUFFER_DIMENSION (0ce0) RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } 00054d20: 0000: 00000ce0 00400040 t0 write 0xce1 (0ce1) 0xce1: 00000000 00054d28: 0000: 00000ce1 00000000 t3 opcode: CP_LOAD_STATE4 (30) (11 dwords) { DST_OFF = 8 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } 00054d3c: 0.000000 0.000000 1.000000 1.000000 64.000000 64.000000 1.000000 1.000000 00054d3c: 0000: 00000000 00000000 3f800000 3f800000 42800000 42800000 3f800000 3f800000 00054d30: 0000: c0093000 00a00008 00000001 00000000 00000000 3f800000 3f800000 42800000 00054d50: 0020: 42800000 3f800000 3f800000 t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x80000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 2 } draw[35] register values + 00000004 UNKNOWN_0CC5: 0x4 + 00000000 UNKNOWN_0CC6: 0 + 00400040 RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } + 00000000 0xce1: 00000000 + 00000002 HLSQ_MODE_CONTROL: 0x2 + 00000000 UNKNOWN_0E42: 0 + 00000000 UCHE_INVALIDATE0: 0 + 00000012 UCHE_INVALIDATE1: 0x12 + 00000004 SP_MODE_CONTROL: 0x4 + 00000068 TPL1_TP_MODE_CONTROL: 0x68 + 00188000 GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } + 00000000 UNKNOWN_2001: 0 + 00000001 GRAS_CNTL: { IJ_PERSP } !+ 00000002 GRAS_ALPHA_CONTROL: { 0x2 } + 00000000 GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } !+ 00000a08 GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = 4 | MSAA_DISABLE | RASTER_MODE = 0 } + 00000000 GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } + 003f003f GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } + 003f003f GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } + 00000000 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } !+ 00010202 RB_MODE_CONTROL: { WIDTH = 64 | HEIGHT = 64 | ENABLE_GMEM } !+ 00000022 RB_RENDER_CONTROL: { DISABLE_COLOR_PIPE | 0x2 } !+ 00009000 RB_MSAA_CONTROL: { DISABLE | SAMPLES = 4 } + ff000000 RB_CLEAR_COLOR_DW0: 0xff000000 + 00000000 RB_CLEAR_COLOR_DW1: 0 + 00000000 RB_CLEAR_COLOR_DW2: 0 + 00000000 RB_CLEAR_COLOR_DW3: 0 + 00000e00 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } + 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } !+ 00000f22 RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_FOUR | MODE = RB_COPY_CLEAR | FASTCLEAR = 0xf | GMEM_BASE = 0 } + 0004f000 RB_COPY_DEST_BASE: { BASE = 0x4f000 } + 00000008 RB_COPY_DEST_PITCH: { PITCH = 256 } !+ 03000868 RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_IF_ALPHA_OFF | COMPONENT_ENABLE = 0 | ENDIAN = ENDIAN_NONE | TILE = TILE4_3 } + 00000000 RB_BIN_OFFSET: { X = 0 | Y = 0 } !+ 40001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | 0x40000000 } !+ 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } + 00000000 UNKNOWN_2152: 0 + 00000000 UNKNOWN_2153: 0 + 00000000 UNKNOWN_2154: 0 + 00000000 UNKNOWN_2155: 0 + 00000000 UNKNOWN_2156: 0 + 00000001 UNKNOWN_2157: 0x1 + 0000001d UNKNOWN_21C3: 0x1d + 00000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 } + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + 00000000 PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } + 00000001 UNKNOWN_21E6: 0x1 + 000a0000 VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } + fc030000 VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } + fcfcfcfc VFD_CONTROL_2: 0xfcfcfcfc + fcfcfc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } + 0000fcfc VFD_CONTROL_4: 0xfcfc + 00000000 VFD_INDEX_OFFSET: 0 + 00000000 UNKNOWN_2209: 0 + 00060010 SP_SP_CTRL_REG: { 0x60010 } + 000005c3 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } + 00200c10 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } + 01000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } !+ 0010fc03 SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } !+ 00001e03 SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00fcfc00 UNKNOWN_22D7: 0xfcfc00 !+ 00000008 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } + 00000001 SP_VS_OBJ_START: 0x1 + 00000002 SP_VS_LENGTH_REG: 2 + 00000000 TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } + 00000003 TPL1_TP_FS_TEX_COUNT: 0x3 + 080004f0 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } + fcfc0120 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } + 27f3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } + 02010042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } !+ 0041423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00004200 HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } + 00000007 HLSQ_UPDATE_CONTROL: 0x7 00054d5c: 0000: c0023800 00080888 00000001 00000002 0016b07c: 0000: c0013f00 00054994 000000f6 t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:00054d6c ibsize:00000037 t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } 00054d6c: 0000: 00002200 082a0008 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00054d74: 0000: c0002600 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x1e 00054d7c: 0000: 00000ec3 0000001e t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x28 00054d84: 0000: 00000f03 00000028 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00054d8c: 0000: c0002600 00000000 t0 write HLSQ_MODE_CONTROL (0e05) HLSQ_MODE_CONTROL: 0x1 00054d94: 0000: 00000e05 00000001 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0x600a0 } 00054d9c: 0000: 000023c0 080604f0 t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x7 00054da4: 0000: 000023db 00000007 t0 write PC_RESTART_INDEX (21c6) PC_RESTART_INDEX: 0xffffffff 00054dac: 0000: 000021c6 ffffffff t0 write UNKNOWN_21E6 (21e6) UNKNOWN_21E6: 0x1 00054db4: 0000: 000021e6 00000001 t0 write UNKNOWN_21C3 (21c3) UNKNOWN_21C3: 0x1f 00054dbc: 0000: 000021c3 0000001f t0 write TPL1_TP_TEX_OFFSET (2380) TPL1_TP_TEX_OFFSET: 0x808 00054dc4: 0000: 00002380 00000808 t0 write GRAS_SU_POINT_MINMAX (2070) GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 4092.000000 } GRAS_SU_POINT_SIZE: 0.500000 00054dcc: 0000: 00012070 ffc00010 00000008 t0 write UNKNOWN_2152 (2152) UNKNOWN_2152: 0 UNKNOWN_2153: 0 00054dd8: 0000: 00012152 00000000 00000000 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00054de4: 0000: c0002600 00000000 t0 write UNKNOWN_0CC5 (0cc5) UNKNOWN_0CC5: 0x4 00054dec: 0000: 00000cc5 00000004 t0 write 0xcc4 (0cc4) 0xcc4: 00000000 00054df4: 0000: 00000cc4 00000000 t0 write 0xd03 (0d03) 0xd03: 80200000 00054dfc: 0000: 00000d03 80200000 t0 write UNKNOWN_0EC2 (0ec2) UNKNOWN_0EC2: 0x40000 00054e04: 0000: 00000ec2 00040000 t0 write VPC_DEBUG_ECO_CONTROL (0e64) VPC_DEBUG_ECO_CONTROL: 0x100 00054e0c: 0000: 00000e64 00000100 t0 write UNKNOWN_0E42 (0e42) UNKNOWN_0E42: 0 00054e14: 0000: 00000e42 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x1e 00054e1c: 0000: 00000ec3 0000001e t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x28 00054e24: 0000: 00000f03 00000028 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 00054e2c: 0000: c0014300 00040000 00000000 t0 write VFD_INDEX_OFFSET (2208) VFD_INDEX_OFFSET: 0 00054e38: 0000: 00002208 00000000 t0 write UNKNOWN_2209 (2209) UNKNOWN_2209: 0 00054e40: 0000: 00002209 00000000 0016b088: 0000: c0013f00 00054d6c 00000037 t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:00055328 ibsize:000000ac t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x3 00055328: 0000: 000023db 00000003 t0 write SP_INSTR_CACHE_CTRL (22c1) SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } 00055330: 0000: 000022c1 000005c3 t0 write HLSQ_CONTROL_1_REG (23c1) HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x1008 } 00055338: 0000: 000023c1 fcfc1108 t0 write HLSQ_CONTROL_2_REG (23c2) HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 00055340: 0000: 000023c2 fff3f3f0 t0 write HLSQ_VS_CONTROL_REG (23c5) HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 2 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 1 } 00055348: 0000: 000023c5 01010002 t0 write HLSQ_HS_CONTROL_REG (23c7) HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 00055350: 0000: 000023c7 007e0200 t0 write HLSQ_DS_CONTROL_REG (23c8) HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 00055358: 0000: 000023c8 007e0200 t0 write HLSQ_GS_CONTROL_REG (23c9) HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 00055360: 0000: 000023c9 007e0200 t0 write HLSQ_FS_CONTROL_REG (23c6) HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 2 | CONSTOBJECTOFFSET = 2 | ENABLED | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 } 00055368: 0000: 000023c6 017f0202 t0 write SP_VS_OBJ_OFFSET_REG (22e0) SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 00055370: 0000: 000022e0 00000000 t0 write SP_HS_OBJ_OFFSET_REG (230d) SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } 00055378: 0000: 0000230d 7e020000 t0 write SP_DS_OBJ_OFFSET_REG (2334) SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } 00055380: 0000: 00002334 7e020000 t0 write SP_GS_OBJ_OFFSET_REG (235b) SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } 00055388: 0000: 0000235b 7e020000 t0 write SP_FS_OBJ_OFFSET_REG (22ea) SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } 00055390: 0000: 000022ea 7e020000 t0 write SP_VS_OBJ_START (22e1) SP_VS_OBJ_START: 0x49000 00049000: 0000: 00000000 13000000 00000000 00000000 00000000 00000000 00000000 00000000 * :0:0000:0000[13000000x_00000000x] (sy)end :0:0001:0001[00000000x_00000000x] nop :0:0002:0002[00000000x_00000000x] nop :0:0003:0003[00000000x_00000000x] nop :0:0004:0004[00000000x_00000000x] nop Stats: - shaderdb: 5 instr, 4 nops, 1 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 0 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 0 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) 00055398: 0000: 000022e1 00049000 t0 write SP_HS_OBJ_START (230e) SP_HS_OBJ_START: 0 000553a0: 0000: 0000230e 00000000 t0 write SP_DS_OBJ_START (2335) SP_DS_OBJ_START: 0 000553a8: 0000: 00002335 00000000 t0 write SP_GS_OBJ_START (235c) SP_GS_OBJ_START: 0 000553b0: 0000: 0000235c 00000000 t0 write SP_VS_LENGTH_REG (22e5) SP_VS_LENGTH_REG: 1 000553b8: 0000: 000022e5 00000001 t3 opcode: CP_LOAD_STATE4 (30) (3 dwords) { DST_OFF = 0 | STATE_SRC = SS4_INDIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 1 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0x49000 } :0:0000:0000[13000000x_00000000x] (sy)end :0:0001:0001[00000000x_00000000x] nop :0:0002:0002[00000000x_00000000x] nop :0:0003:0003[00000000x_00000000x] nop :0:0004:0004[00000000x_00000000x] nop Stats: - shaderdb: 5 instr, 4 nops, 1 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 0 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 0 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) 000553c0: 0000: c0013000 00620000 00049000 t0 write 0x2072 (2072) 0x2072: 00000000 000553cc: 0000: 00002072 00000000 t0 write UNKNOWN_2155 (2155) UNKNOWN_2155: 0 000553d4: 0000: 00002155 00000000 t0 write GRAS_CNTL (2003) GRAS_CNTL: { IJ_PERSP } 000553dc: 0000: 00002003 00000001 t0 write VPC_VARYING_INTERP[0].MODE (2142) VPC_VARYING_INTERP[0].MODE: 0 000553e4: 0000: 00002142 00000000 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0x600a0 } 000553ec: 0000: 000023c0 080604f0 t0 write HLSQ_CONTROL_3_REG (23c3) HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } 000553f4: 0000: 000023c3 fcfcfc00 t0 write HLSQ_CONTROL_4_REG (23c4) HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r0.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } 000553fc: 0000: 000023c4 00fcfc00 t0 write SP_FS_CTRL_REG0 (22e8) SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE } SP_FS_CTRL_REG1: { CONSTLENGTH = 2 | VARYING | 0x80000000 } 00055404: 0000: 000122e8 00340412 80100002 t0 write SP_FS_OBJ_START (22eb) SP_FS_OBJ_START: 0x46000 00046000: 0000: 00002000 5730cb00 00000000 03000000 00000000 00000000 00000000 00000000 * :2:0000:0000[5730cb00x_00002000x] (sy)(rpt3)bary.f (ei)hr0.x, (r)0, r0.x :0:0001:0004[03000000x_00000000x] end :0:0002:0005[00000000x_00000000x] nop :0:0003:0006[00000000x_00000000x] nop :0:0004:0007[00000000x_00000000x] nop :0:0005:0008[00000000x_00000000x] nop Stats: - shaderdb: 9 instr, 4 nops, 5 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 1 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 4 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) 00055410: 0000: 000022eb 00046000 t0 write SP_FS_LENGTH_REG (22ef) SP_FS_LENGTH_REG: 1 00055418: 0000: 000022ef 00000001 t0 write RB_RENDER_COMPONENTS (20fb) RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } 00055420: 0000: 000020fb 0000000f t3 opcode: CP_LOAD_STATE4 (30) (3 dwords) { DST_OFF = 0 | STATE_SRC = SS4_INDIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 1 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0x46000 } :2:0000:0000[5730cb00x_00002000x] (sy)(rpt3)bary.f (ei)hr0.x, (r)0, r0.x :0:0001:0004[03000000x_00000000x] end :0:0002:0005[00000000x_00000000x] nop :0:0003:0006[00000000x_00000000x] nop :0:0004:0007[00000000x_00000000x] nop :0:0005:0008[00000000x_00000000x] nop Stats: - shaderdb: 9 instr, 4 nops, 5 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 1 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 4 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) 00055428: 0000: c0013000 00720000 00046000 t0 write SP_SP_CTRL_REG (22c0) SP_SP_CTRL_REG: { 0x60010 } 00055434: 0000: 000022c0 00060010 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 28 | GROUP_ID = 3 } { ADDR_LO = 0x9a950 } 0005543c: 0000: c0014300 0300001c 0009a950 t0 write RB_DEPTH_INFO (2103) RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTH4_NONE | DEPTH_BASE = 0 } RB_DEPTH_PITCH: 0 RB_DEPTH_PITCH2: 0 00055448: 0000: 00022103 00000000 00000000 00000000 t0 write GRAS_DEPTH_CONTROL (2077) GRAS_DEPTH_CONTROL: { FORMAT = DEPTH4_NONE } 00055458: 0000: 00002077 00000000 t0 write RB_STENCIL_INFO (2108) RB_STENCIL_INFO: { STENCIL_BASE = 0 } RB_STENCIL_PITCH: 0 0x210a: 00000000 00055460: 0000: 00022108 00000000 00000000 00000000 t0 write 0x2002 (2002) 0x2002: 00000000 00055470: 0000: 00002002 00000000 t0 write RB_ALPHA_CONTROL (20f8) RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } 00055478: 0000: 000020f8 00000e00 t0 write RB_MRT[0].CONTROL (20a4) RB_MRT[0].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0x7 } 00055480: 0000: 000020a4 07000c00 t0 write RB_MRT[0].BLEND_CONTROL (20a8) RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } 00055488: 0000: 000020a8 00000000 t0 write GRAS_CL_CLIP_CNTL (2000) GRAS_CL_CLIP_CNTL: { 0x80000 } 00055490: 0000: 00002000 00080000 t0 write GRAS_SU_POLY_OFFSET_SCALE (2074) GRAS_SU_POLY_OFFSET_SCALE: 0.000000 GRAS_SU_POLY_OFFSET_OFFSET: 0.000000 GRAS_SU_POLY_OFFSET_CLAMP: 0.000000 00055498: 0000: 00022074 00000000 00000000 00000000 t0 write GRAS_SU_MODE_CONTROL (2078) GRAS_SU_MODE_CONTROL: { FRONT_CW | LINEHALFWIDTH = 0.500000 | MSAA_ENABLE | RENDERING_PASS } 000554a8: 0000: 00002078 00102014 t0 write GRAS_SC_SCREEN_SCISSOR_TL (207c) GRAS_SC_SCREEN_SCISSOR_TL: { X = 2 | Y = 13 } GRAS_SC_SCREEN_SCISSOR_BR: { X = 33 | Y = 44 } 000554b0: 0000: 0001207c 000d0002 002c0021 t0 write GRAS_CL_VPORT_XOFFSET_0 (2008) GRAS_CL_VPORT_XOFFSET_0: 18.000000 GRAS_CL_VPORT_XSCALE_0: 16.000000 GRAS_CL_VPORT_YOFFSET_0: 29.000000 GRAS_CL_VPORT_YSCALE_0: 16.000000 GRAS_CL_VPORT_ZOFFSET_0: 0.500000 GRAS_CL_VPORT_ZSCALE_0: 0.500000 000554bc: 0000: 00052008 41900000 41800000 41e80000 41800000 3f000000 3f000000 t0 write GRAS_CL_GB_CLIP_ADJ (2004) GRAS_CL_GB_CLIP_ADJ: { HORZ = 511 | VERT = 511 } 000554d8: 0000: 00002004 0007fdff t0 write GRAS_SC_CONTROL (207b) GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 4 | RASTER_MODE = 0 } 000554e0: 0000: 0000207b 00000200 t0 write 0x2382 (2382) 0x2382: 00000002 000554e8: 0000: 00002382 00000002 t0 write RB_MSAA_CONTROL (20a2) RB_MSAA_CONTROL: { SAMPLES = 4 } 000554f0: 0000: 000020a2 00008000 t0 write RB_RENDER_CONTROL2 (20a3) RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 4 | IJ_PERSP_PIXEL } 000554f8: 0000: 000020a3 00001200 t0 write RB_MRT[0].BUF_INFO (20a5) RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB4_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_ALWAYS | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 1024 } RB_MRT[0].BASE: 0 RB_MRT[0].CONTROL3: { STRIDE = 64 } 00055500: 0000: 000220a5 0010029a 00000000 00000200 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 43 | GROUP_ID = 2 } { ADDR_LO = 0x9a9c0 } 00055510: 0000: c0014300 0200002b 0009a9c0 t0 write 0x215c (215c) 0x215c: 00000000 0x215d: 00000000 0005551c: 0000: 0001215c 00000000 00000000 t0 write 0x215f (215f) 0x215f: 00000000 00055528: 0000: 0000215f 00000000 t0 write 0x215e (215e) 0x215e: 00000000 00055530: 0000: 0000215e 00000000 t0 write 0x2161 (2161) 0x2161: 00000000 0x2162: 00000000 00055538: 0000: 00012161 00000000 00000000 t0 write 0x2164 (2164) 0x2164: 00000000 00055544: 0000: 00002164 00000000 t0 write 0x2163 (2163) 0x2163: 00000000 0005554c: 0000: 00002163 00000000 t0 write 0x2166 (2166) 0x2166: 00000000 0x2167: 00000000 00055554: 0000: 00012166 00000000 00000000 t0 write 0x2169 (2169) 0x2169: 00000000 00055560: 0000: 00002169 00000000 t0 write 0x2168 (2168) 0x2168: 00000000 00055568: 0000: 00002168 00000000 t0 write 0x216b (216b) 0x216b: 00000000 0x216c: 00000000 00055570: 0000: 0001216b 00000000 00000000 t0 write VPC_SO_FLUSH_WADDR_3 (216e) VPC_SO_FLUSH_WADDR_3: 0 0005557c: 0000: 0000216e 00000000 t0 write 0x216d (216d) 0x216d: 00000000 00055584: 0000: 0000216d 00000000 t0 write UNKNOWN_2156 (2156) UNKNOWN_2156: 0 0005558c: 0000: 00002156 00000000 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 18 | GROUP_ID = 1 } { ADDR_LO = 0x9aa70 } 00055594: 0000: c0014300 01000012 0009aa70 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 15 | GROUP_ID = 0 } { ADDR_LO = 0x9aac0 } 000555a0: 0000: c0014300 0000000f 0009aac0 group_id: 0 count: 15 addr: 000000000009aac0 flags: 0 0009aac0: 0000: 00002073 00000000 00002101 00000000 00002106 00000000 000021e5 00000000 0009aae0: 0020: 0001210b 00000000 00000000 00002381 00000000 000023a0 00000000 t0 write GRAS_ALPHA_CONTROL (2073) GRAS_ALPHA_CONTROL: { 0 } 0009aac0: 0000: 00002073 00000000 t0 write RB_DEPTH_CONTROL (2101) RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } 0009aac8: 0000: 00002101 00000000 t0 write RB_STENCIL_CONTROL (2106) RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } 0009aad0: 0000: 00002106 00000000 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 0009aad8: 0000: 000021e5 00000000 t0 write RB_STENCILREFMASK (210b) RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 0009aae0: 0000: 0001210b 00000000 00000000 t0 write TPL1_TP_TEX_COUNT (2381) TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } 0009aaec: 0000: 00002381 00000000 t0 write TPL1_TP_FS_TEX_COUNT (23a0) TPL1_TP_FS_TEX_COUNT: 0 0009aaf4: 0000: 000023a0 00000000 group_id: 1 count: 18 addr: 000000000009aa70 flags: 0 0009aa70: 0000: 00002200 082a0008 00002201 fcfc0081 00002203 0000fc00 0007220a 0008080f 0009aa90: 0020: 0009a8f0 00000060 00000001 0000080f 0009a920 00000030 00000001 0001228a 0009aab0: 0040: 7000411f 3000011f t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } 0009aa70: 0000: 00002200 082a0008 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } 0009aa78: 0000: 00002201 fcfc0081 t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } 0009aa80: 0000: 00002203 0000fc00 t0 write VFD_FETCH[0].INSTR_0 (220a) VFD_FETCH[0].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 | SWITCHNEXT } VFD_FETCH[0].INSTR_1: 0x9a8f0 VFD_FETCH[0].INSTR_2: { SIZE = 0x60 } VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 } VFD_FETCH[0x1].INSTR_1: 0x9a920 VFD_FETCH[0x1].INSTR_2: { SIZE = 0x30 } VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } 0009aa88: 0000: 0007220a 0008080f 0009a8f0 00000060 00000001 0000080f 0009a920 00000030 0009aaa8: 0020: 00000001 t0 write VFD_DECODE[0].INSTR (228a) VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID | SWITCHNEXT } VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID } 0009aaac: 0000: 0001228a 7000411f 3000011f group_id: 2 count: 43 addr: 000000000009a9c0 flags: 0 0009a9c0: 0000: 000020a1 00000000 000022f1 0001a100 000022f0 fc00fc01 00002100 00000001 0009a9e0: 0020: 000021e5 00000000 000020f9 ffff0501 0000214a 00000000 00002140 42001004 0009aa00: 0040: 001922c6 0010fc04 00001e00 00000000 00000000 00000000 00000000 00000000 * 0009aa40: 0080: 00000000 00000000 00fcfc00 00000008 00000000 00000000 00000000 00000000 * t0 write RB_RENDER_CONTROL (20a1) RB_RENDER_CONTROL: { 0 } 0009a9c0: 0000: 000020a1 00000000 t0 write SP_FS_MRT[0].REG (22f1) SP_FS_MRT[0].REG: { REGID = r0.x | HALF_PRECISION | MRTFORMAT = RB4_R8G8B8A8_UNORM } 0009a9c8: 0000: 000022f1 0001a100 t0 write SP_FS_OUTPUT_REG (22f0) SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 0009a9d0: 0000: 000022f0 fc00fc01 t0 write RB_FS_OUTPUT_REG (2100) RB_FS_OUTPUT_REG: { MRT = 1 } 0009a9d8: 0000: 00002100 00000001 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 0009a9e0: 0000: 000021e5 00000000 t0 write RB_FS_OUTPUT (20f9) RB_FS_OUTPUT: { ENABLE_BLEND = 0x1 | INDEPENDENT_BLEND | SAMPLE_MASK = 0xffff | 0x400 } 0009a9e8: 0000: 000020f9 ffff0501 t0 write VPC_VARYING_PS_REPL[0].MODE (214a) VPC_VARYING_PS_REPL[0].MODE: 0 0009a9f0: 0000: 0000214a 00000000 t0 write VPC_ATTR (2140) VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 } 0009a9f8: 0000: 00002140 42001004 t0 write SP_VS_PARAM_REG (22c6) SP_VS_PARAM_REG: { POSREGID = r1.x | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } SP_VS_OUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } UNKNOWN_22D7: 0xfcfc00 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 0009aa00: 0000: 001922c6 0010fc04 00001e00 00000000 00000000 00000000 00000000 00000000 * 0009aa40: 0040: 00000000 00000000 00fcfc00 00000008 00000000 00000000 00000000 00000000 * group_id: 3 count: 28 addr: 000000000009a950 flags: 0 0009a950: 0000: 000021c4 02000001 00002141 00040400 00002001 00000000 000022c4 00200800 0009a970: 0020: 000022c5 08000002 0000230c 00000000 00002318 00000000 00002319 00000000 0009a990: 0040: 00002340 00000000 00002202 fcfcfcfc 00002204 0000fcfc 00002154 00000000 0009a9b0: 0060: 000021e7 00000000 000021c5 00000012 t0 write PC_PRIM_VTX_CNTL (21c4) PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } 0009a950: 0000: 000021c4 02000001 t0 write VPC_PACK (2141) VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } 0009a958: 0000: 00002141 00040400 t0 write UNKNOWN_2001 (2001) UNKNOWN_2001: 0 0009a960: 0000: 00002001 00000000 t0 write SP_VS_CTRL_REG0 (22c4) SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 2 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 0009a968: 0000: 000022c4 00200800 t0 write SP_VS_CTRL_REG1 (22c5) SP_VS_CTRL_REG1: { CONSTLENGTH = 2 | INITIALOUTSTANDING = 8 } 0009a970: 0000: 000022c5 08000002 t0 write 0x230c (230c) 0x230c: 00000000 0009a978: 0000: 0000230c 00000000 t0 write 0x2318 (2318) 0x2318: 00000000 0009a980: 0000: 00002318 00000000 t0 write 0x2319 (2319) 0x2319: 00000000 0009a988: 0000: 00002319 00000000 t0 write 0x2340 (2340) 0x2340: 00000000 0009a990: 0000: 00002340 00000000 t0 write VFD_CONTROL_2 (2202) VFD_CONTROL_2: 0xfcfcfcfc 0009a998: 0000: 00002202 fcfcfcfc t0 write VFD_CONTROL_4 (2204) VFD_CONTROL_4: 0xfcfc 0009a9a0: 0000: 00002204 0000fcfc t0 write UNKNOWN_2154 (2154) UNKNOWN_2154: 0 0009a9a8: 0000: 00002154 00000000 t0 write PC_HS_PARAM (21e7) PC_HS_PARAM: { VERTICES_OUT = 0 | SPACING = EQUAL_SPACING } 0009a9b0: 0000: 000021e7 00000000 t0 write PC_PRIM_VTX_CNTL2 (21c5) PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 0009a9b8: 0000: 000021c5 00000012 t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = USE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x200000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 3 } draw[36] register values + 00000000 0xcc4: 00000000 + 00000004 UNKNOWN_0CC5: 0x4 + 80200000 0xd03: 80200000 !+ 00000001 HLSQ_MODE_CONTROL: 0x1 + 00000000 UNKNOWN_0E42: 0 + 00000100 VPC_DEBUG_ECO_CONTROL: 0x100 + 00040000 UNKNOWN_0EC2: 0x40000 !+ 0000001e SP_MODE_CONTROL: 0x1e !+ 00000028 TPL1_TP_MODE_CONTROL: 0x28 !+ 00080000 GRAS_CL_CLIP_CNTL: { 0x80000 } + 00000000 UNKNOWN_2001: 0 + 00000000 0x2002: 00000000 + 00000001 GRAS_CNTL: { IJ_PERSP } + 0007fdff GRAS_CL_GB_CLIP_ADJ: { HORZ = 511 | VERT = 511 } + 41900000 GRAS_CL_VPORT_XOFFSET_0: 18.000000 + 41800000 GRAS_CL_VPORT_XSCALE_0: 16.000000 + 41e80000 GRAS_CL_VPORT_YOFFSET_0: 29.000000 + 41800000 GRAS_CL_VPORT_YSCALE_0: 16.000000 + 3f000000 GRAS_CL_VPORT_ZOFFSET_0: 0.500000 + 3f000000 GRAS_CL_VPORT_ZSCALE_0: 0.500000 + ffc00010 GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 4092.000000 } + 00000008 GRAS_SU_POINT_SIZE: 0.500000 + 00000000 0x2072: 00000000 !+ 00000000 GRAS_ALPHA_CONTROL: { 0 } + 00000000 GRAS_SU_POLY_OFFSET_SCALE: 0.000000 + 00000000 GRAS_SU_POLY_OFFSET_OFFSET: 0.000000 + 00000000 GRAS_SU_POLY_OFFSET_CLAMP: 0.000000 + 00000000 GRAS_DEPTH_CONTROL: { FORMAT = DEPTH4_NONE } !+ 00102014 GRAS_SU_MODE_CONTROL: { FRONT_CW | LINEHALFWIDTH = 0.500000 | MSAA_ENABLE | RENDERING_PASS } !+ 00000200 GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 4 | RASTER_MODE = 0 } !+ 000d0002 GRAS_SC_SCREEN_SCISSOR_TL: { X = 2 | Y = 13 } !+ 002c0021 GRAS_SC_SCREEN_SCISSOR_BR: { X = 33 | Y = 44 } !+ 00000000 RB_RENDER_CONTROL: { 0 } !+ 00008000 RB_MSAA_CONTROL: { SAMPLES = 4 } !+ 00001200 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 4 | IJ_PERSP_PIXEL } !+ 07000c00 RB_MRT[0].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0x7 } !+ 0010029a RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB4_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_ALWAYS | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 1024 } !+ 00000000 RB_MRT[0].BASE: 0 !+ 00000200 RB_MRT[0].CONTROL3: { STRIDE = 64 } + 00000000 RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } + 00000e00 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } !+ ffff0501 RB_FS_OUTPUT: { ENABLE_BLEND = 0x1 | INDEPENDENT_BLEND | SAMPLE_MASK = 0xffff | 0x400 } + 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } + 00000001 RB_FS_OUTPUT_REG: { MRT = 1 } + 00000000 RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } + 00000000 RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTH4_NONE | DEPTH_BASE = 0 } + 00000000 RB_DEPTH_PITCH: 0 + 00000000 RB_DEPTH_PITCH2: 0 + 00000000 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } + 00000000 RB_STENCIL_INFO: { STENCIL_BASE = 0 } + 00000000 RB_STENCIL_PITCH: 0 + 00000000 0x210a: 00000000 + 00000000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } + 00000000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } !+ 42001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 } + 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } !+ 00000000 VPC_VARYING_INTERP[0].MODE: 0 !+ 00000000 VPC_VARYING_PS_REPL[0].MODE: 0 + 00000000 UNKNOWN_2152: 0 + 00000000 UNKNOWN_2153: 0 + 00000000 UNKNOWN_2154: 0 + 00000000 UNKNOWN_2155: 0 + 00000000 UNKNOWN_2156: 0 + 00000000 0x215c: 00000000 + 00000000 0x215d: 00000000 + 00000000 0x215e: 00000000 + 00000000 0x215f: 00000000 + 00000000 0x2161: 00000000 + 00000000 0x2162: 00000000 + 00000000 0x2163: 00000000 + 00000000 0x2164: 00000000 + 00000000 0x2166: 00000000 + 00000000 0x2167: 00000000 + 00000000 0x2168: 00000000 + 00000000 0x2169: 00000000 + 00000000 0x216b: 00000000 + 00000000 0x216c: 00000000 + 00000000 0x216d: 00000000 + 00000000 VPC_SO_FLUSH_WADDR_3: 0 !+ 0000001f UNKNOWN_21C3: 0x1f !+ 02000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + ffffffff PC_RESTART_INDEX: 0xffffffff + 00000000 PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } + 00000001 UNKNOWN_21E6: 0x1 + 00000000 PC_HS_PARAM: { VERTICES_OUT = 0 | SPACING = EQUAL_SPACING } !+ 082a0008 VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } !+ fcfc0081 VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } + fcfcfcfc VFD_CONTROL_2: 0xfcfcfcfc !+ 0000fc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } + 0000fcfc VFD_CONTROL_4: 0xfcfc + 00000000 VFD_INDEX_OFFSET: 0 + 00000000 UNKNOWN_2209: 0 + 0008080f VFD_FETCH[0].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 | SWITCHNEXT } !+ 0009a8f0 VFD_FETCH[0].INSTR_1: 0x9a8f0 + 00000060 VFD_FETCH[0].INSTR_2: { SIZE = 0x60 } + 00000001 VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } + 0000080f VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 } !+ 0009a920 VFD_FETCH[0x1].INSTR_1: 0x9a920 + 00000030 VFD_FETCH[0x1].INSTR_2: { SIZE = 0x30 } + 00000001 VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } + 7000411f VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID | SWITCHNEXT } + 3000011f VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID } + 00060010 SP_SP_CTRL_REG: { 0x60010 } + 000005c3 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } !+ 00200800 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 2 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } !+ 08000002 SP_VS_CTRL_REG1: { CONSTLENGTH = 2 | INITIALOUTSTANDING = 8 } !+ 0010fc04 SP_VS_PARAM_REG: { POSREGID = r1.x | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } !+ 00001e00 SP_VS_OUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00fcfc00 UNKNOWN_22D7: 0xfcfc00 + 00000008 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } !+ 00049000 SP_VS_OBJ_START: 0x49000 00049000: 0000: 00000000 13000000 00000000 00000000 00000000 00000000 00000000 00000000 * :0:0000:0000[13000000x_00000000x] (sy)end :0:0001:0001[00000000x_00000000x] nop :0:0002:0002[00000000x_00000000x] nop :0:0003:0003[00000000x_00000000x] nop :0:0004:0004[00000000x_00000000x] nop Stats: - shaderdb: 5 instr, 4 nops, 1 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 0 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 0 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) !+ 00000001 SP_VS_LENGTH_REG: 1 !+ 00340412 SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE } !+ 80100002 SP_FS_CTRL_REG1: { CONSTLENGTH = 2 | VARYING | 0x80000000 } !+ 7e020000 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } !+ 00046000 SP_FS_OBJ_START: 0x46000 00046000: 0000: 00002000 5730cb00 00000000 03000000 00000000 00000000 00000000 00000000 * :2:0000:0000[5730cb00x_00002000x] (sy)(rpt3)bary.f (ei)hr0.x, (r)0, r0.x :0:0001:0004[03000000x_00000000x] end :0:0002:0005[00000000x_00000000x] nop :0:0003:0006[00000000x_00000000x] nop :0:0004:0007[00000000x_00000000x] nop :0:0005:0008[00000000x_00000000x] nop Stats: - shaderdb: 9 instr, 4 nops, 5 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 1 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 4 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) + 00000001 SP_FS_LENGTH_REG: 1 !+ fc00fc01 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r63.x } !+ 0001a100 SP_FS_MRT[0].REG: { REGID = r0.x | HALF_PRECISION | MRTFORMAT = RB4_R8G8B8A8_UNORM } + 00000000 0x230c: 00000000 + 7e020000 SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } + 00000000 SP_HS_OBJ_START: 0 + 00000000 0x2318: 00000000 + 00000000 0x2319: 00000000 + 7e020000 SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } + 00000000 SP_DS_OBJ_START: 0 + 00000000 0x2340: 00000000 + 7e020000 SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } + 00000000 SP_GS_OBJ_START: 0 + 00000808 TPL1_TP_TEX_OFFSET: 0x808 + 00000000 TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } !+ 00000002 0x2382: 00000002 !+ 00000000 TPL1_TP_FS_TEX_COUNT: 0 !+ 080604f0 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0x600a0 } !+ fcfc1108 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x1008 } !+ fff3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } + fcfcfc00 HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } !+ 00fcfc00 HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r0.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } !+ 01010002 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 2 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 1 } !+ 017f0202 HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 2 | CONSTOBJECTOFFSET = 2 | ENABLED | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 } !+ 007e0200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } !+ 007e0200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } !+ 007e0200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } !+ 00000003 HLSQ_UPDATE_CONTROL: 0x3 000555ac: 0000: c0023800 00200984 00000001 00000003 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 18 | GROUP_ID = 1 } { ADDR_LO = 0x9ac30 } 000555bc: 0000: c0014300 01000012 0009ac30 group_id: 1 count: 18 addr: 000000000009ac30 flags: 0 0009ac30: 0000: 00002200 082a0008 00002201 fcfc0081 00002203 0000fc00 0007220a 0008080f 0009ac50: 0020: 0009abd0 00000060 00000001 0000080f 0009ac00 00000030 00000001 0001228a 0009ac70: 0040: 7000411f 3000011f t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } 0009ac30: 0000: 00002200 082a0008 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } 0009ac38: 0000: 00002201 fcfc0081 t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } 0009ac40: 0000: 00002203 0000fc00 t0 write VFD_FETCH[0].INSTR_0 (220a) VFD_FETCH[0].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 | SWITCHNEXT } VFD_FETCH[0].INSTR_1: 0x9abd0 VFD_FETCH[0].INSTR_2: { SIZE = 0x60 } VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 } VFD_FETCH[0x1].INSTR_1: 0x9ac00 VFD_FETCH[0x1].INSTR_2: { SIZE = 0x30 } VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } 0009ac48: 0000: 0007220a 0008080f 0009abd0 00000060 00000001 0000080f 0009ac00 00000030 0009ac68: 0020: 00000001 t0 write VFD_DECODE[0].INSTR (228a) VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID | SWITCHNEXT } VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID } 0009ac6c: 0000: 0001228a 7000411f 3000011f t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = USE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x200000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 3 } draw[37] register values + 082a0008 VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } + fcfc0081 VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } + 0000fc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } + 0008080f VFD_FETCH[0].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 | SWITCHNEXT } !+ 0009abd0 VFD_FETCH[0].INSTR_1: 0x9abd0 + 00000060 VFD_FETCH[0].INSTR_2: { SIZE = 0x60 } + 00000001 VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } + 0000080f VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 } !+ 0009ac00 VFD_FETCH[0x1].INSTR_1: 0x9ac00 + 00000030 VFD_FETCH[0x1].INSTR_2: { SIZE = 0x30 } + 00000001 VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } + 7000411f VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID | SWITCHNEXT } + 3000011f VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID } 000555c8: 0000: c0023800 00200984 00000001 00000003 0016b094: 0000: c0013f00 00055328 000000ac t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 0016b0a0: 0000: c0014300 00040000 00000000 t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:00171b04 ibsize:000000f7 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00171b04: 0000: c0002600 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x4 00171b0c: 0000: 00000ec3 00000004 t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x68 00171b14: 0000: 00000f03 00000068 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00171b1c: 0000: c0002600 00000000 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } 00171b24: 0000: 000023c0 080004f0 t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = 0x1d } event (null) 00171b2c: 0000: c0004600 0000001d t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = FACENESS_FLUSH } event FACENESS_FLUSH 00171b34: 0000: c0004600 0000001c t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00171b3c: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0 00171b44: 0000: 00000cc6 00000000 t0 write UNKNOWN_0E42 (0e42) UNKNOWN_0E42: 0 00171b4c: 0000: 00000e42 00000000 t0 write HLSQ_MODE_CONTROL (0e05) HLSQ_MODE_CONTROL: 0x2 00171b54: 0000: 00000e05 00000002 t0 write UNKNOWN_0CC5 (0cc5) UNKNOWN_0CC5: 0x4 00171b5c: 0000: 00000cc5 00000004 t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x7 00171b64: 0000: 000023db 00000007 t0 write VFD_CONTROL_2 (2202) VFD_CONTROL_2: 0xfcfcfcfc 00171b6c: 0000: 00002202 fcfcfcfc t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } 00171b74: 0000: 00002203 fcfcfc00 t0 write VFD_CONTROL_4 (2204) VFD_CONTROL_4: 0xfcfc 00171b7c: 0000: 00002204 0000fcfc t0 write VFD_INDEX_OFFSET (2208) VFD_INDEX_OFFSET: 0 00171b84: 0000: 00002208 00000000 t0 write UNKNOWN_2209 (2209) UNKNOWN_2209: 0 00171b8c: 0000: 00002209 00000000 t0 write UNKNOWN_2152 (2152) UNKNOWN_2152: 0 UNKNOWN_2153: 0 00171b94: 0000: 00012152 00000000 00000000 t0 write UNKNOWN_2156 (2156) UNKNOWN_2156: 0 00171ba0: 0000: 00002156 00000000 t0 write UNKNOWN_2154 (2154) UNKNOWN_2154: 0 00171ba8: 0000: 00002154 00000000 t0 write UNKNOWN_2155 (2155) UNKNOWN_2155: 0 00171bb0: 0000: 00002155 00000000 t0 write UNKNOWN_21C3 (21c3) UNKNOWN_21C3: 0x1d 00171bb8: 0000: 000021c3 0000001d t0 write PC_PRIM_VTX_CNTL2 (21c5) PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 00171bc0: 0000: 000021c5 00000012 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 00171bc8: 0000: 000021e5 00000000 t0 write GRAS_SU_MODE_CONTROL (2078) GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } 00171bd0: 0000: 00002078 00000000 t0 write UNKNOWN_2001 (2001) UNKNOWN_2001: 0 00171bd8: 0000: 00002001 00000000 t0 write GRAS_CNTL (2003) GRAS_CNTL: { IJ_PERSP } 00171be0: 0000: 00002003 00000001 t0 write GRAS_CL_CLIP_CNTL (2000) GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } 00171be8: 0000: 00002000 00188000 t0 write TPL1_TP_TEX_COUNT (2381) TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } 00171bf0: 0000: 00002381 00000000 t0 write TPL1_TP_FS_TEX_COUNT (23a0) TPL1_TP_FS_TEX_COUNT: 0x3 00171bf8: 0000: 000023a0 00000003 t0 write RB_ALPHA_CONTROL (20f8) RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } 00171c00: 0000: 000020f8 00000e00 t0 write RB_RENDER_COMPONENTS (20fb) RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } 00171c08: 0000: 000020fb 0000000f t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 00171c10: 0000: c0014300 00040000 00000000 t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } 00171c1c: 0000: 00002200 000a0000 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } 00171c24: 0000: 00002201 fc030000 t0 write SP_INSTR_CACHE_CTRL (22c1) SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } 00171c2c: 0000: 000022c1 000005c3 t0 write HLSQ_CONTROL_1_REG (23c1) HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } 00171c34: 0000: 000023c1 fcfc0120 t0 write HLSQ_CONTROL_2_REG (23c2) HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 00171c3c: 0000: 000023c2 27f3f3f0 t0 write HLSQ_VS_CONTROL_REG (23c5) HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } 00171c44: 0000: 000023c5 02010042 t0 write HLSQ_FS_CONTROL_REG (23c6) HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00171c4c: 0000: 000023c6 0041423e t0 write HLSQ_HS_CONTROL_REG (23c7) HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00171c54: 0000: 000023c7 00404200 t0 write HLSQ_DS_CONTROL_REG (23c8) HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00171c5c: 0000: 000023c8 00404200 t0 write HLSQ_GS_CONTROL_REG (23c9) HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00171c64: 0000: 000023c9 00404200 t0 write HLSQ_CS_CONTROL_REG (23ca) HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } 00171c6c: 0000: 000023ca 00004200 t0 write SP_SP_CTRL_REG (22c0) SP_SP_CTRL_REG: { 0x60010 } 00171c74: 0000: 000022c0 00060010 t0 write UNKNOWN_21E6 (21e6) UNKNOWN_21E6: 0x1 00171c7c: 0000: 000021e6 00000001 t0 write SP_VS_CTRL_REG0 (22c4) SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 00171c84: 0000: 000022c4 00200c10 t0 write SP_VS_CTRL_REG1 (22c5) SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } 00171c8c: 0000: 000022c5 01000042 t0 write VPC_ATTR (2140) VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | 0x40000000 } 00171c94: 0000: 00002140 40001004 t0 write VPC_PACK (2141) VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } 00171c9c: 0000: 00002141 00040400 t0 write PC_PRIM_VTX_CNTL (21c4) PC_PRIM_VTX_CNTL: { VAROUT = 1 } 00171ca4: 0000: 000021c4 00000001 t0 write SP_VS_PARAM_REG (22c6) SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } UNKNOWN_22D7: 0xfcfc00 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 00171cac: 0000: 001922c6 0010fc03 00001e03 00000000 00000000 00000000 00000000 00000000 * 00171cec: 0040: 00000000 00000000 00fcfc00 00000008 00000000 00000000 00000000 00000000 * t0 write SP_VS_OBJ_OFFSET_REG (22e0) SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 00171d18: 0000: 000022e0 00000000 t0 write SP_VS_OBJ_START (22e1) SP_VS_OBJ_START: 0x1 00171d20: 0000: 000022e1 00000001 t0 write SP_VS_LENGTH_REG (22e5) SP_VS_LENGTH_REG: 2 00171d28: 0000: 000022e5 00000002 t3 opcode: CP_LOAD_STATE4 (30) (67 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } :2:0000:0000[56d81803x_20020003x] (sy)(ss)(nop3) shl.b r0.w, r0.w, 2 :1:0001:0004[20150000x_00000003x] cov.s32s16 hr0.x, r0.w :0:0002:0005[00000200x_00000000x] (rpt2)nop :1:0003:0008[201100f4x_00000000x] mova a0.x, hr0.x :0:0004:0009[00000500x_00000000x] (rpt5)nop :1:0005:0015[20154003x_00000c20x] mov.s32s32 r0.w, c :1:0006:0016[20154004x_00000c21x] mov.s32s32 r1.x, c :1:0007:0017[20154005x_00000c22x] mov.s32s32 r1.y, c :1:0008:0018[20156006x_00000c23x] (ul)mov.s32s32 r1.z, c :0:0009:0019[03000000x_00000000x] end :2:0010:0020[46f00007x_20050000x] shr.b r1.w, r0.x, 5 :2:0011:0021[43980008x_201f0000x] (nop2) and.b r2.x, r0.x, 31 :2:0012:0024[43980807x_201f0007x] (nop3) and.b r1.w, r1.w, 31 :2:0013:0028[46100807x_20100007x] (nop1) mul.u24 r1.w, r1.w, 16 :3:0014:0030[62040007x_00071014x] mad.u24 r1.w, c5.x, r2.x, r1.w :0:0015:0031[00000500x_00000000x] (rpt5)nop :6:0016:0037[c2c60f00x_04800006x] stlw.u32 l[r1.w], r0.w, 4 :0:0017:0038[04800000x_00000000x] chmask :0:0018:0039[05000000x_00000000x] chsh Stats: - shaderdb: 40 instr, 24 nops, 16 non-nops, 5 mov, 1 cov - shaderdb: 0 last-baryf, 0 half, 2 full, 5 constlen - shaderdb: 27 cat0, 6 cat1, 5 cat2, 1 cat3, 0 cat4, 0 cat5, 1 cat6, 0 cat7 - shaderdb: 0 sstall, 1 (ss), 1 (sy) 00171d30: 0000: c0413000 00a00000 00000000 20020003 56d81803 00000003 20150000 00000000 00171d50: 0020: 00000200 00000000 201100f4 00000000 00000500 00000c20 20154003 00000c21 00171d70: 0040: 20154004 00000c22 20154005 00000c23 20156006 00000000 03000000 20050000 00171d90: 0060: 46f00007 201f0000 43980008 201f0007 43980807 20100007 46100807 00071014 00171db0: 0080: 62040007 00000000 00000500 04800006 c2c60f00 00000000 04800000 00000000 00171dd0: 00a0: 05000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 * t0 write GRAS_SC_CONTROL (207b) GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = 0 | MSAA_DISABLE | RASTER_MODE = 0 } 00171e3c: 0000: 0000207b 00000808 t0 write RB_MSAA_CONTROL (20a2) RB_MSAA_CONTROL: { DISABLE | SAMPLES = 0 } 00171e44: 0000: 000020a2 00001000 t0 write RB_RENDER_CONTROL (20a1) RB_RENDER_CONTROL: { DISABLE_COLOR_PIPE | 0x2 } 00171e4c: 0000: 000020a1 00000022 t0 write RB_DEPTH_CONTROL (2101) RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } 00171e54: 0000: 00002101 00000000 t0 write GRAS_ALPHA_CONTROL (2073) GRAS_ALPHA_CONTROL: { 0x2 } 00171e5c: 0000: 00002073 00000002 t0 write RB_STENCIL_CONTROL (2106) RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } 00171e64: 0000: 00002106 00000000 t0 write RB_COPY_CONTROL (20fc) RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_FOUR | MODE = RB_COPY_DEPTH_STENCIL | FASTCLEAR = 0 | GMEM_BASE = 0 } RB_COPY_DEST_BASE: { BASE = 0x4f000 } RB_COPY_DEST_PITCH: { PITCH = 256 } RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_DISABLE | COMPONENT_ENABLE = 0xf | ENDIAN = ENDIAN_NONE | TILE = TILE4_3 } 00171e6c: 0000: 000320fc 00000052 0004f000 00000008 0303c068 t0 write UNKNOWN_20EF (20ef) UNKNOWN_20EF: 0 00171e80: 0000: 000020ef 00000000 t0 write GRAS_SC_SCREEN_SCISSOR_TL (207c) GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } 00171e88: 0000: 0001207c 00000000 003f003f t0 write RB_FRAME_BUFFER_DIMENSION (0ce0) RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } 00171e94: 0000: 00000ce0 00400040 t0 write 0xce1 (0ce1) 0xce1: 00000000 00171e9c: 0000: 00000ce1 00000000 t3 opcode: CP_LOAD_STATE4 (30) (11 dwords) { DST_OFF = 8 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } 00171eb0: 0.000000 0.000000 1.000000 1.000000 64.000000 64.000000 1.000000 1.000000 00171eb0: 0000: 00000000 00000000 3f800000 3f800000 42800000 42800000 3f800000 3f800000 00171ea4: 0000: c0093000 00a00008 00000001 00000000 00000000 3f800000 3f800000 42800000 00171ec4: 0020: 42800000 3f800000 3f800000 t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x80000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 2 } draw[38] register values + 00000004 UNKNOWN_0CC5: 0x4 + 00000000 UNKNOWN_0CC6: 0 + 00400040 RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } + 00000000 0xce1: 00000000 !+ 00000002 HLSQ_MODE_CONTROL: 0x2 + 00000000 UNKNOWN_0E42: 0 !+ 00000004 SP_MODE_CONTROL: 0x4 !+ 00000068 TPL1_TP_MODE_CONTROL: 0x68 !+ 00188000 GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } + 00000000 UNKNOWN_2001: 0 + 00000001 GRAS_CNTL: { IJ_PERSP } !+ 00000002 GRAS_ALPHA_CONTROL: { 0x2 } !+ 00000000 GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } !+ 00000808 GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = 0 | MSAA_DISABLE | RASTER_MODE = 0 } !+ 00000000 GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } !+ 003f003f GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } !+ 00000022 RB_RENDER_CONTROL: { DISABLE_COLOR_PIPE | 0x2 } !+ 00001000 RB_MSAA_CONTROL: { DISABLE | SAMPLES = 0 } + 00000000 UNKNOWN_20EF: 0 + 00000e00 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } + 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } !+ 00000052 RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_FOUR | MODE = RB_COPY_DEPTH_STENCIL | FASTCLEAR = 0 | GMEM_BASE = 0 } + 0004f000 RB_COPY_DEST_BASE: { BASE = 0x4f000 } + 00000008 RB_COPY_DEST_PITCH: { PITCH = 256 } !+ 0303c068 RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_DISABLE | COMPONENT_ENABLE = 0xf | ENDIAN = ENDIAN_NONE | TILE = TILE4_3 } + 00000000 RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } + 00000000 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } !+ 40001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | 0x40000000 } + 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } + 00000000 UNKNOWN_2152: 0 + 00000000 UNKNOWN_2153: 0 + 00000000 UNKNOWN_2154: 0 + 00000000 UNKNOWN_2155: 0 + 00000000 UNKNOWN_2156: 0 !+ 0000001d UNKNOWN_21C3: 0x1d !+ 00000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 } + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + 00000000 PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } + 00000001 UNKNOWN_21E6: 0x1 !+ 000a0000 VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } !+ fc030000 VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } + fcfcfcfc VFD_CONTROL_2: 0xfcfcfcfc !+ fcfcfc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } + 0000fcfc VFD_CONTROL_4: 0xfcfc + 00000000 VFD_INDEX_OFFSET: 0 + 00000000 UNKNOWN_2209: 0 + 00060010 SP_SP_CTRL_REG: { 0x60010 } + 000005c3 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } !+ 00200c10 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } !+ 01000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } !+ 0010fc03 SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } !+ 00001e03 SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00fcfc00 UNKNOWN_22D7: 0xfcfc00 + 00000008 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } !+ 00000001 SP_VS_OBJ_START: 0x1 !+ 00000002 SP_VS_LENGTH_REG: 2 + 00000000 TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } !+ 00000003 TPL1_TP_FS_TEX_COUNT: 0x3 !+ 080004f0 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } !+ fcfc0120 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } !+ 27f3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } !+ 02010042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } !+ 0041423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } !+ 00404200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } !+ 00404200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } !+ 00404200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00004200 HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } !+ 00000007 HLSQ_UPDATE_CONTROL: 0x7 00171ed0: 0000: c0023800 00080888 00000001 00000002 0016b0ac: 0000: c0013f00 00171b04 000000f7 t3 opcode: (null) (1d) (2 dwords) 0016b0b8: 0000: c0001d00 00000000 ############################################################ vertices: 0 ############################################################ cmdstream: 8 dwords t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:000555d8 ibsize:00000155 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 000555d8: 0000: c0002600 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x4 000555e0: 0000: 00000ec3 00000004 t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x68 000555e8: 0000: 00000f03 00000068 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 000555f0: 0000: c0002600 00000000 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } 000555f8: 0000: 000023c0 080004f0 t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = 0x1d } event (null) 00055600: 0000: c0004600 0000001d t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = FACENESS_FLUSH } event FACENESS_FLUSH 00055608: 0000: c0004600 0000001c t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00055610: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0 00055618: 0000: 00000cc6 00000000 t0 write UNKNOWN_0E42 (0e42) UNKNOWN_0E42: 0 00055620: 0000: 00000e42 00000000 t0 write HLSQ_MODE_CONTROL (0e05) HLSQ_MODE_CONTROL: 0x2 00055628: 0000: 00000e05 00000002 t0 write UNKNOWN_0CC5 (0cc5) UNKNOWN_0CC5: 0x4 00055630: 0000: 00000cc5 00000004 t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x7 00055638: 0000: 000023db 00000007 t0 write VFD_CONTROL_2 (2202) VFD_CONTROL_2: 0xfcfcfcfc 00055640: 0000: 00002202 fcfcfcfc t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } 00055648: 0000: 00002203 fcfcfc00 t0 write VFD_CONTROL_4 (2204) VFD_CONTROL_4: 0xfcfc 00055650: 0000: 00002204 0000fcfc t0 write VFD_INDEX_OFFSET (2208) VFD_INDEX_OFFSET: 0 00055658: 0000: 00002208 00000000 t0 write UNKNOWN_2209 (2209) UNKNOWN_2209: 0 00055660: 0000: 00002209 00000000 t0 write UNKNOWN_2152 (2152) UNKNOWN_2152: 0 UNKNOWN_2153: 0 00055668: 0000: 00012152 00000000 00000000 t0 write UNKNOWN_2156 (2156) UNKNOWN_2156: 0 00055674: 0000: 00002156 00000000 t0 write UNKNOWN_2154 (2154) UNKNOWN_2154: 0 0005567c: 0000: 00002154 00000000 t0 write UNKNOWN_2155 (2155) UNKNOWN_2155: 0 00055684: 0000: 00002155 00000000 t0 write UNKNOWN_21C3 (21c3) UNKNOWN_21C3: 0x1d 0005568c: 0000: 000021c3 0000001d t0 write PC_PRIM_VTX_CNTL2 (21c5) PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 00055694: 0000: 000021c5 00000012 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 0005569c: 0000: 000021e5 00000000 t0 write GRAS_SU_MODE_CONTROL (2078) GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } 000556a4: 0000: 00002078 00000000 t0 write UNKNOWN_2001 (2001) UNKNOWN_2001: 0 000556ac: 0000: 00002001 00000000 t0 write GRAS_CNTL (2003) GRAS_CNTL: { IJ_PERSP } 000556b4: 0000: 00002003 00000001 t0 write GRAS_CL_CLIP_CNTL (2000) GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } 000556bc: 0000: 00002000 00188000 t0 write TPL1_TP_TEX_COUNT (2381) TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } 000556c4: 0000: 00002381 00000000 t0 write TPL1_TP_FS_TEX_COUNT (23a0) TPL1_TP_FS_TEX_COUNT: 0x3 000556cc: 0000: 000023a0 00000003 t0 write RB_ALPHA_CONTROL (20f8) RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } 000556d4: 0000: 000020f8 00000e00 t0 write RB_RENDER_COMPONENTS (20fb) RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } 000556dc: 0000: 000020fb 0000000f t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 000556e4: 0000: c0014300 00040000 00000000 t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } 000556f0: 0000: 00002200 000a0000 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } 000556f8: 0000: 00002201 fc030000 t0 write SP_INSTR_CACHE_CTRL (22c1) SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } 00055700: 0000: 000022c1 000005c3 t0 write HLSQ_CONTROL_1_REG (23c1) HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } 00055708: 0000: 000023c1 fcfc0120 t0 write HLSQ_CONTROL_2_REG (23c2) HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 00055710: 0000: 000023c2 27f3f3f0 t0 write HLSQ_VS_CONTROL_REG (23c5) HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } 00055718: 0000: 000023c5 02010042 t0 write HLSQ_FS_CONTROL_REG (23c6) HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 1 } 00055720: 0000: 000023c6 0141423e t0 write HLSQ_HS_CONTROL_REG (23c7) HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00055728: 0000: 000023c7 00404200 t0 write HLSQ_DS_CONTROL_REG (23c8) HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00055730: 0000: 000023c8 00404200 t0 write HLSQ_GS_CONTROL_REG (23c9) HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00055738: 0000: 000023c9 00404200 t0 write HLSQ_CS_CONTROL_REG (23ca) HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } 00055740: 0000: 000023ca 00004200 t0 write SP_SP_CTRL_REG (22c0) SP_SP_CTRL_REG: { 0x60010 } 00055748: 0000: 000022c0 00060010 t0 write UNKNOWN_21E6 (21e6) UNKNOWN_21E6: 0x1 00055750: 0000: 000021e6 00000001 t0 write SP_VS_CTRL_REG0 (22c4) SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 00055758: 0000: 000022c4 00200c10 t0 write SP_VS_CTRL_REG1 (22c5) SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } 00055760: 0000: 000022c5 01000042 t0 write VPC_ATTR (2140) VPC_ATTR: { TOTALATTR = 8 | THRDASSIGN = 1 | ENABLE | 0x40000000 } 00055768: 0000: 00002140 42001008 t0 write VPC_PACK (2141) VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 8 | NUMNONPOSVSVAR = 6 } 00055770: 0000: 00002141 00060800 t0 write PC_PRIM_VTX_CNTL (21c4) PC_PRIM_VTX_CNTL: { VAROUT = 1 } 00055778: 0000: 000021c4 00000001 t0 write SP_VS_PARAM_REG (22c6) SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 2 } SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r1.w | B_COMPMASK = 0x3 } SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } UNKNOWN_22D7: 0xfcfc00 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 12 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 00055780: 0000: 001922c6 0020fc03 06071e03 00000000 00000000 00000000 00000000 00000000 * 000557c0: 0040: 00000000 00000000 00fcfc00 00000c08 00000000 00000000 00000000 00000000 * t0 write SP_VS_OBJ_OFFSET_REG (22e0) SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 000557ec: 0000: 000022e0 00000000 t0 write SP_VS_OBJ_START (22e1) SP_VS_OBJ_START: 0x1 000557f4: 0000: 000022e1 00000001 t0 write SP_VS_LENGTH_REG (22e5) SP_VS_LENGTH_REG: 2 000557fc: 0000: 000022e5 00000002 t3 opcode: CP_LOAD_STATE4 (30) (67 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } :2:0000:0000[56d81803x_20020003x] (sy)(ss)(nop3) shl.b r0.w, r0.w, 2 :1:0001:0004[20150000x_00000003x] cov.s32s16 hr0.x, r0.w :0:0002:0005[00000200x_00000000x] (rpt2)nop :1:0003:0008[201100f4x_00000000x] mova a0.x, hr0.x :0:0004:0009[00000500x_00000000x] (rpt5)nop :1:0005:0015[20154003x_00000c20x] mov.s32s32 r0.w, c :1:0006:0016[20154004x_00000c21x] mov.s32s32 r1.x, c :1:0007:0017[20154007x_00000c22x] mov.s32s32 r1.w, c :1:0008:0018[20156008x_00000c23x] (ul)mov.s32s32 r2.x, c :1:0009:0019[20554005x_00000000x] mov.s32s32 r1.y, 0 :1:0010:0020[20554006x_3f800000x] mov.s32s32 r1.z, 1065353216 :0:0011:0021[03000000x_00000000x] end :2:0012:0022[46f00009x_20050000x] shr.b r2.y, r0.x, 5 :2:0013:0023[4398000ax_201f0000x] (nop2) and.b r2.z, r0.x, 31 :2:0014:0026[43980809x_201f0009x] (nop3) and.b r2.y, r2.y, 31 :2:0015:0030[46100809x_20180009x] (nop1) mul.u24 r2.y, r2.y, 24 :3:0016:0032[62050009x_00091014x] mad.u24 r2.y, c5.x, r2.z, r2.y :0:0017:0033[00000500x_00000000x] (rpt5)nop :6:0018:0039[c2c61300x_04800006x] stlw.u32 l[r2.y], r0.w, 4 :6:0019:0040[c2c61310x_0280000ex] stlw.u32 l[r2.y+16], r1.w, 2 :0:0020:0041[04800000x_00000000x] chmask :0:0021:0042[05000000x_00000000x] chsh Stats: - shaderdb: 43 instr, 24 nops, 19 non-nops, 7 mov, 1 cov - shaderdb: 0 last-baryf, 0 half, 3 full, 5 constlen - shaderdb: 27 cat0, 8 cat1, 5 cat2, 1 cat3, 0 cat4, 0 cat5, 2 cat6, 0 cat7 - shaderdb: 0 sstall, 1 (ss), 1 (sy) 00055804: 0000: c0413000 00a00000 00000000 20020003 56d81803 00000003 20150000 00000000 00055824: 0020: 00000200 00000000 201100f4 00000000 00000500 00000c20 20154003 00000c21 00055844: 0040: 20154004 00000c22 20154007 00000c23 20156008 00000000 20554005 3f800000 00055864: 0060: 20554006 00000000 03000000 20050000 46f00009 201f0000 4398000a 201f0009 00055884: 0080: 43980809 20180009 46100809 00091014 62050009 00000000 00000500 04800006 000558a4: 00a0: c2c61300 0280000e c2c61310 00000000 04800000 00000000 05000000 00000000 * t0 write HLSQ_CONTROL_3_REG (23c3) HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } 00055910: 0000: 000023c3 fcfcfc00 t0 write HLSQ_CONTROL_4_REG (23c4) HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } 00055918: 0000: 000023c4 00fcfcfc t0 write SP_FS_CTRL_REG0 (22e8) SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 0 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE | PIXLODENABLE } SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 } 00055920: 0000: 000122e8 00700402 8010003e t0 write SP_FS_OBJ_OFFSET_REG (22ea) SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 } 0005592c: 0000: 000022ea 40420000 t0 write SP_FS_OBJ_START (22eb) SP_FS_OBJ_START: 0x1 00055934: 0000: 000022eb 00000001 t0 write SP_FS_LENGTH_REG (22ef) SP_FS_LENGTH_REG: 1 0005593c: 0000: 000022ef 00000001 t0 write SP_FS_OUTPUT_REG (22f0) SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r0.x | SAMPLEMASK_REGID = r0.x } 00055944: 0000: 000022f0 00000001 t0 write VPC_VARYING_INTERP[0].MODE (2142) VPC_VARYING_INTERP[0].MODE: 0xe000 0005594c: 0000: 00002142 0000e000 t0 write RB_FS_OUTPUT_REG (2100) RB_FS_OUTPUT_REG: { MRT = 1 } 00055954: 0000: 00002100 00000001 t3 opcode: CP_LOAD_STATE4 (30) (35 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 1 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } :2:0000:0000[57309902x_00002004x] (sy)(ss)(rpt1)bary.f (ei)r0.z, (r)4, r0.x :0:0001:0002[00000500x_00000000x] (rpt5)nop :5:0002:0008[a0c01f00x_00000005x] sam (f32)(xyzw)r0.x, r0.z, s#0, t#0 :0:0003:0009[03000000x_00000000x] end :0:0004:0010[00000000x_00000000x] nop :0:0005:0011[00000000x_00000000x] nop :0:0006:0012[00000000x_00000000x] nop :0:0007:0013[00000000x_00000000x] nop Stats: - shaderdb: 14 instr, 10 nops, 4 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 0 half, 1 full, 0 constlen - shaderdb: 11 cat0, 0 cat1, 2 cat2, 0 cat3, 0 cat4, 1 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 1 (ss), 1 (sy) 0005595c: 0000: c0213000 00700000 00000000 00002004 57309902 00000000 00000500 00000005 0005597c: 0020: a0c01f00 00000000 03000000 00000000 00000000 00000000 00000000 00000000 * t0 write RB_FS_OUTPUT (20f9) RB_FS_OUTPUT: { ENABLE_BLEND = 0 | SAMPLE_MASK = 0xffff } 000559e8: 0000: 000020f9 ffff0000 t0 write RB_MRT[0].CONTROL (20a4) RB_MRT[0].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0xf } 000559f0: 0000: 000020a4 0f000000 t0 write RB_MRT[0x1].CONTROL (20a9) RB_MRT[0x1].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0xf } 000559f8: 0000: 000020a9 0f000000 t0 write RB_MRT[0].BLEND_CONTROL (20a8) RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } 00055a00: 0000: 000020a8 00000000 t3 opcode: CP_LOAD_STATE4 (30) (5 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_TEX | NUM_UNIT = 1 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } { XY_MAG = A4XX_TEX_NEAREST | XY_MIN = A4XX_TEX_NEAREST | WRAP_S = A4XX_TEX_CLAMP_TO_EDGE | WRAP_T = A4XX_TEX_CLAMP_TO_EDGE | WRAP_R = A4XX_TEX_CLAMP_TO_EDGE | ANISO = A4XX_TEX_ANISO_1 | LOD_BIAS = 0.000000 | 0x60000 } { COMPARE_FUNC = FUNC_LEQUAL | UNNORM_COORDS | MIPFILTER_LINEAR_FAR | MAX_LOD = 0.000000 | MIN_LOD = 0.000000 | 0x1 } 00055a14: 0000: 00060920 00000067 00055a08: 0000: c0033000 00500000 00000000 00060920 00000067 t0 write GRAS_SC_CONTROL (207b) GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 0 | RASTER_MODE = 0 } 00055a1c: 0000: 0000207b 00000000 t0 write RB_MSAA_CONTROL (20a2) RB_MSAA_CONTROL: { SAMPLES = 0 } 00055a24: 0000: 000020a2 00000000 t0 write RB_RENDER_CONTROL (20a1) RB_RENDER_CONTROL: { 0 } 00055a2c: 0000: 000020a1 00000000 t0 write 0x2382 (2382) 0x2382: 00000000 00055a34: 0000: 00002382 00000000 t0 write RB_DEPTH_CONTROL (2101) RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } 00055a3c: 0000: 00002101 00000000 t0 write GRAS_ALPHA_CONTROL (2073) GRAS_ALPHA_CONTROL: { 0 } 00055a44: 0000: 00002073 00000000 t0 write RB_STENCIL_CONTROL (2106) RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } 00055a4c: 0000: 00002106 00000000 t0 write SP_FS_MRT[0].REG (22f1) SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = RB4_R8G8B8A8_UNORM } 00055a54: 0000: 000022f1 0001a000 t0 write RB_MRT[0].BUF_INFO (20a5) RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB4_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE4_3 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 256 } RB_MRT[0].BASE: 0x166000 RB_MRT[0].CONTROL3: { STRIDE = 0 } 00055a5c: 0000: 000220a5 000400da 00166000 00000000 t3 opcode: CP_LOAD_STATE4 (30) (11 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_TEX | NUM_UNIT = 1 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } { TILED | SWIZ_X = A4XX_TEX_X | SWIZ_Y = A4XX_TEX_Y | SWIZ_Z = A4XX_TEX_Z | SWIZ_W = A4XX_TEX_W | MIPLVLS = 0 | FMT = TFMT4_8_8_8_8_UNORM | TYPE = A4XX_TEX_2D | 0x2 } { HEIGHT = 64 | WIDTH = 64 } { PITCHALIGN = 0 | PITCH = 256 | SWAP = WZYX } { LAYERSZ = 0 | DEPTH = 1 | 0x20000 } { LAYERSZ = 4096 | BASE = 0x4f000 } { 5 = 0 } { 6 = 0 } { 7 = 0 } 00055a78: 0000: 27006883 00200040 00020000 00060000 0004f001 00000000 00000000 00000000 00055a6c: 0000: c0093000 00500000 00000001 27006883 00200040 00020000 00060000 0004f001 * t0 write VPC_VARYING_PS_REPL[0].MODE (214a) VPC_VARYING_PS_REPL[0].MODE: 0x99999999 00055a98: 0000: 0000214a 99999999 t0 write GRAS_SC_SCREEN_SCISSOR_TL (207c) GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } 00055aa0: 0000: 0001207c 00000000 003f003f t0 write GRAS_SC_WINDOW_SCISSOR_BR (209c) GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 00055aac: 0000: 0001209c 003f003f 00000000 t0 write RB_FRAME_BUFFER_DIMENSION (0ce0) RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } 00055ab8: 0000: 00000ce0 00400040 t0 write 0xce1 (0ce1) 0xce1: 00000000 00055ac0: 0000: 00000ce1 00000000 t0 write RB_RENDER_CONTROL2 (20a3) RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 | IJ_PERSP_PIXEL } 00055ac8: 0000: 000020a3 00001000 t0 write RB_MODE_CONTROL (20a0) RB_MODE_CONTROL: { WIDTH = 0 | HEIGHT = 0 | 0xc00000 } 00055ad0: 0000: 000020a0 00c00000 t3 opcode: CP_LOAD_STATE4 (30) (11 dwords) { DST_OFF = 8 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } 00055ae4: 0.000000 0.000000 0.000000 0.000000 64.000000 64.000000 64.000000 64.000000 00055ae4: 0000: 00000000 00000000 00000000 00000000 42800000 42800000 42800000 42800000 00055ad8: 0000: c0093000 00a00008 00000001 00000000 00000000 00000000 00000000 42800000 00055af8: 0020: 42800000 42800000 42800000 t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x80000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 2 } draw[39] register values + 00000004 UNKNOWN_0CC5: 0x4 + 00000000 UNKNOWN_0CC6: 0 + 00400040 RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } + 00000000 0xce1: 00000000 + 00000002 HLSQ_MODE_CONTROL: 0x2 + 00000000 UNKNOWN_0E42: 0 + 00000004 SP_MODE_CONTROL: 0x4 + 00000068 TPL1_TP_MODE_CONTROL: 0x68 + 00188000 GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } + 00000000 UNKNOWN_2001: 0 + 00000001 GRAS_CNTL: { IJ_PERSP } !+ 00000000 GRAS_ALPHA_CONTROL: { 0 } + 00000000 GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } !+ 00000000 GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 0 | RASTER_MODE = 0 } + 00000000 GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } + 003f003f GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } + 003f003f GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } + 00000000 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } !+ 00c00000 RB_MODE_CONTROL: { WIDTH = 0 | HEIGHT = 0 | 0xc00000 } !+ 00000000 RB_RENDER_CONTROL: { 0 } !+ 00000000 RB_MSAA_CONTROL: { SAMPLES = 0 } !+ 00001000 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 | IJ_PERSP_PIXEL } !+ 0f000000 RB_MRT[0].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0xf } !+ 000400da RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB4_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE4_3 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 256 } !+ 00166000 RB_MRT[0].BASE: 0x166000 !+ 00000000 RB_MRT[0].CONTROL3: { STRIDE = 0 } + 00000000 RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } + 0f000000 RB_MRT[0x1].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0xf } + 00000e00 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } !+ ffff0000 RB_FS_OUTPUT: { ENABLE_BLEND = 0 | SAMPLE_MASK = 0xffff } + 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } + 00000001 RB_FS_OUTPUT_REG: { MRT = 1 } + 00000000 RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } + 00000000 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } !+ 42001008 VPC_ATTR: { TOTALATTR = 8 | THRDASSIGN = 1 | ENABLE | 0x40000000 } !+ 00060800 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 8 | NUMNONPOSVSVAR = 6 } !+ 0000e000 VPC_VARYING_INTERP[0].MODE: 0xe000 !+ 99999999 VPC_VARYING_PS_REPL[0].MODE: 0x99999999 + 00000000 UNKNOWN_2152: 0 + 00000000 UNKNOWN_2153: 0 + 00000000 UNKNOWN_2154: 0 + 00000000 UNKNOWN_2155: 0 + 00000000 UNKNOWN_2156: 0 + 0000001d UNKNOWN_21C3: 0x1d + 00000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 } + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + 00000000 PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } + 00000001 UNKNOWN_21E6: 0x1 + 000a0000 VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } + fc030000 VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } + fcfcfcfc VFD_CONTROL_2: 0xfcfcfcfc + fcfcfc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } + 0000fcfc VFD_CONTROL_4: 0xfcfc + 00000000 VFD_INDEX_OFFSET: 0 + 00000000 UNKNOWN_2209: 0 + 00060010 SP_SP_CTRL_REG: { 0x60010 } + 000005c3 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } + 00200c10 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } + 01000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } !+ 0020fc03 SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 2 } !+ 06071e03 SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r1.w | B_COMPMASK = 0x3 } + 00000000 SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00fcfc00 UNKNOWN_22D7: 0xfcfc00 !+ 00000c08 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 12 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } + 00000001 SP_VS_OBJ_START: 0x1 + 00000002 SP_VS_LENGTH_REG: 2 !+ 00700402 SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 0 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE | PIXLODENABLE } !+ 8010003e SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 } !+ 40420000 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 } !+ 00000001 SP_FS_OBJ_START: 0x1 + 00000001 SP_FS_LENGTH_REG: 1 !+ 00000001 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r0.x | SAMPLEMASK_REGID = r0.x } !+ 0001a000 SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = RB4_R8G8B8A8_UNORM } + 00000000 TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } !+ 00000000 0x2382: 00000000 + 00000003 TPL1_TP_FS_TEX_COUNT: 0x3 + 080004f0 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } + fcfc0120 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } + 27f3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } + fcfcfc00 HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } !+ 00fcfcfc HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } + 02010042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } !+ 0141423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 1 } + 00404200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00004200 HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } + 00000007 HLSQ_UPDATE_CONTROL: 0x7 00055b04: 0000: c0023800 00080888 00000001 00000002 t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = CACHE_FLUSH } event CACHE_FLUSH 00055b14: 0000: c0004600 00000006 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00055b1c: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0x8000012 00055b24: 0000: 00000cc6 08000012 00173000: 0000: c0013f00 000555d8 00000155 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 0017300c: 0000: c0014300 00040000 00000000 t3 opcode: (null) (1d) (2 dwords) 00173018: 0000: c0001d00 00000000 ############################################################ vertices: 0 ############################################################ cmdstream: 51 dwords t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 0016b000: 0000: c0002600 00000000 t0 write UCHE_INVALIDATE0 (0e8a) UCHE_INVALIDATE0: 0 UCHE_INVALIDATE1: 0x12 0016b008: 0000: 00010e8a 00000000 00000012 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 0016b014: 0000: c0002600 00000000 t0 write RB_MODE_CONTROL (20a0) RB_MODE_CONTROL: { WIDTH = 64 | HEIGHT = 64 | ENABLE_GMEM } 0016b01c: 0000: 000020a0 00010202 t0 write RB_FRAME_BUFFER_DIMENSION (0ce0) RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } 0016b024: 0000: 00000ce0 00400040 t0 write 0xce1 (0ce1) 0xce1: 00000001 0016b02c: 0000: 00000ce1 00000001 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 0016b034: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0 0016b03c: 0000: 00000cc6 00000000 t3 opcode: (null) (1d) (2 dwords) 0016b044: 0000: c0001d00 00000000 t0 write GRAS_SC_WINDOW_SCISSOR_BR (209c) GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 0016b04c: 0000: 0001209c 003f003f 00000000 t0 write RB_BIN_OFFSET (210d) RB_BIN_OFFSET: { X = 0 | Y = 0 } 0016b058: 0000: 0000210d 00000000 t0 write GRAS_SC_WINDOW_SCISSOR_BR (209c) GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 0016b060: 0000: 0001209c 003f003f 00000000 t0 write UNKNOWN_2157 (2157) UNKNOWN_2157: 0x1 0016b06c: 0000: 00002157 00000001 t3 opcode: (null) (64) (2 dwords) 0016b074: 0000: c0006400 00000001 t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:00054994 ibsize:000000f6 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00054994: 0000: c0002600 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x4 0005499c: 0000: 00000ec3 00000004 t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x68 000549a4: 0000: 00000f03 00000068 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 000549ac: 0000: c0002600 00000000 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } 000549b4: 0000: 000023c0 080004f0 t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = 0x1d } event (null) 000549bc: 0000: c0004600 0000001d t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = FACENESS_FLUSH } event FACENESS_FLUSH 000549c4: 0000: c0004600 0000001c t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 000549cc: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0 000549d4: 0000: 00000cc6 00000000 t0 write UNKNOWN_0E42 (0e42) UNKNOWN_0E42: 0 000549dc: 0000: 00000e42 00000000 t0 write HLSQ_MODE_CONTROL (0e05) HLSQ_MODE_CONTROL: 0x2 000549e4: 0000: 00000e05 00000002 t0 write UNKNOWN_0CC5 (0cc5) UNKNOWN_0CC5: 0x4 000549ec: 0000: 00000cc5 00000004 t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x7 000549f4: 0000: 000023db 00000007 t0 write VFD_CONTROL_2 (2202) VFD_CONTROL_2: 0xfcfcfcfc 000549fc: 0000: 00002202 fcfcfcfc t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } 00054a04: 0000: 00002203 fcfcfc00 t0 write VFD_CONTROL_4 (2204) VFD_CONTROL_4: 0xfcfc 00054a0c: 0000: 00002204 0000fcfc t0 write VFD_INDEX_OFFSET (2208) VFD_INDEX_OFFSET: 0 00054a14: 0000: 00002208 00000000 t0 write UNKNOWN_2209 (2209) UNKNOWN_2209: 0 00054a1c: 0000: 00002209 00000000 t0 write UNKNOWN_2152 (2152) UNKNOWN_2152: 0 UNKNOWN_2153: 0 00054a24: 0000: 00012152 00000000 00000000 t0 write UNKNOWN_2156 (2156) UNKNOWN_2156: 0 00054a30: 0000: 00002156 00000000 t0 write UNKNOWN_2154 (2154) UNKNOWN_2154: 0 00054a38: 0000: 00002154 00000000 t0 write UNKNOWN_2155 (2155) UNKNOWN_2155: 0 00054a40: 0000: 00002155 00000000 t0 write UNKNOWN_21C3 (21c3) UNKNOWN_21C3: 0x1d 00054a48: 0000: 000021c3 0000001d t0 write PC_PRIM_VTX_CNTL2 (21c5) PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 00054a50: 0000: 000021c5 00000012 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 00054a58: 0000: 000021e5 00000000 t0 write GRAS_SU_MODE_CONTROL (2078) GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } 00054a60: 0000: 00002078 00000000 t0 write UNKNOWN_2001 (2001) UNKNOWN_2001: 0 00054a68: 0000: 00002001 00000000 t0 write GRAS_CNTL (2003) GRAS_CNTL: { IJ_PERSP } 00054a70: 0000: 00002003 00000001 t0 write GRAS_CL_CLIP_CNTL (2000) GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } 00054a78: 0000: 00002000 00188000 t0 write TPL1_TP_TEX_COUNT (2381) TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } 00054a80: 0000: 00002381 00000000 t0 write TPL1_TP_FS_TEX_COUNT (23a0) TPL1_TP_FS_TEX_COUNT: 0x3 00054a88: 0000: 000023a0 00000003 t0 write RB_ALPHA_CONTROL (20f8) RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } 00054a90: 0000: 000020f8 00000e00 t0 write RB_RENDER_COMPONENTS (20fb) RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } 00054a98: 0000: 000020fb 0000000f t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 00054aa0: 0000: c0014300 00040000 00000000 t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } 00054aac: 0000: 00002200 000a0000 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } 00054ab4: 0000: 00002201 fc030000 t0 write SP_INSTR_CACHE_CTRL (22c1) SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } 00054abc: 0000: 000022c1 000005c3 t0 write HLSQ_CONTROL_1_REG (23c1) HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } 00054ac4: 0000: 000023c1 fcfc0120 t0 write HLSQ_CONTROL_2_REG (23c2) HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 00054acc: 0000: 000023c2 27f3f3f0 t0 write HLSQ_VS_CONTROL_REG (23c5) HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } 00054ad4: 0000: 000023c5 02010042 t0 write HLSQ_FS_CONTROL_REG (23c6) HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00054adc: 0000: 000023c6 0041423e t0 write HLSQ_HS_CONTROL_REG (23c7) HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00054ae4: 0000: 000023c7 00404200 t0 write HLSQ_DS_CONTROL_REG (23c8) HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00054aec: 0000: 000023c8 00404200 t0 write HLSQ_GS_CONTROL_REG (23c9) HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00054af4: 0000: 000023c9 00404200 t0 write HLSQ_CS_CONTROL_REG (23ca) HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } 00054afc: 0000: 000023ca 00004200 t0 write SP_SP_CTRL_REG (22c0) SP_SP_CTRL_REG: { 0x60010 } 00054b04: 0000: 000022c0 00060010 t0 write UNKNOWN_21E6 (21e6) UNKNOWN_21E6: 0x1 00054b0c: 0000: 000021e6 00000001 t0 write SP_VS_CTRL_REG0 (22c4) SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 00054b14: 0000: 000022c4 00200c10 t0 write SP_VS_CTRL_REG1 (22c5) SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } 00054b1c: 0000: 000022c5 01000042 t0 write VPC_ATTR (2140) VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | 0x40000000 } 00054b24: 0000: 00002140 40001004 t0 write VPC_PACK (2141) VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } 00054b2c: 0000: 00002141 00040400 t0 write PC_PRIM_VTX_CNTL (21c4) PC_PRIM_VTX_CNTL: { VAROUT = 1 } 00054b34: 0000: 000021c4 00000001 t0 write SP_VS_PARAM_REG (22c6) SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } UNKNOWN_22D7: 0xfcfc00 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 00054b3c: 0000: 001922c6 0010fc03 00001e03 00000000 00000000 00000000 00000000 00000000 * 00054b7c: 0040: 00000000 00000000 00fcfc00 00000008 00000000 00000000 00000000 00000000 * t0 write SP_VS_OBJ_OFFSET_REG (22e0) SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 00054ba8: 0000: 000022e0 00000000 t0 write SP_VS_OBJ_START (22e1) SP_VS_OBJ_START: 0x1 00054bb0: 0000: 000022e1 00000001 t0 write SP_VS_LENGTH_REG (22e5) SP_VS_LENGTH_REG: 2 00054bb8: 0000: 000022e5 00000002 t3 opcode: CP_LOAD_STATE4 (30) (67 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } :2:0000:0000[56d81803x_20020003x] (sy)(ss)(nop3) shl.b r0.w, r0.w, 2 :1:0001:0004[20150000x_00000003x] cov.s32s16 hr0.x, r0.w :0:0002:0005[00000200x_00000000x] (rpt2)nop :1:0003:0008[201100f4x_00000000x] mova a0.x, hr0.x :0:0004:0009[00000500x_00000000x] (rpt5)nop :1:0005:0015[20154003x_00000c20x] mov.s32s32 r0.w, c :1:0006:0016[20154004x_00000c21x] mov.s32s32 r1.x, c :1:0007:0017[20154005x_00000c22x] mov.s32s32 r1.y, c :1:0008:0018[20156006x_00000c23x] (ul)mov.s32s32 r1.z, c :0:0009:0019[03000000x_00000000x] end :2:0010:0020[46f00007x_20050000x] shr.b r1.w, r0.x, 5 :2:0011:0021[43980008x_201f0000x] (nop2) and.b r2.x, r0.x, 31 :2:0012:0024[43980807x_201f0007x] (nop3) and.b r1.w, r1.w, 31 :2:0013:0028[46100807x_20100007x] (nop1) mul.u24 r1.w, r1.w, 16 :3:0014:0030[62040007x_00071014x] mad.u24 r1.w, c5.x, r2.x, r1.w :0:0015:0031[00000500x_00000000x] (rpt5)nop :6:0016:0037[c2c60f00x_04800006x] stlw.u32 l[r1.w], r0.w, 4 :0:0017:0038[04800000x_00000000x] chmask :0:0018:0039[05000000x_00000000x] chsh Stats: - shaderdb: 40 instr, 24 nops, 16 non-nops, 5 mov, 1 cov - shaderdb: 0 last-baryf, 0 half, 2 full, 5 constlen - shaderdb: 27 cat0, 6 cat1, 5 cat2, 1 cat3, 0 cat4, 0 cat5, 1 cat6, 0 cat7 - shaderdb: 0 sstall, 1 (ss), 1 (sy) 00054bc0: 0000: c0413000 00a00000 00000000 20020003 56d81803 00000003 20150000 00000000 00054be0: 0020: 00000200 00000000 201100f4 00000000 00000500 00000c20 20154003 00000c21 00054c00: 0040: 20154004 00000c22 20154005 00000c23 20156006 00000000 03000000 20050000 00054c20: 0060: 46f00007 201f0000 43980008 201f0007 43980807 20100007 46100807 00071014 00054c40: 0080: 62040007 00000000 00000500 04800006 c2c60f00 00000000 04800000 00000000 00054c60: 00a0: 05000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 * t0 write GRAS_ALPHA_CONTROL (2073) GRAS_ALPHA_CONTROL: { 0x2 } 00054ccc: 0000: 00002073 00000002 t0 write GRAS_SC_CONTROL (207b) GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = 4 | MSAA_DISABLE | RASTER_MODE = 0 } 00054cd4: 0000: 0000207b 00000a08 t0 write RB_MSAA_CONTROL (20a2) RB_MSAA_CONTROL: { DISABLE | SAMPLES = 4 } 00054cdc: 0000: 000020a2 00009000 t0 write RB_RENDER_CONTROL (20a1) RB_RENDER_CONTROL: { DISABLE_COLOR_PIPE | 0x2 } 00054ce4: 0000: 000020a1 00000022 t0 write RB_CLEAR_COLOR_DW0 (20cc) RB_CLEAR_COLOR_DW0: 0xff000000 RB_CLEAR_COLOR_DW1: 0 RB_CLEAR_COLOR_DW2: 0 RB_CLEAR_COLOR_DW3: 0 00054cec: 0000: 000320cc ff000000 00000000 00000000 00000000 t0 write RB_COPY_CONTROL (20fc) RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_FOUR | MODE = RB_COPY_CLEAR | FASTCLEAR = 0xf | GMEM_BASE = 0 } RB_COPY_DEST_BASE: { BASE = 0x4f000 } RB_COPY_DEST_PITCH: { PITCH = 256 } RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_IF_ALPHA_OFF | COMPONENT_ENABLE = 0 | ENDIAN = ENDIAN_NONE | TILE = TILE4_3 } 00054d00: 0000: 000320fc 00000f22 0004f000 00000008 03000868 t0 write GRAS_SC_SCREEN_SCISSOR_TL (207c) GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } 00054d14: 0000: 0001207c 00000000 003f003f t0 write RB_FRAME_BUFFER_DIMENSION (0ce0) RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } 00054d20: 0000: 00000ce0 00400040 t0 write 0xce1 (0ce1) 0xce1: 00000000 00054d28: 0000: 00000ce1 00000000 t3 opcode: CP_LOAD_STATE4 (30) (11 dwords) { DST_OFF = 8 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } 00054d3c: 0.000000 0.000000 1.000000 1.000000 64.000000 64.000000 1.000000 1.000000 00054d3c: 0000: 00000000 00000000 3f800000 3f800000 42800000 42800000 3f800000 3f800000 00054d30: 0000: c0093000 00a00008 00000001 00000000 00000000 3f800000 3f800000 42800000 00054d50: 0020: 42800000 3f800000 3f800000 t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x80000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 2 } draw[40] register values + 00000004 UNKNOWN_0CC5: 0x4 + 00000000 UNKNOWN_0CC6: 0 + 00400040 RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } + 00000000 0xce1: 00000000 + 00000002 HLSQ_MODE_CONTROL: 0x2 + 00000000 UNKNOWN_0E42: 0 + 00000000 UCHE_INVALIDATE0: 0 + 00000012 UCHE_INVALIDATE1: 0x12 + 00000004 SP_MODE_CONTROL: 0x4 + 00000068 TPL1_TP_MODE_CONTROL: 0x68 + 00188000 GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } + 00000000 UNKNOWN_2001: 0 + 00000001 GRAS_CNTL: { IJ_PERSP } !+ 00000002 GRAS_ALPHA_CONTROL: { 0x2 } + 00000000 GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } !+ 00000a08 GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = 4 | MSAA_DISABLE | RASTER_MODE = 0 } + 00000000 GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } + 003f003f GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } + 003f003f GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } + 00000000 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } !+ 00010202 RB_MODE_CONTROL: { WIDTH = 64 | HEIGHT = 64 | ENABLE_GMEM } !+ 00000022 RB_RENDER_CONTROL: { DISABLE_COLOR_PIPE | 0x2 } !+ 00009000 RB_MSAA_CONTROL: { DISABLE | SAMPLES = 4 } + ff000000 RB_CLEAR_COLOR_DW0: 0xff000000 + 00000000 RB_CLEAR_COLOR_DW1: 0 + 00000000 RB_CLEAR_COLOR_DW2: 0 + 00000000 RB_CLEAR_COLOR_DW3: 0 + 00000e00 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } + 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } !+ 00000f22 RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_FOUR | MODE = RB_COPY_CLEAR | FASTCLEAR = 0xf | GMEM_BASE = 0 } + 0004f000 RB_COPY_DEST_BASE: { BASE = 0x4f000 } + 00000008 RB_COPY_DEST_PITCH: { PITCH = 256 } !+ 03000868 RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_IF_ALPHA_OFF | COMPONENT_ENABLE = 0 | ENDIAN = ENDIAN_NONE | TILE = TILE4_3 } + 00000000 RB_BIN_OFFSET: { X = 0 | Y = 0 } !+ 40001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | 0x40000000 } !+ 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } + 00000000 UNKNOWN_2152: 0 + 00000000 UNKNOWN_2153: 0 + 00000000 UNKNOWN_2154: 0 + 00000000 UNKNOWN_2155: 0 + 00000000 UNKNOWN_2156: 0 + 00000001 UNKNOWN_2157: 0x1 + 0000001d UNKNOWN_21C3: 0x1d + 00000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 } + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + 00000000 PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } + 00000001 UNKNOWN_21E6: 0x1 + 000a0000 VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } + fc030000 VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } + fcfcfcfc VFD_CONTROL_2: 0xfcfcfcfc + fcfcfc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } + 0000fcfc VFD_CONTROL_4: 0xfcfc + 00000000 VFD_INDEX_OFFSET: 0 + 00000000 UNKNOWN_2209: 0 + 00060010 SP_SP_CTRL_REG: { 0x60010 } + 000005c3 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } + 00200c10 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } + 01000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } !+ 0010fc03 SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } !+ 00001e03 SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00fcfc00 UNKNOWN_22D7: 0xfcfc00 !+ 00000008 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } + 00000001 SP_VS_OBJ_START: 0x1 + 00000002 SP_VS_LENGTH_REG: 2 + 00000000 TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } + 00000003 TPL1_TP_FS_TEX_COUNT: 0x3 + 080004f0 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } + fcfc0120 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } + 27f3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } + 02010042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } !+ 0041423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00004200 HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } + 00000007 HLSQ_UPDATE_CONTROL: 0x7 00054d5c: 0000: c0023800 00080888 00000001 00000002 0016b07c: 0000: c0013f00 00054994 000000f6 t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:00054d6c ibsize:00000037 t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } 00054d6c: 0000: 00002200 082a0008 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00054d74: 0000: c0002600 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x1e 00054d7c: 0000: 00000ec3 0000001e t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x28 00054d84: 0000: 00000f03 00000028 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00054d8c: 0000: c0002600 00000000 t0 write HLSQ_MODE_CONTROL (0e05) HLSQ_MODE_CONTROL: 0x1 00054d94: 0000: 00000e05 00000001 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0x600a0 } 00054d9c: 0000: 000023c0 080604f0 t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x7 00054da4: 0000: 000023db 00000007 t0 write PC_RESTART_INDEX (21c6) PC_RESTART_INDEX: 0xffffffff 00054dac: 0000: 000021c6 ffffffff t0 write UNKNOWN_21E6 (21e6) UNKNOWN_21E6: 0x1 00054db4: 0000: 000021e6 00000001 t0 write UNKNOWN_21C3 (21c3) UNKNOWN_21C3: 0x1f 00054dbc: 0000: 000021c3 0000001f t0 write TPL1_TP_TEX_OFFSET (2380) TPL1_TP_TEX_OFFSET: 0x808 00054dc4: 0000: 00002380 00000808 t0 write GRAS_SU_POINT_MINMAX (2070) GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 4092.000000 } GRAS_SU_POINT_SIZE: 0.500000 00054dcc: 0000: 00012070 ffc00010 00000008 t0 write UNKNOWN_2152 (2152) UNKNOWN_2152: 0 UNKNOWN_2153: 0 00054dd8: 0000: 00012152 00000000 00000000 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00054de4: 0000: c0002600 00000000 t0 write UNKNOWN_0CC5 (0cc5) UNKNOWN_0CC5: 0x4 00054dec: 0000: 00000cc5 00000004 t0 write 0xcc4 (0cc4) 0xcc4: 00000000 00054df4: 0000: 00000cc4 00000000 t0 write 0xd03 (0d03) 0xd03: 80200000 00054dfc: 0000: 00000d03 80200000 t0 write UNKNOWN_0EC2 (0ec2) UNKNOWN_0EC2: 0x40000 00054e04: 0000: 00000ec2 00040000 t0 write VPC_DEBUG_ECO_CONTROL (0e64) VPC_DEBUG_ECO_CONTROL: 0x100 00054e0c: 0000: 00000e64 00000100 t0 write UNKNOWN_0E42 (0e42) UNKNOWN_0E42: 0 00054e14: 0000: 00000e42 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x1e 00054e1c: 0000: 00000ec3 0000001e t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x28 00054e24: 0000: 00000f03 00000028 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 00054e2c: 0000: c0014300 00040000 00000000 t0 write VFD_INDEX_OFFSET (2208) VFD_INDEX_OFFSET: 0 00054e38: 0000: 00002208 00000000 t0 write UNKNOWN_2209 (2209) UNKNOWN_2209: 0 00054e40: 0000: 00002209 00000000 0016b088: 0000: c0013f00 00054d6c 00000037 t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:00055328 ibsize:000000ac t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x3 00055328: 0000: 000023db 00000003 t0 write SP_INSTR_CACHE_CTRL (22c1) SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } 00055330: 0000: 000022c1 000005c3 t0 write HLSQ_CONTROL_1_REG (23c1) HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x1008 } 00055338: 0000: 000023c1 fcfc1108 t0 write HLSQ_CONTROL_2_REG (23c2) HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 00055340: 0000: 000023c2 fff3f3f0 t0 write HLSQ_VS_CONTROL_REG (23c5) HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 2 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 1 } 00055348: 0000: 000023c5 01010002 t0 write HLSQ_HS_CONTROL_REG (23c7) HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 00055350: 0000: 000023c7 007e0200 t0 write HLSQ_DS_CONTROL_REG (23c8) HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 00055358: 0000: 000023c8 007e0200 t0 write HLSQ_GS_CONTROL_REG (23c9) HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 00055360: 0000: 000023c9 007e0200 t0 write HLSQ_FS_CONTROL_REG (23c6) HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 2 | CONSTOBJECTOFFSET = 2 | ENABLED | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 } 00055368: 0000: 000023c6 017f0202 t0 write SP_VS_OBJ_OFFSET_REG (22e0) SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 00055370: 0000: 000022e0 00000000 t0 write SP_HS_OBJ_OFFSET_REG (230d) SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } 00055378: 0000: 0000230d 7e020000 t0 write SP_DS_OBJ_OFFSET_REG (2334) SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } 00055380: 0000: 00002334 7e020000 t0 write SP_GS_OBJ_OFFSET_REG (235b) SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } 00055388: 0000: 0000235b 7e020000 t0 write SP_FS_OBJ_OFFSET_REG (22ea) SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } 00055390: 0000: 000022ea 7e020000 t0 write SP_VS_OBJ_START (22e1) SP_VS_OBJ_START: 0x49000 00049000: 0000: 00000000 13000000 00000000 00000000 00000000 00000000 00000000 00000000 * :0:0000:0000[13000000x_00000000x] (sy)end :0:0001:0001[00000000x_00000000x] nop :0:0002:0002[00000000x_00000000x] nop :0:0003:0003[00000000x_00000000x] nop :0:0004:0004[00000000x_00000000x] nop Stats: - shaderdb: 5 instr, 4 nops, 1 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 0 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 0 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) 00055398: 0000: 000022e1 00049000 t0 write SP_HS_OBJ_START (230e) SP_HS_OBJ_START: 0 000553a0: 0000: 0000230e 00000000 t0 write SP_DS_OBJ_START (2335) SP_DS_OBJ_START: 0 000553a8: 0000: 00002335 00000000 t0 write SP_GS_OBJ_START (235c) SP_GS_OBJ_START: 0 000553b0: 0000: 0000235c 00000000 t0 write SP_VS_LENGTH_REG (22e5) SP_VS_LENGTH_REG: 1 000553b8: 0000: 000022e5 00000001 t3 opcode: CP_LOAD_STATE4 (30) (3 dwords) { DST_OFF = 0 | STATE_SRC = SS4_INDIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 1 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0x49000 } :0:0000:0000[13000000x_00000000x] (sy)end :0:0001:0001[00000000x_00000000x] nop :0:0002:0002[00000000x_00000000x] nop :0:0003:0003[00000000x_00000000x] nop :0:0004:0004[00000000x_00000000x] nop Stats: - shaderdb: 5 instr, 4 nops, 1 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 0 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 0 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) 000553c0: 0000: c0013000 00620000 00049000 t0 write 0x2072 (2072) 0x2072: 00000000 000553cc: 0000: 00002072 00000000 t0 write UNKNOWN_2155 (2155) UNKNOWN_2155: 0 000553d4: 0000: 00002155 00000000 t0 write GRAS_CNTL (2003) GRAS_CNTL: { IJ_PERSP } 000553dc: 0000: 00002003 00000001 t0 write VPC_VARYING_INTERP[0].MODE (2142) VPC_VARYING_INTERP[0].MODE: 0 000553e4: 0000: 00002142 00000000 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0x600a0 } 000553ec: 0000: 000023c0 080604f0 t0 write HLSQ_CONTROL_3_REG (23c3) HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } 000553f4: 0000: 000023c3 fcfcfc00 t0 write HLSQ_CONTROL_4_REG (23c4) HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r0.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } 000553fc: 0000: 000023c4 00fcfc00 t0 write SP_FS_CTRL_REG0 (22e8) SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE } SP_FS_CTRL_REG1: { CONSTLENGTH = 2 | VARYING | 0x80000000 } 00055404: 0000: 000122e8 00340412 80100002 t0 write SP_FS_OBJ_START (22eb) SP_FS_OBJ_START: 0x46000 00046000: 0000: 00002000 5730cb00 00000000 03000000 00000000 00000000 00000000 00000000 * :2:0000:0000[5730cb00x_00002000x] (sy)(rpt3)bary.f (ei)hr0.x, (r)0, r0.x :0:0001:0004[03000000x_00000000x] end :0:0002:0005[00000000x_00000000x] nop :0:0003:0006[00000000x_00000000x] nop :0:0004:0007[00000000x_00000000x] nop :0:0005:0008[00000000x_00000000x] nop Stats: - shaderdb: 9 instr, 4 nops, 5 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 1 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 4 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) 00055410: 0000: 000022eb 00046000 t0 write SP_FS_LENGTH_REG (22ef) SP_FS_LENGTH_REG: 1 00055418: 0000: 000022ef 00000001 t0 write RB_RENDER_COMPONENTS (20fb) RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } 00055420: 0000: 000020fb 0000000f t3 opcode: CP_LOAD_STATE4 (30) (3 dwords) { DST_OFF = 0 | STATE_SRC = SS4_INDIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 1 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0x46000 } :2:0000:0000[5730cb00x_00002000x] (sy)(rpt3)bary.f (ei)hr0.x, (r)0, r0.x :0:0001:0004[03000000x_00000000x] end :0:0002:0005[00000000x_00000000x] nop :0:0003:0006[00000000x_00000000x] nop :0:0004:0007[00000000x_00000000x] nop :0:0005:0008[00000000x_00000000x] nop Stats: - shaderdb: 9 instr, 4 nops, 5 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 1 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 4 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) 00055428: 0000: c0013000 00720000 00046000 t0 write SP_SP_CTRL_REG (22c0) SP_SP_CTRL_REG: { 0x60010 } 00055434: 0000: 000022c0 00060010 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 28 | GROUP_ID = 3 } { ADDR_LO = 0x9ace0 } 0005543c: 0000: c0014300 0300001c 0009ace0 t0 write RB_DEPTH_INFO (2103) RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTH4_NONE | DEPTH_BASE = 0 } RB_DEPTH_PITCH: 0 RB_DEPTH_PITCH2: 0 00055448: 0000: 00022103 00000000 00000000 00000000 t0 write GRAS_DEPTH_CONTROL (2077) GRAS_DEPTH_CONTROL: { FORMAT = DEPTH4_NONE } 00055458: 0000: 00002077 00000000 t0 write RB_STENCIL_INFO (2108) RB_STENCIL_INFO: { STENCIL_BASE = 0 } RB_STENCIL_PITCH: 0 0x210a: 00000000 00055460: 0000: 00022108 00000000 00000000 00000000 t0 write 0x2002 (2002) 0x2002: 00000000 00055470: 0000: 00002002 00000000 t0 write RB_ALPHA_CONTROL (20f8) RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } 00055478: 0000: 000020f8 00000e00 t0 write RB_MRT[0].CONTROL (20a4) RB_MRT[0].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0x7 } 00055480: 0000: 000020a4 07000c00 t0 write RB_MRT[0].BLEND_CONTROL (20a8) RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } 00055488: 0000: 000020a8 00000000 t0 write GRAS_CL_CLIP_CNTL (2000) GRAS_CL_CLIP_CNTL: { 0x80000 } 00055490: 0000: 00002000 00080000 t0 write GRAS_SU_POLY_OFFSET_SCALE (2074) GRAS_SU_POLY_OFFSET_SCALE: 0.000000 GRAS_SU_POLY_OFFSET_OFFSET: 0.000000 GRAS_SU_POLY_OFFSET_CLAMP: 0.000000 00055498: 0000: 00022074 00000000 00000000 00000000 t0 write GRAS_SU_MODE_CONTROL (2078) GRAS_SU_MODE_CONTROL: { FRONT_CW | LINEHALFWIDTH = 0.500000 | MSAA_ENABLE | RENDERING_PASS } 000554a8: 0000: 00002078 00102014 t0 write GRAS_SC_SCREEN_SCISSOR_TL (207c) GRAS_SC_SCREEN_SCISSOR_TL: { X = 2 | Y = 13 } GRAS_SC_SCREEN_SCISSOR_BR: { X = 33 | Y = 44 } 000554b0: 0000: 0001207c 000d0002 002c0021 t0 write GRAS_CL_VPORT_XOFFSET_0 (2008) GRAS_CL_VPORT_XOFFSET_0: 18.000000 GRAS_CL_VPORT_XSCALE_0: 16.000000 GRAS_CL_VPORT_YOFFSET_0: 29.000000 GRAS_CL_VPORT_YSCALE_0: 16.000000 GRAS_CL_VPORT_ZOFFSET_0: 0.500000 GRAS_CL_VPORT_ZSCALE_0: 0.500000 000554bc: 0000: 00052008 41900000 41800000 41e80000 41800000 3f000000 3f000000 t0 write GRAS_CL_GB_CLIP_ADJ (2004) GRAS_CL_GB_CLIP_ADJ: { HORZ = 511 | VERT = 511 } 000554d8: 0000: 00002004 0007fdff t0 write GRAS_SC_CONTROL (207b) GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 4 | RASTER_MODE = 0 } 000554e0: 0000: 0000207b 00000200 t0 write 0x2382 (2382) 0x2382: 00000002 000554e8: 0000: 00002382 00000002 t0 write RB_MSAA_CONTROL (20a2) RB_MSAA_CONTROL: { SAMPLES = 4 } 000554f0: 0000: 000020a2 00008000 t0 write RB_RENDER_CONTROL2 (20a3) RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 4 | IJ_PERSP_PIXEL } 000554f8: 0000: 000020a3 00001200 t0 write RB_MRT[0].BUF_INFO (20a5) RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB4_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_ALWAYS | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 1024 } RB_MRT[0].BASE: 0 RB_MRT[0].CONTROL3: { STRIDE = 64 } 00055500: 0000: 000220a5 0010029a 00000000 00000200 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 43 | GROUP_ID = 2 } { ADDR_LO = 0x9ad50 } 00055510: 0000: c0014300 0200002b 0009ad50 t0 write 0x215c (215c) 0x215c: 00000000 0x215d: 00000000 0005551c: 0000: 0001215c 00000000 00000000 t0 write 0x215f (215f) 0x215f: 00000000 00055528: 0000: 0000215f 00000000 t0 write 0x215e (215e) 0x215e: 00000000 00055530: 0000: 0000215e 00000000 t0 write 0x2161 (2161) 0x2161: 00000000 0x2162: 00000000 00055538: 0000: 00012161 00000000 00000000 t0 write 0x2164 (2164) 0x2164: 00000000 00055544: 0000: 00002164 00000000 t0 write 0x2163 (2163) 0x2163: 00000000 0005554c: 0000: 00002163 00000000 t0 write 0x2166 (2166) 0x2166: 00000000 0x2167: 00000000 00055554: 0000: 00012166 00000000 00000000 t0 write 0x2169 (2169) 0x2169: 00000000 00055560: 0000: 00002169 00000000 t0 write 0x2168 (2168) 0x2168: 00000000 00055568: 0000: 00002168 00000000 t0 write 0x216b (216b) 0x216b: 00000000 0x216c: 00000000 00055570: 0000: 0001216b 00000000 00000000 t0 write VPC_SO_FLUSH_WADDR_3 (216e) VPC_SO_FLUSH_WADDR_3: 0 0005557c: 0000: 0000216e 00000000 t0 write 0x216d (216d) 0x216d: 00000000 00055584: 0000: 0000216d 00000000 t0 write UNKNOWN_2156 (2156) UNKNOWN_2156: 0 0005558c: 0000: 00002156 00000000 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 18 | GROUP_ID = 1 } { ADDR_LO = 0x9ae00 } 00055594: 0000: c0014300 01000012 0009ae00 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 15 | GROUP_ID = 0 } { ADDR_LO = 0x9ae50 } 000555a0: 0000: c0014300 0000000f 0009ae50 group_id: 0 count: 15 addr: 000000000009ae50 flags: 0 0009ae50: 0000: 00002073 00000000 00002101 00000000 00002106 00000000 000021e5 00000000 0009ae70: 0020: 0001210b 00000000 00000000 00002381 00000000 000023a0 00000000 t0 write GRAS_ALPHA_CONTROL (2073) GRAS_ALPHA_CONTROL: { 0 } 0009ae50: 0000: 00002073 00000000 t0 write RB_DEPTH_CONTROL (2101) RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } 0009ae58: 0000: 00002101 00000000 t0 write RB_STENCIL_CONTROL (2106) RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } 0009ae60: 0000: 00002106 00000000 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 0009ae68: 0000: 000021e5 00000000 t0 write RB_STENCILREFMASK (210b) RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 0009ae70: 0000: 0001210b 00000000 00000000 t0 write TPL1_TP_TEX_COUNT (2381) TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } 0009ae7c: 0000: 00002381 00000000 t0 write TPL1_TP_FS_TEX_COUNT (23a0) TPL1_TP_FS_TEX_COUNT: 0 0009ae84: 0000: 000023a0 00000000 group_id: 1 count: 18 addr: 000000000009ae00 flags: 0 0009ae00: 0000: 00002200 082a0008 00002201 fcfc0081 00002203 0000fc00 0007220a 0008080f 0009ae20: 0020: 0009ac80 00000060 00000001 0000080f 0009acb0 00000030 00000001 0001228a 0009ae40: 0040: 7000411f 3000011f t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } 0009ae00: 0000: 00002200 082a0008 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } 0009ae08: 0000: 00002201 fcfc0081 t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } 0009ae10: 0000: 00002203 0000fc00 t0 write VFD_FETCH[0].INSTR_0 (220a) VFD_FETCH[0].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 | SWITCHNEXT } VFD_FETCH[0].INSTR_1: 0x9ac80 VFD_FETCH[0].INSTR_2: { SIZE = 0x60 } VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 } VFD_FETCH[0x1].INSTR_1: 0x9acb0 VFD_FETCH[0x1].INSTR_2: { SIZE = 0x30 } VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } 0009ae18: 0000: 0007220a 0008080f 0009ac80 00000060 00000001 0000080f 0009acb0 00000030 0009ae38: 0020: 00000001 t0 write VFD_DECODE[0].INSTR (228a) VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID | SWITCHNEXT } VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID } 0009ae3c: 0000: 0001228a 7000411f 3000011f group_id: 2 count: 43 addr: 000000000009ad50 flags: 0 0009ad50: 0000: 000020a1 00000000 000022f1 0001a100 000022f0 fc00fc01 00002100 00000001 0009ad70: 0020: 000021e5 00000000 000020f9 ffff0501 0000214a 00000000 00002140 42001004 0009ad90: 0040: 001922c6 0010fc04 00001e00 00000000 00000000 00000000 00000000 00000000 * 0009add0: 0080: 00000000 00000000 00fcfc00 00000008 00000000 00000000 00000000 00000000 * t0 write RB_RENDER_CONTROL (20a1) RB_RENDER_CONTROL: { 0 } 0009ad50: 0000: 000020a1 00000000 t0 write SP_FS_MRT[0].REG (22f1) SP_FS_MRT[0].REG: { REGID = r0.x | HALF_PRECISION | MRTFORMAT = RB4_R8G8B8A8_UNORM } 0009ad58: 0000: 000022f1 0001a100 t0 write SP_FS_OUTPUT_REG (22f0) SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 0009ad60: 0000: 000022f0 fc00fc01 t0 write RB_FS_OUTPUT_REG (2100) RB_FS_OUTPUT_REG: { MRT = 1 } 0009ad68: 0000: 00002100 00000001 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 0009ad70: 0000: 000021e5 00000000 t0 write RB_FS_OUTPUT (20f9) RB_FS_OUTPUT: { ENABLE_BLEND = 0x1 | INDEPENDENT_BLEND | SAMPLE_MASK = 0xffff | 0x400 } 0009ad78: 0000: 000020f9 ffff0501 t0 write VPC_VARYING_PS_REPL[0].MODE (214a) VPC_VARYING_PS_REPL[0].MODE: 0 0009ad80: 0000: 0000214a 00000000 t0 write VPC_ATTR (2140) VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 } 0009ad88: 0000: 00002140 42001004 t0 write SP_VS_PARAM_REG (22c6) SP_VS_PARAM_REG: { POSREGID = r1.x | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } SP_VS_OUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } UNKNOWN_22D7: 0xfcfc00 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 0009ad90: 0000: 001922c6 0010fc04 00001e00 00000000 00000000 00000000 00000000 00000000 * 0009add0: 0040: 00000000 00000000 00fcfc00 00000008 00000000 00000000 00000000 00000000 * group_id: 3 count: 28 addr: 000000000009ace0 flags: 0 0009ace0: 0000: 000021c4 02000001 00002141 00040400 00002001 00000000 000022c4 00200800 0009ad00: 0020: 000022c5 08000002 0000230c 00000000 00002318 00000000 00002319 00000000 0009ad20: 0040: 00002340 00000000 00002202 fcfcfcfc 00002204 0000fcfc 00002154 00000000 0009ad40: 0060: 000021e7 00000000 000021c5 00000012 t0 write PC_PRIM_VTX_CNTL (21c4) PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } 0009ace0: 0000: 000021c4 02000001 t0 write VPC_PACK (2141) VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } 0009ace8: 0000: 00002141 00040400 t0 write UNKNOWN_2001 (2001) UNKNOWN_2001: 0 0009acf0: 0000: 00002001 00000000 t0 write SP_VS_CTRL_REG0 (22c4) SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 2 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 0009acf8: 0000: 000022c4 00200800 t0 write SP_VS_CTRL_REG1 (22c5) SP_VS_CTRL_REG1: { CONSTLENGTH = 2 | INITIALOUTSTANDING = 8 } 0009ad00: 0000: 000022c5 08000002 t0 write 0x230c (230c) 0x230c: 00000000 0009ad08: 0000: 0000230c 00000000 t0 write 0x2318 (2318) 0x2318: 00000000 0009ad10: 0000: 00002318 00000000 t0 write 0x2319 (2319) 0x2319: 00000000 0009ad18: 0000: 00002319 00000000 t0 write 0x2340 (2340) 0x2340: 00000000 0009ad20: 0000: 00002340 00000000 t0 write VFD_CONTROL_2 (2202) VFD_CONTROL_2: 0xfcfcfcfc 0009ad28: 0000: 00002202 fcfcfcfc t0 write VFD_CONTROL_4 (2204) VFD_CONTROL_4: 0xfcfc 0009ad30: 0000: 00002204 0000fcfc t0 write UNKNOWN_2154 (2154) UNKNOWN_2154: 0 0009ad38: 0000: 00002154 00000000 t0 write PC_HS_PARAM (21e7) PC_HS_PARAM: { VERTICES_OUT = 0 | SPACING = EQUAL_SPACING } 0009ad40: 0000: 000021e7 00000000 t0 write PC_PRIM_VTX_CNTL2 (21c5) PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 0009ad48: 0000: 000021c5 00000012 t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = USE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x200000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 3 } draw[41] register values + 00000000 0xcc4: 00000000 + 00000004 UNKNOWN_0CC5: 0x4 + 80200000 0xd03: 80200000 !+ 00000001 HLSQ_MODE_CONTROL: 0x1 + 00000000 UNKNOWN_0E42: 0 + 00000100 VPC_DEBUG_ECO_CONTROL: 0x100 + 00040000 UNKNOWN_0EC2: 0x40000 !+ 0000001e SP_MODE_CONTROL: 0x1e !+ 00000028 TPL1_TP_MODE_CONTROL: 0x28 !+ 00080000 GRAS_CL_CLIP_CNTL: { 0x80000 } + 00000000 UNKNOWN_2001: 0 + 00000000 0x2002: 00000000 + 00000001 GRAS_CNTL: { IJ_PERSP } + 0007fdff GRAS_CL_GB_CLIP_ADJ: { HORZ = 511 | VERT = 511 } + 41900000 GRAS_CL_VPORT_XOFFSET_0: 18.000000 + 41800000 GRAS_CL_VPORT_XSCALE_0: 16.000000 + 41e80000 GRAS_CL_VPORT_YOFFSET_0: 29.000000 + 41800000 GRAS_CL_VPORT_YSCALE_0: 16.000000 + 3f000000 GRAS_CL_VPORT_ZOFFSET_0: 0.500000 + 3f000000 GRAS_CL_VPORT_ZSCALE_0: 0.500000 + ffc00010 GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 4092.000000 } + 00000008 GRAS_SU_POINT_SIZE: 0.500000 + 00000000 0x2072: 00000000 !+ 00000000 GRAS_ALPHA_CONTROL: { 0 } + 00000000 GRAS_SU_POLY_OFFSET_SCALE: 0.000000 + 00000000 GRAS_SU_POLY_OFFSET_OFFSET: 0.000000 + 00000000 GRAS_SU_POLY_OFFSET_CLAMP: 0.000000 + 00000000 GRAS_DEPTH_CONTROL: { FORMAT = DEPTH4_NONE } !+ 00102014 GRAS_SU_MODE_CONTROL: { FRONT_CW | LINEHALFWIDTH = 0.500000 | MSAA_ENABLE | RENDERING_PASS } !+ 00000200 GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 4 | RASTER_MODE = 0 } !+ 000d0002 GRAS_SC_SCREEN_SCISSOR_TL: { X = 2 | Y = 13 } !+ 002c0021 GRAS_SC_SCREEN_SCISSOR_BR: { X = 33 | Y = 44 } !+ 00000000 RB_RENDER_CONTROL: { 0 } !+ 00008000 RB_MSAA_CONTROL: { SAMPLES = 4 } !+ 00001200 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 4 | IJ_PERSP_PIXEL } !+ 07000c00 RB_MRT[0].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0x7 } !+ 0010029a RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB4_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_ALWAYS | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 1024 } !+ 00000000 RB_MRT[0].BASE: 0 !+ 00000200 RB_MRT[0].CONTROL3: { STRIDE = 64 } + 00000000 RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } + 00000e00 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } !+ ffff0501 RB_FS_OUTPUT: { ENABLE_BLEND = 0x1 | INDEPENDENT_BLEND | SAMPLE_MASK = 0xffff | 0x400 } + 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } + 00000001 RB_FS_OUTPUT_REG: { MRT = 1 } + 00000000 RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } + 00000000 RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTH4_NONE | DEPTH_BASE = 0 } + 00000000 RB_DEPTH_PITCH: 0 + 00000000 RB_DEPTH_PITCH2: 0 + 00000000 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } + 00000000 RB_STENCIL_INFO: { STENCIL_BASE = 0 } + 00000000 RB_STENCIL_PITCH: 0 + 00000000 0x210a: 00000000 + 00000000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } + 00000000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } !+ 42001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 } + 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } !+ 00000000 VPC_VARYING_INTERP[0].MODE: 0 !+ 00000000 VPC_VARYING_PS_REPL[0].MODE: 0 + 00000000 UNKNOWN_2152: 0 + 00000000 UNKNOWN_2153: 0 + 00000000 UNKNOWN_2154: 0 + 00000000 UNKNOWN_2155: 0 + 00000000 UNKNOWN_2156: 0 + 00000000 0x215c: 00000000 + 00000000 0x215d: 00000000 + 00000000 0x215e: 00000000 + 00000000 0x215f: 00000000 + 00000000 0x2161: 00000000 + 00000000 0x2162: 00000000 + 00000000 0x2163: 00000000 + 00000000 0x2164: 00000000 + 00000000 0x2166: 00000000 + 00000000 0x2167: 00000000 + 00000000 0x2168: 00000000 + 00000000 0x2169: 00000000 + 00000000 0x216b: 00000000 + 00000000 0x216c: 00000000 + 00000000 0x216d: 00000000 + 00000000 VPC_SO_FLUSH_WADDR_3: 0 !+ 0000001f UNKNOWN_21C3: 0x1f !+ 02000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + ffffffff PC_RESTART_INDEX: 0xffffffff + 00000000 PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } + 00000001 UNKNOWN_21E6: 0x1 + 00000000 PC_HS_PARAM: { VERTICES_OUT = 0 | SPACING = EQUAL_SPACING } !+ 082a0008 VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } !+ fcfc0081 VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } + fcfcfcfc VFD_CONTROL_2: 0xfcfcfcfc !+ 0000fc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } + 0000fcfc VFD_CONTROL_4: 0xfcfc + 00000000 VFD_INDEX_OFFSET: 0 + 00000000 UNKNOWN_2209: 0 + 0008080f VFD_FETCH[0].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 | SWITCHNEXT } !+ 0009ac80 VFD_FETCH[0].INSTR_1: 0x9ac80 + 00000060 VFD_FETCH[0].INSTR_2: { SIZE = 0x60 } + 00000001 VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } + 0000080f VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 } !+ 0009acb0 VFD_FETCH[0x1].INSTR_1: 0x9acb0 + 00000030 VFD_FETCH[0x1].INSTR_2: { SIZE = 0x30 } + 00000001 VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } + 7000411f VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID | SWITCHNEXT } + 3000011f VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID } + 00060010 SP_SP_CTRL_REG: { 0x60010 } + 000005c3 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } !+ 00200800 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 2 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } !+ 08000002 SP_VS_CTRL_REG1: { CONSTLENGTH = 2 | INITIALOUTSTANDING = 8 } !+ 0010fc04 SP_VS_PARAM_REG: { POSREGID = r1.x | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } !+ 00001e00 SP_VS_OUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00fcfc00 UNKNOWN_22D7: 0xfcfc00 + 00000008 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } !+ 00049000 SP_VS_OBJ_START: 0x49000 00049000: 0000: 00000000 13000000 00000000 00000000 00000000 00000000 00000000 00000000 * :0:0000:0000[13000000x_00000000x] (sy)end :0:0001:0001[00000000x_00000000x] nop :0:0002:0002[00000000x_00000000x] nop :0:0003:0003[00000000x_00000000x] nop :0:0004:0004[00000000x_00000000x] nop Stats: - shaderdb: 5 instr, 4 nops, 1 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 0 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 0 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) !+ 00000001 SP_VS_LENGTH_REG: 1 !+ 00340412 SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE } !+ 80100002 SP_FS_CTRL_REG1: { CONSTLENGTH = 2 | VARYING | 0x80000000 } !+ 7e020000 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } !+ 00046000 SP_FS_OBJ_START: 0x46000 00046000: 0000: 00002000 5730cb00 00000000 03000000 00000000 00000000 00000000 00000000 * :2:0000:0000[5730cb00x_00002000x] (sy)(rpt3)bary.f (ei)hr0.x, (r)0, r0.x :0:0001:0004[03000000x_00000000x] end :0:0002:0005[00000000x_00000000x] nop :0:0003:0006[00000000x_00000000x] nop :0:0004:0007[00000000x_00000000x] nop :0:0005:0008[00000000x_00000000x] nop Stats: - shaderdb: 9 instr, 4 nops, 5 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 1 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 4 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) + 00000001 SP_FS_LENGTH_REG: 1 !+ fc00fc01 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r63.x } !+ 0001a100 SP_FS_MRT[0].REG: { REGID = r0.x | HALF_PRECISION | MRTFORMAT = RB4_R8G8B8A8_UNORM } + 00000000 0x230c: 00000000 + 7e020000 SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } + 00000000 SP_HS_OBJ_START: 0 + 00000000 0x2318: 00000000 + 00000000 0x2319: 00000000 + 7e020000 SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } + 00000000 SP_DS_OBJ_START: 0 + 00000000 0x2340: 00000000 + 7e020000 SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } + 00000000 SP_GS_OBJ_START: 0 + 00000808 TPL1_TP_TEX_OFFSET: 0x808 + 00000000 TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } !+ 00000002 0x2382: 00000002 !+ 00000000 TPL1_TP_FS_TEX_COUNT: 0 !+ 080604f0 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0x600a0 } !+ fcfc1108 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x1008 } !+ fff3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } + fcfcfc00 HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } !+ 00fcfc00 HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r0.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } !+ 01010002 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 2 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 1 } !+ 017f0202 HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 2 | CONSTOBJECTOFFSET = 2 | ENABLED | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 } !+ 007e0200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } !+ 007e0200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } !+ 007e0200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } !+ 00000003 HLSQ_UPDATE_CONTROL: 0x3 000555ac: 0000: c0023800 00200984 00000001 00000003 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 18 | GROUP_ID = 1 } { ADDR_LO = 0x9afc0 } 000555bc: 0000: c0014300 01000012 0009afc0 group_id: 1 count: 18 addr: 000000000009afc0 flags: 0 0009afc0: 0000: 00002200 082a0008 00002201 fcfc0081 00002203 0000fc00 0007220a 0008080f 0009afe0: 0020: 0009af60 00000060 00000001 0000080f 0009af90 00000030 00000001 0001228a 0009b000: 0040: 7000411f 3000011f t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } 0009afc0: 0000: 00002200 082a0008 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } 0009afc8: 0000: 00002201 fcfc0081 t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } 0009afd0: 0000: 00002203 0000fc00 t0 write VFD_FETCH[0].INSTR_0 (220a) VFD_FETCH[0].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 | SWITCHNEXT } VFD_FETCH[0].INSTR_1: 0x9af60 VFD_FETCH[0].INSTR_2: { SIZE = 0x60 } VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 } VFD_FETCH[0x1].INSTR_1: 0x9af90 VFD_FETCH[0x1].INSTR_2: { SIZE = 0x30 } VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } 0009afd8: 0000: 0007220a 0008080f 0009af60 00000060 00000001 0000080f 0009af90 00000030 0009aff8: 0020: 00000001 t0 write VFD_DECODE[0].INSTR (228a) VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID | SWITCHNEXT } VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID } 0009affc: 0000: 0001228a 7000411f 3000011f t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = USE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x200000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 3 } draw[42] register values + 082a0008 VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } + fcfc0081 VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } + 0000fc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } + 0008080f VFD_FETCH[0].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 | SWITCHNEXT } !+ 0009af60 VFD_FETCH[0].INSTR_1: 0x9af60 + 00000060 VFD_FETCH[0].INSTR_2: { SIZE = 0x60 } + 00000001 VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } + 0000080f VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 } !+ 0009af90 VFD_FETCH[0x1].INSTR_1: 0x9af90 + 00000030 VFD_FETCH[0x1].INSTR_2: { SIZE = 0x30 } + 00000001 VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } + 7000411f VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID | SWITCHNEXT } + 3000011f VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID } 000555c8: 0000: c0023800 00200984 00000001 00000003 0016b094: 0000: c0013f00 00055328 000000ac t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 0016b0a0: 0000: c0014300 00040000 00000000 t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:00171ee0 ibsize:00000046 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00171ee0: 0000: c0002600 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x4 00171ee8: 0000: 00000ec3 00000004 t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x68 00171ef0: 0000: 00000f03 00000068 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00171ef8: 0000: c0002600 00000000 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } 00171f00: 0000: 000023c0 080004f0 t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = 0x1d } event (null) 00171f08: 0000: c0004600 0000001d t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = FACENESS_FLUSH } event FACENESS_FLUSH 00171f10: 0000: c0004600 0000001c t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00171f18: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0 00171f20: 0000: 00000cc6 00000000 t0 write UNKNOWN_0E42 (0e42) UNKNOWN_0E42: 0 00171f28: 0000: 00000e42 00000000 t0 write HLSQ_MODE_CONTROL (0e05) HLSQ_MODE_CONTROL: 0x2 00171f30: 0000: 00000e05 00000002 t0 write UNKNOWN_0CC5 (0cc5) UNKNOWN_0CC5: 0x4 00171f38: 0000: 00000cc5 00000004 t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x7 00171f40: 0000: 000023db 00000007 t0 write VFD_CONTROL_2 (2202) VFD_CONTROL_2: 0xfcfcfcfc 00171f48: 0000: 00002202 fcfcfcfc t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } 00171f50: 0000: 00002203 fcfcfc00 t0 write VFD_CONTROL_4 (2204) VFD_CONTROL_4: 0xfcfc 00171f58: 0000: 00002204 0000fcfc t0 write VFD_INDEX_OFFSET (2208) VFD_INDEX_OFFSET: 0 00171f60: 0000: 00002208 00000000 t0 write UNKNOWN_2209 (2209) UNKNOWN_2209: 0 00171f68: 0000: 00002209 00000000 t0 write UNKNOWN_2152 (2152) UNKNOWN_2152: 0 UNKNOWN_2153: 0 00171f70: 0000: 00012152 00000000 00000000 t0 write UNKNOWN_2156 (2156) UNKNOWN_2156: 0 00171f7c: 0000: 00002156 00000000 t0 write UNKNOWN_2154 (2154) UNKNOWN_2154: 0 00171f84: 0000: 00002154 00000000 t0 write UNKNOWN_2155 (2155) UNKNOWN_2155: 0 00171f8c: 0000: 00002155 00000000 t0 write UNKNOWN_21C3 (21c3) UNKNOWN_21C3: 0x1d 00171f94: 0000: 000021c3 0000001d t0 write PC_PRIM_VTX_CNTL2 (21c5) PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 00171f9c: 0000: 000021c5 00000012 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 00171fa4: 0000: 000021e5 00000000 t0 write GRAS_SU_MODE_CONTROL (2078) GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } 00171fac: 0000: 00002078 00000000 t0 write UNKNOWN_2001 (2001) UNKNOWN_2001: 0 00171fb4: 0000: 00002001 00000000 t0 write GRAS_CNTL (2003) GRAS_CNTL: { IJ_PERSP } 00171fbc: 0000: 00002003 00000001 t0 write GRAS_CL_CLIP_CNTL (2000) GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } 00171fc4: 0000: 00002000 00188000 t0 write TPL1_TP_TEX_COUNT (2381) TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } 00171fcc: 0000: 00002381 00000000 t0 write TPL1_TP_FS_TEX_COUNT (23a0) TPL1_TP_FS_TEX_COUNT: 0x3 00171fd4: 0000: 000023a0 00000003 t0 write RB_ALPHA_CONTROL (20f8) RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } 00171fdc: 0000: 000020f8 00000e00 t0 write RB_RENDER_COMPONENTS (20fb) RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } 00171fe4: 0000: 000020fb 0000000f t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 00171fec: 0000: c0014300 00040000 00000000 0016b0ac: 0000: c0013f00 00171ee0 00000046 t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:001f9000 ibsize:000000b1 t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } 001f9000: 0000: 00002200 000a0000 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } 001f9008: 0000: 00002201 fc030000 t0 write SP_INSTR_CACHE_CTRL (22c1) SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } 001f9010: 0000: 000022c1 000005c3 t0 write HLSQ_CONTROL_1_REG (23c1) HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } 001f9018: 0000: 000023c1 fcfc0120 t0 write HLSQ_CONTROL_2_REG (23c2) HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 001f9020: 0000: 000023c2 27f3f3f0 t0 write HLSQ_VS_CONTROL_REG (23c5) HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } 001f9028: 0000: 000023c5 02010042 t0 write HLSQ_FS_CONTROL_REG (23c6) HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 001f9030: 0000: 000023c6 0041423e t0 write HLSQ_HS_CONTROL_REG (23c7) HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 001f9038: 0000: 000023c7 00404200 t0 write HLSQ_DS_CONTROL_REG (23c8) HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 001f9040: 0000: 000023c8 00404200 t0 write HLSQ_GS_CONTROL_REG (23c9) HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 001f9048: 0000: 000023c9 00404200 t0 write HLSQ_CS_CONTROL_REG (23ca) HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } 001f9050: 0000: 000023ca 00004200 t0 write SP_SP_CTRL_REG (22c0) SP_SP_CTRL_REG: { 0x60010 } 001f9058: 0000: 000022c0 00060010 t0 write UNKNOWN_21E6 (21e6) UNKNOWN_21E6: 0x1 001f9060: 0000: 000021e6 00000001 t0 write SP_VS_CTRL_REG0 (22c4) SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 001f9068: 0000: 000022c4 00200c10 t0 write SP_VS_CTRL_REG1 (22c5) SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } 001f9070: 0000: 000022c5 01000042 t0 write VPC_ATTR (2140) VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | 0x40000000 } 001f9078: 0000: 00002140 40001004 t0 write VPC_PACK (2141) VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } 001f9080: 0000: 00002141 00040400 t0 write PC_PRIM_VTX_CNTL (21c4) PC_PRIM_VTX_CNTL: { VAROUT = 1 } 001f9088: 0000: 000021c4 00000001 t0 write SP_VS_PARAM_REG (22c6) SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } UNKNOWN_22D7: 0xfcfc00 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 001f9090: 0000: 001922c6 0010fc03 00001e03 00000000 00000000 00000000 00000000 00000000 * 001f90d0: 0040: 00000000 00000000 00fcfc00 00000008 00000000 00000000 00000000 00000000 * t0 write SP_VS_OBJ_OFFSET_REG (22e0) SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 001f90fc: 0000: 000022e0 00000000 t0 write SP_VS_OBJ_START (22e1) SP_VS_OBJ_START: 0x1 001f9104: 0000: 000022e1 00000001 t0 write SP_VS_LENGTH_REG (22e5) SP_VS_LENGTH_REG: 2 001f910c: 0000: 000022e5 00000002 t3 opcode: CP_LOAD_STATE4 (30) (67 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } :2:0000:0000[56d81803x_20020003x] (sy)(ss)(nop3) shl.b r0.w, r0.w, 2 :1:0001:0004[20150000x_00000003x] cov.s32s16 hr0.x, r0.w :0:0002:0005[00000200x_00000000x] (rpt2)nop :1:0003:0008[201100f4x_00000000x] mova a0.x, hr0.x :0:0004:0009[00000500x_00000000x] (rpt5)nop :1:0005:0015[20154003x_00000c20x] mov.s32s32 r0.w, c :1:0006:0016[20154004x_00000c21x] mov.s32s32 r1.x, c :1:0007:0017[20154005x_00000c22x] mov.s32s32 r1.y, c :1:0008:0018[20156006x_00000c23x] (ul)mov.s32s32 r1.z, c :0:0009:0019[03000000x_00000000x] end :2:0010:0020[46f00007x_20050000x] shr.b r1.w, r0.x, 5 :2:0011:0021[43980008x_201f0000x] (nop2) and.b r2.x, r0.x, 31 :2:0012:0024[43980807x_201f0007x] (nop3) and.b r1.w, r1.w, 31 :2:0013:0028[46100807x_20100007x] (nop1) mul.u24 r1.w, r1.w, 16 :3:0014:0030[62040007x_00071014x] mad.u24 r1.w, c5.x, r2.x, r1.w :0:0015:0031[00000500x_00000000x] (rpt5)nop :6:0016:0037[c2c60f00x_04800006x] stlw.u32 l[r1.w], r0.w, 4 :0:0017:0038[04800000x_00000000x] chmask :0:0018:0039[05000000x_00000000x] chsh Stats: - shaderdb: 40 instr, 24 nops, 16 non-nops, 5 mov, 1 cov - shaderdb: 0 last-baryf, 0 half, 2 full, 5 constlen - shaderdb: 27 cat0, 6 cat1, 5 cat2, 1 cat3, 0 cat4, 0 cat5, 1 cat6, 0 cat7 - shaderdb: 0 sstall, 1 (ss), 1 (sy) 001f9114: 0000: c0413000 00a00000 00000000 20020003 56d81803 00000003 20150000 00000000 001f9134: 0020: 00000200 00000000 201100f4 00000000 00000500 00000c20 20154003 00000c21 001f9154: 0040: 20154004 00000c22 20154005 00000c23 20156006 00000000 03000000 20050000 001f9174: 0060: 46f00007 201f0000 43980008 201f0007 43980807 20100007 46100807 00071014 001f9194: 0080: 62040007 00000000 00000500 04800006 c2c60f00 00000000 04800000 00000000 001f91b4: 00a0: 05000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 * t0 write GRAS_SC_CONTROL (207b) GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = 0 | MSAA_DISABLE | RASTER_MODE = 0 } 001f9220: 0000: 0000207b 00000808 t0 write RB_MSAA_CONTROL (20a2) RB_MSAA_CONTROL: { DISABLE | SAMPLES = 0 } 001f9228: 0000: 000020a2 00001000 t0 write RB_RENDER_CONTROL (20a1) RB_RENDER_CONTROL: { DISABLE_COLOR_PIPE | 0x2 } 001f9230: 0000: 000020a1 00000022 t0 write RB_DEPTH_CONTROL (2101) RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } 001f9238: 0000: 00002101 00000000 t0 write GRAS_ALPHA_CONTROL (2073) GRAS_ALPHA_CONTROL: { 0x2 } 001f9240: 0000: 00002073 00000002 t0 write RB_STENCIL_CONTROL (2106) RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } 001f9248: 0000: 00002106 00000000 t0 write RB_COPY_CONTROL (20fc) RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_FOUR | MODE = RB_COPY_DEPTH_STENCIL | FASTCLEAR = 0 | GMEM_BASE = 0 } RB_COPY_DEST_BASE: { BASE = 0x4f000 } RB_COPY_DEST_PITCH: { PITCH = 256 } RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_DISABLE | COMPONENT_ENABLE = 0xf | ENDIAN = ENDIAN_NONE | TILE = TILE4_3 } 001f9250: 0000: 000320fc 00000052 0004f000 00000008 0303c068 t0 write UNKNOWN_20EF (20ef) UNKNOWN_20EF: 0 001f9264: 0000: 000020ef 00000000 t0 write GRAS_SC_SCREEN_SCISSOR_TL (207c) GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } 001f926c: 0000: 0001207c 00000000 003f003f t0 write RB_FRAME_BUFFER_DIMENSION (0ce0) RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } 001f9278: 0000: 00000ce0 00400040 t0 write 0xce1 (0ce1) 0xce1: 00000000 001f9280: 0000: 00000ce1 00000000 t3 opcode: CP_LOAD_STATE4 (30) (11 dwords) { DST_OFF = 8 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } 001f9294: 0.000000 0.000000 1.000000 1.000000 64.000000 64.000000 1.000000 1.000000 001f9294: 0000: 00000000 00000000 3f800000 3f800000 42800000 42800000 3f800000 3f800000 001f9288: 0000: c0093000 00a00008 00000001 00000000 00000000 3f800000 3f800000 42800000 001f92a8: 0020: 42800000 3f800000 3f800000 t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x80000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 2 } draw[43] register values + 00000004 UNKNOWN_0CC5: 0x4 + 00000000 UNKNOWN_0CC6: 0 + 00400040 RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } + 00000000 0xce1: 00000000 !+ 00000002 HLSQ_MODE_CONTROL: 0x2 + 00000000 UNKNOWN_0E42: 0 !+ 00000004 SP_MODE_CONTROL: 0x4 !+ 00000068 TPL1_TP_MODE_CONTROL: 0x68 !+ 00188000 GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } + 00000000 UNKNOWN_2001: 0 + 00000001 GRAS_CNTL: { IJ_PERSP } !+ 00000002 GRAS_ALPHA_CONTROL: { 0x2 } !+ 00000000 GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } !+ 00000808 GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = 0 | MSAA_DISABLE | RASTER_MODE = 0 } !+ 00000000 GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } !+ 003f003f GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } !+ 00000022 RB_RENDER_CONTROL: { DISABLE_COLOR_PIPE | 0x2 } !+ 00001000 RB_MSAA_CONTROL: { DISABLE | SAMPLES = 0 } + 00000000 UNKNOWN_20EF: 0 + 00000e00 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } + 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } !+ 00000052 RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_FOUR | MODE = RB_COPY_DEPTH_STENCIL | FASTCLEAR = 0 | GMEM_BASE = 0 } + 0004f000 RB_COPY_DEST_BASE: { BASE = 0x4f000 } + 00000008 RB_COPY_DEST_PITCH: { PITCH = 256 } !+ 0303c068 RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_DISABLE | COMPONENT_ENABLE = 0xf | ENDIAN = ENDIAN_NONE | TILE = TILE4_3 } + 00000000 RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } + 00000000 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } !+ 40001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | 0x40000000 } + 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } + 00000000 UNKNOWN_2152: 0 + 00000000 UNKNOWN_2153: 0 + 00000000 UNKNOWN_2154: 0 + 00000000 UNKNOWN_2155: 0 + 00000000 UNKNOWN_2156: 0 !+ 0000001d UNKNOWN_21C3: 0x1d !+ 00000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 } + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + 00000000 PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } + 00000001 UNKNOWN_21E6: 0x1 !+ 000a0000 VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } !+ fc030000 VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } + fcfcfcfc VFD_CONTROL_2: 0xfcfcfcfc !+ fcfcfc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } + 0000fcfc VFD_CONTROL_4: 0xfcfc + 00000000 VFD_INDEX_OFFSET: 0 + 00000000 UNKNOWN_2209: 0 + 00060010 SP_SP_CTRL_REG: { 0x60010 } + 000005c3 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } !+ 00200c10 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } !+ 01000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } !+ 0010fc03 SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } !+ 00001e03 SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00fcfc00 UNKNOWN_22D7: 0xfcfc00 + 00000008 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } !+ 00000001 SP_VS_OBJ_START: 0x1 !+ 00000002 SP_VS_LENGTH_REG: 2 + 00000000 TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } !+ 00000003 TPL1_TP_FS_TEX_COUNT: 0x3 !+ 080004f0 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } !+ fcfc0120 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } !+ 27f3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } !+ 02010042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } !+ 0041423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } !+ 00404200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } !+ 00404200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } !+ 00404200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00004200 HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } !+ 00000007 HLSQ_UPDATE_CONTROL: 0x7 001f92b4: 0000: c0023800 00080888 00000001 00000002 0016b0b8: 0000: c0013f00 001f9000 000000b1 t3 opcode: (null) (1d) (2 dwords) 0016b0c4: 0000: c0001d00 00000000 ############################################################ vertices: 0 ############################################################ cmdstream: 8 dwords t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:000555d8 ibsize:00000155 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 000555d8: 0000: c0002600 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x4 000555e0: 0000: 00000ec3 00000004 t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x68 000555e8: 0000: 00000f03 00000068 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 000555f0: 0000: c0002600 00000000 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } 000555f8: 0000: 000023c0 080004f0 t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = 0x1d } event (null) 00055600: 0000: c0004600 0000001d t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = FACENESS_FLUSH } event FACENESS_FLUSH 00055608: 0000: c0004600 0000001c t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00055610: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0 00055618: 0000: 00000cc6 00000000 t0 write UNKNOWN_0E42 (0e42) UNKNOWN_0E42: 0 00055620: 0000: 00000e42 00000000 t0 write HLSQ_MODE_CONTROL (0e05) HLSQ_MODE_CONTROL: 0x2 00055628: 0000: 00000e05 00000002 t0 write UNKNOWN_0CC5 (0cc5) UNKNOWN_0CC5: 0x4 00055630: 0000: 00000cc5 00000004 t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x7 00055638: 0000: 000023db 00000007 t0 write VFD_CONTROL_2 (2202) VFD_CONTROL_2: 0xfcfcfcfc 00055640: 0000: 00002202 fcfcfcfc t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } 00055648: 0000: 00002203 fcfcfc00 t0 write VFD_CONTROL_4 (2204) VFD_CONTROL_4: 0xfcfc 00055650: 0000: 00002204 0000fcfc t0 write VFD_INDEX_OFFSET (2208) VFD_INDEX_OFFSET: 0 00055658: 0000: 00002208 00000000 t0 write UNKNOWN_2209 (2209) UNKNOWN_2209: 0 00055660: 0000: 00002209 00000000 t0 write UNKNOWN_2152 (2152) UNKNOWN_2152: 0 UNKNOWN_2153: 0 00055668: 0000: 00012152 00000000 00000000 t0 write UNKNOWN_2156 (2156) UNKNOWN_2156: 0 00055674: 0000: 00002156 00000000 t0 write UNKNOWN_2154 (2154) UNKNOWN_2154: 0 0005567c: 0000: 00002154 00000000 t0 write UNKNOWN_2155 (2155) UNKNOWN_2155: 0 00055684: 0000: 00002155 00000000 t0 write UNKNOWN_21C3 (21c3) UNKNOWN_21C3: 0x1d 0005568c: 0000: 000021c3 0000001d t0 write PC_PRIM_VTX_CNTL2 (21c5) PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 00055694: 0000: 000021c5 00000012 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 0005569c: 0000: 000021e5 00000000 t0 write GRAS_SU_MODE_CONTROL (2078) GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } 000556a4: 0000: 00002078 00000000 t0 write UNKNOWN_2001 (2001) UNKNOWN_2001: 0 000556ac: 0000: 00002001 00000000 t0 write GRAS_CNTL (2003) GRAS_CNTL: { IJ_PERSP } 000556b4: 0000: 00002003 00000001 t0 write GRAS_CL_CLIP_CNTL (2000) GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } 000556bc: 0000: 00002000 00188000 t0 write TPL1_TP_TEX_COUNT (2381) TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } 000556c4: 0000: 00002381 00000000 t0 write TPL1_TP_FS_TEX_COUNT (23a0) TPL1_TP_FS_TEX_COUNT: 0x3 000556cc: 0000: 000023a0 00000003 t0 write RB_ALPHA_CONTROL (20f8) RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } 000556d4: 0000: 000020f8 00000e00 t0 write RB_RENDER_COMPONENTS (20fb) RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } 000556dc: 0000: 000020fb 0000000f t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 000556e4: 0000: c0014300 00040000 00000000 t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } 000556f0: 0000: 00002200 000a0000 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } 000556f8: 0000: 00002201 fc030000 t0 write SP_INSTR_CACHE_CTRL (22c1) SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } 00055700: 0000: 000022c1 000005c3 t0 write HLSQ_CONTROL_1_REG (23c1) HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } 00055708: 0000: 000023c1 fcfc0120 t0 write HLSQ_CONTROL_2_REG (23c2) HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 00055710: 0000: 000023c2 27f3f3f0 t0 write HLSQ_VS_CONTROL_REG (23c5) HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } 00055718: 0000: 000023c5 02010042 t0 write HLSQ_FS_CONTROL_REG (23c6) HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 1 } 00055720: 0000: 000023c6 0141423e t0 write HLSQ_HS_CONTROL_REG (23c7) HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00055728: 0000: 000023c7 00404200 t0 write HLSQ_DS_CONTROL_REG (23c8) HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00055730: 0000: 000023c8 00404200 t0 write HLSQ_GS_CONTROL_REG (23c9) HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00055738: 0000: 000023c9 00404200 t0 write HLSQ_CS_CONTROL_REG (23ca) HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } 00055740: 0000: 000023ca 00004200 t0 write SP_SP_CTRL_REG (22c0) SP_SP_CTRL_REG: { 0x60010 } 00055748: 0000: 000022c0 00060010 t0 write UNKNOWN_21E6 (21e6) UNKNOWN_21E6: 0x1 00055750: 0000: 000021e6 00000001 t0 write SP_VS_CTRL_REG0 (22c4) SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 00055758: 0000: 000022c4 00200c10 t0 write SP_VS_CTRL_REG1 (22c5) SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } 00055760: 0000: 000022c5 01000042 t0 write VPC_ATTR (2140) VPC_ATTR: { TOTALATTR = 8 | THRDASSIGN = 1 | ENABLE | 0x40000000 } 00055768: 0000: 00002140 42001008 t0 write VPC_PACK (2141) VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 8 | NUMNONPOSVSVAR = 6 } 00055770: 0000: 00002141 00060800 t0 write PC_PRIM_VTX_CNTL (21c4) PC_PRIM_VTX_CNTL: { VAROUT = 1 } 00055778: 0000: 000021c4 00000001 t0 write SP_VS_PARAM_REG (22c6) SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 2 } SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r1.w | B_COMPMASK = 0x3 } SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } UNKNOWN_22D7: 0xfcfc00 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 12 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 00055780: 0000: 001922c6 0020fc03 06071e03 00000000 00000000 00000000 00000000 00000000 * 000557c0: 0040: 00000000 00000000 00fcfc00 00000c08 00000000 00000000 00000000 00000000 * t0 write SP_VS_OBJ_OFFSET_REG (22e0) SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 000557ec: 0000: 000022e0 00000000 t0 write SP_VS_OBJ_START (22e1) SP_VS_OBJ_START: 0x1 000557f4: 0000: 000022e1 00000001 t0 write SP_VS_LENGTH_REG (22e5) SP_VS_LENGTH_REG: 2 000557fc: 0000: 000022e5 00000002 t3 opcode: CP_LOAD_STATE4 (30) (67 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } :2:0000:0000[56d81803x_20020003x] (sy)(ss)(nop3) shl.b r0.w, r0.w, 2 :1:0001:0004[20150000x_00000003x] cov.s32s16 hr0.x, r0.w :0:0002:0005[00000200x_00000000x] (rpt2)nop :1:0003:0008[201100f4x_00000000x] mova a0.x, hr0.x :0:0004:0009[00000500x_00000000x] (rpt5)nop :1:0005:0015[20154003x_00000c20x] mov.s32s32 r0.w, c :1:0006:0016[20154004x_00000c21x] mov.s32s32 r1.x, c :1:0007:0017[20154007x_00000c22x] mov.s32s32 r1.w, c :1:0008:0018[20156008x_00000c23x] (ul)mov.s32s32 r2.x, c :1:0009:0019[20554005x_00000000x] mov.s32s32 r1.y, 0 :1:0010:0020[20554006x_3f800000x] mov.s32s32 r1.z, 1065353216 :0:0011:0021[03000000x_00000000x] end :2:0012:0022[46f00009x_20050000x] shr.b r2.y, r0.x, 5 :2:0013:0023[4398000ax_201f0000x] (nop2) and.b r2.z, r0.x, 31 :2:0014:0026[43980809x_201f0009x] (nop3) and.b r2.y, r2.y, 31 :2:0015:0030[46100809x_20180009x] (nop1) mul.u24 r2.y, r2.y, 24 :3:0016:0032[62050009x_00091014x] mad.u24 r2.y, c5.x, r2.z, r2.y :0:0017:0033[00000500x_00000000x] (rpt5)nop :6:0018:0039[c2c61300x_04800006x] stlw.u32 l[r2.y], r0.w, 4 :6:0019:0040[c2c61310x_0280000ex] stlw.u32 l[r2.y+16], r1.w, 2 :0:0020:0041[04800000x_00000000x] chmask :0:0021:0042[05000000x_00000000x] chsh Stats: - shaderdb: 43 instr, 24 nops, 19 non-nops, 7 mov, 1 cov - shaderdb: 0 last-baryf, 0 half, 3 full, 5 constlen - shaderdb: 27 cat0, 8 cat1, 5 cat2, 1 cat3, 0 cat4, 0 cat5, 2 cat6, 0 cat7 - shaderdb: 0 sstall, 1 (ss), 1 (sy) 00055804: 0000: c0413000 00a00000 00000000 20020003 56d81803 00000003 20150000 00000000 00055824: 0020: 00000200 00000000 201100f4 00000000 00000500 00000c20 20154003 00000c21 00055844: 0040: 20154004 00000c22 20154007 00000c23 20156008 00000000 20554005 3f800000 00055864: 0060: 20554006 00000000 03000000 20050000 46f00009 201f0000 4398000a 201f0009 00055884: 0080: 43980809 20180009 46100809 00091014 62050009 00000000 00000500 04800006 000558a4: 00a0: c2c61300 0280000e c2c61310 00000000 04800000 00000000 05000000 00000000 * t0 write HLSQ_CONTROL_3_REG (23c3) HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } 00055910: 0000: 000023c3 fcfcfc00 t0 write HLSQ_CONTROL_4_REG (23c4) HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } 00055918: 0000: 000023c4 00fcfcfc t0 write SP_FS_CTRL_REG0 (22e8) SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 0 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE | PIXLODENABLE } SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 } 00055920: 0000: 000122e8 00700402 8010003e t0 write SP_FS_OBJ_OFFSET_REG (22ea) SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 } 0005592c: 0000: 000022ea 40420000 t0 write SP_FS_OBJ_START (22eb) SP_FS_OBJ_START: 0x1 00055934: 0000: 000022eb 00000001 t0 write SP_FS_LENGTH_REG (22ef) SP_FS_LENGTH_REG: 1 0005593c: 0000: 000022ef 00000001 t0 write SP_FS_OUTPUT_REG (22f0) SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r0.x | SAMPLEMASK_REGID = r0.x } 00055944: 0000: 000022f0 00000001 t0 write VPC_VARYING_INTERP[0].MODE (2142) VPC_VARYING_INTERP[0].MODE: 0xe000 0005594c: 0000: 00002142 0000e000 t0 write RB_FS_OUTPUT_REG (2100) RB_FS_OUTPUT_REG: { MRT = 1 } 00055954: 0000: 00002100 00000001 t3 opcode: CP_LOAD_STATE4 (30) (35 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 1 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } :2:0000:0000[57309902x_00002004x] (sy)(ss)(rpt1)bary.f (ei)r0.z, (r)4, r0.x :0:0001:0002[00000500x_00000000x] (rpt5)nop :5:0002:0008[a0c01f00x_00000005x] sam (f32)(xyzw)r0.x, r0.z, s#0, t#0 :0:0003:0009[03000000x_00000000x] end :0:0004:0010[00000000x_00000000x] nop :0:0005:0011[00000000x_00000000x] nop :0:0006:0012[00000000x_00000000x] nop :0:0007:0013[00000000x_00000000x] nop Stats: - shaderdb: 14 instr, 10 nops, 4 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 0 half, 1 full, 0 constlen - shaderdb: 11 cat0, 0 cat1, 2 cat2, 0 cat3, 0 cat4, 1 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 1 (ss), 1 (sy) 0005595c: 0000: c0213000 00700000 00000000 00002004 57309902 00000000 00000500 00000005 0005597c: 0020: a0c01f00 00000000 03000000 00000000 00000000 00000000 00000000 00000000 * t0 write RB_FS_OUTPUT (20f9) RB_FS_OUTPUT: { ENABLE_BLEND = 0 | SAMPLE_MASK = 0xffff } 000559e8: 0000: 000020f9 ffff0000 t0 write RB_MRT[0].CONTROL (20a4) RB_MRT[0].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0xf } 000559f0: 0000: 000020a4 0f000000 t0 write RB_MRT[0x1].CONTROL (20a9) RB_MRT[0x1].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0xf } 000559f8: 0000: 000020a9 0f000000 t0 write RB_MRT[0].BLEND_CONTROL (20a8) RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } 00055a00: 0000: 000020a8 00000000 t3 opcode: CP_LOAD_STATE4 (30) (5 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_TEX | NUM_UNIT = 1 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } { XY_MAG = A4XX_TEX_NEAREST | XY_MIN = A4XX_TEX_NEAREST | WRAP_S = A4XX_TEX_CLAMP_TO_EDGE | WRAP_T = A4XX_TEX_CLAMP_TO_EDGE | WRAP_R = A4XX_TEX_CLAMP_TO_EDGE | ANISO = A4XX_TEX_ANISO_1 | LOD_BIAS = 0.000000 | 0x60000 } { COMPARE_FUNC = FUNC_LEQUAL | UNNORM_COORDS | MIPFILTER_LINEAR_FAR | MAX_LOD = 0.000000 | MIN_LOD = 0.000000 | 0x1 } 00055a14: 0000: 00060920 00000067 00055a08: 0000: c0033000 00500000 00000000 00060920 00000067 t0 write GRAS_SC_CONTROL (207b) GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 0 | RASTER_MODE = 0 } 00055a1c: 0000: 0000207b 00000000 t0 write RB_MSAA_CONTROL (20a2) RB_MSAA_CONTROL: { SAMPLES = 0 } 00055a24: 0000: 000020a2 00000000 t0 write RB_RENDER_CONTROL (20a1) RB_RENDER_CONTROL: { 0 } 00055a2c: 0000: 000020a1 00000000 t0 write 0x2382 (2382) 0x2382: 00000000 00055a34: 0000: 00002382 00000000 t0 write RB_DEPTH_CONTROL (2101) RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } 00055a3c: 0000: 00002101 00000000 t0 write GRAS_ALPHA_CONTROL (2073) GRAS_ALPHA_CONTROL: { 0 } 00055a44: 0000: 00002073 00000000 t0 write RB_STENCIL_CONTROL (2106) RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } 00055a4c: 0000: 00002106 00000000 t0 write SP_FS_MRT[0].REG (22f1) SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = RB4_R8G8B8A8_UNORM } 00055a54: 0000: 000022f1 0001a000 t0 write RB_MRT[0].BUF_INFO (20a5) RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB4_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE4_3 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 256 } RB_MRT[0].BASE: 0x166000 RB_MRT[0].CONTROL3: { STRIDE = 0 } 00055a5c: 0000: 000220a5 000400da 00166000 00000000 t3 opcode: CP_LOAD_STATE4 (30) (11 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_TEX | NUM_UNIT = 1 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } { TILED | SWIZ_X = A4XX_TEX_X | SWIZ_Y = A4XX_TEX_Y | SWIZ_Z = A4XX_TEX_Z | SWIZ_W = A4XX_TEX_W | MIPLVLS = 0 | FMT = TFMT4_8_8_8_8_UNORM | TYPE = A4XX_TEX_2D | 0x2 } { HEIGHT = 64 | WIDTH = 64 } { PITCHALIGN = 0 | PITCH = 256 | SWAP = WZYX } { LAYERSZ = 0 | DEPTH = 1 | 0x20000 } { LAYERSZ = 4096 | BASE = 0x4f000 } { 5 = 0 } { 6 = 0 } { 7 = 0 } 00055a78: 0000: 27006883 00200040 00020000 00060000 0004f001 00000000 00000000 00000000 00055a6c: 0000: c0093000 00500000 00000001 27006883 00200040 00020000 00060000 0004f001 * t0 write VPC_VARYING_PS_REPL[0].MODE (214a) VPC_VARYING_PS_REPL[0].MODE: 0x99999999 00055a98: 0000: 0000214a 99999999 t0 write GRAS_SC_SCREEN_SCISSOR_TL (207c) GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } 00055aa0: 0000: 0001207c 00000000 003f003f t0 write GRAS_SC_WINDOW_SCISSOR_BR (209c) GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 00055aac: 0000: 0001209c 003f003f 00000000 t0 write RB_FRAME_BUFFER_DIMENSION (0ce0) RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } 00055ab8: 0000: 00000ce0 00400040 t0 write 0xce1 (0ce1) 0xce1: 00000000 00055ac0: 0000: 00000ce1 00000000 t0 write RB_RENDER_CONTROL2 (20a3) RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 | IJ_PERSP_PIXEL } 00055ac8: 0000: 000020a3 00001000 t0 write RB_MODE_CONTROL (20a0) RB_MODE_CONTROL: { WIDTH = 0 | HEIGHT = 0 | 0xc00000 } 00055ad0: 0000: 000020a0 00c00000 t3 opcode: CP_LOAD_STATE4 (30) (11 dwords) { DST_OFF = 8 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } 00055ae4: 0.000000 0.000000 0.000000 0.000000 64.000000 64.000000 64.000000 64.000000 00055ae4: 0000: 00000000 00000000 00000000 00000000 42800000 42800000 42800000 42800000 00055ad8: 0000: c0093000 00a00008 00000001 00000000 00000000 00000000 00000000 42800000 00055af8: 0020: 42800000 42800000 42800000 t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x80000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 2 } draw[44] register values + 00000004 UNKNOWN_0CC5: 0x4 + 00000000 UNKNOWN_0CC6: 0 + 00400040 RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } + 00000000 0xce1: 00000000 + 00000002 HLSQ_MODE_CONTROL: 0x2 + 00000000 UNKNOWN_0E42: 0 + 00000004 SP_MODE_CONTROL: 0x4 + 00000068 TPL1_TP_MODE_CONTROL: 0x68 + 00188000 GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } + 00000000 UNKNOWN_2001: 0 + 00000001 GRAS_CNTL: { IJ_PERSP } !+ 00000000 GRAS_ALPHA_CONTROL: { 0 } + 00000000 GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } !+ 00000000 GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 0 | RASTER_MODE = 0 } + 00000000 GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } + 003f003f GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } + 003f003f GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } + 00000000 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } !+ 00c00000 RB_MODE_CONTROL: { WIDTH = 0 | HEIGHT = 0 | 0xc00000 } !+ 00000000 RB_RENDER_CONTROL: { 0 } !+ 00000000 RB_MSAA_CONTROL: { SAMPLES = 0 } !+ 00001000 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 | IJ_PERSP_PIXEL } !+ 0f000000 RB_MRT[0].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0xf } !+ 000400da RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB4_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE4_3 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 256 } !+ 00166000 RB_MRT[0].BASE: 0x166000 !+ 00000000 RB_MRT[0].CONTROL3: { STRIDE = 0 } + 00000000 RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } + 0f000000 RB_MRT[0x1].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0xf } + 00000e00 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } !+ ffff0000 RB_FS_OUTPUT: { ENABLE_BLEND = 0 | SAMPLE_MASK = 0xffff } + 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } + 00000001 RB_FS_OUTPUT_REG: { MRT = 1 } + 00000000 RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } + 00000000 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } !+ 42001008 VPC_ATTR: { TOTALATTR = 8 | THRDASSIGN = 1 | ENABLE | 0x40000000 } !+ 00060800 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 8 | NUMNONPOSVSVAR = 6 } !+ 0000e000 VPC_VARYING_INTERP[0].MODE: 0xe000 !+ 99999999 VPC_VARYING_PS_REPL[0].MODE: 0x99999999 + 00000000 UNKNOWN_2152: 0 + 00000000 UNKNOWN_2153: 0 + 00000000 UNKNOWN_2154: 0 + 00000000 UNKNOWN_2155: 0 + 00000000 UNKNOWN_2156: 0 + 0000001d UNKNOWN_21C3: 0x1d + 00000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 } + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + 00000000 PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } + 00000001 UNKNOWN_21E6: 0x1 + 000a0000 VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } + fc030000 VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } + fcfcfcfc VFD_CONTROL_2: 0xfcfcfcfc + fcfcfc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } + 0000fcfc VFD_CONTROL_4: 0xfcfc + 00000000 VFD_INDEX_OFFSET: 0 + 00000000 UNKNOWN_2209: 0 + 00060010 SP_SP_CTRL_REG: { 0x60010 } + 000005c3 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } + 00200c10 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } + 01000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } !+ 0020fc03 SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 2 } !+ 06071e03 SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r1.w | B_COMPMASK = 0x3 } + 00000000 SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00fcfc00 UNKNOWN_22D7: 0xfcfc00 !+ 00000c08 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 12 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } + 00000001 SP_VS_OBJ_START: 0x1 + 00000002 SP_VS_LENGTH_REG: 2 !+ 00700402 SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 0 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE | PIXLODENABLE } !+ 8010003e SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 } !+ 40420000 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 } !+ 00000001 SP_FS_OBJ_START: 0x1 + 00000001 SP_FS_LENGTH_REG: 1 !+ 00000001 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r0.x | SAMPLEMASK_REGID = r0.x } !+ 0001a000 SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = RB4_R8G8B8A8_UNORM } + 00000000 TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } !+ 00000000 0x2382: 00000000 + 00000003 TPL1_TP_FS_TEX_COUNT: 0x3 + 080004f0 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } + fcfc0120 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } + 27f3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } + fcfcfc00 HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } !+ 00fcfcfc HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } + 02010042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } !+ 0141423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 1 } + 00404200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00004200 HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } + 00000007 HLSQ_UPDATE_CONTROL: 0x7 00055b04: 0000: c0023800 00080888 00000001 00000002 t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = CACHE_FLUSH } event CACHE_FLUSH 00055b14: 0000: c0004600 00000006 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00055b1c: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0x8000012 00055b24: 0000: 00000cc6 08000012 00173000: 0000: c0013f00 000555d8 00000155 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 0017300c: 0000: c0014300 00040000 00000000 t3 opcode: (null) (1d) (2 dwords) 00173018: 0000: c0001d00 00000000 ############################################################ vertices: 0 ############################################################ cmdstream: 48 dwords t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 0016b000: 0000: c0002600 00000000 t0 write UCHE_INVALIDATE0 (0e8a) UCHE_INVALIDATE0: 0 UCHE_INVALIDATE1: 0x12 0016b008: 0000: 00010e8a 00000000 00000012 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 0016b014: 0000: c0002600 00000000 t0 write RB_MODE_CONTROL (20a0) RB_MODE_CONTROL: { WIDTH = 64 | HEIGHT = 64 | ENABLE_GMEM } 0016b01c: 0000: 000020a0 00010202 t0 write RB_FRAME_BUFFER_DIMENSION (0ce0) RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } 0016b024: 0000: 00000ce0 00400040 t0 write 0xce1 (0ce1) 0xce1: 00000001 0016b02c: 0000: 00000ce1 00000001 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 0016b034: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0 0016b03c: 0000: 00000cc6 00000000 t3 opcode: (null) (1d) (2 dwords) 0016b044: 0000: c0001d00 00000000 t0 write GRAS_SC_WINDOW_SCISSOR_BR (209c) GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 0016b04c: 0000: 0001209c 003f003f 00000000 t0 write RB_BIN_OFFSET (210d) RB_BIN_OFFSET: { X = 0 | Y = 0 } 0016b058: 0000: 0000210d 00000000 t0 write GRAS_SC_WINDOW_SCISSOR_BR (209c) GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 0016b060: 0000: 0001209c 003f003f 00000000 t0 write UNKNOWN_2157 (2157) UNKNOWN_2157: 0x1 0016b06c: 0000: 00002157 00000001 t3 opcode: (null) (64) (2 dwords) 0016b074: 0000: c0006400 00000001 t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:00054994 ibsize:000000f6 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00054994: 0000: c0002600 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x4 0005499c: 0000: 00000ec3 00000004 t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x68 000549a4: 0000: 00000f03 00000068 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 000549ac: 0000: c0002600 00000000 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } 000549b4: 0000: 000023c0 080004f0 t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = 0x1d } event (null) 000549bc: 0000: c0004600 0000001d t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = FACENESS_FLUSH } event FACENESS_FLUSH 000549c4: 0000: c0004600 0000001c t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 000549cc: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0 000549d4: 0000: 00000cc6 00000000 t0 write UNKNOWN_0E42 (0e42) UNKNOWN_0E42: 0 000549dc: 0000: 00000e42 00000000 t0 write HLSQ_MODE_CONTROL (0e05) HLSQ_MODE_CONTROL: 0x2 000549e4: 0000: 00000e05 00000002 t0 write UNKNOWN_0CC5 (0cc5) UNKNOWN_0CC5: 0x4 000549ec: 0000: 00000cc5 00000004 t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x7 000549f4: 0000: 000023db 00000007 t0 write VFD_CONTROL_2 (2202) VFD_CONTROL_2: 0xfcfcfcfc 000549fc: 0000: 00002202 fcfcfcfc t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } 00054a04: 0000: 00002203 fcfcfc00 t0 write VFD_CONTROL_4 (2204) VFD_CONTROL_4: 0xfcfc 00054a0c: 0000: 00002204 0000fcfc t0 write VFD_INDEX_OFFSET (2208) VFD_INDEX_OFFSET: 0 00054a14: 0000: 00002208 00000000 t0 write UNKNOWN_2209 (2209) UNKNOWN_2209: 0 00054a1c: 0000: 00002209 00000000 t0 write UNKNOWN_2152 (2152) UNKNOWN_2152: 0 UNKNOWN_2153: 0 00054a24: 0000: 00012152 00000000 00000000 t0 write UNKNOWN_2156 (2156) UNKNOWN_2156: 0 00054a30: 0000: 00002156 00000000 t0 write UNKNOWN_2154 (2154) UNKNOWN_2154: 0 00054a38: 0000: 00002154 00000000 t0 write UNKNOWN_2155 (2155) UNKNOWN_2155: 0 00054a40: 0000: 00002155 00000000 t0 write UNKNOWN_21C3 (21c3) UNKNOWN_21C3: 0x1d 00054a48: 0000: 000021c3 0000001d t0 write PC_PRIM_VTX_CNTL2 (21c5) PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 00054a50: 0000: 000021c5 00000012 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 00054a58: 0000: 000021e5 00000000 t0 write GRAS_SU_MODE_CONTROL (2078) GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } 00054a60: 0000: 00002078 00000000 t0 write UNKNOWN_2001 (2001) UNKNOWN_2001: 0 00054a68: 0000: 00002001 00000000 t0 write GRAS_CNTL (2003) GRAS_CNTL: { IJ_PERSP } 00054a70: 0000: 00002003 00000001 t0 write GRAS_CL_CLIP_CNTL (2000) GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } 00054a78: 0000: 00002000 00188000 t0 write TPL1_TP_TEX_COUNT (2381) TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } 00054a80: 0000: 00002381 00000000 t0 write TPL1_TP_FS_TEX_COUNT (23a0) TPL1_TP_FS_TEX_COUNT: 0x3 00054a88: 0000: 000023a0 00000003 t0 write RB_ALPHA_CONTROL (20f8) RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } 00054a90: 0000: 000020f8 00000e00 t0 write RB_RENDER_COMPONENTS (20fb) RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } 00054a98: 0000: 000020fb 0000000f t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 00054aa0: 0000: c0014300 00040000 00000000 t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } 00054aac: 0000: 00002200 000a0000 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } 00054ab4: 0000: 00002201 fc030000 t0 write SP_INSTR_CACHE_CTRL (22c1) SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } 00054abc: 0000: 000022c1 000005c3 t0 write HLSQ_CONTROL_1_REG (23c1) HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } 00054ac4: 0000: 000023c1 fcfc0120 t0 write HLSQ_CONTROL_2_REG (23c2) HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 00054acc: 0000: 000023c2 27f3f3f0 t0 write HLSQ_VS_CONTROL_REG (23c5) HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } 00054ad4: 0000: 000023c5 02010042 t0 write HLSQ_FS_CONTROL_REG (23c6) HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00054adc: 0000: 000023c6 0041423e t0 write HLSQ_HS_CONTROL_REG (23c7) HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00054ae4: 0000: 000023c7 00404200 t0 write HLSQ_DS_CONTROL_REG (23c8) HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00054aec: 0000: 000023c8 00404200 t0 write HLSQ_GS_CONTROL_REG (23c9) HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00054af4: 0000: 000023c9 00404200 t0 write HLSQ_CS_CONTROL_REG (23ca) HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } 00054afc: 0000: 000023ca 00004200 t0 write SP_SP_CTRL_REG (22c0) SP_SP_CTRL_REG: { 0x60010 } 00054b04: 0000: 000022c0 00060010 t0 write UNKNOWN_21E6 (21e6) UNKNOWN_21E6: 0x1 00054b0c: 0000: 000021e6 00000001 t0 write SP_VS_CTRL_REG0 (22c4) SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 00054b14: 0000: 000022c4 00200c10 t0 write SP_VS_CTRL_REG1 (22c5) SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } 00054b1c: 0000: 000022c5 01000042 t0 write VPC_ATTR (2140) VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | 0x40000000 } 00054b24: 0000: 00002140 40001004 t0 write VPC_PACK (2141) VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } 00054b2c: 0000: 00002141 00040400 t0 write PC_PRIM_VTX_CNTL (21c4) PC_PRIM_VTX_CNTL: { VAROUT = 1 } 00054b34: 0000: 000021c4 00000001 t0 write SP_VS_PARAM_REG (22c6) SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } UNKNOWN_22D7: 0xfcfc00 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 00054b3c: 0000: 001922c6 0010fc03 00001e03 00000000 00000000 00000000 00000000 00000000 * 00054b7c: 0040: 00000000 00000000 00fcfc00 00000008 00000000 00000000 00000000 00000000 * t0 write SP_VS_OBJ_OFFSET_REG (22e0) SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 00054ba8: 0000: 000022e0 00000000 t0 write SP_VS_OBJ_START (22e1) SP_VS_OBJ_START: 0x1 00054bb0: 0000: 000022e1 00000001 t0 write SP_VS_LENGTH_REG (22e5) SP_VS_LENGTH_REG: 2 00054bb8: 0000: 000022e5 00000002 t3 opcode: CP_LOAD_STATE4 (30) (67 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } :2:0000:0000[56d81803x_20020003x] (sy)(ss)(nop3) shl.b r0.w, r0.w, 2 :1:0001:0004[20150000x_00000003x] cov.s32s16 hr0.x, r0.w :0:0002:0005[00000200x_00000000x] (rpt2)nop :1:0003:0008[201100f4x_00000000x] mova a0.x, hr0.x :0:0004:0009[00000500x_00000000x] (rpt5)nop :1:0005:0015[20154003x_00000c20x] mov.s32s32 r0.w, c :1:0006:0016[20154004x_00000c21x] mov.s32s32 r1.x, c :1:0007:0017[20154005x_00000c22x] mov.s32s32 r1.y, c :1:0008:0018[20156006x_00000c23x] (ul)mov.s32s32 r1.z, c :0:0009:0019[03000000x_00000000x] end :2:0010:0020[46f00007x_20050000x] shr.b r1.w, r0.x, 5 :2:0011:0021[43980008x_201f0000x] (nop2) and.b r2.x, r0.x, 31 :2:0012:0024[43980807x_201f0007x] (nop3) and.b r1.w, r1.w, 31 :2:0013:0028[46100807x_20100007x] (nop1) mul.u24 r1.w, r1.w, 16 :3:0014:0030[62040007x_00071014x] mad.u24 r1.w, c5.x, r2.x, r1.w :0:0015:0031[00000500x_00000000x] (rpt5)nop :6:0016:0037[c2c60f00x_04800006x] stlw.u32 l[r1.w], r0.w, 4 :0:0017:0038[04800000x_00000000x] chmask :0:0018:0039[05000000x_00000000x] chsh Stats: - shaderdb: 40 instr, 24 nops, 16 non-nops, 5 mov, 1 cov - shaderdb: 0 last-baryf, 0 half, 2 full, 5 constlen - shaderdb: 27 cat0, 6 cat1, 5 cat2, 1 cat3, 0 cat4, 0 cat5, 1 cat6, 0 cat7 - shaderdb: 0 sstall, 1 (ss), 1 (sy) 00054bc0: 0000: c0413000 00a00000 00000000 20020003 56d81803 00000003 20150000 00000000 00054be0: 0020: 00000200 00000000 201100f4 00000000 00000500 00000c20 20154003 00000c21 00054c00: 0040: 20154004 00000c22 20154005 00000c23 20156006 00000000 03000000 20050000 00054c20: 0060: 46f00007 201f0000 43980008 201f0007 43980807 20100007 46100807 00071014 00054c40: 0080: 62040007 00000000 00000500 04800006 c2c60f00 00000000 04800000 00000000 00054c60: 00a0: 05000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 * t0 write GRAS_ALPHA_CONTROL (2073) GRAS_ALPHA_CONTROL: { 0x2 } 00054ccc: 0000: 00002073 00000002 t0 write GRAS_SC_CONTROL (207b) GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = 4 | MSAA_DISABLE | RASTER_MODE = 0 } 00054cd4: 0000: 0000207b 00000a08 t0 write RB_MSAA_CONTROL (20a2) RB_MSAA_CONTROL: { DISABLE | SAMPLES = 4 } 00054cdc: 0000: 000020a2 00009000 t0 write RB_RENDER_CONTROL (20a1) RB_RENDER_CONTROL: { DISABLE_COLOR_PIPE | 0x2 } 00054ce4: 0000: 000020a1 00000022 t0 write RB_CLEAR_COLOR_DW0 (20cc) RB_CLEAR_COLOR_DW0: 0xff000000 RB_CLEAR_COLOR_DW1: 0 RB_CLEAR_COLOR_DW2: 0 RB_CLEAR_COLOR_DW3: 0 00054cec: 0000: 000320cc ff000000 00000000 00000000 00000000 t0 write RB_COPY_CONTROL (20fc) RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_FOUR | MODE = RB_COPY_CLEAR | FASTCLEAR = 0xf | GMEM_BASE = 0 } RB_COPY_DEST_BASE: { BASE = 0x4f000 } RB_COPY_DEST_PITCH: { PITCH = 256 } RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_IF_ALPHA_OFF | COMPONENT_ENABLE = 0 | ENDIAN = ENDIAN_NONE | TILE = TILE4_3 } 00054d00: 0000: 000320fc 00000f22 0004f000 00000008 03000868 t0 write GRAS_SC_SCREEN_SCISSOR_TL (207c) GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } 00054d14: 0000: 0001207c 00000000 003f003f t0 write RB_FRAME_BUFFER_DIMENSION (0ce0) RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } 00054d20: 0000: 00000ce0 00400040 t0 write 0xce1 (0ce1) 0xce1: 00000000 00054d28: 0000: 00000ce1 00000000 t3 opcode: CP_LOAD_STATE4 (30) (11 dwords) { DST_OFF = 8 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } 00054d3c: 0.000000 0.000000 1.000000 1.000000 64.000000 64.000000 1.000000 1.000000 00054d3c: 0000: 00000000 00000000 3f800000 3f800000 42800000 42800000 3f800000 3f800000 00054d30: 0000: c0093000 00a00008 00000001 00000000 00000000 3f800000 3f800000 42800000 00054d50: 0020: 42800000 3f800000 3f800000 t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x80000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 2 } draw[45] register values + 00000004 UNKNOWN_0CC5: 0x4 + 00000000 UNKNOWN_0CC6: 0 + 00400040 RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } + 00000000 0xce1: 00000000 + 00000002 HLSQ_MODE_CONTROL: 0x2 + 00000000 UNKNOWN_0E42: 0 + 00000000 UCHE_INVALIDATE0: 0 + 00000012 UCHE_INVALIDATE1: 0x12 + 00000004 SP_MODE_CONTROL: 0x4 + 00000068 TPL1_TP_MODE_CONTROL: 0x68 + 00188000 GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } + 00000000 UNKNOWN_2001: 0 + 00000001 GRAS_CNTL: { IJ_PERSP } !+ 00000002 GRAS_ALPHA_CONTROL: { 0x2 } + 00000000 GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } !+ 00000a08 GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = 4 | MSAA_DISABLE | RASTER_MODE = 0 } + 00000000 GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } + 003f003f GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } + 003f003f GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } + 00000000 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } !+ 00010202 RB_MODE_CONTROL: { WIDTH = 64 | HEIGHT = 64 | ENABLE_GMEM } !+ 00000022 RB_RENDER_CONTROL: { DISABLE_COLOR_PIPE | 0x2 } !+ 00009000 RB_MSAA_CONTROL: { DISABLE | SAMPLES = 4 } + ff000000 RB_CLEAR_COLOR_DW0: 0xff000000 + 00000000 RB_CLEAR_COLOR_DW1: 0 + 00000000 RB_CLEAR_COLOR_DW2: 0 + 00000000 RB_CLEAR_COLOR_DW3: 0 + 00000e00 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } + 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } !+ 00000f22 RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_FOUR | MODE = RB_COPY_CLEAR | FASTCLEAR = 0xf | GMEM_BASE = 0 } + 0004f000 RB_COPY_DEST_BASE: { BASE = 0x4f000 } + 00000008 RB_COPY_DEST_PITCH: { PITCH = 256 } !+ 03000868 RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_IF_ALPHA_OFF | COMPONENT_ENABLE = 0 | ENDIAN = ENDIAN_NONE | TILE = TILE4_3 } + 00000000 RB_BIN_OFFSET: { X = 0 | Y = 0 } !+ 40001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | 0x40000000 } !+ 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } + 00000000 UNKNOWN_2152: 0 + 00000000 UNKNOWN_2153: 0 + 00000000 UNKNOWN_2154: 0 + 00000000 UNKNOWN_2155: 0 + 00000000 UNKNOWN_2156: 0 + 00000001 UNKNOWN_2157: 0x1 + 0000001d UNKNOWN_21C3: 0x1d + 00000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 } + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + 00000000 PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } + 00000001 UNKNOWN_21E6: 0x1 + 000a0000 VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } + fc030000 VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } + fcfcfcfc VFD_CONTROL_2: 0xfcfcfcfc + fcfcfc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } + 0000fcfc VFD_CONTROL_4: 0xfcfc + 00000000 VFD_INDEX_OFFSET: 0 + 00000000 UNKNOWN_2209: 0 + 00060010 SP_SP_CTRL_REG: { 0x60010 } + 000005c3 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } + 00200c10 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } + 01000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } !+ 0010fc03 SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } !+ 00001e03 SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00fcfc00 UNKNOWN_22D7: 0xfcfc00 !+ 00000008 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } + 00000001 SP_VS_OBJ_START: 0x1 + 00000002 SP_VS_LENGTH_REG: 2 + 00000000 TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } + 00000003 TPL1_TP_FS_TEX_COUNT: 0x3 + 080004f0 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } + fcfc0120 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } + 27f3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } + 02010042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } !+ 0041423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00004200 HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } + 00000007 HLSQ_UPDATE_CONTROL: 0x7 00054d5c: 0000: c0023800 00080888 00000001 00000002 0016b07c: 0000: c0013f00 00054994 000000f6 t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:00054d6c ibsize:00000037 t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } 00054d6c: 0000: 00002200 082a0008 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00054d74: 0000: c0002600 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x1e 00054d7c: 0000: 00000ec3 0000001e t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x28 00054d84: 0000: 00000f03 00000028 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00054d8c: 0000: c0002600 00000000 t0 write HLSQ_MODE_CONTROL (0e05) HLSQ_MODE_CONTROL: 0x1 00054d94: 0000: 00000e05 00000001 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0x600a0 } 00054d9c: 0000: 000023c0 080604f0 t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x7 00054da4: 0000: 000023db 00000007 t0 write PC_RESTART_INDEX (21c6) PC_RESTART_INDEX: 0xffffffff 00054dac: 0000: 000021c6 ffffffff t0 write UNKNOWN_21E6 (21e6) UNKNOWN_21E6: 0x1 00054db4: 0000: 000021e6 00000001 t0 write UNKNOWN_21C3 (21c3) UNKNOWN_21C3: 0x1f 00054dbc: 0000: 000021c3 0000001f t0 write TPL1_TP_TEX_OFFSET (2380) TPL1_TP_TEX_OFFSET: 0x808 00054dc4: 0000: 00002380 00000808 t0 write GRAS_SU_POINT_MINMAX (2070) GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 4092.000000 } GRAS_SU_POINT_SIZE: 0.500000 00054dcc: 0000: 00012070 ffc00010 00000008 t0 write UNKNOWN_2152 (2152) UNKNOWN_2152: 0 UNKNOWN_2153: 0 00054dd8: 0000: 00012152 00000000 00000000 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00054de4: 0000: c0002600 00000000 t0 write UNKNOWN_0CC5 (0cc5) UNKNOWN_0CC5: 0x4 00054dec: 0000: 00000cc5 00000004 t0 write 0xcc4 (0cc4) 0xcc4: 00000000 00054df4: 0000: 00000cc4 00000000 t0 write 0xd03 (0d03) 0xd03: 80200000 00054dfc: 0000: 00000d03 80200000 t0 write UNKNOWN_0EC2 (0ec2) UNKNOWN_0EC2: 0x40000 00054e04: 0000: 00000ec2 00040000 t0 write VPC_DEBUG_ECO_CONTROL (0e64) VPC_DEBUG_ECO_CONTROL: 0x100 00054e0c: 0000: 00000e64 00000100 t0 write UNKNOWN_0E42 (0e42) UNKNOWN_0E42: 0 00054e14: 0000: 00000e42 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x1e 00054e1c: 0000: 00000ec3 0000001e t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x28 00054e24: 0000: 00000f03 00000028 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 00054e2c: 0000: c0014300 00040000 00000000 t0 write VFD_INDEX_OFFSET (2208) VFD_INDEX_OFFSET: 0 00054e38: 0000: 00002208 00000000 t0 write UNKNOWN_2209 (2209) UNKNOWN_2209: 0 00054e40: 0000: 00002209 00000000 0016b088: 0000: c0013f00 00054d6c 00000037 t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:00055328 ibsize:000000ac t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x3 00055328: 0000: 000023db 00000003 t0 write SP_INSTR_CACHE_CTRL (22c1) SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } 00055330: 0000: 000022c1 000005c3 t0 write HLSQ_CONTROL_1_REG (23c1) HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x1008 } 00055338: 0000: 000023c1 fcfc1108 t0 write HLSQ_CONTROL_2_REG (23c2) HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 00055340: 0000: 000023c2 fff3f3f0 t0 write HLSQ_VS_CONTROL_REG (23c5) HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 2 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 1 } 00055348: 0000: 000023c5 01010002 t0 write HLSQ_HS_CONTROL_REG (23c7) HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 00055350: 0000: 000023c7 007e0200 t0 write HLSQ_DS_CONTROL_REG (23c8) HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 00055358: 0000: 000023c8 007e0200 t0 write HLSQ_GS_CONTROL_REG (23c9) HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 00055360: 0000: 000023c9 007e0200 t0 write HLSQ_FS_CONTROL_REG (23c6) HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 2 | CONSTOBJECTOFFSET = 2 | ENABLED | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 } 00055368: 0000: 000023c6 017f0202 t0 write SP_VS_OBJ_OFFSET_REG (22e0) SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 00055370: 0000: 000022e0 00000000 t0 write SP_HS_OBJ_OFFSET_REG (230d) SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } 00055378: 0000: 0000230d 7e020000 t0 write SP_DS_OBJ_OFFSET_REG (2334) SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } 00055380: 0000: 00002334 7e020000 t0 write SP_GS_OBJ_OFFSET_REG (235b) SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } 00055388: 0000: 0000235b 7e020000 t0 write SP_FS_OBJ_OFFSET_REG (22ea) SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } 00055390: 0000: 000022ea 7e020000 t0 write SP_VS_OBJ_START (22e1) SP_VS_OBJ_START: 0x49000 00049000: 0000: 00000000 13000000 00000000 00000000 00000000 00000000 00000000 00000000 * :0:0000:0000[13000000x_00000000x] (sy)end :0:0001:0001[00000000x_00000000x] nop :0:0002:0002[00000000x_00000000x] nop :0:0003:0003[00000000x_00000000x] nop :0:0004:0004[00000000x_00000000x] nop Stats: - shaderdb: 5 instr, 4 nops, 1 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 0 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 0 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) 00055398: 0000: 000022e1 00049000 t0 write SP_HS_OBJ_START (230e) SP_HS_OBJ_START: 0 000553a0: 0000: 0000230e 00000000 t0 write SP_DS_OBJ_START (2335) SP_DS_OBJ_START: 0 000553a8: 0000: 00002335 00000000 t0 write SP_GS_OBJ_START (235c) SP_GS_OBJ_START: 0 000553b0: 0000: 0000235c 00000000 t0 write SP_VS_LENGTH_REG (22e5) SP_VS_LENGTH_REG: 1 000553b8: 0000: 000022e5 00000001 t3 opcode: CP_LOAD_STATE4 (30) (3 dwords) { DST_OFF = 0 | STATE_SRC = SS4_INDIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 1 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0x49000 } :0:0000:0000[13000000x_00000000x] (sy)end :0:0001:0001[00000000x_00000000x] nop :0:0002:0002[00000000x_00000000x] nop :0:0003:0003[00000000x_00000000x] nop :0:0004:0004[00000000x_00000000x] nop Stats: - shaderdb: 5 instr, 4 nops, 1 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 0 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 0 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) 000553c0: 0000: c0013000 00620000 00049000 t0 write 0x2072 (2072) 0x2072: 00000000 000553cc: 0000: 00002072 00000000 t0 write UNKNOWN_2155 (2155) UNKNOWN_2155: 0 000553d4: 0000: 00002155 00000000 t0 write GRAS_CNTL (2003) GRAS_CNTL: { IJ_PERSP } 000553dc: 0000: 00002003 00000001 t0 write VPC_VARYING_INTERP[0].MODE (2142) VPC_VARYING_INTERP[0].MODE: 0 000553e4: 0000: 00002142 00000000 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0x600a0 } 000553ec: 0000: 000023c0 080604f0 t0 write HLSQ_CONTROL_3_REG (23c3) HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } 000553f4: 0000: 000023c3 fcfcfc00 t0 write HLSQ_CONTROL_4_REG (23c4) HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r0.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } 000553fc: 0000: 000023c4 00fcfc00 t0 write SP_FS_CTRL_REG0 (22e8) SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE } SP_FS_CTRL_REG1: { CONSTLENGTH = 2 | VARYING | 0x80000000 } 00055404: 0000: 000122e8 00340412 80100002 t0 write SP_FS_OBJ_START (22eb) SP_FS_OBJ_START: 0x46000 00046000: 0000: 00002000 5730cb00 00000000 03000000 00000000 00000000 00000000 00000000 * :2:0000:0000[5730cb00x_00002000x] (sy)(rpt3)bary.f (ei)hr0.x, (r)0, r0.x :0:0001:0004[03000000x_00000000x] end :0:0002:0005[00000000x_00000000x] nop :0:0003:0006[00000000x_00000000x] nop :0:0004:0007[00000000x_00000000x] nop :0:0005:0008[00000000x_00000000x] nop Stats: - shaderdb: 9 instr, 4 nops, 5 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 1 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 4 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) 00055410: 0000: 000022eb 00046000 t0 write SP_FS_LENGTH_REG (22ef) SP_FS_LENGTH_REG: 1 00055418: 0000: 000022ef 00000001 t0 write RB_RENDER_COMPONENTS (20fb) RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } 00055420: 0000: 000020fb 0000000f t3 opcode: CP_LOAD_STATE4 (30) (3 dwords) { DST_OFF = 0 | STATE_SRC = SS4_INDIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 1 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0x46000 } :2:0000:0000[5730cb00x_00002000x] (sy)(rpt3)bary.f (ei)hr0.x, (r)0, r0.x :0:0001:0004[03000000x_00000000x] end :0:0002:0005[00000000x_00000000x] nop :0:0003:0006[00000000x_00000000x] nop :0:0004:0007[00000000x_00000000x] nop :0:0005:0008[00000000x_00000000x] nop Stats: - shaderdb: 9 instr, 4 nops, 5 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 1 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 4 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) 00055428: 0000: c0013000 00720000 00046000 t0 write SP_SP_CTRL_REG (22c0) SP_SP_CTRL_REG: { 0x60010 } 00055434: 0000: 000022c0 00060010 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 28 | GROUP_ID = 3 } { ADDR_LO = 0x9b070 } 0005543c: 0000: c0014300 0300001c 0009b070 t0 write RB_DEPTH_INFO (2103) RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTH4_NONE | DEPTH_BASE = 0 } RB_DEPTH_PITCH: 0 RB_DEPTH_PITCH2: 0 00055448: 0000: 00022103 00000000 00000000 00000000 t0 write GRAS_DEPTH_CONTROL (2077) GRAS_DEPTH_CONTROL: { FORMAT = DEPTH4_NONE } 00055458: 0000: 00002077 00000000 t0 write RB_STENCIL_INFO (2108) RB_STENCIL_INFO: { STENCIL_BASE = 0 } RB_STENCIL_PITCH: 0 0x210a: 00000000 00055460: 0000: 00022108 00000000 00000000 00000000 t0 write 0x2002 (2002) 0x2002: 00000000 00055470: 0000: 00002002 00000000 t0 write RB_ALPHA_CONTROL (20f8) RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } 00055478: 0000: 000020f8 00000e00 t0 write RB_MRT[0].CONTROL (20a4) RB_MRT[0].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0x7 } 00055480: 0000: 000020a4 07000c00 t0 write RB_MRT[0].BLEND_CONTROL (20a8) RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } 00055488: 0000: 000020a8 00000000 t0 write GRAS_CL_CLIP_CNTL (2000) GRAS_CL_CLIP_CNTL: { 0x80000 } 00055490: 0000: 00002000 00080000 t0 write GRAS_SU_POLY_OFFSET_SCALE (2074) GRAS_SU_POLY_OFFSET_SCALE: 0.000000 GRAS_SU_POLY_OFFSET_OFFSET: 0.000000 GRAS_SU_POLY_OFFSET_CLAMP: 0.000000 00055498: 0000: 00022074 00000000 00000000 00000000 t0 write GRAS_SU_MODE_CONTROL (2078) GRAS_SU_MODE_CONTROL: { FRONT_CW | LINEHALFWIDTH = 0.500000 | MSAA_ENABLE | RENDERING_PASS } 000554a8: 0000: 00002078 00102014 t0 write GRAS_SC_SCREEN_SCISSOR_TL (207c) GRAS_SC_SCREEN_SCISSOR_TL: { X = 2 | Y = 13 } GRAS_SC_SCREEN_SCISSOR_BR: { X = 33 | Y = 44 } 000554b0: 0000: 0001207c 000d0002 002c0021 t0 write GRAS_CL_VPORT_XOFFSET_0 (2008) GRAS_CL_VPORT_XOFFSET_0: 18.000000 GRAS_CL_VPORT_XSCALE_0: 16.000000 GRAS_CL_VPORT_YOFFSET_0: 29.000000 GRAS_CL_VPORT_YSCALE_0: 16.000000 GRAS_CL_VPORT_ZOFFSET_0: 0.500000 GRAS_CL_VPORT_ZSCALE_0: 0.500000 000554bc: 0000: 00052008 41900000 41800000 41e80000 41800000 3f000000 3f000000 t0 write GRAS_CL_GB_CLIP_ADJ (2004) GRAS_CL_GB_CLIP_ADJ: { HORZ = 511 | VERT = 511 } 000554d8: 0000: 00002004 0007fdff t0 write GRAS_SC_CONTROL (207b) GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 4 | RASTER_MODE = 0 } 000554e0: 0000: 0000207b 00000200 t0 write 0x2382 (2382) 0x2382: 00000002 000554e8: 0000: 00002382 00000002 t0 write RB_MSAA_CONTROL (20a2) RB_MSAA_CONTROL: { SAMPLES = 4 } 000554f0: 0000: 000020a2 00008000 t0 write RB_RENDER_CONTROL2 (20a3) RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 4 | IJ_PERSP_PIXEL } 000554f8: 0000: 000020a3 00001200 t0 write RB_MRT[0].BUF_INFO (20a5) RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB4_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_ALWAYS | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 1024 } RB_MRT[0].BASE: 0 RB_MRT[0].CONTROL3: { STRIDE = 64 } 00055500: 0000: 000220a5 0010029a 00000000 00000200 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 43 | GROUP_ID = 2 } { ADDR_LO = 0x9b0e0 } 00055510: 0000: c0014300 0200002b 0009b0e0 t0 write 0x215c (215c) 0x215c: 00000000 0x215d: 00000000 0005551c: 0000: 0001215c 00000000 00000000 t0 write 0x215f (215f) 0x215f: 00000000 00055528: 0000: 0000215f 00000000 t0 write 0x215e (215e) 0x215e: 00000000 00055530: 0000: 0000215e 00000000 t0 write 0x2161 (2161) 0x2161: 00000000 0x2162: 00000000 00055538: 0000: 00012161 00000000 00000000 t0 write 0x2164 (2164) 0x2164: 00000000 00055544: 0000: 00002164 00000000 t0 write 0x2163 (2163) 0x2163: 00000000 0005554c: 0000: 00002163 00000000 t0 write 0x2166 (2166) 0x2166: 00000000 0x2167: 00000000 00055554: 0000: 00012166 00000000 00000000 t0 write 0x2169 (2169) 0x2169: 00000000 00055560: 0000: 00002169 00000000 t0 write 0x2168 (2168) 0x2168: 00000000 00055568: 0000: 00002168 00000000 t0 write 0x216b (216b) 0x216b: 00000000 0x216c: 00000000 00055570: 0000: 0001216b 00000000 00000000 t0 write VPC_SO_FLUSH_WADDR_3 (216e) VPC_SO_FLUSH_WADDR_3: 0 0005557c: 0000: 0000216e 00000000 t0 write 0x216d (216d) 0x216d: 00000000 00055584: 0000: 0000216d 00000000 t0 write UNKNOWN_2156 (2156) UNKNOWN_2156: 0 0005558c: 0000: 00002156 00000000 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 18 | GROUP_ID = 1 } { ADDR_LO = 0x9b190 } 00055594: 0000: c0014300 01000012 0009b190 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 15 | GROUP_ID = 0 } { ADDR_LO = 0x9b1e0 } 000555a0: 0000: c0014300 0000000f 0009b1e0 group_id: 0 count: 15 addr: 000000000009b1e0 flags: 0 0009b1e0: 0000: 00002073 00000000 00002101 00000000 00002106 00000000 000021e5 00000000 0009b200: 0020: 0001210b 00000000 00000000 00002381 00000000 000023a0 00000000 t0 write GRAS_ALPHA_CONTROL (2073) GRAS_ALPHA_CONTROL: { 0 } 0009b1e0: 0000: 00002073 00000000 t0 write RB_DEPTH_CONTROL (2101) RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } 0009b1e8: 0000: 00002101 00000000 t0 write RB_STENCIL_CONTROL (2106) RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } 0009b1f0: 0000: 00002106 00000000 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 0009b1f8: 0000: 000021e5 00000000 t0 write RB_STENCILREFMASK (210b) RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 0009b200: 0000: 0001210b 00000000 00000000 t0 write TPL1_TP_TEX_COUNT (2381) TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } 0009b20c: 0000: 00002381 00000000 t0 write TPL1_TP_FS_TEX_COUNT (23a0) TPL1_TP_FS_TEX_COUNT: 0 0009b214: 0000: 000023a0 00000000 group_id: 1 count: 18 addr: 000000000009b190 flags: 0 0009b190: 0000: 00002200 082a0008 00002201 fcfc0081 00002203 0000fc00 0007220a 0008080f 0009b1b0: 0020: 0009b010 00000060 00000001 0000080f 0009b040 00000030 00000001 0001228a 0009b1d0: 0040: 7000411f 3000011f t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } 0009b190: 0000: 00002200 082a0008 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } 0009b198: 0000: 00002201 fcfc0081 t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } 0009b1a0: 0000: 00002203 0000fc00 t0 write VFD_FETCH[0].INSTR_0 (220a) VFD_FETCH[0].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 | SWITCHNEXT } VFD_FETCH[0].INSTR_1: 0x9b010 VFD_FETCH[0].INSTR_2: { SIZE = 0x60 } VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 } VFD_FETCH[0x1].INSTR_1: 0x9b040 VFD_FETCH[0x1].INSTR_2: { SIZE = 0x30 } VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } 0009b1a8: 0000: 0007220a 0008080f 0009b010 00000060 00000001 0000080f 0009b040 00000030 0009b1c8: 0020: 00000001 t0 write VFD_DECODE[0].INSTR (228a) VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID | SWITCHNEXT } VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID } 0009b1cc: 0000: 0001228a 7000411f 3000011f group_id: 2 count: 43 addr: 000000000009b0e0 flags: 0 0009b0e0: 0000: 000020a1 00000000 000022f1 0001a100 000022f0 fc00fc01 00002100 00000001 0009b100: 0020: 000021e5 00000000 000020f9 ffff0501 0000214a 00000000 00002140 42001004 0009b120: 0040: 001922c6 0010fc04 00001e00 00000000 00000000 00000000 00000000 00000000 * 0009b160: 0080: 00000000 00000000 00fcfc00 00000008 00000000 00000000 00000000 00000000 * t0 write RB_RENDER_CONTROL (20a1) RB_RENDER_CONTROL: { 0 } 0009b0e0: 0000: 000020a1 00000000 t0 write SP_FS_MRT[0].REG (22f1) SP_FS_MRT[0].REG: { REGID = r0.x | HALF_PRECISION | MRTFORMAT = RB4_R8G8B8A8_UNORM } 0009b0e8: 0000: 000022f1 0001a100 t0 write SP_FS_OUTPUT_REG (22f0) SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 0009b0f0: 0000: 000022f0 fc00fc01 t0 write RB_FS_OUTPUT_REG (2100) RB_FS_OUTPUT_REG: { MRT = 1 } 0009b0f8: 0000: 00002100 00000001 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 0009b100: 0000: 000021e5 00000000 t0 write RB_FS_OUTPUT (20f9) RB_FS_OUTPUT: { ENABLE_BLEND = 0x1 | INDEPENDENT_BLEND | SAMPLE_MASK = 0xffff | 0x400 } 0009b108: 0000: 000020f9 ffff0501 t0 write VPC_VARYING_PS_REPL[0].MODE (214a) VPC_VARYING_PS_REPL[0].MODE: 0 0009b110: 0000: 0000214a 00000000 t0 write VPC_ATTR (2140) VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 } 0009b118: 0000: 00002140 42001004 t0 write SP_VS_PARAM_REG (22c6) SP_VS_PARAM_REG: { POSREGID = r1.x | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } SP_VS_OUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } UNKNOWN_22D7: 0xfcfc00 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 0009b120: 0000: 001922c6 0010fc04 00001e00 00000000 00000000 00000000 00000000 00000000 * 0009b160: 0040: 00000000 00000000 00fcfc00 00000008 00000000 00000000 00000000 00000000 * group_id: 3 count: 28 addr: 000000000009b070 flags: 0 0009b070: 0000: 000021c4 02000001 00002141 00040400 00002001 00000000 000022c4 00200800 0009b090: 0020: 000022c5 08000002 0000230c 00000000 00002318 00000000 00002319 00000000 0009b0b0: 0040: 00002340 00000000 00002202 fcfcfcfc 00002204 0000fcfc 00002154 00000000 0009b0d0: 0060: 000021e7 00000000 000021c5 00000012 t0 write PC_PRIM_VTX_CNTL (21c4) PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } 0009b070: 0000: 000021c4 02000001 t0 write VPC_PACK (2141) VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } 0009b078: 0000: 00002141 00040400 t0 write UNKNOWN_2001 (2001) UNKNOWN_2001: 0 0009b080: 0000: 00002001 00000000 t0 write SP_VS_CTRL_REG0 (22c4) SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 2 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 0009b088: 0000: 000022c4 00200800 t0 write SP_VS_CTRL_REG1 (22c5) SP_VS_CTRL_REG1: { CONSTLENGTH = 2 | INITIALOUTSTANDING = 8 } 0009b090: 0000: 000022c5 08000002 t0 write 0x230c (230c) 0x230c: 00000000 0009b098: 0000: 0000230c 00000000 t0 write 0x2318 (2318) 0x2318: 00000000 0009b0a0: 0000: 00002318 00000000 t0 write 0x2319 (2319) 0x2319: 00000000 0009b0a8: 0000: 00002319 00000000 t0 write 0x2340 (2340) 0x2340: 00000000 0009b0b0: 0000: 00002340 00000000 t0 write VFD_CONTROL_2 (2202) VFD_CONTROL_2: 0xfcfcfcfc 0009b0b8: 0000: 00002202 fcfcfcfc t0 write VFD_CONTROL_4 (2204) VFD_CONTROL_4: 0xfcfc 0009b0c0: 0000: 00002204 0000fcfc t0 write UNKNOWN_2154 (2154) UNKNOWN_2154: 0 0009b0c8: 0000: 00002154 00000000 t0 write PC_HS_PARAM (21e7) PC_HS_PARAM: { VERTICES_OUT = 0 | SPACING = EQUAL_SPACING } 0009b0d0: 0000: 000021e7 00000000 t0 write PC_PRIM_VTX_CNTL2 (21c5) PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 0009b0d8: 0000: 000021c5 00000012 t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = USE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x200000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 3 } draw[46] register values + 00000000 0xcc4: 00000000 + 00000004 UNKNOWN_0CC5: 0x4 + 80200000 0xd03: 80200000 !+ 00000001 HLSQ_MODE_CONTROL: 0x1 + 00000000 UNKNOWN_0E42: 0 + 00000100 VPC_DEBUG_ECO_CONTROL: 0x100 + 00040000 UNKNOWN_0EC2: 0x40000 !+ 0000001e SP_MODE_CONTROL: 0x1e !+ 00000028 TPL1_TP_MODE_CONTROL: 0x28 !+ 00080000 GRAS_CL_CLIP_CNTL: { 0x80000 } + 00000000 UNKNOWN_2001: 0 + 00000000 0x2002: 00000000 + 00000001 GRAS_CNTL: { IJ_PERSP } + 0007fdff GRAS_CL_GB_CLIP_ADJ: { HORZ = 511 | VERT = 511 } + 41900000 GRAS_CL_VPORT_XOFFSET_0: 18.000000 + 41800000 GRAS_CL_VPORT_XSCALE_0: 16.000000 + 41e80000 GRAS_CL_VPORT_YOFFSET_0: 29.000000 + 41800000 GRAS_CL_VPORT_YSCALE_0: 16.000000 + 3f000000 GRAS_CL_VPORT_ZOFFSET_0: 0.500000 + 3f000000 GRAS_CL_VPORT_ZSCALE_0: 0.500000 + ffc00010 GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 4092.000000 } + 00000008 GRAS_SU_POINT_SIZE: 0.500000 + 00000000 0x2072: 00000000 !+ 00000000 GRAS_ALPHA_CONTROL: { 0 } + 00000000 GRAS_SU_POLY_OFFSET_SCALE: 0.000000 + 00000000 GRAS_SU_POLY_OFFSET_OFFSET: 0.000000 + 00000000 GRAS_SU_POLY_OFFSET_CLAMP: 0.000000 + 00000000 GRAS_DEPTH_CONTROL: { FORMAT = DEPTH4_NONE } !+ 00102014 GRAS_SU_MODE_CONTROL: { FRONT_CW | LINEHALFWIDTH = 0.500000 | MSAA_ENABLE | RENDERING_PASS } !+ 00000200 GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 4 | RASTER_MODE = 0 } !+ 000d0002 GRAS_SC_SCREEN_SCISSOR_TL: { X = 2 | Y = 13 } !+ 002c0021 GRAS_SC_SCREEN_SCISSOR_BR: { X = 33 | Y = 44 } !+ 00000000 RB_RENDER_CONTROL: { 0 } !+ 00008000 RB_MSAA_CONTROL: { SAMPLES = 4 } !+ 00001200 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 4 | IJ_PERSP_PIXEL } !+ 07000c00 RB_MRT[0].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0x7 } !+ 0010029a RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB4_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_ALWAYS | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 1024 } !+ 00000000 RB_MRT[0].BASE: 0 !+ 00000200 RB_MRT[0].CONTROL3: { STRIDE = 64 } + 00000000 RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } + 00000e00 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } !+ ffff0501 RB_FS_OUTPUT: { ENABLE_BLEND = 0x1 | INDEPENDENT_BLEND | SAMPLE_MASK = 0xffff | 0x400 } + 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } + 00000001 RB_FS_OUTPUT_REG: { MRT = 1 } + 00000000 RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } + 00000000 RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTH4_NONE | DEPTH_BASE = 0 } + 00000000 RB_DEPTH_PITCH: 0 + 00000000 RB_DEPTH_PITCH2: 0 + 00000000 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } + 00000000 RB_STENCIL_INFO: { STENCIL_BASE = 0 } + 00000000 RB_STENCIL_PITCH: 0 + 00000000 0x210a: 00000000 + 00000000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } + 00000000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } !+ 42001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 } + 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } !+ 00000000 VPC_VARYING_INTERP[0].MODE: 0 !+ 00000000 VPC_VARYING_PS_REPL[0].MODE: 0 + 00000000 UNKNOWN_2152: 0 + 00000000 UNKNOWN_2153: 0 + 00000000 UNKNOWN_2154: 0 + 00000000 UNKNOWN_2155: 0 + 00000000 UNKNOWN_2156: 0 + 00000000 0x215c: 00000000 + 00000000 0x215d: 00000000 + 00000000 0x215e: 00000000 + 00000000 0x215f: 00000000 + 00000000 0x2161: 00000000 + 00000000 0x2162: 00000000 + 00000000 0x2163: 00000000 + 00000000 0x2164: 00000000 + 00000000 0x2166: 00000000 + 00000000 0x2167: 00000000 + 00000000 0x2168: 00000000 + 00000000 0x2169: 00000000 + 00000000 0x216b: 00000000 + 00000000 0x216c: 00000000 + 00000000 0x216d: 00000000 + 00000000 VPC_SO_FLUSH_WADDR_3: 0 !+ 0000001f UNKNOWN_21C3: 0x1f !+ 02000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + ffffffff PC_RESTART_INDEX: 0xffffffff + 00000000 PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } + 00000001 UNKNOWN_21E6: 0x1 + 00000000 PC_HS_PARAM: { VERTICES_OUT = 0 | SPACING = EQUAL_SPACING } !+ 082a0008 VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } !+ fcfc0081 VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } + fcfcfcfc VFD_CONTROL_2: 0xfcfcfcfc !+ 0000fc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } + 0000fcfc VFD_CONTROL_4: 0xfcfc + 00000000 VFD_INDEX_OFFSET: 0 + 00000000 UNKNOWN_2209: 0 + 0008080f VFD_FETCH[0].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 | SWITCHNEXT } !+ 0009b010 VFD_FETCH[0].INSTR_1: 0x9b010 + 00000060 VFD_FETCH[0].INSTR_2: { SIZE = 0x60 } + 00000001 VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } + 0000080f VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 } !+ 0009b040 VFD_FETCH[0x1].INSTR_1: 0x9b040 + 00000030 VFD_FETCH[0x1].INSTR_2: { SIZE = 0x30 } + 00000001 VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } + 7000411f VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID | SWITCHNEXT } + 3000011f VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID } + 00060010 SP_SP_CTRL_REG: { 0x60010 } + 000005c3 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } !+ 00200800 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 2 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } !+ 08000002 SP_VS_CTRL_REG1: { CONSTLENGTH = 2 | INITIALOUTSTANDING = 8 } !+ 0010fc04 SP_VS_PARAM_REG: { POSREGID = r1.x | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } !+ 00001e00 SP_VS_OUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00fcfc00 UNKNOWN_22D7: 0xfcfc00 + 00000008 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } !+ 00049000 SP_VS_OBJ_START: 0x49000 00049000: 0000: 00000000 13000000 00000000 00000000 00000000 00000000 00000000 00000000 * :0:0000:0000[13000000x_00000000x] (sy)end :0:0001:0001[00000000x_00000000x] nop :0:0002:0002[00000000x_00000000x] nop :0:0003:0003[00000000x_00000000x] nop :0:0004:0004[00000000x_00000000x] nop Stats: - shaderdb: 5 instr, 4 nops, 1 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 0 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 0 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) !+ 00000001 SP_VS_LENGTH_REG: 1 !+ 00340412 SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE } !+ 80100002 SP_FS_CTRL_REG1: { CONSTLENGTH = 2 | VARYING | 0x80000000 } !+ 7e020000 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } !+ 00046000 SP_FS_OBJ_START: 0x46000 00046000: 0000: 00002000 5730cb00 00000000 03000000 00000000 00000000 00000000 00000000 * :2:0000:0000[5730cb00x_00002000x] (sy)(rpt3)bary.f (ei)hr0.x, (r)0, r0.x :0:0001:0004[03000000x_00000000x] end :0:0002:0005[00000000x_00000000x] nop :0:0003:0006[00000000x_00000000x] nop :0:0004:0007[00000000x_00000000x] nop :0:0005:0008[00000000x_00000000x] nop Stats: - shaderdb: 9 instr, 4 nops, 5 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 1 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 4 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) + 00000001 SP_FS_LENGTH_REG: 1 !+ fc00fc01 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r63.x } !+ 0001a100 SP_FS_MRT[0].REG: { REGID = r0.x | HALF_PRECISION | MRTFORMAT = RB4_R8G8B8A8_UNORM } + 00000000 0x230c: 00000000 + 7e020000 SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } + 00000000 SP_HS_OBJ_START: 0 + 00000000 0x2318: 00000000 + 00000000 0x2319: 00000000 + 7e020000 SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } + 00000000 SP_DS_OBJ_START: 0 + 00000000 0x2340: 00000000 + 7e020000 SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } + 00000000 SP_GS_OBJ_START: 0 + 00000808 TPL1_TP_TEX_OFFSET: 0x808 + 00000000 TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } !+ 00000002 0x2382: 00000002 !+ 00000000 TPL1_TP_FS_TEX_COUNT: 0 !+ 080604f0 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0x600a0 } !+ fcfc1108 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x1008 } !+ fff3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } + fcfcfc00 HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } !+ 00fcfc00 HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r0.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } !+ 01010002 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 2 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 1 } !+ 017f0202 HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 2 | CONSTOBJECTOFFSET = 2 | ENABLED | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 } !+ 007e0200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } !+ 007e0200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } !+ 007e0200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } !+ 00000003 HLSQ_UPDATE_CONTROL: 0x3 000555ac: 0000: c0023800 00200984 00000001 00000003 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 18 | GROUP_ID = 1 } { ADDR_LO = 0x9b350 } 000555bc: 0000: c0014300 01000012 0009b350 group_id: 1 count: 18 addr: 000000000009b350 flags: 0 0009b350: 0000: 00002200 082a0008 00002201 fcfc0081 00002203 0000fc00 0007220a 0008080f 0009b370: 0020: 0009b2f0 00000060 00000001 0000080f 0009b320 00000030 00000001 0001228a 0009b390: 0040: 7000411f 3000011f t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } 0009b350: 0000: 00002200 082a0008 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } 0009b358: 0000: 00002201 fcfc0081 t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } 0009b360: 0000: 00002203 0000fc00 t0 write VFD_FETCH[0].INSTR_0 (220a) VFD_FETCH[0].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 | SWITCHNEXT } VFD_FETCH[0].INSTR_1: 0x9b2f0 VFD_FETCH[0].INSTR_2: { SIZE = 0x60 } VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 } VFD_FETCH[0x1].INSTR_1: 0x9b320 VFD_FETCH[0x1].INSTR_2: { SIZE = 0x30 } VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } 0009b368: 0000: 0007220a 0008080f 0009b2f0 00000060 00000001 0000080f 0009b320 00000030 0009b388: 0020: 00000001 t0 write VFD_DECODE[0].INSTR (228a) VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID | SWITCHNEXT } VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID } 0009b38c: 0000: 0001228a 7000411f 3000011f t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = USE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x200000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 3 } draw[47] register values + 082a0008 VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } + fcfc0081 VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } + 0000fc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } + 0008080f VFD_FETCH[0].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 | SWITCHNEXT } !+ 0009b2f0 VFD_FETCH[0].INSTR_1: 0x9b2f0 + 00000060 VFD_FETCH[0].INSTR_2: { SIZE = 0x60 } + 00000001 VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } + 0000080f VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 } !+ 0009b320 VFD_FETCH[0x1].INSTR_1: 0x9b320 + 00000030 VFD_FETCH[0x1].INSTR_2: { SIZE = 0x30 } + 00000001 VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } + 7000411f VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID | SWITCHNEXT } + 3000011f VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID } 000555c8: 0000: c0023800 00200984 00000001 00000003 0016b094: 0000: c0013f00 00055328 000000ac t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 0016b0a0: 0000: c0014300 00040000 00000000 t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:001f92c4 ibsize:000000f7 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 001f92c4: 0000: c0002600 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x4 001f92cc: 0000: 00000ec3 00000004 t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x68 001f92d4: 0000: 00000f03 00000068 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 001f92dc: 0000: c0002600 00000000 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } 001f92e4: 0000: 000023c0 080004f0 t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = 0x1d } event (null) 001f92ec: 0000: c0004600 0000001d t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = FACENESS_FLUSH } event FACENESS_FLUSH 001f92f4: 0000: c0004600 0000001c t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 001f92fc: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0 001f9304: 0000: 00000cc6 00000000 t0 write UNKNOWN_0E42 (0e42) UNKNOWN_0E42: 0 001f930c: 0000: 00000e42 00000000 t0 write HLSQ_MODE_CONTROL (0e05) HLSQ_MODE_CONTROL: 0x2 001f9314: 0000: 00000e05 00000002 t0 write UNKNOWN_0CC5 (0cc5) UNKNOWN_0CC5: 0x4 001f931c: 0000: 00000cc5 00000004 t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x7 001f9324: 0000: 000023db 00000007 t0 write VFD_CONTROL_2 (2202) VFD_CONTROL_2: 0xfcfcfcfc 001f932c: 0000: 00002202 fcfcfcfc t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } 001f9334: 0000: 00002203 fcfcfc00 t0 write VFD_CONTROL_4 (2204) VFD_CONTROL_4: 0xfcfc 001f933c: 0000: 00002204 0000fcfc t0 write VFD_INDEX_OFFSET (2208) VFD_INDEX_OFFSET: 0 001f9344: 0000: 00002208 00000000 t0 write UNKNOWN_2209 (2209) UNKNOWN_2209: 0 001f934c: 0000: 00002209 00000000 t0 write UNKNOWN_2152 (2152) UNKNOWN_2152: 0 UNKNOWN_2153: 0 001f9354: 0000: 00012152 00000000 00000000 t0 write UNKNOWN_2156 (2156) UNKNOWN_2156: 0 001f9360: 0000: 00002156 00000000 t0 write UNKNOWN_2154 (2154) UNKNOWN_2154: 0 001f9368: 0000: 00002154 00000000 t0 write UNKNOWN_2155 (2155) UNKNOWN_2155: 0 001f9370: 0000: 00002155 00000000 t0 write UNKNOWN_21C3 (21c3) UNKNOWN_21C3: 0x1d 001f9378: 0000: 000021c3 0000001d t0 write PC_PRIM_VTX_CNTL2 (21c5) PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 001f9380: 0000: 000021c5 00000012 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 001f9388: 0000: 000021e5 00000000 t0 write GRAS_SU_MODE_CONTROL (2078) GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } 001f9390: 0000: 00002078 00000000 t0 write UNKNOWN_2001 (2001) UNKNOWN_2001: 0 001f9398: 0000: 00002001 00000000 t0 write GRAS_CNTL (2003) GRAS_CNTL: { IJ_PERSP } 001f93a0: 0000: 00002003 00000001 t0 write GRAS_CL_CLIP_CNTL (2000) GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } 001f93a8: 0000: 00002000 00188000 t0 write TPL1_TP_TEX_COUNT (2381) TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } 001f93b0: 0000: 00002381 00000000 t0 write TPL1_TP_FS_TEX_COUNT (23a0) TPL1_TP_FS_TEX_COUNT: 0x3 001f93b8: 0000: 000023a0 00000003 t0 write RB_ALPHA_CONTROL (20f8) RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } 001f93c0: 0000: 000020f8 00000e00 t0 write RB_RENDER_COMPONENTS (20fb) RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } 001f93c8: 0000: 000020fb 0000000f t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 001f93d0: 0000: c0014300 00040000 00000000 t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } 001f93dc: 0000: 00002200 000a0000 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } 001f93e4: 0000: 00002201 fc030000 t0 write SP_INSTR_CACHE_CTRL (22c1) SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } 001f93ec: 0000: 000022c1 000005c3 t0 write HLSQ_CONTROL_1_REG (23c1) HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } 001f93f4: 0000: 000023c1 fcfc0120 t0 write HLSQ_CONTROL_2_REG (23c2) HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 001f93fc: 0000: 000023c2 27f3f3f0 t0 write HLSQ_VS_CONTROL_REG (23c5) HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } 001f9404: 0000: 000023c5 02010042 t0 write HLSQ_FS_CONTROL_REG (23c6) HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 001f940c: 0000: 000023c6 0041423e t0 write HLSQ_HS_CONTROL_REG (23c7) HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 001f9414: 0000: 000023c7 00404200 t0 write HLSQ_DS_CONTROL_REG (23c8) HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 001f941c: 0000: 000023c8 00404200 t0 write HLSQ_GS_CONTROL_REG (23c9) HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 001f9424: 0000: 000023c9 00404200 t0 write HLSQ_CS_CONTROL_REG (23ca) HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } 001f942c: 0000: 000023ca 00004200 t0 write SP_SP_CTRL_REG (22c0) SP_SP_CTRL_REG: { 0x60010 } 001f9434: 0000: 000022c0 00060010 t0 write UNKNOWN_21E6 (21e6) UNKNOWN_21E6: 0x1 001f943c: 0000: 000021e6 00000001 t0 write SP_VS_CTRL_REG0 (22c4) SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 001f9444: 0000: 000022c4 00200c10 t0 write SP_VS_CTRL_REG1 (22c5) SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } 001f944c: 0000: 000022c5 01000042 t0 write VPC_ATTR (2140) VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | 0x40000000 } 001f9454: 0000: 00002140 40001004 t0 write VPC_PACK (2141) VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } 001f945c: 0000: 00002141 00040400 t0 write PC_PRIM_VTX_CNTL (21c4) PC_PRIM_VTX_CNTL: { VAROUT = 1 } 001f9464: 0000: 000021c4 00000001 t0 write SP_VS_PARAM_REG (22c6) SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } UNKNOWN_22D7: 0xfcfc00 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 001f946c: 0000: 001922c6 0010fc03 00001e03 00000000 00000000 00000000 00000000 00000000 * 001f94ac: 0040: 00000000 00000000 00fcfc00 00000008 00000000 00000000 00000000 00000000 * t0 write SP_VS_OBJ_OFFSET_REG (22e0) SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 001f94d8: 0000: 000022e0 00000000 t0 write SP_VS_OBJ_START (22e1) SP_VS_OBJ_START: 0x1 001f94e0: 0000: 000022e1 00000001 t0 write SP_VS_LENGTH_REG (22e5) SP_VS_LENGTH_REG: 2 001f94e8: 0000: 000022e5 00000002 t3 opcode: CP_LOAD_STATE4 (30) (67 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } :2:0000:0000[56d81803x_20020003x] (sy)(ss)(nop3) shl.b r0.w, r0.w, 2 :1:0001:0004[20150000x_00000003x] cov.s32s16 hr0.x, r0.w :0:0002:0005[00000200x_00000000x] (rpt2)nop :1:0003:0008[201100f4x_00000000x] mova a0.x, hr0.x :0:0004:0009[00000500x_00000000x] (rpt5)nop :1:0005:0015[20154003x_00000c20x] mov.s32s32 r0.w, c :1:0006:0016[20154004x_00000c21x] mov.s32s32 r1.x, c :1:0007:0017[20154005x_00000c22x] mov.s32s32 r1.y, c :1:0008:0018[20156006x_00000c23x] (ul)mov.s32s32 r1.z, c :0:0009:0019[03000000x_00000000x] end :2:0010:0020[46f00007x_20050000x] shr.b r1.w, r0.x, 5 :2:0011:0021[43980008x_201f0000x] (nop2) and.b r2.x, r0.x, 31 :2:0012:0024[43980807x_201f0007x] (nop3) and.b r1.w, r1.w, 31 :2:0013:0028[46100807x_20100007x] (nop1) mul.u24 r1.w, r1.w, 16 :3:0014:0030[62040007x_00071014x] mad.u24 r1.w, c5.x, r2.x, r1.w :0:0015:0031[00000500x_00000000x] (rpt5)nop :6:0016:0037[c2c60f00x_04800006x] stlw.u32 l[r1.w], r0.w, 4 :0:0017:0038[04800000x_00000000x] chmask :0:0018:0039[05000000x_00000000x] chsh Stats: - shaderdb: 40 instr, 24 nops, 16 non-nops, 5 mov, 1 cov - shaderdb: 0 last-baryf, 0 half, 2 full, 5 constlen - shaderdb: 27 cat0, 6 cat1, 5 cat2, 1 cat3, 0 cat4, 0 cat5, 1 cat6, 0 cat7 - shaderdb: 0 sstall, 1 (ss), 1 (sy) 001f94f0: 0000: c0413000 00a00000 00000000 20020003 56d81803 00000003 20150000 00000000 001f9510: 0020: 00000200 00000000 201100f4 00000000 00000500 00000c20 20154003 00000c21 001f9530: 0040: 20154004 00000c22 20154005 00000c23 20156006 00000000 03000000 20050000 001f9550: 0060: 46f00007 201f0000 43980008 201f0007 43980807 20100007 46100807 00071014 001f9570: 0080: 62040007 00000000 00000500 04800006 c2c60f00 00000000 04800000 00000000 001f9590: 00a0: 05000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 * t0 write GRAS_SC_CONTROL (207b) GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = 0 | MSAA_DISABLE | RASTER_MODE = 0 } 001f95fc: 0000: 0000207b 00000808 t0 write RB_MSAA_CONTROL (20a2) RB_MSAA_CONTROL: { DISABLE | SAMPLES = 0 } 001f9604: 0000: 000020a2 00001000 t0 write RB_RENDER_CONTROL (20a1) RB_RENDER_CONTROL: { DISABLE_COLOR_PIPE | 0x2 } 001f960c: 0000: 000020a1 00000022 t0 write RB_DEPTH_CONTROL (2101) RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } 001f9614: 0000: 00002101 00000000 t0 write GRAS_ALPHA_CONTROL (2073) GRAS_ALPHA_CONTROL: { 0x2 } 001f961c: 0000: 00002073 00000002 t0 write RB_STENCIL_CONTROL (2106) RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } 001f9624: 0000: 00002106 00000000 t0 write RB_COPY_CONTROL (20fc) RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_FOUR | MODE = RB_COPY_DEPTH_STENCIL | FASTCLEAR = 0 | GMEM_BASE = 0 } RB_COPY_DEST_BASE: { BASE = 0x4f000 } RB_COPY_DEST_PITCH: { PITCH = 256 } RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_DISABLE | COMPONENT_ENABLE = 0xf | ENDIAN = ENDIAN_NONE | TILE = TILE4_3 } 001f962c: 0000: 000320fc 00000052 0004f000 00000008 0303c068 t0 write UNKNOWN_20EF (20ef) UNKNOWN_20EF: 0 001f9640: 0000: 000020ef 00000000 t0 write GRAS_SC_SCREEN_SCISSOR_TL (207c) GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } 001f9648: 0000: 0001207c 00000000 003f003f t0 write RB_FRAME_BUFFER_DIMENSION (0ce0) RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } 001f9654: 0000: 00000ce0 00400040 t0 write 0xce1 (0ce1) 0xce1: 00000000 001f965c: 0000: 00000ce1 00000000 t3 opcode: CP_LOAD_STATE4 (30) (11 dwords) { DST_OFF = 8 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } 001f9670: 0.000000 0.000000 1.000000 1.000000 64.000000 64.000000 1.000000 1.000000 001f9670: 0000: 00000000 00000000 3f800000 3f800000 42800000 42800000 3f800000 3f800000 001f9664: 0000: c0093000 00a00008 00000001 00000000 00000000 3f800000 3f800000 42800000 001f9684: 0020: 42800000 3f800000 3f800000 t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x80000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 2 } draw[48] register values + 00000004 UNKNOWN_0CC5: 0x4 + 00000000 UNKNOWN_0CC6: 0 + 00400040 RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } + 00000000 0xce1: 00000000 !+ 00000002 HLSQ_MODE_CONTROL: 0x2 + 00000000 UNKNOWN_0E42: 0 !+ 00000004 SP_MODE_CONTROL: 0x4 !+ 00000068 TPL1_TP_MODE_CONTROL: 0x68 !+ 00188000 GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } + 00000000 UNKNOWN_2001: 0 + 00000001 GRAS_CNTL: { IJ_PERSP } !+ 00000002 GRAS_ALPHA_CONTROL: { 0x2 } !+ 00000000 GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } !+ 00000808 GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = 0 | MSAA_DISABLE | RASTER_MODE = 0 } !+ 00000000 GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } !+ 003f003f GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } !+ 00000022 RB_RENDER_CONTROL: { DISABLE_COLOR_PIPE | 0x2 } !+ 00001000 RB_MSAA_CONTROL: { DISABLE | SAMPLES = 0 } + 00000000 UNKNOWN_20EF: 0 + 00000e00 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } + 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } !+ 00000052 RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_FOUR | MODE = RB_COPY_DEPTH_STENCIL | FASTCLEAR = 0 | GMEM_BASE = 0 } + 0004f000 RB_COPY_DEST_BASE: { BASE = 0x4f000 } + 00000008 RB_COPY_DEST_PITCH: { PITCH = 256 } !+ 0303c068 RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_DISABLE | COMPONENT_ENABLE = 0xf | ENDIAN = ENDIAN_NONE | TILE = TILE4_3 } + 00000000 RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } + 00000000 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } !+ 40001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | 0x40000000 } + 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } + 00000000 UNKNOWN_2152: 0 + 00000000 UNKNOWN_2153: 0 + 00000000 UNKNOWN_2154: 0 + 00000000 UNKNOWN_2155: 0 + 00000000 UNKNOWN_2156: 0 !+ 0000001d UNKNOWN_21C3: 0x1d !+ 00000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 } + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + 00000000 PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } + 00000001 UNKNOWN_21E6: 0x1 !+ 000a0000 VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } !+ fc030000 VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } + fcfcfcfc VFD_CONTROL_2: 0xfcfcfcfc !+ fcfcfc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } + 0000fcfc VFD_CONTROL_4: 0xfcfc + 00000000 VFD_INDEX_OFFSET: 0 + 00000000 UNKNOWN_2209: 0 + 00060010 SP_SP_CTRL_REG: { 0x60010 } + 000005c3 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } !+ 00200c10 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } !+ 01000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } !+ 0010fc03 SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } !+ 00001e03 SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00fcfc00 UNKNOWN_22D7: 0xfcfc00 + 00000008 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } !+ 00000001 SP_VS_OBJ_START: 0x1 !+ 00000002 SP_VS_LENGTH_REG: 2 + 00000000 TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } !+ 00000003 TPL1_TP_FS_TEX_COUNT: 0x3 !+ 080004f0 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } !+ fcfc0120 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } !+ 27f3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } !+ 02010042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } !+ 0041423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } !+ 00404200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } !+ 00404200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } !+ 00404200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00004200 HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } !+ 00000007 HLSQ_UPDATE_CONTROL: 0x7 001f9690: 0000: c0023800 00080888 00000001 00000002 0016b0ac: 0000: c0013f00 001f92c4 000000f7 t3 opcode: (null) (1d) (2 dwords) 0016b0b8: 0000: c0001d00 00000000 ############################################################ vertices: 0 ############################################################ cmdstream: 8 dwords t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:000555d8 ibsize:00000155 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 000555d8: 0000: c0002600 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x4 000555e0: 0000: 00000ec3 00000004 t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x68 000555e8: 0000: 00000f03 00000068 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 000555f0: 0000: c0002600 00000000 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } 000555f8: 0000: 000023c0 080004f0 t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = 0x1d } event (null) 00055600: 0000: c0004600 0000001d t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = FACENESS_FLUSH } event FACENESS_FLUSH 00055608: 0000: c0004600 0000001c t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00055610: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0 00055618: 0000: 00000cc6 00000000 t0 write UNKNOWN_0E42 (0e42) UNKNOWN_0E42: 0 00055620: 0000: 00000e42 00000000 t0 write HLSQ_MODE_CONTROL (0e05) HLSQ_MODE_CONTROL: 0x2 00055628: 0000: 00000e05 00000002 t0 write UNKNOWN_0CC5 (0cc5) UNKNOWN_0CC5: 0x4 00055630: 0000: 00000cc5 00000004 t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x7 00055638: 0000: 000023db 00000007 t0 write VFD_CONTROL_2 (2202) VFD_CONTROL_2: 0xfcfcfcfc 00055640: 0000: 00002202 fcfcfcfc t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } 00055648: 0000: 00002203 fcfcfc00 t0 write VFD_CONTROL_4 (2204) VFD_CONTROL_4: 0xfcfc 00055650: 0000: 00002204 0000fcfc t0 write VFD_INDEX_OFFSET (2208) VFD_INDEX_OFFSET: 0 00055658: 0000: 00002208 00000000 t0 write UNKNOWN_2209 (2209) UNKNOWN_2209: 0 00055660: 0000: 00002209 00000000 t0 write UNKNOWN_2152 (2152) UNKNOWN_2152: 0 UNKNOWN_2153: 0 00055668: 0000: 00012152 00000000 00000000 t0 write UNKNOWN_2156 (2156) UNKNOWN_2156: 0 00055674: 0000: 00002156 00000000 t0 write UNKNOWN_2154 (2154) UNKNOWN_2154: 0 0005567c: 0000: 00002154 00000000 t0 write UNKNOWN_2155 (2155) UNKNOWN_2155: 0 00055684: 0000: 00002155 00000000 t0 write UNKNOWN_21C3 (21c3) UNKNOWN_21C3: 0x1d 0005568c: 0000: 000021c3 0000001d t0 write PC_PRIM_VTX_CNTL2 (21c5) PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 00055694: 0000: 000021c5 00000012 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 0005569c: 0000: 000021e5 00000000 t0 write GRAS_SU_MODE_CONTROL (2078) GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } 000556a4: 0000: 00002078 00000000 t0 write UNKNOWN_2001 (2001) UNKNOWN_2001: 0 000556ac: 0000: 00002001 00000000 t0 write GRAS_CNTL (2003) GRAS_CNTL: { IJ_PERSP } 000556b4: 0000: 00002003 00000001 t0 write GRAS_CL_CLIP_CNTL (2000) GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } 000556bc: 0000: 00002000 00188000 t0 write TPL1_TP_TEX_COUNT (2381) TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } 000556c4: 0000: 00002381 00000000 t0 write TPL1_TP_FS_TEX_COUNT (23a0) TPL1_TP_FS_TEX_COUNT: 0x3 000556cc: 0000: 000023a0 00000003 t0 write RB_ALPHA_CONTROL (20f8) RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } 000556d4: 0000: 000020f8 00000e00 t0 write RB_RENDER_COMPONENTS (20fb) RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } 000556dc: 0000: 000020fb 0000000f t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 000556e4: 0000: c0014300 00040000 00000000 t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } 000556f0: 0000: 00002200 000a0000 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } 000556f8: 0000: 00002201 fc030000 t0 write SP_INSTR_CACHE_CTRL (22c1) SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } 00055700: 0000: 000022c1 000005c3 t0 write HLSQ_CONTROL_1_REG (23c1) HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } 00055708: 0000: 000023c1 fcfc0120 t0 write HLSQ_CONTROL_2_REG (23c2) HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 00055710: 0000: 000023c2 27f3f3f0 t0 write HLSQ_VS_CONTROL_REG (23c5) HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } 00055718: 0000: 000023c5 02010042 t0 write HLSQ_FS_CONTROL_REG (23c6) HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 1 } 00055720: 0000: 000023c6 0141423e t0 write HLSQ_HS_CONTROL_REG (23c7) HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00055728: 0000: 000023c7 00404200 t0 write HLSQ_DS_CONTROL_REG (23c8) HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00055730: 0000: 000023c8 00404200 t0 write HLSQ_GS_CONTROL_REG (23c9) HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00055738: 0000: 000023c9 00404200 t0 write HLSQ_CS_CONTROL_REG (23ca) HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } 00055740: 0000: 000023ca 00004200 t0 write SP_SP_CTRL_REG (22c0) SP_SP_CTRL_REG: { 0x60010 } 00055748: 0000: 000022c0 00060010 t0 write UNKNOWN_21E6 (21e6) UNKNOWN_21E6: 0x1 00055750: 0000: 000021e6 00000001 t0 write SP_VS_CTRL_REG0 (22c4) SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 00055758: 0000: 000022c4 00200c10 t0 write SP_VS_CTRL_REG1 (22c5) SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } 00055760: 0000: 000022c5 01000042 t0 write VPC_ATTR (2140) VPC_ATTR: { TOTALATTR = 8 | THRDASSIGN = 1 | ENABLE | 0x40000000 } 00055768: 0000: 00002140 42001008 t0 write VPC_PACK (2141) VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 8 | NUMNONPOSVSVAR = 6 } 00055770: 0000: 00002141 00060800 t0 write PC_PRIM_VTX_CNTL (21c4) PC_PRIM_VTX_CNTL: { VAROUT = 1 } 00055778: 0000: 000021c4 00000001 t0 write SP_VS_PARAM_REG (22c6) SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 2 } SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r1.w | B_COMPMASK = 0x3 } SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } UNKNOWN_22D7: 0xfcfc00 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 12 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 00055780: 0000: 001922c6 0020fc03 06071e03 00000000 00000000 00000000 00000000 00000000 * 000557c0: 0040: 00000000 00000000 00fcfc00 00000c08 00000000 00000000 00000000 00000000 * t0 write SP_VS_OBJ_OFFSET_REG (22e0) SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 000557ec: 0000: 000022e0 00000000 t0 write SP_VS_OBJ_START (22e1) SP_VS_OBJ_START: 0x1 000557f4: 0000: 000022e1 00000001 t0 write SP_VS_LENGTH_REG (22e5) SP_VS_LENGTH_REG: 2 000557fc: 0000: 000022e5 00000002 t3 opcode: CP_LOAD_STATE4 (30) (67 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } :2:0000:0000[56d81803x_20020003x] (sy)(ss)(nop3) shl.b r0.w, r0.w, 2 :1:0001:0004[20150000x_00000003x] cov.s32s16 hr0.x, r0.w :0:0002:0005[00000200x_00000000x] (rpt2)nop :1:0003:0008[201100f4x_00000000x] mova a0.x, hr0.x :0:0004:0009[00000500x_00000000x] (rpt5)nop :1:0005:0015[20154003x_00000c20x] mov.s32s32 r0.w, c :1:0006:0016[20154004x_00000c21x] mov.s32s32 r1.x, c :1:0007:0017[20154007x_00000c22x] mov.s32s32 r1.w, c :1:0008:0018[20156008x_00000c23x] (ul)mov.s32s32 r2.x, c :1:0009:0019[20554005x_00000000x] mov.s32s32 r1.y, 0 :1:0010:0020[20554006x_3f800000x] mov.s32s32 r1.z, 1065353216 :0:0011:0021[03000000x_00000000x] end :2:0012:0022[46f00009x_20050000x] shr.b r2.y, r0.x, 5 :2:0013:0023[4398000ax_201f0000x] (nop2) and.b r2.z, r0.x, 31 :2:0014:0026[43980809x_201f0009x] (nop3) and.b r2.y, r2.y, 31 :2:0015:0030[46100809x_20180009x] (nop1) mul.u24 r2.y, r2.y, 24 :3:0016:0032[62050009x_00091014x] mad.u24 r2.y, c5.x, r2.z, r2.y :0:0017:0033[00000500x_00000000x] (rpt5)nop :6:0018:0039[c2c61300x_04800006x] stlw.u32 l[r2.y], r0.w, 4 :6:0019:0040[c2c61310x_0280000ex] stlw.u32 l[r2.y+16], r1.w, 2 :0:0020:0041[04800000x_00000000x] chmask :0:0021:0042[05000000x_00000000x] chsh Stats: - shaderdb: 43 instr, 24 nops, 19 non-nops, 7 mov, 1 cov - shaderdb: 0 last-baryf, 0 half, 3 full, 5 constlen - shaderdb: 27 cat0, 8 cat1, 5 cat2, 1 cat3, 0 cat4, 0 cat5, 2 cat6, 0 cat7 - shaderdb: 0 sstall, 1 (ss), 1 (sy) 00055804: 0000: c0413000 00a00000 00000000 20020003 56d81803 00000003 20150000 00000000 00055824: 0020: 00000200 00000000 201100f4 00000000 00000500 00000c20 20154003 00000c21 00055844: 0040: 20154004 00000c22 20154007 00000c23 20156008 00000000 20554005 3f800000 00055864: 0060: 20554006 00000000 03000000 20050000 46f00009 201f0000 4398000a 201f0009 00055884: 0080: 43980809 20180009 46100809 00091014 62050009 00000000 00000500 04800006 000558a4: 00a0: c2c61300 0280000e c2c61310 00000000 04800000 00000000 05000000 00000000 * t0 write HLSQ_CONTROL_3_REG (23c3) HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } 00055910: 0000: 000023c3 fcfcfc00 t0 write HLSQ_CONTROL_4_REG (23c4) HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } 00055918: 0000: 000023c4 00fcfcfc t0 write SP_FS_CTRL_REG0 (22e8) SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 0 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE | PIXLODENABLE } SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 } 00055920: 0000: 000122e8 00700402 8010003e t0 write SP_FS_OBJ_OFFSET_REG (22ea) SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 } 0005592c: 0000: 000022ea 40420000 t0 write SP_FS_OBJ_START (22eb) SP_FS_OBJ_START: 0x1 00055934: 0000: 000022eb 00000001 t0 write SP_FS_LENGTH_REG (22ef) SP_FS_LENGTH_REG: 1 0005593c: 0000: 000022ef 00000001 t0 write SP_FS_OUTPUT_REG (22f0) SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r0.x | SAMPLEMASK_REGID = r0.x } 00055944: 0000: 000022f0 00000001 t0 write VPC_VARYING_INTERP[0].MODE (2142) VPC_VARYING_INTERP[0].MODE: 0xe000 0005594c: 0000: 00002142 0000e000 t0 write RB_FS_OUTPUT_REG (2100) RB_FS_OUTPUT_REG: { MRT = 1 } 00055954: 0000: 00002100 00000001 t3 opcode: CP_LOAD_STATE4 (30) (35 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 1 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } :2:0000:0000[57309902x_00002004x] (sy)(ss)(rpt1)bary.f (ei)r0.z, (r)4, r0.x :0:0001:0002[00000500x_00000000x] (rpt5)nop :5:0002:0008[a0c01f00x_00000005x] sam (f32)(xyzw)r0.x, r0.z, s#0, t#0 :0:0003:0009[03000000x_00000000x] end :0:0004:0010[00000000x_00000000x] nop :0:0005:0011[00000000x_00000000x] nop :0:0006:0012[00000000x_00000000x] nop :0:0007:0013[00000000x_00000000x] nop Stats: - shaderdb: 14 instr, 10 nops, 4 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 0 half, 1 full, 0 constlen - shaderdb: 11 cat0, 0 cat1, 2 cat2, 0 cat3, 0 cat4, 1 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 1 (ss), 1 (sy) 0005595c: 0000: c0213000 00700000 00000000 00002004 57309902 00000000 00000500 00000005 0005597c: 0020: a0c01f00 00000000 03000000 00000000 00000000 00000000 00000000 00000000 * t0 write RB_FS_OUTPUT (20f9) RB_FS_OUTPUT: { ENABLE_BLEND = 0 | SAMPLE_MASK = 0xffff } 000559e8: 0000: 000020f9 ffff0000 t0 write RB_MRT[0].CONTROL (20a4) RB_MRT[0].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0xf } 000559f0: 0000: 000020a4 0f000000 t0 write RB_MRT[0x1].CONTROL (20a9) RB_MRT[0x1].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0xf } 000559f8: 0000: 000020a9 0f000000 t0 write RB_MRT[0].BLEND_CONTROL (20a8) RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } 00055a00: 0000: 000020a8 00000000 t3 opcode: CP_LOAD_STATE4 (30) (5 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_TEX | NUM_UNIT = 1 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } { XY_MAG = A4XX_TEX_NEAREST | XY_MIN = A4XX_TEX_NEAREST | WRAP_S = A4XX_TEX_CLAMP_TO_EDGE | WRAP_T = A4XX_TEX_CLAMP_TO_EDGE | WRAP_R = A4XX_TEX_CLAMP_TO_EDGE | ANISO = A4XX_TEX_ANISO_1 | LOD_BIAS = 0.000000 | 0x60000 } { COMPARE_FUNC = FUNC_LEQUAL | UNNORM_COORDS | MIPFILTER_LINEAR_FAR | MAX_LOD = 0.000000 | MIN_LOD = 0.000000 | 0x1 } 00055a14: 0000: 00060920 00000067 00055a08: 0000: c0033000 00500000 00000000 00060920 00000067 t0 write GRAS_SC_CONTROL (207b) GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 0 | RASTER_MODE = 0 } 00055a1c: 0000: 0000207b 00000000 t0 write RB_MSAA_CONTROL (20a2) RB_MSAA_CONTROL: { SAMPLES = 0 } 00055a24: 0000: 000020a2 00000000 t0 write RB_RENDER_CONTROL (20a1) RB_RENDER_CONTROL: { 0 } 00055a2c: 0000: 000020a1 00000000 t0 write 0x2382 (2382) 0x2382: 00000000 00055a34: 0000: 00002382 00000000 t0 write RB_DEPTH_CONTROL (2101) RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } 00055a3c: 0000: 00002101 00000000 t0 write GRAS_ALPHA_CONTROL (2073) GRAS_ALPHA_CONTROL: { 0 } 00055a44: 0000: 00002073 00000000 t0 write RB_STENCIL_CONTROL (2106) RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } 00055a4c: 0000: 00002106 00000000 t0 write SP_FS_MRT[0].REG (22f1) SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = RB4_R8G8B8A8_UNORM } 00055a54: 0000: 000022f1 0001a000 t0 write RB_MRT[0].BUF_INFO (20a5) RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB4_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE4_3 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 256 } RB_MRT[0].BASE: 0x166000 RB_MRT[0].CONTROL3: { STRIDE = 0 } 00055a5c: 0000: 000220a5 000400da 00166000 00000000 t3 opcode: CP_LOAD_STATE4 (30) (11 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_TEX | NUM_UNIT = 1 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } { TILED | SWIZ_X = A4XX_TEX_X | SWIZ_Y = A4XX_TEX_Y | SWIZ_Z = A4XX_TEX_Z | SWIZ_W = A4XX_TEX_W | MIPLVLS = 0 | FMT = TFMT4_8_8_8_8_UNORM | TYPE = A4XX_TEX_2D | 0x2 } { HEIGHT = 64 | WIDTH = 64 } { PITCHALIGN = 0 | PITCH = 256 | SWAP = WZYX } { LAYERSZ = 0 | DEPTH = 1 | 0x20000 } { LAYERSZ = 4096 | BASE = 0x4f000 } { 5 = 0 } { 6 = 0 } { 7 = 0 } 00055a78: 0000: 27006883 00200040 00020000 00060000 0004f001 00000000 00000000 00000000 00055a6c: 0000: c0093000 00500000 00000001 27006883 00200040 00020000 00060000 0004f001 * t0 write VPC_VARYING_PS_REPL[0].MODE (214a) VPC_VARYING_PS_REPL[0].MODE: 0x99999999 00055a98: 0000: 0000214a 99999999 t0 write GRAS_SC_SCREEN_SCISSOR_TL (207c) GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } 00055aa0: 0000: 0001207c 00000000 003f003f t0 write GRAS_SC_WINDOW_SCISSOR_BR (209c) GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 00055aac: 0000: 0001209c 003f003f 00000000 t0 write RB_FRAME_BUFFER_DIMENSION (0ce0) RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } 00055ab8: 0000: 00000ce0 00400040 t0 write 0xce1 (0ce1) 0xce1: 00000000 00055ac0: 0000: 00000ce1 00000000 t0 write RB_RENDER_CONTROL2 (20a3) RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 | IJ_PERSP_PIXEL } 00055ac8: 0000: 000020a3 00001000 t0 write RB_MODE_CONTROL (20a0) RB_MODE_CONTROL: { WIDTH = 0 | HEIGHT = 0 | 0xc00000 } 00055ad0: 0000: 000020a0 00c00000 t3 opcode: CP_LOAD_STATE4 (30) (11 dwords) { DST_OFF = 8 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } 00055ae4: 0.000000 0.000000 0.000000 0.000000 64.000000 64.000000 64.000000 64.000000 00055ae4: 0000: 00000000 00000000 00000000 00000000 42800000 42800000 42800000 42800000 00055ad8: 0000: c0093000 00a00008 00000001 00000000 00000000 00000000 00000000 42800000 00055af8: 0020: 42800000 42800000 42800000 t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x80000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 2 } draw[49] register values + 00000004 UNKNOWN_0CC5: 0x4 + 00000000 UNKNOWN_0CC6: 0 + 00400040 RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } + 00000000 0xce1: 00000000 + 00000002 HLSQ_MODE_CONTROL: 0x2 + 00000000 UNKNOWN_0E42: 0 + 00000004 SP_MODE_CONTROL: 0x4 + 00000068 TPL1_TP_MODE_CONTROL: 0x68 + 00188000 GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } + 00000000 UNKNOWN_2001: 0 + 00000001 GRAS_CNTL: { IJ_PERSP } !+ 00000000 GRAS_ALPHA_CONTROL: { 0 } + 00000000 GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } !+ 00000000 GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 0 | RASTER_MODE = 0 } + 00000000 GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } + 003f003f GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } + 003f003f GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } + 00000000 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } !+ 00c00000 RB_MODE_CONTROL: { WIDTH = 0 | HEIGHT = 0 | 0xc00000 } !+ 00000000 RB_RENDER_CONTROL: { 0 } !+ 00000000 RB_MSAA_CONTROL: { SAMPLES = 0 } !+ 00001000 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 | IJ_PERSP_PIXEL } !+ 0f000000 RB_MRT[0].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0xf } !+ 000400da RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB4_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE4_3 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 256 } !+ 00166000 RB_MRT[0].BASE: 0x166000 !+ 00000000 RB_MRT[0].CONTROL3: { STRIDE = 0 } + 00000000 RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } + 0f000000 RB_MRT[0x1].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0xf } + 00000e00 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } !+ ffff0000 RB_FS_OUTPUT: { ENABLE_BLEND = 0 | SAMPLE_MASK = 0xffff } + 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } + 00000001 RB_FS_OUTPUT_REG: { MRT = 1 } + 00000000 RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } + 00000000 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } !+ 42001008 VPC_ATTR: { TOTALATTR = 8 | THRDASSIGN = 1 | ENABLE | 0x40000000 } !+ 00060800 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 8 | NUMNONPOSVSVAR = 6 } !+ 0000e000 VPC_VARYING_INTERP[0].MODE: 0xe000 !+ 99999999 VPC_VARYING_PS_REPL[0].MODE: 0x99999999 + 00000000 UNKNOWN_2152: 0 + 00000000 UNKNOWN_2153: 0 + 00000000 UNKNOWN_2154: 0 + 00000000 UNKNOWN_2155: 0 + 00000000 UNKNOWN_2156: 0 + 0000001d UNKNOWN_21C3: 0x1d + 00000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 } + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + 00000000 PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } + 00000001 UNKNOWN_21E6: 0x1 + 000a0000 VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } + fc030000 VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } + fcfcfcfc VFD_CONTROL_2: 0xfcfcfcfc + fcfcfc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } + 0000fcfc VFD_CONTROL_4: 0xfcfc + 00000000 VFD_INDEX_OFFSET: 0 + 00000000 UNKNOWN_2209: 0 + 00060010 SP_SP_CTRL_REG: { 0x60010 } + 000005c3 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } + 00200c10 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } + 01000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } !+ 0020fc03 SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 2 } !+ 06071e03 SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r1.w | B_COMPMASK = 0x3 } + 00000000 SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00fcfc00 UNKNOWN_22D7: 0xfcfc00 !+ 00000c08 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 12 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } + 00000001 SP_VS_OBJ_START: 0x1 + 00000002 SP_VS_LENGTH_REG: 2 !+ 00700402 SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 0 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE | PIXLODENABLE } !+ 8010003e SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 } !+ 40420000 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 } !+ 00000001 SP_FS_OBJ_START: 0x1 + 00000001 SP_FS_LENGTH_REG: 1 !+ 00000001 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r0.x | SAMPLEMASK_REGID = r0.x } !+ 0001a000 SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = RB4_R8G8B8A8_UNORM } + 00000000 TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } !+ 00000000 0x2382: 00000000 + 00000003 TPL1_TP_FS_TEX_COUNT: 0x3 + 080004f0 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } + fcfc0120 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } + 27f3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } + fcfcfc00 HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } !+ 00fcfcfc HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } + 02010042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } !+ 0141423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 1 } + 00404200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00004200 HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } + 00000007 HLSQ_UPDATE_CONTROL: 0x7 00055b04: 0000: c0023800 00080888 00000001 00000002 t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = CACHE_FLUSH } event CACHE_FLUSH 00055b14: 0000: c0004600 00000006 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00055b1c: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0x8000012 00055b24: 0000: 00000cc6 08000012 00173000: 0000: c0013f00 000555d8 00000155 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 0017300c: 0000: c0014300 00040000 00000000 t3 opcode: (null) (1d) (2 dwords) 00173018: 0000: c0001d00 00000000 ############################################################ vertices: 0 ############################################################ cmdstream: 48 dwords t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 0016b000: 0000: c0002600 00000000 t0 write UCHE_INVALIDATE0 (0e8a) UCHE_INVALIDATE0: 0 UCHE_INVALIDATE1: 0x12 0016b008: 0000: 00010e8a 00000000 00000012 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 0016b014: 0000: c0002600 00000000 t0 write RB_MODE_CONTROL (20a0) RB_MODE_CONTROL: { WIDTH = 64 | HEIGHT = 64 | ENABLE_GMEM } 0016b01c: 0000: 000020a0 00010202 t0 write RB_FRAME_BUFFER_DIMENSION (0ce0) RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } 0016b024: 0000: 00000ce0 00400040 t0 write 0xce1 (0ce1) 0xce1: 00000001 0016b02c: 0000: 00000ce1 00000001 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 0016b034: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0 0016b03c: 0000: 00000cc6 00000000 t3 opcode: (null) (1d) (2 dwords) 0016b044: 0000: c0001d00 00000000 t0 write GRAS_SC_WINDOW_SCISSOR_BR (209c) GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 0016b04c: 0000: 0001209c 003f003f 00000000 t0 write RB_BIN_OFFSET (210d) RB_BIN_OFFSET: { X = 0 | Y = 0 } 0016b058: 0000: 0000210d 00000000 t0 write GRAS_SC_WINDOW_SCISSOR_BR (209c) GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 0016b060: 0000: 0001209c 003f003f 00000000 t0 write UNKNOWN_2157 (2157) UNKNOWN_2157: 0x1 0016b06c: 0000: 00002157 00000001 t3 opcode: (null) (64) (2 dwords) 0016b074: 0000: c0006400 00000001 t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:00054994 ibsize:000000f6 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00054994: 0000: c0002600 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x4 0005499c: 0000: 00000ec3 00000004 t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x68 000549a4: 0000: 00000f03 00000068 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 000549ac: 0000: c0002600 00000000 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } 000549b4: 0000: 000023c0 080004f0 t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = 0x1d } event (null) 000549bc: 0000: c0004600 0000001d t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = FACENESS_FLUSH } event FACENESS_FLUSH 000549c4: 0000: c0004600 0000001c t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 000549cc: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0 000549d4: 0000: 00000cc6 00000000 t0 write UNKNOWN_0E42 (0e42) UNKNOWN_0E42: 0 000549dc: 0000: 00000e42 00000000 t0 write HLSQ_MODE_CONTROL (0e05) HLSQ_MODE_CONTROL: 0x2 000549e4: 0000: 00000e05 00000002 t0 write UNKNOWN_0CC5 (0cc5) UNKNOWN_0CC5: 0x4 000549ec: 0000: 00000cc5 00000004 t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x7 000549f4: 0000: 000023db 00000007 t0 write VFD_CONTROL_2 (2202) VFD_CONTROL_2: 0xfcfcfcfc 000549fc: 0000: 00002202 fcfcfcfc t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } 00054a04: 0000: 00002203 fcfcfc00 t0 write VFD_CONTROL_4 (2204) VFD_CONTROL_4: 0xfcfc 00054a0c: 0000: 00002204 0000fcfc t0 write VFD_INDEX_OFFSET (2208) VFD_INDEX_OFFSET: 0 00054a14: 0000: 00002208 00000000 t0 write UNKNOWN_2209 (2209) UNKNOWN_2209: 0 00054a1c: 0000: 00002209 00000000 t0 write UNKNOWN_2152 (2152) UNKNOWN_2152: 0 UNKNOWN_2153: 0 00054a24: 0000: 00012152 00000000 00000000 t0 write UNKNOWN_2156 (2156) UNKNOWN_2156: 0 00054a30: 0000: 00002156 00000000 t0 write UNKNOWN_2154 (2154) UNKNOWN_2154: 0 00054a38: 0000: 00002154 00000000 t0 write UNKNOWN_2155 (2155) UNKNOWN_2155: 0 00054a40: 0000: 00002155 00000000 t0 write UNKNOWN_21C3 (21c3) UNKNOWN_21C3: 0x1d 00054a48: 0000: 000021c3 0000001d t0 write PC_PRIM_VTX_CNTL2 (21c5) PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 00054a50: 0000: 000021c5 00000012 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 00054a58: 0000: 000021e5 00000000 t0 write GRAS_SU_MODE_CONTROL (2078) GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } 00054a60: 0000: 00002078 00000000 t0 write UNKNOWN_2001 (2001) UNKNOWN_2001: 0 00054a68: 0000: 00002001 00000000 t0 write GRAS_CNTL (2003) GRAS_CNTL: { IJ_PERSP } 00054a70: 0000: 00002003 00000001 t0 write GRAS_CL_CLIP_CNTL (2000) GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } 00054a78: 0000: 00002000 00188000 t0 write TPL1_TP_TEX_COUNT (2381) TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } 00054a80: 0000: 00002381 00000000 t0 write TPL1_TP_FS_TEX_COUNT (23a0) TPL1_TP_FS_TEX_COUNT: 0x3 00054a88: 0000: 000023a0 00000003 t0 write RB_ALPHA_CONTROL (20f8) RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } 00054a90: 0000: 000020f8 00000e00 t0 write RB_RENDER_COMPONENTS (20fb) RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } 00054a98: 0000: 000020fb 0000000f t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 00054aa0: 0000: c0014300 00040000 00000000 t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } 00054aac: 0000: 00002200 000a0000 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } 00054ab4: 0000: 00002201 fc030000 t0 write SP_INSTR_CACHE_CTRL (22c1) SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } 00054abc: 0000: 000022c1 000005c3 t0 write HLSQ_CONTROL_1_REG (23c1) HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } 00054ac4: 0000: 000023c1 fcfc0120 t0 write HLSQ_CONTROL_2_REG (23c2) HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 00054acc: 0000: 000023c2 27f3f3f0 t0 write HLSQ_VS_CONTROL_REG (23c5) HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } 00054ad4: 0000: 000023c5 02010042 t0 write HLSQ_FS_CONTROL_REG (23c6) HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00054adc: 0000: 000023c6 0041423e t0 write HLSQ_HS_CONTROL_REG (23c7) HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00054ae4: 0000: 000023c7 00404200 t0 write HLSQ_DS_CONTROL_REG (23c8) HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00054aec: 0000: 000023c8 00404200 t0 write HLSQ_GS_CONTROL_REG (23c9) HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00054af4: 0000: 000023c9 00404200 t0 write HLSQ_CS_CONTROL_REG (23ca) HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } 00054afc: 0000: 000023ca 00004200 t0 write SP_SP_CTRL_REG (22c0) SP_SP_CTRL_REG: { 0x60010 } 00054b04: 0000: 000022c0 00060010 t0 write UNKNOWN_21E6 (21e6) UNKNOWN_21E6: 0x1 00054b0c: 0000: 000021e6 00000001 t0 write SP_VS_CTRL_REG0 (22c4) SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 00054b14: 0000: 000022c4 00200c10 t0 write SP_VS_CTRL_REG1 (22c5) SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } 00054b1c: 0000: 000022c5 01000042 t0 write VPC_ATTR (2140) VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | 0x40000000 } 00054b24: 0000: 00002140 40001004 t0 write VPC_PACK (2141) VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } 00054b2c: 0000: 00002141 00040400 t0 write PC_PRIM_VTX_CNTL (21c4) PC_PRIM_VTX_CNTL: { VAROUT = 1 } 00054b34: 0000: 000021c4 00000001 t0 write SP_VS_PARAM_REG (22c6) SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } UNKNOWN_22D7: 0xfcfc00 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 00054b3c: 0000: 001922c6 0010fc03 00001e03 00000000 00000000 00000000 00000000 00000000 * 00054b7c: 0040: 00000000 00000000 00fcfc00 00000008 00000000 00000000 00000000 00000000 * t0 write SP_VS_OBJ_OFFSET_REG (22e0) SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 00054ba8: 0000: 000022e0 00000000 t0 write SP_VS_OBJ_START (22e1) SP_VS_OBJ_START: 0x1 00054bb0: 0000: 000022e1 00000001 t0 write SP_VS_LENGTH_REG (22e5) SP_VS_LENGTH_REG: 2 00054bb8: 0000: 000022e5 00000002 t3 opcode: CP_LOAD_STATE4 (30) (67 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } :2:0000:0000[56d81803x_20020003x] (sy)(ss)(nop3) shl.b r0.w, r0.w, 2 :1:0001:0004[20150000x_00000003x] cov.s32s16 hr0.x, r0.w :0:0002:0005[00000200x_00000000x] (rpt2)nop :1:0003:0008[201100f4x_00000000x] mova a0.x, hr0.x :0:0004:0009[00000500x_00000000x] (rpt5)nop :1:0005:0015[20154003x_00000c20x] mov.s32s32 r0.w, c :1:0006:0016[20154004x_00000c21x] mov.s32s32 r1.x, c :1:0007:0017[20154005x_00000c22x] mov.s32s32 r1.y, c :1:0008:0018[20156006x_00000c23x] (ul)mov.s32s32 r1.z, c :0:0009:0019[03000000x_00000000x] end :2:0010:0020[46f00007x_20050000x] shr.b r1.w, r0.x, 5 :2:0011:0021[43980008x_201f0000x] (nop2) and.b r2.x, r0.x, 31 :2:0012:0024[43980807x_201f0007x] (nop3) and.b r1.w, r1.w, 31 :2:0013:0028[46100807x_20100007x] (nop1) mul.u24 r1.w, r1.w, 16 :3:0014:0030[62040007x_00071014x] mad.u24 r1.w, c5.x, r2.x, r1.w :0:0015:0031[00000500x_00000000x] (rpt5)nop :6:0016:0037[c2c60f00x_04800006x] stlw.u32 l[r1.w], r0.w, 4 :0:0017:0038[04800000x_00000000x] chmask :0:0018:0039[05000000x_00000000x] chsh Stats: - shaderdb: 40 instr, 24 nops, 16 non-nops, 5 mov, 1 cov - shaderdb: 0 last-baryf, 0 half, 2 full, 5 constlen - shaderdb: 27 cat0, 6 cat1, 5 cat2, 1 cat3, 0 cat4, 0 cat5, 1 cat6, 0 cat7 - shaderdb: 0 sstall, 1 (ss), 1 (sy) 00054bc0: 0000: c0413000 00a00000 00000000 20020003 56d81803 00000003 20150000 00000000 00054be0: 0020: 00000200 00000000 201100f4 00000000 00000500 00000c20 20154003 00000c21 00054c00: 0040: 20154004 00000c22 20154005 00000c23 20156006 00000000 03000000 20050000 00054c20: 0060: 46f00007 201f0000 43980008 201f0007 43980807 20100007 46100807 00071014 00054c40: 0080: 62040007 00000000 00000500 04800006 c2c60f00 00000000 04800000 00000000 00054c60: 00a0: 05000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 * t0 write GRAS_ALPHA_CONTROL (2073) GRAS_ALPHA_CONTROL: { 0x2 } 00054ccc: 0000: 00002073 00000002 t0 write GRAS_SC_CONTROL (207b) GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = 4 | MSAA_DISABLE | RASTER_MODE = 0 } 00054cd4: 0000: 0000207b 00000a08 t0 write RB_MSAA_CONTROL (20a2) RB_MSAA_CONTROL: { DISABLE | SAMPLES = 4 } 00054cdc: 0000: 000020a2 00009000 t0 write RB_RENDER_CONTROL (20a1) RB_RENDER_CONTROL: { DISABLE_COLOR_PIPE | 0x2 } 00054ce4: 0000: 000020a1 00000022 t0 write RB_CLEAR_COLOR_DW0 (20cc) RB_CLEAR_COLOR_DW0: 0xff000000 RB_CLEAR_COLOR_DW1: 0 RB_CLEAR_COLOR_DW2: 0 RB_CLEAR_COLOR_DW3: 0 00054cec: 0000: 000320cc ff000000 00000000 00000000 00000000 t0 write RB_COPY_CONTROL (20fc) RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_FOUR | MODE = RB_COPY_CLEAR | FASTCLEAR = 0xf | GMEM_BASE = 0 } RB_COPY_DEST_BASE: { BASE = 0x4f000 } RB_COPY_DEST_PITCH: { PITCH = 256 } RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_IF_ALPHA_OFF | COMPONENT_ENABLE = 0 | ENDIAN = ENDIAN_NONE | TILE = TILE4_3 } 00054d00: 0000: 000320fc 00000f22 0004f000 00000008 03000868 t0 write GRAS_SC_SCREEN_SCISSOR_TL (207c) GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } 00054d14: 0000: 0001207c 00000000 003f003f t0 write RB_FRAME_BUFFER_DIMENSION (0ce0) RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } 00054d20: 0000: 00000ce0 00400040 t0 write 0xce1 (0ce1) 0xce1: 00000000 00054d28: 0000: 00000ce1 00000000 t3 opcode: CP_LOAD_STATE4 (30) (11 dwords) { DST_OFF = 8 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } 00054d3c: 0.000000 0.000000 1.000000 1.000000 64.000000 64.000000 1.000000 1.000000 00054d3c: 0000: 00000000 00000000 3f800000 3f800000 42800000 42800000 3f800000 3f800000 00054d30: 0000: c0093000 00a00008 00000001 00000000 00000000 3f800000 3f800000 42800000 00054d50: 0020: 42800000 3f800000 3f800000 t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x80000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 2 } draw[50] register values + 00000004 UNKNOWN_0CC5: 0x4 + 00000000 UNKNOWN_0CC6: 0 + 00400040 RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } + 00000000 0xce1: 00000000 + 00000002 HLSQ_MODE_CONTROL: 0x2 + 00000000 UNKNOWN_0E42: 0 + 00000000 UCHE_INVALIDATE0: 0 + 00000012 UCHE_INVALIDATE1: 0x12 + 00000004 SP_MODE_CONTROL: 0x4 + 00000068 TPL1_TP_MODE_CONTROL: 0x68 + 00188000 GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } + 00000000 UNKNOWN_2001: 0 + 00000001 GRAS_CNTL: { IJ_PERSP } !+ 00000002 GRAS_ALPHA_CONTROL: { 0x2 } + 00000000 GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } !+ 00000a08 GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = 4 | MSAA_DISABLE | RASTER_MODE = 0 } + 00000000 GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } + 003f003f GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } + 003f003f GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } + 00000000 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } !+ 00010202 RB_MODE_CONTROL: { WIDTH = 64 | HEIGHT = 64 | ENABLE_GMEM } !+ 00000022 RB_RENDER_CONTROL: { DISABLE_COLOR_PIPE | 0x2 } !+ 00009000 RB_MSAA_CONTROL: { DISABLE | SAMPLES = 4 } + ff000000 RB_CLEAR_COLOR_DW0: 0xff000000 + 00000000 RB_CLEAR_COLOR_DW1: 0 + 00000000 RB_CLEAR_COLOR_DW2: 0 + 00000000 RB_CLEAR_COLOR_DW3: 0 + 00000e00 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } + 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } !+ 00000f22 RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_FOUR | MODE = RB_COPY_CLEAR | FASTCLEAR = 0xf | GMEM_BASE = 0 } + 0004f000 RB_COPY_DEST_BASE: { BASE = 0x4f000 } + 00000008 RB_COPY_DEST_PITCH: { PITCH = 256 } !+ 03000868 RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_IF_ALPHA_OFF | COMPONENT_ENABLE = 0 | ENDIAN = ENDIAN_NONE | TILE = TILE4_3 } + 00000000 RB_BIN_OFFSET: { X = 0 | Y = 0 } !+ 40001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | 0x40000000 } !+ 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } + 00000000 UNKNOWN_2152: 0 + 00000000 UNKNOWN_2153: 0 + 00000000 UNKNOWN_2154: 0 + 00000000 UNKNOWN_2155: 0 + 00000000 UNKNOWN_2156: 0 + 00000001 UNKNOWN_2157: 0x1 + 0000001d UNKNOWN_21C3: 0x1d + 00000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 } + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + 00000000 PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } + 00000001 UNKNOWN_21E6: 0x1 + 000a0000 VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } + fc030000 VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } + fcfcfcfc VFD_CONTROL_2: 0xfcfcfcfc + fcfcfc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } + 0000fcfc VFD_CONTROL_4: 0xfcfc + 00000000 VFD_INDEX_OFFSET: 0 + 00000000 UNKNOWN_2209: 0 + 00060010 SP_SP_CTRL_REG: { 0x60010 } + 000005c3 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } + 00200c10 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } + 01000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } !+ 0010fc03 SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } !+ 00001e03 SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00fcfc00 UNKNOWN_22D7: 0xfcfc00 !+ 00000008 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } + 00000001 SP_VS_OBJ_START: 0x1 + 00000002 SP_VS_LENGTH_REG: 2 + 00000000 TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } + 00000003 TPL1_TP_FS_TEX_COUNT: 0x3 + 080004f0 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } + fcfc0120 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } + 27f3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } + 02010042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } !+ 0041423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00004200 HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } + 00000007 HLSQ_UPDATE_CONTROL: 0x7 00054d5c: 0000: c0023800 00080888 00000001 00000002 0016b07c: 0000: c0013f00 00054994 000000f6 t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:00054d6c ibsize:00000037 t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } 00054d6c: 0000: 00002200 082a0008 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00054d74: 0000: c0002600 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x1e 00054d7c: 0000: 00000ec3 0000001e t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x28 00054d84: 0000: 00000f03 00000028 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00054d8c: 0000: c0002600 00000000 t0 write HLSQ_MODE_CONTROL (0e05) HLSQ_MODE_CONTROL: 0x1 00054d94: 0000: 00000e05 00000001 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0x600a0 } 00054d9c: 0000: 000023c0 080604f0 t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x7 00054da4: 0000: 000023db 00000007 t0 write PC_RESTART_INDEX (21c6) PC_RESTART_INDEX: 0xffffffff 00054dac: 0000: 000021c6 ffffffff t0 write UNKNOWN_21E6 (21e6) UNKNOWN_21E6: 0x1 00054db4: 0000: 000021e6 00000001 t0 write UNKNOWN_21C3 (21c3) UNKNOWN_21C3: 0x1f 00054dbc: 0000: 000021c3 0000001f t0 write TPL1_TP_TEX_OFFSET (2380) TPL1_TP_TEX_OFFSET: 0x808 00054dc4: 0000: 00002380 00000808 t0 write GRAS_SU_POINT_MINMAX (2070) GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 4092.000000 } GRAS_SU_POINT_SIZE: 0.500000 00054dcc: 0000: 00012070 ffc00010 00000008 t0 write UNKNOWN_2152 (2152) UNKNOWN_2152: 0 UNKNOWN_2153: 0 00054dd8: 0000: 00012152 00000000 00000000 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00054de4: 0000: c0002600 00000000 t0 write UNKNOWN_0CC5 (0cc5) UNKNOWN_0CC5: 0x4 00054dec: 0000: 00000cc5 00000004 t0 write 0xcc4 (0cc4) 0xcc4: 00000000 00054df4: 0000: 00000cc4 00000000 t0 write 0xd03 (0d03) 0xd03: 80200000 00054dfc: 0000: 00000d03 80200000 t0 write UNKNOWN_0EC2 (0ec2) UNKNOWN_0EC2: 0x40000 00054e04: 0000: 00000ec2 00040000 t0 write VPC_DEBUG_ECO_CONTROL (0e64) VPC_DEBUG_ECO_CONTROL: 0x100 00054e0c: 0000: 00000e64 00000100 t0 write UNKNOWN_0E42 (0e42) UNKNOWN_0E42: 0 00054e14: 0000: 00000e42 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x1e 00054e1c: 0000: 00000ec3 0000001e t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x28 00054e24: 0000: 00000f03 00000028 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 00054e2c: 0000: c0014300 00040000 00000000 t0 write VFD_INDEX_OFFSET (2208) VFD_INDEX_OFFSET: 0 00054e38: 0000: 00002208 00000000 t0 write UNKNOWN_2209 (2209) UNKNOWN_2209: 0 00054e40: 0000: 00002209 00000000 0016b088: 0000: c0013f00 00054d6c 00000037 t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:00055328 ibsize:000000ac t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x3 00055328: 0000: 000023db 00000003 t0 write SP_INSTR_CACHE_CTRL (22c1) SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } 00055330: 0000: 000022c1 000005c3 t0 write HLSQ_CONTROL_1_REG (23c1) HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x1008 } 00055338: 0000: 000023c1 fcfc1108 t0 write HLSQ_CONTROL_2_REG (23c2) HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 00055340: 0000: 000023c2 fff3f3f0 t0 write HLSQ_VS_CONTROL_REG (23c5) HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 2 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 1 } 00055348: 0000: 000023c5 01010002 t0 write HLSQ_HS_CONTROL_REG (23c7) HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 00055350: 0000: 000023c7 007e0200 t0 write HLSQ_DS_CONTROL_REG (23c8) HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 00055358: 0000: 000023c8 007e0200 t0 write HLSQ_GS_CONTROL_REG (23c9) HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 00055360: 0000: 000023c9 007e0200 t0 write HLSQ_FS_CONTROL_REG (23c6) HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 2 | CONSTOBJECTOFFSET = 2 | ENABLED | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 } 00055368: 0000: 000023c6 017f0202 t0 write SP_VS_OBJ_OFFSET_REG (22e0) SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 00055370: 0000: 000022e0 00000000 t0 write SP_HS_OBJ_OFFSET_REG (230d) SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } 00055378: 0000: 0000230d 7e020000 t0 write SP_DS_OBJ_OFFSET_REG (2334) SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } 00055380: 0000: 00002334 7e020000 t0 write SP_GS_OBJ_OFFSET_REG (235b) SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } 00055388: 0000: 0000235b 7e020000 t0 write SP_FS_OBJ_OFFSET_REG (22ea) SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } 00055390: 0000: 000022ea 7e020000 t0 write SP_VS_OBJ_START (22e1) SP_VS_OBJ_START: 0x49000 00049000: 0000: 00000000 13000000 00000000 00000000 00000000 00000000 00000000 00000000 * :0:0000:0000[13000000x_00000000x] (sy)end :0:0001:0001[00000000x_00000000x] nop :0:0002:0002[00000000x_00000000x] nop :0:0003:0003[00000000x_00000000x] nop :0:0004:0004[00000000x_00000000x] nop Stats: - shaderdb: 5 instr, 4 nops, 1 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 0 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 0 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) 00055398: 0000: 000022e1 00049000 t0 write SP_HS_OBJ_START (230e) SP_HS_OBJ_START: 0 000553a0: 0000: 0000230e 00000000 t0 write SP_DS_OBJ_START (2335) SP_DS_OBJ_START: 0 000553a8: 0000: 00002335 00000000 t0 write SP_GS_OBJ_START (235c) SP_GS_OBJ_START: 0 000553b0: 0000: 0000235c 00000000 t0 write SP_VS_LENGTH_REG (22e5) SP_VS_LENGTH_REG: 1 000553b8: 0000: 000022e5 00000001 t3 opcode: CP_LOAD_STATE4 (30) (3 dwords) { DST_OFF = 0 | STATE_SRC = SS4_INDIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 1 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0x49000 } :0:0000:0000[13000000x_00000000x] (sy)end :0:0001:0001[00000000x_00000000x] nop :0:0002:0002[00000000x_00000000x] nop :0:0003:0003[00000000x_00000000x] nop :0:0004:0004[00000000x_00000000x] nop Stats: - shaderdb: 5 instr, 4 nops, 1 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 0 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 0 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) 000553c0: 0000: c0013000 00620000 00049000 t0 write 0x2072 (2072) 0x2072: 00000000 000553cc: 0000: 00002072 00000000 t0 write UNKNOWN_2155 (2155) UNKNOWN_2155: 0 000553d4: 0000: 00002155 00000000 t0 write GRAS_CNTL (2003) GRAS_CNTL: { IJ_PERSP } 000553dc: 0000: 00002003 00000001 t0 write VPC_VARYING_INTERP[0].MODE (2142) VPC_VARYING_INTERP[0].MODE: 0 000553e4: 0000: 00002142 00000000 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0x600a0 } 000553ec: 0000: 000023c0 080604f0 t0 write HLSQ_CONTROL_3_REG (23c3) HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } 000553f4: 0000: 000023c3 fcfcfc00 t0 write HLSQ_CONTROL_4_REG (23c4) HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r0.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } 000553fc: 0000: 000023c4 00fcfc00 t0 write SP_FS_CTRL_REG0 (22e8) SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE } SP_FS_CTRL_REG1: { CONSTLENGTH = 2 | VARYING | 0x80000000 } 00055404: 0000: 000122e8 00340412 80100002 t0 write SP_FS_OBJ_START (22eb) SP_FS_OBJ_START: 0x46000 00046000: 0000: 00002000 5730cb00 00000000 03000000 00000000 00000000 00000000 00000000 * :2:0000:0000[5730cb00x_00002000x] (sy)(rpt3)bary.f (ei)hr0.x, (r)0, r0.x :0:0001:0004[03000000x_00000000x] end :0:0002:0005[00000000x_00000000x] nop :0:0003:0006[00000000x_00000000x] nop :0:0004:0007[00000000x_00000000x] nop :0:0005:0008[00000000x_00000000x] nop Stats: - shaderdb: 9 instr, 4 nops, 5 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 1 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 4 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) 00055410: 0000: 000022eb 00046000 t0 write SP_FS_LENGTH_REG (22ef) SP_FS_LENGTH_REG: 1 00055418: 0000: 000022ef 00000001 t0 write RB_RENDER_COMPONENTS (20fb) RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } 00055420: 0000: 000020fb 0000000f t3 opcode: CP_LOAD_STATE4 (30) (3 dwords) { DST_OFF = 0 | STATE_SRC = SS4_INDIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 1 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0x46000 } :2:0000:0000[5730cb00x_00002000x] (sy)(rpt3)bary.f (ei)hr0.x, (r)0, r0.x :0:0001:0004[03000000x_00000000x] end :0:0002:0005[00000000x_00000000x] nop :0:0003:0006[00000000x_00000000x] nop :0:0004:0007[00000000x_00000000x] nop :0:0005:0008[00000000x_00000000x] nop Stats: - shaderdb: 9 instr, 4 nops, 5 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 1 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 4 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) 00055428: 0000: c0013000 00720000 00046000 t0 write SP_SP_CTRL_REG (22c0) SP_SP_CTRL_REG: { 0x60010 } 00055434: 0000: 000022c0 00060010 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 28 | GROUP_ID = 3 } { ADDR_LO = 0x9b400 } 0005543c: 0000: c0014300 0300001c 0009b400 t0 write RB_DEPTH_INFO (2103) RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTH4_NONE | DEPTH_BASE = 0 } RB_DEPTH_PITCH: 0 RB_DEPTH_PITCH2: 0 00055448: 0000: 00022103 00000000 00000000 00000000 t0 write GRAS_DEPTH_CONTROL (2077) GRAS_DEPTH_CONTROL: { FORMAT = DEPTH4_NONE } 00055458: 0000: 00002077 00000000 t0 write RB_STENCIL_INFO (2108) RB_STENCIL_INFO: { STENCIL_BASE = 0 } RB_STENCIL_PITCH: 0 0x210a: 00000000 00055460: 0000: 00022108 00000000 00000000 00000000 t0 write 0x2002 (2002) 0x2002: 00000000 00055470: 0000: 00002002 00000000 t0 write RB_ALPHA_CONTROL (20f8) RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } 00055478: 0000: 000020f8 00000e00 t0 write RB_MRT[0].CONTROL (20a4) RB_MRT[0].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0x7 } 00055480: 0000: 000020a4 07000c00 t0 write RB_MRT[0].BLEND_CONTROL (20a8) RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } 00055488: 0000: 000020a8 00000000 t0 write GRAS_CL_CLIP_CNTL (2000) GRAS_CL_CLIP_CNTL: { 0x80000 } 00055490: 0000: 00002000 00080000 t0 write GRAS_SU_POLY_OFFSET_SCALE (2074) GRAS_SU_POLY_OFFSET_SCALE: 0.000000 GRAS_SU_POLY_OFFSET_OFFSET: 0.000000 GRAS_SU_POLY_OFFSET_CLAMP: 0.000000 00055498: 0000: 00022074 00000000 00000000 00000000 t0 write GRAS_SU_MODE_CONTROL (2078) GRAS_SU_MODE_CONTROL: { FRONT_CW | LINEHALFWIDTH = 0.500000 | MSAA_ENABLE | RENDERING_PASS } 000554a8: 0000: 00002078 00102014 t0 write GRAS_SC_SCREEN_SCISSOR_TL (207c) GRAS_SC_SCREEN_SCISSOR_TL: { X = 2 | Y = 13 } GRAS_SC_SCREEN_SCISSOR_BR: { X = 33 | Y = 44 } 000554b0: 0000: 0001207c 000d0002 002c0021 t0 write GRAS_CL_VPORT_XOFFSET_0 (2008) GRAS_CL_VPORT_XOFFSET_0: 18.000000 GRAS_CL_VPORT_XSCALE_0: 16.000000 GRAS_CL_VPORT_YOFFSET_0: 29.000000 GRAS_CL_VPORT_YSCALE_0: 16.000000 GRAS_CL_VPORT_ZOFFSET_0: 0.500000 GRAS_CL_VPORT_ZSCALE_0: 0.500000 000554bc: 0000: 00052008 41900000 41800000 41e80000 41800000 3f000000 3f000000 t0 write GRAS_CL_GB_CLIP_ADJ (2004) GRAS_CL_GB_CLIP_ADJ: { HORZ = 511 | VERT = 511 } 000554d8: 0000: 00002004 0007fdff t0 write GRAS_SC_CONTROL (207b) GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 4 | RASTER_MODE = 0 } 000554e0: 0000: 0000207b 00000200 t0 write 0x2382 (2382) 0x2382: 00000002 000554e8: 0000: 00002382 00000002 t0 write RB_MSAA_CONTROL (20a2) RB_MSAA_CONTROL: { SAMPLES = 4 } 000554f0: 0000: 000020a2 00008000 t0 write RB_RENDER_CONTROL2 (20a3) RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 4 | IJ_PERSP_PIXEL } 000554f8: 0000: 000020a3 00001200 t0 write RB_MRT[0].BUF_INFO (20a5) RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB4_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_ALWAYS | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 1024 } RB_MRT[0].BASE: 0 RB_MRT[0].CONTROL3: { STRIDE = 64 } 00055500: 0000: 000220a5 0010029a 00000000 00000200 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 43 | GROUP_ID = 2 } { ADDR_LO = 0x9b470 } 00055510: 0000: c0014300 0200002b 0009b470 t0 write 0x215c (215c) 0x215c: 00000000 0x215d: 00000000 0005551c: 0000: 0001215c 00000000 00000000 t0 write 0x215f (215f) 0x215f: 00000000 00055528: 0000: 0000215f 00000000 t0 write 0x215e (215e) 0x215e: 00000000 00055530: 0000: 0000215e 00000000 t0 write 0x2161 (2161) 0x2161: 00000000 0x2162: 00000000 00055538: 0000: 00012161 00000000 00000000 t0 write 0x2164 (2164) 0x2164: 00000000 00055544: 0000: 00002164 00000000 t0 write 0x2163 (2163) 0x2163: 00000000 0005554c: 0000: 00002163 00000000 t0 write 0x2166 (2166) 0x2166: 00000000 0x2167: 00000000 00055554: 0000: 00012166 00000000 00000000 t0 write 0x2169 (2169) 0x2169: 00000000 00055560: 0000: 00002169 00000000 t0 write 0x2168 (2168) 0x2168: 00000000 00055568: 0000: 00002168 00000000 t0 write 0x216b (216b) 0x216b: 00000000 0x216c: 00000000 00055570: 0000: 0001216b 00000000 00000000 t0 write VPC_SO_FLUSH_WADDR_3 (216e) VPC_SO_FLUSH_WADDR_3: 0 0005557c: 0000: 0000216e 00000000 t0 write 0x216d (216d) 0x216d: 00000000 00055584: 0000: 0000216d 00000000 t0 write UNKNOWN_2156 (2156) UNKNOWN_2156: 0 0005558c: 0000: 00002156 00000000 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 18 | GROUP_ID = 1 } { ADDR_LO = 0x9b520 } 00055594: 0000: c0014300 01000012 0009b520 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 15 | GROUP_ID = 0 } { ADDR_LO = 0x9b570 } 000555a0: 0000: c0014300 0000000f 0009b570 group_id: 0 count: 15 addr: 000000000009b570 flags: 0 0009b570: 0000: 00002073 00000000 00002101 00000000 00002106 00000000 000021e5 00000000 0009b590: 0020: 0001210b 00000000 00000000 00002381 00000000 000023a0 00000000 t0 write GRAS_ALPHA_CONTROL (2073) GRAS_ALPHA_CONTROL: { 0 } 0009b570: 0000: 00002073 00000000 t0 write RB_DEPTH_CONTROL (2101) RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } 0009b578: 0000: 00002101 00000000 t0 write RB_STENCIL_CONTROL (2106) RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } 0009b580: 0000: 00002106 00000000 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 0009b588: 0000: 000021e5 00000000 t0 write RB_STENCILREFMASK (210b) RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 0009b590: 0000: 0001210b 00000000 00000000 t0 write TPL1_TP_TEX_COUNT (2381) TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } 0009b59c: 0000: 00002381 00000000 t0 write TPL1_TP_FS_TEX_COUNT (23a0) TPL1_TP_FS_TEX_COUNT: 0 0009b5a4: 0000: 000023a0 00000000 group_id: 1 count: 18 addr: 000000000009b520 flags: 0 0009b520: 0000: 00002200 082a0008 00002201 fcfc0081 00002203 0000fc00 0007220a 0008080f 0009b540: 0020: 0009b3a0 00000060 00000001 0000080f 0009b3d0 00000030 00000001 0001228a 0009b560: 0040: 7000411f 3000011f t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } 0009b520: 0000: 00002200 082a0008 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } 0009b528: 0000: 00002201 fcfc0081 t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } 0009b530: 0000: 00002203 0000fc00 t0 write VFD_FETCH[0].INSTR_0 (220a) VFD_FETCH[0].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 | SWITCHNEXT } VFD_FETCH[0].INSTR_1: 0x9b3a0 VFD_FETCH[0].INSTR_2: { SIZE = 0x60 } VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 } VFD_FETCH[0x1].INSTR_1: 0x9b3d0 VFD_FETCH[0x1].INSTR_2: { SIZE = 0x30 } VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } 0009b538: 0000: 0007220a 0008080f 0009b3a0 00000060 00000001 0000080f 0009b3d0 00000030 0009b558: 0020: 00000001 t0 write VFD_DECODE[0].INSTR (228a) VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID | SWITCHNEXT } VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID } 0009b55c: 0000: 0001228a 7000411f 3000011f group_id: 2 count: 43 addr: 000000000009b470 flags: 0 0009b470: 0000: 000020a1 00000000 000022f1 0001a100 000022f0 fc00fc01 00002100 00000001 0009b490: 0020: 000021e5 00000000 000020f9 ffff0501 0000214a 00000000 00002140 42001004 0009b4b0: 0040: 001922c6 0010fc04 00001e00 00000000 00000000 00000000 00000000 00000000 * 0009b4f0: 0080: 00000000 00000000 00fcfc00 00000008 00000000 00000000 00000000 00000000 * t0 write RB_RENDER_CONTROL (20a1) RB_RENDER_CONTROL: { 0 } 0009b470: 0000: 000020a1 00000000 t0 write SP_FS_MRT[0].REG (22f1) SP_FS_MRT[0].REG: { REGID = r0.x | HALF_PRECISION | MRTFORMAT = RB4_R8G8B8A8_UNORM } 0009b478: 0000: 000022f1 0001a100 t0 write SP_FS_OUTPUT_REG (22f0) SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 0009b480: 0000: 000022f0 fc00fc01 t0 write RB_FS_OUTPUT_REG (2100) RB_FS_OUTPUT_REG: { MRT = 1 } 0009b488: 0000: 00002100 00000001 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 0009b490: 0000: 000021e5 00000000 t0 write RB_FS_OUTPUT (20f9) RB_FS_OUTPUT: { ENABLE_BLEND = 0x1 | INDEPENDENT_BLEND | SAMPLE_MASK = 0xffff | 0x400 } 0009b498: 0000: 000020f9 ffff0501 t0 write VPC_VARYING_PS_REPL[0].MODE (214a) VPC_VARYING_PS_REPL[0].MODE: 0 0009b4a0: 0000: 0000214a 00000000 t0 write VPC_ATTR (2140) VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 } 0009b4a8: 0000: 00002140 42001004 t0 write SP_VS_PARAM_REG (22c6) SP_VS_PARAM_REG: { POSREGID = r1.x | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } SP_VS_OUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } UNKNOWN_22D7: 0xfcfc00 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 0009b4b0: 0000: 001922c6 0010fc04 00001e00 00000000 00000000 00000000 00000000 00000000 * 0009b4f0: 0040: 00000000 00000000 00fcfc00 00000008 00000000 00000000 00000000 00000000 * group_id: 3 count: 28 addr: 000000000009b400 flags: 0 0009b400: 0000: 000021c4 02000001 00002141 00040400 00002001 00000000 000022c4 00200800 0009b420: 0020: 000022c5 08000002 0000230c 00000000 00002318 00000000 00002319 00000000 0009b440: 0040: 00002340 00000000 00002202 fcfcfcfc 00002204 0000fcfc 00002154 00000000 0009b460: 0060: 000021e7 00000000 000021c5 00000012 t0 write PC_PRIM_VTX_CNTL (21c4) PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } 0009b400: 0000: 000021c4 02000001 t0 write VPC_PACK (2141) VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } 0009b408: 0000: 00002141 00040400 t0 write UNKNOWN_2001 (2001) UNKNOWN_2001: 0 0009b410: 0000: 00002001 00000000 t0 write SP_VS_CTRL_REG0 (22c4) SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 2 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 0009b418: 0000: 000022c4 00200800 t0 write SP_VS_CTRL_REG1 (22c5) SP_VS_CTRL_REG1: { CONSTLENGTH = 2 | INITIALOUTSTANDING = 8 } 0009b420: 0000: 000022c5 08000002 t0 write 0x230c (230c) 0x230c: 00000000 0009b428: 0000: 0000230c 00000000 t0 write 0x2318 (2318) 0x2318: 00000000 0009b430: 0000: 00002318 00000000 t0 write 0x2319 (2319) 0x2319: 00000000 0009b438: 0000: 00002319 00000000 t0 write 0x2340 (2340) 0x2340: 00000000 0009b440: 0000: 00002340 00000000 t0 write VFD_CONTROL_2 (2202) VFD_CONTROL_2: 0xfcfcfcfc 0009b448: 0000: 00002202 fcfcfcfc t0 write VFD_CONTROL_4 (2204) VFD_CONTROL_4: 0xfcfc 0009b450: 0000: 00002204 0000fcfc t0 write UNKNOWN_2154 (2154) UNKNOWN_2154: 0 0009b458: 0000: 00002154 00000000 t0 write PC_HS_PARAM (21e7) PC_HS_PARAM: { VERTICES_OUT = 0 | SPACING = EQUAL_SPACING } 0009b460: 0000: 000021e7 00000000 t0 write PC_PRIM_VTX_CNTL2 (21c5) PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 0009b468: 0000: 000021c5 00000012 t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = USE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x200000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 3 } draw[51] register values + 00000000 0xcc4: 00000000 + 00000004 UNKNOWN_0CC5: 0x4 + 80200000 0xd03: 80200000 !+ 00000001 HLSQ_MODE_CONTROL: 0x1 + 00000000 UNKNOWN_0E42: 0 + 00000100 VPC_DEBUG_ECO_CONTROL: 0x100 + 00040000 UNKNOWN_0EC2: 0x40000 !+ 0000001e SP_MODE_CONTROL: 0x1e !+ 00000028 TPL1_TP_MODE_CONTROL: 0x28 !+ 00080000 GRAS_CL_CLIP_CNTL: { 0x80000 } + 00000000 UNKNOWN_2001: 0 + 00000000 0x2002: 00000000 + 00000001 GRAS_CNTL: { IJ_PERSP } + 0007fdff GRAS_CL_GB_CLIP_ADJ: { HORZ = 511 | VERT = 511 } + 41900000 GRAS_CL_VPORT_XOFFSET_0: 18.000000 + 41800000 GRAS_CL_VPORT_XSCALE_0: 16.000000 + 41e80000 GRAS_CL_VPORT_YOFFSET_0: 29.000000 + 41800000 GRAS_CL_VPORT_YSCALE_0: 16.000000 + 3f000000 GRAS_CL_VPORT_ZOFFSET_0: 0.500000 + 3f000000 GRAS_CL_VPORT_ZSCALE_0: 0.500000 + ffc00010 GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 4092.000000 } + 00000008 GRAS_SU_POINT_SIZE: 0.500000 + 00000000 0x2072: 00000000 !+ 00000000 GRAS_ALPHA_CONTROL: { 0 } + 00000000 GRAS_SU_POLY_OFFSET_SCALE: 0.000000 + 00000000 GRAS_SU_POLY_OFFSET_OFFSET: 0.000000 + 00000000 GRAS_SU_POLY_OFFSET_CLAMP: 0.000000 + 00000000 GRAS_DEPTH_CONTROL: { FORMAT = DEPTH4_NONE } !+ 00102014 GRAS_SU_MODE_CONTROL: { FRONT_CW | LINEHALFWIDTH = 0.500000 | MSAA_ENABLE | RENDERING_PASS } !+ 00000200 GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 4 | RASTER_MODE = 0 } !+ 000d0002 GRAS_SC_SCREEN_SCISSOR_TL: { X = 2 | Y = 13 } !+ 002c0021 GRAS_SC_SCREEN_SCISSOR_BR: { X = 33 | Y = 44 } !+ 00000000 RB_RENDER_CONTROL: { 0 } !+ 00008000 RB_MSAA_CONTROL: { SAMPLES = 4 } !+ 00001200 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 4 | IJ_PERSP_PIXEL } !+ 07000c00 RB_MRT[0].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0x7 } !+ 0010029a RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB4_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_ALWAYS | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 1024 } !+ 00000000 RB_MRT[0].BASE: 0 !+ 00000200 RB_MRT[0].CONTROL3: { STRIDE = 64 } + 00000000 RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } + 00000e00 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } !+ ffff0501 RB_FS_OUTPUT: { ENABLE_BLEND = 0x1 | INDEPENDENT_BLEND | SAMPLE_MASK = 0xffff | 0x400 } + 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } + 00000001 RB_FS_OUTPUT_REG: { MRT = 1 } + 00000000 RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } + 00000000 RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTH4_NONE | DEPTH_BASE = 0 } + 00000000 RB_DEPTH_PITCH: 0 + 00000000 RB_DEPTH_PITCH2: 0 + 00000000 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } + 00000000 RB_STENCIL_INFO: { STENCIL_BASE = 0 } + 00000000 RB_STENCIL_PITCH: 0 + 00000000 0x210a: 00000000 + 00000000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } + 00000000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } !+ 42001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 } + 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } !+ 00000000 VPC_VARYING_INTERP[0].MODE: 0 !+ 00000000 VPC_VARYING_PS_REPL[0].MODE: 0 + 00000000 UNKNOWN_2152: 0 + 00000000 UNKNOWN_2153: 0 + 00000000 UNKNOWN_2154: 0 + 00000000 UNKNOWN_2155: 0 + 00000000 UNKNOWN_2156: 0 + 00000000 0x215c: 00000000 + 00000000 0x215d: 00000000 + 00000000 0x215e: 00000000 + 00000000 0x215f: 00000000 + 00000000 0x2161: 00000000 + 00000000 0x2162: 00000000 + 00000000 0x2163: 00000000 + 00000000 0x2164: 00000000 + 00000000 0x2166: 00000000 + 00000000 0x2167: 00000000 + 00000000 0x2168: 00000000 + 00000000 0x2169: 00000000 + 00000000 0x216b: 00000000 + 00000000 0x216c: 00000000 + 00000000 0x216d: 00000000 + 00000000 VPC_SO_FLUSH_WADDR_3: 0 !+ 0000001f UNKNOWN_21C3: 0x1f !+ 02000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + ffffffff PC_RESTART_INDEX: 0xffffffff + 00000000 PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } + 00000001 UNKNOWN_21E6: 0x1 + 00000000 PC_HS_PARAM: { VERTICES_OUT = 0 | SPACING = EQUAL_SPACING } !+ 082a0008 VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } !+ fcfc0081 VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } + fcfcfcfc VFD_CONTROL_2: 0xfcfcfcfc !+ 0000fc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } + 0000fcfc VFD_CONTROL_4: 0xfcfc + 00000000 VFD_INDEX_OFFSET: 0 + 00000000 UNKNOWN_2209: 0 + 0008080f VFD_FETCH[0].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 | SWITCHNEXT } !+ 0009b3a0 VFD_FETCH[0].INSTR_1: 0x9b3a0 + 00000060 VFD_FETCH[0].INSTR_2: { SIZE = 0x60 } + 00000001 VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } + 0000080f VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 } !+ 0009b3d0 VFD_FETCH[0x1].INSTR_1: 0x9b3d0 + 00000030 VFD_FETCH[0x1].INSTR_2: { SIZE = 0x30 } + 00000001 VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } + 7000411f VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID | SWITCHNEXT } + 3000011f VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID } + 00060010 SP_SP_CTRL_REG: { 0x60010 } + 000005c3 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } !+ 00200800 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 2 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } !+ 08000002 SP_VS_CTRL_REG1: { CONSTLENGTH = 2 | INITIALOUTSTANDING = 8 } !+ 0010fc04 SP_VS_PARAM_REG: { POSREGID = r1.x | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } !+ 00001e00 SP_VS_OUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00fcfc00 UNKNOWN_22D7: 0xfcfc00 + 00000008 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } !+ 00049000 SP_VS_OBJ_START: 0x49000 00049000: 0000: 00000000 13000000 00000000 00000000 00000000 00000000 00000000 00000000 * :0:0000:0000[13000000x_00000000x] (sy)end :0:0001:0001[00000000x_00000000x] nop :0:0002:0002[00000000x_00000000x] nop :0:0003:0003[00000000x_00000000x] nop :0:0004:0004[00000000x_00000000x] nop Stats: - shaderdb: 5 instr, 4 nops, 1 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 0 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 0 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) !+ 00000001 SP_VS_LENGTH_REG: 1 !+ 00340412 SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE } !+ 80100002 SP_FS_CTRL_REG1: { CONSTLENGTH = 2 | VARYING | 0x80000000 } !+ 7e020000 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } !+ 00046000 SP_FS_OBJ_START: 0x46000 00046000: 0000: 00002000 5730cb00 00000000 03000000 00000000 00000000 00000000 00000000 * :2:0000:0000[5730cb00x_00002000x] (sy)(rpt3)bary.f (ei)hr0.x, (r)0, r0.x :0:0001:0004[03000000x_00000000x] end :0:0002:0005[00000000x_00000000x] nop :0:0003:0006[00000000x_00000000x] nop :0:0004:0007[00000000x_00000000x] nop :0:0005:0008[00000000x_00000000x] nop Stats: - shaderdb: 9 instr, 4 nops, 5 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 1 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 4 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) + 00000001 SP_FS_LENGTH_REG: 1 !+ fc00fc01 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r63.x } !+ 0001a100 SP_FS_MRT[0].REG: { REGID = r0.x | HALF_PRECISION | MRTFORMAT = RB4_R8G8B8A8_UNORM } + 00000000 0x230c: 00000000 + 7e020000 SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } + 00000000 SP_HS_OBJ_START: 0 + 00000000 0x2318: 00000000 + 00000000 0x2319: 00000000 + 7e020000 SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } + 00000000 SP_DS_OBJ_START: 0 + 00000000 0x2340: 00000000 + 7e020000 SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } + 00000000 SP_GS_OBJ_START: 0 + 00000808 TPL1_TP_TEX_OFFSET: 0x808 + 00000000 TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } !+ 00000002 0x2382: 00000002 !+ 00000000 TPL1_TP_FS_TEX_COUNT: 0 !+ 080604f0 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0x600a0 } !+ fcfc1108 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x1008 } !+ fff3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } + fcfcfc00 HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } !+ 00fcfc00 HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r0.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } !+ 01010002 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 2 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 1 } !+ 017f0202 HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 2 | CONSTOBJECTOFFSET = 2 | ENABLED | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 } !+ 007e0200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } !+ 007e0200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } !+ 007e0200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } !+ 00000003 HLSQ_UPDATE_CONTROL: 0x3 000555ac: 0000: c0023800 00200984 00000001 00000003 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 18 | GROUP_ID = 1 } { ADDR_LO = 0x9b6e0 } 000555bc: 0000: c0014300 01000012 0009b6e0 group_id: 1 count: 18 addr: 000000000009b6e0 flags: 0 0009b6e0: 0000: 00002200 082a0008 00002201 fcfc0081 00002203 0000fc00 0007220a 0008080f 0009b700: 0020: 0009b680 00000060 00000001 0000080f 0009b6b0 00000030 00000001 0001228a 0009b720: 0040: 7000411f 3000011f t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } 0009b6e0: 0000: 00002200 082a0008 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } 0009b6e8: 0000: 00002201 fcfc0081 t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } 0009b6f0: 0000: 00002203 0000fc00 t0 write VFD_FETCH[0].INSTR_0 (220a) VFD_FETCH[0].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 | SWITCHNEXT } VFD_FETCH[0].INSTR_1: 0x9b680 VFD_FETCH[0].INSTR_2: { SIZE = 0x60 } VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 } VFD_FETCH[0x1].INSTR_1: 0x9b6b0 VFD_FETCH[0x1].INSTR_2: { SIZE = 0x30 } VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } 0009b6f8: 0000: 0007220a 0008080f 0009b680 00000060 00000001 0000080f 0009b6b0 00000030 0009b718: 0020: 00000001 t0 write VFD_DECODE[0].INSTR (228a) VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID | SWITCHNEXT } VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID } 0009b71c: 0000: 0001228a 7000411f 3000011f t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = USE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x200000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 3 } draw[52] register values + 082a0008 VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } + fcfc0081 VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } + 0000fc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } + 0008080f VFD_FETCH[0].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 | SWITCHNEXT } !+ 0009b680 VFD_FETCH[0].INSTR_1: 0x9b680 + 00000060 VFD_FETCH[0].INSTR_2: { SIZE = 0x60 } + 00000001 VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } + 0000080f VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 } !+ 0009b6b0 VFD_FETCH[0x1].INSTR_1: 0x9b6b0 + 00000030 VFD_FETCH[0x1].INSTR_2: { SIZE = 0x30 } + 00000001 VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } + 7000411f VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID | SWITCHNEXT } + 3000011f VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID } 000555c8: 0000: c0023800 00200984 00000001 00000003 0016b094: 0000: c0013f00 00055328 000000ac t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 0016b0a0: 0000: c0014300 00040000 00000000 t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:001f96a0 ibsize:000000f7 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 001f96a0: 0000: c0002600 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x4 001f96a8: 0000: 00000ec3 00000004 t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x68 001f96b0: 0000: 00000f03 00000068 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 001f96b8: 0000: c0002600 00000000 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } 001f96c0: 0000: 000023c0 080004f0 t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = 0x1d } event (null) 001f96c8: 0000: c0004600 0000001d t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = FACENESS_FLUSH } event FACENESS_FLUSH 001f96d0: 0000: c0004600 0000001c t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 001f96d8: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0 001f96e0: 0000: 00000cc6 00000000 t0 write UNKNOWN_0E42 (0e42) UNKNOWN_0E42: 0 001f96e8: 0000: 00000e42 00000000 t0 write HLSQ_MODE_CONTROL (0e05) HLSQ_MODE_CONTROL: 0x2 001f96f0: 0000: 00000e05 00000002 t0 write UNKNOWN_0CC5 (0cc5) UNKNOWN_0CC5: 0x4 001f96f8: 0000: 00000cc5 00000004 t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x7 001f9700: 0000: 000023db 00000007 t0 write VFD_CONTROL_2 (2202) VFD_CONTROL_2: 0xfcfcfcfc 001f9708: 0000: 00002202 fcfcfcfc t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } 001f9710: 0000: 00002203 fcfcfc00 t0 write VFD_CONTROL_4 (2204) VFD_CONTROL_4: 0xfcfc 001f9718: 0000: 00002204 0000fcfc t0 write VFD_INDEX_OFFSET (2208) VFD_INDEX_OFFSET: 0 001f9720: 0000: 00002208 00000000 t0 write UNKNOWN_2209 (2209) UNKNOWN_2209: 0 001f9728: 0000: 00002209 00000000 t0 write UNKNOWN_2152 (2152) UNKNOWN_2152: 0 UNKNOWN_2153: 0 001f9730: 0000: 00012152 00000000 00000000 t0 write UNKNOWN_2156 (2156) UNKNOWN_2156: 0 001f973c: 0000: 00002156 00000000 t0 write UNKNOWN_2154 (2154) UNKNOWN_2154: 0 001f9744: 0000: 00002154 00000000 t0 write UNKNOWN_2155 (2155) UNKNOWN_2155: 0 001f974c: 0000: 00002155 00000000 t0 write UNKNOWN_21C3 (21c3) UNKNOWN_21C3: 0x1d 001f9754: 0000: 000021c3 0000001d t0 write PC_PRIM_VTX_CNTL2 (21c5) PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 001f975c: 0000: 000021c5 00000012 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 001f9764: 0000: 000021e5 00000000 t0 write GRAS_SU_MODE_CONTROL (2078) GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } 001f976c: 0000: 00002078 00000000 t0 write UNKNOWN_2001 (2001) UNKNOWN_2001: 0 001f9774: 0000: 00002001 00000000 t0 write GRAS_CNTL (2003) GRAS_CNTL: { IJ_PERSP } 001f977c: 0000: 00002003 00000001 t0 write GRAS_CL_CLIP_CNTL (2000) GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } 001f9784: 0000: 00002000 00188000 t0 write TPL1_TP_TEX_COUNT (2381) TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } 001f978c: 0000: 00002381 00000000 t0 write TPL1_TP_FS_TEX_COUNT (23a0) TPL1_TP_FS_TEX_COUNT: 0x3 001f9794: 0000: 000023a0 00000003 t0 write RB_ALPHA_CONTROL (20f8) RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } 001f979c: 0000: 000020f8 00000e00 t0 write RB_RENDER_COMPONENTS (20fb) RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } 001f97a4: 0000: 000020fb 0000000f t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 001f97ac: 0000: c0014300 00040000 00000000 t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } 001f97b8: 0000: 00002200 000a0000 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } 001f97c0: 0000: 00002201 fc030000 t0 write SP_INSTR_CACHE_CTRL (22c1) SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } 001f97c8: 0000: 000022c1 000005c3 t0 write HLSQ_CONTROL_1_REG (23c1) HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } 001f97d0: 0000: 000023c1 fcfc0120 t0 write HLSQ_CONTROL_2_REG (23c2) HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 001f97d8: 0000: 000023c2 27f3f3f0 t0 write HLSQ_VS_CONTROL_REG (23c5) HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } 001f97e0: 0000: 000023c5 02010042 t0 write HLSQ_FS_CONTROL_REG (23c6) HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 001f97e8: 0000: 000023c6 0041423e t0 write HLSQ_HS_CONTROL_REG (23c7) HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 001f97f0: 0000: 000023c7 00404200 t0 write HLSQ_DS_CONTROL_REG (23c8) HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 001f97f8: 0000: 000023c8 00404200 t0 write HLSQ_GS_CONTROL_REG (23c9) HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 001f9800: 0000: 000023c9 00404200 t0 write HLSQ_CS_CONTROL_REG (23ca) HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } 001f9808: 0000: 000023ca 00004200 t0 write SP_SP_CTRL_REG (22c0) SP_SP_CTRL_REG: { 0x60010 } 001f9810: 0000: 000022c0 00060010 t0 write UNKNOWN_21E6 (21e6) UNKNOWN_21E6: 0x1 001f9818: 0000: 000021e6 00000001 t0 write SP_VS_CTRL_REG0 (22c4) SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 001f9820: 0000: 000022c4 00200c10 t0 write SP_VS_CTRL_REG1 (22c5) SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } 001f9828: 0000: 000022c5 01000042 t0 write VPC_ATTR (2140) VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | 0x40000000 } 001f9830: 0000: 00002140 40001004 t0 write VPC_PACK (2141) VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } 001f9838: 0000: 00002141 00040400 t0 write PC_PRIM_VTX_CNTL (21c4) PC_PRIM_VTX_CNTL: { VAROUT = 1 } 001f9840: 0000: 000021c4 00000001 t0 write SP_VS_PARAM_REG (22c6) SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } UNKNOWN_22D7: 0xfcfc00 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 001f9848: 0000: 001922c6 0010fc03 00001e03 00000000 00000000 00000000 00000000 00000000 * 001f9888: 0040: 00000000 00000000 00fcfc00 00000008 00000000 00000000 00000000 00000000 * t0 write SP_VS_OBJ_OFFSET_REG (22e0) SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 001f98b4: 0000: 000022e0 00000000 t0 write SP_VS_OBJ_START (22e1) SP_VS_OBJ_START: 0x1 001f98bc: 0000: 000022e1 00000001 t0 write SP_VS_LENGTH_REG (22e5) SP_VS_LENGTH_REG: 2 001f98c4: 0000: 000022e5 00000002 t3 opcode: CP_LOAD_STATE4 (30) (67 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } :2:0000:0000[56d81803x_20020003x] (sy)(ss)(nop3) shl.b r0.w, r0.w, 2 :1:0001:0004[20150000x_00000003x] cov.s32s16 hr0.x, r0.w :0:0002:0005[00000200x_00000000x] (rpt2)nop :1:0003:0008[201100f4x_00000000x] mova a0.x, hr0.x :0:0004:0009[00000500x_00000000x] (rpt5)nop :1:0005:0015[20154003x_00000c20x] mov.s32s32 r0.w, c :1:0006:0016[20154004x_00000c21x] mov.s32s32 r1.x, c :1:0007:0017[20154005x_00000c22x] mov.s32s32 r1.y, c :1:0008:0018[20156006x_00000c23x] (ul)mov.s32s32 r1.z, c :0:0009:0019[03000000x_00000000x] end :2:0010:0020[46f00007x_20050000x] shr.b r1.w, r0.x, 5 :2:0011:0021[43980008x_201f0000x] (nop2) and.b r2.x, r0.x, 31 :2:0012:0024[43980807x_201f0007x] (nop3) and.b r1.w, r1.w, 31 :2:0013:0028[46100807x_20100007x] (nop1) mul.u24 r1.w, r1.w, 16 :3:0014:0030[62040007x_00071014x] mad.u24 r1.w, c5.x, r2.x, r1.w :0:0015:0031[00000500x_00000000x] (rpt5)nop :6:0016:0037[c2c60f00x_04800006x] stlw.u32 l[r1.w], r0.w, 4 :0:0017:0038[04800000x_00000000x] chmask :0:0018:0039[05000000x_00000000x] chsh Stats: - shaderdb: 40 instr, 24 nops, 16 non-nops, 5 mov, 1 cov - shaderdb: 0 last-baryf, 0 half, 2 full, 5 constlen - shaderdb: 27 cat0, 6 cat1, 5 cat2, 1 cat3, 0 cat4, 0 cat5, 1 cat6, 0 cat7 - shaderdb: 0 sstall, 1 (ss), 1 (sy) 001f98cc: 0000: c0413000 00a00000 00000000 20020003 56d81803 00000003 20150000 00000000 001f98ec: 0020: 00000200 00000000 201100f4 00000000 00000500 00000c20 20154003 00000c21 001f990c: 0040: 20154004 00000c22 20154005 00000c23 20156006 00000000 03000000 20050000 001f992c: 0060: 46f00007 201f0000 43980008 201f0007 43980807 20100007 46100807 00071014 001f994c: 0080: 62040007 00000000 00000500 04800006 c2c60f00 00000000 04800000 00000000 001f996c: 00a0: 05000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 * t0 write GRAS_SC_CONTROL (207b) GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = 0 | MSAA_DISABLE | RASTER_MODE = 0 } 001f99d8: 0000: 0000207b 00000808 t0 write RB_MSAA_CONTROL (20a2) RB_MSAA_CONTROL: { DISABLE | SAMPLES = 0 } 001f99e0: 0000: 000020a2 00001000 t0 write RB_RENDER_CONTROL (20a1) RB_RENDER_CONTROL: { DISABLE_COLOR_PIPE | 0x2 } 001f99e8: 0000: 000020a1 00000022 t0 write RB_DEPTH_CONTROL (2101) RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } 001f99f0: 0000: 00002101 00000000 t0 write GRAS_ALPHA_CONTROL (2073) GRAS_ALPHA_CONTROL: { 0x2 } 001f99f8: 0000: 00002073 00000002 t0 write RB_STENCIL_CONTROL (2106) RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } 001f9a00: 0000: 00002106 00000000 t0 write RB_COPY_CONTROL (20fc) RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_FOUR | MODE = RB_COPY_DEPTH_STENCIL | FASTCLEAR = 0 | GMEM_BASE = 0 } RB_COPY_DEST_BASE: { BASE = 0x4f000 } RB_COPY_DEST_PITCH: { PITCH = 256 } RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_DISABLE | COMPONENT_ENABLE = 0xf | ENDIAN = ENDIAN_NONE | TILE = TILE4_3 } 001f9a08: 0000: 000320fc 00000052 0004f000 00000008 0303c068 t0 write UNKNOWN_20EF (20ef) UNKNOWN_20EF: 0 001f9a1c: 0000: 000020ef 00000000 t0 write GRAS_SC_SCREEN_SCISSOR_TL (207c) GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } 001f9a24: 0000: 0001207c 00000000 003f003f t0 write RB_FRAME_BUFFER_DIMENSION (0ce0) RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } 001f9a30: 0000: 00000ce0 00400040 t0 write 0xce1 (0ce1) 0xce1: 00000000 001f9a38: 0000: 00000ce1 00000000 t3 opcode: CP_LOAD_STATE4 (30) (11 dwords) { DST_OFF = 8 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } 001f9a4c: 0.000000 0.000000 1.000000 1.000000 64.000000 64.000000 1.000000 1.000000 001f9a4c: 0000: 00000000 00000000 3f800000 3f800000 42800000 42800000 3f800000 3f800000 001f9a40: 0000: c0093000 00a00008 00000001 00000000 00000000 3f800000 3f800000 42800000 001f9a60: 0020: 42800000 3f800000 3f800000 t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x80000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 2 } draw[53] register values + 00000004 UNKNOWN_0CC5: 0x4 + 00000000 UNKNOWN_0CC6: 0 + 00400040 RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } + 00000000 0xce1: 00000000 !+ 00000002 HLSQ_MODE_CONTROL: 0x2 + 00000000 UNKNOWN_0E42: 0 !+ 00000004 SP_MODE_CONTROL: 0x4 !+ 00000068 TPL1_TP_MODE_CONTROL: 0x68 !+ 00188000 GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } + 00000000 UNKNOWN_2001: 0 + 00000001 GRAS_CNTL: { IJ_PERSP } !+ 00000002 GRAS_ALPHA_CONTROL: { 0x2 } !+ 00000000 GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } !+ 00000808 GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = 0 | MSAA_DISABLE | RASTER_MODE = 0 } !+ 00000000 GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } !+ 003f003f GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } !+ 00000022 RB_RENDER_CONTROL: { DISABLE_COLOR_PIPE | 0x2 } !+ 00001000 RB_MSAA_CONTROL: { DISABLE | SAMPLES = 0 } + 00000000 UNKNOWN_20EF: 0 + 00000e00 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } + 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } !+ 00000052 RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_FOUR | MODE = RB_COPY_DEPTH_STENCIL | FASTCLEAR = 0 | GMEM_BASE = 0 } + 0004f000 RB_COPY_DEST_BASE: { BASE = 0x4f000 } + 00000008 RB_COPY_DEST_PITCH: { PITCH = 256 } !+ 0303c068 RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_DISABLE | COMPONENT_ENABLE = 0xf | ENDIAN = ENDIAN_NONE | TILE = TILE4_3 } + 00000000 RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } + 00000000 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } !+ 40001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | 0x40000000 } + 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } + 00000000 UNKNOWN_2152: 0 + 00000000 UNKNOWN_2153: 0 + 00000000 UNKNOWN_2154: 0 + 00000000 UNKNOWN_2155: 0 + 00000000 UNKNOWN_2156: 0 !+ 0000001d UNKNOWN_21C3: 0x1d !+ 00000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 } + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + 00000000 PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } + 00000001 UNKNOWN_21E6: 0x1 !+ 000a0000 VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } !+ fc030000 VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } + fcfcfcfc VFD_CONTROL_2: 0xfcfcfcfc !+ fcfcfc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } + 0000fcfc VFD_CONTROL_4: 0xfcfc + 00000000 VFD_INDEX_OFFSET: 0 + 00000000 UNKNOWN_2209: 0 + 00060010 SP_SP_CTRL_REG: { 0x60010 } + 000005c3 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } !+ 00200c10 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } !+ 01000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } !+ 0010fc03 SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } !+ 00001e03 SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00fcfc00 UNKNOWN_22D7: 0xfcfc00 + 00000008 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } !+ 00000001 SP_VS_OBJ_START: 0x1 !+ 00000002 SP_VS_LENGTH_REG: 2 + 00000000 TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } !+ 00000003 TPL1_TP_FS_TEX_COUNT: 0x3 !+ 080004f0 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } !+ fcfc0120 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } !+ 27f3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } !+ 02010042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } !+ 0041423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } !+ 00404200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } !+ 00404200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } !+ 00404200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00004200 HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } !+ 00000007 HLSQ_UPDATE_CONTROL: 0x7 001f9a6c: 0000: c0023800 00080888 00000001 00000002 0016b0ac: 0000: c0013f00 001f96a0 000000f7 t3 opcode: (null) (1d) (2 dwords) 0016b0b8: 0000: c0001d00 00000000 ############################################################ vertices: 0 ############################################################ cmdstream: 8 dwords t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:000555d8 ibsize:00000155 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 000555d8: 0000: c0002600 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x4 000555e0: 0000: 00000ec3 00000004 t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x68 000555e8: 0000: 00000f03 00000068 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 000555f0: 0000: c0002600 00000000 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } 000555f8: 0000: 000023c0 080004f0 t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = 0x1d } event (null) 00055600: 0000: c0004600 0000001d t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = FACENESS_FLUSH } event FACENESS_FLUSH 00055608: 0000: c0004600 0000001c t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00055610: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0 00055618: 0000: 00000cc6 00000000 t0 write UNKNOWN_0E42 (0e42) UNKNOWN_0E42: 0 00055620: 0000: 00000e42 00000000 t0 write HLSQ_MODE_CONTROL (0e05) HLSQ_MODE_CONTROL: 0x2 00055628: 0000: 00000e05 00000002 t0 write UNKNOWN_0CC5 (0cc5) UNKNOWN_0CC5: 0x4 00055630: 0000: 00000cc5 00000004 t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x7 00055638: 0000: 000023db 00000007 t0 write VFD_CONTROL_2 (2202) VFD_CONTROL_2: 0xfcfcfcfc 00055640: 0000: 00002202 fcfcfcfc t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } 00055648: 0000: 00002203 fcfcfc00 t0 write VFD_CONTROL_4 (2204) VFD_CONTROL_4: 0xfcfc 00055650: 0000: 00002204 0000fcfc t0 write VFD_INDEX_OFFSET (2208) VFD_INDEX_OFFSET: 0 00055658: 0000: 00002208 00000000 t0 write UNKNOWN_2209 (2209) UNKNOWN_2209: 0 00055660: 0000: 00002209 00000000 t0 write UNKNOWN_2152 (2152) UNKNOWN_2152: 0 UNKNOWN_2153: 0 00055668: 0000: 00012152 00000000 00000000 t0 write UNKNOWN_2156 (2156) UNKNOWN_2156: 0 00055674: 0000: 00002156 00000000 t0 write UNKNOWN_2154 (2154) UNKNOWN_2154: 0 0005567c: 0000: 00002154 00000000 t0 write UNKNOWN_2155 (2155) UNKNOWN_2155: 0 00055684: 0000: 00002155 00000000 t0 write UNKNOWN_21C3 (21c3) UNKNOWN_21C3: 0x1d 0005568c: 0000: 000021c3 0000001d t0 write PC_PRIM_VTX_CNTL2 (21c5) PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 00055694: 0000: 000021c5 00000012 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 0005569c: 0000: 000021e5 00000000 t0 write GRAS_SU_MODE_CONTROL (2078) GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } 000556a4: 0000: 00002078 00000000 t0 write UNKNOWN_2001 (2001) UNKNOWN_2001: 0 000556ac: 0000: 00002001 00000000 t0 write GRAS_CNTL (2003) GRAS_CNTL: { IJ_PERSP } 000556b4: 0000: 00002003 00000001 t0 write GRAS_CL_CLIP_CNTL (2000) GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } 000556bc: 0000: 00002000 00188000 t0 write TPL1_TP_TEX_COUNT (2381) TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } 000556c4: 0000: 00002381 00000000 t0 write TPL1_TP_FS_TEX_COUNT (23a0) TPL1_TP_FS_TEX_COUNT: 0x3 000556cc: 0000: 000023a0 00000003 t0 write RB_ALPHA_CONTROL (20f8) RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } 000556d4: 0000: 000020f8 00000e00 t0 write RB_RENDER_COMPONENTS (20fb) RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } 000556dc: 0000: 000020fb 0000000f t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 000556e4: 0000: c0014300 00040000 00000000 t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } 000556f0: 0000: 00002200 000a0000 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } 000556f8: 0000: 00002201 fc030000 t0 write SP_INSTR_CACHE_CTRL (22c1) SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } 00055700: 0000: 000022c1 000005c3 t0 write HLSQ_CONTROL_1_REG (23c1) HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } 00055708: 0000: 000023c1 fcfc0120 t0 write HLSQ_CONTROL_2_REG (23c2) HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 00055710: 0000: 000023c2 27f3f3f0 t0 write HLSQ_VS_CONTROL_REG (23c5) HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } 00055718: 0000: 000023c5 02010042 t0 write HLSQ_FS_CONTROL_REG (23c6) HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 1 } 00055720: 0000: 000023c6 0141423e t0 write HLSQ_HS_CONTROL_REG (23c7) HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00055728: 0000: 000023c7 00404200 t0 write HLSQ_DS_CONTROL_REG (23c8) HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00055730: 0000: 000023c8 00404200 t0 write HLSQ_GS_CONTROL_REG (23c9) HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00055738: 0000: 000023c9 00404200 t0 write HLSQ_CS_CONTROL_REG (23ca) HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } 00055740: 0000: 000023ca 00004200 t0 write SP_SP_CTRL_REG (22c0) SP_SP_CTRL_REG: { 0x60010 } 00055748: 0000: 000022c0 00060010 t0 write UNKNOWN_21E6 (21e6) UNKNOWN_21E6: 0x1 00055750: 0000: 000021e6 00000001 t0 write SP_VS_CTRL_REG0 (22c4) SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 00055758: 0000: 000022c4 00200c10 t0 write SP_VS_CTRL_REG1 (22c5) SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } 00055760: 0000: 000022c5 01000042 t0 write VPC_ATTR (2140) VPC_ATTR: { TOTALATTR = 8 | THRDASSIGN = 1 | ENABLE | 0x40000000 } 00055768: 0000: 00002140 42001008 t0 write VPC_PACK (2141) VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 8 | NUMNONPOSVSVAR = 6 } 00055770: 0000: 00002141 00060800 t0 write PC_PRIM_VTX_CNTL (21c4) PC_PRIM_VTX_CNTL: { VAROUT = 1 } 00055778: 0000: 000021c4 00000001 t0 write SP_VS_PARAM_REG (22c6) SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 2 } SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r1.w | B_COMPMASK = 0x3 } SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } UNKNOWN_22D7: 0xfcfc00 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 12 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 00055780: 0000: 001922c6 0020fc03 06071e03 00000000 00000000 00000000 00000000 00000000 * 000557c0: 0040: 00000000 00000000 00fcfc00 00000c08 00000000 00000000 00000000 00000000 * t0 write SP_VS_OBJ_OFFSET_REG (22e0) SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 000557ec: 0000: 000022e0 00000000 t0 write SP_VS_OBJ_START (22e1) SP_VS_OBJ_START: 0x1 000557f4: 0000: 000022e1 00000001 t0 write SP_VS_LENGTH_REG (22e5) SP_VS_LENGTH_REG: 2 000557fc: 0000: 000022e5 00000002 t3 opcode: CP_LOAD_STATE4 (30) (67 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } :2:0000:0000[56d81803x_20020003x] (sy)(ss)(nop3) shl.b r0.w, r0.w, 2 :1:0001:0004[20150000x_00000003x] cov.s32s16 hr0.x, r0.w :0:0002:0005[00000200x_00000000x] (rpt2)nop :1:0003:0008[201100f4x_00000000x] mova a0.x, hr0.x :0:0004:0009[00000500x_00000000x] (rpt5)nop :1:0005:0015[20154003x_00000c20x] mov.s32s32 r0.w, c :1:0006:0016[20154004x_00000c21x] mov.s32s32 r1.x, c :1:0007:0017[20154007x_00000c22x] mov.s32s32 r1.w, c :1:0008:0018[20156008x_00000c23x] (ul)mov.s32s32 r2.x, c :1:0009:0019[20554005x_00000000x] mov.s32s32 r1.y, 0 :1:0010:0020[20554006x_3f800000x] mov.s32s32 r1.z, 1065353216 :0:0011:0021[03000000x_00000000x] end :2:0012:0022[46f00009x_20050000x] shr.b r2.y, r0.x, 5 :2:0013:0023[4398000ax_201f0000x] (nop2) and.b r2.z, r0.x, 31 :2:0014:0026[43980809x_201f0009x] (nop3) and.b r2.y, r2.y, 31 :2:0015:0030[46100809x_20180009x] (nop1) mul.u24 r2.y, r2.y, 24 :3:0016:0032[62050009x_00091014x] mad.u24 r2.y, c5.x, r2.z, r2.y :0:0017:0033[00000500x_00000000x] (rpt5)nop :6:0018:0039[c2c61300x_04800006x] stlw.u32 l[r2.y], r0.w, 4 :6:0019:0040[c2c61310x_0280000ex] stlw.u32 l[r2.y+16], r1.w, 2 :0:0020:0041[04800000x_00000000x] chmask :0:0021:0042[05000000x_00000000x] chsh Stats: - shaderdb: 43 instr, 24 nops, 19 non-nops, 7 mov, 1 cov - shaderdb: 0 last-baryf, 0 half, 3 full, 5 constlen - shaderdb: 27 cat0, 8 cat1, 5 cat2, 1 cat3, 0 cat4, 0 cat5, 2 cat6, 0 cat7 - shaderdb: 0 sstall, 1 (ss), 1 (sy) 00055804: 0000: c0413000 00a00000 00000000 20020003 56d81803 00000003 20150000 00000000 00055824: 0020: 00000200 00000000 201100f4 00000000 00000500 00000c20 20154003 00000c21 00055844: 0040: 20154004 00000c22 20154007 00000c23 20156008 00000000 20554005 3f800000 00055864: 0060: 20554006 00000000 03000000 20050000 46f00009 201f0000 4398000a 201f0009 00055884: 0080: 43980809 20180009 46100809 00091014 62050009 00000000 00000500 04800006 000558a4: 00a0: c2c61300 0280000e c2c61310 00000000 04800000 00000000 05000000 00000000 * t0 write HLSQ_CONTROL_3_REG (23c3) HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } 00055910: 0000: 000023c3 fcfcfc00 t0 write HLSQ_CONTROL_4_REG (23c4) HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } 00055918: 0000: 000023c4 00fcfcfc t0 write SP_FS_CTRL_REG0 (22e8) SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 0 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE | PIXLODENABLE } SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 } 00055920: 0000: 000122e8 00700402 8010003e t0 write SP_FS_OBJ_OFFSET_REG (22ea) SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 } 0005592c: 0000: 000022ea 40420000 t0 write SP_FS_OBJ_START (22eb) SP_FS_OBJ_START: 0x1 00055934: 0000: 000022eb 00000001 t0 write SP_FS_LENGTH_REG (22ef) SP_FS_LENGTH_REG: 1 0005593c: 0000: 000022ef 00000001 t0 write SP_FS_OUTPUT_REG (22f0) SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r0.x | SAMPLEMASK_REGID = r0.x } 00055944: 0000: 000022f0 00000001 t0 write VPC_VARYING_INTERP[0].MODE (2142) VPC_VARYING_INTERP[0].MODE: 0xe000 0005594c: 0000: 00002142 0000e000 t0 write RB_FS_OUTPUT_REG (2100) RB_FS_OUTPUT_REG: { MRT = 1 } 00055954: 0000: 00002100 00000001 t3 opcode: CP_LOAD_STATE4 (30) (35 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 1 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } :2:0000:0000[57309902x_00002004x] (sy)(ss)(rpt1)bary.f (ei)r0.z, (r)4, r0.x :0:0001:0002[00000500x_00000000x] (rpt5)nop :5:0002:0008[a0c01f00x_00000005x] sam (f32)(xyzw)r0.x, r0.z, s#0, t#0 :0:0003:0009[03000000x_00000000x] end :0:0004:0010[00000000x_00000000x] nop :0:0005:0011[00000000x_00000000x] nop :0:0006:0012[00000000x_00000000x] nop :0:0007:0013[00000000x_00000000x] nop Stats: - shaderdb: 14 instr, 10 nops, 4 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 0 half, 1 full, 0 constlen - shaderdb: 11 cat0, 0 cat1, 2 cat2, 0 cat3, 0 cat4, 1 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 1 (ss), 1 (sy) 0005595c: 0000: c0213000 00700000 00000000 00002004 57309902 00000000 00000500 00000005 0005597c: 0020: a0c01f00 00000000 03000000 00000000 00000000 00000000 00000000 00000000 * t0 write RB_FS_OUTPUT (20f9) RB_FS_OUTPUT: { ENABLE_BLEND = 0 | SAMPLE_MASK = 0xffff } 000559e8: 0000: 000020f9 ffff0000 t0 write RB_MRT[0].CONTROL (20a4) RB_MRT[0].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0xf } 000559f0: 0000: 000020a4 0f000000 t0 write RB_MRT[0x1].CONTROL (20a9) RB_MRT[0x1].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0xf } 000559f8: 0000: 000020a9 0f000000 t0 write RB_MRT[0].BLEND_CONTROL (20a8) RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } 00055a00: 0000: 000020a8 00000000 t3 opcode: CP_LOAD_STATE4 (30) (5 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_TEX | NUM_UNIT = 1 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } { XY_MAG = A4XX_TEX_NEAREST | XY_MIN = A4XX_TEX_NEAREST | WRAP_S = A4XX_TEX_CLAMP_TO_EDGE | WRAP_T = A4XX_TEX_CLAMP_TO_EDGE | WRAP_R = A4XX_TEX_CLAMP_TO_EDGE | ANISO = A4XX_TEX_ANISO_1 | LOD_BIAS = 0.000000 | 0x60000 } { COMPARE_FUNC = FUNC_LEQUAL | UNNORM_COORDS | MIPFILTER_LINEAR_FAR | MAX_LOD = 0.000000 | MIN_LOD = 0.000000 | 0x1 } 00055a14: 0000: 00060920 00000067 00055a08: 0000: c0033000 00500000 00000000 00060920 00000067 t0 write GRAS_SC_CONTROL (207b) GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 0 | RASTER_MODE = 0 } 00055a1c: 0000: 0000207b 00000000 t0 write RB_MSAA_CONTROL (20a2) RB_MSAA_CONTROL: { SAMPLES = 0 } 00055a24: 0000: 000020a2 00000000 t0 write RB_RENDER_CONTROL (20a1) RB_RENDER_CONTROL: { 0 } 00055a2c: 0000: 000020a1 00000000 t0 write 0x2382 (2382) 0x2382: 00000000 00055a34: 0000: 00002382 00000000 t0 write RB_DEPTH_CONTROL (2101) RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } 00055a3c: 0000: 00002101 00000000 t0 write GRAS_ALPHA_CONTROL (2073) GRAS_ALPHA_CONTROL: { 0 } 00055a44: 0000: 00002073 00000000 t0 write RB_STENCIL_CONTROL (2106) RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } 00055a4c: 0000: 00002106 00000000 t0 write SP_FS_MRT[0].REG (22f1) SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = RB4_R8G8B8A8_UNORM } 00055a54: 0000: 000022f1 0001a000 t0 write RB_MRT[0].BUF_INFO (20a5) RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB4_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE4_3 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 256 } RB_MRT[0].BASE: 0x166000 RB_MRT[0].CONTROL3: { STRIDE = 0 } 00055a5c: 0000: 000220a5 000400da 00166000 00000000 t3 opcode: CP_LOAD_STATE4 (30) (11 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_TEX | NUM_UNIT = 1 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } { TILED | SWIZ_X = A4XX_TEX_X | SWIZ_Y = A4XX_TEX_Y | SWIZ_Z = A4XX_TEX_Z | SWIZ_W = A4XX_TEX_W | MIPLVLS = 0 | FMT = TFMT4_8_8_8_8_UNORM | TYPE = A4XX_TEX_2D | 0x2 } { HEIGHT = 64 | WIDTH = 64 } { PITCHALIGN = 0 | PITCH = 256 | SWAP = WZYX } { LAYERSZ = 0 | DEPTH = 1 | 0x20000 } { LAYERSZ = 4096 | BASE = 0x4f000 } { 5 = 0 } { 6 = 0 } { 7 = 0 } 00055a78: 0000: 27006883 00200040 00020000 00060000 0004f001 00000000 00000000 00000000 00055a6c: 0000: c0093000 00500000 00000001 27006883 00200040 00020000 00060000 0004f001 * t0 write VPC_VARYING_PS_REPL[0].MODE (214a) VPC_VARYING_PS_REPL[0].MODE: 0x99999999 00055a98: 0000: 0000214a 99999999 t0 write GRAS_SC_SCREEN_SCISSOR_TL (207c) GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } 00055aa0: 0000: 0001207c 00000000 003f003f t0 write GRAS_SC_WINDOW_SCISSOR_BR (209c) GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 00055aac: 0000: 0001209c 003f003f 00000000 t0 write RB_FRAME_BUFFER_DIMENSION (0ce0) RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } 00055ab8: 0000: 00000ce0 00400040 t0 write 0xce1 (0ce1) 0xce1: 00000000 00055ac0: 0000: 00000ce1 00000000 t0 write RB_RENDER_CONTROL2 (20a3) RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 | IJ_PERSP_PIXEL } 00055ac8: 0000: 000020a3 00001000 t0 write RB_MODE_CONTROL (20a0) RB_MODE_CONTROL: { WIDTH = 0 | HEIGHT = 0 | 0xc00000 } 00055ad0: 0000: 000020a0 00c00000 t3 opcode: CP_LOAD_STATE4 (30) (11 dwords) { DST_OFF = 8 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } 00055ae4: 0.000000 0.000000 0.000000 0.000000 64.000000 64.000000 64.000000 64.000000 00055ae4: 0000: 00000000 00000000 00000000 00000000 42800000 42800000 42800000 42800000 00055ad8: 0000: c0093000 00a00008 00000001 00000000 00000000 00000000 00000000 42800000 00055af8: 0020: 42800000 42800000 42800000 t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x80000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 2 } draw[54] register values + 00000004 UNKNOWN_0CC5: 0x4 + 00000000 UNKNOWN_0CC6: 0 + 00400040 RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } + 00000000 0xce1: 00000000 + 00000002 HLSQ_MODE_CONTROL: 0x2 + 00000000 UNKNOWN_0E42: 0 + 00000004 SP_MODE_CONTROL: 0x4 + 00000068 TPL1_TP_MODE_CONTROL: 0x68 + 00188000 GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } + 00000000 UNKNOWN_2001: 0 + 00000001 GRAS_CNTL: { IJ_PERSP } !+ 00000000 GRAS_ALPHA_CONTROL: { 0 } + 00000000 GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } !+ 00000000 GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 0 | RASTER_MODE = 0 } + 00000000 GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } + 003f003f GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } + 003f003f GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } + 00000000 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } !+ 00c00000 RB_MODE_CONTROL: { WIDTH = 0 | HEIGHT = 0 | 0xc00000 } !+ 00000000 RB_RENDER_CONTROL: { 0 } !+ 00000000 RB_MSAA_CONTROL: { SAMPLES = 0 } !+ 00001000 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 | IJ_PERSP_PIXEL } !+ 0f000000 RB_MRT[0].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0xf } !+ 000400da RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB4_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE4_3 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 256 } !+ 00166000 RB_MRT[0].BASE: 0x166000 !+ 00000000 RB_MRT[0].CONTROL3: { STRIDE = 0 } + 00000000 RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } + 0f000000 RB_MRT[0x1].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0xf } + 00000e00 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } !+ ffff0000 RB_FS_OUTPUT: { ENABLE_BLEND = 0 | SAMPLE_MASK = 0xffff } + 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } + 00000001 RB_FS_OUTPUT_REG: { MRT = 1 } + 00000000 RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } + 00000000 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } !+ 42001008 VPC_ATTR: { TOTALATTR = 8 | THRDASSIGN = 1 | ENABLE | 0x40000000 } !+ 00060800 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 8 | NUMNONPOSVSVAR = 6 } !+ 0000e000 VPC_VARYING_INTERP[0].MODE: 0xe000 !+ 99999999 VPC_VARYING_PS_REPL[0].MODE: 0x99999999 + 00000000 UNKNOWN_2152: 0 + 00000000 UNKNOWN_2153: 0 + 00000000 UNKNOWN_2154: 0 + 00000000 UNKNOWN_2155: 0 + 00000000 UNKNOWN_2156: 0 + 0000001d UNKNOWN_21C3: 0x1d + 00000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 } + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + 00000000 PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } + 00000001 UNKNOWN_21E6: 0x1 + 000a0000 VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } + fc030000 VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } + fcfcfcfc VFD_CONTROL_2: 0xfcfcfcfc + fcfcfc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } + 0000fcfc VFD_CONTROL_4: 0xfcfc + 00000000 VFD_INDEX_OFFSET: 0 + 00000000 UNKNOWN_2209: 0 + 00060010 SP_SP_CTRL_REG: { 0x60010 } + 000005c3 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } + 00200c10 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } + 01000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } !+ 0020fc03 SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 2 } !+ 06071e03 SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r1.w | B_COMPMASK = 0x3 } + 00000000 SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00fcfc00 UNKNOWN_22D7: 0xfcfc00 !+ 00000c08 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 12 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } + 00000001 SP_VS_OBJ_START: 0x1 + 00000002 SP_VS_LENGTH_REG: 2 !+ 00700402 SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 0 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE | PIXLODENABLE } !+ 8010003e SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 } !+ 40420000 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 } !+ 00000001 SP_FS_OBJ_START: 0x1 + 00000001 SP_FS_LENGTH_REG: 1 !+ 00000001 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r0.x | SAMPLEMASK_REGID = r0.x } !+ 0001a000 SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = RB4_R8G8B8A8_UNORM } + 00000000 TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } !+ 00000000 0x2382: 00000000 + 00000003 TPL1_TP_FS_TEX_COUNT: 0x3 + 080004f0 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } + fcfc0120 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } + 27f3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } + fcfcfc00 HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } !+ 00fcfcfc HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } + 02010042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } !+ 0141423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 1 } + 00404200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00004200 HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } + 00000007 HLSQ_UPDATE_CONTROL: 0x7 00055b04: 0000: c0023800 00080888 00000001 00000002 t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = CACHE_FLUSH } event CACHE_FLUSH 00055b14: 0000: c0004600 00000006 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00055b1c: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0x8000012 00055b24: 0000: 00000cc6 08000012 00173000: 0000: c0013f00 000555d8 00000155 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 0017300c: 0000: c0014300 00040000 00000000 t3 opcode: (null) (1d) (2 dwords) 00173018: 0000: c0001d00 00000000 ############################################################ vertices: 0 ############################################################ cmdstream: 48 dwords t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 0016b000: 0000: c0002600 00000000 t0 write UCHE_INVALIDATE0 (0e8a) UCHE_INVALIDATE0: 0 UCHE_INVALIDATE1: 0x12 0016b008: 0000: 00010e8a 00000000 00000012 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 0016b014: 0000: c0002600 00000000 t0 write RB_MODE_CONTROL (20a0) RB_MODE_CONTROL: { WIDTH = 64 | HEIGHT = 64 | ENABLE_GMEM } 0016b01c: 0000: 000020a0 00010202 t0 write RB_FRAME_BUFFER_DIMENSION (0ce0) RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } 0016b024: 0000: 00000ce0 00400040 t0 write 0xce1 (0ce1) 0xce1: 00000001 0016b02c: 0000: 00000ce1 00000001 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 0016b034: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0 0016b03c: 0000: 00000cc6 00000000 t3 opcode: (null) (1d) (2 dwords) 0016b044: 0000: c0001d00 00000000 t0 write GRAS_SC_WINDOW_SCISSOR_BR (209c) GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 0016b04c: 0000: 0001209c 003f003f 00000000 t0 write RB_BIN_OFFSET (210d) RB_BIN_OFFSET: { X = 0 | Y = 0 } 0016b058: 0000: 0000210d 00000000 t0 write GRAS_SC_WINDOW_SCISSOR_BR (209c) GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 0016b060: 0000: 0001209c 003f003f 00000000 t0 write UNKNOWN_2157 (2157) UNKNOWN_2157: 0x1 0016b06c: 0000: 00002157 00000001 t3 opcode: (null) (64) (2 dwords) 0016b074: 0000: c0006400 00000001 t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:00054994 ibsize:000000f6 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00054994: 0000: c0002600 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x4 0005499c: 0000: 00000ec3 00000004 t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x68 000549a4: 0000: 00000f03 00000068 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 000549ac: 0000: c0002600 00000000 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } 000549b4: 0000: 000023c0 080004f0 t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = 0x1d } event (null) 000549bc: 0000: c0004600 0000001d t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = FACENESS_FLUSH } event FACENESS_FLUSH 000549c4: 0000: c0004600 0000001c t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 000549cc: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0 000549d4: 0000: 00000cc6 00000000 t0 write UNKNOWN_0E42 (0e42) UNKNOWN_0E42: 0 000549dc: 0000: 00000e42 00000000 t0 write HLSQ_MODE_CONTROL (0e05) HLSQ_MODE_CONTROL: 0x2 000549e4: 0000: 00000e05 00000002 t0 write UNKNOWN_0CC5 (0cc5) UNKNOWN_0CC5: 0x4 000549ec: 0000: 00000cc5 00000004 t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x7 000549f4: 0000: 000023db 00000007 t0 write VFD_CONTROL_2 (2202) VFD_CONTROL_2: 0xfcfcfcfc 000549fc: 0000: 00002202 fcfcfcfc t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } 00054a04: 0000: 00002203 fcfcfc00 t0 write VFD_CONTROL_4 (2204) VFD_CONTROL_4: 0xfcfc 00054a0c: 0000: 00002204 0000fcfc t0 write VFD_INDEX_OFFSET (2208) VFD_INDEX_OFFSET: 0 00054a14: 0000: 00002208 00000000 t0 write UNKNOWN_2209 (2209) UNKNOWN_2209: 0 00054a1c: 0000: 00002209 00000000 t0 write UNKNOWN_2152 (2152) UNKNOWN_2152: 0 UNKNOWN_2153: 0 00054a24: 0000: 00012152 00000000 00000000 t0 write UNKNOWN_2156 (2156) UNKNOWN_2156: 0 00054a30: 0000: 00002156 00000000 t0 write UNKNOWN_2154 (2154) UNKNOWN_2154: 0 00054a38: 0000: 00002154 00000000 t0 write UNKNOWN_2155 (2155) UNKNOWN_2155: 0 00054a40: 0000: 00002155 00000000 t0 write UNKNOWN_21C3 (21c3) UNKNOWN_21C3: 0x1d 00054a48: 0000: 000021c3 0000001d t0 write PC_PRIM_VTX_CNTL2 (21c5) PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 00054a50: 0000: 000021c5 00000012 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 00054a58: 0000: 000021e5 00000000 t0 write GRAS_SU_MODE_CONTROL (2078) GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } 00054a60: 0000: 00002078 00000000 t0 write UNKNOWN_2001 (2001) UNKNOWN_2001: 0 00054a68: 0000: 00002001 00000000 t0 write GRAS_CNTL (2003) GRAS_CNTL: { IJ_PERSP } 00054a70: 0000: 00002003 00000001 t0 write GRAS_CL_CLIP_CNTL (2000) GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } 00054a78: 0000: 00002000 00188000 t0 write TPL1_TP_TEX_COUNT (2381) TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } 00054a80: 0000: 00002381 00000000 t0 write TPL1_TP_FS_TEX_COUNT (23a0) TPL1_TP_FS_TEX_COUNT: 0x3 00054a88: 0000: 000023a0 00000003 t0 write RB_ALPHA_CONTROL (20f8) RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } 00054a90: 0000: 000020f8 00000e00 t0 write RB_RENDER_COMPONENTS (20fb) RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } 00054a98: 0000: 000020fb 0000000f t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 00054aa0: 0000: c0014300 00040000 00000000 t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } 00054aac: 0000: 00002200 000a0000 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } 00054ab4: 0000: 00002201 fc030000 t0 write SP_INSTR_CACHE_CTRL (22c1) SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } 00054abc: 0000: 000022c1 000005c3 t0 write HLSQ_CONTROL_1_REG (23c1) HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } 00054ac4: 0000: 000023c1 fcfc0120 t0 write HLSQ_CONTROL_2_REG (23c2) HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 00054acc: 0000: 000023c2 27f3f3f0 t0 write HLSQ_VS_CONTROL_REG (23c5) HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } 00054ad4: 0000: 000023c5 02010042 t0 write HLSQ_FS_CONTROL_REG (23c6) HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00054adc: 0000: 000023c6 0041423e t0 write HLSQ_HS_CONTROL_REG (23c7) HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00054ae4: 0000: 000023c7 00404200 t0 write HLSQ_DS_CONTROL_REG (23c8) HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00054aec: 0000: 000023c8 00404200 t0 write HLSQ_GS_CONTROL_REG (23c9) HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00054af4: 0000: 000023c9 00404200 t0 write HLSQ_CS_CONTROL_REG (23ca) HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } 00054afc: 0000: 000023ca 00004200 t0 write SP_SP_CTRL_REG (22c0) SP_SP_CTRL_REG: { 0x60010 } 00054b04: 0000: 000022c0 00060010 t0 write UNKNOWN_21E6 (21e6) UNKNOWN_21E6: 0x1 00054b0c: 0000: 000021e6 00000001 t0 write SP_VS_CTRL_REG0 (22c4) SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 00054b14: 0000: 000022c4 00200c10 t0 write SP_VS_CTRL_REG1 (22c5) SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } 00054b1c: 0000: 000022c5 01000042 t0 write VPC_ATTR (2140) VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | 0x40000000 } 00054b24: 0000: 00002140 40001004 t0 write VPC_PACK (2141) VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } 00054b2c: 0000: 00002141 00040400 t0 write PC_PRIM_VTX_CNTL (21c4) PC_PRIM_VTX_CNTL: { VAROUT = 1 } 00054b34: 0000: 000021c4 00000001 t0 write SP_VS_PARAM_REG (22c6) SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } UNKNOWN_22D7: 0xfcfc00 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 00054b3c: 0000: 001922c6 0010fc03 00001e03 00000000 00000000 00000000 00000000 00000000 * 00054b7c: 0040: 00000000 00000000 00fcfc00 00000008 00000000 00000000 00000000 00000000 * t0 write SP_VS_OBJ_OFFSET_REG (22e0) SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 00054ba8: 0000: 000022e0 00000000 t0 write SP_VS_OBJ_START (22e1) SP_VS_OBJ_START: 0x1 00054bb0: 0000: 000022e1 00000001 t0 write SP_VS_LENGTH_REG (22e5) SP_VS_LENGTH_REG: 2 00054bb8: 0000: 000022e5 00000002 t3 opcode: CP_LOAD_STATE4 (30) (67 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } :2:0000:0000[56d81803x_20020003x] (sy)(ss)(nop3) shl.b r0.w, r0.w, 2 :1:0001:0004[20150000x_00000003x] cov.s32s16 hr0.x, r0.w :0:0002:0005[00000200x_00000000x] (rpt2)nop :1:0003:0008[201100f4x_00000000x] mova a0.x, hr0.x :0:0004:0009[00000500x_00000000x] (rpt5)nop :1:0005:0015[20154003x_00000c20x] mov.s32s32 r0.w, c :1:0006:0016[20154004x_00000c21x] mov.s32s32 r1.x, c :1:0007:0017[20154005x_00000c22x] mov.s32s32 r1.y, c :1:0008:0018[20156006x_00000c23x] (ul)mov.s32s32 r1.z, c :0:0009:0019[03000000x_00000000x] end :2:0010:0020[46f00007x_20050000x] shr.b r1.w, r0.x, 5 :2:0011:0021[43980008x_201f0000x] (nop2) and.b r2.x, r0.x, 31 :2:0012:0024[43980807x_201f0007x] (nop3) and.b r1.w, r1.w, 31 :2:0013:0028[46100807x_20100007x] (nop1) mul.u24 r1.w, r1.w, 16 :3:0014:0030[62040007x_00071014x] mad.u24 r1.w, c5.x, r2.x, r1.w :0:0015:0031[00000500x_00000000x] (rpt5)nop :6:0016:0037[c2c60f00x_04800006x] stlw.u32 l[r1.w], r0.w, 4 :0:0017:0038[04800000x_00000000x] chmask :0:0018:0039[05000000x_00000000x] chsh Stats: - shaderdb: 40 instr, 24 nops, 16 non-nops, 5 mov, 1 cov - shaderdb: 0 last-baryf, 0 half, 2 full, 5 constlen - shaderdb: 27 cat0, 6 cat1, 5 cat2, 1 cat3, 0 cat4, 0 cat5, 1 cat6, 0 cat7 - shaderdb: 0 sstall, 1 (ss), 1 (sy) 00054bc0: 0000: c0413000 00a00000 00000000 20020003 56d81803 00000003 20150000 00000000 00054be0: 0020: 00000200 00000000 201100f4 00000000 00000500 00000c20 20154003 00000c21 00054c00: 0040: 20154004 00000c22 20154005 00000c23 20156006 00000000 03000000 20050000 00054c20: 0060: 46f00007 201f0000 43980008 201f0007 43980807 20100007 46100807 00071014 00054c40: 0080: 62040007 00000000 00000500 04800006 c2c60f00 00000000 04800000 00000000 00054c60: 00a0: 05000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 * t0 write GRAS_ALPHA_CONTROL (2073) GRAS_ALPHA_CONTROL: { 0x2 } 00054ccc: 0000: 00002073 00000002 t0 write GRAS_SC_CONTROL (207b) GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = 4 | MSAA_DISABLE | RASTER_MODE = 0 } 00054cd4: 0000: 0000207b 00000a08 t0 write RB_MSAA_CONTROL (20a2) RB_MSAA_CONTROL: { DISABLE | SAMPLES = 4 } 00054cdc: 0000: 000020a2 00009000 t0 write RB_RENDER_CONTROL (20a1) RB_RENDER_CONTROL: { DISABLE_COLOR_PIPE | 0x2 } 00054ce4: 0000: 000020a1 00000022 t0 write RB_CLEAR_COLOR_DW0 (20cc) RB_CLEAR_COLOR_DW0: 0xff000000 RB_CLEAR_COLOR_DW1: 0 RB_CLEAR_COLOR_DW2: 0 RB_CLEAR_COLOR_DW3: 0 00054cec: 0000: 000320cc ff000000 00000000 00000000 00000000 t0 write RB_COPY_CONTROL (20fc) RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_FOUR | MODE = RB_COPY_CLEAR | FASTCLEAR = 0xf | GMEM_BASE = 0 } RB_COPY_DEST_BASE: { BASE = 0x4f000 } RB_COPY_DEST_PITCH: { PITCH = 256 } RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_IF_ALPHA_OFF | COMPONENT_ENABLE = 0 | ENDIAN = ENDIAN_NONE | TILE = TILE4_3 } 00054d00: 0000: 000320fc 00000f22 0004f000 00000008 03000868 t0 write GRAS_SC_SCREEN_SCISSOR_TL (207c) GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } 00054d14: 0000: 0001207c 00000000 003f003f t0 write RB_FRAME_BUFFER_DIMENSION (0ce0) RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } 00054d20: 0000: 00000ce0 00400040 t0 write 0xce1 (0ce1) 0xce1: 00000000 00054d28: 0000: 00000ce1 00000000 t3 opcode: CP_LOAD_STATE4 (30) (11 dwords) { DST_OFF = 8 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } 00054d3c: 0.000000 0.000000 1.000000 1.000000 64.000000 64.000000 1.000000 1.000000 00054d3c: 0000: 00000000 00000000 3f800000 3f800000 42800000 42800000 3f800000 3f800000 00054d30: 0000: c0093000 00a00008 00000001 00000000 00000000 3f800000 3f800000 42800000 00054d50: 0020: 42800000 3f800000 3f800000 t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x80000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 2 } draw[55] register values + 00000004 UNKNOWN_0CC5: 0x4 + 00000000 UNKNOWN_0CC6: 0 + 00400040 RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } + 00000000 0xce1: 00000000 + 00000002 HLSQ_MODE_CONTROL: 0x2 + 00000000 UNKNOWN_0E42: 0 + 00000000 UCHE_INVALIDATE0: 0 + 00000012 UCHE_INVALIDATE1: 0x12 + 00000004 SP_MODE_CONTROL: 0x4 + 00000068 TPL1_TP_MODE_CONTROL: 0x68 + 00188000 GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } + 00000000 UNKNOWN_2001: 0 + 00000001 GRAS_CNTL: { IJ_PERSP } !+ 00000002 GRAS_ALPHA_CONTROL: { 0x2 } + 00000000 GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } !+ 00000a08 GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = 4 | MSAA_DISABLE | RASTER_MODE = 0 } + 00000000 GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } + 003f003f GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } + 003f003f GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } + 00000000 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } !+ 00010202 RB_MODE_CONTROL: { WIDTH = 64 | HEIGHT = 64 | ENABLE_GMEM } !+ 00000022 RB_RENDER_CONTROL: { DISABLE_COLOR_PIPE | 0x2 } !+ 00009000 RB_MSAA_CONTROL: { DISABLE | SAMPLES = 4 } + ff000000 RB_CLEAR_COLOR_DW0: 0xff000000 + 00000000 RB_CLEAR_COLOR_DW1: 0 + 00000000 RB_CLEAR_COLOR_DW2: 0 + 00000000 RB_CLEAR_COLOR_DW3: 0 + 00000e00 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } + 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } !+ 00000f22 RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_FOUR | MODE = RB_COPY_CLEAR | FASTCLEAR = 0xf | GMEM_BASE = 0 } + 0004f000 RB_COPY_DEST_BASE: { BASE = 0x4f000 } + 00000008 RB_COPY_DEST_PITCH: { PITCH = 256 } !+ 03000868 RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_IF_ALPHA_OFF | COMPONENT_ENABLE = 0 | ENDIAN = ENDIAN_NONE | TILE = TILE4_3 } + 00000000 RB_BIN_OFFSET: { X = 0 | Y = 0 } !+ 40001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | 0x40000000 } !+ 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } + 00000000 UNKNOWN_2152: 0 + 00000000 UNKNOWN_2153: 0 + 00000000 UNKNOWN_2154: 0 + 00000000 UNKNOWN_2155: 0 + 00000000 UNKNOWN_2156: 0 + 00000001 UNKNOWN_2157: 0x1 + 0000001d UNKNOWN_21C3: 0x1d + 00000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 } + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + 00000000 PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } + 00000001 UNKNOWN_21E6: 0x1 + 000a0000 VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } + fc030000 VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } + fcfcfcfc VFD_CONTROL_2: 0xfcfcfcfc + fcfcfc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } + 0000fcfc VFD_CONTROL_4: 0xfcfc + 00000000 VFD_INDEX_OFFSET: 0 + 00000000 UNKNOWN_2209: 0 + 00060010 SP_SP_CTRL_REG: { 0x60010 } + 000005c3 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } + 00200c10 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } + 01000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } !+ 0010fc03 SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } !+ 00001e03 SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00fcfc00 UNKNOWN_22D7: 0xfcfc00 !+ 00000008 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } + 00000001 SP_VS_OBJ_START: 0x1 + 00000002 SP_VS_LENGTH_REG: 2 + 00000000 TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } + 00000003 TPL1_TP_FS_TEX_COUNT: 0x3 + 080004f0 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } + fcfc0120 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } + 27f3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } + 02010042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } !+ 0041423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00004200 HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } + 00000007 HLSQ_UPDATE_CONTROL: 0x7 00054d5c: 0000: c0023800 00080888 00000001 00000002 0016b07c: 0000: c0013f00 00054994 000000f6 t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:00054d6c ibsize:00000037 t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } 00054d6c: 0000: 00002200 082a0008 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00054d74: 0000: c0002600 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x1e 00054d7c: 0000: 00000ec3 0000001e t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x28 00054d84: 0000: 00000f03 00000028 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00054d8c: 0000: c0002600 00000000 t0 write HLSQ_MODE_CONTROL (0e05) HLSQ_MODE_CONTROL: 0x1 00054d94: 0000: 00000e05 00000001 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0x600a0 } 00054d9c: 0000: 000023c0 080604f0 t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x7 00054da4: 0000: 000023db 00000007 t0 write PC_RESTART_INDEX (21c6) PC_RESTART_INDEX: 0xffffffff 00054dac: 0000: 000021c6 ffffffff t0 write UNKNOWN_21E6 (21e6) UNKNOWN_21E6: 0x1 00054db4: 0000: 000021e6 00000001 t0 write UNKNOWN_21C3 (21c3) UNKNOWN_21C3: 0x1f 00054dbc: 0000: 000021c3 0000001f t0 write TPL1_TP_TEX_OFFSET (2380) TPL1_TP_TEX_OFFSET: 0x808 00054dc4: 0000: 00002380 00000808 t0 write GRAS_SU_POINT_MINMAX (2070) GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 4092.000000 } GRAS_SU_POINT_SIZE: 0.500000 00054dcc: 0000: 00012070 ffc00010 00000008 t0 write UNKNOWN_2152 (2152) UNKNOWN_2152: 0 UNKNOWN_2153: 0 00054dd8: 0000: 00012152 00000000 00000000 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00054de4: 0000: c0002600 00000000 t0 write UNKNOWN_0CC5 (0cc5) UNKNOWN_0CC5: 0x4 00054dec: 0000: 00000cc5 00000004 t0 write 0xcc4 (0cc4) 0xcc4: 00000000 00054df4: 0000: 00000cc4 00000000 t0 write 0xd03 (0d03) 0xd03: 80200000 00054dfc: 0000: 00000d03 80200000 t0 write UNKNOWN_0EC2 (0ec2) UNKNOWN_0EC2: 0x40000 00054e04: 0000: 00000ec2 00040000 t0 write VPC_DEBUG_ECO_CONTROL (0e64) VPC_DEBUG_ECO_CONTROL: 0x100 00054e0c: 0000: 00000e64 00000100 t0 write UNKNOWN_0E42 (0e42) UNKNOWN_0E42: 0 00054e14: 0000: 00000e42 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x1e 00054e1c: 0000: 00000ec3 0000001e t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x28 00054e24: 0000: 00000f03 00000028 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 00054e2c: 0000: c0014300 00040000 00000000 t0 write VFD_INDEX_OFFSET (2208) VFD_INDEX_OFFSET: 0 00054e38: 0000: 00002208 00000000 t0 write UNKNOWN_2209 (2209) UNKNOWN_2209: 0 00054e40: 0000: 00002209 00000000 0016b088: 0000: c0013f00 00054d6c 00000037 t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:00055328 ibsize:000000ac t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x3 00055328: 0000: 000023db 00000003 t0 write SP_INSTR_CACHE_CTRL (22c1) SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } 00055330: 0000: 000022c1 000005c3 t0 write HLSQ_CONTROL_1_REG (23c1) HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x1008 } 00055338: 0000: 000023c1 fcfc1108 t0 write HLSQ_CONTROL_2_REG (23c2) HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 00055340: 0000: 000023c2 fff3f3f0 t0 write HLSQ_VS_CONTROL_REG (23c5) HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 2 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 1 } 00055348: 0000: 000023c5 01010002 t0 write HLSQ_HS_CONTROL_REG (23c7) HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 00055350: 0000: 000023c7 007e0200 t0 write HLSQ_DS_CONTROL_REG (23c8) HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 00055358: 0000: 000023c8 007e0200 t0 write HLSQ_GS_CONTROL_REG (23c9) HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 00055360: 0000: 000023c9 007e0200 t0 write HLSQ_FS_CONTROL_REG (23c6) HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 2 | CONSTOBJECTOFFSET = 2 | ENABLED | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 } 00055368: 0000: 000023c6 017f0202 t0 write SP_VS_OBJ_OFFSET_REG (22e0) SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 00055370: 0000: 000022e0 00000000 t0 write SP_HS_OBJ_OFFSET_REG (230d) SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } 00055378: 0000: 0000230d 7e020000 t0 write SP_DS_OBJ_OFFSET_REG (2334) SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } 00055380: 0000: 00002334 7e020000 t0 write SP_GS_OBJ_OFFSET_REG (235b) SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } 00055388: 0000: 0000235b 7e020000 t0 write SP_FS_OBJ_OFFSET_REG (22ea) SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } 00055390: 0000: 000022ea 7e020000 t0 write SP_VS_OBJ_START (22e1) SP_VS_OBJ_START: 0x49000 00049000: 0000: 00000000 13000000 00000000 00000000 00000000 00000000 00000000 00000000 * :0:0000:0000[13000000x_00000000x] (sy)end :0:0001:0001[00000000x_00000000x] nop :0:0002:0002[00000000x_00000000x] nop :0:0003:0003[00000000x_00000000x] nop :0:0004:0004[00000000x_00000000x] nop Stats: - shaderdb: 5 instr, 4 nops, 1 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 0 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 0 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) 00055398: 0000: 000022e1 00049000 t0 write SP_HS_OBJ_START (230e) SP_HS_OBJ_START: 0 000553a0: 0000: 0000230e 00000000 t0 write SP_DS_OBJ_START (2335) SP_DS_OBJ_START: 0 000553a8: 0000: 00002335 00000000 t0 write SP_GS_OBJ_START (235c) SP_GS_OBJ_START: 0 000553b0: 0000: 0000235c 00000000 t0 write SP_VS_LENGTH_REG (22e5) SP_VS_LENGTH_REG: 1 000553b8: 0000: 000022e5 00000001 t3 opcode: CP_LOAD_STATE4 (30) (3 dwords) { DST_OFF = 0 | STATE_SRC = SS4_INDIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 1 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0x49000 } :0:0000:0000[13000000x_00000000x] (sy)end :0:0001:0001[00000000x_00000000x] nop :0:0002:0002[00000000x_00000000x] nop :0:0003:0003[00000000x_00000000x] nop :0:0004:0004[00000000x_00000000x] nop Stats: - shaderdb: 5 instr, 4 nops, 1 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 0 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 0 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) 000553c0: 0000: c0013000 00620000 00049000 t0 write 0x2072 (2072) 0x2072: 00000000 000553cc: 0000: 00002072 00000000 t0 write UNKNOWN_2155 (2155) UNKNOWN_2155: 0 000553d4: 0000: 00002155 00000000 t0 write GRAS_CNTL (2003) GRAS_CNTL: { IJ_PERSP } 000553dc: 0000: 00002003 00000001 t0 write VPC_VARYING_INTERP[0].MODE (2142) VPC_VARYING_INTERP[0].MODE: 0 000553e4: 0000: 00002142 00000000 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0x600a0 } 000553ec: 0000: 000023c0 080604f0 t0 write HLSQ_CONTROL_3_REG (23c3) HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } 000553f4: 0000: 000023c3 fcfcfc00 t0 write HLSQ_CONTROL_4_REG (23c4) HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r0.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } 000553fc: 0000: 000023c4 00fcfc00 t0 write SP_FS_CTRL_REG0 (22e8) SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE } SP_FS_CTRL_REG1: { CONSTLENGTH = 2 | VARYING | 0x80000000 } 00055404: 0000: 000122e8 00340412 80100002 t0 write SP_FS_OBJ_START (22eb) SP_FS_OBJ_START: 0x46000 00046000: 0000: 00002000 5730cb00 00000000 03000000 00000000 00000000 00000000 00000000 * :2:0000:0000[5730cb00x_00002000x] (sy)(rpt3)bary.f (ei)hr0.x, (r)0, r0.x :0:0001:0004[03000000x_00000000x] end :0:0002:0005[00000000x_00000000x] nop :0:0003:0006[00000000x_00000000x] nop :0:0004:0007[00000000x_00000000x] nop :0:0005:0008[00000000x_00000000x] nop Stats: - shaderdb: 9 instr, 4 nops, 5 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 1 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 4 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) 00055410: 0000: 000022eb 00046000 t0 write SP_FS_LENGTH_REG (22ef) SP_FS_LENGTH_REG: 1 00055418: 0000: 000022ef 00000001 t0 write RB_RENDER_COMPONENTS (20fb) RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } 00055420: 0000: 000020fb 0000000f t3 opcode: CP_LOAD_STATE4 (30) (3 dwords) { DST_OFF = 0 | STATE_SRC = SS4_INDIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 1 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0x46000 } :2:0000:0000[5730cb00x_00002000x] (sy)(rpt3)bary.f (ei)hr0.x, (r)0, r0.x :0:0001:0004[03000000x_00000000x] end :0:0002:0005[00000000x_00000000x] nop :0:0003:0006[00000000x_00000000x] nop :0:0004:0007[00000000x_00000000x] nop :0:0005:0008[00000000x_00000000x] nop Stats: - shaderdb: 9 instr, 4 nops, 5 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 1 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 4 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) 00055428: 0000: c0013000 00720000 00046000 t0 write SP_SP_CTRL_REG (22c0) SP_SP_CTRL_REG: { 0x60010 } 00055434: 0000: 000022c0 00060010 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 28 | GROUP_ID = 3 } { ADDR_LO = 0x9b790 } 0005543c: 0000: c0014300 0300001c 0009b790 t0 write RB_DEPTH_INFO (2103) RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTH4_NONE | DEPTH_BASE = 0 } RB_DEPTH_PITCH: 0 RB_DEPTH_PITCH2: 0 00055448: 0000: 00022103 00000000 00000000 00000000 t0 write GRAS_DEPTH_CONTROL (2077) GRAS_DEPTH_CONTROL: { FORMAT = DEPTH4_NONE } 00055458: 0000: 00002077 00000000 t0 write RB_STENCIL_INFO (2108) RB_STENCIL_INFO: { STENCIL_BASE = 0 } RB_STENCIL_PITCH: 0 0x210a: 00000000 00055460: 0000: 00022108 00000000 00000000 00000000 t0 write 0x2002 (2002) 0x2002: 00000000 00055470: 0000: 00002002 00000000 t0 write RB_ALPHA_CONTROL (20f8) RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } 00055478: 0000: 000020f8 00000e00 t0 write RB_MRT[0].CONTROL (20a4) RB_MRT[0].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0x7 } 00055480: 0000: 000020a4 07000c00 t0 write RB_MRT[0].BLEND_CONTROL (20a8) RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } 00055488: 0000: 000020a8 00000000 t0 write GRAS_CL_CLIP_CNTL (2000) GRAS_CL_CLIP_CNTL: { 0x80000 } 00055490: 0000: 00002000 00080000 t0 write GRAS_SU_POLY_OFFSET_SCALE (2074) GRAS_SU_POLY_OFFSET_SCALE: 0.000000 GRAS_SU_POLY_OFFSET_OFFSET: 0.000000 GRAS_SU_POLY_OFFSET_CLAMP: 0.000000 00055498: 0000: 00022074 00000000 00000000 00000000 t0 write GRAS_SU_MODE_CONTROL (2078) GRAS_SU_MODE_CONTROL: { FRONT_CW | LINEHALFWIDTH = 0.500000 | MSAA_ENABLE | RENDERING_PASS } 000554a8: 0000: 00002078 00102014 t0 write GRAS_SC_SCREEN_SCISSOR_TL (207c) GRAS_SC_SCREEN_SCISSOR_TL: { X = 2 | Y = 13 } GRAS_SC_SCREEN_SCISSOR_BR: { X = 33 | Y = 44 } 000554b0: 0000: 0001207c 000d0002 002c0021 t0 write GRAS_CL_VPORT_XOFFSET_0 (2008) GRAS_CL_VPORT_XOFFSET_0: 18.000000 GRAS_CL_VPORT_XSCALE_0: 16.000000 GRAS_CL_VPORT_YOFFSET_0: 29.000000 GRAS_CL_VPORT_YSCALE_0: 16.000000 GRAS_CL_VPORT_ZOFFSET_0: 0.500000 GRAS_CL_VPORT_ZSCALE_0: 0.500000 000554bc: 0000: 00052008 41900000 41800000 41e80000 41800000 3f000000 3f000000 t0 write GRAS_CL_GB_CLIP_ADJ (2004) GRAS_CL_GB_CLIP_ADJ: { HORZ = 511 | VERT = 511 } 000554d8: 0000: 00002004 0007fdff t0 write GRAS_SC_CONTROL (207b) GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 4 | RASTER_MODE = 0 } 000554e0: 0000: 0000207b 00000200 t0 write 0x2382 (2382) 0x2382: 00000002 000554e8: 0000: 00002382 00000002 t0 write RB_MSAA_CONTROL (20a2) RB_MSAA_CONTROL: { SAMPLES = 4 } 000554f0: 0000: 000020a2 00008000 t0 write RB_RENDER_CONTROL2 (20a3) RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 4 | IJ_PERSP_PIXEL } 000554f8: 0000: 000020a3 00001200 t0 write RB_MRT[0].BUF_INFO (20a5) RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB4_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_ALWAYS | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 1024 } RB_MRT[0].BASE: 0 RB_MRT[0].CONTROL3: { STRIDE = 64 } 00055500: 0000: 000220a5 0010029a 00000000 00000200 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 43 | GROUP_ID = 2 } { ADDR_LO = 0x9b800 } 00055510: 0000: c0014300 0200002b 0009b800 t0 write 0x215c (215c) 0x215c: 00000000 0x215d: 00000000 0005551c: 0000: 0001215c 00000000 00000000 t0 write 0x215f (215f) 0x215f: 00000000 00055528: 0000: 0000215f 00000000 t0 write 0x215e (215e) 0x215e: 00000000 00055530: 0000: 0000215e 00000000 t0 write 0x2161 (2161) 0x2161: 00000000 0x2162: 00000000 00055538: 0000: 00012161 00000000 00000000 t0 write 0x2164 (2164) 0x2164: 00000000 00055544: 0000: 00002164 00000000 t0 write 0x2163 (2163) 0x2163: 00000000 0005554c: 0000: 00002163 00000000 t0 write 0x2166 (2166) 0x2166: 00000000 0x2167: 00000000 00055554: 0000: 00012166 00000000 00000000 t0 write 0x2169 (2169) 0x2169: 00000000 00055560: 0000: 00002169 00000000 t0 write 0x2168 (2168) 0x2168: 00000000 00055568: 0000: 00002168 00000000 t0 write 0x216b (216b) 0x216b: 00000000 0x216c: 00000000 00055570: 0000: 0001216b 00000000 00000000 t0 write VPC_SO_FLUSH_WADDR_3 (216e) VPC_SO_FLUSH_WADDR_3: 0 0005557c: 0000: 0000216e 00000000 t0 write 0x216d (216d) 0x216d: 00000000 00055584: 0000: 0000216d 00000000 t0 write UNKNOWN_2156 (2156) UNKNOWN_2156: 0 0005558c: 0000: 00002156 00000000 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 18 | GROUP_ID = 1 } { ADDR_LO = 0x9b8b0 } 00055594: 0000: c0014300 01000012 0009b8b0 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 15 | GROUP_ID = 0 } { ADDR_LO = 0x9b900 } 000555a0: 0000: c0014300 0000000f 0009b900 group_id: 0 count: 15 addr: 000000000009b900 flags: 0 0009b900: 0000: 00002073 00000000 00002101 00000000 00002106 00000000 000021e5 00000000 0009b920: 0020: 0001210b 00000000 00000000 00002381 00000000 000023a0 00000000 t0 write GRAS_ALPHA_CONTROL (2073) GRAS_ALPHA_CONTROL: { 0 } 0009b900: 0000: 00002073 00000000 t0 write RB_DEPTH_CONTROL (2101) RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } 0009b908: 0000: 00002101 00000000 t0 write RB_STENCIL_CONTROL (2106) RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } 0009b910: 0000: 00002106 00000000 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 0009b918: 0000: 000021e5 00000000 t0 write RB_STENCILREFMASK (210b) RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 0009b920: 0000: 0001210b 00000000 00000000 t0 write TPL1_TP_TEX_COUNT (2381) TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } 0009b92c: 0000: 00002381 00000000 t0 write TPL1_TP_FS_TEX_COUNT (23a0) TPL1_TP_FS_TEX_COUNT: 0 0009b934: 0000: 000023a0 00000000 group_id: 1 count: 18 addr: 000000000009b8b0 flags: 0 0009b8b0: 0000: 00002200 082a0008 00002201 fcfc0081 00002203 0000fc00 0007220a 0008080f 0009b8d0: 0020: 0009b730 00000060 00000001 0000080f 0009b760 00000030 00000001 0001228a 0009b8f0: 0040: 7000411f 3000011f t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } 0009b8b0: 0000: 00002200 082a0008 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } 0009b8b8: 0000: 00002201 fcfc0081 t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } 0009b8c0: 0000: 00002203 0000fc00 t0 write VFD_FETCH[0].INSTR_0 (220a) VFD_FETCH[0].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 | SWITCHNEXT } VFD_FETCH[0].INSTR_1: 0x9b730 VFD_FETCH[0].INSTR_2: { SIZE = 0x60 } VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 } VFD_FETCH[0x1].INSTR_1: 0x9b760 VFD_FETCH[0x1].INSTR_2: { SIZE = 0x30 } VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } 0009b8c8: 0000: 0007220a 0008080f 0009b730 00000060 00000001 0000080f 0009b760 00000030 0009b8e8: 0020: 00000001 t0 write VFD_DECODE[0].INSTR (228a) VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID | SWITCHNEXT } VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID } 0009b8ec: 0000: 0001228a 7000411f 3000011f group_id: 2 count: 43 addr: 000000000009b800 flags: 0 0009b800: 0000: 000020a1 00000000 000022f1 0001a100 000022f0 fc00fc01 00002100 00000001 0009b820: 0020: 000021e5 00000000 000020f9 ffff0501 0000214a 00000000 00002140 42001004 0009b840: 0040: 001922c6 0010fc04 00001e00 00000000 00000000 00000000 00000000 00000000 * 0009b880: 0080: 00000000 00000000 00fcfc00 00000008 00000000 00000000 00000000 00000000 * t0 write RB_RENDER_CONTROL (20a1) RB_RENDER_CONTROL: { 0 } 0009b800: 0000: 000020a1 00000000 t0 write SP_FS_MRT[0].REG (22f1) SP_FS_MRT[0].REG: { REGID = r0.x | HALF_PRECISION | MRTFORMAT = RB4_R8G8B8A8_UNORM } 0009b808: 0000: 000022f1 0001a100 t0 write SP_FS_OUTPUT_REG (22f0) SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 0009b810: 0000: 000022f0 fc00fc01 t0 write RB_FS_OUTPUT_REG (2100) RB_FS_OUTPUT_REG: { MRT = 1 } 0009b818: 0000: 00002100 00000001 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 0009b820: 0000: 000021e5 00000000 t0 write RB_FS_OUTPUT (20f9) RB_FS_OUTPUT: { ENABLE_BLEND = 0x1 | INDEPENDENT_BLEND | SAMPLE_MASK = 0xffff | 0x400 } 0009b828: 0000: 000020f9 ffff0501 t0 write VPC_VARYING_PS_REPL[0].MODE (214a) VPC_VARYING_PS_REPL[0].MODE: 0 0009b830: 0000: 0000214a 00000000 t0 write VPC_ATTR (2140) VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 } 0009b838: 0000: 00002140 42001004 t0 write SP_VS_PARAM_REG (22c6) SP_VS_PARAM_REG: { POSREGID = r1.x | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } SP_VS_OUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } UNKNOWN_22D7: 0xfcfc00 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 0009b840: 0000: 001922c6 0010fc04 00001e00 00000000 00000000 00000000 00000000 00000000 * 0009b880: 0040: 00000000 00000000 00fcfc00 00000008 00000000 00000000 00000000 00000000 * group_id: 3 count: 28 addr: 000000000009b790 flags: 0 0009b790: 0000: 000021c4 02000001 00002141 00040400 00002001 00000000 000022c4 00200800 0009b7b0: 0020: 000022c5 08000002 0000230c 00000000 00002318 00000000 00002319 00000000 0009b7d0: 0040: 00002340 00000000 00002202 fcfcfcfc 00002204 0000fcfc 00002154 00000000 0009b7f0: 0060: 000021e7 00000000 000021c5 00000012 t0 write PC_PRIM_VTX_CNTL (21c4) PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } 0009b790: 0000: 000021c4 02000001 t0 write VPC_PACK (2141) VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } 0009b798: 0000: 00002141 00040400 t0 write UNKNOWN_2001 (2001) UNKNOWN_2001: 0 0009b7a0: 0000: 00002001 00000000 t0 write SP_VS_CTRL_REG0 (22c4) SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 2 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 0009b7a8: 0000: 000022c4 00200800 t0 write SP_VS_CTRL_REG1 (22c5) SP_VS_CTRL_REG1: { CONSTLENGTH = 2 | INITIALOUTSTANDING = 8 } 0009b7b0: 0000: 000022c5 08000002 t0 write 0x230c (230c) 0x230c: 00000000 0009b7b8: 0000: 0000230c 00000000 t0 write 0x2318 (2318) 0x2318: 00000000 0009b7c0: 0000: 00002318 00000000 t0 write 0x2319 (2319) 0x2319: 00000000 0009b7c8: 0000: 00002319 00000000 t0 write 0x2340 (2340) 0x2340: 00000000 0009b7d0: 0000: 00002340 00000000 t0 write VFD_CONTROL_2 (2202) VFD_CONTROL_2: 0xfcfcfcfc 0009b7d8: 0000: 00002202 fcfcfcfc t0 write VFD_CONTROL_4 (2204) VFD_CONTROL_4: 0xfcfc 0009b7e0: 0000: 00002204 0000fcfc t0 write UNKNOWN_2154 (2154) UNKNOWN_2154: 0 0009b7e8: 0000: 00002154 00000000 t0 write PC_HS_PARAM (21e7) PC_HS_PARAM: { VERTICES_OUT = 0 | SPACING = EQUAL_SPACING } 0009b7f0: 0000: 000021e7 00000000 t0 write PC_PRIM_VTX_CNTL2 (21c5) PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 0009b7f8: 0000: 000021c5 00000012 t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = USE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x200000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 3 } draw[56] register values + 00000000 0xcc4: 00000000 + 00000004 UNKNOWN_0CC5: 0x4 + 80200000 0xd03: 80200000 !+ 00000001 HLSQ_MODE_CONTROL: 0x1 + 00000000 UNKNOWN_0E42: 0 + 00000100 VPC_DEBUG_ECO_CONTROL: 0x100 + 00040000 UNKNOWN_0EC2: 0x40000 !+ 0000001e SP_MODE_CONTROL: 0x1e !+ 00000028 TPL1_TP_MODE_CONTROL: 0x28 !+ 00080000 GRAS_CL_CLIP_CNTL: { 0x80000 } + 00000000 UNKNOWN_2001: 0 + 00000000 0x2002: 00000000 + 00000001 GRAS_CNTL: { IJ_PERSP } + 0007fdff GRAS_CL_GB_CLIP_ADJ: { HORZ = 511 | VERT = 511 } + 41900000 GRAS_CL_VPORT_XOFFSET_0: 18.000000 + 41800000 GRAS_CL_VPORT_XSCALE_0: 16.000000 + 41e80000 GRAS_CL_VPORT_YOFFSET_0: 29.000000 + 41800000 GRAS_CL_VPORT_YSCALE_0: 16.000000 + 3f000000 GRAS_CL_VPORT_ZOFFSET_0: 0.500000 + 3f000000 GRAS_CL_VPORT_ZSCALE_0: 0.500000 + ffc00010 GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 4092.000000 } + 00000008 GRAS_SU_POINT_SIZE: 0.500000 + 00000000 0x2072: 00000000 !+ 00000000 GRAS_ALPHA_CONTROL: { 0 } + 00000000 GRAS_SU_POLY_OFFSET_SCALE: 0.000000 + 00000000 GRAS_SU_POLY_OFFSET_OFFSET: 0.000000 + 00000000 GRAS_SU_POLY_OFFSET_CLAMP: 0.000000 + 00000000 GRAS_DEPTH_CONTROL: { FORMAT = DEPTH4_NONE } !+ 00102014 GRAS_SU_MODE_CONTROL: { FRONT_CW | LINEHALFWIDTH = 0.500000 | MSAA_ENABLE | RENDERING_PASS } !+ 00000200 GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 4 | RASTER_MODE = 0 } !+ 000d0002 GRAS_SC_SCREEN_SCISSOR_TL: { X = 2 | Y = 13 } !+ 002c0021 GRAS_SC_SCREEN_SCISSOR_BR: { X = 33 | Y = 44 } !+ 00000000 RB_RENDER_CONTROL: { 0 } !+ 00008000 RB_MSAA_CONTROL: { SAMPLES = 4 } !+ 00001200 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 4 | IJ_PERSP_PIXEL } !+ 07000c00 RB_MRT[0].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0x7 } !+ 0010029a RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB4_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_ALWAYS | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 1024 } !+ 00000000 RB_MRT[0].BASE: 0 !+ 00000200 RB_MRT[0].CONTROL3: { STRIDE = 64 } + 00000000 RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } + 00000e00 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } !+ ffff0501 RB_FS_OUTPUT: { ENABLE_BLEND = 0x1 | INDEPENDENT_BLEND | SAMPLE_MASK = 0xffff | 0x400 } + 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } + 00000001 RB_FS_OUTPUT_REG: { MRT = 1 } + 00000000 RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } + 00000000 RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTH4_NONE | DEPTH_BASE = 0 } + 00000000 RB_DEPTH_PITCH: 0 + 00000000 RB_DEPTH_PITCH2: 0 + 00000000 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } + 00000000 RB_STENCIL_INFO: { STENCIL_BASE = 0 } + 00000000 RB_STENCIL_PITCH: 0 + 00000000 0x210a: 00000000 + 00000000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } + 00000000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } !+ 42001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 } + 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } !+ 00000000 VPC_VARYING_INTERP[0].MODE: 0 !+ 00000000 VPC_VARYING_PS_REPL[0].MODE: 0 + 00000000 UNKNOWN_2152: 0 + 00000000 UNKNOWN_2153: 0 + 00000000 UNKNOWN_2154: 0 + 00000000 UNKNOWN_2155: 0 + 00000000 UNKNOWN_2156: 0 + 00000000 0x215c: 00000000 + 00000000 0x215d: 00000000 + 00000000 0x215e: 00000000 + 00000000 0x215f: 00000000 + 00000000 0x2161: 00000000 + 00000000 0x2162: 00000000 + 00000000 0x2163: 00000000 + 00000000 0x2164: 00000000 + 00000000 0x2166: 00000000 + 00000000 0x2167: 00000000 + 00000000 0x2168: 00000000 + 00000000 0x2169: 00000000 + 00000000 0x216b: 00000000 + 00000000 0x216c: 00000000 + 00000000 0x216d: 00000000 + 00000000 VPC_SO_FLUSH_WADDR_3: 0 !+ 0000001f UNKNOWN_21C3: 0x1f !+ 02000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + ffffffff PC_RESTART_INDEX: 0xffffffff + 00000000 PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } + 00000001 UNKNOWN_21E6: 0x1 + 00000000 PC_HS_PARAM: { VERTICES_OUT = 0 | SPACING = EQUAL_SPACING } !+ 082a0008 VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } !+ fcfc0081 VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } + fcfcfcfc VFD_CONTROL_2: 0xfcfcfcfc !+ 0000fc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } + 0000fcfc VFD_CONTROL_4: 0xfcfc + 00000000 VFD_INDEX_OFFSET: 0 + 00000000 UNKNOWN_2209: 0 + 0008080f VFD_FETCH[0].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 | SWITCHNEXT } !+ 0009b730 VFD_FETCH[0].INSTR_1: 0x9b730 + 00000060 VFD_FETCH[0].INSTR_2: { SIZE = 0x60 } + 00000001 VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } + 0000080f VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 } !+ 0009b760 VFD_FETCH[0x1].INSTR_1: 0x9b760 + 00000030 VFD_FETCH[0x1].INSTR_2: { SIZE = 0x30 } + 00000001 VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } + 7000411f VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID | SWITCHNEXT } + 3000011f VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID } + 00060010 SP_SP_CTRL_REG: { 0x60010 } + 000005c3 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } !+ 00200800 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 2 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } !+ 08000002 SP_VS_CTRL_REG1: { CONSTLENGTH = 2 | INITIALOUTSTANDING = 8 } !+ 0010fc04 SP_VS_PARAM_REG: { POSREGID = r1.x | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } !+ 00001e00 SP_VS_OUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00fcfc00 UNKNOWN_22D7: 0xfcfc00 + 00000008 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } !+ 00049000 SP_VS_OBJ_START: 0x49000 00049000: 0000: 00000000 13000000 00000000 00000000 00000000 00000000 00000000 00000000 * :0:0000:0000[13000000x_00000000x] (sy)end :0:0001:0001[00000000x_00000000x] nop :0:0002:0002[00000000x_00000000x] nop :0:0003:0003[00000000x_00000000x] nop :0:0004:0004[00000000x_00000000x] nop Stats: - shaderdb: 5 instr, 4 nops, 1 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 0 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 0 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) !+ 00000001 SP_VS_LENGTH_REG: 1 !+ 00340412 SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE } !+ 80100002 SP_FS_CTRL_REG1: { CONSTLENGTH = 2 | VARYING | 0x80000000 } !+ 7e020000 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } !+ 00046000 SP_FS_OBJ_START: 0x46000 00046000: 0000: 00002000 5730cb00 00000000 03000000 00000000 00000000 00000000 00000000 * :2:0000:0000[5730cb00x_00002000x] (sy)(rpt3)bary.f (ei)hr0.x, (r)0, r0.x :0:0001:0004[03000000x_00000000x] end :0:0002:0005[00000000x_00000000x] nop :0:0003:0006[00000000x_00000000x] nop :0:0004:0007[00000000x_00000000x] nop :0:0005:0008[00000000x_00000000x] nop Stats: - shaderdb: 9 instr, 4 nops, 5 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 1 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 4 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) + 00000001 SP_FS_LENGTH_REG: 1 !+ fc00fc01 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r63.x } !+ 0001a100 SP_FS_MRT[0].REG: { REGID = r0.x | HALF_PRECISION | MRTFORMAT = RB4_R8G8B8A8_UNORM } + 00000000 0x230c: 00000000 + 7e020000 SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } + 00000000 SP_HS_OBJ_START: 0 + 00000000 0x2318: 00000000 + 00000000 0x2319: 00000000 + 7e020000 SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } + 00000000 SP_DS_OBJ_START: 0 + 00000000 0x2340: 00000000 + 7e020000 SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } + 00000000 SP_GS_OBJ_START: 0 + 00000808 TPL1_TP_TEX_OFFSET: 0x808 + 00000000 TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } !+ 00000002 0x2382: 00000002 !+ 00000000 TPL1_TP_FS_TEX_COUNT: 0 !+ 080604f0 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0x600a0 } !+ fcfc1108 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x1008 } !+ fff3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } + fcfcfc00 HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } !+ 00fcfc00 HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r0.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } !+ 01010002 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 2 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 1 } !+ 017f0202 HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 2 | CONSTOBJECTOFFSET = 2 | ENABLED | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 } !+ 007e0200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } !+ 007e0200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } !+ 007e0200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } !+ 00000003 HLSQ_UPDATE_CONTROL: 0x3 000555ac: 0000: c0023800 00200984 00000001 00000003 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 18 | GROUP_ID = 1 } { ADDR_LO = 0x9ba70 } 000555bc: 0000: c0014300 01000012 0009ba70 group_id: 1 count: 18 addr: 000000000009ba70 flags: 0 0009ba70: 0000: 00002200 082a0008 00002201 fcfc0081 00002203 0000fc00 0007220a 0008080f 0009ba90: 0020: 0009ba10 00000060 00000001 0000080f 0009ba40 00000030 00000001 0001228a 0009bab0: 0040: 7000411f 3000011f t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } 0009ba70: 0000: 00002200 082a0008 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } 0009ba78: 0000: 00002201 fcfc0081 t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } 0009ba80: 0000: 00002203 0000fc00 t0 write VFD_FETCH[0].INSTR_0 (220a) VFD_FETCH[0].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 | SWITCHNEXT } VFD_FETCH[0].INSTR_1: 0x9ba10 VFD_FETCH[0].INSTR_2: { SIZE = 0x60 } VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 } VFD_FETCH[0x1].INSTR_1: 0x9ba40 VFD_FETCH[0x1].INSTR_2: { SIZE = 0x30 } VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } 0009ba88: 0000: 0007220a 0008080f 0009ba10 00000060 00000001 0000080f 0009ba40 00000030 0009baa8: 0020: 00000001 t0 write VFD_DECODE[0].INSTR (228a) VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID | SWITCHNEXT } VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID } 0009baac: 0000: 0001228a 7000411f 3000011f t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = USE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x200000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 3 } draw[57] register values + 082a0008 VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } + fcfc0081 VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } + 0000fc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } + 0008080f VFD_FETCH[0].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 | SWITCHNEXT } !+ 0009ba10 VFD_FETCH[0].INSTR_1: 0x9ba10 + 00000060 VFD_FETCH[0].INSTR_2: { SIZE = 0x60 } + 00000001 VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } + 0000080f VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 } !+ 0009ba40 VFD_FETCH[0x1].INSTR_1: 0x9ba40 + 00000030 VFD_FETCH[0x1].INSTR_2: { SIZE = 0x30 } + 00000001 VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } + 7000411f VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID | SWITCHNEXT } + 3000011f VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID } 000555c8: 0000: c0023800 00200984 00000001 00000003 0016b094: 0000: c0013f00 00055328 000000ac t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 0016b0a0: 0000: c0014300 00040000 00000000 t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:001f9a7c ibsize:000000f7 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 001f9a7c: 0000: c0002600 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x4 001f9a84: 0000: 00000ec3 00000004 t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x68 001f9a8c: 0000: 00000f03 00000068 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 001f9a94: 0000: c0002600 00000000 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } 001f9a9c: 0000: 000023c0 080004f0 t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = 0x1d } event (null) 001f9aa4: 0000: c0004600 0000001d t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = FACENESS_FLUSH } event FACENESS_FLUSH 001f9aac: 0000: c0004600 0000001c t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 001f9ab4: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0 001f9abc: 0000: 00000cc6 00000000 t0 write UNKNOWN_0E42 (0e42) UNKNOWN_0E42: 0 001f9ac4: 0000: 00000e42 00000000 t0 write HLSQ_MODE_CONTROL (0e05) HLSQ_MODE_CONTROL: 0x2 001f9acc: 0000: 00000e05 00000002 t0 write UNKNOWN_0CC5 (0cc5) UNKNOWN_0CC5: 0x4 001f9ad4: 0000: 00000cc5 00000004 t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x7 001f9adc: 0000: 000023db 00000007 t0 write VFD_CONTROL_2 (2202) VFD_CONTROL_2: 0xfcfcfcfc 001f9ae4: 0000: 00002202 fcfcfcfc t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } 001f9aec: 0000: 00002203 fcfcfc00 t0 write VFD_CONTROL_4 (2204) VFD_CONTROL_4: 0xfcfc 001f9af4: 0000: 00002204 0000fcfc t0 write VFD_INDEX_OFFSET (2208) VFD_INDEX_OFFSET: 0 001f9afc: 0000: 00002208 00000000 t0 write UNKNOWN_2209 (2209) UNKNOWN_2209: 0 001f9b04: 0000: 00002209 00000000 t0 write UNKNOWN_2152 (2152) UNKNOWN_2152: 0 UNKNOWN_2153: 0 001f9b0c: 0000: 00012152 00000000 00000000 t0 write UNKNOWN_2156 (2156) UNKNOWN_2156: 0 001f9b18: 0000: 00002156 00000000 t0 write UNKNOWN_2154 (2154) UNKNOWN_2154: 0 001f9b20: 0000: 00002154 00000000 t0 write UNKNOWN_2155 (2155) UNKNOWN_2155: 0 001f9b28: 0000: 00002155 00000000 t0 write UNKNOWN_21C3 (21c3) UNKNOWN_21C3: 0x1d 001f9b30: 0000: 000021c3 0000001d t0 write PC_PRIM_VTX_CNTL2 (21c5) PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 001f9b38: 0000: 000021c5 00000012 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 001f9b40: 0000: 000021e5 00000000 t0 write GRAS_SU_MODE_CONTROL (2078) GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } 001f9b48: 0000: 00002078 00000000 t0 write UNKNOWN_2001 (2001) UNKNOWN_2001: 0 001f9b50: 0000: 00002001 00000000 t0 write GRAS_CNTL (2003) GRAS_CNTL: { IJ_PERSP } 001f9b58: 0000: 00002003 00000001 t0 write GRAS_CL_CLIP_CNTL (2000) GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } 001f9b60: 0000: 00002000 00188000 t0 write TPL1_TP_TEX_COUNT (2381) TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } 001f9b68: 0000: 00002381 00000000 t0 write TPL1_TP_FS_TEX_COUNT (23a0) TPL1_TP_FS_TEX_COUNT: 0x3 001f9b70: 0000: 000023a0 00000003 t0 write RB_ALPHA_CONTROL (20f8) RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } 001f9b78: 0000: 000020f8 00000e00 t0 write RB_RENDER_COMPONENTS (20fb) RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } 001f9b80: 0000: 000020fb 0000000f t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 001f9b88: 0000: c0014300 00040000 00000000 t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } 001f9b94: 0000: 00002200 000a0000 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } 001f9b9c: 0000: 00002201 fc030000 t0 write SP_INSTR_CACHE_CTRL (22c1) SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } 001f9ba4: 0000: 000022c1 000005c3 t0 write HLSQ_CONTROL_1_REG (23c1) HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } 001f9bac: 0000: 000023c1 fcfc0120 t0 write HLSQ_CONTROL_2_REG (23c2) HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 001f9bb4: 0000: 000023c2 27f3f3f0 t0 write HLSQ_VS_CONTROL_REG (23c5) HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } 001f9bbc: 0000: 000023c5 02010042 t0 write HLSQ_FS_CONTROL_REG (23c6) HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 001f9bc4: 0000: 000023c6 0041423e t0 write HLSQ_HS_CONTROL_REG (23c7) HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 001f9bcc: 0000: 000023c7 00404200 t0 write HLSQ_DS_CONTROL_REG (23c8) HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 001f9bd4: 0000: 000023c8 00404200 t0 write HLSQ_GS_CONTROL_REG (23c9) HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 001f9bdc: 0000: 000023c9 00404200 t0 write HLSQ_CS_CONTROL_REG (23ca) HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } 001f9be4: 0000: 000023ca 00004200 t0 write SP_SP_CTRL_REG (22c0) SP_SP_CTRL_REG: { 0x60010 } 001f9bec: 0000: 000022c0 00060010 t0 write UNKNOWN_21E6 (21e6) UNKNOWN_21E6: 0x1 001f9bf4: 0000: 000021e6 00000001 t0 write SP_VS_CTRL_REG0 (22c4) SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 001f9bfc: 0000: 000022c4 00200c10 t0 write SP_VS_CTRL_REG1 (22c5) SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } 001f9c04: 0000: 000022c5 01000042 t0 write VPC_ATTR (2140) VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | 0x40000000 } 001f9c0c: 0000: 00002140 40001004 t0 write VPC_PACK (2141) VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } 001f9c14: 0000: 00002141 00040400 t0 write PC_PRIM_VTX_CNTL (21c4) PC_PRIM_VTX_CNTL: { VAROUT = 1 } 001f9c1c: 0000: 000021c4 00000001 t0 write SP_VS_PARAM_REG (22c6) SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } UNKNOWN_22D7: 0xfcfc00 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 001f9c24: 0000: 001922c6 0010fc03 00001e03 00000000 00000000 00000000 00000000 00000000 * 001f9c64: 0040: 00000000 00000000 00fcfc00 00000008 00000000 00000000 00000000 00000000 * t0 write SP_VS_OBJ_OFFSET_REG (22e0) SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 001f9c90: 0000: 000022e0 00000000 t0 write SP_VS_OBJ_START (22e1) SP_VS_OBJ_START: 0x1 001f9c98: 0000: 000022e1 00000001 t0 write SP_VS_LENGTH_REG (22e5) SP_VS_LENGTH_REG: 2 001f9ca0: 0000: 000022e5 00000002 t3 opcode: CP_LOAD_STATE4 (30) (67 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } :2:0000:0000[56d81803x_20020003x] (sy)(ss)(nop3) shl.b r0.w, r0.w, 2 :1:0001:0004[20150000x_00000003x] cov.s32s16 hr0.x, r0.w :0:0002:0005[00000200x_00000000x] (rpt2)nop :1:0003:0008[201100f4x_00000000x] mova a0.x, hr0.x :0:0004:0009[00000500x_00000000x] (rpt5)nop :1:0005:0015[20154003x_00000c20x] mov.s32s32 r0.w, c :1:0006:0016[20154004x_00000c21x] mov.s32s32 r1.x, c :1:0007:0017[20154005x_00000c22x] mov.s32s32 r1.y, c :1:0008:0018[20156006x_00000c23x] (ul)mov.s32s32 r1.z, c :0:0009:0019[03000000x_00000000x] end :2:0010:0020[46f00007x_20050000x] shr.b r1.w, r0.x, 5 :2:0011:0021[43980008x_201f0000x] (nop2) and.b r2.x, r0.x, 31 :2:0012:0024[43980807x_201f0007x] (nop3) and.b r1.w, r1.w, 31 :2:0013:0028[46100807x_20100007x] (nop1) mul.u24 r1.w, r1.w, 16 :3:0014:0030[62040007x_00071014x] mad.u24 r1.w, c5.x, r2.x, r1.w :0:0015:0031[00000500x_00000000x] (rpt5)nop :6:0016:0037[c2c60f00x_04800006x] stlw.u32 l[r1.w], r0.w, 4 :0:0017:0038[04800000x_00000000x] chmask :0:0018:0039[05000000x_00000000x] chsh Stats: - shaderdb: 40 instr, 24 nops, 16 non-nops, 5 mov, 1 cov - shaderdb: 0 last-baryf, 0 half, 2 full, 5 constlen - shaderdb: 27 cat0, 6 cat1, 5 cat2, 1 cat3, 0 cat4, 0 cat5, 1 cat6, 0 cat7 - shaderdb: 0 sstall, 1 (ss), 1 (sy) 001f9ca8: 0000: c0413000 00a00000 00000000 20020003 56d81803 00000003 20150000 00000000 001f9cc8: 0020: 00000200 00000000 201100f4 00000000 00000500 00000c20 20154003 00000c21 001f9ce8: 0040: 20154004 00000c22 20154005 00000c23 20156006 00000000 03000000 20050000 001f9d08: 0060: 46f00007 201f0000 43980008 201f0007 43980807 20100007 46100807 00071014 001f9d28: 0080: 62040007 00000000 00000500 04800006 c2c60f00 00000000 04800000 00000000 001f9d48: 00a0: 05000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 * t0 write GRAS_SC_CONTROL (207b) GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = 0 | MSAA_DISABLE | RASTER_MODE = 0 } 001f9db4: 0000: 0000207b 00000808 t0 write RB_MSAA_CONTROL (20a2) RB_MSAA_CONTROL: { DISABLE | SAMPLES = 0 } 001f9dbc: 0000: 000020a2 00001000 t0 write RB_RENDER_CONTROL (20a1) RB_RENDER_CONTROL: { DISABLE_COLOR_PIPE | 0x2 } 001f9dc4: 0000: 000020a1 00000022 t0 write RB_DEPTH_CONTROL (2101) RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } 001f9dcc: 0000: 00002101 00000000 t0 write GRAS_ALPHA_CONTROL (2073) GRAS_ALPHA_CONTROL: { 0x2 } 001f9dd4: 0000: 00002073 00000002 t0 write RB_STENCIL_CONTROL (2106) RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } 001f9ddc: 0000: 00002106 00000000 t0 write RB_COPY_CONTROL (20fc) RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_FOUR | MODE = RB_COPY_DEPTH_STENCIL | FASTCLEAR = 0 | GMEM_BASE = 0 } RB_COPY_DEST_BASE: { BASE = 0x4f000 } RB_COPY_DEST_PITCH: { PITCH = 256 } RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_DISABLE | COMPONENT_ENABLE = 0xf | ENDIAN = ENDIAN_NONE | TILE = TILE4_3 } 001f9de4: 0000: 000320fc 00000052 0004f000 00000008 0303c068 t0 write UNKNOWN_20EF (20ef) UNKNOWN_20EF: 0 001f9df8: 0000: 000020ef 00000000 t0 write GRAS_SC_SCREEN_SCISSOR_TL (207c) GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } 001f9e00: 0000: 0001207c 00000000 003f003f t0 write RB_FRAME_BUFFER_DIMENSION (0ce0) RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } 001f9e0c: 0000: 00000ce0 00400040 t0 write 0xce1 (0ce1) 0xce1: 00000000 001f9e14: 0000: 00000ce1 00000000 t3 opcode: CP_LOAD_STATE4 (30) (11 dwords) { DST_OFF = 8 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } 001f9e28: 0.000000 0.000000 1.000000 1.000000 64.000000 64.000000 1.000000 1.000000 001f9e28: 0000: 00000000 00000000 3f800000 3f800000 42800000 42800000 3f800000 3f800000 001f9e1c: 0000: c0093000 00a00008 00000001 00000000 00000000 3f800000 3f800000 42800000 001f9e3c: 0020: 42800000 3f800000 3f800000 t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x80000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 2 } draw[58] register values + 00000004 UNKNOWN_0CC5: 0x4 + 00000000 UNKNOWN_0CC6: 0 + 00400040 RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } + 00000000 0xce1: 00000000 !+ 00000002 HLSQ_MODE_CONTROL: 0x2 + 00000000 UNKNOWN_0E42: 0 !+ 00000004 SP_MODE_CONTROL: 0x4 !+ 00000068 TPL1_TP_MODE_CONTROL: 0x68 !+ 00188000 GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } + 00000000 UNKNOWN_2001: 0 + 00000001 GRAS_CNTL: { IJ_PERSP } !+ 00000002 GRAS_ALPHA_CONTROL: { 0x2 } !+ 00000000 GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } !+ 00000808 GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = 0 | MSAA_DISABLE | RASTER_MODE = 0 } !+ 00000000 GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } !+ 003f003f GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } !+ 00000022 RB_RENDER_CONTROL: { DISABLE_COLOR_PIPE | 0x2 } !+ 00001000 RB_MSAA_CONTROL: { DISABLE | SAMPLES = 0 } + 00000000 UNKNOWN_20EF: 0 + 00000e00 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } + 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } !+ 00000052 RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_FOUR | MODE = RB_COPY_DEPTH_STENCIL | FASTCLEAR = 0 | GMEM_BASE = 0 } + 0004f000 RB_COPY_DEST_BASE: { BASE = 0x4f000 } + 00000008 RB_COPY_DEST_PITCH: { PITCH = 256 } !+ 0303c068 RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_DISABLE | COMPONENT_ENABLE = 0xf | ENDIAN = ENDIAN_NONE | TILE = TILE4_3 } + 00000000 RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } + 00000000 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } !+ 40001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | 0x40000000 } + 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } + 00000000 UNKNOWN_2152: 0 + 00000000 UNKNOWN_2153: 0 + 00000000 UNKNOWN_2154: 0 + 00000000 UNKNOWN_2155: 0 + 00000000 UNKNOWN_2156: 0 !+ 0000001d UNKNOWN_21C3: 0x1d !+ 00000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 } + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + 00000000 PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } + 00000001 UNKNOWN_21E6: 0x1 !+ 000a0000 VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } !+ fc030000 VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } + fcfcfcfc VFD_CONTROL_2: 0xfcfcfcfc !+ fcfcfc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } + 0000fcfc VFD_CONTROL_4: 0xfcfc + 00000000 VFD_INDEX_OFFSET: 0 + 00000000 UNKNOWN_2209: 0 + 00060010 SP_SP_CTRL_REG: { 0x60010 } + 000005c3 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } !+ 00200c10 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } !+ 01000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } !+ 0010fc03 SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } !+ 00001e03 SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00fcfc00 UNKNOWN_22D7: 0xfcfc00 + 00000008 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } !+ 00000001 SP_VS_OBJ_START: 0x1 !+ 00000002 SP_VS_LENGTH_REG: 2 + 00000000 TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } !+ 00000003 TPL1_TP_FS_TEX_COUNT: 0x3 !+ 080004f0 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } !+ fcfc0120 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } !+ 27f3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } !+ 02010042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } !+ 0041423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } !+ 00404200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } !+ 00404200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } !+ 00404200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00004200 HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } !+ 00000007 HLSQ_UPDATE_CONTROL: 0x7 001f9e48: 0000: c0023800 00080888 00000001 00000002 0016b0ac: 0000: c0013f00 001f9a7c 000000f7 t3 opcode: (null) (1d) (2 dwords) 0016b0b8: 0000: c0001d00 00000000 ############################################################ vertices: 0 ############################################################ cmdstream: 8 dwords t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:000555d8 ibsize:00000155 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 000555d8: 0000: c0002600 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x4 000555e0: 0000: 00000ec3 00000004 t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x68 000555e8: 0000: 00000f03 00000068 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 000555f0: 0000: c0002600 00000000 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } 000555f8: 0000: 000023c0 080004f0 t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = 0x1d } event (null) 00055600: 0000: c0004600 0000001d t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = FACENESS_FLUSH } event FACENESS_FLUSH 00055608: 0000: c0004600 0000001c t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00055610: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0 00055618: 0000: 00000cc6 00000000 t0 write UNKNOWN_0E42 (0e42) UNKNOWN_0E42: 0 00055620: 0000: 00000e42 00000000 t0 write HLSQ_MODE_CONTROL (0e05) HLSQ_MODE_CONTROL: 0x2 00055628: 0000: 00000e05 00000002 t0 write UNKNOWN_0CC5 (0cc5) UNKNOWN_0CC5: 0x4 00055630: 0000: 00000cc5 00000004 t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x7 00055638: 0000: 000023db 00000007 t0 write VFD_CONTROL_2 (2202) VFD_CONTROL_2: 0xfcfcfcfc 00055640: 0000: 00002202 fcfcfcfc t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } 00055648: 0000: 00002203 fcfcfc00 t0 write VFD_CONTROL_4 (2204) VFD_CONTROL_4: 0xfcfc 00055650: 0000: 00002204 0000fcfc t0 write VFD_INDEX_OFFSET (2208) VFD_INDEX_OFFSET: 0 00055658: 0000: 00002208 00000000 t0 write UNKNOWN_2209 (2209) UNKNOWN_2209: 0 00055660: 0000: 00002209 00000000 t0 write UNKNOWN_2152 (2152) UNKNOWN_2152: 0 UNKNOWN_2153: 0 00055668: 0000: 00012152 00000000 00000000 t0 write UNKNOWN_2156 (2156) UNKNOWN_2156: 0 00055674: 0000: 00002156 00000000 t0 write UNKNOWN_2154 (2154) UNKNOWN_2154: 0 0005567c: 0000: 00002154 00000000 t0 write UNKNOWN_2155 (2155) UNKNOWN_2155: 0 00055684: 0000: 00002155 00000000 t0 write UNKNOWN_21C3 (21c3) UNKNOWN_21C3: 0x1d 0005568c: 0000: 000021c3 0000001d t0 write PC_PRIM_VTX_CNTL2 (21c5) PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 00055694: 0000: 000021c5 00000012 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 0005569c: 0000: 000021e5 00000000 t0 write GRAS_SU_MODE_CONTROL (2078) GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } 000556a4: 0000: 00002078 00000000 t0 write UNKNOWN_2001 (2001) UNKNOWN_2001: 0 000556ac: 0000: 00002001 00000000 t0 write GRAS_CNTL (2003) GRAS_CNTL: { IJ_PERSP } 000556b4: 0000: 00002003 00000001 t0 write GRAS_CL_CLIP_CNTL (2000) GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } 000556bc: 0000: 00002000 00188000 t0 write TPL1_TP_TEX_COUNT (2381) TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } 000556c4: 0000: 00002381 00000000 t0 write TPL1_TP_FS_TEX_COUNT (23a0) TPL1_TP_FS_TEX_COUNT: 0x3 000556cc: 0000: 000023a0 00000003 t0 write RB_ALPHA_CONTROL (20f8) RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } 000556d4: 0000: 000020f8 00000e00 t0 write RB_RENDER_COMPONENTS (20fb) RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } 000556dc: 0000: 000020fb 0000000f t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 000556e4: 0000: c0014300 00040000 00000000 t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } 000556f0: 0000: 00002200 000a0000 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } 000556f8: 0000: 00002201 fc030000 t0 write SP_INSTR_CACHE_CTRL (22c1) SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } 00055700: 0000: 000022c1 000005c3 t0 write HLSQ_CONTROL_1_REG (23c1) HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } 00055708: 0000: 000023c1 fcfc0120 t0 write HLSQ_CONTROL_2_REG (23c2) HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 00055710: 0000: 000023c2 27f3f3f0 t0 write HLSQ_VS_CONTROL_REG (23c5) HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } 00055718: 0000: 000023c5 02010042 t0 write HLSQ_FS_CONTROL_REG (23c6) HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 1 } 00055720: 0000: 000023c6 0141423e t0 write HLSQ_HS_CONTROL_REG (23c7) HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00055728: 0000: 000023c7 00404200 t0 write HLSQ_DS_CONTROL_REG (23c8) HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00055730: 0000: 000023c8 00404200 t0 write HLSQ_GS_CONTROL_REG (23c9) HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00055738: 0000: 000023c9 00404200 t0 write HLSQ_CS_CONTROL_REG (23ca) HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } 00055740: 0000: 000023ca 00004200 t0 write SP_SP_CTRL_REG (22c0) SP_SP_CTRL_REG: { 0x60010 } 00055748: 0000: 000022c0 00060010 t0 write UNKNOWN_21E6 (21e6) UNKNOWN_21E6: 0x1 00055750: 0000: 000021e6 00000001 t0 write SP_VS_CTRL_REG0 (22c4) SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 00055758: 0000: 000022c4 00200c10 t0 write SP_VS_CTRL_REG1 (22c5) SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } 00055760: 0000: 000022c5 01000042 t0 write VPC_ATTR (2140) VPC_ATTR: { TOTALATTR = 8 | THRDASSIGN = 1 | ENABLE | 0x40000000 } 00055768: 0000: 00002140 42001008 t0 write VPC_PACK (2141) VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 8 | NUMNONPOSVSVAR = 6 } 00055770: 0000: 00002141 00060800 t0 write PC_PRIM_VTX_CNTL (21c4) PC_PRIM_VTX_CNTL: { VAROUT = 1 } 00055778: 0000: 000021c4 00000001 t0 write SP_VS_PARAM_REG (22c6) SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 2 } SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r1.w | B_COMPMASK = 0x3 } SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } UNKNOWN_22D7: 0xfcfc00 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 12 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 00055780: 0000: 001922c6 0020fc03 06071e03 00000000 00000000 00000000 00000000 00000000 * 000557c0: 0040: 00000000 00000000 00fcfc00 00000c08 00000000 00000000 00000000 00000000 * t0 write SP_VS_OBJ_OFFSET_REG (22e0) SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 000557ec: 0000: 000022e0 00000000 t0 write SP_VS_OBJ_START (22e1) SP_VS_OBJ_START: 0x1 000557f4: 0000: 000022e1 00000001 t0 write SP_VS_LENGTH_REG (22e5) SP_VS_LENGTH_REG: 2 000557fc: 0000: 000022e5 00000002 t3 opcode: CP_LOAD_STATE4 (30) (67 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } :2:0000:0000[56d81803x_20020003x] (sy)(ss)(nop3) shl.b r0.w, r0.w, 2 :1:0001:0004[20150000x_00000003x] cov.s32s16 hr0.x, r0.w :0:0002:0005[00000200x_00000000x] (rpt2)nop :1:0003:0008[201100f4x_00000000x] mova a0.x, hr0.x :0:0004:0009[00000500x_00000000x] (rpt5)nop :1:0005:0015[20154003x_00000c20x] mov.s32s32 r0.w, c :1:0006:0016[20154004x_00000c21x] mov.s32s32 r1.x, c :1:0007:0017[20154007x_00000c22x] mov.s32s32 r1.w, c :1:0008:0018[20156008x_00000c23x] (ul)mov.s32s32 r2.x, c :1:0009:0019[20554005x_00000000x] mov.s32s32 r1.y, 0 :1:0010:0020[20554006x_3f800000x] mov.s32s32 r1.z, 1065353216 :0:0011:0021[03000000x_00000000x] end :2:0012:0022[46f00009x_20050000x] shr.b r2.y, r0.x, 5 :2:0013:0023[4398000ax_201f0000x] (nop2) and.b r2.z, r0.x, 31 :2:0014:0026[43980809x_201f0009x] (nop3) and.b r2.y, r2.y, 31 :2:0015:0030[46100809x_20180009x] (nop1) mul.u24 r2.y, r2.y, 24 :3:0016:0032[62050009x_00091014x] mad.u24 r2.y, c5.x, r2.z, r2.y :0:0017:0033[00000500x_00000000x] (rpt5)nop :6:0018:0039[c2c61300x_04800006x] stlw.u32 l[r2.y], r0.w, 4 :6:0019:0040[c2c61310x_0280000ex] stlw.u32 l[r2.y+16], r1.w, 2 :0:0020:0041[04800000x_00000000x] chmask :0:0021:0042[05000000x_00000000x] chsh Stats: - shaderdb: 43 instr, 24 nops, 19 non-nops, 7 mov, 1 cov - shaderdb: 0 last-baryf, 0 half, 3 full, 5 constlen - shaderdb: 27 cat0, 8 cat1, 5 cat2, 1 cat3, 0 cat4, 0 cat5, 2 cat6, 0 cat7 - shaderdb: 0 sstall, 1 (ss), 1 (sy) 00055804: 0000: c0413000 00a00000 00000000 20020003 56d81803 00000003 20150000 00000000 00055824: 0020: 00000200 00000000 201100f4 00000000 00000500 00000c20 20154003 00000c21 00055844: 0040: 20154004 00000c22 20154007 00000c23 20156008 00000000 20554005 3f800000 00055864: 0060: 20554006 00000000 03000000 20050000 46f00009 201f0000 4398000a 201f0009 00055884: 0080: 43980809 20180009 46100809 00091014 62050009 00000000 00000500 04800006 000558a4: 00a0: c2c61300 0280000e c2c61310 00000000 04800000 00000000 05000000 00000000 * t0 write HLSQ_CONTROL_3_REG (23c3) HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } 00055910: 0000: 000023c3 fcfcfc00 t0 write HLSQ_CONTROL_4_REG (23c4) HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } 00055918: 0000: 000023c4 00fcfcfc t0 write SP_FS_CTRL_REG0 (22e8) SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 0 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE | PIXLODENABLE } SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 } 00055920: 0000: 000122e8 00700402 8010003e t0 write SP_FS_OBJ_OFFSET_REG (22ea) SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 } 0005592c: 0000: 000022ea 40420000 t0 write SP_FS_OBJ_START (22eb) SP_FS_OBJ_START: 0x1 00055934: 0000: 000022eb 00000001 t0 write SP_FS_LENGTH_REG (22ef) SP_FS_LENGTH_REG: 1 0005593c: 0000: 000022ef 00000001 t0 write SP_FS_OUTPUT_REG (22f0) SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r0.x | SAMPLEMASK_REGID = r0.x } 00055944: 0000: 000022f0 00000001 t0 write VPC_VARYING_INTERP[0].MODE (2142) VPC_VARYING_INTERP[0].MODE: 0xe000 0005594c: 0000: 00002142 0000e000 t0 write RB_FS_OUTPUT_REG (2100) RB_FS_OUTPUT_REG: { MRT = 1 } 00055954: 0000: 00002100 00000001 t3 opcode: CP_LOAD_STATE4 (30) (35 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 1 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } :2:0000:0000[57309902x_00002004x] (sy)(ss)(rpt1)bary.f (ei)r0.z, (r)4, r0.x :0:0001:0002[00000500x_00000000x] (rpt5)nop :5:0002:0008[a0c01f00x_00000005x] sam (f32)(xyzw)r0.x, r0.z, s#0, t#0 :0:0003:0009[03000000x_00000000x] end :0:0004:0010[00000000x_00000000x] nop :0:0005:0011[00000000x_00000000x] nop :0:0006:0012[00000000x_00000000x] nop :0:0007:0013[00000000x_00000000x] nop Stats: - shaderdb: 14 instr, 10 nops, 4 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 0 half, 1 full, 0 constlen - shaderdb: 11 cat0, 0 cat1, 2 cat2, 0 cat3, 0 cat4, 1 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 1 (ss), 1 (sy) 0005595c: 0000: c0213000 00700000 00000000 00002004 57309902 00000000 00000500 00000005 0005597c: 0020: a0c01f00 00000000 03000000 00000000 00000000 00000000 00000000 00000000 * t0 write RB_FS_OUTPUT (20f9) RB_FS_OUTPUT: { ENABLE_BLEND = 0 | SAMPLE_MASK = 0xffff } 000559e8: 0000: 000020f9 ffff0000 t0 write RB_MRT[0].CONTROL (20a4) RB_MRT[0].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0xf } 000559f0: 0000: 000020a4 0f000000 t0 write RB_MRT[0x1].CONTROL (20a9) RB_MRT[0x1].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0xf } 000559f8: 0000: 000020a9 0f000000 t0 write RB_MRT[0].BLEND_CONTROL (20a8) RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } 00055a00: 0000: 000020a8 00000000 t3 opcode: CP_LOAD_STATE4 (30) (5 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_TEX | NUM_UNIT = 1 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } { XY_MAG = A4XX_TEX_NEAREST | XY_MIN = A4XX_TEX_NEAREST | WRAP_S = A4XX_TEX_CLAMP_TO_EDGE | WRAP_T = A4XX_TEX_CLAMP_TO_EDGE | WRAP_R = A4XX_TEX_CLAMP_TO_EDGE | ANISO = A4XX_TEX_ANISO_1 | LOD_BIAS = 0.000000 | 0x60000 } { COMPARE_FUNC = FUNC_LEQUAL | UNNORM_COORDS | MIPFILTER_LINEAR_FAR | MAX_LOD = 0.000000 | MIN_LOD = 0.000000 | 0x1 } 00055a14: 0000: 00060920 00000067 00055a08: 0000: c0033000 00500000 00000000 00060920 00000067 t0 write GRAS_SC_CONTROL (207b) GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 0 | RASTER_MODE = 0 } 00055a1c: 0000: 0000207b 00000000 t0 write RB_MSAA_CONTROL (20a2) RB_MSAA_CONTROL: { SAMPLES = 0 } 00055a24: 0000: 000020a2 00000000 t0 write RB_RENDER_CONTROL (20a1) RB_RENDER_CONTROL: { 0 } 00055a2c: 0000: 000020a1 00000000 t0 write 0x2382 (2382) 0x2382: 00000000 00055a34: 0000: 00002382 00000000 t0 write RB_DEPTH_CONTROL (2101) RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } 00055a3c: 0000: 00002101 00000000 t0 write GRAS_ALPHA_CONTROL (2073) GRAS_ALPHA_CONTROL: { 0 } 00055a44: 0000: 00002073 00000000 t0 write RB_STENCIL_CONTROL (2106) RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } 00055a4c: 0000: 00002106 00000000 t0 write SP_FS_MRT[0].REG (22f1) SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = RB4_R8G8B8A8_UNORM } 00055a54: 0000: 000022f1 0001a000 t0 write RB_MRT[0].BUF_INFO (20a5) RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB4_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE4_3 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 256 } RB_MRT[0].BASE: 0x166000 RB_MRT[0].CONTROL3: { STRIDE = 0 } 00055a5c: 0000: 000220a5 000400da 00166000 00000000 t3 opcode: CP_LOAD_STATE4 (30) (11 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_TEX | NUM_UNIT = 1 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } { TILED | SWIZ_X = A4XX_TEX_X | SWIZ_Y = A4XX_TEX_Y | SWIZ_Z = A4XX_TEX_Z | SWIZ_W = A4XX_TEX_W | MIPLVLS = 0 | FMT = TFMT4_8_8_8_8_UNORM | TYPE = A4XX_TEX_2D | 0x2 } { HEIGHT = 64 | WIDTH = 64 } { PITCHALIGN = 0 | PITCH = 256 | SWAP = WZYX } { LAYERSZ = 0 | DEPTH = 1 | 0x20000 } { LAYERSZ = 4096 | BASE = 0x4f000 } { 5 = 0 } { 6 = 0 } { 7 = 0 } 00055a78: 0000: 27006883 00200040 00020000 00060000 0004f001 00000000 00000000 00000000 00055a6c: 0000: c0093000 00500000 00000001 27006883 00200040 00020000 00060000 0004f001 * t0 write VPC_VARYING_PS_REPL[0].MODE (214a) VPC_VARYING_PS_REPL[0].MODE: 0x99999999 00055a98: 0000: 0000214a 99999999 t0 write GRAS_SC_SCREEN_SCISSOR_TL (207c) GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } 00055aa0: 0000: 0001207c 00000000 003f003f t0 write GRAS_SC_WINDOW_SCISSOR_BR (209c) GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 00055aac: 0000: 0001209c 003f003f 00000000 t0 write RB_FRAME_BUFFER_DIMENSION (0ce0) RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } 00055ab8: 0000: 00000ce0 00400040 t0 write 0xce1 (0ce1) 0xce1: 00000000 00055ac0: 0000: 00000ce1 00000000 t0 write RB_RENDER_CONTROL2 (20a3) RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 | IJ_PERSP_PIXEL } 00055ac8: 0000: 000020a3 00001000 t0 write RB_MODE_CONTROL (20a0) RB_MODE_CONTROL: { WIDTH = 0 | HEIGHT = 0 | 0xc00000 } 00055ad0: 0000: 000020a0 00c00000 t3 opcode: CP_LOAD_STATE4 (30) (11 dwords) { DST_OFF = 8 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } 00055ae4: 0.000000 0.000000 0.000000 0.000000 64.000000 64.000000 64.000000 64.000000 00055ae4: 0000: 00000000 00000000 00000000 00000000 42800000 42800000 42800000 42800000 00055ad8: 0000: c0093000 00a00008 00000001 00000000 00000000 00000000 00000000 42800000 00055af8: 0020: 42800000 42800000 42800000 t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x80000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 2 } draw[59] register values + 00000004 UNKNOWN_0CC5: 0x4 + 00000000 UNKNOWN_0CC6: 0 + 00400040 RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } + 00000000 0xce1: 00000000 + 00000002 HLSQ_MODE_CONTROL: 0x2 + 00000000 UNKNOWN_0E42: 0 + 00000004 SP_MODE_CONTROL: 0x4 + 00000068 TPL1_TP_MODE_CONTROL: 0x68 + 00188000 GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } + 00000000 UNKNOWN_2001: 0 + 00000001 GRAS_CNTL: { IJ_PERSP } !+ 00000000 GRAS_ALPHA_CONTROL: { 0 } + 00000000 GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } !+ 00000000 GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 0 | RASTER_MODE = 0 } + 00000000 GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } + 003f003f GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } + 003f003f GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } + 00000000 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } !+ 00c00000 RB_MODE_CONTROL: { WIDTH = 0 | HEIGHT = 0 | 0xc00000 } !+ 00000000 RB_RENDER_CONTROL: { 0 } !+ 00000000 RB_MSAA_CONTROL: { SAMPLES = 0 } !+ 00001000 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 | IJ_PERSP_PIXEL } !+ 0f000000 RB_MRT[0].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0xf } !+ 000400da RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB4_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE4_3 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 256 } !+ 00166000 RB_MRT[0].BASE: 0x166000 !+ 00000000 RB_MRT[0].CONTROL3: { STRIDE = 0 } + 00000000 RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } + 0f000000 RB_MRT[0x1].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0xf } + 00000e00 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } !+ ffff0000 RB_FS_OUTPUT: { ENABLE_BLEND = 0 | SAMPLE_MASK = 0xffff } + 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } + 00000001 RB_FS_OUTPUT_REG: { MRT = 1 } + 00000000 RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } + 00000000 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } !+ 42001008 VPC_ATTR: { TOTALATTR = 8 | THRDASSIGN = 1 | ENABLE | 0x40000000 } !+ 00060800 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 8 | NUMNONPOSVSVAR = 6 } !+ 0000e000 VPC_VARYING_INTERP[0].MODE: 0xe000 !+ 99999999 VPC_VARYING_PS_REPL[0].MODE: 0x99999999 + 00000000 UNKNOWN_2152: 0 + 00000000 UNKNOWN_2153: 0 + 00000000 UNKNOWN_2154: 0 + 00000000 UNKNOWN_2155: 0 + 00000000 UNKNOWN_2156: 0 + 0000001d UNKNOWN_21C3: 0x1d + 00000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 } + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + 00000000 PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } + 00000001 UNKNOWN_21E6: 0x1 + 000a0000 VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } + fc030000 VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } + fcfcfcfc VFD_CONTROL_2: 0xfcfcfcfc + fcfcfc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } + 0000fcfc VFD_CONTROL_4: 0xfcfc + 00000000 VFD_INDEX_OFFSET: 0 + 00000000 UNKNOWN_2209: 0 + 00060010 SP_SP_CTRL_REG: { 0x60010 } + 000005c3 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } + 00200c10 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } + 01000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } !+ 0020fc03 SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 2 } !+ 06071e03 SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r1.w | B_COMPMASK = 0x3 } + 00000000 SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00fcfc00 UNKNOWN_22D7: 0xfcfc00 !+ 00000c08 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 12 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } + 00000001 SP_VS_OBJ_START: 0x1 + 00000002 SP_VS_LENGTH_REG: 2 !+ 00700402 SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 0 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE | PIXLODENABLE } !+ 8010003e SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 } !+ 40420000 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 } !+ 00000001 SP_FS_OBJ_START: 0x1 + 00000001 SP_FS_LENGTH_REG: 1 !+ 00000001 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r0.x | SAMPLEMASK_REGID = r0.x } !+ 0001a000 SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = RB4_R8G8B8A8_UNORM } + 00000000 TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } !+ 00000000 0x2382: 00000000 + 00000003 TPL1_TP_FS_TEX_COUNT: 0x3 + 080004f0 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } + fcfc0120 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } + 27f3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } + fcfcfc00 HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } !+ 00fcfcfc HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } + 02010042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } !+ 0141423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 1 } + 00404200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00004200 HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } + 00000007 HLSQ_UPDATE_CONTROL: 0x7 00055b04: 0000: c0023800 00080888 00000001 00000002 t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = CACHE_FLUSH } event CACHE_FLUSH 00055b14: 0000: c0004600 00000006 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00055b1c: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0x8000012 00055b24: 0000: 00000cc6 08000012 00173000: 0000: c0013f00 000555d8 00000155 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 0017300c: 0000: c0014300 00040000 00000000 t3 opcode: (null) (1d) (2 dwords) 00173018: 0000: c0001d00 00000000 ############################################################ vertices: 0 ############################################################ cmdstream: 48 dwords t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 0016b000: 0000: c0002600 00000000 t0 write UCHE_INVALIDATE0 (0e8a) UCHE_INVALIDATE0: 0 UCHE_INVALIDATE1: 0x12 0016b008: 0000: 00010e8a 00000000 00000012 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 0016b014: 0000: c0002600 00000000 t0 write RB_MODE_CONTROL (20a0) RB_MODE_CONTROL: { WIDTH = 64 | HEIGHT = 64 | ENABLE_GMEM } 0016b01c: 0000: 000020a0 00010202 t0 write RB_FRAME_BUFFER_DIMENSION (0ce0) RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } 0016b024: 0000: 00000ce0 00400040 t0 write 0xce1 (0ce1) 0xce1: 00000001 0016b02c: 0000: 00000ce1 00000001 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 0016b034: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0 0016b03c: 0000: 00000cc6 00000000 t3 opcode: (null) (1d) (2 dwords) 0016b044: 0000: c0001d00 00000000 t0 write GRAS_SC_WINDOW_SCISSOR_BR (209c) GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 0016b04c: 0000: 0001209c 003f003f 00000000 t0 write RB_BIN_OFFSET (210d) RB_BIN_OFFSET: { X = 0 | Y = 0 } 0016b058: 0000: 0000210d 00000000 t0 write GRAS_SC_WINDOW_SCISSOR_BR (209c) GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 0016b060: 0000: 0001209c 003f003f 00000000 t0 write UNKNOWN_2157 (2157) UNKNOWN_2157: 0x1 0016b06c: 0000: 00002157 00000001 t3 opcode: (null) (64) (2 dwords) 0016b074: 0000: c0006400 00000001 t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:00054994 ibsize:000000f6 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00054994: 0000: c0002600 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x4 0005499c: 0000: 00000ec3 00000004 t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x68 000549a4: 0000: 00000f03 00000068 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 000549ac: 0000: c0002600 00000000 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } 000549b4: 0000: 000023c0 080004f0 t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = 0x1d } event (null) 000549bc: 0000: c0004600 0000001d t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = FACENESS_FLUSH } event FACENESS_FLUSH 000549c4: 0000: c0004600 0000001c t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 000549cc: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0 000549d4: 0000: 00000cc6 00000000 t0 write UNKNOWN_0E42 (0e42) UNKNOWN_0E42: 0 000549dc: 0000: 00000e42 00000000 t0 write HLSQ_MODE_CONTROL (0e05) HLSQ_MODE_CONTROL: 0x2 000549e4: 0000: 00000e05 00000002 t0 write UNKNOWN_0CC5 (0cc5) UNKNOWN_0CC5: 0x4 000549ec: 0000: 00000cc5 00000004 t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x7 000549f4: 0000: 000023db 00000007 t0 write VFD_CONTROL_2 (2202) VFD_CONTROL_2: 0xfcfcfcfc 000549fc: 0000: 00002202 fcfcfcfc t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } 00054a04: 0000: 00002203 fcfcfc00 t0 write VFD_CONTROL_4 (2204) VFD_CONTROL_4: 0xfcfc 00054a0c: 0000: 00002204 0000fcfc t0 write VFD_INDEX_OFFSET (2208) VFD_INDEX_OFFSET: 0 00054a14: 0000: 00002208 00000000 t0 write UNKNOWN_2209 (2209) UNKNOWN_2209: 0 00054a1c: 0000: 00002209 00000000 t0 write UNKNOWN_2152 (2152) UNKNOWN_2152: 0 UNKNOWN_2153: 0 00054a24: 0000: 00012152 00000000 00000000 t0 write UNKNOWN_2156 (2156) UNKNOWN_2156: 0 00054a30: 0000: 00002156 00000000 t0 write UNKNOWN_2154 (2154) UNKNOWN_2154: 0 00054a38: 0000: 00002154 00000000 t0 write UNKNOWN_2155 (2155) UNKNOWN_2155: 0 00054a40: 0000: 00002155 00000000 t0 write UNKNOWN_21C3 (21c3) UNKNOWN_21C3: 0x1d 00054a48: 0000: 000021c3 0000001d t0 write PC_PRIM_VTX_CNTL2 (21c5) PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 00054a50: 0000: 000021c5 00000012 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 00054a58: 0000: 000021e5 00000000 t0 write GRAS_SU_MODE_CONTROL (2078) GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } 00054a60: 0000: 00002078 00000000 t0 write UNKNOWN_2001 (2001) UNKNOWN_2001: 0 00054a68: 0000: 00002001 00000000 t0 write GRAS_CNTL (2003) GRAS_CNTL: { IJ_PERSP } 00054a70: 0000: 00002003 00000001 t0 write GRAS_CL_CLIP_CNTL (2000) GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } 00054a78: 0000: 00002000 00188000 t0 write TPL1_TP_TEX_COUNT (2381) TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } 00054a80: 0000: 00002381 00000000 t0 write TPL1_TP_FS_TEX_COUNT (23a0) TPL1_TP_FS_TEX_COUNT: 0x3 00054a88: 0000: 000023a0 00000003 t0 write RB_ALPHA_CONTROL (20f8) RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } 00054a90: 0000: 000020f8 00000e00 t0 write RB_RENDER_COMPONENTS (20fb) RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } 00054a98: 0000: 000020fb 0000000f t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 00054aa0: 0000: c0014300 00040000 00000000 t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } 00054aac: 0000: 00002200 000a0000 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } 00054ab4: 0000: 00002201 fc030000 t0 write SP_INSTR_CACHE_CTRL (22c1) SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } 00054abc: 0000: 000022c1 000005c3 t0 write HLSQ_CONTROL_1_REG (23c1) HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } 00054ac4: 0000: 000023c1 fcfc0120 t0 write HLSQ_CONTROL_2_REG (23c2) HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 00054acc: 0000: 000023c2 27f3f3f0 t0 write HLSQ_VS_CONTROL_REG (23c5) HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } 00054ad4: 0000: 000023c5 02010042 t0 write HLSQ_FS_CONTROL_REG (23c6) HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00054adc: 0000: 000023c6 0041423e t0 write HLSQ_HS_CONTROL_REG (23c7) HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00054ae4: 0000: 000023c7 00404200 t0 write HLSQ_DS_CONTROL_REG (23c8) HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00054aec: 0000: 000023c8 00404200 t0 write HLSQ_GS_CONTROL_REG (23c9) HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00054af4: 0000: 000023c9 00404200 t0 write HLSQ_CS_CONTROL_REG (23ca) HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } 00054afc: 0000: 000023ca 00004200 t0 write SP_SP_CTRL_REG (22c0) SP_SP_CTRL_REG: { 0x60010 } 00054b04: 0000: 000022c0 00060010 t0 write UNKNOWN_21E6 (21e6) UNKNOWN_21E6: 0x1 00054b0c: 0000: 000021e6 00000001 t0 write SP_VS_CTRL_REG0 (22c4) SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 00054b14: 0000: 000022c4 00200c10 t0 write SP_VS_CTRL_REG1 (22c5) SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } 00054b1c: 0000: 000022c5 01000042 t0 write VPC_ATTR (2140) VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | 0x40000000 } 00054b24: 0000: 00002140 40001004 t0 write VPC_PACK (2141) VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } 00054b2c: 0000: 00002141 00040400 t0 write PC_PRIM_VTX_CNTL (21c4) PC_PRIM_VTX_CNTL: { VAROUT = 1 } 00054b34: 0000: 000021c4 00000001 t0 write SP_VS_PARAM_REG (22c6) SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } UNKNOWN_22D7: 0xfcfc00 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 00054b3c: 0000: 001922c6 0010fc03 00001e03 00000000 00000000 00000000 00000000 00000000 * 00054b7c: 0040: 00000000 00000000 00fcfc00 00000008 00000000 00000000 00000000 00000000 * t0 write SP_VS_OBJ_OFFSET_REG (22e0) SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 00054ba8: 0000: 000022e0 00000000 t0 write SP_VS_OBJ_START (22e1) SP_VS_OBJ_START: 0x1 00054bb0: 0000: 000022e1 00000001 t0 write SP_VS_LENGTH_REG (22e5) SP_VS_LENGTH_REG: 2 00054bb8: 0000: 000022e5 00000002 t3 opcode: CP_LOAD_STATE4 (30) (67 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } :2:0000:0000[56d81803x_20020003x] (sy)(ss)(nop3) shl.b r0.w, r0.w, 2 :1:0001:0004[20150000x_00000003x] cov.s32s16 hr0.x, r0.w :0:0002:0005[00000200x_00000000x] (rpt2)nop :1:0003:0008[201100f4x_00000000x] mova a0.x, hr0.x :0:0004:0009[00000500x_00000000x] (rpt5)nop :1:0005:0015[20154003x_00000c20x] mov.s32s32 r0.w, c :1:0006:0016[20154004x_00000c21x] mov.s32s32 r1.x, c :1:0007:0017[20154005x_00000c22x] mov.s32s32 r1.y, c :1:0008:0018[20156006x_00000c23x] (ul)mov.s32s32 r1.z, c :0:0009:0019[03000000x_00000000x] end :2:0010:0020[46f00007x_20050000x] shr.b r1.w, r0.x, 5 :2:0011:0021[43980008x_201f0000x] (nop2) and.b r2.x, r0.x, 31 :2:0012:0024[43980807x_201f0007x] (nop3) and.b r1.w, r1.w, 31 :2:0013:0028[46100807x_20100007x] (nop1) mul.u24 r1.w, r1.w, 16 :3:0014:0030[62040007x_00071014x] mad.u24 r1.w, c5.x, r2.x, r1.w :0:0015:0031[00000500x_00000000x] (rpt5)nop :6:0016:0037[c2c60f00x_04800006x] stlw.u32 l[r1.w], r0.w, 4 :0:0017:0038[04800000x_00000000x] chmask :0:0018:0039[05000000x_00000000x] chsh Stats: - shaderdb: 40 instr, 24 nops, 16 non-nops, 5 mov, 1 cov - shaderdb: 0 last-baryf, 0 half, 2 full, 5 constlen - shaderdb: 27 cat0, 6 cat1, 5 cat2, 1 cat3, 0 cat4, 0 cat5, 1 cat6, 0 cat7 - shaderdb: 0 sstall, 1 (ss), 1 (sy) 00054bc0: 0000: c0413000 00a00000 00000000 20020003 56d81803 00000003 20150000 00000000 00054be0: 0020: 00000200 00000000 201100f4 00000000 00000500 00000c20 20154003 00000c21 00054c00: 0040: 20154004 00000c22 20154005 00000c23 20156006 00000000 03000000 20050000 00054c20: 0060: 46f00007 201f0000 43980008 201f0007 43980807 20100007 46100807 00071014 00054c40: 0080: 62040007 00000000 00000500 04800006 c2c60f00 00000000 04800000 00000000 00054c60: 00a0: 05000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 * t0 write GRAS_ALPHA_CONTROL (2073) GRAS_ALPHA_CONTROL: { 0x2 } 00054ccc: 0000: 00002073 00000002 t0 write GRAS_SC_CONTROL (207b) GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = 4 | MSAA_DISABLE | RASTER_MODE = 0 } 00054cd4: 0000: 0000207b 00000a08 t0 write RB_MSAA_CONTROL (20a2) RB_MSAA_CONTROL: { DISABLE | SAMPLES = 4 } 00054cdc: 0000: 000020a2 00009000 t0 write RB_RENDER_CONTROL (20a1) RB_RENDER_CONTROL: { DISABLE_COLOR_PIPE | 0x2 } 00054ce4: 0000: 000020a1 00000022 t0 write RB_CLEAR_COLOR_DW0 (20cc) RB_CLEAR_COLOR_DW0: 0xff000000 RB_CLEAR_COLOR_DW1: 0 RB_CLEAR_COLOR_DW2: 0 RB_CLEAR_COLOR_DW3: 0 00054cec: 0000: 000320cc ff000000 00000000 00000000 00000000 t0 write RB_COPY_CONTROL (20fc) RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_FOUR | MODE = RB_COPY_CLEAR | FASTCLEAR = 0xf | GMEM_BASE = 0 } RB_COPY_DEST_BASE: { BASE = 0x4f000 } RB_COPY_DEST_PITCH: { PITCH = 256 } RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_IF_ALPHA_OFF | COMPONENT_ENABLE = 0 | ENDIAN = ENDIAN_NONE | TILE = TILE4_3 } 00054d00: 0000: 000320fc 00000f22 0004f000 00000008 03000868 t0 write GRAS_SC_SCREEN_SCISSOR_TL (207c) GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } 00054d14: 0000: 0001207c 00000000 003f003f t0 write RB_FRAME_BUFFER_DIMENSION (0ce0) RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } 00054d20: 0000: 00000ce0 00400040 t0 write 0xce1 (0ce1) 0xce1: 00000000 00054d28: 0000: 00000ce1 00000000 t3 opcode: CP_LOAD_STATE4 (30) (11 dwords) { DST_OFF = 8 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } 00054d3c: 0.000000 0.000000 1.000000 1.000000 64.000000 64.000000 1.000000 1.000000 00054d3c: 0000: 00000000 00000000 3f800000 3f800000 42800000 42800000 3f800000 3f800000 00054d30: 0000: c0093000 00a00008 00000001 00000000 00000000 3f800000 3f800000 42800000 00054d50: 0020: 42800000 3f800000 3f800000 t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x80000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 2 } draw[60] register values + 00000004 UNKNOWN_0CC5: 0x4 + 00000000 UNKNOWN_0CC6: 0 + 00400040 RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } + 00000000 0xce1: 00000000 + 00000002 HLSQ_MODE_CONTROL: 0x2 + 00000000 UNKNOWN_0E42: 0 + 00000000 UCHE_INVALIDATE0: 0 + 00000012 UCHE_INVALIDATE1: 0x12 + 00000004 SP_MODE_CONTROL: 0x4 + 00000068 TPL1_TP_MODE_CONTROL: 0x68 + 00188000 GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } + 00000000 UNKNOWN_2001: 0 + 00000001 GRAS_CNTL: { IJ_PERSP } !+ 00000002 GRAS_ALPHA_CONTROL: { 0x2 } + 00000000 GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } !+ 00000a08 GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = 4 | MSAA_DISABLE | RASTER_MODE = 0 } + 00000000 GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } + 003f003f GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } + 003f003f GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } + 00000000 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } !+ 00010202 RB_MODE_CONTROL: { WIDTH = 64 | HEIGHT = 64 | ENABLE_GMEM } !+ 00000022 RB_RENDER_CONTROL: { DISABLE_COLOR_PIPE | 0x2 } !+ 00009000 RB_MSAA_CONTROL: { DISABLE | SAMPLES = 4 } + ff000000 RB_CLEAR_COLOR_DW0: 0xff000000 + 00000000 RB_CLEAR_COLOR_DW1: 0 + 00000000 RB_CLEAR_COLOR_DW2: 0 + 00000000 RB_CLEAR_COLOR_DW3: 0 + 00000e00 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } + 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } !+ 00000f22 RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_FOUR | MODE = RB_COPY_CLEAR | FASTCLEAR = 0xf | GMEM_BASE = 0 } + 0004f000 RB_COPY_DEST_BASE: { BASE = 0x4f000 } + 00000008 RB_COPY_DEST_PITCH: { PITCH = 256 } !+ 03000868 RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_IF_ALPHA_OFF | COMPONENT_ENABLE = 0 | ENDIAN = ENDIAN_NONE | TILE = TILE4_3 } + 00000000 RB_BIN_OFFSET: { X = 0 | Y = 0 } !+ 40001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | 0x40000000 } !+ 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } + 00000000 UNKNOWN_2152: 0 + 00000000 UNKNOWN_2153: 0 + 00000000 UNKNOWN_2154: 0 + 00000000 UNKNOWN_2155: 0 + 00000000 UNKNOWN_2156: 0 + 00000001 UNKNOWN_2157: 0x1 + 0000001d UNKNOWN_21C3: 0x1d + 00000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 } + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + 00000000 PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } + 00000001 UNKNOWN_21E6: 0x1 + 000a0000 VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } + fc030000 VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } + fcfcfcfc VFD_CONTROL_2: 0xfcfcfcfc + fcfcfc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } + 0000fcfc VFD_CONTROL_4: 0xfcfc + 00000000 VFD_INDEX_OFFSET: 0 + 00000000 UNKNOWN_2209: 0 + 00060010 SP_SP_CTRL_REG: { 0x60010 } + 000005c3 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } + 00200c10 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } + 01000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } !+ 0010fc03 SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } !+ 00001e03 SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00fcfc00 UNKNOWN_22D7: 0xfcfc00 !+ 00000008 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } + 00000001 SP_VS_OBJ_START: 0x1 + 00000002 SP_VS_LENGTH_REG: 2 + 00000000 TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } + 00000003 TPL1_TP_FS_TEX_COUNT: 0x3 + 080004f0 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } + fcfc0120 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } + 27f3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } + 02010042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } !+ 0041423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00004200 HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } + 00000007 HLSQ_UPDATE_CONTROL: 0x7 00054d5c: 0000: c0023800 00080888 00000001 00000002 0016b07c: 0000: c0013f00 00054994 000000f6 t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:00054d6c ibsize:00000037 t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } 00054d6c: 0000: 00002200 082a0008 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00054d74: 0000: c0002600 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x1e 00054d7c: 0000: 00000ec3 0000001e t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x28 00054d84: 0000: 00000f03 00000028 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00054d8c: 0000: c0002600 00000000 t0 write HLSQ_MODE_CONTROL (0e05) HLSQ_MODE_CONTROL: 0x1 00054d94: 0000: 00000e05 00000001 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0x600a0 } 00054d9c: 0000: 000023c0 080604f0 t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x7 00054da4: 0000: 000023db 00000007 t0 write PC_RESTART_INDEX (21c6) PC_RESTART_INDEX: 0xffffffff 00054dac: 0000: 000021c6 ffffffff t0 write UNKNOWN_21E6 (21e6) UNKNOWN_21E6: 0x1 00054db4: 0000: 000021e6 00000001 t0 write UNKNOWN_21C3 (21c3) UNKNOWN_21C3: 0x1f 00054dbc: 0000: 000021c3 0000001f t0 write TPL1_TP_TEX_OFFSET (2380) TPL1_TP_TEX_OFFSET: 0x808 00054dc4: 0000: 00002380 00000808 t0 write GRAS_SU_POINT_MINMAX (2070) GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 4092.000000 } GRAS_SU_POINT_SIZE: 0.500000 00054dcc: 0000: 00012070 ffc00010 00000008 t0 write UNKNOWN_2152 (2152) UNKNOWN_2152: 0 UNKNOWN_2153: 0 00054dd8: 0000: 00012152 00000000 00000000 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00054de4: 0000: c0002600 00000000 t0 write UNKNOWN_0CC5 (0cc5) UNKNOWN_0CC5: 0x4 00054dec: 0000: 00000cc5 00000004 t0 write 0xcc4 (0cc4) 0xcc4: 00000000 00054df4: 0000: 00000cc4 00000000 t0 write 0xd03 (0d03) 0xd03: 80200000 00054dfc: 0000: 00000d03 80200000 t0 write UNKNOWN_0EC2 (0ec2) UNKNOWN_0EC2: 0x40000 00054e04: 0000: 00000ec2 00040000 t0 write VPC_DEBUG_ECO_CONTROL (0e64) VPC_DEBUG_ECO_CONTROL: 0x100 00054e0c: 0000: 00000e64 00000100 t0 write UNKNOWN_0E42 (0e42) UNKNOWN_0E42: 0 00054e14: 0000: 00000e42 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x1e 00054e1c: 0000: 00000ec3 0000001e t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x28 00054e24: 0000: 00000f03 00000028 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 00054e2c: 0000: c0014300 00040000 00000000 t0 write VFD_INDEX_OFFSET (2208) VFD_INDEX_OFFSET: 0 00054e38: 0000: 00002208 00000000 t0 write UNKNOWN_2209 (2209) UNKNOWN_2209: 0 00054e40: 0000: 00002209 00000000 0016b088: 0000: c0013f00 00054d6c 00000037 t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:00055328 ibsize:000000ac t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x3 00055328: 0000: 000023db 00000003 t0 write SP_INSTR_CACHE_CTRL (22c1) SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } 00055330: 0000: 000022c1 000005c3 t0 write HLSQ_CONTROL_1_REG (23c1) HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x1008 } 00055338: 0000: 000023c1 fcfc1108 t0 write HLSQ_CONTROL_2_REG (23c2) HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 00055340: 0000: 000023c2 fff3f3f0 t0 write HLSQ_VS_CONTROL_REG (23c5) HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 2 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 1 } 00055348: 0000: 000023c5 01010002 t0 write HLSQ_HS_CONTROL_REG (23c7) HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 00055350: 0000: 000023c7 007e0200 t0 write HLSQ_DS_CONTROL_REG (23c8) HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 00055358: 0000: 000023c8 007e0200 t0 write HLSQ_GS_CONTROL_REG (23c9) HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 00055360: 0000: 000023c9 007e0200 t0 write HLSQ_FS_CONTROL_REG (23c6) HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 2 | CONSTOBJECTOFFSET = 2 | ENABLED | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 } 00055368: 0000: 000023c6 017f0202 t0 write SP_VS_OBJ_OFFSET_REG (22e0) SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 00055370: 0000: 000022e0 00000000 t0 write SP_HS_OBJ_OFFSET_REG (230d) SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } 00055378: 0000: 0000230d 7e020000 t0 write SP_DS_OBJ_OFFSET_REG (2334) SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } 00055380: 0000: 00002334 7e020000 t0 write SP_GS_OBJ_OFFSET_REG (235b) SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } 00055388: 0000: 0000235b 7e020000 t0 write SP_FS_OBJ_OFFSET_REG (22ea) SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } 00055390: 0000: 000022ea 7e020000 t0 write SP_VS_OBJ_START (22e1) SP_VS_OBJ_START: 0x49000 00049000: 0000: 00000000 13000000 00000000 00000000 00000000 00000000 00000000 00000000 * :0:0000:0000[13000000x_00000000x] (sy)end :0:0001:0001[00000000x_00000000x] nop :0:0002:0002[00000000x_00000000x] nop :0:0003:0003[00000000x_00000000x] nop :0:0004:0004[00000000x_00000000x] nop Stats: - shaderdb: 5 instr, 4 nops, 1 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 0 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 0 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) 00055398: 0000: 000022e1 00049000 t0 write SP_HS_OBJ_START (230e) SP_HS_OBJ_START: 0 000553a0: 0000: 0000230e 00000000 t0 write SP_DS_OBJ_START (2335) SP_DS_OBJ_START: 0 000553a8: 0000: 00002335 00000000 t0 write SP_GS_OBJ_START (235c) SP_GS_OBJ_START: 0 000553b0: 0000: 0000235c 00000000 t0 write SP_VS_LENGTH_REG (22e5) SP_VS_LENGTH_REG: 1 000553b8: 0000: 000022e5 00000001 t3 opcode: CP_LOAD_STATE4 (30) (3 dwords) { DST_OFF = 0 | STATE_SRC = SS4_INDIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 1 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0x49000 } :0:0000:0000[13000000x_00000000x] (sy)end :0:0001:0001[00000000x_00000000x] nop :0:0002:0002[00000000x_00000000x] nop :0:0003:0003[00000000x_00000000x] nop :0:0004:0004[00000000x_00000000x] nop Stats: - shaderdb: 5 instr, 4 nops, 1 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 0 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 0 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) 000553c0: 0000: c0013000 00620000 00049000 t0 write 0x2072 (2072) 0x2072: 00000000 000553cc: 0000: 00002072 00000000 t0 write UNKNOWN_2155 (2155) UNKNOWN_2155: 0 000553d4: 0000: 00002155 00000000 t0 write GRAS_CNTL (2003) GRAS_CNTL: { IJ_PERSP } 000553dc: 0000: 00002003 00000001 t0 write VPC_VARYING_INTERP[0].MODE (2142) VPC_VARYING_INTERP[0].MODE: 0 000553e4: 0000: 00002142 00000000 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0x600a0 } 000553ec: 0000: 000023c0 080604f0 t0 write HLSQ_CONTROL_3_REG (23c3) HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } 000553f4: 0000: 000023c3 fcfcfc00 t0 write HLSQ_CONTROL_4_REG (23c4) HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r0.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } 000553fc: 0000: 000023c4 00fcfc00 t0 write SP_FS_CTRL_REG0 (22e8) SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE } SP_FS_CTRL_REG1: { CONSTLENGTH = 2 | VARYING | 0x80000000 } 00055404: 0000: 000122e8 00340412 80100002 t0 write SP_FS_OBJ_START (22eb) SP_FS_OBJ_START: 0x46000 00046000: 0000: 00002000 5730cb00 00000000 03000000 00000000 00000000 00000000 00000000 * :2:0000:0000[5730cb00x_00002000x] (sy)(rpt3)bary.f (ei)hr0.x, (r)0, r0.x :0:0001:0004[03000000x_00000000x] end :0:0002:0005[00000000x_00000000x] nop :0:0003:0006[00000000x_00000000x] nop :0:0004:0007[00000000x_00000000x] nop :0:0005:0008[00000000x_00000000x] nop Stats: - shaderdb: 9 instr, 4 nops, 5 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 1 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 4 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) 00055410: 0000: 000022eb 00046000 t0 write SP_FS_LENGTH_REG (22ef) SP_FS_LENGTH_REG: 1 00055418: 0000: 000022ef 00000001 t0 write RB_RENDER_COMPONENTS (20fb) RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } 00055420: 0000: 000020fb 0000000f t3 opcode: CP_LOAD_STATE4 (30) (3 dwords) { DST_OFF = 0 | STATE_SRC = SS4_INDIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 1 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0x46000 } :2:0000:0000[5730cb00x_00002000x] (sy)(rpt3)bary.f (ei)hr0.x, (r)0, r0.x :0:0001:0004[03000000x_00000000x] end :0:0002:0005[00000000x_00000000x] nop :0:0003:0006[00000000x_00000000x] nop :0:0004:0007[00000000x_00000000x] nop :0:0005:0008[00000000x_00000000x] nop Stats: - shaderdb: 9 instr, 4 nops, 5 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 1 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 4 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) 00055428: 0000: c0013000 00720000 00046000 t0 write SP_SP_CTRL_REG (22c0) SP_SP_CTRL_REG: { 0x60010 } 00055434: 0000: 000022c0 00060010 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 28 | GROUP_ID = 3 } { ADDR_LO = 0x9bb20 } 0005543c: 0000: c0014300 0300001c 0009bb20 t0 write RB_DEPTH_INFO (2103) RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTH4_NONE | DEPTH_BASE = 0 } RB_DEPTH_PITCH: 0 RB_DEPTH_PITCH2: 0 00055448: 0000: 00022103 00000000 00000000 00000000 t0 write GRAS_DEPTH_CONTROL (2077) GRAS_DEPTH_CONTROL: { FORMAT = DEPTH4_NONE } 00055458: 0000: 00002077 00000000 t0 write RB_STENCIL_INFO (2108) RB_STENCIL_INFO: { STENCIL_BASE = 0 } RB_STENCIL_PITCH: 0 0x210a: 00000000 00055460: 0000: 00022108 00000000 00000000 00000000 t0 write 0x2002 (2002) 0x2002: 00000000 00055470: 0000: 00002002 00000000 t0 write RB_ALPHA_CONTROL (20f8) RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } 00055478: 0000: 000020f8 00000e00 t0 write RB_MRT[0].CONTROL (20a4) RB_MRT[0].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0x7 } 00055480: 0000: 000020a4 07000c00 t0 write RB_MRT[0].BLEND_CONTROL (20a8) RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } 00055488: 0000: 000020a8 00000000 t0 write GRAS_CL_CLIP_CNTL (2000) GRAS_CL_CLIP_CNTL: { 0x80000 } 00055490: 0000: 00002000 00080000 t0 write GRAS_SU_POLY_OFFSET_SCALE (2074) GRAS_SU_POLY_OFFSET_SCALE: 0.000000 GRAS_SU_POLY_OFFSET_OFFSET: 0.000000 GRAS_SU_POLY_OFFSET_CLAMP: 0.000000 00055498: 0000: 00022074 00000000 00000000 00000000 t0 write GRAS_SU_MODE_CONTROL (2078) GRAS_SU_MODE_CONTROL: { FRONT_CW | LINEHALFWIDTH = 0.500000 | MSAA_ENABLE | RENDERING_PASS } 000554a8: 0000: 00002078 00102014 t0 write GRAS_SC_SCREEN_SCISSOR_TL (207c) GRAS_SC_SCREEN_SCISSOR_TL: { X = 2 | Y = 13 } GRAS_SC_SCREEN_SCISSOR_BR: { X = 33 | Y = 44 } 000554b0: 0000: 0001207c 000d0002 002c0021 t0 write GRAS_CL_VPORT_XOFFSET_0 (2008) GRAS_CL_VPORT_XOFFSET_0: 18.000000 GRAS_CL_VPORT_XSCALE_0: 16.000000 GRAS_CL_VPORT_YOFFSET_0: 29.000000 GRAS_CL_VPORT_YSCALE_0: 16.000000 GRAS_CL_VPORT_ZOFFSET_0: 0.500000 GRAS_CL_VPORT_ZSCALE_0: 0.500000 000554bc: 0000: 00052008 41900000 41800000 41e80000 41800000 3f000000 3f000000 t0 write GRAS_CL_GB_CLIP_ADJ (2004) GRAS_CL_GB_CLIP_ADJ: { HORZ = 511 | VERT = 511 } 000554d8: 0000: 00002004 0007fdff t0 write GRAS_SC_CONTROL (207b) GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 4 | RASTER_MODE = 0 } 000554e0: 0000: 0000207b 00000200 t0 write 0x2382 (2382) 0x2382: 00000002 000554e8: 0000: 00002382 00000002 t0 write RB_MSAA_CONTROL (20a2) RB_MSAA_CONTROL: { SAMPLES = 4 } 000554f0: 0000: 000020a2 00008000 t0 write RB_RENDER_CONTROL2 (20a3) RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 4 | IJ_PERSP_PIXEL } 000554f8: 0000: 000020a3 00001200 t0 write RB_MRT[0].BUF_INFO (20a5) RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB4_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_ALWAYS | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 1024 } RB_MRT[0].BASE: 0 RB_MRT[0].CONTROL3: { STRIDE = 64 } 00055500: 0000: 000220a5 0010029a 00000000 00000200 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 43 | GROUP_ID = 2 } { ADDR_LO = 0x9bb90 } 00055510: 0000: c0014300 0200002b 0009bb90 t0 write 0x215c (215c) 0x215c: 00000000 0x215d: 00000000 0005551c: 0000: 0001215c 00000000 00000000 t0 write 0x215f (215f) 0x215f: 00000000 00055528: 0000: 0000215f 00000000 t0 write 0x215e (215e) 0x215e: 00000000 00055530: 0000: 0000215e 00000000 t0 write 0x2161 (2161) 0x2161: 00000000 0x2162: 00000000 00055538: 0000: 00012161 00000000 00000000 t0 write 0x2164 (2164) 0x2164: 00000000 00055544: 0000: 00002164 00000000 t0 write 0x2163 (2163) 0x2163: 00000000 0005554c: 0000: 00002163 00000000 t0 write 0x2166 (2166) 0x2166: 00000000 0x2167: 00000000 00055554: 0000: 00012166 00000000 00000000 t0 write 0x2169 (2169) 0x2169: 00000000 00055560: 0000: 00002169 00000000 t0 write 0x2168 (2168) 0x2168: 00000000 00055568: 0000: 00002168 00000000 t0 write 0x216b (216b) 0x216b: 00000000 0x216c: 00000000 00055570: 0000: 0001216b 00000000 00000000 t0 write VPC_SO_FLUSH_WADDR_3 (216e) VPC_SO_FLUSH_WADDR_3: 0 0005557c: 0000: 0000216e 00000000 t0 write 0x216d (216d) 0x216d: 00000000 00055584: 0000: 0000216d 00000000 t0 write UNKNOWN_2156 (2156) UNKNOWN_2156: 0 0005558c: 0000: 00002156 00000000 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 18 | GROUP_ID = 1 } { ADDR_LO = 0x9bc40 } 00055594: 0000: c0014300 01000012 0009bc40 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 15 | GROUP_ID = 0 } { ADDR_LO = 0x9bc90 } 000555a0: 0000: c0014300 0000000f 0009bc90 group_id: 0 count: 15 addr: 000000000009bc90 flags: 0 0009bc90: 0000: 00002073 00000000 00002101 00000000 00002106 00000000 000021e5 00000000 0009bcb0: 0020: 0001210b 00000000 00000000 00002381 00000000 000023a0 00000000 t0 write GRAS_ALPHA_CONTROL (2073) GRAS_ALPHA_CONTROL: { 0 } 0009bc90: 0000: 00002073 00000000 t0 write RB_DEPTH_CONTROL (2101) RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } 0009bc98: 0000: 00002101 00000000 t0 write RB_STENCIL_CONTROL (2106) RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } 0009bca0: 0000: 00002106 00000000 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 0009bca8: 0000: 000021e5 00000000 t0 write RB_STENCILREFMASK (210b) RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 0009bcb0: 0000: 0001210b 00000000 00000000 t0 write TPL1_TP_TEX_COUNT (2381) TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } 0009bcbc: 0000: 00002381 00000000 t0 write TPL1_TP_FS_TEX_COUNT (23a0) TPL1_TP_FS_TEX_COUNT: 0 0009bcc4: 0000: 000023a0 00000000 group_id: 1 count: 18 addr: 000000000009bc40 flags: 0 0009bc40: 0000: 00002200 082a0008 00002201 fcfc0081 00002203 0000fc00 0007220a 0008080f 0009bc60: 0020: 0009bac0 00000060 00000001 0000080f 0009baf0 00000030 00000001 0001228a 0009bc80: 0040: 7000411f 3000011f t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } 0009bc40: 0000: 00002200 082a0008 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } 0009bc48: 0000: 00002201 fcfc0081 t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } 0009bc50: 0000: 00002203 0000fc00 t0 write VFD_FETCH[0].INSTR_0 (220a) VFD_FETCH[0].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 | SWITCHNEXT } VFD_FETCH[0].INSTR_1: 0x9bac0 VFD_FETCH[0].INSTR_2: { SIZE = 0x60 } VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 } VFD_FETCH[0x1].INSTR_1: 0x9baf0 VFD_FETCH[0x1].INSTR_2: { SIZE = 0x30 } VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } 0009bc58: 0000: 0007220a 0008080f 0009bac0 00000060 00000001 0000080f 0009baf0 00000030 0009bc78: 0020: 00000001 t0 write VFD_DECODE[0].INSTR (228a) VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID | SWITCHNEXT } VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID } 0009bc7c: 0000: 0001228a 7000411f 3000011f group_id: 2 count: 43 addr: 000000000009bb90 flags: 0 0009bb90: 0000: 000020a1 00000000 000022f1 0001a100 000022f0 fc00fc01 00002100 00000001 0009bbb0: 0020: 000021e5 00000000 000020f9 ffff0501 0000214a 00000000 00002140 42001004 0009bbd0: 0040: 001922c6 0010fc04 00001e00 00000000 00000000 00000000 00000000 00000000 * 0009bc10: 0080: 00000000 00000000 00fcfc00 00000008 00000000 00000000 00000000 00000000 * t0 write RB_RENDER_CONTROL (20a1) RB_RENDER_CONTROL: { 0 } 0009bb90: 0000: 000020a1 00000000 t0 write SP_FS_MRT[0].REG (22f1) SP_FS_MRT[0].REG: { REGID = r0.x | HALF_PRECISION | MRTFORMAT = RB4_R8G8B8A8_UNORM } 0009bb98: 0000: 000022f1 0001a100 t0 write SP_FS_OUTPUT_REG (22f0) SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 0009bba0: 0000: 000022f0 fc00fc01 t0 write RB_FS_OUTPUT_REG (2100) RB_FS_OUTPUT_REG: { MRT = 1 } 0009bba8: 0000: 00002100 00000001 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 0009bbb0: 0000: 000021e5 00000000 t0 write RB_FS_OUTPUT (20f9) RB_FS_OUTPUT: { ENABLE_BLEND = 0x1 | INDEPENDENT_BLEND | SAMPLE_MASK = 0xffff | 0x400 } 0009bbb8: 0000: 000020f9 ffff0501 t0 write VPC_VARYING_PS_REPL[0].MODE (214a) VPC_VARYING_PS_REPL[0].MODE: 0 0009bbc0: 0000: 0000214a 00000000 t0 write VPC_ATTR (2140) VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 } 0009bbc8: 0000: 00002140 42001004 t0 write SP_VS_PARAM_REG (22c6) SP_VS_PARAM_REG: { POSREGID = r1.x | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } SP_VS_OUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } UNKNOWN_22D7: 0xfcfc00 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 0009bbd0: 0000: 001922c6 0010fc04 00001e00 00000000 00000000 00000000 00000000 00000000 * 0009bc10: 0040: 00000000 00000000 00fcfc00 00000008 00000000 00000000 00000000 00000000 * group_id: 3 count: 28 addr: 000000000009bb20 flags: 0 0009bb20: 0000: 000021c4 02000001 00002141 00040400 00002001 00000000 000022c4 00200800 0009bb40: 0020: 000022c5 08000002 0000230c 00000000 00002318 00000000 00002319 00000000 0009bb60: 0040: 00002340 00000000 00002202 fcfcfcfc 00002204 0000fcfc 00002154 00000000 0009bb80: 0060: 000021e7 00000000 000021c5 00000012 t0 write PC_PRIM_VTX_CNTL (21c4) PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } 0009bb20: 0000: 000021c4 02000001 t0 write VPC_PACK (2141) VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } 0009bb28: 0000: 00002141 00040400 t0 write UNKNOWN_2001 (2001) UNKNOWN_2001: 0 0009bb30: 0000: 00002001 00000000 t0 write SP_VS_CTRL_REG0 (22c4) SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 2 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 0009bb38: 0000: 000022c4 00200800 t0 write SP_VS_CTRL_REG1 (22c5) SP_VS_CTRL_REG1: { CONSTLENGTH = 2 | INITIALOUTSTANDING = 8 } 0009bb40: 0000: 000022c5 08000002 t0 write 0x230c (230c) 0x230c: 00000000 0009bb48: 0000: 0000230c 00000000 t0 write 0x2318 (2318) 0x2318: 00000000 0009bb50: 0000: 00002318 00000000 t0 write 0x2319 (2319) 0x2319: 00000000 0009bb58: 0000: 00002319 00000000 t0 write 0x2340 (2340) 0x2340: 00000000 0009bb60: 0000: 00002340 00000000 t0 write VFD_CONTROL_2 (2202) VFD_CONTROL_2: 0xfcfcfcfc 0009bb68: 0000: 00002202 fcfcfcfc t0 write VFD_CONTROL_4 (2204) VFD_CONTROL_4: 0xfcfc 0009bb70: 0000: 00002204 0000fcfc t0 write UNKNOWN_2154 (2154) UNKNOWN_2154: 0 0009bb78: 0000: 00002154 00000000 t0 write PC_HS_PARAM (21e7) PC_HS_PARAM: { VERTICES_OUT = 0 | SPACING = EQUAL_SPACING } 0009bb80: 0000: 000021e7 00000000 t0 write PC_PRIM_VTX_CNTL2 (21c5) PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 0009bb88: 0000: 000021c5 00000012 t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = USE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x200000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 3 } draw[61] register values + 00000000 0xcc4: 00000000 + 00000004 UNKNOWN_0CC5: 0x4 + 80200000 0xd03: 80200000 !+ 00000001 HLSQ_MODE_CONTROL: 0x1 + 00000000 UNKNOWN_0E42: 0 + 00000100 VPC_DEBUG_ECO_CONTROL: 0x100 + 00040000 UNKNOWN_0EC2: 0x40000 !+ 0000001e SP_MODE_CONTROL: 0x1e !+ 00000028 TPL1_TP_MODE_CONTROL: 0x28 !+ 00080000 GRAS_CL_CLIP_CNTL: { 0x80000 } + 00000000 UNKNOWN_2001: 0 + 00000000 0x2002: 00000000 + 00000001 GRAS_CNTL: { IJ_PERSP } + 0007fdff GRAS_CL_GB_CLIP_ADJ: { HORZ = 511 | VERT = 511 } + 41900000 GRAS_CL_VPORT_XOFFSET_0: 18.000000 + 41800000 GRAS_CL_VPORT_XSCALE_0: 16.000000 + 41e80000 GRAS_CL_VPORT_YOFFSET_0: 29.000000 + 41800000 GRAS_CL_VPORT_YSCALE_0: 16.000000 + 3f000000 GRAS_CL_VPORT_ZOFFSET_0: 0.500000 + 3f000000 GRAS_CL_VPORT_ZSCALE_0: 0.500000 + ffc00010 GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 4092.000000 } + 00000008 GRAS_SU_POINT_SIZE: 0.500000 + 00000000 0x2072: 00000000 !+ 00000000 GRAS_ALPHA_CONTROL: { 0 } + 00000000 GRAS_SU_POLY_OFFSET_SCALE: 0.000000 + 00000000 GRAS_SU_POLY_OFFSET_OFFSET: 0.000000 + 00000000 GRAS_SU_POLY_OFFSET_CLAMP: 0.000000 + 00000000 GRAS_DEPTH_CONTROL: { FORMAT = DEPTH4_NONE } !+ 00102014 GRAS_SU_MODE_CONTROL: { FRONT_CW | LINEHALFWIDTH = 0.500000 | MSAA_ENABLE | RENDERING_PASS } !+ 00000200 GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 4 | RASTER_MODE = 0 } !+ 000d0002 GRAS_SC_SCREEN_SCISSOR_TL: { X = 2 | Y = 13 } !+ 002c0021 GRAS_SC_SCREEN_SCISSOR_BR: { X = 33 | Y = 44 } !+ 00000000 RB_RENDER_CONTROL: { 0 } !+ 00008000 RB_MSAA_CONTROL: { SAMPLES = 4 } !+ 00001200 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 4 | IJ_PERSP_PIXEL } !+ 07000c00 RB_MRT[0].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0x7 } !+ 0010029a RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB4_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_ALWAYS | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 1024 } !+ 00000000 RB_MRT[0].BASE: 0 !+ 00000200 RB_MRT[0].CONTROL3: { STRIDE = 64 } + 00000000 RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } + 00000e00 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } !+ ffff0501 RB_FS_OUTPUT: { ENABLE_BLEND = 0x1 | INDEPENDENT_BLEND | SAMPLE_MASK = 0xffff | 0x400 } + 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } + 00000001 RB_FS_OUTPUT_REG: { MRT = 1 } + 00000000 RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } + 00000000 RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTH4_NONE | DEPTH_BASE = 0 } + 00000000 RB_DEPTH_PITCH: 0 + 00000000 RB_DEPTH_PITCH2: 0 + 00000000 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } + 00000000 RB_STENCIL_INFO: { STENCIL_BASE = 0 } + 00000000 RB_STENCIL_PITCH: 0 + 00000000 0x210a: 00000000 + 00000000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } + 00000000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } !+ 42001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 } + 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } !+ 00000000 VPC_VARYING_INTERP[0].MODE: 0 !+ 00000000 VPC_VARYING_PS_REPL[0].MODE: 0 + 00000000 UNKNOWN_2152: 0 + 00000000 UNKNOWN_2153: 0 + 00000000 UNKNOWN_2154: 0 + 00000000 UNKNOWN_2155: 0 + 00000000 UNKNOWN_2156: 0 + 00000000 0x215c: 00000000 + 00000000 0x215d: 00000000 + 00000000 0x215e: 00000000 + 00000000 0x215f: 00000000 + 00000000 0x2161: 00000000 + 00000000 0x2162: 00000000 + 00000000 0x2163: 00000000 + 00000000 0x2164: 00000000 + 00000000 0x2166: 00000000 + 00000000 0x2167: 00000000 + 00000000 0x2168: 00000000 + 00000000 0x2169: 00000000 + 00000000 0x216b: 00000000 + 00000000 0x216c: 00000000 + 00000000 0x216d: 00000000 + 00000000 VPC_SO_FLUSH_WADDR_3: 0 !+ 0000001f UNKNOWN_21C3: 0x1f !+ 02000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + ffffffff PC_RESTART_INDEX: 0xffffffff + 00000000 PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } + 00000001 UNKNOWN_21E6: 0x1 + 00000000 PC_HS_PARAM: { VERTICES_OUT = 0 | SPACING = EQUAL_SPACING } !+ 082a0008 VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } !+ fcfc0081 VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } + fcfcfcfc VFD_CONTROL_2: 0xfcfcfcfc !+ 0000fc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } + 0000fcfc VFD_CONTROL_4: 0xfcfc + 00000000 VFD_INDEX_OFFSET: 0 + 00000000 UNKNOWN_2209: 0 + 0008080f VFD_FETCH[0].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 | SWITCHNEXT } !+ 0009bac0 VFD_FETCH[0].INSTR_1: 0x9bac0 + 00000060 VFD_FETCH[0].INSTR_2: { SIZE = 0x60 } + 00000001 VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } + 0000080f VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 } !+ 0009baf0 VFD_FETCH[0x1].INSTR_1: 0x9baf0 + 00000030 VFD_FETCH[0x1].INSTR_2: { SIZE = 0x30 } + 00000001 VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } + 7000411f VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID | SWITCHNEXT } + 3000011f VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID } + 00060010 SP_SP_CTRL_REG: { 0x60010 } + 000005c3 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } !+ 00200800 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 2 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } !+ 08000002 SP_VS_CTRL_REG1: { CONSTLENGTH = 2 | INITIALOUTSTANDING = 8 } !+ 0010fc04 SP_VS_PARAM_REG: { POSREGID = r1.x | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } !+ 00001e00 SP_VS_OUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00fcfc00 UNKNOWN_22D7: 0xfcfc00 + 00000008 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } !+ 00049000 SP_VS_OBJ_START: 0x49000 00049000: 0000: 00000000 13000000 00000000 00000000 00000000 00000000 00000000 00000000 * :0:0000:0000[13000000x_00000000x] (sy)end :0:0001:0001[00000000x_00000000x] nop :0:0002:0002[00000000x_00000000x] nop :0:0003:0003[00000000x_00000000x] nop :0:0004:0004[00000000x_00000000x] nop Stats: - shaderdb: 5 instr, 4 nops, 1 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 0 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 0 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) !+ 00000001 SP_VS_LENGTH_REG: 1 !+ 00340412 SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE } !+ 80100002 SP_FS_CTRL_REG1: { CONSTLENGTH = 2 | VARYING | 0x80000000 } !+ 7e020000 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } !+ 00046000 SP_FS_OBJ_START: 0x46000 00046000: 0000: 00002000 5730cb00 00000000 03000000 00000000 00000000 00000000 00000000 * :2:0000:0000[5730cb00x_00002000x] (sy)(rpt3)bary.f (ei)hr0.x, (r)0, r0.x :0:0001:0004[03000000x_00000000x] end :0:0002:0005[00000000x_00000000x] nop :0:0003:0006[00000000x_00000000x] nop :0:0004:0007[00000000x_00000000x] nop :0:0005:0008[00000000x_00000000x] nop Stats: - shaderdb: 9 instr, 4 nops, 5 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 1 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 4 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) + 00000001 SP_FS_LENGTH_REG: 1 !+ fc00fc01 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r63.x } !+ 0001a100 SP_FS_MRT[0].REG: { REGID = r0.x | HALF_PRECISION | MRTFORMAT = RB4_R8G8B8A8_UNORM } + 00000000 0x230c: 00000000 + 7e020000 SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } + 00000000 SP_HS_OBJ_START: 0 + 00000000 0x2318: 00000000 + 00000000 0x2319: 00000000 + 7e020000 SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } + 00000000 SP_DS_OBJ_START: 0 + 00000000 0x2340: 00000000 + 7e020000 SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } + 00000000 SP_GS_OBJ_START: 0 + 00000808 TPL1_TP_TEX_OFFSET: 0x808 + 00000000 TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } !+ 00000002 0x2382: 00000002 !+ 00000000 TPL1_TP_FS_TEX_COUNT: 0 !+ 080604f0 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0x600a0 } !+ fcfc1108 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x1008 } !+ fff3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } + fcfcfc00 HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } !+ 00fcfc00 HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r0.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } !+ 01010002 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 2 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 1 } !+ 017f0202 HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 2 | CONSTOBJECTOFFSET = 2 | ENABLED | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 } !+ 007e0200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } !+ 007e0200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } !+ 007e0200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } !+ 00000003 HLSQ_UPDATE_CONTROL: 0x3 000555ac: 0000: c0023800 00200984 00000001 00000003 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 18 | GROUP_ID = 1 } { ADDR_LO = 0x9be00 } 000555bc: 0000: c0014300 01000012 0009be00 group_id: 1 count: 18 addr: 000000000009be00 flags: 0 0009be00: 0000: 00002200 082a0008 00002201 fcfc0081 00002203 0000fc00 0007220a 0008080f 0009be20: 0020: 0009bda0 00000060 00000001 0000080f 0009bdd0 00000030 00000001 0001228a 0009be40: 0040: 7000411f 3000011f t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } 0009be00: 0000: 00002200 082a0008 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } 0009be08: 0000: 00002201 fcfc0081 t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } 0009be10: 0000: 00002203 0000fc00 t0 write VFD_FETCH[0].INSTR_0 (220a) VFD_FETCH[0].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 | SWITCHNEXT } VFD_FETCH[0].INSTR_1: 0x9bda0 VFD_FETCH[0].INSTR_2: { SIZE = 0x60 } VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 } VFD_FETCH[0x1].INSTR_1: 0x9bdd0 VFD_FETCH[0x1].INSTR_2: { SIZE = 0x30 } VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } 0009be18: 0000: 0007220a 0008080f 0009bda0 00000060 00000001 0000080f 0009bdd0 00000030 0009be38: 0020: 00000001 t0 write VFD_DECODE[0].INSTR (228a) VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID | SWITCHNEXT } VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID } 0009be3c: 0000: 0001228a 7000411f 3000011f t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = USE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x200000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 3 } draw[62] register values + 082a0008 VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } + fcfc0081 VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } + 0000fc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } + 0008080f VFD_FETCH[0].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 | SWITCHNEXT } !+ 0009bda0 VFD_FETCH[0].INSTR_1: 0x9bda0 + 00000060 VFD_FETCH[0].INSTR_2: { SIZE = 0x60 } + 00000001 VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } + 0000080f VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 } !+ 0009bdd0 VFD_FETCH[0x1].INSTR_1: 0x9bdd0 + 00000030 VFD_FETCH[0x1].INSTR_2: { SIZE = 0x30 } + 00000001 VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } + 7000411f VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID | SWITCHNEXT } + 3000011f VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID } 000555c8: 0000: c0023800 00200984 00000001 00000003 0016b094: 0000: c0013f00 00055328 000000ac t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 0016b0a0: 0000: c0014300 00040000 00000000 t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:001f9e58 ibsize:000000f7 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 001f9e58: 0000: c0002600 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x4 001f9e60: 0000: 00000ec3 00000004 t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x68 001f9e68: 0000: 00000f03 00000068 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 001f9e70: 0000: c0002600 00000000 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } 001f9e78: 0000: 000023c0 080004f0 t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = 0x1d } event (null) 001f9e80: 0000: c0004600 0000001d t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = FACENESS_FLUSH } event FACENESS_FLUSH 001f9e88: 0000: c0004600 0000001c t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 001f9e90: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0 001f9e98: 0000: 00000cc6 00000000 t0 write UNKNOWN_0E42 (0e42) UNKNOWN_0E42: 0 001f9ea0: 0000: 00000e42 00000000 t0 write HLSQ_MODE_CONTROL (0e05) HLSQ_MODE_CONTROL: 0x2 001f9ea8: 0000: 00000e05 00000002 t0 write UNKNOWN_0CC5 (0cc5) UNKNOWN_0CC5: 0x4 001f9eb0: 0000: 00000cc5 00000004 t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x7 001f9eb8: 0000: 000023db 00000007 t0 write VFD_CONTROL_2 (2202) VFD_CONTROL_2: 0xfcfcfcfc 001f9ec0: 0000: 00002202 fcfcfcfc t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } 001f9ec8: 0000: 00002203 fcfcfc00 t0 write VFD_CONTROL_4 (2204) VFD_CONTROL_4: 0xfcfc 001f9ed0: 0000: 00002204 0000fcfc t0 write VFD_INDEX_OFFSET (2208) VFD_INDEX_OFFSET: 0 001f9ed8: 0000: 00002208 00000000 t0 write UNKNOWN_2209 (2209) UNKNOWN_2209: 0 001f9ee0: 0000: 00002209 00000000 t0 write UNKNOWN_2152 (2152) UNKNOWN_2152: 0 UNKNOWN_2153: 0 001f9ee8: 0000: 00012152 00000000 00000000 t0 write UNKNOWN_2156 (2156) UNKNOWN_2156: 0 001f9ef4: 0000: 00002156 00000000 t0 write UNKNOWN_2154 (2154) UNKNOWN_2154: 0 001f9efc: 0000: 00002154 00000000 t0 write UNKNOWN_2155 (2155) UNKNOWN_2155: 0 001f9f04: 0000: 00002155 00000000 t0 write UNKNOWN_21C3 (21c3) UNKNOWN_21C3: 0x1d 001f9f0c: 0000: 000021c3 0000001d t0 write PC_PRIM_VTX_CNTL2 (21c5) PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 001f9f14: 0000: 000021c5 00000012 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 001f9f1c: 0000: 000021e5 00000000 t0 write GRAS_SU_MODE_CONTROL (2078) GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } 001f9f24: 0000: 00002078 00000000 t0 write UNKNOWN_2001 (2001) UNKNOWN_2001: 0 001f9f2c: 0000: 00002001 00000000 t0 write GRAS_CNTL (2003) GRAS_CNTL: { IJ_PERSP } 001f9f34: 0000: 00002003 00000001 t0 write GRAS_CL_CLIP_CNTL (2000) GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } 001f9f3c: 0000: 00002000 00188000 t0 write TPL1_TP_TEX_COUNT (2381) TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } 001f9f44: 0000: 00002381 00000000 t0 write TPL1_TP_FS_TEX_COUNT (23a0) TPL1_TP_FS_TEX_COUNT: 0x3 001f9f4c: 0000: 000023a0 00000003 t0 write RB_ALPHA_CONTROL (20f8) RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } 001f9f54: 0000: 000020f8 00000e00 t0 write RB_RENDER_COMPONENTS (20fb) RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } 001f9f5c: 0000: 000020fb 0000000f t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 001f9f64: 0000: c0014300 00040000 00000000 t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } 001f9f70: 0000: 00002200 000a0000 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } 001f9f78: 0000: 00002201 fc030000 t0 write SP_INSTR_CACHE_CTRL (22c1) SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } 001f9f80: 0000: 000022c1 000005c3 t0 write HLSQ_CONTROL_1_REG (23c1) HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } 001f9f88: 0000: 000023c1 fcfc0120 t0 write HLSQ_CONTROL_2_REG (23c2) HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 001f9f90: 0000: 000023c2 27f3f3f0 t0 write HLSQ_VS_CONTROL_REG (23c5) HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } 001f9f98: 0000: 000023c5 02010042 t0 write HLSQ_FS_CONTROL_REG (23c6) HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 001f9fa0: 0000: 000023c6 0041423e t0 write HLSQ_HS_CONTROL_REG (23c7) HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 001f9fa8: 0000: 000023c7 00404200 t0 write HLSQ_DS_CONTROL_REG (23c8) HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 001f9fb0: 0000: 000023c8 00404200 t0 write HLSQ_GS_CONTROL_REG (23c9) HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 001f9fb8: 0000: 000023c9 00404200 t0 write HLSQ_CS_CONTROL_REG (23ca) HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } 001f9fc0: 0000: 000023ca 00004200 t0 write SP_SP_CTRL_REG (22c0) SP_SP_CTRL_REG: { 0x60010 } 001f9fc8: 0000: 000022c0 00060010 t0 write UNKNOWN_21E6 (21e6) UNKNOWN_21E6: 0x1 001f9fd0: 0000: 000021e6 00000001 t0 write SP_VS_CTRL_REG0 (22c4) SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 001f9fd8: 0000: 000022c4 00200c10 t0 write SP_VS_CTRL_REG1 (22c5) SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } 001f9fe0: 0000: 000022c5 01000042 t0 write VPC_ATTR (2140) VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | 0x40000000 } 001f9fe8: 0000: 00002140 40001004 t0 write VPC_PACK (2141) VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } 001f9ff0: 0000: 00002141 00040400 t0 write PC_PRIM_VTX_CNTL (21c4) PC_PRIM_VTX_CNTL: { VAROUT = 1 } 001f9ff8: 0000: 000021c4 00000001 t0 write SP_VS_PARAM_REG (22c6) SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } UNKNOWN_22D7: 0xfcfc00 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 001fa000: 0000: 001922c6 0010fc03 00001e03 00000000 00000000 00000000 00000000 00000000 * 001fa040: 0040: 00000000 00000000 00fcfc00 00000008 00000000 00000000 00000000 00000000 * t0 write SP_VS_OBJ_OFFSET_REG (22e0) SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 001fa06c: 0000: 000022e0 00000000 t0 write SP_VS_OBJ_START (22e1) SP_VS_OBJ_START: 0x1 001fa074: 0000: 000022e1 00000001 t0 write SP_VS_LENGTH_REG (22e5) SP_VS_LENGTH_REG: 2 001fa07c: 0000: 000022e5 00000002 t3 opcode: CP_LOAD_STATE4 (30) (67 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } :2:0000:0000[56d81803x_20020003x] (sy)(ss)(nop3) shl.b r0.w, r0.w, 2 :1:0001:0004[20150000x_00000003x] cov.s32s16 hr0.x, r0.w :0:0002:0005[00000200x_00000000x] (rpt2)nop :1:0003:0008[201100f4x_00000000x] mova a0.x, hr0.x :0:0004:0009[00000500x_00000000x] (rpt5)nop :1:0005:0015[20154003x_00000c20x] mov.s32s32 r0.w, c :1:0006:0016[20154004x_00000c21x] mov.s32s32 r1.x, c :1:0007:0017[20154005x_00000c22x] mov.s32s32 r1.y, c :1:0008:0018[20156006x_00000c23x] (ul)mov.s32s32 r1.z, c :0:0009:0019[03000000x_00000000x] end :2:0010:0020[46f00007x_20050000x] shr.b r1.w, r0.x, 5 :2:0011:0021[43980008x_201f0000x] (nop2) and.b r2.x, r0.x, 31 :2:0012:0024[43980807x_201f0007x] (nop3) and.b r1.w, r1.w, 31 :2:0013:0028[46100807x_20100007x] (nop1) mul.u24 r1.w, r1.w, 16 :3:0014:0030[62040007x_00071014x] mad.u24 r1.w, c5.x, r2.x, r1.w :0:0015:0031[00000500x_00000000x] (rpt5)nop :6:0016:0037[c2c60f00x_04800006x] stlw.u32 l[r1.w], r0.w, 4 :0:0017:0038[04800000x_00000000x] chmask :0:0018:0039[05000000x_00000000x] chsh Stats: - shaderdb: 40 instr, 24 nops, 16 non-nops, 5 mov, 1 cov - shaderdb: 0 last-baryf, 0 half, 2 full, 5 constlen - shaderdb: 27 cat0, 6 cat1, 5 cat2, 1 cat3, 0 cat4, 0 cat5, 1 cat6, 0 cat7 - shaderdb: 0 sstall, 1 (ss), 1 (sy) 001fa084: 0000: c0413000 00a00000 00000000 20020003 56d81803 00000003 20150000 00000000 001fa0a4: 0020: 00000200 00000000 201100f4 00000000 00000500 00000c20 20154003 00000c21 001fa0c4: 0040: 20154004 00000c22 20154005 00000c23 20156006 00000000 03000000 20050000 001fa0e4: 0060: 46f00007 201f0000 43980008 201f0007 43980807 20100007 46100807 00071014 001fa104: 0080: 62040007 00000000 00000500 04800006 c2c60f00 00000000 04800000 00000000 001fa124: 00a0: 05000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 * t0 write GRAS_SC_CONTROL (207b) GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = 0 | MSAA_DISABLE | RASTER_MODE = 0 } 001fa190: 0000: 0000207b 00000808 t0 write RB_MSAA_CONTROL (20a2) RB_MSAA_CONTROL: { DISABLE | SAMPLES = 0 } 001fa198: 0000: 000020a2 00001000 t0 write RB_RENDER_CONTROL (20a1) RB_RENDER_CONTROL: { DISABLE_COLOR_PIPE | 0x2 } 001fa1a0: 0000: 000020a1 00000022 t0 write RB_DEPTH_CONTROL (2101) RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } 001fa1a8: 0000: 00002101 00000000 t0 write GRAS_ALPHA_CONTROL (2073) GRAS_ALPHA_CONTROL: { 0x2 } 001fa1b0: 0000: 00002073 00000002 t0 write RB_STENCIL_CONTROL (2106) RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } 001fa1b8: 0000: 00002106 00000000 t0 write RB_COPY_CONTROL (20fc) RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_FOUR | MODE = RB_COPY_DEPTH_STENCIL | FASTCLEAR = 0 | GMEM_BASE = 0 } RB_COPY_DEST_BASE: { BASE = 0x4f000 } RB_COPY_DEST_PITCH: { PITCH = 256 } RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_DISABLE | COMPONENT_ENABLE = 0xf | ENDIAN = ENDIAN_NONE | TILE = TILE4_3 } 001fa1c0: 0000: 000320fc 00000052 0004f000 00000008 0303c068 t0 write UNKNOWN_20EF (20ef) UNKNOWN_20EF: 0 001fa1d4: 0000: 000020ef 00000000 t0 write GRAS_SC_SCREEN_SCISSOR_TL (207c) GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } 001fa1dc: 0000: 0001207c 00000000 003f003f t0 write RB_FRAME_BUFFER_DIMENSION (0ce0) RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } 001fa1e8: 0000: 00000ce0 00400040 t0 write 0xce1 (0ce1) 0xce1: 00000000 001fa1f0: 0000: 00000ce1 00000000 t3 opcode: CP_LOAD_STATE4 (30) (11 dwords) { DST_OFF = 8 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } 001fa204: 0.000000 0.000000 1.000000 1.000000 64.000000 64.000000 1.000000 1.000000 001fa204: 0000: 00000000 00000000 3f800000 3f800000 42800000 42800000 3f800000 3f800000 001fa1f8: 0000: c0093000 00a00008 00000001 00000000 00000000 3f800000 3f800000 42800000 001fa218: 0020: 42800000 3f800000 3f800000 t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x80000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 2 } draw[63] register values + 00000004 UNKNOWN_0CC5: 0x4 + 00000000 UNKNOWN_0CC6: 0 + 00400040 RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } + 00000000 0xce1: 00000000 !+ 00000002 HLSQ_MODE_CONTROL: 0x2 + 00000000 UNKNOWN_0E42: 0 !+ 00000004 SP_MODE_CONTROL: 0x4 !+ 00000068 TPL1_TP_MODE_CONTROL: 0x68 !+ 00188000 GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } + 00000000 UNKNOWN_2001: 0 + 00000001 GRAS_CNTL: { IJ_PERSP } !+ 00000002 GRAS_ALPHA_CONTROL: { 0x2 } !+ 00000000 GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } !+ 00000808 GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = 0 | MSAA_DISABLE | RASTER_MODE = 0 } !+ 00000000 GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } !+ 003f003f GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } !+ 00000022 RB_RENDER_CONTROL: { DISABLE_COLOR_PIPE | 0x2 } !+ 00001000 RB_MSAA_CONTROL: { DISABLE | SAMPLES = 0 } + 00000000 UNKNOWN_20EF: 0 + 00000e00 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } + 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } !+ 00000052 RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_FOUR | MODE = RB_COPY_DEPTH_STENCIL | FASTCLEAR = 0 | GMEM_BASE = 0 } + 0004f000 RB_COPY_DEST_BASE: { BASE = 0x4f000 } + 00000008 RB_COPY_DEST_PITCH: { PITCH = 256 } !+ 0303c068 RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_DISABLE | COMPONENT_ENABLE = 0xf | ENDIAN = ENDIAN_NONE | TILE = TILE4_3 } + 00000000 RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } + 00000000 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } !+ 40001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | 0x40000000 } + 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } + 00000000 UNKNOWN_2152: 0 + 00000000 UNKNOWN_2153: 0 + 00000000 UNKNOWN_2154: 0 + 00000000 UNKNOWN_2155: 0 + 00000000 UNKNOWN_2156: 0 !+ 0000001d UNKNOWN_21C3: 0x1d !+ 00000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 } + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + 00000000 PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } + 00000001 UNKNOWN_21E6: 0x1 !+ 000a0000 VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } !+ fc030000 VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } + fcfcfcfc VFD_CONTROL_2: 0xfcfcfcfc !+ fcfcfc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } + 0000fcfc VFD_CONTROL_4: 0xfcfc + 00000000 VFD_INDEX_OFFSET: 0 + 00000000 UNKNOWN_2209: 0 + 00060010 SP_SP_CTRL_REG: { 0x60010 } + 000005c3 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } !+ 00200c10 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } !+ 01000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } !+ 0010fc03 SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } !+ 00001e03 SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00fcfc00 UNKNOWN_22D7: 0xfcfc00 + 00000008 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } !+ 00000001 SP_VS_OBJ_START: 0x1 !+ 00000002 SP_VS_LENGTH_REG: 2 + 00000000 TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } !+ 00000003 TPL1_TP_FS_TEX_COUNT: 0x3 !+ 080004f0 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } !+ fcfc0120 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } !+ 27f3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } !+ 02010042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } !+ 0041423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } !+ 00404200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } !+ 00404200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } !+ 00404200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00004200 HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } !+ 00000007 HLSQ_UPDATE_CONTROL: 0x7 001fa224: 0000: c0023800 00080888 00000001 00000002 0016b0ac: 0000: c0013f00 001f9e58 000000f7 t3 opcode: (null) (1d) (2 dwords) 0016b0b8: 0000: c0001d00 00000000 ############################################################ vertices: 0 ############################################################ cmdstream: 8 dwords t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:000555d8 ibsize:00000155 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 000555d8: 0000: c0002600 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x4 000555e0: 0000: 00000ec3 00000004 t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x68 000555e8: 0000: 00000f03 00000068 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 000555f0: 0000: c0002600 00000000 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } 000555f8: 0000: 000023c0 080004f0 t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = 0x1d } event (null) 00055600: 0000: c0004600 0000001d t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = FACENESS_FLUSH } event FACENESS_FLUSH 00055608: 0000: c0004600 0000001c t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00055610: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0 00055618: 0000: 00000cc6 00000000 t0 write UNKNOWN_0E42 (0e42) UNKNOWN_0E42: 0 00055620: 0000: 00000e42 00000000 t0 write HLSQ_MODE_CONTROL (0e05) HLSQ_MODE_CONTROL: 0x2 00055628: 0000: 00000e05 00000002 t0 write UNKNOWN_0CC5 (0cc5) UNKNOWN_0CC5: 0x4 00055630: 0000: 00000cc5 00000004 t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x7 00055638: 0000: 000023db 00000007 t0 write VFD_CONTROL_2 (2202) VFD_CONTROL_2: 0xfcfcfcfc 00055640: 0000: 00002202 fcfcfcfc t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } 00055648: 0000: 00002203 fcfcfc00 t0 write VFD_CONTROL_4 (2204) VFD_CONTROL_4: 0xfcfc 00055650: 0000: 00002204 0000fcfc t0 write VFD_INDEX_OFFSET (2208) VFD_INDEX_OFFSET: 0 00055658: 0000: 00002208 00000000 t0 write UNKNOWN_2209 (2209) UNKNOWN_2209: 0 00055660: 0000: 00002209 00000000 t0 write UNKNOWN_2152 (2152) UNKNOWN_2152: 0 UNKNOWN_2153: 0 00055668: 0000: 00012152 00000000 00000000 t0 write UNKNOWN_2156 (2156) UNKNOWN_2156: 0 00055674: 0000: 00002156 00000000 t0 write UNKNOWN_2154 (2154) UNKNOWN_2154: 0 0005567c: 0000: 00002154 00000000 t0 write UNKNOWN_2155 (2155) UNKNOWN_2155: 0 00055684: 0000: 00002155 00000000 t0 write UNKNOWN_21C3 (21c3) UNKNOWN_21C3: 0x1d 0005568c: 0000: 000021c3 0000001d t0 write PC_PRIM_VTX_CNTL2 (21c5) PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 00055694: 0000: 000021c5 00000012 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 0005569c: 0000: 000021e5 00000000 t0 write GRAS_SU_MODE_CONTROL (2078) GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } 000556a4: 0000: 00002078 00000000 t0 write UNKNOWN_2001 (2001) UNKNOWN_2001: 0 000556ac: 0000: 00002001 00000000 t0 write GRAS_CNTL (2003) GRAS_CNTL: { IJ_PERSP } 000556b4: 0000: 00002003 00000001 t0 write GRAS_CL_CLIP_CNTL (2000) GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } 000556bc: 0000: 00002000 00188000 t0 write TPL1_TP_TEX_COUNT (2381) TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } 000556c4: 0000: 00002381 00000000 t0 write TPL1_TP_FS_TEX_COUNT (23a0) TPL1_TP_FS_TEX_COUNT: 0x3 000556cc: 0000: 000023a0 00000003 t0 write RB_ALPHA_CONTROL (20f8) RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } 000556d4: 0000: 000020f8 00000e00 t0 write RB_RENDER_COMPONENTS (20fb) RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } 000556dc: 0000: 000020fb 0000000f t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 000556e4: 0000: c0014300 00040000 00000000 t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } 000556f0: 0000: 00002200 000a0000 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } 000556f8: 0000: 00002201 fc030000 t0 write SP_INSTR_CACHE_CTRL (22c1) SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } 00055700: 0000: 000022c1 000005c3 t0 write HLSQ_CONTROL_1_REG (23c1) HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } 00055708: 0000: 000023c1 fcfc0120 t0 write HLSQ_CONTROL_2_REG (23c2) HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 00055710: 0000: 000023c2 27f3f3f0 t0 write HLSQ_VS_CONTROL_REG (23c5) HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } 00055718: 0000: 000023c5 02010042 t0 write HLSQ_FS_CONTROL_REG (23c6) HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 1 } 00055720: 0000: 000023c6 0141423e t0 write HLSQ_HS_CONTROL_REG (23c7) HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00055728: 0000: 000023c7 00404200 t0 write HLSQ_DS_CONTROL_REG (23c8) HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00055730: 0000: 000023c8 00404200 t0 write HLSQ_GS_CONTROL_REG (23c9) HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00055738: 0000: 000023c9 00404200 t0 write HLSQ_CS_CONTROL_REG (23ca) HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } 00055740: 0000: 000023ca 00004200 t0 write SP_SP_CTRL_REG (22c0) SP_SP_CTRL_REG: { 0x60010 } 00055748: 0000: 000022c0 00060010 t0 write UNKNOWN_21E6 (21e6) UNKNOWN_21E6: 0x1 00055750: 0000: 000021e6 00000001 t0 write SP_VS_CTRL_REG0 (22c4) SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 00055758: 0000: 000022c4 00200c10 t0 write SP_VS_CTRL_REG1 (22c5) SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } 00055760: 0000: 000022c5 01000042 t0 write VPC_ATTR (2140) VPC_ATTR: { TOTALATTR = 8 | THRDASSIGN = 1 | ENABLE | 0x40000000 } 00055768: 0000: 00002140 42001008 t0 write VPC_PACK (2141) VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 8 | NUMNONPOSVSVAR = 6 } 00055770: 0000: 00002141 00060800 t0 write PC_PRIM_VTX_CNTL (21c4) PC_PRIM_VTX_CNTL: { VAROUT = 1 } 00055778: 0000: 000021c4 00000001 t0 write SP_VS_PARAM_REG (22c6) SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 2 } SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r1.w | B_COMPMASK = 0x3 } SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } UNKNOWN_22D7: 0xfcfc00 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 12 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 00055780: 0000: 001922c6 0020fc03 06071e03 00000000 00000000 00000000 00000000 00000000 * 000557c0: 0040: 00000000 00000000 00fcfc00 00000c08 00000000 00000000 00000000 00000000 * t0 write SP_VS_OBJ_OFFSET_REG (22e0) SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 000557ec: 0000: 000022e0 00000000 t0 write SP_VS_OBJ_START (22e1) SP_VS_OBJ_START: 0x1 000557f4: 0000: 000022e1 00000001 t0 write SP_VS_LENGTH_REG (22e5) SP_VS_LENGTH_REG: 2 000557fc: 0000: 000022e5 00000002 t3 opcode: CP_LOAD_STATE4 (30) (67 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } :2:0000:0000[56d81803x_20020003x] (sy)(ss)(nop3) shl.b r0.w, r0.w, 2 :1:0001:0004[20150000x_00000003x] cov.s32s16 hr0.x, r0.w :0:0002:0005[00000200x_00000000x] (rpt2)nop :1:0003:0008[201100f4x_00000000x] mova a0.x, hr0.x :0:0004:0009[00000500x_00000000x] (rpt5)nop :1:0005:0015[20154003x_00000c20x] mov.s32s32 r0.w, c :1:0006:0016[20154004x_00000c21x] mov.s32s32 r1.x, c :1:0007:0017[20154007x_00000c22x] mov.s32s32 r1.w, c :1:0008:0018[20156008x_00000c23x] (ul)mov.s32s32 r2.x, c :1:0009:0019[20554005x_00000000x] mov.s32s32 r1.y, 0 :1:0010:0020[20554006x_3f800000x] mov.s32s32 r1.z, 1065353216 :0:0011:0021[03000000x_00000000x] end :2:0012:0022[46f00009x_20050000x] shr.b r2.y, r0.x, 5 :2:0013:0023[4398000ax_201f0000x] (nop2) and.b r2.z, r0.x, 31 :2:0014:0026[43980809x_201f0009x] (nop3) and.b r2.y, r2.y, 31 :2:0015:0030[46100809x_20180009x] (nop1) mul.u24 r2.y, r2.y, 24 :3:0016:0032[62050009x_00091014x] mad.u24 r2.y, c5.x, r2.z, r2.y :0:0017:0033[00000500x_00000000x] (rpt5)nop :6:0018:0039[c2c61300x_04800006x] stlw.u32 l[r2.y], r0.w, 4 :6:0019:0040[c2c61310x_0280000ex] stlw.u32 l[r2.y+16], r1.w, 2 :0:0020:0041[04800000x_00000000x] chmask :0:0021:0042[05000000x_00000000x] chsh Stats: - shaderdb: 43 instr, 24 nops, 19 non-nops, 7 mov, 1 cov - shaderdb: 0 last-baryf, 0 half, 3 full, 5 constlen - shaderdb: 27 cat0, 8 cat1, 5 cat2, 1 cat3, 0 cat4, 0 cat5, 2 cat6, 0 cat7 - shaderdb: 0 sstall, 1 (ss), 1 (sy) 00055804: 0000: c0413000 00a00000 00000000 20020003 56d81803 00000003 20150000 00000000 00055824: 0020: 00000200 00000000 201100f4 00000000 00000500 00000c20 20154003 00000c21 00055844: 0040: 20154004 00000c22 20154007 00000c23 20156008 00000000 20554005 3f800000 00055864: 0060: 20554006 00000000 03000000 20050000 46f00009 201f0000 4398000a 201f0009 00055884: 0080: 43980809 20180009 46100809 00091014 62050009 00000000 00000500 04800006 000558a4: 00a0: c2c61300 0280000e c2c61310 00000000 04800000 00000000 05000000 00000000 * t0 write HLSQ_CONTROL_3_REG (23c3) HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } 00055910: 0000: 000023c3 fcfcfc00 t0 write HLSQ_CONTROL_4_REG (23c4) HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } 00055918: 0000: 000023c4 00fcfcfc t0 write SP_FS_CTRL_REG0 (22e8) SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 0 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE | PIXLODENABLE } SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 } 00055920: 0000: 000122e8 00700402 8010003e t0 write SP_FS_OBJ_OFFSET_REG (22ea) SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 } 0005592c: 0000: 000022ea 40420000 t0 write SP_FS_OBJ_START (22eb) SP_FS_OBJ_START: 0x1 00055934: 0000: 000022eb 00000001 t0 write SP_FS_LENGTH_REG (22ef) SP_FS_LENGTH_REG: 1 0005593c: 0000: 000022ef 00000001 t0 write SP_FS_OUTPUT_REG (22f0) SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r0.x | SAMPLEMASK_REGID = r0.x } 00055944: 0000: 000022f0 00000001 t0 write VPC_VARYING_INTERP[0].MODE (2142) VPC_VARYING_INTERP[0].MODE: 0xe000 0005594c: 0000: 00002142 0000e000 t0 write RB_FS_OUTPUT_REG (2100) RB_FS_OUTPUT_REG: { MRT = 1 } 00055954: 0000: 00002100 00000001 t3 opcode: CP_LOAD_STATE4 (30) (35 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 1 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } :2:0000:0000[57309902x_00002004x] (sy)(ss)(rpt1)bary.f (ei)r0.z, (r)4, r0.x :0:0001:0002[00000500x_00000000x] (rpt5)nop :5:0002:0008[a0c01f00x_00000005x] sam (f32)(xyzw)r0.x, r0.z, s#0, t#0 :0:0003:0009[03000000x_00000000x] end :0:0004:0010[00000000x_00000000x] nop :0:0005:0011[00000000x_00000000x] nop :0:0006:0012[00000000x_00000000x] nop :0:0007:0013[00000000x_00000000x] nop Stats: - shaderdb: 14 instr, 10 nops, 4 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 0 half, 1 full, 0 constlen - shaderdb: 11 cat0, 0 cat1, 2 cat2, 0 cat3, 0 cat4, 1 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 1 (ss), 1 (sy) 0005595c: 0000: c0213000 00700000 00000000 00002004 57309902 00000000 00000500 00000005 0005597c: 0020: a0c01f00 00000000 03000000 00000000 00000000 00000000 00000000 00000000 * t0 write RB_FS_OUTPUT (20f9) RB_FS_OUTPUT: { ENABLE_BLEND = 0 | SAMPLE_MASK = 0xffff } 000559e8: 0000: 000020f9 ffff0000 t0 write RB_MRT[0].CONTROL (20a4) RB_MRT[0].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0xf } 000559f0: 0000: 000020a4 0f000000 t0 write RB_MRT[0x1].CONTROL (20a9) RB_MRT[0x1].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0xf } 000559f8: 0000: 000020a9 0f000000 t0 write RB_MRT[0].BLEND_CONTROL (20a8) RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } 00055a00: 0000: 000020a8 00000000 t3 opcode: CP_LOAD_STATE4 (30) (5 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_TEX | NUM_UNIT = 1 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } { XY_MAG = A4XX_TEX_NEAREST | XY_MIN = A4XX_TEX_NEAREST | WRAP_S = A4XX_TEX_CLAMP_TO_EDGE | WRAP_T = A4XX_TEX_CLAMP_TO_EDGE | WRAP_R = A4XX_TEX_CLAMP_TO_EDGE | ANISO = A4XX_TEX_ANISO_1 | LOD_BIAS = 0.000000 | 0x60000 } { COMPARE_FUNC = FUNC_LEQUAL | UNNORM_COORDS | MIPFILTER_LINEAR_FAR | MAX_LOD = 0.000000 | MIN_LOD = 0.000000 | 0x1 } 00055a14: 0000: 00060920 00000067 00055a08: 0000: c0033000 00500000 00000000 00060920 00000067 t0 write GRAS_SC_CONTROL (207b) GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 0 | RASTER_MODE = 0 } 00055a1c: 0000: 0000207b 00000000 t0 write RB_MSAA_CONTROL (20a2) RB_MSAA_CONTROL: { SAMPLES = 0 } 00055a24: 0000: 000020a2 00000000 t0 write RB_RENDER_CONTROL (20a1) RB_RENDER_CONTROL: { 0 } 00055a2c: 0000: 000020a1 00000000 t0 write 0x2382 (2382) 0x2382: 00000000 00055a34: 0000: 00002382 00000000 t0 write RB_DEPTH_CONTROL (2101) RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } 00055a3c: 0000: 00002101 00000000 t0 write GRAS_ALPHA_CONTROL (2073) GRAS_ALPHA_CONTROL: { 0 } 00055a44: 0000: 00002073 00000000 t0 write RB_STENCIL_CONTROL (2106) RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } 00055a4c: 0000: 00002106 00000000 t0 write SP_FS_MRT[0].REG (22f1) SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = RB4_R8G8B8A8_UNORM } 00055a54: 0000: 000022f1 0001a000 t0 write RB_MRT[0].BUF_INFO (20a5) RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB4_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE4_3 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 256 } RB_MRT[0].BASE: 0x166000 RB_MRT[0].CONTROL3: { STRIDE = 0 } 00055a5c: 0000: 000220a5 000400da 00166000 00000000 t3 opcode: CP_LOAD_STATE4 (30) (11 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_TEX | NUM_UNIT = 1 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } { TILED | SWIZ_X = A4XX_TEX_X | SWIZ_Y = A4XX_TEX_Y | SWIZ_Z = A4XX_TEX_Z | SWIZ_W = A4XX_TEX_W | MIPLVLS = 0 | FMT = TFMT4_8_8_8_8_UNORM | TYPE = A4XX_TEX_2D | 0x2 } { HEIGHT = 64 | WIDTH = 64 } { PITCHALIGN = 0 | PITCH = 256 | SWAP = WZYX } { LAYERSZ = 0 | DEPTH = 1 | 0x20000 } { LAYERSZ = 4096 | BASE = 0x4f000 } { 5 = 0 } { 6 = 0 } { 7 = 0 } 00055a78: 0000: 27006883 00200040 00020000 00060000 0004f001 00000000 00000000 00000000 00055a6c: 0000: c0093000 00500000 00000001 27006883 00200040 00020000 00060000 0004f001 * t0 write VPC_VARYING_PS_REPL[0].MODE (214a) VPC_VARYING_PS_REPL[0].MODE: 0x99999999 00055a98: 0000: 0000214a 99999999 t0 write GRAS_SC_SCREEN_SCISSOR_TL (207c) GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } 00055aa0: 0000: 0001207c 00000000 003f003f t0 write GRAS_SC_WINDOW_SCISSOR_BR (209c) GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 00055aac: 0000: 0001209c 003f003f 00000000 t0 write RB_FRAME_BUFFER_DIMENSION (0ce0) RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } 00055ab8: 0000: 00000ce0 00400040 t0 write 0xce1 (0ce1) 0xce1: 00000000 00055ac0: 0000: 00000ce1 00000000 t0 write RB_RENDER_CONTROL2 (20a3) RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 | IJ_PERSP_PIXEL } 00055ac8: 0000: 000020a3 00001000 t0 write RB_MODE_CONTROL (20a0) RB_MODE_CONTROL: { WIDTH = 0 | HEIGHT = 0 | 0xc00000 } 00055ad0: 0000: 000020a0 00c00000 t3 opcode: CP_LOAD_STATE4 (30) (11 dwords) { DST_OFF = 8 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } 00055ae4: 0.000000 0.000000 0.000000 0.000000 64.000000 64.000000 64.000000 64.000000 00055ae4: 0000: 00000000 00000000 00000000 00000000 42800000 42800000 42800000 42800000 00055ad8: 0000: c0093000 00a00008 00000001 00000000 00000000 00000000 00000000 42800000 00055af8: 0020: 42800000 42800000 42800000 t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x80000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 2 } draw[64] register values + 00000004 UNKNOWN_0CC5: 0x4 + 00000000 UNKNOWN_0CC6: 0 + 00400040 RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } + 00000000 0xce1: 00000000 + 00000002 HLSQ_MODE_CONTROL: 0x2 + 00000000 UNKNOWN_0E42: 0 + 00000004 SP_MODE_CONTROL: 0x4 + 00000068 TPL1_TP_MODE_CONTROL: 0x68 + 00188000 GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } + 00000000 UNKNOWN_2001: 0 + 00000001 GRAS_CNTL: { IJ_PERSP } !+ 00000000 GRAS_ALPHA_CONTROL: { 0 } + 00000000 GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } !+ 00000000 GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 0 | RASTER_MODE = 0 } + 00000000 GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } + 003f003f GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } + 003f003f GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } + 00000000 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } !+ 00c00000 RB_MODE_CONTROL: { WIDTH = 0 | HEIGHT = 0 | 0xc00000 } !+ 00000000 RB_RENDER_CONTROL: { 0 } !+ 00000000 RB_MSAA_CONTROL: { SAMPLES = 0 } !+ 00001000 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 | IJ_PERSP_PIXEL } !+ 0f000000 RB_MRT[0].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0xf } !+ 000400da RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB4_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE4_3 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 256 } !+ 00166000 RB_MRT[0].BASE: 0x166000 !+ 00000000 RB_MRT[0].CONTROL3: { STRIDE = 0 } + 00000000 RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } + 0f000000 RB_MRT[0x1].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0xf } + 00000e00 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } !+ ffff0000 RB_FS_OUTPUT: { ENABLE_BLEND = 0 | SAMPLE_MASK = 0xffff } + 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } + 00000001 RB_FS_OUTPUT_REG: { MRT = 1 } + 00000000 RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } + 00000000 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } !+ 42001008 VPC_ATTR: { TOTALATTR = 8 | THRDASSIGN = 1 | ENABLE | 0x40000000 } !+ 00060800 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 8 | NUMNONPOSVSVAR = 6 } !+ 0000e000 VPC_VARYING_INTERP[0].MODE: 0xe000 !+ 99999999 VPC_VARYING_PS_REPL[0].MODE: 0x99999999 + 00000000 UNKNOWN_2152: 0 + 00000000 UNKNOWN_2153: 0 + 00000000 UNKNOWN_2154: 0 + 00000000 UNKNOWN_2155: 0 + 00000000 UNKNOWN_2156: 0 + 0000001d UNKNOWN_21C3: 0x1d + 00000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 } + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + 00000000 PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } + 00000001 UNKNOWN_21E6: 0x1 + 000a0000 VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } + fc030000 VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } + fcfcfcfc VFD_CONTROL_2: 0xfcfcfcfc + fcfcfc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } + 0000fcfc VFD_CONTROL_4: 0xfcfc + 00000000 VFD_INDEX_OFFSET: 0 + 00000000 UNKNOWN_2209: 0 + 00060010 SP_SP_CTRL_REG: { 0x60010 } + 000005c3 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } + 00200c10 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } + 01000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } !+ 0020fc03 SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 2 } !+ 06071e03 SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r1.w | B_COMPMASK = 0x3 } + 00000000 SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00fcfc00 UNKNOWN_22D7: 0xfcfc00 !+ 00000c08 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 12 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } + 00000001 SP_VS_OBJ_START: 0x1 + 00000002 SP_VS_LENGTH_REG: 2 !+ 00700402 SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 0 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE | PIXLODENABLE } !+ 8010003e SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 } !+ 40420000 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 } !+ 00000001 SP_FS_OBJ_START: 0x1 + 00000001 SP_FS_LENGTH_REG: 1 !+ 00000001 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r0.x | SAMPLEMASK_REGID = r0.x } !+ 0001a000 SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = RB4_R8G8B8A8_UNORM } + 00000000 TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } !+ 00000000 0x2382: 00000000 + 00000003 TPL1_TP_FS_TEX_COUNT: 0x3 + 080004f0 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } + fcfc0120 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } + 27f3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } + fcfcfc00 HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } !+ 00fcfcfc HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } + 02010042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } !+ 0141423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 1 } + 00404200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00004200 HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } + 00000007 HLSQ_UPDATE_CONTROL: 0x7 00055b04: 0000: c0023800 00080888 00000001 00000002 t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = CACHE_FLUSH } event CACHE_FLUSH 00055b14: 0000: c0004600 00000006 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00055b1c: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0x8000012 00055b24: 0000: 00000cc6 08000012 00173000: 0000: c0013f00 000555d8 00000155 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 0017300c: 0000: c0014300 00040000 00000000 t3 opcode: (null) (1d) (2 dwords) 00173018: 0000: c0001d00 00000000 ############################################################ vertices: 0 ############################################################ cmdstream: 48 dwords t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 0016b000: 0000: c0002600 00000000 t0 write UCHE_INVALIDATE0 (0e8a) UCHE_INVALIDATE0: 0 UCHE_INVALIDATE1: 0x12 0016b008: 0000: 00010e8a 00000000 00000012 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 0016b014: 0000: c0002600 00000000 t0 write RB_MODE_CONTROL (20a0) RB_MODE_CONTROL: { WIDTH = 64 | HEIGHT = 64 | ENABLE_GMEM } 0016b01c: 0000: 000020a0 00010202 t0 write RB_FRAME_BUFFER_DIMENSION (0ce0) RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } 0016b024: 0000: 00000ce0 00400040 t0 write 0xce1 (0ce1) 0xce1: 00000001 0016b02c: 0000: 00000ce1 00000001 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 0016b034: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0 0016b03c: 0000: 00000cc6 00000000 t3 opcode: (null) (1d) (2 dwords) 0016b044: 0000: c0001d00 00000000 t0 write GRAS_SC_WINDOW_SCISSOR_BR (209c) GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 0016b04c: 0000: 0001209c 003f003f 00000000 t0 write RB_BIN_OFFSET (210d) RB_BIN_OFFSET: { X = 0 | Y = 0 } 0016b058: 0000: 0000210d 00000000 t0 write GRAS_SC_WINDOW_SCISSOR_BR (209c) GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 0016b060: 0000: 0001209c 003f003f 00000000 t0 write UNKNOWN_2157 (2157) UNKNOWN_2157: 0x1 0016b06c: 0000: 00002157 00000001 t3 opcode: (null) (64) (2 dwords) 0016b074: 0000: c0006400 00000001 t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:00054994 ibsize:000000f6 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00054994: 0000: c0002600 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x4 0005499c: 0000: 00000ec3 00000004 t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x68 000549a4: 0000: 00000f03 00000068 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 000549ac: 0000: c0002600 00000000 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } 000549b4: 0000: 000023c0 080004f0 t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = 0x1d } event (null) 000549bc: 0000: c0004600 0000001d t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = FACENESS_FLUSH } event FACENESS_FLUSH 000549c4: 0000: c0004600 0000001c t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 000549cc: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0 000549d4: 0000: 00000cc6 00000000 t0 write UNKNOWN_0E42 (0e42) UNKNOWN_0E42: 0 000549dc: 0000: 00000e42 00000000 t0 write HLSQ_MODE_CONTROL (0e05) HLSQ_MODE_CONTROL: 0x2 000549e4: 0000: 00000e05 00000002 t0 write UNKNOWN_0CC5 (0cc5) UNKNOWN_0CC5: 0x4 000549ec: 0000: 00000cc5 00000004 t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x7 000549f4: 0000: 000023db 00000007 t0 write VFD_CONTROL_2 (2202) VFD_CONTROL_2: 0xfcfcfcfc 000549fc: 0000: 00002202 fcfcfcfc t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } 00054a04: 0000: 00002203 fcfcfc00 t0 write VFD_CONTROL_4 (2204) VFD_CONTROL_4: 0xfcfc 00054a0c: 0000: 00002204 0000fcfc t0 write VFD_INDEX_OFFSET (2208) VFD_INDEX_OFFSET: 0 00054a14: 0000: 00002208 00000000 t0 write UNKNOWN_2209 (2209) UNKNOWN_2209: 0 00054a1c: 0000: 00002209 00000000 t0 write UNKNOWN_2152 (2152) UNKNOWN_2152: 0 UNKNOWN_2153: 0 00054a24: 0000: 00012152 00000000 00000000 t0 write UNKNOWN_2156 (2156) UNKNOWN_2156: 0 00054a30: 0000: 00002156 00000000 t0 write UNKNOWN_2154 (2154) UNKNOWN_2154: 0 00054a38: 0000: 00002154 00000000 t0 write UNKNOWN_2155 (2155) UNKNOWN_2155: 0 00054a40: 0000: 00002155 00000000 t0 write UNKNOWN_21C3 (21c3) UNKNOWN_21C3: 0x1d 00054a48: 0000: 000021c3 0000001d t0 write PC_PRIM_VTX_CNTL2 (21c5) PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 00054a50: 0000: 000021c5 00000012 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 00054a58: 0000: 000021e5 00000000 t0 write GRAS_SU_MODE_CONTROL (2078) GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } 00054a60: 0000: 00002078 00000000 t0 write UNKNOWN_2001 (2001) UNKNOWN_2001: 0 00054a68: 0000: 00002001 00000000 t0 write GRAS_CNTL (2003) GRAS_CNTL: { IJ_PERSP } 00054a70: 0000: 00002003 00000001 t0 write GRAS_CL_CLIP_CNTL (2000) GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } 00054a78: 0000: 00002000 00188000 t0 write TPL1_TP_TEX_COUNT (2381) TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } 00054a80: 0000: 00002381 00000000 t0 write TPL1_TP_FS_TEX_COUNT (23a0) TPL1_TP_FS_TEX_COUNT: 0x3 00054a88: 0000: 000023a0 00000003 t0 write RB_ALPHA_CONTROL (20f8) RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } 00054a90: 0000: 000020f8 00000e00 t0 write RB_RENDER_COMPONENTS (20fb) RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } 00054a98: 0000: 000020fb 0000000f t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 00054aa0: 0000: c0014300 00040000 00000000 t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } 00054aac: 0000: 00002200 000a0000 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } 00054ab4: 0000: 00002201 fc030000 t0 write SP_INSTR_CACHE_CTRL (22c1) SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } 00054abc: 0000: 000022c1 000005c3 t0 write HLSQ_CONTROL_1_REG (23c1) HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } 00054ac4: 0000: 000023c1 fcfc0120 t0 write HLSQ_CONTROL_2_REG (23c2) HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 00054acc: 0000: 000023c2 27f3f3f0 t0 write HLSQ_VS_CONTROL_REG (23c5) HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } 00054ad4: 0000: 000023c5 02010042 t0 write HLSQ_FS_CONTROL_REG (23c6) HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00054adc: 0000: 000023c6 0041423e t0 write HLSQ_HS_CONTROL_REG (23c7) HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00054ae4: 0000: 000023c7 00404200 t0 write HLSQ_DS_CONTROL_REG (23c8) HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00054aec: 0000: 000023c8 00404200 t0 write HLSQ_GS_CONTROL_REG (23c9) HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00054af4: 0000: 000023c9 00404200 t0 write HLSQ_CS_CONTROL_REG (23ca) HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } 00054afc: 0000: 000023ca 00004200 t0 write SP_SP_CTRL_REG (22c0) SP_SP_CTRL_REG: { 0x60010 } 00054b04: 0000: 000022c0 00060010 t0 write UNKNOWN_21E6 (21e6) UNKNOWN_21E6: 0x1 00054b0c: 0000: 000021e6 00000001 t0 write SP_VS_CTRL_REG0 (22c4) SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 00054b14: 0000: 000022c4 00200c10 t0 write SP_VS_CTRL_REG1 (22c5) SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } 00054b1c: 0000: 000022c5 01000042 t0 write VPC_ATTR (2140) VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | 0x40000000 } 00054b24: 0000: 00002140 40001004 t0 write VPC_PACK (2141) VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } 00054b2c: 0000: 00002141 00040400 t0 write PC_PRIM_VTX_CNTL (21c4) PC_PRIM_VTX_CNTL: { VAROUT = 1 } 00054b34: 0000: 000021c4 00000001 t0 write SP_VS_PARAM_REG (22c6) SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } UNKNOWN_22D7: 0xfcfc00 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 00054b3c: 0000: 001922c6 0010fc03 00001e03 00000000 00000000 00000000 00000000 00000000 * 00054b7c: 0040: 00000000 00000000 00fcfc00 00000008 00000000 00000000 00000000 00000000 * t0 write SP_VS_OBJ_OFFSET_REG (22e0) SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 00054ba8: 0000: 000022e0 00000000 t0 write SP_VS_OBJ_START (22e1) SP_VS_OBJ_START: 0x1 00054bb0: 0000: 000022e1 00000001 t0 write SP_VS_LENGTH_REG (22e5) SP_VS_LENGTH_REG: 2 00054bb8: 0000: 000022e5 00000002 t3 opcode: CP_LOAD_STATE4 (30) (67 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } :2:0000:0000[56d81803x_20020003x] (sy)(ss)(nop3) shl.b r0.w, r0.w, 2 :1:0001:0004[20150000x_00000003x] cov.s32s16 hr0.x, r0.w :0:0002:0005[00000200x_00000000x] (rpt2)nop :1:0003:0008[201100f4x_00000000x] mova a0.x, hr0.x :0:0004:0009[00000500x_00000000x] (rpt5)nop :1:0005:0015[20154003x_00000c20x] mov.s32s32 r0.w, c :1:0006:0016[20154004x_00000c21x] mov.s32s32 r1.x, c :1:0007:0017[20154005x_00000c22x] mov.s32s32 r1.y, c :1:0008:0018[20156006x_00000c23x] (ul)mov.s32s32 r1.z, c :0:0009:0019[03000000x_00000000x] end :2:0010:0020[46f00007x_20050000x] shr.b r1.w, r0.x, 5 :2:0011:0021[43980008x_201f0000x] (nop2) and.b r2.x, r0.x, 31 :2:0012:0024[43980807x_201f0007x] (nop3) and.b r1.w, r1.w, 31 :2:0013:0028[46100807x_20100007x] (nop1) mul.u24 r1.w, r1.w, 16 :3:0014:0030[62040007x_00071014x] mad.u24 r1.w, c5.x, r2.x, r1.w :0:0015:0031[00000500x_00000000x] (rpt5)nop :6:0016:0037[c2c60f00x_04800006x] stlw.u32 l[r1.w], r0.w, 4 :0:0017:0038[04800000x_00000000x] chmask :0:0018:0039[05000000x_00000000x] chsh Stats: - shaderdb: 40 instr, 24 nops, 16 non-nops, 5 mov, 1 cov - shaderdb: 0 last-baryf, 0 half, 2 full, 5 constlen - shaderdb: 27 cat0, 6 cat1, 5 cat2, 1 cat3, 0 cat4, 0 cat5, 1 cat6, 0 cat7 - shaderdb: 0 sstall, 1 (ss), 1 (sy) 00054bc0: 0000: c0413000 00a00000 00000000 20020003 56d81803 00000003 20150000 00000000 00054be0: 0020: 00000200 00000000 201100f4 00000000 00000500 00000c20 20154003 00000c21 00054c00: 0040: 20154004 00000c22 20154005 00000c23 20156006 00000000 03000000 20050000 00054c20: 0060: 46f00007 201f0000 43980008 201f0007 43980807 20100007 46100807 00071014 00054c40: 0080: 62040007 00000000 00000500 04800006 c2c60f00 00000000 04800000 00000000 00054c60: 00a0: 05000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 * t0 write GRAS_ALPHA_CONTROL (2073) GRAS_ALPHA_CONTROL: { 0x2 } 00054ccc: 0000: 00002073 00000002 t0 write GRAS_SC_CONTROL (207b) GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = 4 | MSAA_DISABLE | RASTER_MODE = 0 } 00054cd4: 0000: 0000207b 00000a08 t0 write RB_MSAA_CONTROL (20a2) RB_MSAA_CONTROL: { DISABLE | SAMPLES = 4 } 00054cdc: 0000: 000020a2 00009000 t0 write RB_RENDER_CONTROL (20a1) RB_RENDER_CONTROL: { DISABLE_COLOR_PIPE | 0x2 } 00054ce4: 0000: 000020a1 00000022 t0 write RB_CLEAR_COLOR_DW0 (20cc) RB_CLEAR_COLOR_DW0: 0xff000000 RB_CLEAR_COLOR_DW1: 0 RB_CLEAR_COLOR_DW2: 0 RB_CLEAR_COLOR_DW3: 0 00054cec: 0000: 000320cc ff000000 00000000 00000000 00000000 t0 write RB_COPY_CONTROL (20fc) RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_FOUR | MODE = RB_COPY_CLEAR | FASTCLEAR = 0xf | GMEM_BASE = 0 } RB_COPY_DEST_BASE: { BASE = 0x4f000 } RB_COPY_DEST_PITCH: { PITCH = 256 } RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_IF_ALPHA_OFF | COMPONENT_ENABLE = 0 | ENDIAN = ENDIAN_NONE | TILE = TILE4_3 } 00054d00: 0000: 000320fc 00000f22 0004f000 00000008 03000868 t0 write GRAS_SC_SCREEN_SCISSOR_TL (207c) GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } 00054d14: 0000: 0001207c 00000000 003f003f t0 write RB_FRAME_BUFFER_DIMENSION (0ce0) RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } 00054d20: 0000: 00000ce0 00400040 t0 write 0xce1 (0ce1) 0xce1: 00000000 00054d28: 0000: 00000ce1 00000000 t3 opcode: CP_LOAD_STATE4 (30) (11 dwords) { DST_OFF = 8 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } 00054d3c: 0.000000 0.000000 1.000000 1.000000 64.000000 64.000000 1.000000 1.000000 00054d3c: 0000: 00000000 00000000 3f800000 3f800000 42800000 42800000 3f800000 3f800000 00054d30: 0000: c0093000 00a00008 00000001 00000000 00000000 3f800000 3f800000 42800000 00054d50: 0020: 42800000 3f800000 3f800000 t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x80000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 2 } draw[65] register values + 00000004 UNKNOWN_0CC5: 0x4 + 00000000 UNKNOWN_0CC6: 0 + 00400040 RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } + 00000000 0xce1: 00000000 + 00000002 HLSQ_MODE_CONTROL: 0x2 + 00000000 UNKNOWN_0E42: 0 + 00000000 UCHE_INVALIDATE0: 0 + 00000012 UCHE_INVALIDATE1: 0x12 + 00000004 SP_MODE_CONTROL: 0x4 + 00000068 TPL1_TP_MODE_CONTROL: 0x68 + 00188000 GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } + 00000000 UNKNOWN_2001: 0 + 00000001 GRAS_CNTL: { IJ_PERSP } !+ 00000002 GRAS_ALPHA_CONTROL: { 0x2 } + 00000000 GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } !+ 00000a08 GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = 4 | MSAA_DISABLE | RASTER_MODE = 0 } + 00000000 GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } + 003f003f GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } + 003f003f GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } + 00000000 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } !+ 00010202 RB_MODE_CONTROL: { WIDTH = 64 | HEIGHT = 64 | ENABLE_GMEM } !+ 00000022 RB_RENDER_CONTROL: { DISABLE_COLOR_PIPE | 0x2 } !+ 00009000 RB_MSAA_CONTROL: { DISABLE | SAMPLES = 4 } + ff000000 RB_CLEAR_COLOR_DW0: 0xff000000 + 00000000 RB_CLEAR_COLOR_DW1: 0 + 00000000 RB_CLEAR_COLOR_DW2: 0 + 00000000 RB_CLEAR_COLOR_DW3: 0 + 00000e00 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } + 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } !+ 00000f22 RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_FOUR | MODE = RB_COPY_CLEAR | FASTCLEAR = 0xf | GMEM_BASE = 0 } + 0004f000 RB_COPY_DEST_BASE: { BASE = 0x4f000 } + 00000008 RB_COPY_DEST_PITCH: { PITCH = 256 } !+ 03000868 RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_IF_ALPHA_OFF | COMPONENT_ENABLE = 0 | ENDIAN = ENDIAN_NONE | TILE = TILE4_3 } + 00000000 RB_BIN_OFFSET: { X = 0 | Y = 0 } !+ 40001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | 0x40000000 } !+ 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } + 00000000 UNKNOWN_2152: 0 + 00000000 UNKNOWN_2153: 0 + 00000000 UNKNOWN_2154: 0 + 00000000 UNKNOWN_2155: 0 + 00000000 UNKNOWN_2156: 0 + 00000001 UNKNOWN_2157: 0x1 + 0000001d UNKNOWN_21C3: 0x1d + 00000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 } + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + 00000000 PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } + 00000001 UNKNOWN_21E6: 0x1 + 000a0000 VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } + fc030000 VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } + fcfcfcfc VFD_CONTROL_2: 0xfcfcfcfc + fcfcfc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } + 0000fcfc VFD_CONTROL_4: 0xfcfc + 00000000 VFD_INDEX_OFFSET: 0 + 00000000 UNKNOWN_2209: 0 + 00060010 SP_SP_CTRL_REG: { 0x60010 } + 000005c3 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } + 00200c10 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } + 01000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } !+ 0010fc03 SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } !+ 00001e03 SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00fcfc00 UNKNOWN_22D7: 0xfcfc00 !+ 00000008 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } + 00000001 SP_VS_OBJ_START: 0x1 + 00000002 SP_VS_LENGTH_REG: 2 + 00000000 TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } + 00000003 TPL1_TP_FS_TEX_COUNT: 0x3 + 080004f0 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } + fcfc0120 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } + 27f3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } + 02010042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } !+ 0041423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00004200 HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } + 00000007 HLSQ_UPDATE_CONTROL: 0x7 00054d5c: 0000: c0023800 00080888 00000001 00000002 0016b07c: 0000: c0013f00 00054994 000000f6 t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:00054d6c ibsize:00000037 t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } 00054d6c: 0000: 00002200 082a0008 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00054d74: 0000: c0002600 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x1e 00054d7c: 0000: 00000ec3 0000001e t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x28 00054d84: 0000: 00000f03 00000028 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00054d8c: 0000: c0002600 00000000 t0 write HLSQ_MODE_CONTROL (0e05) HLSQ_MODE_CONTROL: 0x1 00054d94: 0000: 00000e05 00000001 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0x600a0 } 00054d9c: 0000: 000023c0 080604f0 t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x7 00054da4: 0000: 000023db 00000007 t0 write PC_RESTART_INDEX (21c6) PC_RESTART_INDEX: 0xffffffff 00054dac: 0000: 000021c6 ffffffff t0 write UNKNOWN_21E6 (21e6) UNKNOWN_21E6: 0x1 00054db4: 0000: 000021e6 00000001 t0 write UNKNOWN_21C3 (21c3) UNKNOWN_21C3: 0x1f 00054dbc: 0000: 000021c3 0000001f t0 write TPL1_TP_TEX_OFFSET (2380) TPL1_TP_TEX_OFFSET: 0x808 00054dc4: 0000: 00002380 00000808 t0 write GRAS_SU_POINT_MINMAX (2070) GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 4092.000000 } GRAS_SU_POINT_SIZE: 0.500000 00054dcc: 0000: 00012070 ffc00010 00000008 t0 write UNKNOWN_2152 (2152) UNKNOWN_2152: 0 UNKNOWN_2153: 0 00054dd8: 0000: 00012152 00000000 00000000 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00054de4: 0000: c0002600 00000000 t0 write UNKNOWN_0CC5 (0cc5) UNKNOWN_0CC5: 0x4 00054dec: 0000: 00000cc5 00000004 t0 write 0xcc4 (0cc4) 0xcc4: 00000000 00054df4: 0000: 00000cc4 00000000 t0 write 0xd03 (0d03) 0xd03: 80200000 00054dfc: 0000: 00000d03 80200000 t0 write UNKNOWN_0EC2 (0ec2) UNKNOWN_0EC2: 0x40000 00054e04: 0000: 00000ec2 00040000 t0 write VPC_DEBUG_ECO_CONTROL (0e64) VPC_DEBUG_ECO_CONTROL: 0x100 00054e0c: 0000: 00000e64 00000100 t0 write UNKNOWN_0E42 (0e42) UNKNOWN_0E42: 0 00054e14: 0000: 00000e42 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x1e 00054e1c: 0000: 00000ec3 0000001e t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x28 00054e24: 0000: 00000f03 00000028 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 00054e2c: 0000: c0014300 00040000 00000000 t0 write VFD_INDEX_OFFSET (2208) VFD_INDEX_OFFSET: 0 00054e38: 0000: 00002208 00000000 t0 write UNKNOWN_2209 (2209) UNKNOWN_2209: 0 00054e40: 0000: 00002209 00000000 0016b088: 0000: c0013f00 00054d6c 00000037 t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:00055328 ibsize:000000ac t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x3 00055328: 0000: 000023db 00000003 t0 write SP_INSTR_CACHE_CTRL (22c1) SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } 00055330: 0000: 000022c1 000005c3 t0 write HLSQ_CONTROL_1_REG (23c1) HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x1008 } 00055338: 0000: 000023c1 fcfc1108 t0 write HLSQ_CONTROL_2_REG (23c2) HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 00055340: 0000: 000023c2 fff3f3f0 t0 write HLSQ_VS_CONTROL_REG (23c5) HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 2 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 1 } 00055348: 0000: 000023c5 01010002 t0 write HLSQ_HS_CONTROL_REG (23c7) HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 00055350: 0000: 000023c7 007e0200 t0 write HLSQ_DS_CONTROL_REG (23c8) HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 00055358: 0000: 000023c8 007e0200 t0 write HLSQ_GS_CONTROL_REG (23c9) HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 00055360: 0000: 000023c9 007e0200 t0 write HLSQ_FS_CONTROL_REG (23c6) HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 2 | CONSTOBJECTOFFSET = 2 | ENABLED | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 } 00055368: 0000: 000023c6 017f0202 t0 write SP_VS_OBJ_OFFSET_REG (22e0) SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 00055370: 0000: 000022e0 00000000 t0 write SP_HS_OBJ_OFFSET_REG (230d) SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } 00055378: 0000: 0000230d 7e020000 t0 write SP_DS_OBJ_OFFSET_REG (2334) SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } 00055380: 0000: 00002334 7e020000 t0 write SP_GS_OBJ_OFFSET_REG (235b) SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } 00055388: 0000: 0000235b 7e020000 t0 write SP_FS_OBJ_OFFSET_REG (22ea) SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } 00055390: 0000: 000022ea 7e020000 t0 write SP_VS_OBJ_START (22e1) SP_VS_OBJ_START: 0x49000 00049000: 0000: 00000000 13000000 00000000 00000000 00000000 00000000 00000000 00000000 * :0:0000:0000[13000000x_00000000x] (sy)end :0:0001:0001[00000000x_00000000x] nop :0:0002:0002[00000000x_00000000x] nop :0:0003:0003[00000000x_00000000x] nop :0:0004:0004[00000000x_00000000x] nop Stats: - shaderdb: 5 instr, 4 nops, 1 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 0 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 0 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) 00055398: 0000: 000022e1 00049000 t0 write SP_HS_OBJ_START (230e) SP_HS_OBJ_START: 0 000553a0: 0000: 0000230e 00000000 t0 write SP_DS_OBJ_START (2335) SP_DS_OBJ_START: 0 000553a8: 0000: 00002335 00000000 t0 write SP_GS_OBJ_START (235c) SP_GS_OBJ_START: 0 000553b0: 0000: 0000235c 00000000 t0 write SP_VS_LENGTH_REG (22e5) SP_VS_LENGTH_REG: 1 000553b8: 0000: 000022e5 00000001 t3 opcode: CP_LOAD_STATE4 (30) (3 dwords) { DST_OFF = 0 | STATE_SRC = SS4_INDIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 1 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0x49000 } :0:0000:0000[13000000x_00000000x] (sy)end :0:0001:0001[00000000x_00000000x] nop :0:0002:0002[00000000x_00000000x] nop :0:0003:0003[00000000x_00000000x] nop :0:0004:0004[00000000x_00000000x] nop Stats: - shaderdb: 5 instr, 4 nops, 1 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 0 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 0 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) 000553c0: 0000: c0013000 00620000 00049000 t0 write 0x2072 (2072) 0x2072: 00000000 000553cc: 0000: 00002072 00000000 t0 write UNKNOWN_2155 (2155) UNKNOWN_2155: 0 000553d4: 0000: 00002155 00000000 t0 write GRAS_CNTL (2003) GRAS_CNTL: { IJ_PERSP } 000553dc: 0000: 00002003 00000001 t0 write VPC_VARYING_INTERP[0].MODE (2142) VPC_VARYING_INTERP[0].MODE: 0 000553e4: 0000: 00002142 00000000 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0x600a0 } 000553ec: 0000: 000023c0 080604f0 t0 write HLSQ_CONTROL_3_REG (23c3) HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } 000553f4: 0000: 000023c3 fcfcfc00 t0 write HLSQ_CONTROL_4_REG (23c4) HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r0.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } 000553fc: 0000: 000023c4 00fcfc00 t0 write SP_FS_CTRL_REG0 (22e8) SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE } SP_FS_CTRL_REG1: { CONSTLENGTH = 2 | VARYING | 0x80000000 } 00055404: 0000: 000122e8 00340412 80100002 t0 write SP_FS_OBJ_START (22eb) SP_FS_OBJ_START: 0x46000 00046000: 0000: 00002000 5730cb00 00000000 03000000 00000000 00000000 00000000 00000000 * :2:0000:0000[5730cb00x_00002000x] (sy)(rpt3)bary.f (ei)hr0.x, (r)0, r0.x :0:0001:0004[03000000x_00000000x] end :0:0002:0005[00000000x_00000000x] nop :0:0003:0006[00000000x_00000000x] nop :0:0004:0007[00000000x_00000000x] nop :0:0005:0008[00000000x_00000000x] nop Stats: - shaderdb: 9 instr, 4 nops, 5 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 1 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 4 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) 00055410: 0000: 000022eb 00046000 t0 write SP_FS_LENGTH_REG (22ef) SP_FS_LENGTH_REG: 1 00055418: 0000: 000022ef 00000001 t0 write RB_RENDER_COMPONENTS (20fb) RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } 00055420: 0000: 000020fb 0000000f t3 opcode: CP_LOAD_STATE4 (30) (3 dwords) { DST_OFF = 0 | STATE_SRC = SS4_INDIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 1 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0x46000 } :2:0000:0000[5730cb00x_00002000x] (sy)(rpt3)bary.f (ei)hr0.x, (r)0, r0.x :0:0001:0004[03000000x_00000000x] end :0:0002:0005[00000000x_00000000x] nop :0:0003:0006[00000000x_00000000x] nop :0:0004:0007[00000000x_00000000x] nop :0:0005:0008[00000000x_00000000x] nop Stats: - shaderdb: 9 instr, 4 nops, 5 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 1 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 4 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) 00055428: 0000: c0013000 00720000 00046000 t0 write SP_SP_CTRL_REG (22c0) SP_SP_CTRL_REG: { 0x60010 } 00055434: 0000: 000022c0 00060010 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 28 | GROUP_ID = 3 } { ADDR_LO = 0x9beb0 } 0005543c: 0000: c0014300 0300001c 0009beb0 t0 write RB_DEPTH_INFO (2103) RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTH4_NONE | DEPTH_BASE = 0 } RB_DEPTH_PITCH: 0 RB_DEPTH_PITCH2: 0 00055448: 0000: 00022103 00000000 00000000 00000000 t0 write GRAS_DEPTH_CONTROL (2077) GRAS_DEPTH_CONTROL: { FORMAT = DEPTH4_NONE } 00055458: 0000: 00002077 00000000 t0 write RB_STENCIL_INFO (2108) RB_STENCIL_INFO: { STENCIL_BASE = 0 } RB_STENCIL_PITCH: 0 0x210a: 00000000 00055460: 0000: 00022108 00000000 00000000 00000000 t0 write 0x2002 (2002) 0x2002: 00000000 00055470: 0000: 00002002 00000000 t0 write RB_ALPHA_CONTROL (20f8) RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } 00055478: 0000: 000020f8 00000e00 t0 write RB_MRT[0].CONTROL (20a4) RB_MRT[0].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0x7 } 00055480: 0000: 000020a4 07000c00 t0 write RB_MRT[0].BLEND_CONTROL (20a8) RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } 00055488: 0000: 000020a8 00000000 t0 write GRAS_CL_CLIP_CNTL (2000) GRAS_CL_CLIP_CNTL: { 0x80000 } 00055490: 0000: 00002000 00080000 t0 write GRAS_SU_POLY_OFFSET_SCALE (2074) GRAS_SU_POLY_OFFSET_SCALE: 0.000000 GRAS_SU_POLY_OFFSET_OFFSET: 0.000000 GRAS_SU_POLY_OFFSET_CLAMP: 0.000000 00055498: 0000: 00022074 00000000 00000000 00000000 t0 write GRAS_SU_MODE_CONTROL (2078) GRAS_SU_MODE_CONTROL: { FRONT_CW | LINEHALFWIDTH = 0.500000 | MSAA_ENABLE | RENDERING_PASS } 000554a8: 0000: 00002078 00102014 t0 write GRAS_SC_SCREEN_SCISSOR_TL (207c) GRAS_SC_SCREEN_SCISSOR_TL: { X = 2 | Y = 13 } GRAS_SC_SCREEN_SCISSOR_BR: { X = 33 | Y = 44 } 000554b0: 0000: 0001207c 000d0002 002c0021 t0 write GRAS_CL_VPORT_XOFFSET_0 (2008) GRAS_CL_VPORT_XOFFSET_0: 18.000000 GRAS_CL_VPORT_XSCALE_0: 16.000000 GRAS_CL_VPORT_YOFFSET_0: 29.000000 GRAS_CL_VPORT_YSCALE_0: 16.000000 GRAS_CL_VPORT_ZOFFSET_0: 0.500000 GRAS_CL_VPORT_ZSCALE_0: 0.500000 000554bc: 0000: 00052008 41900000 41800000 41e80000 41800000 3f000000 3f000000 t0 write GRAS_CL_GB_CLIP_ADJ (2004) GRAS_CL_GB_CLIP_ADJ: { HORZ = 511 | VERT = 511 } 000554d8: 0000: 00002004 0007fdff t0 write GRAS_SC_CONTROL (207b) GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 4 | RASTER_MODE = 0 } 000554e0: 0000: 0000207b 00000200 t0 write 0x2382 (2382) 0x2382: 00000002 000554e8: 0000: 00002382 00000002 t0 write RB_MSAA_CONTROL (20a2) RB_MSAA_CONTROL: { SAMPLES = 4 } 000554f0: 0000: 000020a2 00008000 t0 write RB_RENDER_CONTROL2 (20a3) RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 4 | IJ_PERSP_PIXEL } 000554f8: 0000: 000020a3 00001200 t0 write RB_MRT[0].BUF_INFO (20a5) RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB4_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_ALWAYS | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 1024 } RB_MRT[0].BASE: 0 RB_MRT[0].CONTROL3: { STRIDE = 64 } 00055500: 0000: 000220a5 0010029a 00000000 00000200 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 43 | GROUP_ID = 2 } { ADDR_LO = 0x9bf20 } 00055510: 0000: c0014300 0200002b 0009bf20 t0 write 0x215c (215c) 0x215c: 00000000 0x215d: 00000000 0005551c: 0000: 0001215c 00000000 00000000 t0 write 0x215f (215f) 0x215f: 00000000 00055528: 0000: 0000215f 00000000 t0 write 0x215e (215e) 0x215e: 00000000 00055530: 0000: 0000215e 00000000 t0 write 0x2161 (2161) 0x2161: 00000000 0x2162: 00000000 00055538: 0000: 00012161 00000000 00000000 t0 write 0x2164 (2164) 0x2164: 00000000 00055544: 0000: 00002164 00000000 t0 write 0x2163 (2163) 0x2163: 00000000 0005554c: 0000: 00002163 00000000 t0 write 0x2166 (2166) 0x2166: 00000000 0x2167: 00000000 00055554: 0000: 00012166 00000000 00000000 t0 write 0x2169 (2169) 0x2169: 00000000 00055560: 0000: 00002169 00000000 t0 write 0x2168 (2168) 0x2168: 00000000 00055568: 0000: 00002168 00000000 t0 write 0x216b (216b) 0x216b: 00000000 0x216c: 00000000 00055570: 0000: 0001216b 00000000 00000000 t0 write VPC_SO_FLUSH_WADDR_3 (216e) VPC_SO_FLUSH_WADDR_3: 0 0005557c: 0000: 0000216e 00000000 t0 write 0x216d (216d) 0x216d: 00000000 00055584: 0000: 0000216d 00000000 t0 write UNKNOWN_2156 (2156) UNKNOWN_2156: 0 0005558c: 0000: 00002156 00000000 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 18 | GROUP_ID = 1 } { ADDR_LO = 0x9bfd0 } 00055594: 0000: c0014300 01000012 0009bfd0 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 15 | GROUP_ID = 0 } { ADDR_LO = 0x9c020 } 000555a0: 0000: c0014300 0000000f 0009c020 group_id: 0 count: 15 addr: 000000000009c020 flags: 0 0009c020: 0000: 00002073 00000000 00002101 00000000 00002106 00000000 000021e5 00000000 0009c040: 0020: 0001210b 00000000 00000000 00002381 00000000 000023a0 00000000 t0 write GRAS_ALPHA_CONTROL (2073) GRAS_ALPHA_CONTROL: { 0 } 0009c020: 0000: 00002073 00000000 t0 write RB_DEPTH_CONTROL (2101) RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } 0009c028: 0000: 00002101 00000000 t0 write RB_STENCIL_CONTROL (2106) RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } 0009c030: 0000: 00002106 00000000 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 0009c038: 0000: 000021e5 00000000 t0 write RB_STENCILREFMASK (210b) RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 0009c040: 0000: 0001210b 00000000 00000000 t0 write TPL1_TP_TEX_COUNT (2381) TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } 0009c04c: 0000: 00002381 00000000 t0 write TPL1_TP_FS_TEX_COUNT (23a0) TPL1_TP_FS_TEX_COUNT: 0 0009c054: 0000: 000023a0 00000000 group_id: 1 count: 18 addr: 000000000009bfd0 flags: 0 0009bfd0: 0000: 00002200 082a0008 00002201 fcfc0081 00002203 0000fc00 0007220a 0008080f 0009bff0: 0020: 0009be50 00000060 00000001 0000080f 0009be80 00000030 00000001 0001228a 0009c010: 0040: 7000411f 3000011f t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } 0009bfd0: 0000: 00002200 082a0008 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } 0009bfd8: 0000: 00002201 fcfc0081 t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } 0009bfe0: 0000: 00002203 0000fc00 t0 write VFD_FETCH[0].INSTR_0 (220a) VFD_FETCH[0].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 | SWITCHNEXT } VFD_FETCH[0].INSTR_1: 0x9be50 VFD_FETCH[0].INSTR_2: { SIZE = 0x60 } VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 } VFD_FETCH[0x1].INSTR_1: 0x9be80 VFD_FETCH[0x1].INSTR_2: { SIZE = 0x30 } VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } 0009bfe8: 0000: 0007220a 0008080f 0009be50 00000060 00000001 0000080f 0009be80 00000030 0009c008: 0020: 00000001 t0 write VFD_DECODE[0].INSTR (228a) VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID | SWITCHNEXT } VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID } 0009c00c: 0000: 0001228a 7000411f 3000011f group_id: 2 count: 43 addr: 000000000009bf20 flags: 0 0009bf20: 0000: 000020a1 00000000 000022f1 0001a100 000022f0 fc00fc01 00002100 00000001 0009bf40: 0020: 000021e5 00000000 000020f9 ffff0501 0000214a 00000000 00002140 42001004 0009bf60: 0040: 001922c6 0010fc04 00001e00 00000000 00000000 00000000 00000000 00000000 * 0009bfa0: 0080: 00000000 00000000 00fcfc00 00000008 00000000 00000000 00000000 00000000 * t0 write RB_RENDER_CONTROL (20a1) RB_RENDER_CONTROL: { 0 } 0009bf20: 0000: 000020a1 00000000 t0 write SP_FS_MRT[0].REG (22f1) SP_FS_MRT[0].REG: { REGID = r0.x | HALF_PRECISION | MRTFORMAT = RB4_R8G8B8A8_UNORM } 0009bf28: 0000: 000022f1 0001a100 t0 write SP_FS_OUTPUT_REG (22f0) SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 0009bf30: 0000: 000022f0 fc00fc01 t0 write RB_FS_OUTPUT_REG (2100) RB_FS_OUTPUT_REG: { MRT = 1 } 0009bf38: 0000: 00002100 00000001 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 0009bf40: 0000: 000021e5 00000000 t0 write RB_FS_OUTPUT (20f9) RB_FS_OUTPUT: { ENABLE_BLEND = 0x1 | INDEPENDENT_BLEND | SAMPLE_MASK = 0xffff | 0x400 } 0009bf48: 0000: 000020f9 ffff0501 t0 write VPC_VARYING_PS_REPL[0].MODE (214a) VPC_VARYING_PS_REPL[0].MODE: 0 0009bf50: 0000: 0000214a 00000000 t0 write VPC_ATTR (2140) VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 } 0009bf58: 0000: 00002140 42001004 t0 write SP_VS_PARAM_REG (22c6) SP_VS_PARAM_REG: { POSREGID = r1.x | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } SP_VS_OUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } UNKNOWN_22D7: 0xfcfc00 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 0009bf60: 0000: 001922c6 0010fc04 00001e00 00000000 00000000 00000000 00000000 00000000 * 0009bfa0: 0040: 00000000 00000000 00fcfc00 00000008 00000000 00000000 00000000 00000000 * group_id: 3 count: 28 addr: 000000000009beb0 flags: 0 0009beb0: 0000: 000021c4 02000001 00002141 00040400 00002001 00000000 000022c4 00200800 0009bed0: 0020: 000022c5 08000002 0000230c 00000000 00002318 00000000 00002319 00000000 0009bef0: 0040: 00002340 00000000 00002202 fcfcfcfc 00002204 0000fcfc 00002154 00000000 0009bf10: 0060: 000021e7 00000000 000021c5 00000012 t0 write PC_PRIM_VTX_CNTL (21c4) PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } 0009beb0: 0000: 000021c4 02000001 t0 write VPC_PACK (2141) VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } 0009beb8: 0000: 00002141 00040400 t0 write UNKNOWN_2001 (2001) UNKNOWN_2001: 0 0009bec0: 0000: 00002001 00000000 t0 write SP_VS_CTRL_REG0 (22c4) SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 2 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 0009bec8: 0000: 000022c4 00200800 t0 write SP_VS_CTRL_REG1 (22c5) SP_VS_CTRL_REG1: { CONSTLENGTH = 2 | INITIALOUTSTANDING = 8 } 0009bed0: 0000: 000022c5 08000002 t0 write 0x230c (230c) 0x230c: 00000000 0009bed8: 0000: 0000230c 00000000 t0 write 0x2318 (2318) 0x2318: 00000000 0009bee0: 0000: 00002318 00000000 t0 write 0x2319 (2319) 0x2319: 00000000 0009bee8: 0000: 00002319 00000000 t0 write 0x2340 (2340) 0x2340: 00000000 0009bef0: 0000: 00002340 00000000 t0 write VFD_CONTROL_2 (2202) VFD_CONTROL_2: 0xfcfcfcfc 0009bef8: 0000: 00002202 fcfcfcfc t0 write VFD_CONTROL_4 (2204) VFD_CONTROL_4: 0xfcfc 0009bf00: 0000: 00002204 0000fcfc t0 write UNKNOWN_2154 (2154) UNKNOWN_2154: 0 0009bf08: 0000: 00002154 00000000 t0 write PC_HS_PARAM (21e7) PC_HS_PARAM: { VERTICES_OUT = 0 | SPACING = EQUAL_SPACING } 0009bf10: 0000: 000021e7 00000000 t0 write PC_PRIM_VTX_CNTL2 (21c5) PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 0009bf18: 0000: 000021c5 00000012 t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = USE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x200000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 3 } draw[66] register values + 00000000 0xcc4: 00000000 + 00000004 UNKNOWN_0CC5: 0x4 + 80200000 0xd03: 80200000 !+ 00000001 HLSQ_MODE_CONTROL: 0x1 + 00000000 UNKNOWN_0E42: 0 + 00000100 VPC_DEBUG_ECO_CONTROL: 0x100 + 00040000 UNKNOWN_0EC2: 0x40000 !+ 0000001e SP_MODE_CONTROL: 0x1e !+ 00000028 TPL1_TP_MODE_CONTROL: 0x28 !+ 00080000 GRAS_CL_CLIP_CNTL: { 0x80000 } + 00000000 UNKNOWN_2001: 0 + 00000000 0x2002: 00000000 + 00000001 GRAS_CNTL: { IJ_PERSP } + 0007fdff GRAS_CL_GB_CLIP_ADJ: { HORZ = 511 | VERT = 511 } + 41900000 GRAS_CL_VPORT_XOFFSET_0: 18.000000 + 41800000 GRAS_CL_VPORT_XSCALE_0: 16.000000 + 41e80000 GRAS_CL_VPORT_YOFFSET_0: 29.000000 + 41800000 GRAS_CL_VPORT_YSCALE_0: 16.000000 + 3f000000 GRAS_CL_VPORT_ZOFFSET_0: 0.500000 + 3f000000 GRAS_CL_VPORT_ZSCALE_0: 0.500000 + ffc00010 GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 4092.000000 } + 00000008 GRAS_SU_POINT_SIZE: 0.500000 + 00000000 0x2072: 00000000 !+ 00000000 GRAS_ALPHA_CONTROL: { 0 } + 00000000 GRAS_SU_POLY_OFFSET_SCALE: 0.000000 + 00000000 GRAS_SU_POLY_OFFSET_OFFSET: 0.000000 + 00000000 GRAS_SU_POLY_OFFSET_CLAMP: 0.000000 + 00000000 GRAS_DEPTH_CONTROL: { FORMAT = DEPTH4_NONE } !+ 00102014 GRAS_SU_MODE_CONTROL: { FRONT_CW | LINEHALFWIDTH = 0.500000 | MSAA_ENABLE | RENDERING_PASS } !+ 00000200 GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 4 | RASTER_MODE = 0 } !+ 000d0002 GRAS_SC_SCREEN_SCISSOR_TL: { X = 2 | Y = 13 } !+ 002c0021 GRAS_SC_SCREEN_SCISSOR_BR: { X = 33 | Y = 44 } !+ 00000000 RB_RENDER_CONTROL: { 0 } !+ 00008000 RB_MSAA_CONTROL: { SAMPLES = 4 } !+ 00001200 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 4 | IJ_PERSP_PIXEL } !+ 07000c00 RB_MRT[0].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0x7 } !+ 0010029a RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB4_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_ALWAYS | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 1024 } !+ 00000000 RB_MRT[0].BASE: 0 !+ 00000200 RB_MRT[0].CONTROL3: { STRIDE = 64 } + 00000000 RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } + 00000e00 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } !+ ffff0501 RB_FS_OUTPUT: { ENABLE_BLEND = 0x1 | INDEPENDENT_BLEND | SAMPLE_MASK = 0xffff | 0x400 } + 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } + 00000001 RB_FS_OUTPUT_REG: { MRT = 1 } + 00000000 RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } + 00000000 RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTH4_NONE | DEPTH_BASE = 0 } + 00000000 RB_DEPTH_PITCH: 0 + 00000000 RB_DEPTH_PITCH2: 0 + 00000000 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } + 00000000 RB_STENCIL_INFO: { STENCIL_BASE = 0 } + 00000000 RB_STENCIL_PITCH: 0 + 00000000 0x210a: 00000000 + 00000000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } + 00000000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } !+ 42001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 } + 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } !+ 00000000 VPC_VARYING_INTERP[0].MODE: 0 !+ 00000000 VPC_VARYING_PS_REPL[0].MODE: 0 + 00000000 UNKNOWN_2152: 0 + 00000000 UNKNOWN_2153: 0 + 00000000 UNKNOWN_2154: 0 + 00000000 UNKNOWN_2155: 0 + 00000000 UNKNOWN_2156: 0 + 00000000 0x215c: 00000000 + 00000000 0x215d: 00000000 + 00000000 0x215e: 00000000 + 00000000 0x215f: 00000000 + 00000000 0x2161: 00000000 + 00000000 0x2162: 00000000 + 00000000 0x2163: 00000000 + 00000000 0x2164: 00000000 + 00000000 0x2166: 00000000 + 00000000 0x2167: 00000000 + 00000000 0x2168: 00000000 + 00000000 0x2169: 00000000 + 00000000 0x216b: 00000000 + 00000000 0x216c: 00000000 + 00000000 0x216d: 00000000 + 00000000 VPC_SO_FLUSH_WADDR_3: 0 !+ 0000001f UNKNOWN_21C3: 0x1f !+ 02000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + ffffffff PC_RESTART_INDEX: 0xffffffff + 00000000 PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } + 00000001 UNKNOWN_21E6: 0x1 + 00000000 PC_HS_PARAM: { VERTICES_OUT = 0 | SPACING = EQUAL_SPACING } !+ 082a0008 VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } !+ fcfc0081 VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } + fcfcfcfc VFD_CONTROL_2: 0xfcfcfcfc !+ 0000fc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } + 0000fcfc VFD_CONTROL_4: 0xfcfc + 00000000 VFD_INDEX_OFFSET: 0 + 00000000 UNKNOWN_2209: 0 + 0008080f VFD_FETCH[0].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 | SWITCHNEXT } !+ 0009be50 VFD_FETCH[0].INSTR_1: 0x9be50 + 00000060 VFD_FETCH[0].INSTR_2: { SIZE = 0x60 } + 00000001 VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } + 0000080f VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 } !+ 0009be80 VFD_FETCH[0x1].INSTR_1: 0x9be80 + 00000030 VFD_FETCH[0x1].INSTR_2: { SIZE = 0x30 } + 00000001 VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } + 7000411f VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID | SWITCHNEXT } + 3000011f VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID } + 00060010 SP_SP_CTRL_REG: { 0x60010 } + 000005c3 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } !+ 00200800 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 2 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } !+ 08000002 SP_VS_CTRL_REG1: { CONSTLENGTH = 2 | INITIALOUTSTANDING = 8 } !+ 0010fc04 SP_VS_PARAM_REG: { POSREGID = r1.x | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } !+ 00001e00 SP_VS_OUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00fcfc00 UNKNOWN_22D7: 0xfcfc00 + 00000008 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } !+ 00049000 SP_VS_OBJ_START: 0x49000 00049000: 0000: 00000000 13000000 00000000 00000000 00000000 00000000 00000000 00000000 * :0:0000:0000[13000000x_00000000x] (sy)end :0:0001:0001[00000000x_00000000x] nop :0:0002:0002[00000000x_00000000x] nop :0:0003:0003[00000000x_00000000x] nop :0:0004:0004[00000000x_00000000x] nop Stats: - shaderdb: 5 instr, 4 nops, 1 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 0 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 0 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) !+ 00000001 SP_VS_LENGTH_REG: 1 !+ 00340412 SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE } !+ 80100002 SP_FS_CTRL_REG1: { CONSTLENGTH = 2 | VARYING | 0x80000000 } !+ 7e020000 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } !+ 00046000 SP_FS_OBJ_START: 0x46000 00046000: 0000: 00002000 5730cb00 00000000 03000000 00000000 00000000 00000000 00000000 * :2:0000:0000[5730cb00x_00002000x] (sy)(rpt3)bary.f (ei)hr0.x, (r)0, r0.x :0:0001:0004[03000000x_00000000x] end :0:0002:0005[00000000x_00000000x] nop :0:0003:0006[00000000x_00000000x] nop :0:0004:0007[00000000x_00000000x] nop :0:0005:0008[00000000x_00000000x] nop Stats: - shaderdb: 9 instr, 4 nops, 5 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 1 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 4 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) + 00000001 SP_FS_LENGTH_REG: 1 !+ fc00fc01 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r63.x } !+ 0001a100 SP_FS_MRT[0].REG: { REGID = r0.x | HALF_PRECISION | MRTFORMAT = RB4_R8G8B8A8_UNORM } + 00000000 0x230c: 00000000 + 7e020000 SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } + 00000000 SP_HS_OBJ_START: 0 + 00000000 0x2318: 00000000 + 00000000 0x2319: 00000000 + 7e020000 SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } + 00000000 SP_DS_OBJ_START: 0 + 00000000 0x2340: 00000000 + 7e020000 SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } + 00000000 SP_GS_OBJ_START: 0 + 00000808 TPL1_TP_TEX_OFFSET: 0x808 + 00000000 TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } !+ 00000002 0x2382: 00000002 !+ 00000000 TPL1_TP_FS_TEX_COUNT: 0 !+ 080604f0 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0x600a0 } !+ fcfc1108 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x1008 } !+ fff3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } + fcfcfc00 HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } !+ 00fcfc00 HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r0.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } !+ 01010002 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 2 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 1 } !+ 017f0202 HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 2 | CONSTOBJECTOFFSET = 2 | ENABLED | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 } !+ 007e0200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } !+ 007e0200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } !+ 007e0200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } !+ 00000003 HLSQ_UPDATE_CONTROL: 0x3 000555ac: 0000: c0023800 00200984 00000001 00000003 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 18 | GROUP_ID = 1 } { ADDR_LO = 0x9c190 } 000555bc: 0000: c0014300 01000012 0009c190 group_id: 1 count: 18 addr: 000000000009c190 flags: 0 0009c190: 0000: 00002200 082a0008 00002201 fcfc0081 00002203 0000fc00 0007220a 0008080f 0009c1b0: 0020: 0009c130 00000060 00000001 0000080f 0009c160 00000030 00000001 0001228a 0009c1d0: 0040: 7000411f 3000011f t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } 0009c190: 0000: 00002200 082a0008 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } 0009c198: 0000: 00002201 fcfc0081 t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } 0009c1a0: 0000: 00002203 0000fc00 t0 write VFD_FETCH[0].INSTR_0 (220a) VFD_FETCH[0].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 | SWITCHNEXT } VFD_FETCH[0].INSTR_1: 0x9c130 VFD_FETCH[0].INSTR_2: { SIZE = 0x60 } VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 } VFD_FETCH[0x1].INSTR_1: 0x9c160 VFD_FETCH[0x1].INSTR_2: { SIZE = 0x30 } VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } 0009c1a8: 0000: 0007220a 0008080f 0009c130 00000060 00000001 0000080f 0009c160 00000030 0009c1c8: 0020: 00000001 t0 write VFD_DECODE[0].INSTR (228a) VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID | SWITCHNEXT } VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID } 0009c1cc: 0000: 0001228a 7000411f 3000011f t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = USE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x200000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 3 } draw[67] register values + 082a0008 VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } + fcfc0081 VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } + 0000fc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } + 0008080f VFD_FETCH[0].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 | SWITCHNEXT } !+ 0009c130 VFD_FETCH[0].INSTR_1: 0x9c130 + 00000060 VFD_FETCH[0].INSTR_2: { SIZE = 0x60 } + 00000001 VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } + 0000080f VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 } !+ 0009c160 VFD_FETCH[0x1].INSTR_1: 0x9c160 + 00000030 VFD_FETCH[0x1].INSTR_2: { SIZE = 0x30 } + 00000001 VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } + 7000411f VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID | SWITCHNEXT } + 3000011f VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID } 000555c8: 0000: c0023800 00200984 00000001 00000003 0016b094: 0000: c0013f00 00055328 000000ac t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 0016b0a0: 0000: c0014300 00040000 00000000 t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:001fa234 ibsize:000000f7 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 001fa234: 0000: c0002600 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x4 001fa23c: 0000: 00000ec3 00000004 t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x68 001fa244: 0000: 00000f03 00000068 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 001fa24c: 0000: c0002600 00000000 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } 001fa254: 0000: 000023c0 080004f0 t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = 0x1d } event (null) 001fa25c: 0000: c0004600 0000001d t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = FACENESS_FLUSH } event FACENESS_FLUSH 001fa264: 0000: c0004600 0000001c t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 001fa26c: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0 001fa274: 0000: 00000cc6 00000000 t0 write UNKNOWN_0E42 (0e42) UNKNOWN_0E42: 0 001fa27c: 0000: 00000e42 00000000 t0 write HLSQ_MODE_CONTROL (0e05) HLSQ_MODE_CONTROL: 0x2 001fa284: 0000: 00000e05 00000002 t0 write UNKNOWN_0CC5 (0cc5) UNKNOWN_0CC5: 0x4 001fa28c: 0000: 00000cc5 00000004 t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x7 001fa294: 0000: 000023db 00000007 t0 write VFD_CONTROL_2 (2202) VFD_CONTROL_2: 0xfcfcfcfc 001fa29c: 0000: 00002202 fcfcfcfc t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } 001fa2a4: 0000: 00002203 fcfcfc00 t0 write VFD_CONTROL_4 (2204) VFD_CONTROL_4: 0xfcfc 001fa2ac: 0000: 00002204 0000fcfc t0 write VFD_INDEX_OFFSET (2208) VFD_INDEX_OFFSET: 0 001fa2b4: 0000: 00002208 00000000 t0 write UNKNOWN_2209 (2209) UNKNOWN_2209: 0 001fa2bc: 0000: 00002209 00000000 t0 write UNKNOWN_2152 (2152) UNKNOWN_2152: 0 UNKNOWN_2153: 0 001fa2c4: 0000: 00012152 00000000 00000000 t0 write UNKNOWN_2156 (2156) UNKNOWN_2156: 0 001fa2d0: 0000: 00002156 00000000 t0 write UNKNOWN_2154 (2154) UNKNOWN_2154: 0 001fa2d8: 0000: 00002154 00000000 t0 write UNKNOWN_2155 (2155) UNKNOWN_2155: 0 001fa2e0: 0000: 00002155 00000000 t0 write UNKNOWN_21C3 (21c3) UNKNOWN_21C3: 0x1d 001fa2e8: 0000: 000021c3 0000001d t0 write PC_PRIM_VTX_CNTL2 (21c5) PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 001fa2f0: 0000: 000021c5 00000012 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 001fa2f8: 0000: 000021e5 00000000 t0 write GRAS_SU_MODE_CONTROL (2078) GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } 001fa300: 0000: 00002078 00000000 t0 write UNKNOWN_2001 (2001) UNKNOWN_2001: 0 001fa308: 0000: 00002001 00000000 t0 write GRAS_CNTL (2003) GRAS_CNTL: { IJ_PERSP } 001fa310: 0000: 00002003 00000001 t0 write GRAS_CL_CLIP_CNTL (2000) GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } 001fa318: 0000: 00002000 00188000 t0 write TPL1_TP_TEX_COUNT (2381) TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } 001fa320: 0000: 00002381 00000000 t0 write TPL1_TP_FS_TEX_COUNT (23a0) TPL1_TP_FS_TEX_COUNT: 0x3 001fa328: 0000: 000023a0 00000003 t0 write RB_ALPHA_CONTROL (20f8) RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } 001fa330: 0000: 000020f8 00000e00 t0 write RB_RENDER_COMPONENTS (20fb) RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } 001fa338: 0000: 000020fb 0000000f t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 001fa340: 0000: c0014300 00040000 00000000 t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } 001fa34c: 0000: 00002200 000a0000 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } 001fa354: 0000: 00002201 fc030000 t0 write SP_INSTR_CACHE_CTRL (22c1) SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } 001fa35c: 0000: 000022c1 000005c3 t0 write HLSQ_CONTROL_1_REG (23c1) HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } 001fa364: 0000: 000023c1 fcfc0120 t0 write HLSQ_CONTROL_2_REG (23c2) HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 001fa36c: 0000: 000023c2 27f3f3f0 t0 write HLSQ_VS_CONTROL_REG (23c5) HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } 001fa374: 0000: 000023c5 02010042 t0 write HLSQ_FS_CONTROL_REG (23c6) HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 001fa37c: 0000: 000023c6 0041423e t0 write HLSQ_HS_CONTROL_REG (23c7) HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 001fa384: 0000: 000023c7 00404200 t0 write HLSQ_DS_CONTROL_REG (23c8) HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 001fa38c: 0000: 000023c8 00404200 t0 write HLSQ_GS_CONTROL_REG (23c9) HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 001fa394: 0000: 000023c9 00404200 t0 write HLSQ_CS_CONTROL_REG (23ca) HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } 001fa39c: 0000: 000023ca 00004200 t0 write SP_SP_CTRL_REG (22c0) SP_SP_CTRL_REG: { 0x60010 } 001fa3a4: 0000: 000022c0 00060010 t0 write UNKNOWN_21E6 (21e6) UNKNOWN_21E6: 0x1 001fa3ac: 0000: 000021e6 00000001 t0 write SP_VS_CTRL_REG0 (22c4) SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 001fa3b4: 0000: 000022c4 00200c10 t0 write SP_VS_CTRL_REG1 (22c5) SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } 001fa3bc: 0000: 000022c5 01000042 t0 write VPC_ATTR (2140) VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | 0x40000000 } 001fa3c4: 0000: 00002140 40001004 t0 write VPC_PACK (2141) VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } 001fa3cc: 0000: 00002141 00040400 t0 write PC_PRIM_VTX_CNTL (21c4) PC_PRIM_VTX_CNTL: { VAROUT = 1 } 001fa3d4: 0000: 000021c4 00000001 t0 write SP_VS_PARAM_REG (22c6) SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } UNKNOWN_22D7: 0xfcfc00 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 001fa3dc: 0000: 001922c6 0010fc03 00001e03 00000000 00000000 00000000 00000000 00000000 * 001fa41c: 0040: 00000000 00000000 00fcfc00 00000008 00000000 00000000 00000000 00000000 * t0 write SP_VS_OBJ_OFFSET_REG (22e0) SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 001fa448: 0000: 000022e0 00000000 t0 write SP_VS_OBJ_START (22e1) SP_VS_OBJ_START: 0x1 001fa450: 0000: 000022e1 00000001 t0 write SP_VS_LENGTH_REG (22e5) SP_VS_LENGTH_REG: 2 001fa458: 0000: 000022e5 00000002 t3 opcode: CP_LOAD_STATE4 (30) (67 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } :2:0000:0000[56d81803x_20020003x] (sy)(ss)(nop3) shl.b r0.w, r0.w, 2 :1:0001:0004[20150000x_00000003x] cov.s32s16 hr0.x, r0.w :0:0002:0005[00000200x_00000000x] (rpt2)nop :1:0003:0008[201100f4x_00000000x] mova a0.x, hr0.x :0:0004:0009[00000500x_00000000x] (rpt5)nop :1:0005:0015[20154003x_00000c20x] mov.s32s32 r0.w, c :1:0006:0016[20154004x_00000c21x] mov.s32s32 r1.x, c :1:0007:0017[20154005x_00000c22x] mov.s32s32 r1.y, c :1:0008:0018[20156006x_00000c23x] (ul)mov.s32s32 r1.z, c :0:0009:0019[03000000x_00000000x] end :2:0010:0020[46f00007x_20050000x] shr.b r1.w, r0.x, 5 :2:0011:0021[43980008x_201f0000x] (nop2) and.b r2.x, r0.x, 31 :2:0012:0024[43980807x_201f0007x] (nop3) and.b r1.w, r1.w, 31 :2:0013:0028[46100807x_20100007x] (nop1) mul.u24 r1.w, r1.w, 16 :3:0014:0030[62040007x_00071014x] mad.u24 r1.w, c5.x, r2.x, r1.w :0:0015:0031[00000500x_00000000x] (rpt5)nop :6:0016:0037[c2c60f00x_04800006x] stlw.u32 l[r1.w], r0.w, 4 :0:0017:0038[04800000x_00000000x] chmask :0:0018:0039[05000000x_00000000x] chsh Stats: - shaderdb: 40 instr, 24 nops, 16 non-nops, 5 mov, 1 cov - shaderdb: 0 last-baryf, 0 half, 2 full, 5 constlen - shaderdb: 27 cat0, 6 cat1, 5 cat2, 1 cat3, 0 cat4, 0 cat5, 1 cat6, 0 cat7 - shaderdb: 0 sstall, 1 (ss), 1 (sy) 001fa460: 0000: c0413000 00a00000 00000000 20020003 56d81803 00000003 20150000 00000000 001fa480: 0020: 00000200 00000000 201100f4 00000000 00000500 00000c20 20154003 00000c21 001fa4a0: 0040: 20154004 00000c22 20154005 00000c23 20156006 00000000 03000000 20050000 001fa4c0: 0060: 46f00007 201f0000 43980008 201f0007 43980807 20100007 46100807 00071014 001fa4e0: 0080: 62040007 00000000 00000500 04800006 c2c60f00 00000000 04800000 00000000 001fa500: 00a0: 05000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 * t0 write GRAS_SC_CONTROL (207b) GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = 0 | MSAA_DISABLE | RASTER_MODE = 0 } 001fa56c: 0000: 0000207b 00000808 t0 write RB_MSAA_CONTROL (20a2) RB_MSAA_CONTROL: { DISABLE | SAMPLES = 0 } 001fa574: 0000: 000020a2 00001000 t0 write RB_RENDER_CONTROL (20a1) RB_RENDER_CONTROL: { DISABLE_COLOR_PIPE | 0x2 } 001fa57c: 0000: 000020a1 00000022 t0 write RB_DEPTH_CONTROL (2101) RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } 001fa584: 0000: 00002101 00000000 t0 write GRAS_ALPHA_CONTROL (2073) GRAS_ALPHA_CONTROL: { 0x2 } 001fa58c: 0000: 00002073 00000002 t0 write RB_STENCIL_CONTROL (2106) RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } 001fa594: 0000: 00002106 00000000 t0 write RB_COPY_CONTROL (20fc) RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_FOUR | MODE = RB_COPY_DEPTH_STENCIL | FASTCLEAR = 0 | GMEM_BASE = 0 } RB_COPY_DEST_BASE: { BASE = 0x4f000 } RB_COPY_DEST_PITCH: { PITCH = 256 } RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_DISABLE | COMPONENT_ENABLE = 0xf | ENDIAN = ENDIAN_NONE | TILE = TILE4_3 } 001fa59c: 0000: 000320fc 00000052 0004f000 00000008 0303c068 t0 write UNKNOWN_20EF (20ef) UNKNOWN_20EF: 0 001fa5b0: 0000: 000020ef 00000000 t0 write GRAS_SC_SCREEN_SCISSOR_TL (207c) GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } 001fa5b8: 0000: 0001207c 00000000 003f003f t0 write RB_FRAME_BUFFER_DIMENSION (0ce0) RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } 001fa5c4: 0000: 00000ce0 00400040 t0 write 0xce1 (0ce1) 0xce1: 00000000 001fa5cc: 0000: 00000ce1 00000000 t3 opcode: CP_LOAD_STATE4 (30) (11 dwords) { DST_OFF = 8 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } 001fa5e0: 0.000000 0.000000 1.000000 1.000000 64.000000 64.000000 1.000000 1.000000 001fa5e0: 0000: 00000000 00000000 3f800000 3f800000 42800000 42800000 3f800000 3f800000 001fa5d4: 0000: c0093000 00a00008 00000001 00000000 00000000 3f800000 3f800000 42800000 001fa5f4: 0020: 42800000 3f800000 3f800000 t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x80000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 2 } draw[68] register values + 00000004 UNKNOWN_0CC5: 0x4 + 00000000 UNKNOWN_0CC6: 0 + 00400040 RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } + 00000000 0xce1: 00000000 !+ 00000002 HLSQ_MODE_CONTROL: 0x2 + 00000000 UNKNOWN_0E42: 0 !+ 00000004 SP_MODE_CONTROL: 0x4 !+ 00000068 TPL1_TP_MODE_CONTROL: 0x68 !+ 00188000 GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } + 00000000 UNKNOWN_2001: 0 + 00000001 GRAS_CNTL: { IJ_PERSP } !+ 00000002 GRAS_ALPHA_CONTROL: { 0x2 } !+ 00000000 GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } !+ 00000808 GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = 0 | MSAA_DISABLE | RASTER_MODE = 0 } !+ 00000000 GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } !+ 003f003f GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } !+ 00000022 RB_RENDER_CONTROL: { DISABLE_COLOR_PIPE | 0x2 } !+ 00001000 RB_MSAA_CONTROL: { DISABLE | SAMPLES = 0 } + 00000000 UNKNOWN_20EF: 0 + 00000e00 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } + 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } !+ 00000052 RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_FOUR | MODE = RB_COPY_DEPTH_STENCIL | FASTCLEAR = 0 | GMEM_BASE = 0 } + 0004f000 RB_COPY_DEST_BASE: { BASE = 0x4f000 } + 00000008 RB_COPY_DEST_PITCH: { PITCH = 256 } !+ 0303c068 RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_DISABLE | COMPONENT_ENABLE = 0xf | ENDIAN = ENDIAN_NONE | TILE = TILE4_3 } + 00000000 RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } + 00000000 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } !+ 40001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | 0x40000000 } + 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } + 00000000 UNKNOWN_2152: 0 + 00000000 UNKNOWN_2153: 0 + 00000000 UNKNOWN_2154: 0 + 00000000 UNKNOWN_2155: 0 + 00000000 UNKNOWN_2156: 0 !+ 0000001d UNKNOWN_21C3: 0x1d !+ 00000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 } + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + 00000000 PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } + 00000001 UNKNOWN_21E6: 0x1 !+ 000a0000 VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } !+ fc030000 VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } + fcfcfcfc VFD_CONTROL_2: 0xfcfcfcfc !+ fcfcfc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } + 0000fcfc VFD_CONTROL_4: 0xfcfc + 00000000 VFD_INDEX_OFFSET: 0 + 00000000 UNKNOWN_2209: 0 + 00060010 SP_SP_CTRL_REG: { 0x60010 } + 000005c3 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } !+ 00200c10 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } !+ 01000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } !+ 0010fc03 SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } !+ 00001e03 SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00fcfc00 UNKNOWN_22D7: 0xfcfc00 + 00000008 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } !+ 00000001 SP_VS_OBJ_START: 0x1 !+ 00000002 SP_VS_LENGTH_REG: 2 + 00000000 TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } !+ 00000003 TPL1_TP_FS_TEX_COUNT: 0x3 !+ 080004f0 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } !+ fcfc0120 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } !+ 27f3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } !+ 02010042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } !+ 0041423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } !+ 00404200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } !+ 00404200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } !+ 00404200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00004200 HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } !+ 00000007 HLSQ_UPDATE_CONTROL: 0x7 001fa600: 0000: c0023800 00080888 00000001 00000002 0016b0ac: 0000: c0013f00 001fa234 000000f7 t3 opcode: (null) (1d) (2 dwords) 0016b0b8: 0000: c0001d00 00000000 ############################################################ vertices: 0 ############################################################ cmdstream: 8 dwords t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:000555d8 ibsize:00000155 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 000555d8: 0000: c0002600 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x4 000555e0: 0000: 00000ec3 00000004 t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x68 000555e8: 0000: 00000f03 00000068 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 000555f0: 0000: c0002600 00000000 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } 000555f8: 0000: 000023c0 080004f0 t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = 0x1d } event (null) 00055600: 0000: c0004600 0000001d t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = FACENESS_FLUSH } event FACENESS_FLUSH 00055608: 0000: c0004600 0000001c t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00055610: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0 00055618: 0000: 00000cc6 00000000 t0 write UNKNOWN_0E42 (0e42) UNKNOWN_0E42: 0 00055620: 0000: 00000e42 00000000 t0 write HLSQ_MODE_CONTROL (0e05) HLSQ_MODE_CONTROL: 0x2 00055628: 0000: 00000e05 00000002 t0 write UNKNOWN_0CC5 (0cc5) UNKNOWN_0CC5: 0x4 00055630: 0000: 00000cc5 00000004 t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x7 00055638: 0000: 000023db 00000007 t0 write VFD_CONTROL_2 (2202) VFD_CONTROL_2: 0xfcfcfcfc 00055640: 0000: 00002202 fcfcfcfc t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } 00055648: 0000: 00002203 fcfcfc00 t0 write VFD_CONTROL_4 (2204) VFD_CONTROL_4: 0xfcfc 00055650: 0000: 00002204 0000fcfc t0 write VFD_INDEX_OFFSET (2208) VFD_INDEX_OFFSET: 0 00055658: 0000: 00002208 00000000 t0 write UNKNOWN_2209 (2209) UNKNOWN_2209: 0 00055660: 0000: 00002209 00000000 t0 write UNKNOWN_2152 (2152) UNKNOWN_2152: 0 UNKNOWN_2153: 0 00055668: 0000: 00012152 00000000 00000000 t0 write UNKNOWN_2156 (2156) UNKNOWN_2156: 0 00055674: 0000: 00002156 00000000 t0 write UNKNOWN_2154 (2154) UNKNOWN_2154: 0 0005567c: 0000: 00002154 00000000 t0 write UNKNOWN_2155 (2155) UNKNOWN_2155: 0 00055684: 0000: 00002155 00000000 t0 write UNKNOWN_21C3 (21c3) UNKNOWN_21C3: 0x1d 0005568c: 0000: 000021c3 0000001d t0 write PC_PRIM_VTX_CNTL2 (21c5) PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 00055694: 0000: 000021c5 00000012 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 0005569c: 0000: 000021e5 00000000 t0 write GRAS_SU_MODE_CONTROL (2078) GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } 000556a4: 0000: 00002078 00000000 t0 write UNKNOWN_2001 (2001) UNKNOWN_2001: 0 000556ac: 0000: 00002001 00000000 t0 write GRAS_CNTL (2003) GRAS_CNTL: { IJ_PERSP } 000556b4: 0000: 00002003 00000001 t0 write GRAS_CL_CLIP_CNTL (2000) GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } 000556bc: 0000: 00002000 00188000 t0 write TPL1_TP_TEX_COUNT (2381) TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } 000556c4: 0000: 00002381 00000000 t0 write TPL1_TP_FS_TEX_COUNT (23a0) TPL1_TP_FS_TEX_COUNT: 0x3 000556cc: 0000: 000023a0 00000003 t0 write RB_ALPHA_CONTROL (20f8) RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } 000556d4: 0000: 000020f8 00000e00 t0 write RB_RENDER_COMPONENTS (20fb) RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } 000556dc: 0000: 000020fb 0000000f t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 000556e4: 0000: c0014300 00040000 00000000 t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } 000556f0: 0000: 00002200 000a0000 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } 000556f8: 0000: 00002201 fc030000 t0 write SP_INSTR_CACHE_CTRL (22c1) SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } 00055700: 0000: 000022c1 000005c3 t0 write HLSQ_CONTROL_1_REG (23c1) HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } 00055708: 0000: 000023c1 fcfc0120 t0 write HLSQ_CONTROL_2_REG (23c2) HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 00055710: 0000: 000023c2 27f3f3f0 t0 write HLSQ_VS_CONTROL_REG (23c5) HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } 00055718: 0000: 000023c5 02010042 t0 write HLSQ_FS_CONTROL_REG (23c6) HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 1 } 00055720: 0000: 000023c6 0141423e t0 write HLSQ_HS_CONTROL_REG (23c7) HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00055728: 0000: 000023c7 00404200 t0 write HLSQ_DS_CONTROL_REG (23c8) HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00055730: 0000: 000023c8 00404200 t0 write HLSQ_GS_CONTROL_REG (23c9) HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00055738: 0000: 000023c9 00404200 t0 write HLSQ_CS_CONTROL_REG (23ca) HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } 00055740: 0000: 000023ca 00004200 t0 write SP_SP_CTRL_REG (22c0) SP_SP_CTRL_REG: { 0x60010 } 00055748: 0000: 000022c0 00060010 t0 write UNKNOWN_21E6 (21e6) UNKNOWN_21E6: 0x1 00055750: 0000: 000021e6 00000001 t0 write SP_VS_CTRL_REG0 (22c4) SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 00055758: 0000: 000022c4 00200c10 t0 write SP_VS_CTRL_REG1 (22c5) SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } 00055760: 0000: 000022c5 01000042 t0 write VPC_ATTR (2140) VPC_ATTR: { TOTALATTR = 8 | THRDASSIGN = 1 | ENABLE | 0x40000000 } 00055768: 0000: 00002140 42001008 t0 write VPC_PACK (2141) VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 8 | NUMNONPOSVSVAR = 6 } 00055770: 0000: 00002141 00060800 t0 write PC_PRIM_VTX_CNTL (21c4) PC_PRIM_VTX_CNTL: { VAROUT = 1 } 00055778: 0000: 000021c4 00000001 t0 write SP_VS_PARAM_REG (22c6) SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 2 } SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r1.w | B_COMPMASK = 0x3 } SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } UNKNOWN_22D7: 0xfcfc00 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 12 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 00055780: 0000: 001922c6 0020fc03 06071e03 00000000 00000000 00000000 00000000 00000000 * 000557c0: 0040: 00000000 00000000 00fcfc00 00000c08 00000000 00000000 00000000 00000000 * t0 write SP_VS_OBJ_OFFSET_REG (22e0) SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 000557ec: 0000: 000022e0 00000000 t0 write SP_VS_OBJ_START (22e1) SP_VS_OBJ_START: 0x1 000557f4: 0000: 000022e1 00000001 t0 write SP_VS_LENGTH_REG (22e5) SP_VS_LENGTH_REG: 2 000557fc: 0000: 000022e5 00000002 t3 opcode: CP_LOAD_STATE4 (30) (67 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } :2:0000:0000[56d81803x_20020003x] (sy)(ss)(nop3) shl.b r0.w, r0.w, 2 :1:0001:0004[20150000x_00000003x] cov.s32s16 hr0.x, r0.w :0:0002:0005[00000200x_00000000x] (rpt2)nop :1:0003:0008[201100f4x_00000000x] mova a0.x, hr0.x :0:0004:0009[00000500x_00000000x] (rpt5)nop :1:0005:0015[20154003x_00000c20x] mov.s32s32 r0.w, c :1:0006:0016[20154004x_00000c21x] mov.s32s32 r1.x, c :1:0007:0017[20154007x_00000c22x] mov.s32s32 r1.w, c :1:0008:0018[20156008x_00000c23x] (ul)mov.s32s32 r2.x, c :1:0009:0019[20554005x_00000000x] mov.s32s32 r1.y, 0 :1:0010:0020[20554006x_3f800000x] mov.s32s32 r1.z, 1065353216 :0:0011:0021[03000000x_00000000x] end :2:0012:0022[46f00009x_20050000x] shr.b r2.y, r0.x, 5 :2:0013:0023[4398000ax_201f0000x] (nop2) and.b r2.z, r0.x, 31 :2:0014:0026[43980809x_201f0009x] (nop3) and.b r2.y, r2.y, 31 :2:0015:0030[46100809x_20180009x] (nop1) mul.u24 r2.y, r2.y, 24 :3:0016:0032[62050009x_00091014x] mad.u24 r2.y, c5.x, r2.z, r2.y :0:0017:0033[00000500x_00000000x] (rpt5)nop :6:0018:0039[c2c61300x_04800006x] stlw.u32 l[r2.y], r0.w, 4 :6:0019:0040[c2c61310x_0280000ex] stlw.u32 l[r2.y+16], r1.w, 2 :0:0020:0041[04800000x_00000000x] chmask :0:0021:0042[05000000x_00000000x] chsh Stats: - shaderdb: 43 instr, 24 nops, 19 non-nops, 7 mov, 1 cov - shaderdb: 0 last-baryf, 0 half, 3 full, 5 constlen - shaderdb: 27 cat0, 8 cat1, 5 cat2, 1 cat3, 0 cat4, 0 cat5, 2 cat6, 0 cat7 - shaderdb: 0 sstall, 1 (ss), 1 (sy) 00055804: 0000: c0413000 00a00000 00000000 20020003 56d81803 00000003 20150000 00000000 00055824: 0020: 00000200 00000000 201100f4 00000000 00000500 00000c20 20154003 00000c21 00055844: 0040: 20154004 00000c22 20154007 00000c23 20156008 00000000 20554005 3f800000 00055864: 0060: 20554006 00000000 03000000 20050000 46f00009 201f0000 4398000a 201f0009 00055884: 0080: 43980809 20180009 46100809 00091014 62050009 00000000 00000500 04800006 000558a4: 00a0: c2c61300 0280000e c2c61310 00000000 04800000 00000000 05000000 00000000 * t0 write HLSQ_CONTROL_3_REG (23c3) HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } 00055910: 0000: 000023c3 fcfcfc00 t0 write HLSQ_CONTROL_4_REG (23c4) HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } 00055918: 0000: 000023c4 00fcfcfc t0 write SP_FS_CTRL_REG0 (22e8) SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 0 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE | PIXLODENABLE } SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 } 00055920: 0000: 000122e8 00700402 8010003e t0 write SP_FS_OBJ_OFFSET_REG (22ea) SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 } 0005592c: 0000: 000022ea 40420000 t0 write SP_FS_OBJ_START (22eb) SP_FS_OBJ_START: 0x1 00055934: 0000: 000022eb 00000001 t0 write SP_FS_LENGTH_REG (22ef) SP_FS_LENGTH_REG: 1 0005593c: 0000: 000022ef 00000001 t0 write SP_FS_OUTPUT_REG (22f0) SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r0.x | SAMPLEMASK_REGID = r0.x } 00055944: 0000: 000022f0 00000001 t0 write VPC_VARYING_INTERP[0].MODE (2142) VPC_VARYING_INTERP[0].MODE: 0xe000 0005594c: 0000: 00002142 0000e000 t0 write RB_FS_OUTPUT_REG (2100) RB_FS_OUTPUT_REG: { MRT = 1 } 00055954: 0000: 00002100 00000001 t3 opcode: CP_LOAD_STATE4 (30) (35 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 1 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } :2:0000:0000[57309902x_00002004x] (sy)(ss)(rpt1)bary.f (ei)r0.z, (r)4, r0.x :0:0001:0002[00000500x_00000000x] (rpt5)nop :5:0002:0008[a0c01f00x_00000005x] sam (f32)(xyzw)r0.x, r0.z, s#0, t#0 :0:0003:0009[03000000x_00000000x] end :0:0004:0010[00000000x_00000000x] nop :0:0005:0011[00000000x_00000000x] nop :0:0006:0012[00000000x_00000000x] nop :0:0007:0013[00000000x_00000000x] nop Stats: - shaderdb: 14 instr, 10 nops, 4 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 0 half, 1 full, 0 constlen - shaderdb: 11 cat0, 0 cat1, 2 cat2, 0 cat3, 0 cat4, 1 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 1 (ss), 1 (sy) 0005595c: 0000: c0213000 00700000 00000000 00002004 57309902 00000000 00000500 00000005 0005597c: 0020: a0c01f00 00000000 03000000 00000000 00000000 00000000 00000000 00000000 * t0 write RB_FS_OUTPUT (20f9) RB_FS_OUTPUT: { ENABLE_BLEND = 0 | SAMPLE_MASK = 0xffff } 000559e8: 0000: 000020f9 ffff0000 t0 write RB_MRT[0].CONTROL (20a4) RB_MRT[0].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0xf } 000559f0: 0000: 000020a4 0f000000 t0 write RB_MRT[0x1].CONTROL (20a9) RB_MRT[0x1].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0xf } 000559f8: 0000: 000020a9 0f000000 t0 write RB_MRT[0].BLEND_CONTROL (20a8) RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } 00055a00: 0000: 000020a8 00000000 t3 opcode: CP_LOAD_STATE4 (30) (5 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_TEX | NUM_UNIT = 1 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } { XY_MAG = A4XX_TEX_NEAREST | XY_MIN = A4XX_TEX_NEAREST | WRAP_S = A4XX_TEX_CLAMP_TO_EDGE | WRAP_T = A4XX_TEX_CLAMP_TO_EDGE | WRAP_R = A4XX_TEX_CLAMP_TO_EDGE | ANISO = A4XX_TEX_ANISO_1 | LOD_BIAS = 0.000000 | 0x60000 } { COMPARE_FUNC = FUNC_LEQUAL | UNNORM_COORDS | MIPFILTER_LINEAR_FAR | MAX_LOD = 0.000000 | MIN_LOD = 0.000000 | 0x1 } 00055a14: 0000: 00060920 00000067 00055a08: 0000: c0033000 00500000 00000000 00060920 00000067 t0 write GRAS_SC_CONTROL (207b) GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 0 | RASTER_MODE = 0 } 00055a1c: 0000: 0000207b 00000000 t0 write RB_MSAA_CONTROL (20a2) RB_MSAA_CONTROL: { SAMPLES = 0 } 00055a24: 0000: 000020a2 00000000 t0 write RB_RENDER_CONTROL (20a1) RB_RENDER_CONTROL: { 0 } 00055a2c: 0000: 000020a1 00000000 t0 write 0x2382 (2382) 0x2382: 00000000 00055a34: 0000: 00002382 00000000 t0 write RB_DEPTH_CONTROL (2101) RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } 00055a3c: 0000: 00002101 00000000 t0 write GRAS_ALPHA_CONTROL (2073) GRAS_ALPHA_CONTROL: { 0 } 00055a44: 0000: 00002073 00000000 t0 write RB_STENCIL_CONTROL (2106) RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } 00055a4c: 0000: 00002106 00000000 t0 write SP_FS_MRT[0].REG (22f1) SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = RB4_R8G8B8A8_UNORM } 00055a54: 0000: 000022f1 0001a000 t0 write RB_MRT[0].BUF_INFO (20a5) RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB4_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE4_3 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 256 } RB_MRT[0].BASE: 0x166000 RB_MRT[0].CONTROL3: { STRIDE = 0 } 00055a5c: 0000: 000220a5 000400da 00166000 00000000 t3 opcode: CP_LOAD_STATE4 (30) (11 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_TEX | NUM_UNIT = 1 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } { TILED | SWIZ_X = A4XX_TEX_X | SWIZ_Y = A4XX_TEX_Y | SWIZ_Z = A4XX_TEX_Z | SWIZ_W = A4XX_TEX_W | MIPLVLS = 0 | FMT = TFMT4_8_8_8_8_UNORM | TYPE = A4XX_TEX_2D | 0x2 } { HEIGHT = 64 | WIDTH = 64 } { PITCHALIGN = 0 | PITCH = 256 | SWAP = WZYX } { LAYERSZ = 0 | DEPTH = 1 | 0x20000 } { LAYERSZ = 4096 | BASE = 0x4f000 } { 5 = 0 } { 6 = 0 } { 7 = 0 } 00055a78: 0000: 27006883 00200040 00020000 00060000 0004f001 00000000 00000000 00000000 00055a6c: 0000: c0093000 00500000 00000001 27006883 00200040 00020000 00060000 0004f001 * t0 write VPC_VARYING_PS_REPL[0].MODE (214a) VPC_VARYING_PS_REPL[0].MODE: 0x99999999 00055a98: 0000: 0000214a 99999999 t0 write GRAS_SC_SCREEN_SCISSOR_TL (207c) GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } 00055aa0: 0000: 0001207c 00000000 003f003f t0 write GRAS_SC_WINDOW_SCISSOR_BR (209c) GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 00055aac: 0000: 0001209c 003f003f 00000000 t0 write RB_FRAME_BUFFER_DIMENSION (0ce0) RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } 00055ab8: 0000: 00000ce0 00400040 t0 write 0xce1 (0ce1) 0xce1: 00000000 00055ac0: 0000: 00000ce1 00000000 t0 write RB_RENDER_CONTROL2 (20a3) RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 | IJ_PERSP_PIXEL } 00055ac8: 0000: 000020a3 00001000 t0 write RB_MODE_CONTROL (20a0) RB_MODE_CONTROL: { WIDTH = 0 | HEIGHT = 0 | 0xc00000 } 00055ad0: 0000: 000020a0 00c00000 t3 opcode: CP_LOAD_STATE4 (30) (11 dwords) { DST_OFF = 8 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } 00055ae4: 0.000000 0.000000 0.000000 0.000000 64.000000 64.000000 64.000000 64.000000 00055ae4: 0000: 00000000 00000000 00000000 00000000 42800000 42800000 42800000 42800000 00055ad8: 0000: c0093000 00a00008 00000001 00000000 00000000 00000000 00000000 42800000 00055af8: 0020: 42800000 42800000 42800000 t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x80000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 2 } draw[69] register values + 00000004 UNKNOWN_0CC5: 0x4 + 00000000 UNKNOWN_0CC6: 0 + 00400040 RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } + 00000000 0xce1: 00000000 + 00000002 HLSQ_MODE_CONTROL: 0x2 + 00000000 UNKNOWN_0E42: 0 + 00000004 SP_MODE_CONTROL: 0x4 + 00000068 TPL1_TP_MODE_CONTROL: 0x68 + 00188000 GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } + 00000000 UNKNOWN_2001: 0 + 00000001 GRAS_CNTL: { IJ_PERSP } !+ 00000000 GRAS_ALPHA_CONTROL: { 0 } + 00000000 GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } !+ 00000000 GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 0 | RASTER_MODE = 0 } + 00000000 GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } + 003f003f GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } + 003f003f GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } + 00000000 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } !+ 00c00000 RB_MODE_CONTROL: { WIDTH = 0 | HEIGHT = 0 | 0xc00000 } !+ 00000000 RB_RENDER_CONTROL: { 0 } !+ 00000000 RB_MSAA_CONTROL: { SAMPLES = 0 } !+ 00001000 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 | IJ_PERSP_PIXEL } !+ 0f000000 RB_MRT[0].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0xf } !+ 000400da RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB4_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE4_3 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 256 } !+ 00166000 RB_MRT[0].BASE: 0x166000 !+ 00000000 RB_MRT[0].CONTROL3: { STRIDE = 0 } + 00000000 RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } + 0f000000 RB_MRT[0x1].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0xf } + 00000e00 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } !+ ffff0000 RB_FS_OUTPUT: { ENABLE_BLEND = 0 | SAMPLE_MASK = 0xffff } + 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } + 00000001 RB_FS_OUTPUT_REG: { MRT = 1 } + 00000000 RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } + 00000000 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } !+ 42001008 VPC_ATTR: { TOTALATTR = 8 | THRDASSIGN = 1 | ENABLE | 0x40000000 } !+ 00060800 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 8 | NUMNONPOSVSVAR = 6 } !+ 0000e000 VPC_VARYING_INTERP[0].MODE: 0xe000 !+ 99999999 VPC_VARYING_PS_REPL[0].MODE: 0x99999999 + 00000000 UNKNOWN_2152: 0 + 00000000 UNKNOWN_2153: 0 + 00000000 UNKNOWN_2154: 0 + 00000000 UNKNOWN_2155: 0 + 00000000 UNKNOWN_2156: 0 + 0000001d UNKNOWN_21C3: 0x1d + 00000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 } + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + 00000000 PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } + 00000001 UNKNOWN_21E6: 0x1 + 000a0000 VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } + fc030000 VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } + fcfcfcfc VFD_CONTROL_2: 0xfcfcfcfc + fcfcfc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } + 0000fcfc VFD_CONTROL_4: 0xfcfc + 00000000 VFD_INDEX_OFFSET: 0 + 00000000 UNKNOWN_2209: 0 + 00060010 SP_SP_CTRL_REG: { 0x60010 } + 000005c3 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } + 00200c10 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } + 01000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } !+ 0020fc03 SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 2 } !+ 06071e03 SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r1.w | B_COMPMASK = 0x3 } + 00000000 SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00fcfc00 UNKNOWN_22D7: 0xfcfc00 !+ 00000c08 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 12 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } + 00000001 SP_VS_OBJ_START: 0x1 + 00000002 SP_VS_LENGTH_REG: 2 !+ 00700402 SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 0 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE | PIXLODENABLE } !+ 8010003e SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 } !+ 40420000 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 } !+ 00000001 SP_FS_OBJ_START: 0x1 + 00000001 SP_FS_LENGTH_REG: 1 !+ 00000001 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r0.x | SAMPLEMASK_REGID = r0.x } !+ 0001a000 SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = RB4_R8G8B8A8_UNORM } + 00000000 TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } !+ 00000000 0x2382: 00000000 + 00000003 TPL1_TP_FS_TEX_COUNT: 0x3 + 080004f0 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } + fcfc0120 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } + 27f3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } + fcfcfc00 HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } !+ 00fcfcfc HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } + 02010042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } !+ 0141423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 1 } + 00404200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00004200 HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } + 00000007 HLSQ_UPDATE_CONTROL: 0x7 00055b04: 0000: c0023800 00080888 00000001 00000002 t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = CACHE_FLUSH } event CACHE_FLUSH 00055b14: 0000: c0004600 00000006 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00055b1c: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0x8000012 00055b24: 0000: 00000cc6 08000012 00173000: 0000: c0013f00 000555d8 00000155 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 0017300c: 0000: c0014300 00040000 00000000 t3 opcode: (null) (1d) (2 dwords) 00173018: 0000: c0001d00 00000000 ############################################################ vertices: 0 ############################################################ cmdstream: 48 dwords t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 0016b000: 0000: c0002600 00000000 t0 write UCHE_INVALIDATE0 (0e8a) UCHE_INVALIDATE0: 0 UCHE_INVALIDATE1: 0x12 0016b008: 0000: 00010e8a 00000000 00000012 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 0016b014: 0000: c0002600 00000000 t0 write RB_MODE_CONTROL (20a0) RB_MODE_CONTROL: { WIDTH = 64 | HEIGHT = 64 | ENABLE_GMEM } 0016b01c: 0000: 000020a0 00010202 t0 write RB_FRAME_BUFFER_DIMENSION (0ce0) RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } 0016b024: 0000: 00000ce0 00400040 t0 write 0xce1 (0ce1) 0xce1: 00000001 0016b02c: 0000: 00000ce1 00000001 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 0016b034: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0 0016b03c: 0000: 00000cc6 00000000 t3 opcode: (null) (1d) (2 dwords) 0016b044: 0000: c0001d00 00000000 t0 write GRAS_SC_WINDOW_SCISSOR_BR (209c) GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 0016b04c: 0000: 0001209c 003f003f 00000000 t0 write RB_BIN_OFFSET (210d) RB_BIN_OFFSET: { X = 0 | Y = 0 } 0016b058: 0000: 0000210d 00000000 t0 write GRAS_SC_WINDOW_SCISSOR_BR (209c) GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 0016b060: 0000: 0001209c 003f003f 00000000 t0 write UNKNOWN_2157 (2157) UNKNOWN_2157: 0x1 0016b06c: 0000: 00002157 00000001 t3 opcode: (null) (64) (2 dwords) 0016b074: 0000: c0006400 00000001 t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:00054994 ibsize:000000f6 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00054994: 0000: c0002600 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x4 0005499c: 0000: 00000ec3 00000004 t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x68 000549a4: 0000: 00000f03 00000068 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 000549ac: 0000: c0002600 00000000 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } 000549b4: 0000: 000023c0 080004f0 t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = 0x1d } event (null) 000549bc: 0000: c0004600 0000001d t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = FACENESS_FLUSH } event FACENESS_FLUSH 000549c4: 0000: c0004600 0000001c t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 000549cc: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0 000549d4: 0000: 00000cc6 00000000 t0 write UNKNOWN_0E42 (0e42) UNKNOWN_0E42: 0 000549dc: 0000: 00000e42 00000000 t0 write HLSQ_MODE_CONTROL (0e05) HLSQ_MODE_CONTROL: 0x2 000549e4: 0000: 00000e05 00000002 t0 write UNKNOWN_0CC5 (0cc5) UNKNOWN_0CC5: 0x4 000549ec: 0000: 00000cc5 00000004 t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x7 000549f4: 0000: 000023db 00000007 t0 write VFD_CONTROL_2 (2202) VFD_CONTROL_2: 0xfcfcfcfc 000549fc: 0000: 00002202 fcfcfcfc t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } 00054a04: 0000: 00002203 fcfcfc00 t0 write VFD_CONTROL_4 (2204) VFD_CONTROL_4: 0xfcfc 00054a0c: 0000: 00002204 0000fcfc t0 write VFD_INDEX_OFFSET (2208) VFD_INDEX_OFFSET: 0 00054a14: 0000: 00002208 00000000 t0 write UNKNOWN_2209 (2209) UNKNOWN_2209: 0 00054a1c: 0000: 00002209 00000000 t0 write UNKNOWN_2152 (2152) UNKNOWN_2152: 0 UNKNOWN_2153: 0 00054a24: 0000: 00012152 00000000 00000000 t0 write UNKNOWN_2156 (2156) UNKNOWN_2156: 0 00054a30: 0000: 00002156 00000000 t0 write UNKNOWN_2154 (2154) UNKNOWN_2154: 0 00054a38: 0000: 00002154 00000000 t0 write UNKNOWN_2155 (2155) UNKNOWN_2155: 0 00054a40: 0000: 00002155 00000000 t0 write UNKNOWN_21C3 (21c3) UNKNOWN_21C3: 0x1d 00054a48: 0000: 000021c3 0000001d t0 write PC_PRIM_VTX_CNTL2 (21c5) PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 00054a50: 0000: 000021c5 00000012 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 00054a58: 0000: 000021e5 00000000 t0 write GRAS_SU_MODE_CONTROL (2078) GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } 00054a60: 0000: 00002078 00000000 t0 write UNKNOWN_2001 (2001) UNKNOWN_2001: 0 00054a68: 0000: 00002001 00000000 t0 write GRAS_CNTL (2003) GRAS_CNTL: { IJ_PERSP } 00054a70: 0000: 00002003 00000001 t0 write GRAS_CL_CLIP_CNTL (2000) GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } 00054a78: 0000: 00002000 00188000 t0 write TPL1_TP_TEX_COUNT (2381) TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } 00054a80: 0000: 00002381 00000000 t0 write TPL1_TP_FS_TEX_COUNT (23a0) TPL1_TP_FS_TEX_COUNT: 0x3 00054a88: 0000: 000023a0 00000003 t0 write RB_ALPHA_CONTROL (20f8) RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } 00054a90: 0000: 000020f8 00000e00 t0 write RB_RENDER_COMPONENTS (20fb) RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } 00054a98: 0000: 000020fb 0000000f t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 00054aa0: 0000: c0014300 00040000 00000000 t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } 00054aac: 0000: 00002200 000a0000 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } 00054ab4: 0000: 00002201 fc030000 t0 write SP_INSTR_CACHE_CTRL (22c1) SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } 00054abc: 0000: 000022c1 000005c3 t0 write HLSQ_CONTROL_1_REG (23c1) HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } 00054ac4: 0000: 000023c1 fcfc0120 t0 write HLSQ_CONTROL_2_REG (23c2) HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 00054acc: 0000: 000023c2 27f3f3f0 t0 write HLSQ_VS_CONTROL_REG (23c5) HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } 00054ad4: 0000: 000023c5 02010042 t0 write HLSQ_FS_CONTROL_REG (23c6) HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00054adc: 0000: 000023c6 0041423e t0 write HLSQ_HS_CONTROL_REG (23c7) HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00054ae4: 0000: 000023c7 00404200 t0 write HLSQ_DS_CONTROL_REG (23c8) HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00054aec: 0000: 000023c8 00404200 t0 write HLSQ_GS_CONTROL_REG (23c9) HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00054af4: 0000: 000023c9 00404200 t0 write HLSQ_CS_CONTROL_REG (23ca) HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } 00054afc: 0000: 000023ca 00004200 t0 write SP_SP_CTRL_REG (22c0) SP_SP_CTRL_REG: { 0x60010 } 00054b04: 0000: 000022c0 00060010 t0 write UNKNOWN_21E6 (21e6) UNKNOWN_21E6: 0x1 00054b0c: 0000: 000021e6 00000001 t0 write SP_VS_CTRL_REG0 (22c4) SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 00054b14: 0000: 000022c4 00200c10 t0 write SP_VS_CTRL_REG1 (22c5) SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } 00054b1c: 0000: 000022c5 01000042 t0 write VPC_ATTR (2140) VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | 0x40000000 } 00054b24: 0000: 00002140 40001004 t0 write VPC_PACK (2141) VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } 00054b2c: 0000: 00002141 00040400 t0 write PC_PRIM_VTX_CNTL (21c4) PC_PRIM_VTX_CNTL: { VAROUT = 1 } 00054b34: 0000: 000021c4 00000001 t0 write SP_VS_PARAM_REG (22c6) SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } UNKNOWN_22D7: 0xfcfc00 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 00054b3c: 0000: 001922c6 0010fc03 00001e03 00000000 00000000 00000000 00000000 00000000 * 00054b7c: 0040: 00000000 00000000 00fcfc00 00000008 00000000 00000000 00000000 00000000 * t0 write SP_VS_OBJ_OFFSET_REG (22e0) SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 00054ba8: 0000: 000022e0 00000000 t0 write SP_VS_OBJ_START (22e1) SP_VS_OBJ_START: 0x1 00054bb0: 0000: 000022e1 00000001 t0 write SP_VS_LENGTH_REG (22e5) SP_VS_LENGTH_REG: 2 00054bb8: 0000: 000022e5 00000002 t3 opcode: CP_LOAD_STATE4 (30) (67 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } :2:0000:0000[56d81803x_20020003x] (sy)(ss)(nop3) shl.b r0.w, r0.w, 2 :1:0001:0004[20150000x_00000003x] cov.s32s16 hr0.x, r0.w :0:0002:0005[00000200x_00000000x] (rpt2)nop :1:0003:0008[201100f4x_00000000x] mova a0.x, hr0.x :0:0004:0009[00000500x_00000000x] (rpt5)nop :1:0005:0015[20154003x_00000c20x] mov.s32s32 r0.w, c :1:0006:0016[20154004x_00000c21x] mov.s32s32 r1.x, c :1:0007:0017[20154005x_00000c22x] mov.s32s32 r1.y, c :1:0008:0018[20156006x_00000c23x] (ul)mov.s32s32 r1.z, c :0:0009:0019[03000000x_00000000x] end :2:0010:0020[46f00007x_20050000x] shr.b r1.w, r0.x, 5 :2:0011:0021[43980008x_201f0000x] (nop2) and.b r2.x, r0.x, 31 :2:0012:0024[43980807x_201f0007x] (nop3) and.b r1.w, r1.w, 31 :2:0013:0028[46100807x_20100007x] (nop1) mul.u24 r1.w, r1.w, 16 :3:0014:0030[62040007x_00071014x] mad.u24 r1.w, c5.x, r2.x, r1.w :0:0015:0031[00000500x_00000000x] (rpt5)nop :6:0016:0037[c2c60f00x_04800006x] stlw.u32 l[r1.w], r0.w, 4 :0:0017:0038[04800000x_00000000x] chmask :0:0018:0039[05000000x_00000000x] chsh Stats: - shaderdb: 40 instr, 24 nops, 16 non-nops, 5 mov, 1 cov - shaderdb: 0 last-baryf, 0 half, 2 full, 5 constlen - shaderdb: 27 cat0, 6 cat1, 5 cat2, 1 cat3, 0 cat4, 0 cat5, 1 cat6, 0 cat7 - shaderdb: 0 sstall, 1 (ss), 1 (sy) 00054bc0: 0000: c0413000 00a00000 00000000 20020003 56d81803 00000003 20150000 00000000 00054be0: 0020: 00000200 00000000 201100f4 00000000 00000500 00000c20 20154003 00000c21 00054c00: 0040: 20154004 00000c22 20154005 00000c23 20156006 00000000 03000000 20050000 00054c20: 0060: 46f00007 201f0000 43980008 201f0007 43980807 20100007 46100807 00071014 00054c40: 0080: 62040007 00000000 00000500 04800006 c2c60f00 00000000 04800000 00000000 00054c60: 00a0: 05000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 * t0 write GRAS_ALPHA_CONTROL (2073) GRAS_ALPHA_CONTROL: { 0x2 } 00054ccc: 0000: 00002073 00000002 t0 write GRAS_SC_CONTROL (207b) GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = 4 | MSAA_DISABLE | RASTER_MODE = 0 } 00054cd4: 0000: 0000207b 00000a08 t0 write RB_MSAA_CONTROL (20a2) RB_MSAA_CONTROL: { DISABLE | SAMPLES = 4 } 00054cdc: 0000: 000020a2 00009000 t0 write RB_RENDER_CONTROL (20a1) RB_RENDER_CONTROL: { DISABLE_COLOR_PIPE | 0x2 } 00054ce4: 0000: 000020a1 00000022 t0 write RB_CLEAR_COLOR_DW0 (20cc) RB_CLEAR_COLOR_DW0: 0xff000000 RB_CLEAR_COLOR_DW1: 0 RB_CLEAR_COLOR_DW2: 0 RB_CLEAR_COLOR_DW3: 0 00054cec: 0000: 000320cc ff000000 00000000 00000000 00000000 t0 write RB_COPY_CONTROL (20fc) RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_FOUR | MODE = RB_COPY_CLEAR | FASTCLEAR = 0xf | GMEM_BASE = 0 } RB_COPY_DEST_BASE: { BASE = 0x4f000 } RB_COPY_DEST_PITCH: { PITCH = 256 } RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_IF_ALPHA_OFF | COMPONENT_ENABLE = 0 | ENDIAN = ENDIAN_NONE | TILE = TILE4_3 } 00054d00: 0000: 000320fc 00000f22 0004f000 00000008 03000868 t0 write GRAS_SC_SCREEN_SCISSOR_TL (207c) GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } 00054d14: 0000: 0001207c 00000000 003f003f t0 write RB_FRAME_BUFFER_DIMENSION (0ce0) RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } 00054d20: 0000: 00000ce0 00400040 t0 write 0xce1 (0ce1) 0xce1: 00000000 00054d28: 0000: 00000ce1 00000000 t3 opcode: CP_LOAD_STATE4 (30) (11 dwords) { DST_OFF = 8 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } 00054d3c: 0.000000 0.000000 1.000000 1.000000 64.000000 64.000000 1.000000 1.000000 00054d3c: 0000: 00000000 00000000 3f800000 3f800000 42800000 42800000 3f800000 3f800000 00054d30: 0000: c0093000 00a00008 00000001 00000000 00000000 3f800000 3f800000 42800000 00054d50: 0020: 42800000 3f800000 3f800000 t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x80000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 2 } draw[70] register values + 00000004 UNKNOWN_0CC5: 0x4 + 00000000 UNKNOWN_0CC6: 0 + 00400040 RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } + 00000000 0xce1: 00000000 + 00000002 HLSQ_MODE_CONTROL: 0x2 + 00000000 UNKNOWN_0E42: 0 + 00000000 UCHE_INVALIDATE0: 0 + 00000012 UCHE_INVALIDATE1: 0x12 + 00000004 SP_MODE_CONTROL: 0x4 + 00000068 TPL1_TP_MODE_CONTROL: 0x68 + 00188000 GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } + 00000000 UNKNOWN_2001: 0 + 00000001 GRAS_CNTL: { IJ_PERSP } !+ 00000002 GRAS_ALPHA_CONTROL: { 0x2 } + 00000000 GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } !+ 00000a08 GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = 4 | MSAA_DISABLE | RASTER_MODE = 0 } + 00000000 GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } + 003f003f GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } + 003f003f GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } + 00000000 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } !+ 00010202 RB_MODE_CONTROL: { WIDTH = 64 | HEIGHT = 64 | ENABLE_GMEM } !+ 00000022 RB_RENDER_CONTROL: { DISABLE_COLOR_PIPE | 0x2 } !+ 00009000 RB_MSAA_CONTROL: { DISABLE | SAMPLES = 4 } + ff000000 RB_CLEAR_COLOR_DW0: 0xff000000 + 00000000 RB_CLEAR_COLOR_DW1: 0 + 00000000 RB_CLEAR_COLOR_DW2: 0 + 00000000 RB_CLEAR_COLOR_DW3: 0 + 00000e00 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } + 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } !+ 00000f22 RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_FOUR | MODE = RB_COPY_CLEAR | FASTCLEAR = 0xf | GMEM_BASE = 0 } + 0004f000 RB_COPY_DEST_BASE: { BASE = 0x4f000 } + 00000008 RB_COPY_DEST_PITCH: { PITCH = 256 } !+ 03000868 RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_IF_ALPHA_OFF | COMPONENT_ENABLE = 0 | ENDIAN = ENDIAN_NONE | TILE = TILE4_3 } + 00000000 RB_BIN_OFFSET: { X = 0 | Y = 0 } !+ 40001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | 0x40000000 } !+ 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } + 00000000 UNKNOWN_2152: 0 + 00000000 UNKNOWN_2153: 0 + 00000000 UNKNOWN_2154: 0 + 00000000 UNKNOWN_2155: 0 + 00000000 UNKNOWN_2156: 0 + 00000001 UNKNOWN_2157: 0x1 + 0000001d UNKNOWN_21C3: 0x1d + 00000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 } + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + 00000000 PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } + 00000001 UNKNOWN_21E6: 0x1 + 000a0000 VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } + fc030000 VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } + fcfcfcfc VFD_CONTROL_2: 0xfcfcfcfc + fcfcfc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } + 0000fcfc VFD_CONTROL_4: 0xfcfc + 00000000 VFD_INDEX_OFFSET: 0 + 00000000 UNKNOWN_2209: 0 + 00060010 SP_SP_CTRL_REG: { 0x60010 } + 000005c3 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } + 00200c10 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } + 01000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } !+ 0010fc03 SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } !+ 00001e03 SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00fcfc00 UNKNOWN_22D7: 0xfcfc00 !+ 00000008 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } + 00000001 SP_VS_OBJ_START: 0x1 + 00000002 SP_VS_LENGTH_REG: 2 + 00000000 TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } + 00000003 TPL1_TP_FS_TEX_COUNT: 0x3 + 080004f0 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } + fcfc0120 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } + 27f3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } + 02010042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } !+ 0041423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00004200 HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } + 00000007 HLSQ_UPDATE_CONTROL: 0x7 00054d5c: 0000: c0023800 00080888 00000001 00000002 0016b07c: 0000: c0013f00 00054994 000000f6 t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:00054d6c ibsize:00000037 t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } 00054d6c: 0000: 00002200 082a0008 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00054d74: 0000: c0002600 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x1e 00054d7c: 0000: 00000ec3 0000001e t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x28 00054d84: 0000: 00000f03 00000028 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00054d8c: 0000: c0002600 00000000 t0 write HLSQ_MODE_CONTROL (0e05) HLSQ_MODE_CONTROL: 0x1 00054d94: 0000: 00000e05 00000001 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0x600a0 } 00054d9c: 0000: 000023c0 080604f0 t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x7 00054da4: 0000: 000023db 00000007 t0 write PC_RESTART_INDEX (21c6) PC_RESTART_INDEX: 0xffffffff 00054dac: 0000: 000021c6 ffffffff t0 write UNKNOWN_21E6 (21e6) UNKNOWN_21E6: 0x1 00054db4: 0000: 000021e6 00000001 t0 write UNKNOWN_21C3 (21c3) UNKNOWN_21C3: 0x1f 00054dbc: 0000: 000021c3 0000001f t0 write TPL1_TP_TEX_OFFSET (2380) TPL1_TP_TEX_OFFSET: 0x808 00054dc4: 0000: 00002380 00000808 t0 write GRAS_SU_POINT_MINMAX (2070) GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 4092.000000 } GRAS_SU_POINT_SIZE: 0.500000 00054dcc: 0000: 00012070 ffc00010 00000008 t0 write UNKNOWN_2152 (2152) UNKNOWN_2152: 0 UNKNOWN_2153: 0 00054dd8: 0000: 00012152 00000000 00000000 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00054de4: 0000: c0002600 00000000 t0 write UNKNOWN_0CC5 (0cc5) UNKNOWN_0CC5: 0x4 00054dec: 0000: 00000cc5 00000004 t0 write 0xcc4 (0cc4) 0xcc4: 00000000 00054df4: 0000: 00000cc4 00000000 t0 write 0xd03 (0d03) 0xd03: 80200000 00054dfc: 0000: 00000d03 80200000 t0 write UNKNOWN_0EC2 (0ec2) UNKNOWN_0EC2: 0x40000 00054e04: 0000: 00000ec2 00040000 t0 write VPC_DEBUG_ECO_CONTROL (0e64) VPC_DEBUG_ECO_CONTROL: 0x100 00054e0c: 0000: 00000e64 00000100 t0 write UNKNOWN_0E42 (0e42) UNKNOWN_0E42: 0 00054e14: 0000: 00000e42 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x1e 00054e1c: 0000: 00000ec3 0000001e t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x28 00054e24: 0000: 00000f03 00000028 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 00054e2c: 0000: c0014300 00040000 00000000 t0 write VFD_INDEX_OFFSET (2208) VFD_INDEX_OFFSET: 0 00054e38: 0000: 00002208 00000000 t0 write UNKNOWN_2209 (2209) UNKNOWN_2209: 0 00054e40: 0000: 00002209 00000000 0016b088: 0000: c0013f00 00054d6c 00000037 t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:00055328 ibsize:000000ac t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x3 00055328: 0000: 000023db 00000003 t0 write SP_INSTR_CACHE_CTRL (22c1) SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } 00055330: 0000: 000022c1 000005c3 t0 write HLSQ_CONTROL_1_REG (23c1) HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x1008 } 00055338: 0000: 000023c1 fcfc1108 t0 write HLSQ_CONTROL_2_REG (23c2) HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 00055340: 0000: 000023c2 fff3f3f0 t0 write HLSQ_VS_CONTROL_REG (23c5) HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 2 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 1 } 00055348: 0000: 000023c5 01010002 t0 write HLSQ_HS_CONTROL_REG (23c7) HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 00055350: 0000: 000023c7 007e0200 t0 write HLSQ_DS_CONTROL_REG (23c8) HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 00055358: 0000: 000023c8 007e0200 t0 write HLSQ_GS_CONTROL_REG (23c9) HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 00055360: 0000: 000023c9 007e0200 t0 write HLSQ_FS_CONTROL_REG (23c6) HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 2 | CONSTOBJECTOFFSET = 2 | ENABLED | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 } 00055368: 0000: 000023c6 017f0202 t0 write SP_VS_OBJ_OFFSET_REG (22e0) SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 00055370: 0000: 000022e0 00000000 t0 write SP_HS_OBJ_OFFSET_REG (230d) SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } 00055378: 0000: 0000230d 7e020000 t0 write SP_DS_OBJ_OFFSET_REG (2334) SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } 00055380: 0000: 00002334 7e020000 t0 write SP_GS_OBJ_OFFSET_REG (235b) SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } 00055388: 0000: 0000235b 7e020000 t0 write SP_FS_OBJ_OFFSET_REG (22ea) SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } 00055390: 0000: 000022ea 7e020000 t0 write SP_VS_OBJ_START (22e1) SP_VS_OBJ_START: 0x49000 00049000: 0000: 00000000 13000000 00000000 00000000 00000000 00000000 00000000 00000000 * :0:0000:0000[13000000x_00000000x] (sy)end :0:0001:0001[00000000x_00000000x] nop :0:0002:0002[00000000x_00000000x] nop :0:0003:0003[00000000x_00000000x] nop :0:0004:0004[00000000x_00000000x] nop Stats: - shaderdb: 5 instr, 4 nops, 1 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 0 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 0 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) 00055398: 0000: 000022e1 00049000 t0 write SP_HS_OBJ_START (230e) SP_HS_OBJ_START: 0 000553a0: 0000: 0000230e 00000000 t0 write SP_DS_OBJ_START (2335) SP_DS_OBJ_START: 0 000553a8: 0000: 00002335 00000000 t0 write SP_GS_OBJ_START (235c) SP_GS_OBJ_START: 0 000553b0: 0000: 0000235c 00000000 t0 write SP_VS_LENGTH_REG (22e5) SP_VS_LENGTH_REG: 1 000553b8: 0000: 000022e5 00000001 t3 opcode: CP_LOAD_STATE4 (30) (3 dwords) { DST_OFF = 0 | STATE_SRC = SS4_INDIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 1 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0x49000 } :0:0000:0000[13000000x_00000000x] (sy)end :0:0001:0001[00000000x_00000000x] nop :0:0002:0002[00000000x_00000000x] nop :0:0003:0003[00000000x_00000000x] nop :0:0004:0004[00000000x_00000000x] nop Stats: - shaderdb: 5 instr, 4 nops, 1 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 0 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 0 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) 000553c0: 0000: c0013000 00620000 00049000 t0 write 0x2072 (2072) 0x2072: 00000000 000553cc: 0000: 00002072 00000000 t0 write UNKNOWN_2155 (2155) UNKNOWN_2155: 0 000553d4: 0000: 00002155 00000000 t0 write GRAS_CNTL (2003) GRAS_CNTL: { IJ_PERSP } 000553dc: 0000: 00002003 00000001 t0 write VPC_VARYING_INTERP[0].MODE (2142) VPC_VARYING_INTERP[0].MODE: 0 000553e4: 0000: 00002142 00000000 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0x600a0 } 000553ec: 0000: 000023c0 080604f0 t0 write HLSQ_CONTROL_3_REG (23c3) HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } 000553f4: 0000: 000023c3 fcfcfc00 t0 write HLSQ_CONTROL_4_REG (23c4) HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r0.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } 000553fc: 0000: 000023c4 00fcfc00 t0 write SP_FS_CTRL_REG0 (22e8) SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE } SP_FS_CTRL_REG1: { CONSTLENGTH = 2 | VARYING | 0x80000000 } 00055404: 0000: 000122e8 00340412 80100002 t0 write SP_FS_OBJ_START (22eb) SP_FS_OBJ_START: 0x46000 00046000: 0000: 00002000 5730cb00 00000000 03000000 00000000 00000000 00000000 00000000 * :2:0000:0000[5730cb00x_00002000x] (sy)(rpt3)bary.f (ei)hr0.x, (r)0, r0.x :0:0001:0004[03000000x_00000000x] end :0:0002:0005[00000000x_00000000x] nop :0:0003:0006[00000000x_00000000x] nop :0:0004:0007[00000000x_00000000x] nop :0:0005:0008[00000000x_00000000x] nop Stats: - shaderdb: 9 instr, 4 nops, 5 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 1 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 4 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) 00055410: 0000: 000022eb 00046000 t0 write SP_FS_LENGTH_REG (22ef) SP_FS_LENGTH_REG: 1 00055418: 0000: 000022ef 00000001 t0 write RB_RENDER_COMPONENTS (20fb) RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } 00055420: 0000: 000020fb 0000000f t3 opcode: CP_LOAD_STATE4 (30) (3 dwords) { DST_OFF = 0 | STATE_SRC = SS4_INDIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 1 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0x46000 } :2:0000:0000[5730cb00x_00002000x] (sy)(rpt3)bary.f (ei)hr0.x, (r)0, r0.x :0:0001:0004[03000000x_00000000x] end :0:0002:0005[00000000x_00000000x] nop :0:0003:0006[00000000x_00000000x] nop :0:0004:0007[00000000x_00000000x] nop :0:0005:0008[00000000x_00000000x] nop Stats: - shaderdb: 9 instr, 4 nops, 5 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 1 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 4 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) 00055428: 0000: c0013000 00720000 00046000 t0 write SP_SP_CTRL_REG (22c0) SP_SP_CTRL_REG: { 0x60010 } 00055434: 0000: 000022c0 00060010 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 28 | GROUP_ID = 3 } { ADDR_LO = 0x9c240 } 0005543c: 0000: c0014300 0300001c 0009c240 t0 write RB_DEPTH_INFO (2103) RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTH4_NONE | DEPTH_BASE = 0 } RB_DEPTH_PITCH: 0 RB_DEPTH_PITCH2: 0 00055448: 0000: 00022103 00000000 00000000 00000000 t0 write GRAS_DEPTH_CONTROL (2077) GRAS_DEPTH_CONTROL: { FORMAT = DEPTH4_NONE } 00055458: 0000: 00002077 00000000 t0 write RB_STENCIL_INFO (2108) RB_STENCIL_INFO: { STENCIL_BASE = 0 } RB_STENCIL_PITCH: 0 0x210a: 00000000 00055460: 0000: 00022108 00000000 00000000 00000000 t0 write 0x2002 (2002) 0x2002: 00000000 00055470: 0000: 00002002 00000000 t0 write RB_ALPHA_CONTROL (20f8) RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } 00055478: 0000: 000020f8 00000e00 t0 write RB_MRT[0].CONTROL (20a4) RB_MRT[0].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0x7 } 00055480: 0000: 000020a4 07000c00 t0 write RB_MRT[0].BLEND_CONTROL (20a8) RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } 00055488: 0000: 000020a8 00000000 t0 write GRAS_CL_CLIP_CNTL (2000) GRAS_CL_CLIP_CNTL: { 0x80000 } 00055490: 0000: 00002000 00080000 t0 write GRAS_SU_POLY_OFFSET_SCALE (2074) GRAS_SU_POLY_OFFSET_SCALE: 0.000000 GRAS_SU_POLY_OFFSET_OFFSET: 0.000000 GRAS_SU_POLY_OFFSET_CLAMP: 0.000000 00055498: 0000: 00022074 00000000 00000000 00000000 t0 write GRAS_SU_MODE_CONTROL (2078) GRAS_SU_MODE_CONTROL: { FRONT_CW | LINEHALFWIDTH = 0.500000 | MSAA_ENABLE | RENDERING_PASS } 000554a8: 0000: 00002078 00102014 t0 write GRAS_SC_SCREEN_SCISSOR_TL (207c) GRAS_SC_SCREEN_SCISSOR_TL: { X = 2 | Y = 13 } GRAS_SC_SCREEN_SCISSOR_BR: { X = 33 | Y = 44 } 000554b0: 0000: 0001207c 000d0002 002c0021 t0 write GRAS_CL_VPORT_XOFFSET_0 (2008) GRAS_CL_VPORT_XOFFSET_0: 18.000000 GRAS_CL_VPORT_XSCALE_0: 16.000000 GRAS_CL_VPORT_YOFFSET_0: 29.000000 GRAS_CL_VPORT_YSCALE_0: 16.000000 GRAS_CL_VPORT_ZOFFSET_0: 0.500000 GRAS_CL_VPORT_ZSCALE_0: 0.500000 000554bc: 0000: 00052008 41900000 41800000 41e80000 41800000 3f000000 3f000000 t0 write GRAS_CL_GB_CLIP_ADJ (2004) GRAS_CL_GB_CLIP_ADJ: { HORZ = 511 | VERT = 511 } 000554d8: 0000: 00002004 0007fdff t0 write GRAS_SC_CONTROL (207b) GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 4 | RASTER_MODE = 0 } 000554e0: 0000: 0000207b 00000200 t0 write 0x2382 (2382) 0x2382: 00000002 000554e8: 0000: 00002382 00000002 t0 write RB_MSAA_CONTROL (20a2) RB_MSAA_CONTROL: { SAMPLES = 4 } 000554f0: 0000: 000020a2 00008000 t0 write RB_RENDER_CONTROL2 (20a3) RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 4 | IJ_PERSP_PIXEL } 000554f8: 0000: 000020a3 00001200 t0 write RB_MRT[0].BUF_INFO (20a5) RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB4_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_ALWAYS | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 1024 } RB_MRT[0].BASE: 0 RB_MRT[0].CONTROL3: { STRIDE = 64 } 00055500: 0000: 000220a5 0010029a 00000000 00000200 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 43 | GROUP_ID = 2 } { ADDR_LO = 0x9c2b0 } 00055510: 0000: c0014300 0200002b 0009c2b0 t0 write 0x215c (215c) 0x215c: 00000000 0x215d: 00000000 0005551c: 0000: 0001215c 00000000 00000000 t0 write 0x215f (215f) 0x215f: 00000000 00055528: 0000: 0000215f 00000000 t0 write 0x215e (215e) 0x215e: 00000000 00055530: 0000: 0000215e 00000000 t0 write 0x2161 (2161) 0x2161: 00000000 0x2162: 00000000 00055538: 0000: 00012161 00000000 00000000 t0 write 0x2164 (2164) 0x2164: 00000000 00055544: 0000: 00002164 00000000 t0 write 0x2163 (2163) 0x2163: 00000000 0005554c: 0000: 00002163 00000000 t0 write 0x2166 (2166) 0x2166: 00000000 0x2167: 00000000 00055554: 0000: 00012166 00000000 00000000 t0 write 0x2169 (2169) 0x2169: 00000000 00055560: 0000: 00002169 00000000 t0 write 0x2168 (2168) 0x2168: 00000000 00055568: 0000: 00002168 00000000 t0 write 0x216b (216b) 0x216b: 00000000 0x216c: 00000000 00055570: 0000: 0001216b 00000000 00000000 t0 write VPC_SO_FLUSH_WADDR_3 (216e) VPC_SO_FLUSH_WADDR_3: 0 0005557c: 0000: 0000216e 00000000 t0 write 0x216d (216d) 0x216d: 00000000 00055584: 0000: 0000216d 00000000 t0 write UNKNOWN_2156 (2156) UNKNOWN_2156: 0 0005558c: 0000: 00002156 00000000 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 18 | GROUP_ID = 1 } { ADDR_LO = 0x9c360 } 00055594: 0000: c0014300 01000012 0009c360 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 15 | GROUP_ID = 0 } { ADDR_LO = 0x9c3b0 } 000555a0: 0000: c0014300 0000000f 0009c3b0 group_id: 0 count: 15 addr: 000000000009c3b0 flags: 0 0009c3b0: 0000: 00002073 00000000 00002101 00000000 00002106 00000000 000021e5 00000000 0009c3d0: 0020: 0001210b 00000000 00000000 00002381 00000000 000023a0 00000000 t0 write GRAS_ALPHA_CONTROL (2073) GRAS_ALPHA_CONTROL: { 0 } 0009c3b0: 0000: 00002073 00000000 t0 write RB_DEPTH_CONTROL (2101) RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } 0009c3b8: 0000: 00002101 00000000 t0 write RB_STENCIL_CONTROL (2106) RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } 0009c3c0: 0000: 00002106 00000000 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 0009c3c8: 0000: 000021e5 00000000 t0 write RB_STENCILREFMASK (210b) RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 0009c3d0: 0000: 0001210b 00000000 00000000 t0 write TPL1_TP_TEX_COUNT (2381) TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } 0009c3dc: 0000: 00002381 00000000 t0 write TPL1_TP_FS_TEX_COUNT (23a0) TPL1_TP_FS_TEX_COUNT: 0 0009c3e4: 0000: 000023a0 00000000 group_id: 1 count: 18 addr: 000000000009c360 flags: 0 0009c360: 0000: 00002200 082a0008 00002201 fcfc0081 00002203 0000fc00 0007220a 0008080f 0009c380: 0020: 0009c1e0 00000060 00000001 0000080f 0009c210 00000030 00000001 0001228a 0009c3a0: 0040: 7000411f 3000011f t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } 0009c360: 0000: 00002200 082a0008 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } 0009c368: 0000: 00002201 fcfc0081 t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } 0009c370: 0000: 00002203 0000fc00 t0 write VFD_FETCH[0].INSTR_0 (220a) VFD_FETCH[0].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 | SWITCHNEXT } VFD_FETCH[0].INSTR_1: 0x9c1e0 VFD_FETCH[0].INSTR_2: { SIZE = 0x60 } VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 } VFD_FETCH[0x1].INSTR_1: 0x9c210 VFD_FETCH[0x1].INSTR_2: { SIZE = 0x30 } VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } 0009c378: 0000: 0007220a 0008080f 0009c1e0 00000060 00000001 0000080f 0009c210 00000030 0009c398: 0020: 00000001 t0 write VFD_DECODE[0].INSTR (228a) VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID | SWITCHNEXT } VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID } 0009c39c: 0000: 0001228a 7000411f 3000011f group_id: 2 count: 43 addr: 000000000009c2b0 flags: 0 0009c2b0: 0000: 000020a1 00000000 000022f1 0001a100 000022f0 fc00fc01 00002100 00000001 0009c2d0: 0020: 000021e5 00000000 000020f9 ffff0501 0000214a 00000000 00002140 42001004 0009c2f0: 0040: 001922c6 0010fc04 00001e00 00000000 00000000 00000000 00000000 00000000 * 0009c330: 0080: 00000000 00000000 00fcfc00 00000008 00000000 00000000 00000000 00000000 * t0 write RB_RENDER_CONTROL (20a1) RB_RENDER_CONTROL: { 0 } 0009c2b0: 0000: 000020a1 00000000 t0 write SP_FS_MRT[0].REG (22f1) SP_FS_MRT[0].REG: { REGID = r0.x | HALF_PRECISION | MRTFORMAT = RB4_R8G8B8A8_UNORM } 0009c2b8: 0000: 000022f1 0001a100 t0 write SP_FS_OUTPUT_REG (22f0) SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 0009c2c0: 0000: 000022f0 fc00fc01 t0 write RB_FS_OUTPUT_REG (2100) RB_FS_OUTPUT_REG: { MRT = 1 } 0009c2c8: 0000: 00002100 00000001 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 0009c2d0: 0000: 000021e5 00000000 t0 write RB_FS_OUTPUT (20f9) RB_FS_OUTPUT: { ENABLE_BLEND = 0x1 | INDEPENDENT_BLEND | SAMPLE_MASK = 0xffff | 0x400 } 0009c2d8: 0000: 000020f9 ffff0501 t0 write VPC_VARYING_PS_REPL[0].MODE (214a) VPC_VARYING_PS_REPL[0].MODE: 0 0009c2e0: 0000: 0000214a 00000000 t0 write VPC_ATTR (2140) VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 } 0009c2e8: 0000: 00002140 42001004 t0 write SP_VS_PARAM_REG (22c6) SP_VS_PARAM_REG: { POSREGID = r1.x | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } SP_VS_OUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } UNKNOWN_22D7: 0xfcfc00 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 0009c2f0: 0000: 001922c6 0010fc04 00001e00 00000000 00000000 00000000 00000000 00000000 * 0009c330: 0040: 00000000 00000000 00fcfc00 00000008 00000000 00000000 00000000 00000000 * group_id: 3 count: 28 addr: 000000000009c240 flags: 0 0009c240: 0000: 000021c4 02000001 00002141 00040400 00002001 00000000 000022c4 00200800 0009c260: 0020: 000022c5 08000002 0000230c 00000000 00002318 00000000 00002319 00000000 0009c280: 0040: 00002340 00000000 00002202 fcfcfcfc 00002204 0000fcfc 00002154 00000000 0009c2a0: 0060: 000021e7 00000000 000021c5 00000012 t0 write PC_PRIM_VTX_CNTL (21c4) PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } 0009c240: 0000: 000021c4 02000001 t0 write VPC_PACK (2141) VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } 0009c248: 0000: 00002141 00040400 t0 write UNKNOWN_2001 (2001) UNKNOWN_2001: 0 0009c250: 0000: 00002001 00000000 t0 write SP_VS_CTRL_REG0 (22c4) SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 2 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 0009c258: 0000: 000022c4 00200800 t0 write SP_VS_CTRL_REG1 (22c5) SP_VS_CTRL_REG1: { CONSTLENGTH = 2 | INITIALOUTSTANDING = 8 } 0009c260: 0000: 000022c5 08000002 t0 write 0x230c (230c) 0x230c: 00000000 0009c268: 0000: 0000230c 00000000 t0 write 0x2318 (2318) 0x2318: 00000000 0009c270: 0000: 00002318 00000000 t0 write 0x2319 (2319) 0x2319: 00000000 0009c278: 0000: 00002319 00000000 t0 write 0x2340 (2340) 0x2340: 00000000 0009c280: 0000: 00002340 00000000 t0 write VFD_CONTROL_2 (2202) VFD_CONTROL_2: 0xfcfcfcfc 0009c288: 0000: 00002202 fcfcfcfc t0 write VFD_CONTROL_4 (2204) VFD_CONTROL_4: 0xfcfc 0009c290: 0000: 00002204 0000fcfc t0 write UNKNOWN_2154 (2154) UNKNOWN_2154: 0 0009c298: 0000: 00002154 00000000 t0 write PC_HS_PARAM (21e7) PC_HS_PARAM: { VERTICES_OUT = 0 | SPACING = EQUAL_SPACING } 0009c2a0: 0000: 000021e7 00000000 t0 write PC_PRIM_VTX_CNTL2 (21c5) PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 0009c2a8: 0000: 000021c5 00000012 t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = USE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x200000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 3 } draw[71] register values + 00000000 0xcc4: 00000000 + 00000004 UNKNOWN_0CC5: 0x4 + 80200000 0xd03: 80200000 !+ 00000001 HLSQ_MODE_CONTROL: 0x1 + 00000000 UNKNOWN_0E42: 0 + 00000100 VPC_DEBUG_ECO_CONTROL: 0x100 + 00040000 UNKNOWN_0EC2: 0x40000 !+ 0000001e SP_MODE_CONTROL: 0x1e !+ 00000028 TPL1_TP_MODE_CONTROL: 0x28 !+ 00080000 GRAS_CL_CLIP_CNTL: { 0x80000 } + 00000000 UNKNOWN_2001: 0 + 00000000 0x2002: 00000000 + 00000001 GRAS_CNTL: { IJ_PERSP } + 0007fdff GRAS_CL_GB_CLIP_ADJ: { HORZ = 511 | VERT = 511 } + 41900000 GRAS_CL_VPORT_XOFFSET_0: 18.000000 + 41800000 GRAS_CL_VPORT_XSCALE_0: 16.000000 + 41e80000 GRAS_CL_VPORT_YOFFSET_0: 29.000000 + 41800000 GRAS_CL_VPORT_YSCALE_0: 16.000000 + 3f000000 GRAS_CL_VPORT_ZOFFSET_0: 0.500000 + 3f000000 GRAS_CL_VPORT_ZSCALE_0: 0.500000 + ffc00010 GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 4092.000000 } + 00000008 GRAS_SU_POINT_SIZE: 0.500000 + 00000000 0x2072: 00000000 !+ 00000000 GRAS_ALPHA_CONTROL: { 0 } + 00000000 GRAS_SU_POLY_OFFSET_SCALE: 0.000000 + 00000000 GRAS_SU_POLY_OFFSET_OFFSET: 0.000000 + 00000000 GRAS_SU_POLY_OFFSET_CLAMP: 0.000000 + 00000000 GRAS_DEPTH_CONTROL: { FORMAT = DEPTH4_NONE } !+ 00102014 GRAS_SU_MODE_CONTROL: { FRONT_CW | LINEHALFWIDTH = 0.500000 | MSAA_ENABLE | RENDERING_PASS } !+ 00000200 GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 4 | RASTER_MODE = 0 } !+ 000d0002 GRAS_SC_SCREEN_SCISSOR_TL: { X = 2 | Y = 13 } !+ 002c0021 GRAS_SC_SCREEN_SCISSOR_BR: { X = 33 | Y = 44 } !+ 00000000 RB_RENDER_CONTROL: { 0 } !+ 00008000 RB_MSAA_CONTROL: { SAMPLES = 4 } !+ 00001200 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 4 | IJ_PERSP_PIXEL } !+ 07000c00 RB_MRT[0].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0x7 } !+ 0010029a RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB4_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_ALWAYS | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 1024 } !+ 00000000 RB_MRT[0].BASE: 0 !+ 00000200 RB_MRT[0].CONTROL3: { STRIDE = 64 } + 00000000 RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } + 00000e00 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } !+ ffff0501 RB_FS_OUTPUT: { ENABLE_BLEND = 0x1 | INDEPENDENT_BLEND | SAMPLE_MASK = 0xffff | 0x400 } + 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } + 00000001 RB_FS_OUTPUT_REG: { MRT = 1 } + 00000000 RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } + 00000000 RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTH4_NONE | DEPTH_BASE = 0 } + 00000000 RB_DEPTH_PITCH: 0 + 00000000 RB_DEPTH_PITCH2: 0 + 00000000 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } + 00000000 RB_STENCIL_INFO: { STENCIL_BASE = 0 } + 00000000 RB_STENCIL_PITCH: 0 + 00000000 0x210a: 00000000 + 00000000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } + 00000000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } !+ 42001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 } + 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } !+ 00000000 VPC_VARYING_INTERP[0].MODE: 0 !+ 00000000 VPC_VARYING_PS_REPL[0].MODE: 0 + 00000000 UNKNOWN_2152: 0 + 00000000 UNKNOWN_2153: 0 + 00000000 UNKNOWN_2154: 0 + 00000000 UNKNOWN_2155: 0 + 00000000 UNKNOWN_2156: 0 + 00000000 0x215c: 00000000 + 00000000 0x215d: 00000000 + 00000000 0x215e: 00000000 + 00000000 0x215f: 00000000 + 00000000 0x2161: 00000000 + 00000000 0x2162: 00000000 + 00000000 0x2163: 00000000 + 00000000 0x2164: 00000000 + 00000000 0x2166: 00000000 + 00000000 0x2167: 00000000 + 00000000 0x2168: 00000000 + 00000000 0x2169: 00000000 + 00000000 0x216b: 00000000 + 00000000 0x216c: 00000000 + 00000000 0x216d: 00000000 + 00000000 VPC_SO_FLUSH_WADDR_3: 0 !+ 0000001f UNKNOWN_21C3: 0x1f !+ 02000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + ffffffff PC_RESTART_INDEX: 0xffffffff + 00000000 PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } + 00000001 UNKNOWN_21E6: 0x1 + 00000000 PC_HS_PARAM: { VERTICES_OUT = 0 | SPACING = EQUAL_SPACING } !+ 082a0008 VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } !+ fcfc0081 VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } + fcfcfcfc VFD_CONTROL_2: 0xfcfcfcfc !+ 0000fc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } + 0000fcfc VFD_CONTROL_4: 0xfcfc + 00000000 VFD_INDEX_OFFSET: 0 + 00000000 UNKNOWN_2209: 0 + 0008080f VFD_FETCH[0].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 | SWITCHNEXT } !+ 0009c1e0 VFD_FETCH[0].INSTR_1: 0x9c1e0 + 00000060 VFD_FETCH[0].INSTR_2: { SIZE = 0x60 } + 00000001 VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } + 0000080f VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 } !+ 0009c210 VFD_FETCH[0x1].INSTR_1: 0x9c210 + 00000030 VFD_FETCH[0x1].INSTR_2: { SIZE = 0x30 } + 00000001 VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } + 7000411f VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID | SWITCHNEXT } + 3000011f VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID } + 00060010 SP_SP_CTRL_REG: { 0x60010 } + 000005c3 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } !+ 00200800 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 2 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } !+ 08000002 SP_VS_CTRL_REG1: { CONSTLENGTH = 2 | INITIALOUTSTANDING = 8 } !+ 0010fc04 SP_VS_PARAM_REG: { POSREGID = r1.x | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } !+ 00001e00 SP_VS_OUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00fcfc00 UNKNOWN_22D7: 0xfcfc00 + 00000008 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } !+ 00049000 SP_VS_OBJ_START: 0x49000 00049000: 0000: 00000000 13000000 00000000 00000000 00000000 00000000 00000000 00000000 * :0:0000:0000[13000000x_00000000x] (sy)end :0:0001:0001[00000000x_00000000x] nop :0:0002:0002[00000000x_00000000x] nop :0:0003:0003[00000000x_00000000x] nop :0:0004:0004[00000000x_00000000x] nop Stats: - shaderdb: 5 instr, 4 nops, 1 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 0 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 0 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) !+ 00000001 SP_VS_LENGTH_REG: 1 !+ 00340412 SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE } !+ 80100002 SP_FS_CTRL_REG1: { CONSTLENGTH = 2 | VARYING | 0x80000000 } !+ 7e020000 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } !+ 00046000 SP_FS_OBJ_START: 0x46000 00046000: 0000: 00002000 5730cb00 00000000 03000000 00000000 00000000 00000000 00000000 * :2:0000:0000[5730cb00x_00002000x] (sy)(rpt3)bary.f (ei)hr0.x, (r)0, r0.x :0:0001:0004[03000000x_00000000x] end :0:0002:0005[00000000x_00000000x] nop :0:0003:0006[00000000x_00000000x] nop :0:0004:0007[00000000x_00000000x] nop :0:0005:0008[00000000x_00000000x] nop Stats: - shaderdb: 9 instr, 4 nops, 5 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 1 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 4 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) + 00000001 SP_FS_LENGTH_REG: 1 !+ fc00fc01 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r63.x } !+ 0001a100 SP_FS_MRT[0].REG: { REGID = r0.x | HALF_PRECISION | MRTFORMAT = RB4_R8G8B8A8_UNORM } + 00000000 0x230c: 00000000 + 7e020000 SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } + 00000000 SP_HS_OBJ_START: 0 + 00000000 0x2318: 00000000 + 00000000 0x2319: 00000000 + 7e020000 SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } + 00000000 SP_DS_OBJ_START: 0 + 00000000 0x2340: 00000000 + 7e020000 SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } + 00000000 SP_GS_OBJ_START: 0 + 00000808 TPL1_TP_TEX_OFFSET: 0x808 + 00000000 TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } !+ 00000002 0x2382: 00000002 !+ 00000000 TPL1_TP_FS_TEX_COUNT: 0 !+ 080604f0 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0x600a0 } !+ fcfc1108 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x1008 } !+ fff3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } + fcfcfc00 HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } !+ 00fcfc00 HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r0.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } !+ 01010002 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 2 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 1 } !+ 017f0202 HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 2 | CONSTOBJECTOFFSET = 2 | ENABLED | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 } !+ 007e0200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } !+ 007e0200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } !+ 007e0200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } !+ 00000003 HLSQ_UPDATE_CONTROL: 0x3 000555ac: 0000: c0023800 00200984 00000001 00000003 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 18 | GROUP_ID = 1 } { ADDR_LO = 0x9c520 } 000555bc: 0000: c0014300 01000012 0009c520 group_id: 1 count: 18 addr: 000000000009c520 flags: 0 0009c520: 0000: 00002200 082a0008 00002201 fcfc0081 00002203 0000fc00 0007220a 0008080f 0009c540: 0020: 0009c4c0 00000060 00000001 0000080f 0009c4f0 00000030 00000001 0001228a 0009c560: 0040: 7000411f 3000011f t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } 0009c520: 0000: 00002200 082a0008 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } 0009c528: 0000: 00002201 fcfc0081 t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } 0009c530: 0000: 00002203 0000fc00 t0 write VFD_FETCH[0].INSTR_0 (220a) VFD_FETCH[0].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 | SWITCHNEXT } VFD_FETCH[0].INSTR_1: 0x9c4c0 VFD_FETCH[0].INSTR_2: { SIZE = 0x60 } VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 } VFD_FETCH[0x1].INSTR_1: 0x9c4f0 VFD_FETCH[0x1].INSTR_2: { SIZE = 0x30 } VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } 0009c538: 0000: 0007220a 0008080f 0009c4c0 00000060 00000001 0000080f 0009c4f0 00000030 0009c558: 0020: 00000001 t0 write VFD_DECODE[0].INSTR (228a) VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID | SWITCHNEXT } VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID } 0009c55c: 0000: 0001228a 7000411f 3000011f t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = USE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x200000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 3 } draw[72] register values + 082a0008 VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } + fcfc0081 VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } + 0000fc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } + 0008080f VFD_FETCH[0].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 | SWITCHNEXT } !+ 0009c4c0 VFD_FETCH[0].INSTR_1: 0x9c4c0 + 00000060 VFD_FETCH[0].INSTR_2: { SIZE = 0x60 } + 00000001 VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } + 0000080f VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 } !+ 0009c4f0 VFD_FETCH[0x1].INSTR_1: 0x9c4f0 + 00000030 VFD_FETCH[0x1].INSTR_2: { SIZE = 0x30 } + 00000001 VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } + 7000411f VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID | SWITCHNEXT } + 3000011f VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID } 000555c8: 0000: c0023800 00200984 00000001 00000003 0016b094: 0000: c0013f00 00055328 000000ac t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 0016b0a0: 0000: c0014300 00040000 00000000 t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:001fa610 ibsize:000000f7 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 001fa610: 0000: c0002600 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x4 001fa618: 0000: 00000ec3 00000004 t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x68 001fa620: 0000: 00000f03 00000068 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 001fa628: 0000: c0002600 00000000 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } 001fa630: 0000: 000023c0 080004f0 t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = 0x1d } event (null) 001fa638: 0000: c0004600 0000001d t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = FACENESS_FLUSH } event FACENESS_FLUSH 001fa640: 0000: c0004600 0000001c t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 001fa648: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0 001fa650: 0000: 00000cc6 00000000 t0 write UNKNOWN_0E42 (0e42) UNKNOWN_0E42: 0 001fa658: 0000: 00000e42 00000000 t0 write HLSQ_MODE_CONTROL (0e05) HLSQ_MODE_CONTROL: 0x2 001fa660: 0000: 00000e05 00000002 t0 write UNKNOWN_0CC5 (0cc5) UNKNOWN_0CC5: 0x4 001fa668: 0000: 00000cc5 00000004 t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x7 001fa670: 0000: 000023db 00000007 t0 write VFD_CONTROL_2 (2202) VFD_CONTROL_2: 0xfcfcfcfc 001fa678: 0000: 00002202 fcfcfcfc t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } 001fa680: 0000: 00002203 fcfcfc00 t0 write VFD_CONTROL_4 (2204) VFD_CONTROL_4: 0xfcfc 001fa688: 0000: 00002204 0000fcfc t0 write VFD_INDEX_OFFSET (2208) VFD_INDEX_OFFSET: 0 001fa690: 0000: 00002208 00000000 t0 write UNKNOWN_2209 (2209) UNKNOWN_2209: 0 001fa698: 0000: 00002209 00000000 t0 write UNKNOWN_2152 (2152) UNKNOWN_2152: 0 UNKNOWN_2153: 0 001fa6a0: 0000: 00012152 00000000 00000000 t0 write UNKNOWN_2156 (2156) UNKNOWN_2156: 0 001fa6ac: 0000: 00002156 00000000 t0 write UNKNOWN_2154 (2154) UNKNOWN_2154: 0 001fa6b4: 0000: 00002154 00000000 t0 write UNKNOWN_2155 (2155) UNKNOWN_2155: 0 001fa6bc: 0000: 00002155 00000000 t0 write UNKNOWN_21C3 (21c3) UNKNOWN_21C3: 0x1d 001fa6c4: 0000: 000021c3 0000001d t0 write PC_PRIM_VTX_CNTL2 (21c5) PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 001fa6cc: 0000: 000021c5 00000012 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 001fa6d4: 0000: 000021e5 00000000 t0 write GRAS_SU_MODE_CONTROL (2078) GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } 001fa6dc: 0000: 00002078 00000000 t0 write UNKNOWN_2001 (2001) UNKNOWN_2001: 0 001fa6e4: 0000: 00002001 00000000 t0 write GRAS_CNTL (2003) GRAS_CNTL: { IJ_PERSP } 001fa6ec: 0000: 00002003 00000001 t0 write GRAS_CL_CLIP_CNTL (2000) GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } 001fa6f4: 0000: 00002000 00188000 t0 write TPL1_TP_TEX_COUNT (2381) TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } 001fa6fc: 0000: 00002381 00000000 t0 write TPL1_TP_FS_TEX_COUNT (23a0) TPL1_TP_FS_TEX_COUNT: 0x3 001fa704: 0000: 000023a0 00000003 t0 write RB_ALPHA_CONTROL (20f8) RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } 001fa70c: 0000: 000020f8 00000e00 t0 write RB_RENDER_COMPONENTS (20fb) RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } 001fa714: 0000: 000020fb 0000000f t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 001fa71c: 0000: c0014300 00040000 00000000 t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } 001fa728: 0000: 00002200 000a0000 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } 001fa730: 0000: 00002201 fc030000 t0 write SP_INSTR_CACHE_CTRL (22c1) SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } 001fa738: 0000: 000022c1 000005c3 t0 write HLSQ_CONTROL_1_REG (23c1) HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } 001fa740: 0000: 000023c1 fcfc0120 t0 write HLSQ_CONTROL_2_REG (23c2) HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 001fa748: 0000: 000023c2 27f3f3f0 t0 write HLSQ_VS_CONTROL_REG (23c5) HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } 001fa750: 0000: 000023c5 02010042 t0 write HLSQ_FS_CONTROL_REG (23c6) HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 001fa758: 0000: 000023c6 0041423e t0 write HLSQ_HS_CONTROL_REG (23c7) HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 001fa760: 0000: 000023c7 00404200 t0 write HLSQ_DS_CONTROL_REG (23c8) HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 001fa768: 0000: 000023c8 00404200 t0 write HLSQ_GS_CONTROL_REG (23c9) HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 001fa770: 0000: 000023c9 00404200 t0 write HLSQ_CS_CONTROL_REG (23ca) HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } 001fa778: 0000: 000023ca 00004200 t0 write SP_SP_CTRL_REG (22c0) SP_SP_CTRL_REG: { 0x60010 } 001fa780: 0000: 000022c0 00060010 t0 write UNKNOWN_21E6 (21e6) UNKNOWN_21E6: 0x1 001fa788: 0000: 000021e6 00000001 t0 write SP_VS_CTRL_REG0 (22c4) SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 001fa790: 0000: 000022c4 00200c10 t0 write SP_VS_CTRL_REG1 (22c5) SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } 001fa798: 0000: 000022c5 01000042 t0 write VPC_ATTR (2140) VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | 0x40000000 } 001fa7a0: 0000: 00002140 40001004 t0 write VPC_PACK (2141) VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } 001fa7a8: 0000: 00002141 00040400 t0 write PC_PRIM_VTX_CNTL (21c4) PC_PRIM_VTX_CNTL: { VAROUT = 1 } 001fa7b0: 0000: 000021c4 00000001 t0 write SP_VS_PARAM_REG (22c6) SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } UNKNOWN_22D7: 0xfcfc00 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 001fa7b8: 0000: 001922c6 0010fc03 00001e03 00000000 00000000 00000000 00000000 00000000 * 001fa7f8: 0040: 00000000 00000000 00fcfc00 00000008 00000000 00000000 00000000 00000000 * t0 write SP_VS_OBJ_OFFSET_REG (22e0) SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 001fa824: 0000: 000022e0 00000000 t0 write SP_VS_OBJ_START (22e1) SP_VS_OBJ_START: 0x1 001fa82c: 0000: 000022e1 00000001 t0 write SP_VS_LENGTH_REG (22e5) SP_VS_LENGTH_REG: 2 001fa834: 0000: 000022e5 00000002 t3 opcode: CP_LOAD_STATE4 (30) (67 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } :2:0000:0000[56d81803x_20020003x] (sy)(ss)(nop3) shl.b r0.w, r0.w, 2 :1:0001:0004[20150000x_00000003x] cov.s32s16 hr0.x, r0.w :0:0002:0005[00000200x_00000000x] (rpt2)nop :1:0003:0008[201100f4x_00000000x] mova a0.x, hr0.x :0:0004:0009[00000500x_00000000x] (rpt5)nop :1:0005:0015[20154003x_00000c20x] mov.s32s32 r0.w, c :1:0006:0016[20154004x_00000c21x] mov.s32s32 r1.x, c :1:0007:0017[20154005x_00000c22x] mov.s32s32 r1.y, c :1:0008:0018[20156006x_00000c23x] (ul)mov.s32s32 r1.z, c :0:0009:0019[03000000x_00000000x] end :2:0010:0020[46f00007x_20050000x] shr.b r1.w, r0.x, 5 :2:0011:0021[43980008x_201f0000x] (nop2) and.b r2.x, r0.x, 31 :2:0012:0024[43980807x_201f0007x] (nop3) and.b r1.w, r1.w, 31 :2:0013:0028[46100807x_20100007x] (nop1) mul.u24 r1.w, r1.w, 16 :3:0014:0030[62040007x_00071014x] mad.u24 r1.w, c5.x, r2.x, r1.w :0:0015:0031[00000500x_00000000x] (rpt5)nop :6:0016:0037[c2c60f00x_04800006x] stlw.u32 l[r1.w], r0.w, 4 :0:0017:0038[04800000x_00000000x] chmask :0:0018:0039[05000000x_00000000x] chsh Stats: - shaderdb: 40 instr, 24 nops, 16 non-nops, 5 mov, 1 cov - shaderdb: 0 last-baryf, 0 half, 2 full, 5 constlen - shaderdb: 27 cat0, 6 cat1, 5 cat2, 1 cat3, 0 cat4, 0 cat5, 1 cat6, 0 cat7 - shaderdb: 0 sstall, 1 (ss), 1 (sy) 001fa83c: 0000: c0413000 00a00000 00000000 20020003 56d81803 00000003 20150000 00000000 001fa85c: 0020: 00000200 00000000 201100f4 00000000 00000500 00000c20 20154003 00000c21 001fa87c: 0040: 20154004 00000c22 20154005 00000c23 20156006 00000000 03000000 20050000 001fa89c: 0060: 46f00007 201f0000 43980008 201f0007 43980807 20100007 46100807 00071014 001fa8bc: 0080: 62040007 00000000 00000500 04800006 c2c60f00 00000000 04800000 00000000 001fa8dc: 00a0: 05000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 * t0 write GRAS_SC_CONTROL (207b) GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = 0 | MSAA_DISABLE | RASTER_MODE = 0 } 001fa948: 0000: 0000207b 00000808 t0 write RB_MSAA_CONTROL (20a2) RB_MSAA_CONTROL: { DISABLE | SAMPLES = 0 } 001fa950: 0000: 000020a2 00001000 t0 write RB_RENDER_CONTROL (20a1) RB_RENDER_CONTROL: { DISABLE_COLOR_PIPE | 0x2 } 001fa958: 0000: 000020a1 00000022 t0 write RB_DEPTH_CONTROL (2101) RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } 001fa960: 0000: 00002101 00000000 t0 write GRAS_ALPHA_CONTROL (2073) GRAS_ALPHA_CONTROL: { 0x2 } 001fa968: 0000: 00002073 00000002 t0 write RB_STENCIL_CONTROL (2106) RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } 001fa970: 0000: 00002106 00000000 t0 write RB_COPY_CONTROL (20fc) RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_FOUR | MODE = RB_COPY_DEPTH_STENCIL | FASTCLEAR = 0 | GMEM_BASE = 0 } RB_COPY_DEST_BASE: { BASE = 0x4f000 } RB_COPY_DEST_PITCH: { PITCH = 256 } RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_DISABLE | COMPONENT_ENABLE = 0xf | ENDIAN = ENDIAN_NONE | TILE = TILE4_3 } 001fa978: 0000: 000320fc 00000052 0004f000 00000008 0303c068 t0 write UNKNOWN_20EF (20ef) UNKNOWN_20EF: 0 001fa98c: 0000: 000020ef 00000000 t0 write GRAS_SC_SCREEN_SCISSOR_TL (207c) GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } 001fa994: 0000: 0001207c 00000000 003f003f t0 write RB_FRAME_BUFFER_DIMENSION (0ce0) RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } 001fa9a0: 0000: 00000ce0 00400040 t0 write 0xce1 (0ce1) 0xce1: 00000000 001fa9a8: 0000: 00000ce1 00000000 t3 opcode: CP_LOAD_STATE4 (30) (11 dwords) { DST_OFF = 8 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } 001fa9bc: 0.000000 0.000000 1.000000 1.000000 64.000000 64.000000 1.000000 1.000000 001fa9bc: 0000: 00000000 00000000 3f800000 3f800000 42800000 42800000 3f800000 3f800000 001fa9b0: 0000: c0093000 00a00008 00000001 00000000 00000000 3f800000 3f800000 42800000 001fa9d0: 0020: 42800000 3f800000 3f800000 t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x80000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 2 } draw[73] register values + 00000004 UNKNOWN_0CC5: 0x4 + 00000000 UNKNOWN_0CC6: 0 + 00400040 RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } + 00000000 0xce1: 00000000 !+ 00000002 HLSQ_MODE_CONTROL: 0x2 + 00000000 UNKNOWN_0E42: 0 !+ 00000004 SP_MODE_CONTROL: 0x4 !+ 00000068 TPL1_TP_MODE_CONTROL: 0x68 !+ 00188000 GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } + 00000000 UNKNOWN_2001: 0 + 00000001 GRAS_CNTL: { IJ_PERSP } !+ 00000002 GRAS_ALPHA_CONTROL: { 0x2 } !+ 00000000 GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } !+ 00000808 GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = 0 | MSAA_DISABLE | RASTER_MODE = 0 } !+ 00000000 GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } !+ 003f003f GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } !+ 00000022 RB_RENDER_CONTROL: { DISABLE_COLOR_PIPE | 0x2 } !+ 00001000 RB_MSAA_CONTROL: { DISABLE | SAMPLES = 0 } + 00000000 UNKNOWN_20EF: 0 + 00000e00 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } + 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } !+ 00000052 RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_FOUR | MODE = RB_COPY_DEPTH_STENCIL | FASTCLEAR = 0 | GMEM_BASE = 0 } + 0004f000 RB_COPY_DEST_BASE: { BASE = 0x4f000 } + 00000008 RB_COPY_DEST_PITCH: { PITCH = 256 } !+ 0303c068 RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_DISABLE | COMPONENT_ENABLE = 0xf | ENDIAN = ENDIAN_NONE | TILE = TILE4_3 } + 00000000 RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } + 00000000 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } !+ 40001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | 0x40000000 } + 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } + 00000000 UNKNOWN_2152: 0 + 00000000 UNKNOWN_2153: 0 + 00000000 UNKNOWN_2154: 0 + 00000000 UNKNOWN_2155: 0 + 00000000 UNKNOWN_2156: 0 !+ 0000001d UNKNOWN_21C3: 0x1d !+ 00000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 } + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + 00000000 PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } + 00000001 UNKNOWN_21E6: 0x1 !+ 000a0000 VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } !+ fc030000 VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } + fcfcfcfc VFD_CONTROL_2: 0xfcfcfcfc !+ fcfcfc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } + 0000fcfc VFD_CONTROL_4: 0xfcfc + 00000000 VFD_INDEX_OFFSET: 0 + 00000000 UNKNOWN_2209: 0 + 00060010 SP_SP_CTRL_REG: { 0x60010 } + 000005c3 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } !+ 00200c10 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } !+ 01000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } !+ 0010fc03 SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } !+ 00001e03 SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00fcfc00 UNKNOWN_22D7: 0xfcfc00 + 00000008 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } !+ 00000001 SP_VS_OBJ_START: 0x1 !+ 00000002 SP_VS_LENGTH_REG: 2 + 00000000 TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } !+ 00000003 TPL1_TP_FS_TEX_COUNT: 0x3 !+ 080004f0 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } !+ fcfc0120 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } !+ 27f3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } !+ 02010042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } !+ 0041423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } !+ 00404200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } !+ 00404200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } !+ 00404200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00004200 HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } !+ 00000007 HLSQ_UPDATE_CONTROL: 0x7 001fa9dc: 0000: c0023800 00080888 00000001 00000002 0016b0ac: 0000: c0013f00 001fa610 000000f7 t3 opcode: (null) (1d) (2 dwords) 0016b0b8: 0000: c0001d00 00000000 ############################################################ vertices: 0 ############################################################ cmdstream: 8 dwords t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:000555d8 ibsize:00000155 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 000555d8: 0000: c0002600 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x4 000555e0: 0000: 00000ec3 00000004 t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x68 000555e8: 0000: 00000f03 00000068 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 000555f0: 0000: c0002600 00000000 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } 000555f8: 0000: 000023c0 080004f0 t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = 0x1d } event (null) 00055600: 0000: c0004600 0000001d t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = FACENESS_FLUSH } event FACENESS_FLUSH 00055608: 0000: c0004600 0000001c t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00055610: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0 00055618: 0000: 00000cc6 00000000 t0 write UNKNOWN_0E42 (0e42) UNKNOWN_0E42: 0 00055620: 0000: 00000e42 00000000 t0 write HLSQ_MODE_CONTROL (0e05) HLSQ_MODE_CONTROL: 0x2 00055628: 0000: 00000e05 00000002 t0 write UNKNOWN_0CC5 (0cc5) UNKNOWN_0CC5: 0x4 00055630: 0000: 00000cc5 00000004 t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x7 00055638: 0000: 000023db 00000007 t0 write VFD_CONTROL_2 (2202) VFD_CONTROL_2: 0xfcfcfcfc 00055640: 0000: 00002202 fcfcfcfc t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } 00055648: 0000: 00002203 fcfcfc00 t0 write VFD_CONTROL_4 (2204) VFD_CONTROL_4: 0xfcfc 00055650: 0000: 00002204 0000fcfc t0 write VFD_INDEX_OFFSET (2208) VFD_INDEX_OFFSET: 0 00055658: 0000: 00002208 00000000 t0 write UNKNOWN_2209 (2209) UNKNOWN_2209: 0 00055660: 0000: 00002209 00000000 t0 write UNKNOWN_2152 (2152) UNKNOWN_2152: 0 UNKNOWN_2153: 0 00055668: 0000: 00012152 00000000 00000000 t0 write UNKNOWN_2156 (2156) UNKNOWN_2156: 0 00055674: 0000: 00002156 00000000 t0 write UNKNOWN_2154 (2154) UNKNOWN_2154: 0 0005567c: 0000: 00002154 00000000 t0 write UNKNOWN_2155 (2155) UNKNOWN_2155: 0 00055684: 0000: 00002155 00000000 t0 write UNKNOWN_21C3 (21c3) UNKNOWN_21C3: 0x1d 0005568c: 0000: 000021c3 0000001d t0 write PC_PRIM_VTX_CNTL2 (21c5) PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 00055694: 0000: 000021c5 00000012 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 0005569c: 0000: 000021e5 00000000 t0 write GRAS_SU_MODE_CONTROL (2078) GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } 000556a4: 0000: 00002078 00000000 t0 write UNKNOWN_2001 (2001) UNKNOWN_2001: 0 000556ac: 0000: 00002001 00000000 t0 write GRAS_CNTL (2003) GRAS_CNTL: { IJ_PERSP } 000556b4: 0000: 00002003 00000001 t0 write GRAS_CL_CLIP_CNTL (2000) GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } 000556bc: 0000: 00002000 00188000 t0 write TPL1_TP_TEX_COUNT (2381) TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } 000556c4: 0000: 00002381 00000000 t0 write TPL1_TP_FS_TEX_COUNT (23a0) TPL1_TP_FS_TEX_COUNT: 0x3 000556cc: 0000: 000023a0 00000003 t0 write RB_ALPHA_CONTROL (20f8) RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } 000556d4: 0000: 000020f8 00000e00 t0 write RB_RENDER_COMPONENTS (20fb) RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } 000556dc: 0000: 000020fb 0000000f t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 000556e4: 0000: c0014300 00040000 00000000 t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } 000556f0: 0000: 00002200 000a0000 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } 000556f8: 0000: 00002201 fc030000 t0 write SP_INSTR_CACHE_CTRL (22c1) SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } 00055700: 0000: 000022c1 000005c3 t0 write HLSQ_CONTROL_1_REG (23c1) HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } 00055708: 0000: 000023c1 fcfc0120 t0 write HLSQ_CONTROL_2_REG (23c2) HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 00055710: 0000: 000023c2 27f3f3f0 t0 write HLSQ_VS_CONTROL_REG (23c5) HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } 00055718: 0000: 000023c5 02010042 t0 write HLSQ_FS_CONTROL_REG (23c6) HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 1 } 00055720: 0000: 000023c6 0141423e t0 write HLSQ_HS_CONTROL_REG (23c7) HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00055728: 0000: 000023c7 00404200 t0 write HLSQ_DS_CONTROL_REG (23c8) HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00055730: 0000: 000023c8 00404200 t0 write HLSQ_GS_CONTROL_REG (23c9) HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00055738: 0000: 000023c9 00404200 t0 write HLSQ_CS_CONTROL_REG (23ca) HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } 00055740: 0000: 000023ca 00004200 t0 write SP_SP_CTRL_REG (22c0) SP_SP_CTRL_REG: { 0x60010 } 00055748: 0000: 000022c0 00060010 t0 write UNKNOWN_21E6 (21e6) UNKNOWN_21E6: 0x1 00055750: 0000: 000021e6 00000001 t0 write SP_VS_CTRL_REG0 (22c4) SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 00055758: 0000: 000022c4 00200c10 t0 write SP_VS_CTRL_REG1 (22c5) SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } 00055760: 0000: 000022c5 01000042 t0 write VPC_ATTR (2140) VPC_ATTR: { TOTALATTR = 8 | THRDASSIGN = 1 | ENABLE | 0x40000000 } 00055768: 0000: 00002140 42001008 t0 write VPC_PACK (2141) VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 8 | NUMNONPOSVSVAR = 6 } 00055770: 0000: 00002141 00060800 t0 write PC_PRIM_VTX_CNTL (21c4) PC_PRIM_VTX_CNTL: { VAROUT = 1 } 00055778: 0000: 000021c4 00000001 t0 write SP_VS_PARAM_REG (22c6) SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 2 } SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r1.w | B_COMPMASK = 0x3 } SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } UNKNOWN_22D7: 0xfcfc00 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 12 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 00055780: 0000: 001922c6 0020fc03 06071e03 00000000 00000000 00000000 00000000 00000000 * 000557c0: 0040: 00000000 00000000 00fcfc00 00000c08 00000000 00000000 00000000 00000000 * t0 write SP_VS_OBJ_OFFSET_REG (22e0) SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 000557ec: 0000: 000022e0 00000000 t0 write SP_VS_OBJ_START (22e1) SP_VS_OBJ_START: 0x1 000557f4: 0000: 000022e1 00000001 t0 write SP_VS_LENGTH_REG (22e5) SP_VS_LENGTH_REG: 2 000557fc: 0000: 000022e5 00000002 t3 opcode: CP_LOAD_STATE4 (30) (67 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } :2:0000:0000[56d81803x_20020003x] (sy)(ss)(nop3) shl.b r0.w, r0.w, 2 :1:0001:0004[20150000x_00000003x] cov.s32s16 hr0.x, r0.w :0:0002:0005[00000200x_00000000x] (rpt2)nop :1:0003:0008[201100f4x_00000000x] mova a0.x, hr0.x :0:0004:0009[00000500x_00000000x] (rpt5)nop :1:0005:0015[20154003x_00000c20x] mov.s32s32 r0.w, c :1:0006:0016[20154004x_00000c21x] mov.s32s32 r1.x, c :1:0007:0017[20154007x_00000c22x] mov.s32s32 r1.w, c :1:0008:0018[20156008x_00000c23x] (ul)mov.s32s32 r2.x, c :1:0009:0019[20554005x_00000000x] mov.s32s32 r1.y, 0 :1:0010:0020[20554006x_3f800000x] mov.s32s32 r1.z, 1065353216 :0:0011:0021[03000000x_00000000x] end :2:0012:0022[46f00009x_20050000x] shr.b r2.y, r0.x, 5 :2:0013:0023[4398000ax_201f0000x] (nop2) and.b r2.z, r0.x, 31 :2:0014:0026[43980809x_201f0009x] (nop3) and.b r2.y, r2.y, 31 :2:0015:0030[46100809x_20180009x] (nop1) mul.u24 r2.y, r2.y, 24 :3:0016:0032[62050009x_00091014x] mad.u24 r2.y, c5.x, r2.z, r2.y :0:0017:0033[00000500x_00000000x] (rpt5)nop :6:0018:0039[c2c61300x_04800006x] stlw.u32 l[r2.y], r0.w, 4 :6:0019:0040[c2c61310x_0280000ex] stlw.u32 l[r2.y+16], r1.w, 2 :0:0020:0041[04800000x_00000000x] chmask :0:0021:0042[05000000x_00000000x] chsh Stats: - shaderdb: 43 instr, 24 nops, 19 non-nops, 7 mov, 1 cov - shaderdb: 0 last-baryf, 0 half, 3 full, 5 constlen - shaderdb: 27 cat0, 8 cat1, 5 cat2, 1 cat3, 0 cat4, 0 cat5, 2 cat6, 0 cat7 - shaderdb: 0 sstall, 1 (ss), 1 (sy) 00055804: 0000: c0413000 00a00000 00000000 20020003 56d81803 00000003 20150000 00000000 00055824: 0020: 00000200 00000000 201100f4 00000000 00000500 00000c20 20154003 00000c21 00055844: 0040: 20154004 00000c22 20154007 00000c23 20156008 00000000 20554005 3f800000 00055864: 0060: 20554006 00000000 03000000 20050000 46f00009 201f0000 4398000a 201f0009 00055884: 0080: 43980809 20180009 46100809 00091014 62050009 00000000 00000500 04800006 000558a4: 00a0: c2c61300 0280000e c2c61310 00000000 04800000 00000000 05000000 00000000 * t0 write HLSQ_CONTROL_3_REG (23c3) HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } 00055910: 0000: 000023c3 fcfcfc00 t0 write HLSQ_CONTROL_4_REG (23c4) HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } 00055918: 0000: 000023c4 00fcfcfc t0 write SP_FS_CTRL_REG0 (22e8) SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 0 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE | PIXLODENABLE } SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 } 00055920: 0000: 000122e8 00700402 8010003e t0 write SP_FS_OBJ_OFFSET_REG (22ea) SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 } 0005592c: 0000: 000022ea 40420000 t0 write SP_FS_OBJ_START (22eb) SP_FS_OBJ_START: 0x1 00055934: 0000: 000022eb 00000001 t0 write SP_FS_LENGTH_REG (22ef) SP_FS_LENGTH_REG: 1 0005593c: 0000: 000022ef 00000001 t0 write SP_FS_OUTPUT_REG (22f0) SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r0.x | SAMPLEMASK_REGID = r0.x } 00055944: 0000: 000022f0 00000001 t0 write VPC_VARYING_INTERP[0].MODE (2142) VPC_VARYING_INTERP[0].MODE: 0xe000 0005594c: 0000: 00002142 0000e000 t0 write RB_FS_OUTPUT_REG (2100) RB_FS_OUTPUT_REG: { MRT = 1 } 00055954: 0000: 00002100 00000001 t3 opcode: CP_LOAD_STATE4 (30) (35 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 1 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } :2:0000:0000[57309902x_00002004x] (sy)(ss)(rpt1)bary.f (ei)r0.z, (r)4, r0.x :0:0001:0002[00000500x_00000000x] (rpt5)nop :5:0002:0008[a0c01f00x_00000005x] sam (f32)(xyzw)r0.x, r0.z, s#0, t#0 :0:0003:0009[03000000x_00000000x] end :0:0004:0010[00000000x_00000000x] nop :0:0005:0011[00000000x_00000000x] nop :0:0006:0012[00000000x_00000000x] nop :0:0007:0013[00000000x_00000000x] nop Stats: - shaderdb: 14 instr, 10 nops, 4 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 0 half, 1 full, 0 constlen - shaderdb: 11 cat0, 0 cat1, 2 cat2, 0 cat3, 0 cat4, 1 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 1 (ss), 1 (sy) 0005595c: 0000: c0213000 00700000 00000000 00002004 57309902 00000000 00000500 00000005 0005597c: 0020: a0c01f00 00000000 03000000 00000000 00000000 00000000 00000000 00000000 * t0 write RB_FS_OUTPUT (20f9) RB_FS_OUTPUT: { ENABLE_BLEND = 0 | SAMPLE_MASK = 0xffff } 000559e8: 0000: 000020f9 ffff0000 t0 write RB_MRT[0].CONTROL (20a4) RB_MRT[0].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0xf } 000559f0: 0000: 000020a4 0f000000 t0 write RB_MRT[0x1].CONTROL (20a9) RB_MRT[0x1].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0xf } 000559f8: 0000: 000020a9 0f000000 t0 write RB_MRT[0].BLEND_CONTROL (20a8) RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } 00055a00: 0000: 000020a8 00000000 t3 opcode: CP_LOAD_STATE4 (30) (5 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_TEX | NUM_UNIT = 1 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } { XY_MAG = A4XX_TEX_NEAREST | XY_MIN = A4XX_TEX_NEAREST | WRAP_S = A4XX_TEX_CLAMP_TO_EDGE | WRAP_T = A4XX_TEX_CLAMP_TO_EDGE | WRAP_R = A4XX_TEX_CLAMP_TO_EDGE | ANISO = A4XX_TEX_ANISO_1 | LOD_BIAS = 0.000000 | 0x60000 } { COMPARE_FUNC = FUNC_LEQUAL | UNNORM_COORDS | MIPFILTER_LINEAR_FAR | MAX_LOD = 0.000000 | MIN_LOD = 0.000000 | 0x1 } 00055a14: 0000: 00060920 00000067 00055a08: 0000: c0033000 00500000 00000000 00060920 00000067 t0 write GRAS_SC_CONTROL (207b) GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 0 | RASTER_MODE = 0 } 00055a1c: 0000: 0000207b 00000000 t0 write RB_MSAA_CONTROL (20a2) RB_MSAA_CONTROL: { SAMPLES = 0 } 00055a24: 0000: 000020a2 00000000 t0 write RB_RENDER_CONTROL (20a1) RB_RENDER_CONTROL: { 0 } 00055a2c: 0000: 000020a1 00000000 t0 write 0x2382 (2382) 0x2382: 00000000 00055a34: 0000: 00002382 00000000 t0 write RB_DEPTH_CONTROL (2101) RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } 00055a3c: 0000: 00002101 00000000 t0 write GRAS_ALPHA_CONTROL (2073) GRAS_ALPHA_CONTROL: { 0 } 00055a44: 0000: 00002073 00000000 t0 write RB_STENCIL_CONTROL (2106) RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } 00055a4c: 0000: 00002106 00000000 t0 write SP_FS_MRT[0].REG (22f1) SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = RB4_R8G8B8A8_UNORM } 00055a54: 0000: 000022f1 0001a000 t0 write RB_MRT[0].BUF_INFO (20a5) RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB4_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE4_3 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 256 } RB_MRT[0].BASE: 0x166000 RB_MRT[0].CONTROL3: { STRIDE = 0 } 00055a5c: 0000: 000220a5 000400da 00166000 00000000 t3 opcode: CP_LOAD_STATE4 (30) (11 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_TEX | NUM_UNIT = 1 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } { TILED | SWIZ_X = A4XX_TEX_X | SWIZ_Y = A4XX_TEX_Y | SWIZ_Z = A4XX_TEX_Z | SWIZ_W = A4XX_TEX_W | MIPLVLS = 0 | FMT = TFMT4_8_8_8_8_UNORM | TYPE = A4XX_TEX_2D | 0x2 } { HEIGHT = 64 | WIDTH = 64 } { PITCHALIGN = 0 | PITCH = 256 | SWAP = WZYX } { LAYERSZ = 0 | DEPTH = 1 | 0x20000 } { LAYERSZ = 4096 | BASE = 0x4f000 } { 5 = 0 } { 6 = 0 } { 7 = 0 } 00055a78: 0000: 27006883 00200040 00020000 00060000 0004f001 00000000 00000000 00000000 00055a6c: 0000: c0093000 00500000 00000001 27006883 00200040 00020000 00060000 0004f001 * t0 write VPC_VARYING_PS_REPL[0].MODE (214a) VPC_VARYING_PS_REPL[0].MODE: 0x99999999 00055a98: 0000: 0000214a 99999999 t0 write GRAS_SC_SCREEN_SCISSOR_TL (207c) GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } 00055aa0: 0000: 0001207c 00000000 003f003f t0 write GRAS_SC_WINDOW_SCISSOR_BR (209c) GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 00055aac: 0000: 0001209c 003f003f 00000000 t0 write RB_FRAME_BUFFER_DIMENSION (0ce0) RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } 00055ab8: 0000: 00000ce0 00400040 t0 write 0xce1 (0ce1) 0xce1: 00000000 00055ac0: 0000: 00000ce1 00000000 t0 write RB_RENDER_CONTROL2 (20a3) RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 | IJ_PERSP_PIXEL } 00055ac8: 0000: 000020a3 00001000 t0 write RB_MODE_CONTROL (20a0) RB_MODE_CONTROL: { WIDTH = 0 | HEIGHT = 0 | 0xc00000 } 00055ad0: 0000: 000020a0 00c00000 t3 opcode: CP_LOAD_STATE4 (30) (11 dwords) { DST_OFF = 8 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } 00055ae4: 0.000000 0.000000 0.000000 0.000000 64.000000 64.000000 64.000000 64.000000 00055ae4: 0000: 00000000 00000000 00000000 00000000 42800000 42800000 42800000 42800000 00055ad8: 0000: c0093000 00a00008 00000001 00000000 00000000 00000000 00000000 42800000 00055af8: 0020: 42800000 42800000 42800000 t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x80000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 2 } draw[74] register values + 00000004 UNKNOWN_0CC5: 0x4 + 00000000 UNKNOWN_0CC6: 0 + 00400040 RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } + 00000000 0xce1: 00000000 + 00000002 HLSQ_MODE_CONTROL: 0x2 + 00000000 UNKNOWN_0E42: 0 + 00000004 SP_MODE_CONTROL: 0x4 + 00000068 TPL1_TP_MODE_CONTROL: 0x68 + 00188000 GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } + 00000000 UNKNOWN_2001: 0 + 00000001 GRAS_CNTL: { IJ_PERSP } !+ 00000000 GRAS_ALPHA_CONTROL: { 0 } + 00000000 GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } !+ 00000000 GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 0 | RASTER_MODE = 0 } + 00000000 GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } + 003f003f GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } + 003f003f GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } + 00000000 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } !+ 00c00000 RB_MODE_CONTROL: { WIDTH = 0 | HEIGHT = 0 | 0xc00000 } !+ 00000000 RB_RENDER_CONTROL: { 0 } !+ 00000000 RB_MSAA_CONTROL: { SAMPLES = 0 } !+ 00001000 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 | IJ_PERSP_PIXEL } !+ 0f000000 RB_MRT[0].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0xf } !+ 000400da RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB4_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE4_3 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 256 } !+ 00166000 RB_MRT[0].BASE: 0x166000 !+ 00000000 RB_MRT[0].CONTROL3: { STRIDE = 0 } + 00000000 RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } + 0f000000 RB_MRT[0x1].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0xf } + 00000e00 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } !+ ffff0000 RB_FS_OUTPUT: { ENABLE_BLEND = 0 | SAMPLE_MASK = 0xffff } + 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } + 00000001 RB_FS_OUTPUT_REG: { MRT = 1 } + 00000000 RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } + 00000000 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } !+ 42001008 VPC_ATTR: { TOTALATTR = 8 | THRDASSIGN = 1 | ENABLE | 0x40000000 } !+ 00060800 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 8 | NUMNONPOSVSVAR = 6 } !+ 0000e000 VPC_VARYING_INTERP[0].MODE: 0xe000 !+ 99999999 VPC_VARYING_PS_REPL[0].MODE: 0x99999999 + 00000000 UNKNOWN_2152: 0 + 00000000 UNKNOWN_2153: 0 + 00000000 UNKNOWN_2154: 0 + 00000000 UNKNOWN_2155: 0 + 00000000 UNKNOWN_2156: 0 + 0000001d UNKNOWN_21C3: 0x1d + 00000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 } + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + 00000000 PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } + 00000001 UNKNOWN_21E6: 0x1 + 000a0000 VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } + fc030000 VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } + fcfcfcfc VFD_CONTROL_2: 0xfcfcfcfc + fcfcfc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } + 0000fcfc VFD_CONTROL_4: 0xfcfc + 00000000 VFD_INDEX_OFFSET: 0 + 00000000 UNKNOWN_2209: 0 + 00060010 SP_SP_CTRL_REG: { 0x60010 } + 000005c3 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } + 00200c10 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } + 01000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } !+ 0020fc03 SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 2 } !+ 06071e03 SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r1.w | B_COMPMASK = 0x3 } + 00000000 SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00fcfc00 UNKNOWN_22D7: 0xfcfc00 !+ 00000c08 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 12 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } + 00000001 SP_VS_OBJ_START: 0x1 + 00000002 SP_VS_LENGTH_REG: 2 !+ 00700402 SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 0 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE | PIXLODENABLE } !+ 8010003e SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 } !+ 40420000 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 } !+ 00000001 SP_FS_OBJ_START: 0x1 + 00000001 SP_FS_LENGTH_REG: 1 !+ 00000001 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r0.x | SAMPLEMASK_REGID = r0.x } !+ 0001a000 SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = RB4_R8G8B8A8_UNORM } + 00000000 TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } !+ 00000000 0x2382: 00000000 + 00000003 TPL1_TP_FS_TEX_COUNT: 0x3 + 080004f0 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } + fcfc0120 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } + 27f3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } + fcfcfc00 HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } !+ 00fcfcfc HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } + 02010042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } !+ 0141423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 1 } + 00404200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00004200 HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } + 00000007 HLSQ_UPDATE_CONTROL: 0x7 00055b04: 0000: c0023800 00080888 00000001 00000002 t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = CACHE_FLUSH } event CACHE_FLUSH 00055b14: 0000: c0004600 00000006 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00055b1c: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0x8000012 00055b24: 0000: 00000cc6 08000012 00173000: 0000: c0013f00 000555d8 00000155 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 0017300c: 0000: c0014300 00040000 00000000 t3 opcode: (null) (1d) (2 dwords) 00173018: 0000: c0001d00 00000000 ############################################################ vertices: 0 ############################################################ cmdstream: 48 dwords t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 0016b000: 0000: c0002600 00000000 t0 write UCHE_INVALIDATE0 (0e8a) UCHE_INVALIDATE0: 0 UCHE_INVALIDATE1: 0x12 0016b008: 0000: 00010e8a 00000000 00000012 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 0016b014: 0000: c0002600 00000000 t0 write RB_MODE_CONTROL (20a0) RB_MODE_CONTROL: { WIDTH = 64 | HEIGHT = 64 | ENABLE_GMEM } 0016b01c: 0000: 000020a0 00010202 t0 write RB_FRAME_BUFFER_DIMENSION (0ce0) RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } 0016b024: 0000: 00000ce0 00400040 t0 write 0xce1 (0ce1) 0xce1: 00000001 0016b02c: 0000: 00000ce1 00000001 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 0016b034: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0 0016b03c: 0000: 00000cc6 00000000 t3 opcode: (null) (1d) (2 dwords) 0016b044: 0000: c0001d00 00000000 t0 write GRAS_SC_WINDOW_SCISSOR_BR (209c) GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 0016b04c: 0000: 0001209c 003f003f 00000000 t0 write RB_BIN_OFFSET (210d) RB_BIN_OFFSET: { X = 0 | Y = 0 } 0016b058: 0000: 0000210d 00000000 t0 write GRAS_SC_WINDOW_SCISSOR_BR (209c) GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 0016b060: 0000: 0001209c 003f003f 00000000 t0 write UNKNOWN_2157 (2157) UNKNOWN_2157: 0x1 0016b06c: 0000: 00002157 00000001 t3 opcode: (null) (64) (2 dwords) 0016b074: 0000: c0006400 00000001 t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:00054994 ibsize:000000f6 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00054994: 0000: c0002600 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x4 0005499c: 0000: 00000ec3 00000004 t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x68 000549a4: 0000: 00000f03 00000068 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 000549ac: 0000: c0002600 00000000 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } 000549b4: 0000: 000023c0 080004f0 t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = 0x1d } event (null) 000549bc: 0000: c0004600 0000001d t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = FACENESS_FLUSH } event FACENESS_FLUSH 000549c4: 0000: c0004600 0000001c t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 000549cc: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0 000549d4: 0000: 00000cc6 00000000 t0 write UNKNOWN_0E42 (0e42) UNKNOWN_0E42: 0 000549dc: 0000: 00000e42 00000000 t0 write HLSQ_MODE_CONTROL (0e05) HLSQ_MODE_CONTROL: 0x2 000549e4: 0000: 00000e05 00000002 t0 write UNKNOWN_0CC5 (0cc5) UNKNOWN_0CC5: 0x4 000549ec: 0000: 00000cc5 00000004 t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x7 000549f4: 0000: 000023db 00000007 t0 write VFD_CONTROL_2 (2202) VFD_CONTROL_2: 0xfcfcfcfc 000549fc: 0000: 00002202 fcfcfcfc t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } 00054a04: 0000: 00002203 fcfcfc00 t0 write VFD_CONTROL_4 (2204) VFD_CONTROL_4: 0xfcfc 00054a0c: 0000: 00002204 0000fcfc t0 write VFD_INDEX_OFFSET (2208) VFD_INDEX_OFFSET: 0 00054a14: 0000: 00002208 00000000 t0 write UNKNOWN_2209 (2209) UNKNOWN_2209: 0 00054a1c: 0000: 00002209 00000000 t0 write UNKNOWN_2152 (2152) UNKNOWN_2152: 0 UNKNOWN_2153: 0 00054a24: 0000: 00012152 00000000 00000000 t0 write UNKNOWN_2156 (2156) UNKNOWN_2156: 0 00054a30: 0000: 00002156 00000000 t0 write UNKNOWN_2154 (2154) UNKNOWN_2154: 0 00054a38: 0000: 00002154 00000000 t0 write UNKNOWN_2155 (2155) UNKNOWN_2155: 0 00054a40: 0000: 00002155 00000000 t0 write UNKNOWN_21C3 (21c3) UNKNOWN_21C3: 0x1d 00054a48: 0000: 000021c3 0000001d t0 write PC_PRIM_VTX_CNTL2 (21c5) PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 00054a50: 0000: 000021c5 00000012 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 00054a58: 0000: 000021e5 00000000 t0 write GRAS_SU_MODE_CONTROL (2078) GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } 00054a60: 0000: 00002078 00000000 t0 write UNKNOWN_2001 (2001) UNKNOWN_2001: 0 00054a68: 0000: 00002001 00000000 t0 write GRAS_CNTL (2003) GRAS_CNTL: { IJ_PERSP } 00054a70: 0000: 00002003 00000001 t0 write GRAS_CL_CLIP_CNTL (2000) GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } 00054a78: 0000: 00002000 00188000 t0 write TPL1_TP_TEX_COUNT (2381) TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } 00054a80: 0000: 00002381 00000000 t0 write TPL1_TP_FS_TEX_COUNT (23a0) TPL1_TP_FS_TEX_COUNT: 0x3 00054a88: 0000: 000023a0 00000003 t0 write RB_ALPHA_CONTROL (20f8) RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } 00054a90: 0000: 000020f8 00000e00 t0 write RB_RENDER_COMPONENTS (20fb) RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } 00054a98: 0000: 000020fb 0000000f t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 00054aa0: 0000: c0014300 00040000 00000000 t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } 00054aac: 0000: 00002200 000a0000 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } 00054ab4: 0000: 00002201 fc030000 t0 write SP_INSTR_CACHE_CTRL (22c1) SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } 00054abc: 0000: 000022c1 000005c3 t0 write HLSQ_CONTROL_1_REG (23c1) HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } 00054ac4: 0000: 000023c1 fcfc0120 t0 write HLSQ_CONTROL_2_REG (23c2) HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 00054acc: 0000: 000023c2 27f3f3f0 t0 write HLSQ_VS_CONTROL_REG (23c5) HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } 00054ad4: 0000: 000023c5 02010042 t0 write HLSQ_FS_CONTROL_REG (23c6) HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00054adc: 0000: 000023c6 0041423e t0 write HLSQ_HS_CONTROL_REG (23c7) HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00054ae4: 0000: 000023c7 00404200 t0 write HLSQ_DS_CONTROL_REG (23c8) HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00054aec: 0000: 000023c8 00404200 t0 write HLSQ_GS_CONTROL_REG (23c9) HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00054af4: 0000: 000023c9 00404200 t0 write HLSQ_CS_CONTROL_REG (23ca) HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } 00054afc: 0000: 000023ca 00004200 t0 write SP_SP_CTRL_REG (22c0) SP_SP_CTRL_REG: { 0x60010 } 00054b04: 0000: 000022c0 00060010 t0 write UNKNOWN_21E6 (21e6) UNKNOWN_21E6: 0x1 00054b0c: 0000: 000021e6 00000001 t0 write SP_VS_CTRL_REG0 (22c4) SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 00054b14: 0000: 000022c4 00200c10 t0 write SP_VS_CTRL_REG1 (22c5) SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } 00054b1c: 0000: 000022c5 01000042 t0 write VPC_ATTR (2140) VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | 0x40000000 } 00054b24: 0000: 00002140 40001004 t0 write VPC_PACK (2141) VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } 00054b2c: 0000: 00002141 00040400 t0 write PC_PRIM_VTX_CNTL (21c4) PC_PRIM_VTX_CNTL: { VAROUT = 1 } 00054b34: 0000: 000021c4 00000001 t0 write SP_VS_PARAM_REG (22c6) SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } UNKNOWN_22D7: 0xfcfc00 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 00054b3c: 0000: 001922c6 0010fc03 00001e03 00000000 00000000 00000000 00000000 00000000 * 00054b7c: 0040: 00000000 00000000 00fcfc00 00000008 00000000 00000000 00000000 00000000 * t0 write SP_VS_OBJ_OFFSET_REG (22e0) SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 00054ba8: 0000: 000022e0 00000000 t0 write SP_VS_OBJ_START (22e1) SP_VS_OBJ_START: 0x1 00054bb0: 0000: 000022e1 00000001 t0 write SP_VS_LENGTH_REG (22e5) SP_VS_LENGTH_REG: 2 00054bb8: 0000: 000022e5 00000002 t3 opcode: CP_LOAD_STATE4 (30) (67 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } :2:0000:0000[56d81803x_20020003x] (sy)(ss)(nop3) shl.b r0.w, r0.w, 2 :1:0001:0004[20150000x_00000003x] cov.s32s16 hr0.x, r0.w :0:0002:0005[00000200x_00000000x] (rpt2)nop :1:0003:0008[201100f4x_00000000x] mova a0.x, hr0.x :0:0004:0009[00000500x_00000000x] (rpt5)nop :1:0005:0015[20154003x_00000c20x] mov.s32s32 r0.w, c :1:0006:0016[20154004x_00000c21x] mov.s32s32 r1.x, c :1:0007:0017[20154005x_00000c22x] mov.s32s32 r1.y, c :1:0008:0018[20156006x_00000c23x] (ul)mov.s32s32 r1.z, c :0:0009:0019[03000000x_00000000x] end :2:0010:0020[46f00007x_20050000x] shr.b r1.w, r0.x, 5 :2:0011:0021[43980008x_201f0000x] (nop2) and.b r2.x, r0.x, 31 :2:0012:0024[43980807x_201f0007x] (nop3) and.b r1.w, r1.w, 31 :2:0013:0028[46100807x_20100007x] (nop1) mul.u24 r1.w, r1.w, 16 :3:0014:0030[62040007x_00071014x] mad.u24 r1.w, c5.x, r2.x, r1.w :0:0015:0031[00000500x_00000000x] (rpt5)nop :6:0016:0037[c2c60f00x_04800006x] stlw.u32 l[r1.w], r0.w, 4 :0:0017:0038[04800000x_00000000x] chmask :0:0018:0039[05000000x_00000000x] chsh Stats: - shaderdb: 40 instr, 24 nops, 16 non-nops, 5 mov, 1 cov - shaderdb: 0 last-baryf, 0 half, 2 full, 5 constlen - shaderdb: 27 cat0, 6 cat1, 5 cat2, 1 cat3, 0 cat4, 0 cat5, 1 cat6, 0 cat7 - shaderdb: 0 sstall, 1 (ss), 1 (sy) 00054bc0: 0000: c0413000 00a00000 00000000 20020003 56d81803 00000003 20150000 00000000 00054be0: 0020: 00000200 00000000 201100f4 00000000 00000500 00000c20 20154003 00000c21 00054c00: 0040: 20154004 00000c22 20154005 00000c23 20156006 00000000 03000000 20050000 00054c20: 0060: 46f00007 201f0000 43980008 201f0007 43980807 20100007 46100807 00071014 00054c40: 0080: 62040007 00000000 00000500 04800006 c2c60f00 00000000 04800000 00000000 00054c60: 00a0: 05000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 * t0 write GRAS_ALPHA_CONTROL (2073) GRAS_ALPHA_CONTROL: { 0x2 } 00054ccc: 0000: 00002073 00000002 t0 write GRAS_SC_CONTROL (207b) GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = 4 | MSAA_DISABLE | RASTER_MODE = 0 } 00054cd4: 0000: 0000207b 00000a08 t0 write RB_MSAA_CONTROL (20a2) RB_MSAA_CONTROL: { DISABLE | SAMPLES = 4 } 00054cdc: 0000: 000020a2 00009000 t0 write RB_RENDER_CONTROL (20a1) RB_RENDER_CONTROL: { DISABLE_COLOR_PIPE | 0x2 } 00054ce4: 0000: 000020a1 00000022 t0 write RB_CLEAR_COLOR_DW0 (20cc) RB_CLEAR_COLOR_DW0: 0xff000000 RB_CLEAR_COLOR_DW1: 0 RB_CLEAR_COLOR_DW2: 0 RB_CLEAR_COLOR_DW3: 0 00054cec: 0000: 000320cc ff000000 00000000 00000000 00000000 t0 write RB_COPY_CONTROL (20fc) RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_FOUR | MODE = RB_COPY_CLEAR | FASTCLEAR = 0xf | GMEM_BASE = 0 } RB_COPY_DEST_BASE: { BASE = 0x4f000 } RB_COPY_DEST_PITCH: { PITCH = 256 } RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_IF_ALPHA_OFF | COMPONENT_ENABLE = 0 | ENDIAN = ENDIAN_NONE | TILE = TILE4_3 } 00054d00: 0000: 000320fc 00000f22 0004f000 00000008 03000868 t0 write GRAS_SC_SCREEN_SCISSOR_TL (207c) GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } 00054d14: 0000: 0001207c 00000000 003f003f t0 write RB_FRAME_BUFFER_DIMENSION (0ce0) RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } 00054d20: 0000: 00000ce0 00400040 t0 write 0xce1 (0ce1) 0xce1: 00000000 00054d28: 0000: 00000ce1 00000000 t3 opcode: CP_LOAD_STATE4 (30) (11 dwords) { DST_OFF = 8 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } 00054d3c: 0.000000 0.000000 1.000000 1.000000 64.000000 64.000000 1.000000 1.000000 00054d3c: 0000: 00000000 00000000 3f800000 3f800000 42800000 42800000 3f800000 3f800000 00054d30: 0000: c0093000 00a00008 00000001 00000000 00000000 3f800000 3f800000 42800000 00054d50: 0020: 42800000 3f800000 3f800000 t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x80000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 2 } draw[75] register values + 00000004 UNKNOWN_0CC5: 0x4 + 00000000 UNKNOWN_0CC6: 0 + 00400040 RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } + 00000000 0xce1: 00000000 + 00000002 HLSQ_MODE_CONTROL: 0x2 + 00000000 UNKNOWN_0E42: 0 + 00000000 UCHE_INVALIDATE0: 0 + 00000012 UCHE_INVALIDATE1: 0x12 + 00000004 SP_MODE_CONTROL: 0x4 + 00000068 TPL1_TP_MODE_CONTROL: 0x68 + 00188000 GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } + 00000000 UNKNOWN_2001: 0 + 00000001 GRAS_CNTL: { IJ_PERSP } !+ 00000002 GRAS_ALPHA_CONTROL: { 0x2 } + 00000000 GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } !+ 00000a08 GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = 4 | MSAA_DISABLE | RASTER_MODE = 0 } + 00000000 GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } + 003f003f GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } + 003f003f GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } + 00000000 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } !+ 00010202 RB_MODE_CONTROL: { WIDTH = 64 | HEIGHT = 64 | ENABLE_GMEM } !+ 00000022 RB_RENDER_CONTROL: { DISABLE_COLOR_PIPE | 0x2 } !+ 00009000 RB_MSAA_CONTROL: { DISABLE | SAMPLES = 4 } + ff000000 RB_CLEAR_COLOR_DW0: 0xff000000 + 00000000 RB_CLEAR_COLOR_DW1: 0 + 00000000 RB_CLEAR_COLOR_DW2: 0 + 00000000 RB_CLEAR_COLOR_DW3: 0 + 00000e00 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } + 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } !+ 00000f22 RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_FOUR | MODE = RB_COPY_CLEAR | FASTCLEAR = 0xf | GMEM_BASE = 0 } + 0004f000 RB_COPY_DEST_BASE: { BASE = 0x4f000 } + 00000008 RB_COPY_DEST_PITCH: { PITCH = 256 } !+ 03000868 RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_IF_ALPHA_OFF | COMPONENT_ENABLE = 0 | ENDIAN = ENDIAN_NONE | TILE = TILE4_3 } + 00000000 RB_BIN_OFFSET: { X = 0 | Y = 0 } !+ 40001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | 0x40000000 } !+ 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } + 00000000 UNKNOWN_2152: 0 + 00000000 UNKNOWN_2153: 0 + 00000000 UNKNOWN_2154: 0 + 00000000 UNKNOWN_2155: 0 + 00000000 UNKNOWN_2156: 0 + 00000001 UNKNOWN_2157: 0x1 + 0000001d UNKNOWN_21C3: 0x1d + 00000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 } + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + 00000000 PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } + 00000001 UNKNOWN_21E6: 0x1 + 000a0000 VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } + fc030000 VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } + fcfcfcfc VFD_CONTROL_2: 0xfcfcfcfc + fcfcfc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } + 0000fcfc VFD_CONTROL_4: 0xfcfc + 00000000 VFD_INDEX_OFFSET: 0 + 00000000 UNKNOWN_2209: 0 + 00060010 SP_SP_CTRL_REG: { 0x60010 } + 000005c3 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } + 00200c10 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } + 01000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } !+ 0010fc03 SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } !+ 00001e03 SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00fcfc00 UNKNOWN_22D7: 0xfcfc00 !+ 00000008 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } + 00000001 SP_VS_OBJ_START: 0x1 + 00000002 SP_VS_LENGTH_REG: 2 + 00000000 TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } + 00000003 TPL1_TP_FS_TEX_COUNT: 0x3 + 080004f0 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } + fcfc0120 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } + 27f3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } + 02010042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } !+ 0041423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00004200 HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } + 00000007 HLSQ_UPDATE_CONTROL: 0x7 00054d5c: 0000: c0023800 00080888 00000001 00000002 0016b07c: 0000: c0013f00 00054994 000000f6 t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:00054d6c ibsize:00000037 t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } 00054d6c: 0000: 00002200 082a0008 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00054d74: 0000: c0002600 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x1e 00054d7c: 0000: 00000ec3 0000001e t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x28 00054d84: 0000: 00000f03 00000028 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00054d8c: 0000: c0002600 00000000 t0 write HLSQ_MODE_CONTROL (0e05) HLSQ_MODE_CONTROL: 0x1 00054d94: 0000: 00000e05 00000001 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0x600a0 } 00054d9c: 0000: 000023c0 080604f0 t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x7 00054da4: 0000: 000023db 00000007 t0 write PC_RESTART_INDEX (21c6) PC_RESTART_INDEX: 0xffffffff 00054dac: 0000: 000021c6 ffffffff t0 write UNKNOWN_21E6 (21e6) UNKNOWN_21E6: 0x1 00054db4: 0000: 000021e6 00000001 t0 write UNKNOWN_21C3 (21c3) UNKNOWN_21C3: 0x1f 00054dbc: 0000: 000021c3 0000001f t0 write TPL1_TP_TEX_OFFSET (2380) TPL1_TP_TEX_OFFSET: 0x808 00054dc4: 0000: 00002380 00000808 t0 write GRAS_SU_POINT_MINMAX (2070) GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 4092.000000 } GRAS_SU_POINT_SIZE: 0.500000 00054dcc: 0000: 00012070 ffc00010 00000008 t0 write UNKNOWN_2152 (2152) UNKNOWN_2152: 0 UNKNOWN_2153: 0 00054dd8: 0000: 00012152 00000000 00000000 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00054de4: 0000: c0002600 00000000 t0 write UNKNOWN_0CC5 (0cc5) UNKNOWN_0CC5: 0x4 00054dec: 0000: 00000cc5 00000004 t0 write 0xcc4 (0cc4) 0xcc4: 00000000 00054df4: 0000: 00000cc4 00000000 t0 write 0xd03 (0d03) 0xd03: 80200000 00054dfc: 0000: 00000d03 80200000 t0 write UNKNOWN_0EC2 (0ec2) UNKNOWN_0EC2: 0x40000 00054e04: 0000: 00000ec2 00040000 t0 write VPC_DEBUG_ECO_CONTROL (0e64) VPC_DEBUG_ECO_CONTROL: 0x100 00054e0c: 0000: 00000e64 00000100 t0 write UNKNOWN_0E42 (0e42) UNKNOWN_0E42: 0 00054e14: 0000: 00000e42 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x1e 00054e1c: 0000: 00000ec3 0000001e t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x28 00054e24: 0000: 00000f03 00000028 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 00054e2c: 0000: c0014300 00040000 00000000 t0 write VFD_INDEX_OFFSET (2208) VFD_INDEX_OFFSET: 0 00054e38: 0000: 00002208 00000000 t0 write UNKNOWN_2209 (2209) UNKNOWN_2209: 0 00054e40: 0000: 00002209 00000000 0016b088: 0000: c0013f00 00054d6c 00000037 t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:00055328 ibsize:000000ac t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x3 00055328: 0000: 000023db 00000003 t0 write SP_INSTR_CACHE_CTRL (22c1) SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } 00055330: 0000: 000022c1 000005c3 t0 write HLSQ_CONTROL_1_REG (23c1) HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x1008 } 00055338: 0000: 000023c1 fcfc1108 t0 write HLSQ_CONTROL_2_REG (23c2) HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 00055340: 0000: 000023c2 fff3f3f0 t0 write HLSQ_VS_CONTROL_REG (23c5) HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 2 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 1 } 00055348: 0000: 000023c5 01010002 t0 write HLSQ_HS_CONTROL_REG (23c7) HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 00055350: 0000: 000023c7 007e0200 t0 write HLSQ_DS_CONTROL_REG (23c8) HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 00055358: 0000: 000023c8 007e0200 t0 write HLSQ_GS_CONTROL_REG (23c9) HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 00055360: 0000: 000023c9 007e0200 t0 write HLSQ_FS_CONTROL_REG (23c6) HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 2 | CONSTOBJECTOFFSET = 2 | ENABLED | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 } 00055368: 0000: 000023c6 017f0202 t0 write SP_VS_OBJ_OFFSET_REG (22e0) SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 00055370: 0000: 000022e0 00000000 t0 write SP_HS_OBJ_OFFSET_REG (230d) SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } 00055378: 0000: 0000230d 7e020000 t0 write SP_DS_OBJ_OFFSET_REG (2334) SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } 00055380: 0000: 00002334 7e020000 t0 write SP_GS_OBJ_OFFSET_REG (235b) SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } 00055388: 0000: 0000235b 7e020000 t0 write SP_FS_OBJ_OFFSET_REG (22ea) SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } 00055390: 0000: 000022ea 7e020000 t0 write SP_VS_OBJ_START (22e1) SP_VS_OBJ_START: 0x49000 00049000: 0000: 00000000 13000000 00000000 00000000 00000000 00000000 00000000 00000000 * :0:0000:0000[13000000x_00000000x] (sy)end :0:0001:0001[00000000x_00000000x] nop :0:0002:0002[00000000x_00000000x] nop :0:0003:0003[00000000x_00000000x] nop :0:0004:0004[00000000x_00000000x] nop Stats: - shaderdb: 5 instr, 4 nops, 1 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 0 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 0 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) 00055398: 0000: 000022e1 00049000 t0 write SP_HS_OBJ_START (230e) SP_HS_OBJ_START: 0 000553a0: 0000: 0000230e 00000000 t0 write SP_DS_OBJ_START (2335) SP_DS_OBJ_START: 0 000553a8: 0000: 00002335 00000000 t0 write SP_GS_OBJ_START (235c) SP_GS_OBJ_START: 0 000553b0: 0000: 0000235c 00000000 t0 write SP_VS_LENGTH_REG (22e5) SP_VS_LENGTH_REG: 1 000553b8: 0000: 000022e5 00000001 t3 opcode: CP_LOAD_STATE4 (30) (3 dwords) { DST_OFF = 0 | STATE_SRC = SS4_INDIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 1 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0x49000 } :0:0000:0000[13000000x_00000000x] (sy)end :0:0001:0001[00000000x_00000000x] nop :0:0002:0002[00000000x_00000000x] nop :0:0003:0003[00000000x_00000000x] nop :0:0004:0004[00000000x_00000000x] nop Stats: - shaderdb: 5 instr, 4 nops, 1 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 0 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 0 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) 000553c0: 0000: c0013000 00620000 00049000 t0 write 0x2072 (2072) 0x2072: 00000000 000553cc: 0000: 00002072 00000000 t0 write UNKNOWN_2155 (2155) UNKNOWN_2155: 0 000553d4: 0000: 00002155 00000000 t0 write GRAS_CNTL (2003) GRAS_CNTL: { IJ_PERSP } 000553dc: 0000: 00002003 00000001 t0 write VPC_VARYING_INTERP[0].MODE (2142) VPC_VARYING_INTERP[0].MODE: 0 000553e4: 0000: 00002142 00000000 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0x600a0 } 000553ec: 0000: 000023c0 080604f0 t0 write HLSQ_CONTROL_3_REG (23c3) HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } 000553f4: 0000: 000023c3 fcfcfc00 t0 write HLSQ_CONTROL_4_REG (23c4) HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r0.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } 000553fc: 0000: 000023c4 00fcfc00 t0 write SP_FS_CTRL_REG0 (22e8) SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE } SP_FS_CTRL_REG1: { CONSTLENGTH = 2 | VARYING | 0x80000000 } 00055404: 0000: 000122e8 00340412 80100002 t0 write SP_FS_OBJ_START (22eb) SP_FS_OBJ_START: 0x46000 00046000: 0000: 00002000 5730cb00 00000000 03000000 00000000 00000000 00000000 00000000 * :2:0000:0000[5730cb00x_00002000x] (sy)(rpt3)bary.f (ei)hr0.x, (r)0, r0.x :0:0001:0004[03000000x_00000000x] end :0:0002:0005[00000000x_00000000x] nop :0:0003:0006[00000000x_00000000x] nop :0:0004:0007[00000000x_00000000x] nop :0:0005:0008[00000000x_00000000x] nop Stats: - shaderdb: 9 instr, 4 nops, 5 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 1 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 4 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) 00055410: 0000: 000022eb 00046000 t0 write SP_FS_LENGTH_REG (22ef) SP_FS_LENGTH_REG: 1 00055418: 0000: 000022ef 00000001 t0 write RB_RENDER_COMPONENTS (20fb) RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } 00055420: 0000: 000020fb 0000000f t3 opcode: CP_LOAD_STATE4 (30) (3 dwords) { DST_OFF = 0 | STATE_SRC = SS4_INDIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 1 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0x46000 } :2:0000:0000[5730cb00x_00002000x] (sy)(rpt3)bary.f (ei)hr0.x, (r)0, r0.x :0:0001:0004[03000000x_00000000x] end :0:0002:0005[00000000x_00000000x] nop :0:0003:0006[00000000x_00000000x] nop :0:0004:0007[00000000x_00000000x] nop :0:0005:0008[00000000x_00000000x] nop Stats: - shaderdb: 9 instr, 4 nops, 5 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 1 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 4 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) 00055428: 0000: c0013000 00720000 00046000 t0 write SP_SP_CTRL_REG (22c0) SP_SP_CTRL_REG: { 0x60010 } 00055434: 0000: 000022c0 00060010 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 28 | GROUP_ID = 3 } { ADDR_LO = 0x9c5d0 } 0005543c: 0000: c0014300 0300001c 0009c5d0 t0 write RB_DEPTH_INFO (2103) RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTH4_NONE | DEPTH_BASE = 0 } RB_DEPTH_PITCH: 0 RB_DEPTH_PITCH2: 0 00055448: 0000: 00022103 00000000 00000000 00000000 t0 write GRAS_DEPTH_CONTROL (2077) GRAS_DEPTH_CONTROL: { FORMAT = DEPTH4_NONE } 00055458: 0000: 00002077 00000000 t0 write RB_STENCIL_INFO (2108) RB_STENCIL_INFO: { STENCIL_BASE = 0 } RB_STENCIL_PITCH: 0 0x210a: 00000000 00055460: 0000: 00022108 00000000 00000000 00000000 t0 write 0x2002 (2002) 0x2002: 00000000 00055470: 0000: 00002002 00000000 t0 write RB_ALPHA_CONTROL (20f8) RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } 00055478: 0000: 000020f8 00000e00 t0 write RB_MRT[0].CONTROL (20a4) RB_MRT[0].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0x7 } 00055480: 0000: 000020a4 07000c00 t0 write RB_MRT[0].BLEND_CONTROL (20a8) RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } 00055488: 0000: 000020a8 00000000 t0 write GRAS_CL_CLIP_CNTL (2000) GRAS_CL_CLIP_CNTL: { 0x80000 } 00055490: 0000: 00002000 00080000 t0 write GRAS_SU_POLY_OFFSET_SCALE (2074) GRAS_SU_POLY_OFFSET_SCALE: 0.000000 GRAS_SU_POLY_OFFSET_OFFSET: 0.000000 GRAS_SU_POLY_OFFSET_CLAMP: 0.000000 00055498: 0000: 00022074 00000000 00000000 00000000 t0 write GRAS_SU_MODE_CONTROL (2078) GRAS_SU_MODE_CONTROL: { FRONT_CW | LINEHALFWIDTH = 0.500000 | MSAA_ENABLE | RENDERING_PASS } 000554a8: 0000: 00002078 00102014 t0 write GRAS_SC_SCREEN_SCISSOR_TL (207c) GRAS_SC_SCREEN_SCISSOR_TL: { X = 2 | Y = 13 } GRAS_SC_SCREEN_SCISSOR_BR: { X = 33 | Y = 44 } 000554b0: 0000: 0001207c 000d0002 002c0021 t0 write GRAS_CL_VPORT_XOFFSET_0 (2008) GRAS_CL_VPORT_XOFFSET_0: 18.000000 GRAS_CL_VPORT_XSCALE_0: 16.000000 GRAS_CL_VPORT_YOFFSET_0: 29.000000 GRAS_CL_VPORT_YSCALE_0: 16.000000 GRAS_CL_VPORT_ZOFFSET_0: 0.500000 GRAS_CL_VPORT_ZSCALE_0: 0.500000 000554bc: 0000: 00052008 41900000 41800000 41e80000 41800000 3f000000 3f000000 t0 write GRAS_CL_GB_CLIP_ADJ (2004) GRAS_CL_GB_CLIP_ADJ: { HORZ = 511 | VERT = 511 } 000554d8: 0000: 00002004 0007fdff t0 write GRAS_SC_CONTROL (207b) GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 4 | RASTER_MODE = 0 } 000554e0: 0000: 0000207b 00000200 t0 write 0x2382 (2382) 0x2382: 00000002 000554e8: 0000: 00002382 00000002 t0 write RB_MSAA_CONTROL (20a2) RB_MSAA_CONTROL: { SAMPLES = 4 } 000554f0: 0000: 000020a2 00008000 t0 write RB_RENDER_CONTROL2 (20a3) RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 4 | IJ_PERSP_PIXEL } 000554f8: 0000: 000020a3 00001200 t0 write RB_MRT[0].BUF_INFO (20a5) RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB4_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_ALWAYS | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 1024 } RB_MRT[0].BASE: 0 RB_MRT[0].CONTROL3: { STRIDE = 64 } 00055500: 0000: 000220a5 0010029a 00000000 00000200 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 43 | GROUP_ID = 2 } { ADDR_LO = 0x9c640 } 00055510: 0000: c0014300 0200002b 0009c640 t0 write 0x215c (215c) 0x215c: 00000000 0x215d: 00000000 0005551c: 0000: 0001215c 00000000 00000000 t0 write 0x215f (215f) 0x215f: 00000000 00055528: 0000: 0000215f 00000000 t0 write 0x215e (215e) 0x215e: 00000000 00055530: 0000: 0000215e 00000000 t0 write 0x2161 (2161) 0x2161: 00000000 0x2162: 00000000 00055538: 0000: 00012161 00000000 00000000 t0 write 0x2164 (2164) 0x2164: 00000000 00055544: 0000: 00002164 00000000 t0 write 0x2163 (2163) 0x2163: 00000000 0005554c: 0000: 00002163 00000000 t0 write 0x2166 (2166) 0x2166: 00000000 0x2167: 00000000 00055554: 0000: 00012166 00000000 00000000 t0 write 0x2169 (2169) 0x2169: 00000000 00055560: 0000: 00002169 00000000 t0 write 0x2168 (2168) 0x2168: 00000000 00055568: 0000: 00002168 00000000 t0 write 0x216b (216b) 0x216b: 00000000 0x216c: 00000000 00055570: 0000: 0001216b 00000000 00000000 t0 write VPC_SO_FLUSH_WADDR_3 (216e) VPC_SO_FLUSH_WADDR_3: 0 0005557c: 0000: 0000216e 00000000 t0 write 0x216d (216d) 0x216d: 00000000 00055584: 0000: 0000216d 00000000 t0 write UNKNOWN_2156 (2156) UNKNOWN_2156: 0 0005558c: 0000: 00002156 00000000 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 18 | GROUP_ID = 1 } { ADDR_LO = 0x9c6f0 } 00055594: 0000: c0014300 01000012 0009c6f0 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 15 | GROUP_ID = 0 } { ADDR_LO = 0x9c740 } 000555a0: 0000: c0014300 0000000f 0009c740 group_id: 0 count: 15 addr: 000000000009c740 flags: 0 0009c740: 0000: 00002073 00000000 00002101 00000000 00002106 00000000 000021e5 00000000 0009c760: 0020: 0001210b 00000000 00000000 00002381 00000000 000023a0 00000000 t0 write GRAS_ALPHA_CONTROL (2073) GRAS_ALPHA_CONTROL: { 0 } 0009c740: 0000: 00002073 00000000 t0 write RB_DEPTH_CONTROL (2101) RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } 0009c748: 0000: 00002101 00000000 t0 write RB_STENCIL_CONTROL (2106) RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } 0009c750: 0000: 00002106 00000000 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 0009c758: 0000: 000021e5 00000000 t0 write RB_STENCILREFMASK (210b) RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 0009c760: 0000: 0001210b 00000000 00000000 t0 write TPL1_TP_TEX_COUNT (2381) TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } 0009c76c: 0000: 00002381 00000000 t0 write TPL1_TP_FS_TEX_COUNT (23a0) TPL1_TP_FS_TEX_COUNT: 0 0009c774: 0000: 000023a0 00000000 group_id: 1 count: 18 addr: 000000000009c6f0 flags: 0 0009c6f0: 0000: 00002200 082a0008 00002201 fcfc0081 00002203 0000fc00 0007220a 0008080f 0009c710: 0020: 0009c570 00000060 00000001 0000080f 0009c5a0 00000030 00000001 0001228a 0009c730: 0040: 7000411f 3000011f t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } 0009c6f0: 0000: 00002200 082a0008 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } 0009c6f8: 0000: 00002201 fcfc0081 t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } 0009c700: 0000: 00002203 0000fc00 t0 write VFD_FETCH[0].INSTR_0 (220a) VFD_FETCH[0].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 | SWITCHNEXT } VFD_FETCH[0].INSTR_1: 0x9c570 VFD_FETCH[0].INSTR_2: { SIZE = 0x60 } VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 } VFD_FETCH[0x1].INSTR_1: 0x9c5a0 VFD_FETCH[0x1].INSTR_2: { SIZE = 0x30 } VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } 0009c708: 0000: 0007220a 0008080f 0009c570 00000060 00000001 0000080f 0009c5a0 00000030 0009c728: 0020: 00000001 t0 write VFD_DECODE[0].INSTR (228a) VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID | SWITCHNEXT } VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID } 0009c72c: 0000: 0001228a 7000411f 3000011f group_id: 2 count: 43 addr: 000000000009c640 flags: 0 0009c640: 0000: 000020a1 00000000 000022f1 0001a100 000022f0 fc00fc01 00002100 00000001 0009c660: 0020: 000021e5 00000000 000020f9 ffff0501 0000214a 00000000 00002140 42001004 0009c680: 0040: 001922c6 0010fc04 00001e00 00000000 00000000 00000000 00000000 00000000 * 0009c6c0: 0080: 00000000 00000000 00fcfc00 00000008 00000000 00000000 00000000 00000000 * t0 write RB_RENDER_CONTROL (20a1) RB_RENDER_CONTROL: { 0 } 0009c640: 0000: 000020a1 00000000 t0 write SP_FS_MRT[0].REG (22f1) SP_FS_MRT[0].REG: { REGID = r0.x | HALF_PRECISION | MRTFORMAT = RB4_R8G8B8A8_UNORM } 0009c648: 0000: 000022f1 0001a100 t0 write SP_FS_OUTPUT_REG (22f0) SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 0009c650: 0000: 000022f0 fc00fc01 t0 write RB_FS_OUTPUT_REG (2100) RB_FS_OUTPUT_REG: { MRT = 1 } 0009c658: 0000: 00002100 00000001 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 0009c660: 0000: 000021e5 00000000 t0 write RB_FS_OUTPUT (20f9) RB_FS_OUTPUT: { ENABLE_BLEND = 0x1 | INDEPENDENT_BLEND | SAMPLE_MASK = 0xffff | 0x400 } 0009c668: 0000: 000020f9 ffff0501 t0 write VPC_VARYING_PS_REPL[0].MODE (214a) VPC_VARYING_PS_REPL[0].MODE: 0 0009c670: 0000: 0000214a 00000000 t0 write VPC_ATTR (2140) VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 } 0009c678: 0000: 00002140 42001004 t0 write SP_VS_PARAM_REG (22c6) SP_VS_PARAM_REG: { POSREGID = r1.x | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } SP_VS_OUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } UNKNOWN_22D7: 0xfcfc00 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 0009c680: 0000: 001922c6 0010fc04 00001e00 00000000 00000000 00000000 00000000 00000000 * 0009c6c0: 0040: 00000000 00000000 00fcfc00 00000008 00000000 00000000 00000000 00000000 * group_id: 3 count: 28 addr: 000000000009c5d0 flags: 0 0009c5d0: 0000: 000021c4 02000001 00002141 00040400 00002001 00000000 000022c4 00200800 0009c5f0: 0020: 000022c5 08000002 0000230c 00000000 00002318 00000000 00002319 00000000 0009c610: 0040: 00002340 00000000 00002202 fcfcfcfc 00002204 0000fcfc 00002154 00000000 0009c630: 0060: 000021e7 00000000 000021c5 00000012 t0 write PC_PRIM_VTX_CNTL (21c4) PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } 0009c5d0: 0000: 000021c4 02000001 t0 write VPC_PACK (2141) VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } 0009c5d8: 0000: 00002141 00040400 t0 write UNKNOWN_2001 (2001) UNKNOWN_2001: 0 0009c5e0: 0000: 00002001 00000000 t0 write SP_VS_CTRL_REG0 (22c4) SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 2 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 0009c5e8: 0000: 000022c4 00200800 t0 write SP_VS_CTRL_REG1 (22c5) SP_VS_CTRL_REG1: { CONSTLENGTH = 2 | INITIALOUTSTANDING = 8 } 0009c5f0: 0000: 000022c5 08000002 t0 write 0x230c (230c) 0x230c: 00000000 0009c5f8: 0000: 0000230c 00000000 t0 write 0x2318 (2318) 0x2318: 00000000 0009c600: 0000: 00002318 00000000 t0 write 0x2319 (2319) 0x2319: 00000000 0009c608: 0000: 00002319 00000000 t0 write 0x2340 (2340) 0x2340: 00000000 0009c610: 0000: 00002340 00000000 t0 write VFD_CONTROL_2 (2202) VFD_CONTROL_2: 0xfcfcfcfc 0009c618: 0000: 00002202 fcfcfcfc t0 write VFD_CONTROL_4 (2204) VFD_CONTROL_4: 0xfcfc 0009c620: 0000: 00002204 0000fcfc t0 write UNKNOWN_2154 (2154) UNKNOWN_2154: 0 0009c628: 0000: 00002154 00000000 t0 write PC_HS_PARAM (21e7) PC_HS_PARAM: { VERTICES_OUT = 0 | SPACING = EQUAL_SPACING } 0009c630: 0000: 000021e7 00000000 t0 write PC_PRIM_VTX_CNTL2 (21c5) PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 0009c638: 0000: 000021c5 00000012 t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = USE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x200000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 3 } draw[76] register values + 00000000 0xcc4: 00000000 + 00000004 UNKNOWN_0CC5: 0x4 + 80200000 0xd03: 80200000 !+ 00000001 HLSQ_MODE_CONTROL: 0x1 + 00000000 UNKNOWN_0E42: 0 + 00000100 VPC_DEBUG_ECO_CONTROL: 0x100 + 00040000 UNKNOWN_0EC2: 0x40000 !+ 0000001e SP_MODE_CONTROL: 0x1e !+ 00000028 TPL1_TP_MODE_CONTROL: 0x28 !+ 00080000 GRAS_CL_CLIP_CNTL: { 0x80000 } + 00000000 UNKNOWN_2001: 0 + 00000000 0x2002: 00000000 + 00000001 GRAS_CNTL: { IJ_PERSP } + 0007fdff GRAS_CL_GB_CLIP_ADJ: { HORZ = 511 | VERT = 511 } + 41900000 GRAS_CL_VPORT_XOFFSET_0: 18.000000 + 41800000 GRAS_CL_VPORT_XSCALE_0: 16.000000 + 41e80000 GRAS_CL_VPORT_YOFFSET_0: 29.000000 + 41800000 GRAS_CL_VPORT_YSCALE_0: 16.000000 + 3f000000 GRAS_CL_VPORT_ZOFFSET_0: 0.500000 + 3f000000 GRAS_CL_VPORT_ZSCALE_0: 0.500000 + ffc00010 GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 4092.000000 } + 00000008 GRAS_SU_POINT_SIZE: 0.500000 + 00000000 0x2072: 00000000 !+ 00000000 GRAS_ALPHA_CONTROL: { 0 } + 00000000 GRAS_SU_POLY_OFFSET_SCALE: 0.000000 + 00000000 GRAS_SU_POLY_OFFSET_OFFSET: 0.000000 + 00000000 GRAS_SU_POLY_OFFSET_CLAMP: 0.000000 + 00000000 GRAS_DEPTH_CONTROL: { FORMAT = DEPTH4_NONE } !+ 00102014 GRAS_SU_MODE_CONTROL: { FRONT_CW | LINEHALFWIDTH = 0.500000 | MSAA_ENABLE | RENDERING_PASS } !+ 00000200 GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 4 | RASTER_MODE = 0 } !+ 000d0002 GRAS_SC_SCREEN_SCISSOR_TL: { X = 2 | Y = 13 } !+ 002c0021 GRAS_SC_SCREEN_SCISSOR_BR: { X = 33 | Y = 44 } !+ 00000000 RB_RENDER_CONTROL: { 0 } !+ 00008000 RB_MSAA_CONTROL: { SAMPLES = 4 } !+ 00001200 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 4 | IJ_PERSP_PIXEL } !+ 07000c00 RB_MRT[0].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0x7 } !+ 0010029a RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB4_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_ALWAYS | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 1024 } !+ 00000000 RB_MRT[0].BASE: 0 !+ 00000200 RB_MRT[0].CONTROL3: { STRIDE = 64 } + 00000000 RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } + 00000e00 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } !+ ffff0501 RB_FS_OUTPUT: { ENABLE_BLEND = 0x1 | INDEPENDENT_BLEND | SAMPLE_MASK = 0xffff | 0x400 } + 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } + 00000001 RB_FS_OUTPUT_REG: { MRT = 1 } + 00000000 RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } + 00000000 RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTH4_NONE | DEPTH_BASE = 0 } + 00000000 RB_DEPTH_PITCH: 0 + 00000000 RB_DEPTH_PITCH2: 0 + 00000000 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } + 00000000 RB_STENCIL_INFO: { STENCIL_BASE = 0 } + 00000000 RB_STENCIL_PITCH: 0 + 00000000 0x210a: 00000000 + 00000000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } + 00000000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } !+ 42001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 } + 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } !+ 00000000 VPC_VARYING_INTERP[0].MODE: 0 !+ 00000000 VPC_VARYING_PS_REPL[0].MODE: 0 + 00000000 UNKNOWN_2152: 0 + 00000000 UNKNOWN_2153: 0 + 00000000 UNKNOWN_2154: 0 + 00000000 UNKNOWN_2155: 0 + 00000000 UNKNOWN_2156: 0 + 00000000 0x215c: 00000000 + 00000000 0x215d: 00000000 + 00000000 0x215e: 00000000 + 00000000 0x215f: 00000000 + 00000000 0x2161: 00000000 + 00000000 0x2162: 00000000 + 00000000 0x2163: 00000000 + 00000000 0x2164: 00000000 + 00000000 0x2166: 00000000 + 00000000 0x2167: 00000000 + 00000000 0x2168: 00000000 + 00000000 0x2169: 00000000 + 00000000 0x216b: 00000000 + 00000000 0x216c: 00000000 + 00000000 0x216d: 00000000 + 00000000 VPC_SO_FLUSH_WADDR_3: 0 !+ 0000001f UNKNOWN_21C3: 0x1f !+ 02000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + ffffffff PC_RESTART_INDEX: 0xffffffff + 00000000 PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } + 00000001 UNKNOWN_21E6: 0x1 + 00000000 PC_HS_PARAM: { VERTICES_OUT = 0 | SPACING = EQUAL_SPACING } !+ 082a0008 VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } !+ fcfc0081 VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } + fcfcfcfc VFD_CONTROL_2: 0xfcfcfcfc !+ 0000fc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } + 0000fcfc VFD_CONTROL_4: 0xfcfc + 00000000 VFD_INDEX_OFFSET: 0 + 00000000 UNKNOWN_2209: 0 + 0008080f VFD_FETCH[0].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 | SWITCHNEXT } !+ 0009c570 VFD_FETCH[0].INSTR_1: 0x9c570 + 00000060 VFD_FETCH[0].INSTR_2: { SIZE = 0x60 } + 00000001 VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } + 0000080f VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 } !+ 0009c5a0 VFD_FETCH[0x1].INSTR_1: 0x9c5a0 + 00000030 VFD_FETCH[0x1].INSTR_2: { SIZE = 0x30 } + 00000001 VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } + 7000411f VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID | SWITCHNEXT } + 3000011f VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID } + 00060010 SP_SP_CTRL_REG: { 0x60010 } + 000005c3 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } !+ 00200800 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 2 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } !+ 08000002 SP_VS_CTRL_REG1: { CONSTLENGTH = 2 | INITIALOUTSTANDING = 8 } !+ 0010fc04 SP_VS_PARAM_REG: { POSREGID = r1.x | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } !+ 00001e00 SP_VS_OUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00fcfc00 UNKNOWN_22D7: 0xfcfc00 + 00000008 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } !+ 00049000 SP_VS_OBJ_START: 0x49000 00049000: 0000: 00000000 13000000 00000000 00000000 00000000 00000000 00000000 00000000 * :0:0000:0000[13000000x_00000000x] (sy)end :0:0001:0001[00000000x_00000000x] nop :0:0002:0002[00000000x_00000000x] nop :0:0003:0003[00000000x_00000000x] nop :0:0004:0004[00000000x_00000000x] nop Stats: - shaderdb: 5 instr, 4 nops, 1 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 0 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 0 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) !+ 00000001 SP_VS_LENGTH_REG: 1 !+ 00340412 SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE } !+ 80100002 SP_FS_CTRL_REG1: { CONSTLENGTH = 2 | VARYING | 0x80000000 } !+ 7e020000 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } !+ 00046000 SP_FS_OBJ_START: 0x46000 00046000: 0000: 00002000 5730cb00 00000000 03000000 00000000 00000000 00000000 00000000 * :2:0000:0000[5730cb00x_00002000x] (sy)(rpt3)bary.f (ei)hr0.x, (r)0, r0.x :0:0001:0004[03000000x_00000000x] end :0:0002:0005[00000000x_00000000x] nop :0:0003:0006[00000000x_00000000x] nop :0:0004:0007[00000000x_00000000x] nop :0:0005:0008[00000000x_00000000x] nop Stats: - shaderdb: 9 instr, 4 nops, 5 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 1 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 4 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) + 00000001 SP_FS_LENGTH_REG: 1 !+ fc00fc01 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r63.x } !+ 0001a100 SP_FS_MRT[0].REG: { REGID = r0.x | HALF_PRECISION | MRTFORMAT = RB4_R8G8B8A8_UNORM } + 00000000 0x230c: 00000000 + 7e020000 SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } + 00000000 SP_HS_OBJ_START: 0 + 00000000 0x2318: 00000000 + 00000000 0x2319: 00000000 + 7e020000 SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } + 00000000 SP_DS_OBJ_START: 0 + 00000000 0x2340: 00000000 + 7e020000 SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } + 00000000 SP_GS_OBJ_START: 0 + 00000808 TPL1_TP_TEX_OFFSET: 0x808 + 00000000 TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } !+ 00000002 0x2382: 00000002 !+ 00000000 TPL1_TP_FS_TEX_COUNT: 0 !+ 080604f0 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0x600a0 } !+ fcfc1108 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x1008 } !+ fff3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } + fcfcfc00 HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } !+ 00fcfc00 HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r0.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } !+ 01010002 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 2 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 1 } !+ 017f0202 HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 2 | CONSTOBJECTOFFSET = 2 | ENABLED | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 } !+ 007e0200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } !+ 007e0200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } !+ 007e0200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } !+ 00000003 HLSQ_UPDATE_CONTROL: 0x3 000555ac: 0000: c0023800 00200984 00000001 00000003 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 18 | GROUP_ID = 1 } { ADDR_LO = 0x9c8b0 } 000555bc: 0000: c0014300 01000012 0009c8b0 group_id: 1 count: 18 addr: 000000000009c8b0 flags: 0 0009c8b0: 0000: 00002200 082a0008 00002201 fcfc0081 00002203 0000fc00 0007220a 0008080f 0009c8d0: 0020: 0009c850 00000060 00000001 0000080f 0009c880 00000030 00000001 0001228a 0009c8f0: 0040: 7000411f 3000011f t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } 0009c8b0: 0000: 00002200 082a0008 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } 0009c8b8: 0000: 00002201 fcfc0081 t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } 0009c8c0: 0000: 00002203 0000fc00 t0 write VFD_FETCH[0].INSTR_0 (220a) VFD_FETCH[0].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 | SWITCHNEXT } VFD_FETCH[0].INSTR_1: 0x9c850 VFD_FETCH[0].INSTR_2: { SIZE = 0x60 } VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 } VFD_FETCH[0x1].INSTR_1: 0x9c880 VFD_FETCH[0x1].INSTR_2: { SIZE = 0x30 } VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } 0009c8c8: 0000: 0007220a 0008080f 0009c850 00000060 00000001 0000080f 0009c880 00000030 0009c8e8: 0020: 00000001 t0 write VFD_DECODE[0].INSTR (228a) VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID | SWITCHNEXT } VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID } 0009c8ec: 0000: 0001228a 7000411f 3000011f t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = USE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x200000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 3 } draw[77] register values + 082a0008 VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } + fcfc0081 VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } + 0000fc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } + 0008080f VFD_FETCH[0].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 | SWITCHNEXT } !+ 0009c850 VFD_FETCH[0].INSTR_1: 0x9c850 + 00000060 VFD_FETCH[0].INSTR_2: { SIZE = 0x60 } + 00000001 VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } + 0000080f VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 } !+ 0009c880 VFD_FETCH[0x1].INSTR_1: 0x9c880 + 00000030 VFD_FETCH[0x1].INSTR_2: { SIZE = 0x30 } + 00000001 VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } + 7000411f VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID | SWITCHNEXT } + 3000011f VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID } 000555c8: 0000: c0023800 00200984 00000001 00000003 0016b094: 0000: c0013f00 00055328 000000ac t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 0016b0a0: 0000: c0014300 00040000 00000000 t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:001fa9ec ibsize:000000f7 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 001fa9ec: 0000: c0002600 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x4 001fa9f4: 0000: 00000ec3 00000004 t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x68 001fa9fc: 0000: 00000f03 00000068 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 001faa04: 0000: c0002600 00000000 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } 001faa0c: 0000: 000023c0 080004f0 t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = 0x1d } event (null) 001faa14: 0000: c0004600 0000001d t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = FACENESS_FLUSH } event FACENESS_FLUSH 001faa1c: 0000: c0004600 0000001c t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 001faa24: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0 001faa2c: 0000: 00000cc6 00000000 t0 write UNKNOWN_0E42 (0e42) UNKNOWN_0E42: 0 001faa34: 0000: 00000e42 00000000 t0 write HLSQ_MODE_CONTROL (0e05) HLSQ_MODE_CONTROL: 0x2 001faa3c: 0000: 00000e05 00000002 t0 write UNKNOWN_0CC5 (0cc5) UNKNOWN_0CC5: 0x4 001faa44: 0000: 00000cc5 00000004 t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x7 001faa4c: 0000: 000023db 00000007 t0 write VFD_CONTROL_2 (2202) VFD_CONTROL_2: 0xfcfcfcfc 001faa54: 0000: 00002202 fcfcfcfc t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } 001faa5c: 0000: 00002203 fcfcfc00 t0 write VFD_CONTROL_4 (2204) VFD_CONTROL_4: 0xfcfc 001faa64: 0000: 00002204 0000fcfc t0 write VFD_INDEX_OFFSET (2208) VFD_INDEX_OFFSET: 0 001faa6c: 0000: 00002208 00000000 t0 write UNKNOWN_2209 (2209) UNKNOWN_2209: 0 001faa74: 0000: 00002209 00000000 t0 write UNKNOWN_2152 (2152) UNKNOWN_2152: 0 UNKNOWN_2153: 0 001faa7c: 0000: 00012152 00000000 00000000 t0 write UNKNOWN_2156 (2156) UNKNOWN_2156: 0 001faa88: 0000: 00002156 00000000 t0 write UNKNOWN_2154 (2154) UNKNOWN_2154: 0 001faa90: 0000: 00002154 00000000 t0 write UNKNOWN_2155 (2155) UNKNOWN_2155: 0 001faa98: 0000: 00002155 00000000 t0 write UNKNOWN_21C3 (21c3) UNKNOWN_21C3: 0x1d 001faaa0: 0000: 000021c3 0000001d t0 write PC_PRIM_VTX_CNTL2 (21c5) PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 001faaa8: 0000: 000021c5 00000012 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 001faab0: 0000: 000021e5 00000000 t0 write GRAS_SU_MODE_CONTROL (2078) GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } 001faab8: 0000: 00002078 00000000 t0 write UNKNOWN_2001 (2001) UNKNOWN_2001: 0 001faac0: 0000: 00002001 00000000 t0 write GRAS_CNTL (2003) GRAS_CNTL: { IJ_PERSP } 001faac8: 0000: 00002003 00000001 t0 write GRAS_CL_CLIP_CNTL (2000) GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } 001faad0: 0000: 00002000 00188000 t0 write TPL1_TP_TEX_COUNT (2381) TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } 001faad8: 0000: 00002381 00000000 t0 write TPL1_TP_FS_TEX_COUNT (23a0) TPL1_TP_FS_TEX_COUNT: 0x3 001faae0: 0000: 000023a0 00000003 t0 write RB_ALPHA_CONTROL (20f8) RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } 001faae8: 0000: 000020f8 00000e00 t0 write RB_RENDER_COMPONENTS (20fb) RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } 001faaf0: 0000: 000020fb 0000000f t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 001faaf8: 0000: c0014300 00040000 00000000 t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } 001fab04: 0000: 00002200 000a0000 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } 001fab0c: 0000: 00002201 fc030000 t0 write SP_INSTR_CACHE_CTRL (22c1) SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } 001fab14: 0000: 000022c1 000005c3 t0 write HLSQ_CONTROL_1_REG (23c1) HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } 001fab1c: 0000: 000023c1 fcfc0120 t0 write HLSQ_CONTROL_2_REG (23c2) HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 001fab24: 0000: 000023c2 27f3f3f0 t0 write HLSQ_VS_CONTROL_REG (23c5) HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } 001fab2c: 0000: 000023c5 02010042 t0 write HLSQ_FS_CONTROL_REG (23c6) HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 001fab34: 0000: 000023c6 0041423e t0 write HLSQ_HS_CONTROL_REG (23c7) HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 001fab3c: 0000: 000023c7 00404200 t0 write HLSQ_DS_CONTROL_REG (23c8) HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 001fab44: 0000: 000023c8 00404200 t0 write HLSQ_GS_CONTROL_REG (23c9) HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 001fab4c: 0000: 000023c9 00404200 t0 write HLSQ_CS_CONTROL_REG (23ca) HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } 001fab54: 0000: 000023ca 00004200 t0 write SP_SP_CTRL_REG (22c0) SP_SP_CTRL_REG: { 0x60010 } 001fab5c: 0000: 000022c0 00060010 t0 write UNKNOWN_21E6 (21e6) UNKNOWN_21E6: 0x1 001fab64: 0000: 000021e6 00000001 t0 write SP_VS_CTRL_REG0 (22c4) SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 001fab6c: 0000: 000022c4 00200c10 t0 write SP_VS_CTRL_REG1 (22c5) SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } 001fab74: 0000: 000022c5 01000042 t0 write VPC_ATTR (2140) VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | 0x40000000 } 001fab7c: 0000: 00002140 40001004 t0 write VPC_PACK (2141) VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } 001fab84: 0000: 00002141 00040400 t0 write PC_PRIM_VTX_CNTL (21c4) PC_PRIM_VTX_CNTL: { VAROUT = 1 } 001fab8c: 0000: 000021c4 00000001 t0 write SP_VS_PARAM_REG (22c6) SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } UNKNOWN_22D7: 0xfcfc00 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 001fab94: 0000: 001922c6 0010fc03 00001e03 00000000 00000000 00000000 00000000 00000000 * 001fabd4: 0040: 00000000 00000000 00fcfc00 00000008 00000000 00000000 00000000 00000000 * t0 write SP_VS_OBJ_OFFSET_REG (22e0) SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 001fac00: 0000: 000022e0 00000000 t0 write SP_VS_OBJ_START (22e1) SP_VS_OBJ_START: 0x1 001fac08: 0000: 000022e1 00000001 t0 write SP_VS_LENGTH_REG (22e5) SP_VS_LENGTH_REG: 2 001fac10: 0000: 000022e5 00000002 t3 opcode: CP_LOAD_STATE4 (30) (67 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } :2:0000:0000[56d81803x_20020003x] (sy)(ss)(nop3) shl.b r0.w, r0.w, 2 :1:0001:0004[20150000x_00000003x] cov.s32s16 hr0.x, r0.w :0:0002:0005[00000200x_00000000x] (rpt2)nop :1:0003:0008[201100f4x_00000000x] mova a0.x, hr0.x :0:0004:0009[00000500x_00000000x] (rpt5)nop :1:0005:0015[20154003x_00000c20x] mov.s32s32 r0.w, c :1:0006:0016[20154004x_00000c21x] mov.s32s32 r1.x, c :1:0007:0017[20154005x_00000c22x] mov.s32s32 r1.y, c :1:0008:0018[20156006x_00000c23x] (ul)mov.s32s32 r1.z, c :0:0009:0019[03000000x_00000000x] end :2:0010:0020[46f00007x_20050000x] shr.b r1.w, r0.x, 5 :2:0011:0021[43980008x_201f0000x] (nop2) and.b r2.x, r0.x, 31 :2:0012:0024[43980807x_201f0007x] (nop3) and.b r1.w, r1.w, 31 :2:0013:0028[46100807x_20100007x] (nop1) mul.u24 r1.w, r1.w, 16 :3:0014:0030[62040007x_00071014x] mad.u24 r1.w, c5.x, r2.x, r1.w :0:0015:0031[00000500x_00000000x] (rpt5)nop :6:0016:0037[c2c60f00x_04800006x] stlw.u32 l[r1.w], r0.w, 4 :0:0017:0038[04800000x_00000000x] chmask :0:0018:0039[05000000x_00000000x] chsh Stats: - shaderdb: 40 instr, 24 nops, 16 non-nops, 5 mov, 1 cov - shaderdb: 0 last-baryf, 0 half, 2 full, 5 constlen - shaderdb: 27 cat0, 6 cat1, 5 cat2, 1 cat3, 0 cat4, 0 cat5, 1 cat6, 0 cat7 - shaderdb: 0 sstall, 1 (ss), 1 (sy) 001fac18: 0000: c0413000 00a00000 00000000 20020003 56d81803 00000003 20150000 00000000 001fac38: 0020: 00000200 00000000 201100f4 00000000 00000500 00000c20 20154003 00000c21 001fac58: 0040: 20154004 00000c22 20154005 00000c23 20156006 00000000 03000000 20050000 001fac78: 0060: 46f00007 201f0000 43980008 201f0007 43980807 20100007 46100807 00071014 001fac98: 0080: 62040007 00000000 00000500 04800006 c2c60f00 00000000 04800000 00000000 001facb8: 00a0: 05000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 * t0 write GRAS_SC_CONTROL (207b) GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = 0 | MSAA_DISABLE | RASTER_MODE = 0 } 001fad24: 0000: 0000207b 00000808 t0 write RB_MSAA_CONTROL (20a2) RB_MSAA_CONTROL: { DISABLE | SAMPLES = 0 } 001fad2c: 0000: 000020a2 00001000 t0 write RB_RENDER_CONTROL (20a1) RB_RENDER_CONTROL: { DISABLE_COLOR_PIPE | 0x2 } 001fad34: 0000: 000020a1 00000022 t0 write RB_DEPTH_CONTROL (2101) RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } 001fad3c: 0000: 00002101 00000000 t0 write GRAS_ALPHA_CONTROL (2073) GRAS_ALPHA_CONTROL: { 0x2 } 001fad44: 0000: 00002073 00000002 t0 write RB_STENCIL_CONTROL (2106) RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } 001fad4c: 0000: 00002106 00000000 t0 write RB_COPY_CONTROL (20fc) RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_FOUR | MODE = RB_COPY_DEPTH_STENCIL | FASTCLEAR = 0 | GMEM_BASE = 0 } RB_COPY_DEST_BASE: { BASE = 0x4f000 } RB_COPY_DEST_PITCH: { PITCH = 256 } RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_DISABLE | COMPONENT_ENABLE = 0xf | ENDIAN = ENDIAN_NONE | TILE = TILE4_3 } 001fad54: 0000: 000320fc 00000052 0004f000 00000008 0303c068 t0 write UNKNOWN_20EF (20ef) UNKNOWN_20EF: 0 001fad68: 0000: 000020ef 00000000 t0 write GRAS_SC_SCREEN_SCISSOR_TL (207c) GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } 001fad70: 0000: 0001207c 00000000 003f003f t0 write RB_FRAME_BUFFER_DIMENSION (0ce0) RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } 001fad7c: 0000: 00000ce0 00400040 t0 write 0xce1 (0ce1) 0xce1: 00000000 001fad84: 0000: 00000ce1 00000000 t3 opcode: CP_LOAD_STATE4 (30) (11 dwords) { DST_OFF = 8 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } 001fad98: 0.000000 0.000000 1.000000 1.000000 64.000000 64.000000 1.000000 1.000000 001fad98: 0000: 00000000 00000000 3f800000 3f800000 42800000 42800000 3f800000 3f800000 001fad8c: 0000: c0093000 00a00008 00000001 00000000 00000000 3f800000 3f800000 42800000 001fadac: 0020: 42800000 3f800000 3f800000 t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x80000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 2 } draw[78] register values + 00000004 UNKNOWN_0CC5: 0x4 + 00000000 UNKNOWN_0CC6: 0 + 00400040 RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } + 00000000 0xce1: 00000000 !+ 00000002 HLSQ_MODE_CONTROL: 0x2 + 00000000 UNKNOWN_0E42: 0 !+ 00000004 SP_MODE_CONTROL: 0x4 !+ 00000068 TPL1_TP_MODE_CONTROL: 0x68 !+ 00188000 GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } + 00000000 UNKNOWN_2001: 0 + 00000001 GRAS_CNTL: { IJ_PERSP } !+ 00000002 GRAS_ALPHA_CONTROL: { 0x2 } !+ 00000000 GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } !+ 00000808 GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = 0 | MSAA_DISABLE | RASTER_MODE = 0 } !+ 00000000 GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } !+ 003f003f GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } !+ 00000022 RB_RENDER_CONTROL: { DISABLE_COLOR_PIPE | 0x2 } !+ 00001000 RB_MSAA_CONTROL: { DISABLE | SAMPLES = 0 } + 00000000 UNKNOWN_20EF: 0 + 00000e00 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } + 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } !+ 00000052 RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_FOUR | MODE = RB_COPY_DEPTH_STENCIL | FASTCLEAR = 0 | GMEM_BASE = 0 } + 0004f000 RB_COPY_DEST_BASE: { BASE = 0x4f000 } + 00000008 RB_COPY_DEST_PITCH: { PITCH = 256 } !+ 0303c068 RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_DISABLE | COMPONENT_ENABLE = 0xf | ENDIAN = ENDIAN_NONE | TILE = TILE4_3 } + 00000000 RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } + 00000000 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } !+ 40001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | 0x40000000 } + 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } + 00000000 UNKNOWN_2152: 0 + 00000000 UNKNOWN_2153: 0 + 00000000 UNKNOWN_2154: 0 + 00000000 UNKNOWN_2155: 0 + 00000000 UNKNOWN_2156: 0 !+ 0000001d UNKNOWN_21C3: 0x1d !+ 00000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 } + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + 00000000 PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } + 00000001 UNKNOWN_21E6: 0x1 !+ 000a0000 VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } !+ fc030000 VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } + fcfcfcfc VFD_CONTROL_2: 0xfcfcfcfc !+ fcfcfc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } + 0000fcfc VFD_CONTROL_4: 0xfcfc + 00000000 VFD_INDEX_OFFSET: 0 + 00000000 UNKNOWN_2209: 0 + 00060010 SP_SP_CTRL_REG: { 0x60010 } + 000005c3 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } !+ 00200c10 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } !+ 01000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } !+ 0010fc03 SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } !+ 00001e03 SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00fcfc00 UNKNOWN_22D7: 0xfcfc00 + 00000008 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } !+ 00000001 SP_VS_OBJ_START: 0x1 !+ 00000002 SP_VS_LENGTH_REG: 2 + 00000000 TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } !+ 00000003 TPL1_TP_FS_TEX_COUNT: 0x3 !+ 080004f0 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } !+ fcfc0120 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } !+ 27f3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } !+ 02010042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } !+ 0041423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } !+ 00404200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } !+ 00404200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } !+ 00404200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00004200 HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } !+ 00000007 HLSQ_UPDATE_CONTROL: 0x7 001fadb8: 0000: c0023800 00080888 00000001 00000002 0016b0ac: 0000: c0013f00 001fa9ec 000000f7 t3 opcode: (null) (1d) (2 dwords) 0016b0b8: 0000: c0001d00 00000000 ############################################################ vertices: 0 ############################################################ cmdstream: 8 dwords t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:000555d8 ibsize:00000155 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 000555d8: 0000: c0002600 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x4 000555e0: 0000: 00000ec3 00000004 t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x68 000555e8: 0000: 00000f03 00000068 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 000555f0: 0000: c0002600 00000000 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } 000555f8: 0000: 000023c0 080004f0 t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = 0x1d } event (null) 00055600: 0000: c0004600 0000001d t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = FACENESS_FLUSH } event FACENESS_FLUSH 00055608: 0000: c0004600 0000001c t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00055610: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0 00055618: 0000: 00000cc6 00000000 t0 write UNKNOWN_0E42 (0e42) UNKNOWN_0E42: 0 00055620: 0000: 00000e42 00000000 t0 write HLSQ_MODE_CONTROL (0e05) HLSQ_MODE_CONTROL: 0x2 00055628: 0000: 00000e05 00000002 t0 write UNKNOWN_0CC5 (0cc5) UNKNOWN_0CC5: 0x4 00055630: 0000: 00000cc5 00000004 t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x7 00055638: 0000: 000023db 00000007 t0 write VFD_CONTROL_2 (2202) VFD_CONTROL_2: 0xfcfcfcfc 00055640: 0000: 00002202 fcfcfcfc t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } 00055648: 0000: 00002203 fcfcfc00 t0 write VFD_CONTROL_4 (2204) VFD_CONTROL_4: 0xfcfc 00055650: 0000: 00002204 0000fcfc t0 write VFD_INDEX_OFFSET (2208) VFD_INDEX_OFFSET: 0 00055658: 0000: 00002208 00000000 t0 write UNKNOWN_2209 (2209) UNKNOWN_2209: 0 00055660: 0000: 00002209 00000000 t0 write UNKNOWN_2152 (2152) UNKNOWN_2152: 0 UNKNOWN_2153: 0 00055668: 0000: 00012152 00000000 00000000 t0 write UNKNOWN_2156 (2156) UNKNOWN_2156: 0 00055674: 0000: 00002156 00000000 t0 write UNKNOWN_2154 (2154) UNKNOWN_2154: 0 0005567c: 0000: 00002154 00000000 t0 write UNKNOWN_2155 (2155) UNKNOWN_2155: 0 00055684: 0000: 00002155 00000000 t0 write UNKNOWN_21C3 (21c3) UNKNOWN_21C3: 0x1d 0005568c: 0000: 000021c3 0000001d t0 write PC_PRIM_VTX_CNTL2 (21c5) PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 00055694: 0000: 000021c5 00000012 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 0005569c: 0000: 000021e5 00000000 t0 write GRAS_SU_MODE_CONTROL (2078) GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } 000556a4: 0000: 00002078 00000000 t0 write UNKNOWN_2001 (2001) UNKNOWN_2001: 0 000556ac: 0000: 00002001 00000000 t0 write GRAS_CNTL (2003) GRAS_CNTL: { IJ_PERSP } 000556b4: 0000: 00002003 00000001 t0 write GRAS_CL_CLIP_CNTL (2000) GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } 000556bc: 0000: 00002000 00188000 t0 write TPL1_TP_TEX_COUNT (2381) TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } 000556c4: 0000: 00002381 00000000 t0 write TPL1_TP_FS_TEX_COUNT (23a0) TPL1_TP_FS_TEX_COUNT: 0x3 000556cc: 0000: 000023a0 00000003 t0 write RB_ALPHA_CONTROL (20f8) RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } 000556d4: 0000: 000020f8 00000e00 t0 write RB_RENDER_COMPONENTS (20fb) RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } 000556dc: 0000: 000020fb 0000000f t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 000556e4: 0000: c0014300 00040000 00000000 t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } 000556f0: 0000: 00002200 000a0000 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } 000556f8: 0000: 00002201 fc030000 t0 write SP_INSTR_CACHE_CTRL (22c1) SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } 00055700: 0000: 000022c1 000005c3 t0 write HLSQ_CONTROL_1_REG (23c1) HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } 00055708: 0000: 000023c1 fcfc0120 t0 write HLSQ_CONTROL_2_REG (23c2) HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 00055710: 0000: 000023c2 27f3f3f0 t0 write HLSQ_VS_CONTROL_REG (23c5) HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } 00055718: 0000: 000023c5 02010042 t0 write HLSQ_FS_CONTROL_REG (23c6) HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 1 } 00055720: 0000: 000023c6 0141423e t0 write HLSQ_HS_CONTROL_REG (23c7) HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00055728: 0000: 000023c7 00404200 t0 write HLSQ_DS_CONTROL_REG (23c8) HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00055730: 0000: 000023c8 00404200 t0 write HLSQ_GS_CONTROL_REG (23c9) HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00055738: 0000: 000023c9 00404200 t0 write HLSQ_CS_CONTROL_REG (23ca) HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } 00055740: 0000: 000023ca 00004200 t0 write SP_SP_CTRL_REG (22c0) SP_SP_CTRL_REG: { 0x60010 } 00055748: 0000: 000022c0 00060010 t0 write UNKNOWN_21E6 (21e6) UNKNOWN_21E6: 0x1 00055750: 0000: 000021e6 00000001 t0 write SP_VS_CTRL_REG0 (22c4) SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 00055758: 0000: 000022c4 00200c10 t0 write SP_VS_CTRL_REG1 (22c5) SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } 00055760: 0000: 000022c5 01000042 t0 write VPC_ATTR (2140) VPC_ATTR: { TOTALATTR = 8 | THRDASSIGN = 1 | ENABLE | 0x40000000 } 00055768: 0000: 00002140 42001008 t0 write VPC_PACK (2141) VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 8 | NUMNONPOSVSVAR = 6 } 00055770: 0000: 00002141 00060800 t0 write PC_PRIM_VTX_CNTL (21c4) PC_PRIM_VTX_CNTL: { VAROUT = 1 } 00055778: 0000: 000021c4 00000001 t0 write SP_VS_PARAM_REG (22c6) SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 2 } SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r1.w | B_COMPMASK = 0x3 } SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } UNKNOWN_22D7: 0xfcfc00 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 12 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 00055780: 0000: 001922c6 0020fc03 06071e03 00000000 00000000 00000000 00000000 00000000 * 000557c0: 0040: 00000000 00000000 00fcfc00 00000c08 00000000 00000000 00000000 00000000 * t0 write SP_VS_OBJ_OFFSET_REG (22e0) SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 000557ec: 0000: 000022e0 00000000 t0 write SP_VS_OBJ_START (22e1) SP_VS_OBJ_START: 0x1 000557f4: 0000: 000022e1 00000001 t0 write SP_VS_LENGTH_REG (22e5) SP_VS_LENGTH_REG: 2 000557fc: 0000: 000022e5 00000002 t3 opcode: CP_LOAD_STATE4 (30) (67 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } :2:0000:0000[56d81803x_20020003x] (sy)(ss)(nop3) shl.b r0.w, r0.w, 2 :1:0001:0004[20150000x_00000003x] cov.s32s16 hr0.x, r0.w :0:0002:0005[00000200x_00000000x] (rpt2)nop :1:0003:0008[201100f4x_00000000x] mova a0.x, hr0.x :0:0004:0009[00000500x_00000000x] (rpt5)nop :1:0005:0015[20154003x_00000c20x] mov.s32s32 r0.w, c :1:0006:0016[20154004x_00000c21x] mov.s32s32 r1.x, c :1:0007:0017[20154007x_00000c22x] mov.s32s32 r1.w, c :1:0008:0018[20156008x_00000c23x] (ul)mov.s32s32 r2.x, c :1:0009:0019[20554005x_00000000x] mov.s32s32 r1.y, 0 :1:0010:0020[20554006x_3f800000x] mov.s32s32 r1.z, 1065353216 :0:0011:0021[03000000x_00000000x] end :2:0012:0022[46f00009x_20050000x] shr.b r2.y, r0.x, 5 :2:0013:0023[4398000ax_201f0000x] (nop2) and.b r2.z, r0.x, 31 :2:0014:0026[43980809x_201f0009x] (nop3) and.b r2.y, r2.y, 31 :2:0015:0030[46100809x_20180009x] (nop1) mul.u24 r2.y, r2.y, 24 :3:0016:0032[62050009x_00091014x] mad.u24 r2.y, c5.x, r2.z, r2.y :0:0017:0033[00000500x_00000000x] (rpt5)nop :6:0018:0039[c2c61300x_04800006x] stlw.u32 l[r2.y], r0.w, 4 :6:0019:0040[c2c61310x_0280000ex] stlw.u32 l[r2.y+16], r1.w, 2 :0:0020:0041[04800000x_00000000x] chmask :0:0021:0042[05000000x_00000000x] chsh Stats: - shaderdb: 43 instr, 24 nops, 19 non-nops, 7 mov, 1 cov - shaderdb: 0 last-baryf, 0 half, 3 full, 5 constlen - shaderdb: 27 cat0, 8 cat1, 5 cat2, 1 cat3, 0 cat4, 0 cat5, 2 cat6, 0 cat7 - shaderdb: 0 sstall, 1 (ss), 1 (sy) 00055804: 0000: c0413000 00a00000 00000000 20020003 56d81803 00000003 20150000 00000000 00055824: 0020: 00000200 00000000 201100f4 00000000 00000500 00000c20 20154003 00000c21 00055844: 0040: 20154004 00000c22 20154007 00000c23 20156008 00000000 20554005 3f800000 00055864: 0060: 20554006 00000000 03000000 20050000 46f00009 201f0000 4398000a 201f0009 00055884: 0080: 43980809 20180009 46100809 00091014 62050009 00000000 00000500 04800006 000558a4: 00a0: c2c61300 0280000e c2c61310 00000000 04800000 00000000 05000000 00000000 * t0 write HLSQ_CONTROL_3_REG (23c3) HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } 00055910: 0000: 000023c3 fcfcfc00 t0 write HLSQ_CONTROL_4_REG (23c4) HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } 00055918: 0000: 000023c4 00fcfcfc t0 write SP_FS_CTRL_REG0 (22e8) SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 0 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE | PIXLODENABLE } SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 } 00055920: 0000: 000122e8 00700402 8010003e t0 write SP_FS_OBJ_OFFSET_REG (22ea) SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 } 0005592c: 0000: 000022ea 40420000 t0 write SP_FS_OBJ_START (22eb) SP_FS_OBJ_START: 0x1 00055934: 0000: 000022eb 00000001 t0 write SP_FS_LENGTH_REG (22ef) SP_FS_LENGTH_REG: 1 0005593c: 0000: 000022ef 00000001 t0 write SP_FS_OUTPUT_REG (22f0) SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r0.x | SAMPLEMASK_REGID = r0.x } 00055944: 0000: 000022f0 00000001 t0 write VPC_VARYING_INTERP[0].MODE (2142) VPC_VARYING_INTERP[0].MODE: 0xe000 0005594c: 0000: 00002142 0000e000 t0 write RB_FS_OUTPUT_REG (2100) RB_FS_OUTPUT_REG: { MRT = 1 } 00055954: 0000: 00002100 00000001 t3 opcode: CP_LOAD_STATE4 (30) (35 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 1 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } :2:0000:0000[57309902x_00002004x] (sy)(ss)(rpt1)bary.f (ei)r0.z, (r)4, r0.x :0:0001:0002[00000500x_00000000x] (rpt5)nop :5:0002:0008[a0c01f00x_00000005x] sam (f32)(xyzw)r0.x, r0.z, s#0, t#0 :0:0003:0009[03000000x_00000000x] end :0:0004:0010[00000000x_00000000x] nop :0:0005:0011[00000000x_00000000x] nop :0:0006:0012[00000000x_00000000x] nop :0:0007:0013[00000000x_00000000x] nop Stats: - shaderdb: 14 instr, 10 nops, 4 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 0 half, 1 full, 0 constlen - shaderdb: 11 cat0, 0 cat1, 2 cat2, 0 cat3, 0 cat4, 1 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 1 (ss), 1 (sy) 0005595c: 0000: c0213000 00700000 00000000 00002004 57309902 00000000 00000500 00000005 0005597c: 0020: a0c01f00 00000000 03000000 00000000 00000000 00000000 00000000 00000000 * t0 write RB_FS_OUTPUT (20f9) RB_FS_OUTPUT: { ENABLE_BLEND = 0 | SAMPLE_MASK = 0xffff } 000559e8: 0000: 000020f9 ffff0000 t0 write RB_MRT[0].CONTROL (20a4) RB_MRT[0].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0xf } 000559f0: 0000: 000020a4 0f000000 t0 write RB_MRT[0x1].CONTROL (20a9) RB_MRT[0x1].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0xf } 000559f8: 0000: 000020a9 0f000000 t0 write RB_MRT[0].BLEND_CONTROL (20a8) RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } 00055a00: 0000: 000020a8 00000000 t3 opcode: CP_LOAD_STATE4 (30) (5 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_TEX | NUM_UNIT = 1 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } { XY_MAG = A4XX_TEX_NEAREST | XY_MIN = A4XX_TEX_NEAREST | WRAP_S = A4XX_TEX_CLAMP_TO_EDGE | WRAP_T = A4XX_TEX_CLAMP_TO_EDGE | WRAP_R = A4XX_TEX_CLAMP_TO_EDGE | ANISO = A4XX_TEX_ANISO_1 | LOD_BIAS = 0.000000 | 0x60000 } { COMPARE_FUNC = FUNC_LEQUAL | UNNORM_COORDS | MIPFILTER_LINEAR_FAR | MAX_LOD = 0.000000 | MIN_LOD = 0.000000 | 0x1 } 00055a14: 0000: 00060920 00000067 00055a08: 0000: c0033000 00500000 00000000 00060920 00000067 t0 write GRAS_SC_CONTROL (207b) GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 0 | RASTER_MODE = 0 } 00055a1c: 0000: 0000207b 00000000 t0 write RB_MSAA_CONTROL (20a2) RB_MSAA_CONTROL: { SAMPLES = 0 } 00055a24: 0000: 000020a2 00000000 t0 write RB_RENDER_CONTROL (20a1) RB_RENDER_CONTROL: { 0 } 00055a2c: 0000: 000020a1 00000000 t0 write 0x2382 (2382) 0x2382: 00000000 00055a34: 0000: 00002382 00000000 t0 write RB_DEPTH_CONTROL (2101) RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } 00055a3c: 0000: 00002101 00000000 t0 write GRAS_ALPHA_CONTROL (2073) GRAS_ALPHA_CONTROL: { 0 } 00055a44: 0000: 00002073 00000000 t0 write RB_STENCIL_CONTROL (2106) RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } 00055a4c: 0000: 00002106 00000000 t0 write SP_FS_MRT[0].REG (22f1) SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = RB4_R8G8B8A8_UNORM } 00055a54: 0000: 000022f1 0001a000 t0 write RB_MRT[0].BUF_INFO (20a5) RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB4_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE4_3 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 256 } RB_MRT[0].BASE: 0x166000 RB_MRT[0].CONTROL3: { STRIDE = 0 } 00055a5c: 0000: 000220a5 000400da 00166000 00000000 t3 opcode: CP_LOAD_STATE4 (30) (11 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_TEX | NUM_UNIT = 1 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } { TILED | SWIZ_X = A4XX_TEX_X | SWIZ_Y = A4XX_TEX_Y | SWIZ_Z = A4XX_TEX_Z | SWIZ_W = A4XX_TEX_W | MIPLVLS = 0 | FMT = TFMT4_8_8_8_8_UNORM | TYPE = A4XX_TEX_2D | 0x2 } { HEIGHT = 64 | WIDTH = 64 } { PITCHALIGN = 0 | PITCH = 256 | SWAP = WZYX } { LAYERSZ = 0 | DEPTH = 1 | 0x20000 } { LAYERSZ = 4096 | BASE = 0x4f000 } { 5 = 0 } { 6 = 0 } { 7 = 0 } 00055a78: 0000: 27006883 00200040 00020000 00060000 0004f001 00000000 00000000 00000000 00055a6c: 0000: c0093000 00500000 00000001 27006883 00200040 00020000 00060000 0004f001 * t0 write VPC_VARYING_PS_REPL[0].MODE (214a) VPC_VARYING_PS_REPL[0].MODE: 0x99999999 00055a98: 0000: 0000214a 99999999 t0 write GRAS_SC_SCREEN_SCISSOR_TL (207c) GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } 00055aa0: 0000: 0001207c 00000000 003f003f t0 write GRAS_SC_WINDOW_SCISSOR_BR (209c) GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 00055aac: 0000: 0001209c 003f003f 00000000 t0 write RB_FRAME_BUFFER_DIMENSION (0ce0) RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } 00055ab8: 0000: 00000ce0 00400040 t0 write 0xce1 (0ce1) 0xce1: 00000000 00055ac0: 0000: 00000ce1 00000000 t0 write RB_RENDER_CONTROL2 (20a3) RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 | IJ_PERSP_PIXEL } 00055ac8: 0000: 000020a3 00001000 t0 write RB_MODE_CONTROL (20a0) RB_MODE_CONTROL: { WIDTH = 0 | HEIGHT = 0 | 0xc00000 } 00055ad0: 0000: 000020a0 00c00000 t3 opcode: CP_LOAD_STATE4 (30) (11 dwords) { DST_OFF = 8 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } 00055ae4: 0.000000 0.000000 0.000000 0.000000 64.000000 64.000000 64.000000 64.000000 00055ae4: 0000: 00000000 00000000 00000000 00000000 42800000 42800000 42800000 42800000 00055ad8: 0000: c0093000 00a00008 00000001 00000000 00000000 00000000 00000000 42800000 00055af8: 0020: 42800000 42800000 42800000 t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x80000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 2 } draw[79] register values + 00000004 UNKNOWN_0CC5: 0x4 + 00000000 UNKNOWN_0CC6: 0 + 00400040 RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } + 00000000 0xce1: 00000000 + 00000002 HLSQ_MODE_CONTROL: 0x2 + 00000000 UNKNOWN_0E42: 0 + 00000004 SP_MODE_CONTROL: 0x4 + 00000068 TPL1_TP_MODE_CONTROL: 0x68 + 00188000 GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } + 00000000 UNKNOWN_2001: 0 + 00000001 GRAS_CNTL: { IJ_PERSP } !+ 00000000 GRAS_ALPHA_CONTROL: { 0 } + 00000000 GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } !+ 00000000 GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 0 | RASTER_MODE = 0 } + 00000000 GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } + 003f003f GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } + 003f003f GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } + 00000000 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } !+ 00c00000 RB_MODE_CONTROL: { WIDTH = 0 | HEIGHT = 0 | 0xc00000 } !+ 00000000 RB_RENDER_CONTROL: { 0 } !+ 00000000 RB_MSAA_CONTROL: { SAMPLES = 0 } !+ 00001000 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 | IJ_PERSP_PIXEL } !+ 0f000000 RB_MRT[0].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0xf } !+ 000400da RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB4_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE4_3 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 256 } !+ 00166000 RB_MRT[0].BASE: 0x166000 !+ 00000000 RB_MRT[0].CONTROL3: { STRIDE = 0 } + 00000000 RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } + 0f000000 RB_MRT[0x1].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0xf } + 00000e00 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } !+ ffff0000 RB_FS_OUTPUT: { ENABLE_BLEND = 0 | SAMPLE_MASK = 0xffff } + 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } + 00000001 RB_FS_OUTPUT_REG: { MRT = 1 } + 00000000 RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } + 00000000 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } !+ 42001008 VPC_ATTR: { TOTALATTR = 8 | THRDASSIGN = 1 | ENABLE | 0x40000000 } !+ 00060800 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 8 | NUMNONPOSVSVAR = 6 } !+ 0000e000 VPC_VARYING_INTERP[0].MODE: 0xe000 !+ 99999999 VPC_VARYING_PS_REPL[0].MODE: 0x99999999 + 00000000 UNKNOWN_2152: 0 + 00000000 UNKNOWN_2153: 0 + 00000000 UNKNOWN_2154: 0 + 00000000 UNKNOWN_2155: 0 + 00000000 UNKNOWN_2156: 0 + 0000001d UNKNOWN_21C3: 0x1d + 00000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 } + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + 00000000 PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } + 00000001 UNKNOWN_21E6: 0x1 + 000a0000 VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } + fc030000 VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } + fcfcfcfc VFD_CONTROL_2: 0xfcfcfcfc + fcfcfc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } + 0000fcfc VFD_CONTROL_4: 0xfcfc + 00000000 VFD_INDEX_OFFSET: 0 + 00000000 UNKNOWN_2209: 0 + 00060010 SP_SP_CTRL_REG: { 0x60010 } + 000005c3 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } + 00200c10 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } + 01000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } !+ 0020fc03 SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 2 } !+ 06071e03 SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r1.w | B_COMPMASK = 0x3 } + 00000000 SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00fcfc00 UNKNOWN_22D7: 0xfcfc00 !+ 00000c08 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 12 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } + 00000001 SP_VS_OBJ_START: 0x1 + 00000002 SP_VS_LENGTH_REG: 2 !+ 00700402 SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 0 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE | PIXLODENABLE } !+ 8010003e SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 } !+ 40420000 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 } !+ 00000001 SP_FS_OBJ_START: 0x1 + 00000001 SP_FS_LENGTH_REG: 1 !+ 00000001 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r0.x | SAMPLEMASK_REGID = r0.x } !+ 0001a000 SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = RB4_R8G8B8A8_UNORM } + 00000000 TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } !+ 00000000 0x2382: 00000000 + 00000003 TPL1_TP_FS_TEX_COUNT: 0x3 + 080004f0 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } + fcfc0120 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } + 27f3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } + fcfcfc00 HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } !+ 00fcfcfc HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } + 02010042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } !+ 0141423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 1 } + 00404200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00004200 HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } + 00000007 HLSQ_UPDATE_CONTROL: 0x7 00055b04: 0000: c0023800 00080888 00000001 00000002 t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = CACHE_FLUSH } event CACHE_FLUSH 00055b14: 0000: c0004600 00000006 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00055b1c: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0x8000012 00055b24: 0000: 00000cc6 08000012 00173000: 0000: c0013f00 000555d8 00000155 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 0017300c: 0000: c0014300 00040000 00000000 t3 opcode: (null) (1d) (2 dwords) 00173018: 0000: c0001d00 00000000 ############################################################ vertices: 0 ############################################################ cmdstream: 51 dwords t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 0016b000: 0000: c0002600 00000000 t0 write UCHE_INVALIDATE0 (0e8a) UCHE_INVALIDATE0: 0 UCHE_INVALIDATE1: 0x12 0016b008: 0000: 00010e8a 00000000 00000012 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 0016b014: 0000: c0002600 00000000 t0 write RB_MODE_CONTROL (20a0) RB_MODE_CONTROL: { WIDTH = 64 | HEIGHT = 64 | ENABLE_GMEM } 0016b01c: 0000: 000020a0 00010202 t0 write RB_FRAME_BUFFER_DIMENSION (0ce0) RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } 0016b024: 0000: 00000ce0 00400040 t0 write 0xce1 (0ce1) 0xce1: 00000001 0016b02c: 0000: 00000ce1 00000001 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 0016b034: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0 0016b03c: 0000: 00000cc6 00000000 t3 opcode: (null) (1d) (2 dwords) 0016b044: 0000: c0001d00 00000000 t0 write GRAS_SC_WINDOW_SCISSOR_BR (209c) GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 0016b04c: 0000: 0001209c 003f003f 00000000 t0 write RB_BIN_OFFSET (210d) RB_BIN_OFFSET: { X = 0 | Y = 0 } 0016b058: 0000: 0000210d 00000000 t0 write GRAS_SC_WINDOW_SCISSOR_BR (209c) GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 0016b060: 0000: 0001209c 003f003f 00000000 t0 write UNKNOWN_2157 (2157) UNKNOWN_2157: 0x1 0016b06c: 0000: 00002157 00000001 t3 opcode: (null) (64) (2 dwords) 0016b074: 0000: c0006400 00000001 t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:00054994 ibsize:000000f6 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00054994: 0000: c0002600 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x4 0005499c: 0000: 00000ec3 00000004 t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x68 000549a4: 0000: 00000f03 00000068 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 000549ac: 0000: c0002600 00000000 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } 000549b4: 0000: 000023c0 080004f0 t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = 0x1d } event (null) 000549bc: 0000: c0004600 0000001d t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = FACENESS_FLUSH } event FACENESS_FLUSH 000549c4: 0000: c0004600 0000001c t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 000549cc: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0 000549d4: 0000: 00000cc6 00000000 t0 write UNKNOWN_0E42 (0e42) UNKNOWN_0E42: 0 000549dc: 0000: 00000e42 00000000 t0 write HLSQ_MODE_CONTROL (0e05) HLSQ_MODE_CONTROL: 0x2 000549e4: 0000: 00000e05 00000002 t0 write UNKNOWN_0CC5 (0cc5) UNKNOWN_0CC5: 0x4 000549ec: 0000: 00000cc5 00000004 t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x7 000549f4: 0000: 000023db 00000007 t0 write VFD_CONTROL_2 (2202) VFD_CONTROL_2: 0xfcfcfcfc 000549fc: 0000: 00002202 fcfcfcfc t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } 00054a04: 0000: 00002203 fcfcfc00 t0 write VFD_CONTROL_4 (2204) VFD_CONTROL_4: 0xfcfc 00054a0c: 0000: 00002204 0000fcfc t0 write VFD_INDEX_OFFSET (2208) VFD_INDEX_OFFSET: 0 00054a14: 0000: 00002208 00000000 t0 write UNKNOWN_2209 (2209) UNKNOWN_2209: 0 00054a1c: 0000: 00002209 00000000 t0 write UNKNOWN_2152 (2152) UNKNOWN_2152: 0 UNKNOWN_2153: 0 00054a24: 0000: 00012152 00000000 00000000 t0 write UNKNOWN_2156 (2156) UNKNOWN_2156: 0 00054a30: 0000: 00002156 00000000 t0 write UNKNOWN_2154 (2154) UNKNOWN_2154: 0 00054a38: 0000: 00002154 00000000 t0 write UNKNOWN_2155 (2155) UNKNOWN_2155: 0 00054a40: 0000: 00002155 00000000 t0 write UNKNOWN_21C3 (21c3) UNKNOWN_21C3: 0x1d 00054a48: 0000: 000021c3 0000001d t0 write PC_PRIM_VTX_CNTL2 (21c5) PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 00054a50: 0000: 000021c5 00000012 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 00054a58: 0000: 000021e5 00000000 t0 write GRAS_SU_MODE_CONTROL (2078) GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } 00054a60: 0000: 00002078 00000000 t0 write UNKNOWN_2001 (2001) UNKNOWN_2001: 0 00054a68: 0000: 00002001 00000000 t0 write GRAS_CNTL (2003) GRAS_CNTL: { IJ_PERSP } 00054a70: 0000: 00002003 00000001 t0 write GRAS_CL_CLIP_CNTL (2000) GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } 00054a78: 0000: 00002000 00188000 t0 write TPL1_TP_TEX_COUNT (2381) TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } 00054a80: 0000: 00002381 00000000 t0 write TPL1_TP_FS_TEX_COUNT (23a0) TPL1_TP_FS_TEX_COUNT: 0x3 00054a88: 0000: 000023a0 00000003 t0 write RB_ALPHA_CONTROL (20f8) RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } 00054a90: 0000: 000020f8 00000e00 t0 write RB_RENDER_COMPONENTS (20fb) RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } 00054a98: 0000: 000020fb 0000000f t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 00054aa0: 0000: c0014300 00040000 00000000 t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } 00054aac: 0000: 00002200 000a0000 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } 00054ab4: 0000: 00002201 fc030000 t0 write SP_INSTR_CACHE_CTRL (22c1) SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } 00054abc: 0000: 000022c1 000005c3 t0 write HLSQ_CONTROL_1_REG (23c1) HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } 00054ac4: 0000: 000023c1 fcfc0120 t0 write HLSQ_CONTROL_2_REG (23c2) HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 00054acc: 0000: 000023c2 27f3f3f0 t0 write HLSQ_VS_CONTROL_REG (23c5) HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } 00054ad4: 0000: 000023c5 02010042 t0 write HLSQ_FS_CONTROL_REG (23c6) HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00054adc: 0000: 000023c6 0041423e t0 write HLSQ_HS_CONTROL_REG (23c7) HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00054ae4: 0000: 000023c7 00404200 t0 write HLSQ_DS_CONTROL_REG (23c8) HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00054aec: 0000: 000023c8 00404200 t0 write HLSQ_GS_CONTROL_REG (23c9) HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00054af4: 0000: 000023c9 00404200 t0 write HLSQ_CS_CONTROL_REG (23ca) HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } 00054afc: 0000: 000023ca 00004200 t0 write SP_SP_CTRL_REG (22c0) SP_SP_CTRL_REG: { 0x60010 } 00054b04: 0000: 000022c0 00060010 t0 write UNKNOWN_21E6 (21e6) UNKNOWN_21E6: 0x1 00054b0c: 0000: 000021e6 00000001 t0 write SP_VS_CTRL_REG0 (22c4) SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 00054b14: 0000: 000022c4 00200c10 t0 write SP_VS_CTRL_REG1 (22c5) SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } 00054b1c: 0000: 000022c5 01000042 t0 write VPC_ATTR (2140) VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | 0x40000000 } 00054b24: 0000: 00002140 40001004 t0 write VPC_PACK (2141) VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } 00054b2c: 0000: 00002141 00040400 t0 write PC_PRIM_VTX_CNTL (21c4) PC_PRIM_VTX_CNTL: { VAROUT = 1 } 00054b34: 0000: 000021c4 00000001 t0 write SP_VS_PARAM_REG (22c6) SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } UNKNOWN_22D7: 0xfcfc00 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 00054b3c: 0000: 001922c6 0010fc03 00001e03 00000000 00000000 00000000 00000000 00000000 * 00054b7c: 0040: 00000000 00000000 00fcfc00 00000008 00000000 00000000 00000000 00000000 * t0 write SP_VS_OBJ_OFFSET_REG (22e0) SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 00054ba8: 0000: 000022e0 00000000 t0 write SP_VS_OBJ_START (22e1) SP_VS_OBJ_START: 0x1 00054bb0: 0000: 000022e1 00000001 t0 write SP_VS_LENGTH_REG (22e5) SP_VS_LENGTH_REG: 2 00054bb8: 0000: 000022e5 00000002 t3 opcode: CP_LOAD_STATE4 (30) (67 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } :2:0000:0000[56d81803x_20020003x] (sy)(ss)(nop3) shl.b r0.w, r0.w, 2 :1:0001:0004[20150000x_00000003x] cov.s32s16 hr0.x, r0.w :0:0002:0005[00000200x_00000000x] (rpt2)nop :1:0003:0008[201100f4x_00000000x] mova a0.x, hr0.x :0:0004:0009[00000500x_00000000x] (rpt5)nop :1:0005:0015[20154003x_00000c20x] mov.s32s32 r0.w, c :1:0006:0016[20154004x_00000c21x] mov.s32s32 r1.x, c :1:0007:0017[20154005x_00000c22x] mov.s32s32 r1.y, c :1:0008:0018[20156006x_00000c23x] (ul)mov.s32s32 r1.z, c :0:0009:0019[03000000x_00000000x] end :2:0010:0020[46f00007x_20050000x] shr.b r1.w, r0.x, 5 :2:0011:0021[43980008x_201f0000x] (nop2) and.b r2.x, r0.x, 31 :2:0012:0024[43980807x_201f0007x] (nop3) and.b r1.w, r1.w, 31 :2:0013:0028[46100807x_20100007x] (nop1) mul.u24 r1.w, r1.w, 16 :3:0014:0030[62040007x_00071014x] mad.u24 r1.w, c5.x, r2.x, r1.w :0:0015:0031[00000500x_00000000x] (rpt5)nop :6:0016:0037[c2c60f00x_04800006x] stlw.u32 l[r1.w], r0.w, 4 :0:0017:0038[04800000x_00000000x] chmask :0:0018:0039[05000000x_00000000x] chsh Stats: - shaderdb: 40 instr, 24 nops, 16 non-nops, 5 mov, 1 cov - shaderdb: 0 last-baryf, 0 half, 2 full, 5 constlen - shaderdb: 27 cat0, 6 cat1, 5 cat2, 1 cat3, 0 cat4, 0 cat5, 1 cat6, 0 cat7 - shaderdb: 0 sstall, 1 (ss), 1 (sy) 00054bc0: 0000: c0413000 00a00000 00000000 20020003 56d81803 00000003 20150000 00000000 00054be0: 0020: 00000200 00000000 201100f4 00000000 00000500 00000c20 20154003 00000c21 00054c00: 0040: 20154004 00000c22 20154005 00000c23 20156006 00000000 03000000 20050000 00054c20: 0060: 46f00007 201f0000 43980008 201f0007 43980807 20100007 46100807 00071014 00054c40: 0080: 62040007 00000000 00000500 04800006 c2c60f00 00000000 04800000 00000000 00054c60: 00a0: 05000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 * t0 write GRAS_ALPHA_CONTROL (2073) GRAS_ALPHA_CONTROL: { 0x2 } 00054ccc: 0000: 00002073 00000002 t0 write GRAS_SC_CONTROL (207b) GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = 4 | MSAA_DISABLE | RASTER_MODE = 0 } 00054cd4: 0000: 0000207b 00000a08 t0 write RB_MSAA_CONTROL (20a2) RB_MSAA_CONTROL: { DISABLE | SAMPLES = 4 } 00054cdc: 0000: 000020a2 00009000 t0 write RB_RENDER_CONTROL (20a1) RB_RENDER_CONTROL: { DISABLE_COLOR_PIPE | 0x2 } 00054ce4: 0000: 000020a1 00000022 t0 write RB_CLEAR_COLOR_DW0 (20cc) RB_CLEAR_COLOR_DW0: 0xff000000 RB_CLEAR_COLOR_DW1: 0 RB_CLEAR_COLOR_DW2: 0 RB_CLEAR_COLOR_DW3: 0 00054cec: 0000: 000320cc ff000000 00000000 00000000 00000000 t0 write RB_COPY_CONTROL (20fc) RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_FOUR | MODE = RB_COPY_CLEAR | FASTCLEAR = 0xf | GMEM_BASE = 0 } RB_COPY_DEST_BASE: { BASE = 0x4f000 } RB_COPY_DEST_PITCH: { PITCH = 256 } RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_IF_ALPHA_OFF | COMPONENT_ENABLE = 0 | ENDIAN = ENDIAN_NONE | TILE = TILE4_3 } 00054d00: 0000: 000320fc 00000f22 0004f000 00000008 03000868 t0 write GRAS_SC_SCREEN_SCISSOR_TL (207c) GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } 00054d14: 0000: 0001207c 00000000 003f003f t0 write RB_FRAME_BUFFER_DIMENSION (0ce0) RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } 00054d20: 0000: 00000ce0 00400040 t0 write 0xce1 (0ce1) 0xce1: 00000000 00054d28: 0000: 00000ce1 00000000 t3 opcode: CP_LOAD_STATE4 (30) (11 dwords) { DST_OFF = 8 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } 00054d3c: 0.000000 0.000000 1.000000 1.000000 64.000000 64.000000 1.000000 1.000000 00054d3c: 0000: 00000000 00000000 3f800000 3f800000 42800000 42800000 3f800000 3f800000 00054d30: 0000: c0093000 00a00008 00000001 00000000 00000000 3f800000 3f800000 42800000 00054d50: 0020: 42800000 3f800000 3f800000 t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x80000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 2 } draw[80] register values + 00000004 UNKNOWN_0CC5: 0x4 + 00000000 UNKNOWN_0CC6: 0 + 00400040 RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } + 00000000 0xce1: 00000000 + 00000002 HLSQ_MODE_CONTROL: 0x2 + 00000000 UNKNOWN_0E42: 0 + 00000000 UCHE_INVALIDATE0: 0 + 00000012 UCHE_INVALIDATE1: 0x12 + 00000004 SP_MODE_CONTROL: 0x4 + 00000068 TPL1_TP_MODE_CONTROL: 0x68 + 00188000 GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } + 00000000 UNKNOWN_2001: 0 + 00000001 GRAS_CNTL: { IJ_PERSP } !+ 00000002 GRAS_ALPHA_CONTROL: { 0x2 } + 00000000 GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } !+ 00000a08 GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = 4 | MSAA_DISABLE | RASTER_MODE = 0 } + 00000000 GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } + 003f003f GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } + 003f003f GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } + 00000000 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } !+ 00010202 RB_MODE_CONTROL: { WIDTH = 64 | HEIGHT = 64 | ENABLE_GMEM } !+ 00000022 RB_RENDER_CONTROL: { DISABLE_COLOR_PIPE | 0x2 } !+ 00009000 RB_MSAA_CONTROL: { DISABLE | SAMPLES = 4 } + ff000000 RB_CLEAR_COLOR_DW0: 0xff000000 + 00000000 RB_CLEAR_COLOR_DW1: 0 + 00000000 RB_CLEAR_COLOR_DW2: 0 + 00000000 RB_CLEAR_COLOR_DW3: 0 + 00000e00 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } + 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } !+ 00000f22 RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_FOUR | MODE = RB_COPY_CLEAR | FASTCLEAR = 0xf | GMEM_BASE = 0 } + 0004f000 RB_COPY_DEST_BASE: { BASE = 0x4f000 } + 00000008 RB_COPY_DEST_PITCH: { PITCH = 256 } !+ 03000868 RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_IF_ALPHA_OFF | COMPONENT_ENABLE = 0 | ENDIAN = ENDIAN_NONE | TILE = TILE4_3 } + 00000000 RB_BIN_OFFSET: { X = 0 | Y = 0 } !+ 40001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | 0x40000000 } !+ 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } + 00000000 UNKNOWN_2152: 0 + 00000000 UNKNOWN_2153: 0 + 00000000 UNKNOWN_2154: 0 + 00000000 UNKNOWN_2155: 0 + 00000000 UNKNOWN_2156: 0 + 00000001 UNKNOWN_2157: 0x1 + 0000001d UNKNOWN_21C3: 0x1d + 00000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 } + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + 00000000 PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } + 00000001 UNKNOWN_21E6: 0x1 + 000a0000 VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } + fc030000 VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } + fcfcfcfc VFD_CONTROL_2: 0xfcfcfcfc + fcfcfc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } + 0000fcfc VFD_CONTROL_4: 0xfcfc + 00000000 VFD_INDEX_OFFSET: 0 + 00000000 UNKNOWN_2209: 0 + 00060010 SP_SP_CTRL_REG: { 0x60010 } + 000005c3 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } + 00200c10 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } + 01000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } !+ 0010fc03 SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } !+ 00001e03 SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00fcfc00 UNKNOWN_22D7: 0xfcfc00 !+ 00000008 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } + 00000001 SP_VS_OBJ_START: 0x1 + 00000002 SP_VS_LENGTH_REG: 2 + 00000000 TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } + 00000003 TPL1_TP_FS_TEX_COUNT: 0x3 + 080004f0 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } + fcfc0120 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } + 27f3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } + 02010042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } !+ 0041423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00004200 HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } + 00000007 HLSQ_UPDATE_CONTROL: 0x7 00054d5c: 0000: c0023800 00080888 00000001 00000002 0016b07c: 0000: c0013f00 00054994 000000f6 t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:00054d6c ibsize:00000037 t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } 00054d6c: 0000: 00002200 082a0008 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00054d74: 0000: c0002600 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x1e 00054d7c: 0000: 00000ec3 0000001e t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x28 00054d84: 0000: 00000f03 00000028 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00054d8c: 0000: c0002600 00000000 t0 write HLSQ_MODE_CONTROL (0e05) HLSQ_MODE_CONTROL: 0x1 00054d94: 0000: 00000e05 00000001 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0x600a0 } 00054d9c: 0000: 000023c0 080604f0 t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x7 00054da4: 0000: 000023db 00000007 t0 write PC_RESTART_INDEX (21c6) PC_RESTART_INDEX: 0xffffffff 00054dac: 0000: 000021c6 ffffffff t0 write UNKNOWN_21E6 (21e6) UNKNOWN_21E6: 0x1 00054db4: 0000: 000021e6 00000001 t0 write UNKNOWN_21C3 (21c3) UNKNOWN_21C3: 0x1f 00054dbc: 0000: 000021c3 0000001f t0 write TPL1_TP_TEX_OFFSET (2380) TPL1_TP_TEX_OFFSET: 0x808 00054dc4: 0000: 00002380 00000808 t0 write GRAS_SU_POINT_MINMAX (2070) GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 4092.000000 } GRAS_SU_POINT_SIZE: 0.500000 00054dcc: 0000: 00012070 ffc00010 00000008 t0 write UNKNOWN_2152 (2152) UNKNOWN_2152: 0 UNKNOWN_2153: 0 00054dd8: 0000: 00012152 00000000 00000000 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00054de4: 0000: c0002600 00000000 t0 write UNKNOWN_0CC5 (0cc5) UNKNOWN_0CC5: 0x4 00054dec: 0000: 00000cc5 00000004 t0 write 0xcc4 (0cc4) 0xcc4: 00000000 00054df4: 0000: 00000cc4 00000000 t0 write 0xd03 (0d03) 0xd03: 80200000 00054dfc: 0000: 00000d03 80200000 t0 write UNKNOWN_0EC2 (0ec2) UNKNOWN_0EC2: 0x40000 00054e04: 0000: 00000ec2 00040000 t0 write VPC_DEBUG_ECO_CONTROL (0e64) VPC_DEBUG_ECO_CONTROL: 0x100 00054e0c: 0000: 00000e64 00000100 t0 write UNKNOWN_0E42 (0e42) UNKNOWN_0E42: 0 00054e14: 0000: 00000e42 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x1e 00054e1c: 0000: 00000ec3 0000001e t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x28 00054e24: 0000: 00000f03 00000028 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 00054e2c: 0000: c0014300 00040000 00000000 t0 write VFD_INDEX_OFFSET (2208) VFD_INDEX_OFFSET: 0 00054e38: 0000: 00002208 00000000 t0 write UNKNOWN_2209 (2209) UNKNOWN_2209: 0 00054e40: 0000: 00002209 00000000 0016b088: 0000: c0013f00 00054d6c 00000037 t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:00055328 ibsize:000000ac t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x3 00055328: 0000: 000023db 00000003 t0 write SP_INSTR_CACHE_CTRL (22c1) SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } 00055330: 0000: 000022c1 000005c3 t0 write HLSQ_CONTROL_1_REG (23c1) HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x1008 } 00055338: 0000: 000023c1 fcfc1108 t0 write HLSQ_CONTROL_2_REG (23c2) HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 00055340: 0000: 000023c2 fff3f3f0 t0 write HLSQ_VS_CONTROL_REG (23c5) HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 2 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 1 } 00055348: 0000: 000023c5 01010002 t0 write HLSQ_HS_CONTROL_REG (23c7) HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 00055350: 0000: 000023c7 007e0200 t0 write HLSQ_DS_CONTROL_REG (23c8) HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 00055358: 0000: 000023c8 007e0200 t0 write HLSQ_GS_CONTROL_REG (23c9) HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 00055360: 0000: 000023c9 007e0200 t0 write HLSQ_FS_CONTROL_REG (23c6) HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 2 | CONSTOBJECTOFFSET = 2 | ENABLED | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 } 00055368: 0000: 000023c6 017f0202 t0 write SP_VS_OBJ_OFFSET_REG (22e0) SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 00055370: 0000: 000022e0 00000000 t0 write SP_HS_OBJ_OFFSET_REG (230d) SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } 00055378: 0000: 0000230d 7e020000 t0 write SP_DS_OBJ_OFFSET_REG (2334) SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } 00055380: 0000: 00002334 7e020000 t0 write SP_GS_OBJ_OFFSET_REG (235b) SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } 00055388: 0000: 0000235b 7e020000 t0 write SP_FS_OBJ_OFFSET_REG (22ea) SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } 00055390: 0000: 000022ea 7e020000 t0 write SP_VS_OBJ_START (22e1) SP_VS_OBJ_START: 0x49000 00049000: 0000: 00000000 13000000 00000000 00000000 00000000 00000000 00000000 00000000 * :0:0000:0000[13000000x_00000000x] (sy)end :0:0001:0001[00000000x_00000000x] nop :0:0002:0002[00000000x_00000000x] nop :0:0003:0003[00000000x_00000000x] nop :0:0004:0004[00000000x_00000000x] nop Stats: - shaderdb: 5 instr, 4 nops, 1 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 0 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 0 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) 00055398: 0000: 000022e1 00049000 t0 write SP_HS_OBJ_START (230e) SP_HS_OBJ_START: 0 000553a0: 0000: 0000230e 00000000 t0 write SP_DS_OBJ_START (2335) SP_DS_OBJ_START: 0 000553a8: 0000: 00002335 00000000 t0 write SP_GS_OBJ_START (235c) SP_GS_OBJ_START: 0 000553b0: 0000: 0000235c 00000000 t0 write SP_VS_LENGTH_REG (22e5) SP_VS_LENGTH_REG: 1 000553b8: 0000: 000022e5 00000001 t3 opcode: CP_LOAD_STATE4 (30) (3 dwords) { DST_OFF = 0 | STATE_SRC = SS4_INDIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 1 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0x49000 } :0:0000:0000[13000000x_00000000x] (sy)end :0:0001:0001[00000000x_00000000x] nop :0:0002:0002[00000000x_00000000x] nop :0:0003:0003[00000000x_00000000x] nop :0:0004:0004[00000000x_00000000x] nop Stats: - shaderdb: 5 instr, 4 nops, 1 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 0 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 0 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) 000553c0: 0000: c0013000 00620000 00049000 t0 write 0x2072 (2072) 0x2072: 00000000 000553cc: 0000: 00002072 00000000 t0 write UNKNOWN_2155 (2155) UNKNOWN_2155: 0 000553d4: 0000: 00002155 00000000 t0 write GRAS_CNTL (2003) GRAS_CNTL: { IJ_PERSP } 000553dc: 0000: 00002003 00000001 t0 write VPC_VARYING_INTERP[0].MODE (2142) VPC_VARYING_INTERP[0].MODE: 0 000553e4: 0000: 00002142 00000000 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0x600a0 } 000553ec: 0000: 000023c0 080604f0 t0 write HLSQ_CONTROL_3_REG (23c3) HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } 000553f4: 0000: 000023c3 fcfcfc00 t0 write HLSQ_CONTROL_4_REG (23c4) HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r0.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } 000553fc: 0000: 000023c4 00fcfc00 t0 write SP_FS_CTRL_REG0 (22e8) SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE } SP_FS_CTRL_REG1: { CONSTLENGTH = 2 | VARYING | 0x80000000 } 00055404: 0000: 000122e8 00340412 80100002 t0 write SP_FS_OBJ_START (22eb) SP_FS_OBJ_START: 0x46000 00046000: 0000: 00002000 5730cb00 00000000 03000000 00000000 00000000 00000000 00000000 * :2:0000:0000[5730cb00x_00002000x] (sy)(rpt3)bary.f (ei)hr0.x, (r)0, r0.x :0:0001:0004[03000000x_00000000x] end :0:0002:0005[00000000x_00000000x] nop :0:0003:0006[00000000x_00000000x] nop :0:0004:0007[00000000x_00000000x] nop :0:0005:0008[00000000x_00000000x] nop Stats: - shaderdb: 9 instr, 4 nops, 5 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 1 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 4 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) 00055410: 0000: 000022eb 00046000 t0 write SP_FS_LENGTH_REG (22ef) SP_FS_LENGTH_REG: 1 00055418: 0000: 000022ef 00000001 t0 write RB_RENDER_COMPONENTS (20fb) RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } 00055420: 0000: 000020fb 0000000f t3 opcode: CP_LOAD_STATE4 (30) (3 dwords) { DST_OFF = 0 | STATE_SRC = SS4_INDIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 1 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0x46000 } :2:0000:0000[5730cb00x_00002000x] (sy)(rpt3)bary.f (ei)hr0.x, (r)0, r0.x :0:0001:0004[03000000x_00000000x] end :0:0002:0005[00000000x_00000000x] nop :0:0003:0006[00000000x_00000000x] nop :0:0004:0007[00000000x_00000000x] nop :0:0005:0008[00000000x_00000000x] nop Stats: - shaderdb: 9 instr, 4 nops, 5 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 1 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 4 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) 00055428: 0000: c0013000 00720000 00046000 t0 write SP_SP_CTRL_REG (22c0) SP_SP_CTRL_REG: { 0x60010 } 00055434: 0000: 000022c0 00060010 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 28 | GROUP_ID = 3 } { ADDR_LO = 0x9c960 } 0005543c: 0000: c0014300 0300001c 0009c960 t0 write RB_DEPTH_INFO (2103) RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTH4_NONE | DEPTH_BASE = 0 } RB_DEPTH_PITCH: 0 RB_DEPTH_PITCH2: 0 00055448: 0000: 00022103 00000000 00000000 00000000 t0 write GRAS_DEPTH_CONTROL (2077) GRAS_DEPTH_CONTROL: { FORMAT = DEPTH4_NONE } 00055458: 0000: 00002077 00000000 t0 write RB_STENCIL_INFO (2108) RB_STENCIL_INFO: { STENCIL_BASE = 0 } RB_STENCIL_PITCH: 0 0x210a: 00000000 00055460: 0000: 00022108 00000000 00000000 00000000 t0 write 0x2002 (2002) 0x2002: 00000000 00055470: 0000: 00002002 00000000 t0 write RB_ALPHA_CONTROL (20f8) RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } 00055478: 0000: 000020f8 00000e00 t0 write RB_MRT[0].CONTROL (20a4) RB_MRT[0].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0x7 } 00055480: 0000: 000020a4 07000c00 t0 write RB_MRT[0].BLEND_CONTROL (20a8) RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } 00055488: 0000: 000020a8 00000000 t0 write GRAS_CL_CLIP_CNTL (2000) GRAS_CL_CLIP_CNTL: { 0x80000 } 00055490: 0000: 00002000 00080000 t0 write GRAS_SU_POLY_OFFSET_SCALE (2074) GRAS_SU_POLY_OFFSET_SCALE: 0.000000 GRAS_SU_POLY_OFFSET_OFFSET: 0.000000 GRAS_SU_POLY_OFFSET_CLAMP: 0.000000 00055498: 0000: 00022074 00000000 00000000 00000000 t0 write GRAS_SU_MODE_CONTROL (2078) GRAS_SU_MODE_CONTROL: { FRONT_CW | LINEHALFWIDTH = 0.500000 | MSAA_ENABLE | RENDERING_PASS } 000554a8: 0000: 00002078 00102014 t0 write GRAS_SC_SCREEN_SCISSOR_TL (207c) GRAS_SC_SCREEN_SCISSOR_TL: { X = 2 | Y = 13 } GRAS_SC_SCREEN_SCISSOR_BR: { X = 33 | Y = 44 } 000554b0: 0000: 0001207c 000d0002 002c0021 t0 write GRAS_CL_VPORT_XOFFSET_0 (2008) GRAS_CL_VPORT_XOFFSET_0: 18.000000 GRAS_CL_VPORT_XSCALE_0: 16.000000 GRAS_CL_VPORT_YOFFSET_0: 29.000000 GRAS_CL_VPORT_YSCALE_0: 16.000000 GRAS_CL_VPORT_ZOFFSET_0: 0.500000 GRAS_CL_VPORT_ZSCALE_0: 0.500000 000554bc: 0000: 00052008 41900000 41800000 41e80000 41800000 3f000000 3f000000 t0 write GRAS_CL_GB_CLIP_ADJ (2004) GRAS_CL_GB_CLIP_ADJ: { HORZ = 511 | VERT = 511 } 000554d8: 0000: 00002004 0007fdff t0 write GRAS_SC_CONTROL (207b) GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 4 | RASTER_MODE = 0 } 000554e0: 0000: 0000207b 00000200 t0 write 0x2382 (2382) 0x2382: 00000002 000554e8: 0000: 00002382 00000002 t0 write RB_MSAA_CONTROL (20a2) RB_MSAA_CONTROL: { SAMPLES = 4 } 000554f0: 0000: 000020a2 00008000 t0 write RB_RENDER_CONTROL2 (20a3) RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 4 | IJ_PERSP_PIXEL } 000554f8: 0000: 000020a3 00001200 t0 write RB_MRT[0].BUF_INFO (20a5) RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB4_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_ALWAYS | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 1024 } RB_MRT[0].BASE: 0 RB_MRT[0].CONTROL3: { STRIDE = 64 } 00055500: 0000: 000220a5 0010029a 00000000 00000200 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 43 | GROUP_ID = 2 } { ADDR_LO = 0x9c9d0 } 00055510: 0000: c0014300 0200002b 0009c9d0 t0 write 0x215c (215c) 0x215c: 00000000 0x215d: 00000000 0005551c: 0000: 0001215c 00000000 00000000 t0 write 0x215f (215f) 0x215f: 00000000 00055528: 0000: 0000215f 00000000 t0 write 0x215e (215e) 0x215e: 00000000 00055530: 0000: 0000215e 00000000 t0 write 0x2161 (2161) 0x2161: 00000000 0x2162: 00000000 00055538: 0000: 00012161 00000000 00000000 t0 write 0x2164 (2164) 0x2164: 00000000 00055544: 0000: 00002164 00000000 t0 write 0x2163 (2163) 0x2163: 00000000 0005554c: 0000: 00002163 00000000 t0 write 0x2166 (2166) 0x2166: 00000000 0x2167: 00000000 00055554: 0000: 00012166 00000000 00000000 t0 write 0x2169 (2169) 0x2169: 00000000 00055560: 0000: 00002169 00000000 t0 write 0x2168 (2168) 0x2168: 00000000 00055568: 0000: 00002168 00000000 t0 write 0x216b (216b) 0x216b: 00000000 0x216c: 00000000 00055570: 0000: 0001216b 00000000 00000000 t0 write VPC_SO_FLUSH_WADDR_3 (216e) VPC_SO_FLUSH_WADDR_3: 0 0005557c: 0000: 0000216e 00000000 t0 write 0x216d (216d) 0x216d: 00000000 00055584: 0000: 0000216d 00000000 t0 write UNKNOWN_2156 (2156) UNKNOWN_2156: 0 0005558c: 0000: 00002156 00000000 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 18 | GROUP_ID = 1 } { ADDR_LO = 0x9ca80 } 00055594: 0000: c0014300 01000012 0009ca80 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 15 | GROUP_ID = 0 } { ADDR_LO = 0x9cad0 } 000555a0: 0000: c0014300 0000000f 0009cad0 group_id: 0 count: 15 addr: 000000000009cad0 flags: 0 0009cad0: 0000: 00002073 00000000 00002101 00000000 00002106 00000000 000021e5 00000000 0009caf0: 0020: 0001210b 00000000 00000000 00002381 00000000 000023a0 00000000 t0 write GRAS_ALPHA_CONTROL (2073) GRAS_ALPHA_CONTROL: { 0 } 0009cad0: 0000: 00002073 00000000 t0 write RB_DEPTH_CONTROL (2101) RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } 0009cad8: 0000: 00002101 00000000 t0 write RB_STENCIL_CONTROL (2106) RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } 0009cae0: 0000: 00002106 00000000 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 0009cae8: 0000: 000021e5 00000000 t0 write RB_STENCILREFMASK (210b) RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 0009caf0: 0000: 0001210b 00000000 00000000 t0 write TPL1_TP_TEX_COUNT (2381) TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } 0009cafc: 0000: 00002381 00000000 t0 write TPL1_TP_FS_TEX_COUNT (23a0) TPL1_TP_FS_TEX_COUNT: 0 0009cb04: 0000: 000023a0 00000000 group_id: 1 count: 18 addr: 000000000009ca80 flags: 0 0009ca80: 0000: 00002200 082a0008 00002201 fcfc0081 00002203 0000fc00 0007220a 0008080f 0009caa0: 0020: 0009c900 00000060 00000001 0000080f 0009c930 00000030 00000001 0001228a 0009cac0: 0040: 7000411f 3000011f t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } 0009ca80: 0000: 00002200 082a0008 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } 0009ca88: 0000: 00002201 fcfc0081 t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } 0009ca90: 0000: 00002203 0000fc00 t0 write VFD_FETCH[0].INSTR_0 (220a) VFD_FETCH[0].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 | SWITCHNEXT } VFD_FETCH[0].INSTR_1: 0x9c900 VFD_FETCH[0].INSTR_2: { SIZE = 0x60 } VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 } VFD_FETCH[0x1].INSTR_1: 0x9c930 VFD_FETCH[0x1].INSTR_2: { SIZE = 0x30 } VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } 0009ca98: 0000: 0007220a 0008080f 0009c900 00000060 00000001 0000080f 0009c930 00000030 0009cab8: 0020: 00000001 t0 write VFD_DECODE[0].INSTR (228a) VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID | SWITCHNEXT } VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID } 0009cabc: 0000: 0001228a 7000411f 3000011f group_id: 2 count: 43 addr: 000000000009c9d0 flags: 0 0009c9d0: 0000: 000020a1 00000000 000022f1 0001a100 000022f0 fc00fc01 00002100 00000001 0009c9f0: 0020: 000021e5 00000000 000020f9 ffff0501 0000214a 00000000 00002140 42001004 0009ca10: 0040: 001922c6 0010fc04 00001e00 00000000 00000000 00000000 00000000 00000000 * 0009ca50: 0080: 00000000 00000000 00fcfc00 00000008 00000000 00000000 00000000 00000000 * t0 write RB_RENDER_CONTROL (20a1) RB_RENDER_CONTROL: { 0 } 0009c9d0: 0000: 000020a1 00000000 t0 write SP_FS_MRT[0].REG (22f1) SP_FS_MRT[0].REG: { REGID = r0.x | HALF_PRECISION | MRTFORMAT = RB4_R8G8B8A8_UNORM } 0009c9d8: 0000: 000022f1 0001a100 t0 write SP_FS_OUTPUT_REG (22f0) SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 0009c9e0: 0000: 000022f0 fc00fc01 t0 write RB_FS_OUTPUT_REG (2100) RB_FS_OUTPUT_REG: { MRT = 1 } 0009c9e8: 0000: 00002100 00000001 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 0009c9f0: 0000: 000021e5 00000000 t0 write RB_FS_OUTPUT (20f9) RB_FS_OUTPUT: { ENABLE_BLEND = 0x1 | INDEPENDENT_BLEND | SAMPLE_MASK = 0xffff | 0x400 } 0009c9f8: 0000: 000020f9 ffff0501 t0 write VPC_VARYING_PS_REPL[0].MODE (214a) VPC_VARYING_PS_REPL[0].MODE: 0 0009ca00: 0000: 0000214a 00000000 t0 write VPC_ATTR (2140) VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 } 0009ca08: 0000: 00002140 42001004 t0 write SP_VS_PARAM_REG (22c6) SP_VS_PARAM_REG: { POSREGID = r1.x | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } SP_VS_OUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } UNKNOWN_22D7: 0xfcfc00 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 0009ca10: 0000: 001922c6 0010fc04 00001e00 00000000 00000000 00000000 00000000 00000000 * 0009ca50: 0040: 00000000 00000000 00fcfc00 00000008 00000000 00000000 00000000 00000000 * group_id: 3 count: 28 addr: 000000000009c960 flags: 0 0009c960: 0000: 000021c4 02000001 00002141 00040400 00002001 00000000 000022c4 00200800 0009c980: 0020: 000022c5 08000002 0000230c 00000000 00002318 00000000 00002319 00000000 0009c9a0: 0040: 00002340 00000000 00002202 fcfcfcfc 00002204 0000fcfc 00002154 00000000 0009c9c0: 0060: 000021e7 00000000 000021c5 00000012 t0 write PC_PRIM_VTX_CNTL (21c4) PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } 0009c960: 0000: 000021c4 02000001 t0 write VPC_PACK (2141) VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } 0009c968: 0000: 00002141 00040400 t0 write UNKNOWN_2001 (2001) UNKNOWN_2001: 0 0009c970: 0000: 00002001 00000000 t0 write SP_VS_CTRL_REG0 (22c4) SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 2 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 0009c978: 0000: 000022c4 00200800 t0 write SP_VS_CTRL_REG1 (22c5) SP_VS_CTRL_REG1: { CONSTLENGTH = 2 | INITIALOUTSTANDING = 8 } 0009c980: 0000: 000022c5 08000002 t0 write 0x230c (230c) 0x230c: 00000000 0009c988: 0000: 0000230c 00000000 t0 write 0x2318 (2318) 0x2318: 00000000 0009c990: 0000: 00002318 00000000 t0 write 0x2319 (2319) 0x2319: 00000000 0009c998: 0000: 00002319 00000000 t0 write 0x2340 (2340) 0x2340: 00000000 0009c9a0: 0000: 00002340 00000000 t0 write VFD_CONTROL_2 (2202) VFD_CONTROL_2: 0xfcfcfcfc 0009c9a8: 0000: 00002202 fcfcfcfc t0 write VFD_CONTROL_4 (2204) VFD_CONTROL_4: 0xfcfc 0009c9b0: 0000: 00002204 0000fcfc t0 write UNKNOWN_2154 (2154) UNKNOWN_2154: 0 0009c9b8: 0000: 00002154 00000000 t0 write PC_HS_PARAM (21e7) PC_HS_PARAM: { VERTICES_OUT = 0 | SPACING = EQUAL_SPACING } 0009c9c0: 0000: 000021e7 00000000 t0 write PC_PRIM_VTX_CNTL2 (21c5) PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 0009c9c8: 0000: 000021c5 00000012 t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = USE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x200000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 3 } draw[81] register values + 00000000 0xcc4: 00000000 + 00000004 UNKNOWN_0CC5: 0x4 + 80200000 0xd03: 80200000 !+ 00000001 HLSQ_MODE_CONTROL: 0x1 + 00000000 UNKNOWN_0E42: 0 + 00000100 VPC_DEBUG_ECO_CONTROL: 0x100 + 00040000 UNKNOWN_0EC2: 0x40000 !+ 0000001e SP_MODE_CONTROL: 0x1e !+ 00000028 TPL1_TP_MODE_CONTROL: 0x28 !+ 00080000 GRAS_CL_CLIP_CNTL: { 0x80000 } + 00000000 UNKNOWN_2001: 0 + 00000000 0x2002: 00000000 + 00000001 GRAS_CNTL: { IJ_PERSP } + 0007fdff GRAS_CL_GB_CLIP_ADJ: { HORZ = 511 | VERT = 511 } + 41900000 GRAS_CL_VPORT_XOFFSET_0: 18.000000 + 41800000 GRAS_CL_VPORT_XSCALE_0: 16.000000 + 41e80000 GRAS_CL_VPORT_YOFFSET_0: 29.000000 + 41800000 GRAS_CL_VPORT_YSCALE_0: 16.000000 + 3f000000 GRAS_CL_VPORT_ZOFFSET_0: 0.500000 + 3f000000 GRAS_CL_VPORT_ZSCALE_0: 0.500000 + ffc00010 GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 4092.000000 } + 00000008 GRAS_SU_POINT_SIZE: 0.500000 + 00000000 0x2072: 00000000 !+ 00000000 GRAS_ALPHA_CONTROL: { 0 } + 00000000 GRAS_SU_POLY_OFFSET_SCALE: 0.000000 + 00000000 GRAS_SU_POLY_OFFSET_OFFSET: 0.000000 + 00000000 GRAS_SU_POLY_OFFSET_CLAMP: 0.000000 + 00000000 GRAS_DEPTH_CONTROL: { FORMAT = DEPTH4_NONE } !+ 00102014 GRAS_SU_MODE_CONTROL: { FRONT_CW | LINEHALFWIDTH = 0.500000 | MSAA_ENABLE | RENDERING_PASS } !+ 00000200 GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 4 | RASTER_MODE = 0 } !+ 000d0002 GRAS_SC_SCREEN_SCISSOR_TL: { X = 2 | Y = 13 } !+ 002c0021 GRAS_SC_SCREEN_SCISSOR_BR: { X = 33 | Y = 44 } !+ 00000000 RB_RENDER_CONTROL: { 0 } !+ 00008000 RB_MSAA_CONTROL: { SAMPLES = 4 } !+ 00001200 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 4 | IJ_PERSP_PIXEL } !+ 07000c00 RB_MRT[0].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0x7 } !+ 0010029a RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB4_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_ALWAYS | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 1024 } !+ 00000000 RB_MRT[0].BASE: 0 !+ 00000200 RB_MRT[0].CONTROL3: { STRIDE = 64 } + 00000000 RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } + 00000e00 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } !+ ffff0501 RB_FS_OUTPUT: { ENABLE_BLEND = 0x1 | INDEPENDENT_BLEND | SAMPLE_MASK = 0xffff | 0x400 } + 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } + 00000001 RB_FS_OUTPUT_REG: { MRT = 1 } + 00000000 RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } + 00000000 RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTH4_NONE | DEPTH_BASE = 0 } + 00000000 RB_DEPTH_PITCH: 0 + 00000000 RB_DEPTH_PITCH2: 0 + 00000000 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } + 00000000 RB_STENCIL_INFO: { STENCIL_BASE = 0 } + 00000000 RB_STENCIL_PITCH: 0 + 00000000 0x210a: 00000000 + 00000000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } + 00000000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } !+ 42001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 } + 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } !+ 00000000 VPC_VARYING_INTERP[0].MODE: 0 !+ 00000000 VPC_VARYING_PS_REPL[0].MODE: 0 + 00000000 UNKNOWN_2152: 0 + 00000000 UNKNOWN_2153: 0 + 00000000 UNKNOWN_2154: 0 + 00000000 UNKNOWN_2155: 0 + 00000000 UNKNOWN_2156: 0 + 00000000 0x215c: 00000000 + 00000000 0x215d: 00000000 + 00000000 0x215e: 00000000 + 00000000 0x215f: 00000000 + 00000000 0x2161: 00000000 + 00000000 0x2162: 00000000 + 00000000 0x2163: 00000000 + 00000000 0x2164: 00000000 + 00000000 0x2166: 00000000 + 00000000 0x2167: 00000000 + 00000000 0x2168: 00000000 + 00000000 0x2169: 00000000 + 00000000 0x216b: 00000000 + 00000000 0x216c: 00000000 + 00000000 0x216d: 00000000 + 00000000 VPC_SO_FLUSH_WADDR_3: 0 !+ 0000001f UNKNOWN_21C3: 0x1f !+ 02000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + ffffffff PC_RESTART_INDEX: 0xffffffff + 00000000 PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } + 00000001 UNKNOWN_21E6: 0x1 + 00000000 PC_HS_PARAM: { VERTICES_OUT = 0 | SPACING = EQUAL_SPACING } !+ 082a0008 VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } !+ fcfc0081 VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } + fcfcfcfc VFD_CONTROL_2: 0xfcfcfcfc !+ 0000fc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } + 0000fcfc VFD_CONTROL_4: 0xfcfc + 00000000 VFD_INDEX_OFFSET: 0 + 00000000 UNKNOWN_2209: 0 + 0008080f VFD_FETCH[0].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 | SWITCHNEXT } !+ 0009c900 VFD_FETCH[0].INSTR_1: 0x9c900 + 00000060 VFD_FETCH[0].INSTR_2: { SIZE = 0x60 } + 00000001 VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } + 0000080f VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 } !+ 0009c930 VFD_FETCH[0x1].INSTR_1: 0x9c930 + 00000030 VFD_FETCH[0x1].INSTR_2: { SIZE = 0x30 } + 00000001 VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } + 7000411f VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID | SWITCHNEXT } + 3000011f VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID } + 00060010 SP_SP_CTRL_REG: { 0x60010 } + 000005c3 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } !+ 00200800 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 2 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } !+ 08000002 SP_VS_CTRL_REG1: { CONSTLENGTH = 2 | INITIALOUTSTANDING = 8 } !+ 0010fc04 SP_VS_PARAM_REG: { POSREGID = r1.x | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } !+ 00001e00 SP_VS_OUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00fcfc00 UNKNOWN_22D7: 0xfcfc00 + 00000008 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } !+ 00049000 SP_VS_OBJ_START: 0x49000 00049000: 0000: 00000000 13000000 00000000 00000000 00000000 00000000 00000000 00000000 * :0:0000:0000[13000000x_00000000x] (sy)end :0:0001:0001[00000000x_00000000x] nop :0:0002:0002[00000000x_00000000x] nop :0:0003:0003[00000000x_00000000x] nop :0:0004:0004[00000000x_00000000x] nop Stats: - shaderdb: 5 instr, 4 nops, 1 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 0 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 0 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) !+ 00000001 SP_VS_LENGTH_REG: 1 !+ 00340412 SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE } !+ 80100002 SP_FS_CTRL_REG1: { CONSTLENGTH = 2 | VARYING | 0x80000000 } !+ 7e020000 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } !+ 00046000 SP_FS_OBJ_START: 0x46000 00046000: 0000: 00002000 5730cb00 00000000 03000000 00000000 00000000 00000000 00000000 * :2:0000:0000[5730cb00x_00002000x] (sy)(rpt3)bary.f (ei)hr0.x, (r)0, r0.x :0:0001:0004[03000000x_00000000x] end :0:0002:0005[00000000x_00000000x] nop :0:0003:0006[00000000x_00000000x] nop :0:0004:0007[00000000x_00000000x] nop :0:0005:0008[00000000x_00000000x] nop Stats: - shaderdb: 9 instr, 4 nops, 5 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 1 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 4 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) + 00000001 SP_FS_LENGTH_REG: 1 !+ fc00fc01 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r63.x } !+ 0001a100 SP_FS_MRT[0].REG: { REGID = r0.x | HALF_PRECISION | MRTFORMAT = RB4_R8G8B8A8_UNORM } + 00000000 0x230c: 00000000 + 7e020000 SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } + 00000000 SP_HS_OBJ_START: 0 + 00000000 0x2318: 00000000 + 00000000 0x2319: 00000000 + 7e020000 SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } + 00000000 SP_DS_OBJ_START: 0 + 00000000 0x2340: 00000000 + 7e020000 SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } + 00000000 SP_GS_OBJ_START: 0 + 00000808 TPL1_TP_TEX_OFFSET: 0x808 + 00000000 TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } !+ 00000002 0x2382: 00000002 !+ 00000000 TPL1_TP_FS_TEX_COUNT: 0 !+ 080604f0 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0x600a0 } !+ fcfc1108 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x1008 } !+ fff3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } + fcfcfc00 HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } !+ 00fcfc00 HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r0.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } !+ 01010002 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 2 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 1 } !+ 017f0202 HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 2 | CONSTOBJECTOFFSET = 2 | ENABLED | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 } !+ 007e0200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } !+ 007e0200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } !+ 007e0200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } !+ 00000003 HLSQ_UPDATE_CONTROL: 0x3 000555ac: 0000: c0023800 00200984 00000001 00000003 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 18 | GROUP_ID = 1 } { ADDR_LO = 0x9cc40 } 000555bc: 0000: c0014300 01000012 0009cc40 group_id: 1 count: 18 addr: 000000000009cc40 flags: 0 0009cc40: 0000: 00002200 082a0008 00002201 fcfc0081 00002203 0000fc00 0007220a 0008080f 0009cc60: 0020: 0009cbe0 00000060 00000001 0000080f 0009cc10 00000030 00000001 0001228a 0009cc80: 0040: 7000411f 3000011f t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } 0009cc40: 0000: 00002200 082a0008 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } 0009cc48: 0000: 00002201 fcfc0081 t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } 0009cc50: 0000: 00002203 0000fc00 t0 write VFD_FETCH[0].INSTR_0 (220a) VFD_FETCH[0].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 | SWITCHNEXT } VFD_FETCH[0].INSTR_1: 0x9cbe0 VFD_FETCH[0].INSTR_2: { SIZE = 0x60 } VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 } VFD_FETCH[0x1].INSTR_1: 0x9cc10 VFD_FETCH[0x1].INSTR_2: { SIZE = 0x30 } VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } 0009cc58: 0000: 0007220a 0008080f 0009cbe0 00000060 00000001 0000080f 0009cc10 00000030 0009cc78: 0020: 00000001 t0 write VFD_DECODE[0].INSTR (228a) VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID | SWITCHNEXT } VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID } 0009cc7c: 0000: 0001228a 7000411f 3000011f t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = USE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x200000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 3 } draw[82] register values + 082a0008 VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } + fcfc0081 VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } + 0000fc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } + 0008080f VFD_FETCH[0].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 | SWITCHNEXT } !+ 0009cbe0 VFD_FETCH[0].INSTR_1: 0x9cbe0 + 00000060 VFD_FETCH[0].INSTR_2: { SIZE = 0x60 } + 00000001 VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } + 0000080f VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 } !+ 0009cc10 VFD_FETCH[0x1].INSTR_1: 0x9cc10 + 00000030 VFD_FETCH[0x1].INSTR_2: { SIZE = 0x30 } + 00000001 VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } + 7000411f VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID | SWITCHNEXT } + 3000011f VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID } 000555c8: 0000: c0023800 00200984 00000001 00000003 0016b094: 0000: c0013f00 00055328 000000ac t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 0016b0a0: 0000: c0014300 00040000 00000000 t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:001fadc8 ibsize:00000046 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 001fadc8: 0000: c0002600 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x4 001fadd0: 0000: 00000ec3 00000004 t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x68 001fadd8: 0000: 00000f03 00000068 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 001fade0: 0000: c0002600 00000000 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } 001fade8: 0000: 000023c0 080004f0 t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = 0x1d } event (null) 001fadf0: 0000: c0004600 0000001d t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = FACENESS_FLUSH } event FACENESS_FLUSH 001fadf8: 0000: c0004600 0000001c t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 001fae00: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0 001fae08: 0000: 00000cc6 00000000 t0 write UNKNOWN_0E42 (0e42) UNKNOWN_0E42: 0 001fae10: 0000: 00000e42 00000000 t0 write HLSQ_MODE_CONTROL (0e05) HLSQ_MODE_CONTROL: 0x2 001fae18: 0000: 00000e05 00000002 t0 write UNKNOWN_0CC5 (0cc5) UNKNOWN_0CC5: 0x4 001fae20: 0000: 00000cc5 00000004 t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x7 001fae28: 0000: 000023db 00000007 t0 write VFD_CONTROL_2 (2202) VFD_CONTROL_2: 0xfcfcfcfc 001fae30: 0000: 00002202 fcfcfcfc t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } 001fae38: 0000: 00002203 fcfcfc00 t0 write VFD_CONTROL_4 (2204) VFD_CONTROL_4: 0xfcfc 001fae40: 0000: 00002204 0000fcfc t0 write VFD_INDEX_OFFSET (2208) VFD_INDEX_OFFSET: 0 001fae48: 0000: 00002208 00000000 t0 write UNKNOWN_2209 (2209) UNKNOWN_2209: 0 001fae50: 0000: 00002209 00000000 t0 write UNKNOWN_2152 (2152) UNKNOWN_2152: 0 UNKNOWN_2153: 0 001fae58: 0000: 00012152 00000000 00000000 t0 write UNKNOWN_2156 (2156) UNKNOWN_2156: 0 001fae64: 0000: 00002156 00000000 t0 write UNKNOWN_2154 (2154) UNKNOWN_2154: 0 001fae6c: 0000: 00002154 00000000 t0 write UNKNOWN_2155 (2155) UNKNOWN_2155: 0 001fae74: 0000: 00002155 00000000 t0 write UNKNOWN_21C3 (21c3) UNKNOWN_21C3: 0x1d 001fae7c: 0000: 000021c3 0000001d t0 write PC_PRIM_VTX_CNTL2 (21c5) PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 001fae84: 0000: 000021c5 00000012 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 001fae8c: 0000: 000021e5 00000000 t0 write GRAS_SU_MODE_CONTROL (2078) GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } 001fae94: 0000: 00002078 00000000 t0 write UNKNOWN_2001 (2001) UNKNOWN_2001: 0 001fae9c: 0000: 00002001 00000000 t0 write GRAS_CNTL (2003) GRAS_CNTL: { IJ_PERSP } 001faea4: 0000: 00002003 00000001 t0 write GRAS_CL_CLIP_CNTL (2000) GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } 001faeac: 0000: 00002000 00188000 t0 write TPL1_TP_TEX_COUNT (2381) TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } 001faeb4: 0000: 00002381 00000000 t0 write TPL1_TP_FS_TEX_COUNT (23a0) TPL1_TP_FS_TEX_COUNT: 0x3 001faebc: 0000: 000023a0 00000003 t0 write RB_ALPHA_CONTROL (20f8) RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } 001faec4: 0000: 000020f8 00000e00 t0 write RB_RENDER_COMPONENTS (20fb) RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } 001faecc: 0000: 000020fb 0000000f t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 001faed4: 0000: c0014300 00040000 00000000 0016b0ac: 0000: c0013f00 001fadc8 00000046 t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:00170000 ibsize:000000b1 t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } 00170000: 0000: 00002200 000a0000 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } 00170008: 0000: 00002201 fc030000 t0 write SP_INSTR_CACHE_CTRL (22c1) SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } 00170010: 0000: 000022c1 000005c3 t0 write HLSQ_CONTROL_1_REG (23c1) HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } 00170018: 0000: 000023c1 fcfc0120 t0 write HLSQ_CONTROL_2_REG (23c2) HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 00170020: 0000: 000023c2 27f3f3f0 t0 write HLSQ_VS_CONTROL_REG (23c5) HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } 00170028: 0000: 000023c5 02010042 t0 write HLSQ_FS_CONTROL_REG (23c6) HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00170030: 0000: 000023c6 0041423e t0 write HLSQ_HS_CONTROL_REG (23c7) HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00170038: 0000: 000023c7 00404200 t0 write HLSQ_DS_CONTROL_REG (23c8) HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00170040: 0000: 000023c8 00404200 t0 write HLSQ_GS_CONTROL_REG (23c9) HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00170048: 0000: 000023c9 00404200 t0 write HLSQ_CS_CONTROL_REG (23ca) HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } 00170050: 0000: 000023ca 00004200 t0 write SP_SP_CTRL_REG (22c0) SP_SP_CTRL_REG: { 0x60010 } 00170058: 0000: 000022c0 00060010 t0 write UNKNOWN_21E6 (21e6) UNKNOWN_21E6: 0x1 00170060: 0000: 000021e6 00000001 t0 write SP_VS_CTRL_REG0 (22c4) SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 00170068: 0000: 000022c4 00200c10 t0 write SP_VS_CTRL_REG1 (22c5) SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } 00170070: 0000: 000022c5 01000042 t0 write VPC_ATTR (2140) VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | 0x40000000 } 00170078: 0000: 00002140 40001004 t0 write VPC_PACK (2141) VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } 00170080: 0000: 00002141 00040400 t0 write PC_PRIM_VTX_CNTL (21c4) PC_PRIM_VTX_CNTL: { VAROUT = 1 } 00170088: 0000: 000021c4 00000001 t0 write SP_VS_PARAM_REG (22c6) SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } UNKNOWN_22D7: 0xfcfc00 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 00170090: 0000: 001922c6 0010fc03 00001e03 00000000 00000000 00000000 00000000 00000000 * 001700d0: 0040: 00000000 00000000 00fcfc00 00000008 00000000 00000000 00000000 00000000 * t0 write SP_VS_OBJ_OFFSET_REG (22e0) SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 001700fc: 0000: 000022e0 00000000 t0 write SP_VS_OBJ_START (22e1) SP_VS_OBJ_START: 0x1 00170104: 0000: 000022e1 00000001 t0 write SP_VS_LENGTH_REG (22e5) SP_VS_LENGTH_REG: 2 0017010c: 0000: 000022e5 00000002 t3 opcode: CP_LOAD_STATE4 (30) (67 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } :2:0000:0000[56d81803x_20020003x] (sy)(ss)(nop3) shl.b r0.w, r0.w, 2 :1:0001:0004[20150000x_00000003x] cov.s32s16 hr0.x, r0.w :0:0002:0005[00000200x_00000000x] (rpt2)nop :1:0003:0008[201100f4x_00000000x] mova a0.x, hr0.x :0:0004:0009[00000500x_00000000x] (rpt5)nop :1:0005:0015[20154003x_00000c20x] mov.s32s32 r0.w, c :1:0006:0016[20154004x_00000c21x] mov.s32s32 r1.x, c :1:0007:0017[20154005x_00000c22x] mov.s32s32 r1.y, c :1:0008:0018[20156006x_00000c23x] (ul)mov.s32s32 r1.z, c :0:0009:0019[03000000x_00000000x] end :2:0010:0020[46f00007x_20050000x] shr.b r1.w, r0.x, 5 :2:0011:0021[43980008x_201f0000x] (nop2) and.b r2.x, r0.x, 31 :2:0012:0024[43980807x_201f0007x] (nop3) and.b r1.w, r1.w, 31 :2:0013:0028[46100807x_20100007x] (nop1) mul.u24 r1.w, r1.w, 16 :3:0014:0030[62040007x_00071014x] mad.u24 r1.w, c5.x, r2.x, r1.w :0:0015:0031[00000500x_00000000x] (rpt5)nop :6:0016:0037[c2c60f00x_04800006x] stlw.u32 l[r1.w], r0.w, 4 :0:0017:0038[04800000x_00000000x] chmask :0:0018:0039[05000000x_00000000x] chsh Stats: - shaderdb: 40 instr, 24 nops, 16 non-nops, 5 mov, 1 cov - shaderdb: 0 last-baryf, 0 half, 2 full, 5 constlen - shaderdb: 27 cat0, 6 cat1, 5 cat2, 1 cat3, 0 cat4, 0 cat5, 1 cat6, 0 cat7 - shaderdb: 0 sstall, 1 (ss), 1 (sy) 00170114: 0000: c0413000 00a00000 00000000 20020003 56d81803 00000003 20150000 00000000 00170134: 0020: 00000200 00000000 201100f4 00000000 00000500 00000c20 20154003 00000c21 00170154: 0040: 20154004 00000c22 20154005 00000c23 20156006 00000000 03000000 20050000 00170174: 0060: 46f00007 201f0000 43980008 201f0007 43980807 20100007 46100807 00071014 00170194: 0080: 62040007 00000000 00000500 04800006 c2c60f00 00000000 04800000 00000000 001701b4: 00a0: 05000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 * t0 write GRAS_SC_CONTROL (207b) GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = 0 | MSAA_DISABLE | RASTER_MODE = 0 } 00170220: 0000: 0000207b 00000808 t0 write RB_MSAA_CONTROL (20a2) RB_MSAA_CONTROL: { DISABLE | SAMPLES = 0 } 00170228: 0000: 000020a2 00001000 t0 write RB_RENDER_CONTROL (20a1) RB_RENDER_CONTROL: { DISABLE_COLOR_PIPE | 0x2 } 00170230: 0000: 000020a1 00000022 t0 write RB_DEPTH_CONTROL (2101) RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } 00170238: 0000: 00002101 00000000 t0 write GRAS_ALPHA_CONTROL (2073) GRAS_ALPHA_CONTROL: { 0x2 } 00170240: 0000: 00002073 00000002 t0 write RB_STENCIL_CONTROL (2106) RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } 00170248: 0000: 00002106 00000000 t0 write RB_COPY_CONTROL (20fc) RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_FOUR | MODE = RB_COPY_DEPTH_STENCIL | FASTCLEAR = 0 | GMEM_BASE = 0 } RB_COPY_DEST_BASE: { BASE = 0x4f000 } RB_COPY_DEST_PITCH: { PITCH = 256 } RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_DISABLE | COMPONENT_ENABLE = 0xf | ENDIAN = ENDIAN_NONE | TILE = TILE4_3 } 00170250: 0000: 000320fc 00000052 0004f000 00000008 0303c068 t0 write UNKNOWN_20EF (20ef) UNKNOWN_20EF: 0 00170264: 0000: 000020ef 00000000 t0 write GRAS_SC_SCREEN_SCISSOR_TL (207c) GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } 0017026c: 0000: 0001207c 00000000 003f003f t0 write RB_FRAME_BUFFER_DIMENSION (0ce0) RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } 00170278: 0000: 00000ce0 00400040 t0 write 0xce1 (0ce1) 0xce1: 00000000 00170280: 0000: 00000ce1 00000000 t3 opcode: CP_LOAD_STATE4 (30) (11 dwords) { DST_OFF = 8 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } 00170294: 0.000000 0.000000 1.000000 1.000000 64.000000 64.000000 1.000000 1.000000 00170294: 0000: 00000000 00000000 3f800000 3f800000 42800000 42800000 3f800000 3f800000 00170288: 0000: c0093000 00a00008 00000001 00000000 00000000 3f800000 3f800000 42800000 001702a8: 0020: 42800000 3f800000 3f800000 t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x80000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 2 } draw[83] register values + 00000004 UNKNOWN_0CC5: 0x4 + 00000000 UNKNOWN_0CC6: 0 + 00400040 RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } + 00000000 0xce1: 00000000 !+ 00000002 HLSQ_MODE_CONTROL: 0x2 + 00000000 UNKNOWN_0E42: 0 !+ 00000004 SP_MODE_CONTROL: 0x4 !+ 00000068 TPL1_TP_MODE_CONTROL: 0x68 !+ 00188000 GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } + 00000000 UNKNOWN_2001: 0 + 00000001 GRAS_CNTL: { IJ_PERSP } !+ 00000002 GRAS_ALPHA_CONTROL: { 0x2 } !+ 00000000 GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } !+ 00000808 GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = 0 | MSAA_DISABLE | RASTER_MODE = 0 } !+ 00000000 GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } !+ 003f003f GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } !+ 00000022 RB_RENDER_CONTROL: { DISABLE_COLOR_PIPE | 0x2 } !+ 00001000 RB_MSAA_CONTROL: { DISABLE | SAMPLES = 0 } + 00000000 UNKNOWN_20EF: 0 + 00000e00 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } + 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } !+ 00000052 RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_FOUR | MODE = RB_COPY_DEPTH_STENCIL | FASTCLEAR = 0 | GMEM_BASE = 0 } + 0004f000 RB_COPY_DEST_BASE: { BASE = 0x4f000 } + 00000008 RB_COPY_DEST_PITCH: { PITCH = 256 } !+ 0303c068 RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_DISABLE | COMPONENT_ENABLE = 0xf | ENDIAN = ENDIAN_NONE | TILE = TILE4_3 } + 00000000 RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } + 00000000 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } !+ 40001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | 0x40000000 } + 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } + 00000000 UNKNOWN_2152: 0 + 00000000 UNKNOWN_2153: 0 + 00000000 UNKNOWN_2154: 0 + 00000000 UNKNOWN_2155: 0 + 00000000 UNKNOWN_2156: 0 !+ 0000001d UNKNOWN_21C3: 0x1d !+ 00000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 } + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + 00000000 PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } + 00000001 UNKNOWN_21E6: 0x1 !+ 000a0000 VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } !+ fc030000 VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } + fcfcfcfc VFD_CONTROL_2: 0xfcfcfcfc !+ fcfcfc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } + 0000fcfc VFD_CONTROL_4: 0xfcfc + 00000000 VFD_INDEX_OFFSET: 0 + 00000000 UNKNOWN_2209: 0 + 00060010 SP_SP_CTRL_REG: { 0x60010 } + 000005c3 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } !+ 00200c10 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } !+ 01000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } !+ 0010fc03 SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } !+ 00001e03 SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00fcfc00 UNKNOWN_22D7: 0xfcfc00 + 00000008 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } !+ 00000001 SP_VS_OBJ_START: 0x1 !+ 00000002 SP_VS_LENGTH_REG: 2 + 00000000 TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } !+ 00000003 TPL1_TP_FS_TEX_COUNT: 0x3 !+ 080004f0 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } !+ fcfc0120 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } !+ 27f3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } !+ 02010042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } !+ 0041423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } !+ 00404200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } !+ 00404200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } !+ 00404200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00004200 HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } !+ 00000007 HLSQ_UPDATE_CONTROL: 0x7 001702b4: 0000: c0023800 00080888 00000001 00000002 0016b0b8: 0000: c0013f00 00170000 000000b1 t3 opcode: (null) (1d) (2 dwords) 0016b0c4: 0000: c0001d00 00000000 ############################################################ vertices: 0 ############################################################ cmdstream: 8 dwords t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:000555d8 ibsize:00000155 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 000555d8: 0000: c0002600 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x4 000555e0: 0000: 00000ec3 00000004 t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x68 000555e8: 0000: 00000f03 00000068 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 000555f0: 0000: c0002600 00000000 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } 000555f8: 0000: 000023c0 080004f0 t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = 0x1d } event (null) 00055600: 0000: c0004600 0000001d t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = FACENESS_FLUSH } event FACENESS_FLUSH 00055608: 0000: c0004600 0000001c t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00055610: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0 00055618: 0000: 00000cc6 00000000 t0 write UNKNOWN_0E42 (0e42) UNKNOWN_0E42: 0 00055620: 0000: 00000e42 00000000 t0 write HLSQ_MODE_CONTROL (0e05) HLSQ_MODE_CONTROL: 0x2 00055628: 0000: 00000e05 00000002 t0 write UNKNOWN_0CC5 (0cc5) UNKNOWN_0CC5: 0x4 00055630: 0000: 00000cc5 00000004 t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x7 00055638: 0000: 000023db 00000007 t0 write VFD_CONTROL_2 (2202) VFD_CONTROL_2: 0xfcfcfcfc 00055640: 0000: 00002202 fcfcfcfc t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } 00055648: 0000: 00002203 fcfcfc00 t0 write VFD_CONTROL_4 (2204) VFD_CONTROL_4: 0xfcfc 00055650: 0000: 00002204 0000fcfc t0 write VFD_INDEX_OFFSET (2208) VFD_INDEX_OFFSET: 0 00055658: 0000: 00002208 00000000 t0 write UNKNOWN_2209 (2209) UNKNOWN_2209: 0 00055660: 0000: 00002209 00000000 t0 write UNKNOWN_2152 (2152) UNKNOWN_2152: 0 UNKNOWN_2153: 0 00055668: 0000: 00012152 00000000 00000000 t0 write UNKNOWN_2156 (2156) UNKNOWN_2156: 0 00055674: 0000: 00002156 00000000 t0 write UNKNOWN_2154 (2154) UNKNOWN_2154: 0 0005567c: 0000: 00002154 00000000 t0 write UNKNOWN_2155 (2155) UNKNOWN_2155: 0 00055684: 0000: 00002155 00000000 t0 write UNKNOWN_21C3 (21c3) UNKNOWN_21C3: 0x1d 0005568c: 0000: 000021c3 0000001d t0 write PC_PRIM_VTX_CNTL2 (21c5) PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 00055694: 0000: 000021c5 00000012 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 0005569c: 0000: 000021e5 00000000 t0 write GRAS_SU_MODE_CONTROL (2078) GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } 000556a4: 0000: 00002078 00000000 t0 write UNKNOWN_2001 (2001) UNKNOWN_2001: 0 000556ac: 0000: 00002001 00000000 t0 write GRAS_CNTL (2003) GRAS_CNTL: { IJ_PERSP } 000556b4: 0000: 00002003 00000001 t0 write GRAS_CL_CLIP_CNTL (2000) GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } 000556bc: 0000: 00002000 00188000 t0 write TPL1_TP_TEX_COUNT (2381) TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } 000556c4: 0000: 00002381 00000000 t0 write TPL1_TP_FS_TEX_COUNT (23a0) TPL1_TP_FS_TEX_COUNT: 0x3 000556cc: 0000: 000023a0 00000003 t0 write RB_ALPHA_CONTROL (20f8) RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } 000556d4: 0000: 000020f8 00000e00 t0 write RB_RENDER_COMPONENTS (20fb) RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } 000556dc: 0000: 000020fb 0000000f t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 000556e4: 0000: c0014300 00040000 00000000 t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } 000556f0: 0000: 00002200 000a0000 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } 000556f8: 0000: 00002201 fc030000 t0 write SP_INSTR_CACHE_CTRL (22c1) SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } 00055700: 0000: 000022c1 000005c3 t0 write HLSQ_CONTROL_1_REG (23c1) HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } 00055708: 0000: 000023c1 fcfc0120 t0 write HLSQ_CONTROL_2_REG (23c2) HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 00055710: 0000: 000023c2 27f3f3f0 t0 write HLSQ_VS_CONTROL_REG (23c5) HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } 00055718: 0000: 000023c5 02010042 t0 write HLSQ_FS_CONTROL_REG (23c6) HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 1 } 00055720: 0000: 000023c6 0141423e t0 write HLSQ_HS_CONTROL_REG (23c7) HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00055728: 0000: 000023c7 00404200 t0 write HLSQ_DS_CONTROL_REG (23c8) HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00055730: 0000: 000023c8 00404200 t0 write HLSQ_GS_CONTROL_REG (23c9) HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00055738: 0000: 000023c9 00404200 t0 write HLSQ_CS_CONTROL_REG (23ca) HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } 00055740: 0000: 000023ca 00004200 t0 write SP_SP_CTRL_REG (22c0) SP_SP_CTRL_REG: { 0x60010 } 00055748: 0000: 000022c0 00060010 t0 write UNKNOWN_21E6 (21e6) UNKNOWN_21E6: 0x1 00055750: 0000: 000021e6 00000001 t0 write SP_VS_CTRL_REG0 (22c4) SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 00055758: 0000: 000022c4 00200c10 t0 write SP_VS_CTRL_REG1 (22c5) SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } 00055760: 0000: 000022c5 01000042 t0 write VPC_ATTR (2140) VPC_ATTR: { TOTALATTR = 8 | THRDASSIGN = 1 | ENABLE | 0x40000000 } 00055768: 0000: 00002140 42001008 t0 write VPC_PACK (2141) VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 8 | NUMNONPOSVSVAR = 6 } 00055770: 0000: 00002141 00060800 t0 write PC_PRIM_VTX_CNTL (21c4) PC_PRIM_VTX_CNTL: { VAROUT = 1 } 00055778: 0000: 000021c4 00000001 t0 write SP_VS_PARAM_REG (22c6) SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 2 } SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r1.w | B_COMPMASK = 0x3 } SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } UNKNOWN_22D7: 0xfcfc00 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 12 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 00055780: 0000: 001922c6 0020fc03 06071e03 00000000 00000000 00000000 00000000 00000000 * 000557c0: 0040: 00000000 00000000 00fcfc00 00000c08 00000000 00000000 00000000 00000000 * t0 write SP_VS_OBJ_OFFSET_REG (22e0) SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 000557ec: 0000: 000022e0 00000000 t0 write SP_VS_OBJ_START (22e1) SP_VS_OBJ_START: 0x1 000557f4: 0000: 000022e1 00000001 t0 write SP_VS_LENGTH_REG (22e5) SP_VS_LENGTH_REG: 2 000557fc: 0000: 000022e5 00000002 t3 opcode: CP_LOAD_STATE4 (30) (67 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } :2:0000:0000[56d81803x_20020003x] (sy)(ss)(nop3) shl.b r0.w, r0.w, 2 :1:0001:0004[20150000x_00000003x] cov.s32s16 hr0.x, r0.w :0:0002:0005[00000200x_00000000x] (rpt2)nop :1:0003:0008[201100f4x_00000000x] mova a0.x, hr0.x :0:0004:0009[00000500x_00000000x] (rpt5)nop :1:0005:0015[20154003x_00000c20x] mov.s32s32 r0.w, c :1:0006:0016[20154004x_00000c21x] mov.s32s32 r1.x, c :1:0007:0017[20154007x_00000c22x] mov.s32s32 r1.w, c :1:0008:0018[20156008x_00000c23x] (ul)mov.s32s32 r2.x, c :1:0009:0019[20554005x_00000000x] mov.s32s32 r1.y, 0 :1:0010:0020[20554006x_3f800000x] mov.s32s32 r1.z, 1065353216 :0:0011:0021[03000000x_00000000x] end :2:0012:0022[46f00009x_20050000x] shr.b r2.y, r0.x, 5 :2:0013:0023[4398000ax_201f0000x] (nop2) and.b r2.z, r0.x, 31 :2:0014:0026[43980809x_201f0009x] (nop3) and.b r2.y, r2.y, 31 :2:0015:0030[46100809x_20180009x] (nop1) mul.u24 r2.y, r2.y, 24 :3:0016:0032[62050009x_00091014x] mad.u24 r2.y, c5.x, r2.z, r2.y :0:0017:0033[00000500x_00000000x] (rpt5)nop :6:0018:0039[c2c61300x_04800006x] stlw.u32 l[r2.y], r0.w, 4 :6:0019:0040[c2c61310x_0280000ex] stlw.u32 l[r2.y+16], r1.w, 2 :0:0020:0041[04800000x_00000000x] chmask :0:0021:0042[05000000x_00000000x] chsh Stats: - shaderdb: 43 instr, 24 nops, 19 non-nops, 7 mov, 1 cov - shaderdb: 0 last-baryf, 0 half, 3 full, 5 constlen - shaderdb: 27 cat0, 8 cat1, 5 cat2, 1 cat3, 0 cat4, 0 cat5, 2 cat6, 0 cat7 - shaderdb: 0 sstall, 1 (ss), 1 (sy) 00055804: 0000: c0413000 00a00000 00000000 20020003 56d81803 00000003 20150000 00000000 00055824: 0020: 00000200 00000000 201100f4 00000000 00000500 00000c20 20154003 00000c21 00055844: 0040: 20154004 00000c22 20154007 00000c23 20156008 00000000 20554005 3f800000 00055864: 0060: 20554006 00000000 03000000 20050000 46f00009 201f0000 4398000a 201f0009 00055884: 0080: 43980809 20180009 46100809 00091014 62050009 00000000 00000500 04800006 000558a4: 00a0: c2c61300 0280000e c2c61310 00000000 04800000 00000000 05000000 00000000 * t0 write HLSQ_CONTROL_3_REG (23c3) HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } 00055910: 0000: 000023c3 fcfcfc00 t0 write HLSQ_CONTROL_4_REG (23c4) HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } 00055918: 0000: 000023c4 00fcfcfc t0 write SP_FS_CTRL_REG0 (22e8) SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 0 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE | PIXLODENABLE } SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 } 00055920: 0000: 000122e8 00700402 8010003e t0 write SP_FS_OBJ_OFFSET_REG (22ea) SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 } 0005592c: 0000: 000022ea 40420000 t0 write SP_FS_OBJ_START (22eb) SP_FS_OBJ_START: 0x1 00055934: 0000: 000022eb 00000001 t0 write SP_FS_LENGTH_REG (22ef) SP_FS_LENGTH_REG: 1 0005593c: 0000: 000022ef 00000001 t0 write SP_FS_OUTPUT_REG (22f0) SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r0.x | SAMPLEMASK_REGID = r0.x } 00055944: 0000: 000022f0 00000001 t0 write VPC_VARYING_INTERP[0].MODE (2142) VPC_VARYING_INTERP[0].MODE: 0xe000 0005594c: 0000: 00002142 0000e000 t0 write RB_FS_OUTPUT_REG (2100) RB_FS_OUTPUT_REG: { MRT = 1 } 00055954: 0000: 00002100 00000001 t3 opcode: CP_LOAD_STATE4 (30) (35 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 1 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } :2:0000:0000[57309902x_00002004x] (sy)(ss)(rpt1)bary.f (ei)r0.z, (r)4, r0.x :0:0001:0002[00000500x_00000000x] (rpt5)nop :5:0002:0008[a0c01f00x_00000005x] sam (f32)(xyzw)r0.x, r0.z, s#0, t#0 :0:0003:0009[03000000x_00000000x] end :0:0004:0010[00000000x_00000000x] nop :0:0005:0011[00000000x_00000000x] nop :0:0006:0012[00000000x_00000000x] nop :0:0007:0013[00000000x_00000000x] nop Stats: - shaderdb: 14 instr, 10 nops, 4 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 0 half, 1 full, 0 constlen - shaderdb: 11 cat0, 0 cat1, 2 cat2, 0 cat3, 0 cat4, 1 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 1 (ss), 1 (sy) 0005595c: 0000: c0213000 00700000 00000000 00002004 57309902 00000000 00000500 00000005 0005597c: 0020: a0c01f00 00000000 03000000 00000000 00000000 00000000 00000000 00000000 * t0 write RB_FS_OUTPUT (20f9) RB_FS_OUTPUT: { ENABLE_BLEND = 0 | SAMPLE_MASK = 0xffff } 000559e8: 0000: 000020f9 ffff0000 t0 write RB_MRT[0].CONTROL (20a4) RB_MRT[0].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0xf } 000559f0: 0000: 000020a4 0f000000 t0 write RB_MRT[0x1].CONTROL (20a9) RB_MRT[0x1].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0xf } 000559f8: 0000: 000020a9 0f000000 t0 write RB_MRT[0].BLEND_CONTROL (20a8) RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } 00055a00: 0000: 000020a8 00000000 t3 opcode: CP_LOAD_STATE4 (30) (5 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_TEX | NUM_UNIT = 1 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } { XY_MAG = A4XX_TEX_NEAREST | XY_MIN = A4XX_TEX_NEAREST | WRAP_S = A4XX_TEX_CLAMP_TO_EDGE | WRAP_T = A4XX_TEX_CLAMP_TO_EDGE | WRAP_R = A4XX_TEX_CLAMP_TO_EDGE | ANISO = A4XX_TEX_ANISO_1 | LOD_BIAS = 0.000000 | 0x60000 } { COMPARE_FUNC = FUNC_LEQUAL | UNNORM_COORDS | MIPFILTER_LINEAR_FAR | MAX_LOD = 0.000000 | MIN_LOD = 0.000000 | 0x1 } 00055a14: 0000: 00060920 00000067 00055a08: 0000: c0033000 00500000 00000000 00060920 00000067 t0 write GRAS_SC_CONTROL (207b) GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 0 | RASTER_MODE = 0 } 00055a1c: 0000: 0000207b 00000000 t0 write RB_MSAA_CONTROL (20a2) RB_MSAA_CONTROL: { SAMPLES = 0 } 00055a24: 0000: 000020a2 00000000 t0 write RB_RENDER_CONTROL (20a1) RB_RENDER_CONTROL: { 0 } 00055a2c: 0000: 000020a1 00000000 t0 write 0x2382 (2382) 0x2382: 00000000 00055a34: 0000: 00002382 00000000 t0 write RB_DEPTH_CONTROL (2101) RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } 00055a3c: 0000: 00002101 00000000 t0 write GRAS_ALPHA_CONTROL (2073) GRAS_ALPHA_CONTROL: { 0 } 00055a44: 0000: 00002073 00000000 t0 write RB_STENCIL_CONTROL (2106) RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } 00055a4c: 0000: 00002106 00000000 t0 write SP_FS_MRT[0].REG (22f1) SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = RB4_R8G8B8A8_UNORM } 00055a54: 0000: 000022f1 0001a000 t0 write RB_MRT[0].BUF_INFO (20a5) RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB4_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE4_3 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 256 } RB_MRT[0].BASE: 0x166000 RB_MRT[0].CONTROL3: { STRIDE = 0 } 00055a5c: 0000: 000220a5 000400da 00166000 00000000 t3 opcode: CP_LOAD_STATE4 (30) (11 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_TEX | NUM_UNIT = 1 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } { TILED | SWIZ_X = A4XX_TEX_X | SWIZ_Y = A4XX_TEX_Y | SWIZ_Z = A4XX_TEX_Z | SWIZ_W = A4XX_TEX_W | MIPLVLS = 0 | FMT = TFMT4_8_8_8_8_UNORM | TYPE = A4XX_TEX_2D | 0x2 } { HEIGHT = 64 | WIDTH = 64 } { PITCHALIGN = 0 | PITCH = 256 | SWAP = WZYX } { LAYERSZ = 0 | DEPTH = 1 | 0x20000 } { LAYERSZ = 4096 | BASE = 0x4f000 } { 5 = 0 } { 6 = 0 } { 7 = 0 } 00055a78: 0000: 27006883 00200040 00020000 00060000 0004f001 00000000 00000000 00000000 00055a6c: 0000: c0093000 00500000 00000001 27006883 00200040 00020000 00060000 0004f001 * t0 write VPC_VARYING_PS_REPL[0].MODE (214a) VPC_VARYING_PS_REPL[0].MODE: 0x99999999 00055a98: 0000: 0000214a 99999999 t0 write GRAS_SC_SCREEN_SCISSOR_TL (207c) GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } 00055aa0: 0000: 0001207c 00000000 003f003f t0 write GRAS_SC_WINDOW_SCISSOR_BR (209c) GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 00055aac: 0000: 0001209c 003f003f 00000000 t0 write RB_FRAME_BUFFER_DIMENSION (0ce0) RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } 00055ab8: 0000: 00000ce0 00400040 t0 write 0xce1 (0ce1) 0xce1: 00000000 00055ac0: 0000: 00000ce1 00000000 t0 write RB_RENDER_CONTROL2 (20a3) RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 | IJ_PERSP_PIXEL } 00055ac8: 0000: 000020a3 00001000 t0 write RB_MODE_CONTROL (20a0) RB_MODE_CONTROL: { WIDTH = 0 | HEIGHT = 0 | 0xc00000 } 00055ad0: 0000: 000020a0 00c00000 t3 opcode: CP_LOAD_STATE4 (30) (11 dwords) { DST_OFF = 8 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } 00055ae4: 0.000000 0.000000 0.000000 0.000000 64.000000 64.000000 64.000000 64.000000 00055ae4: 0000: 00000000 00000000 00000000 00000000 42800000 42800000 42800000 42800000 00055ad8: 0000: c0093000 00a00008 00000001 00000000 00000000 00000000 00000000 42800000 00055af8: 0020: 42800000 42800000 42800000 t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x80000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 2 } draw[84] register values + 00000004 UNKNOWN_0CC5: 0x4 + 00000000 UNKNOWN_0CC6: 0 + 00400040 RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } + 00000000 0xce1: 00000000 + 00000002 HLSQ_MODE_CONTROL: 0x2 + 00000000 UNKNOWN_0E42: 0 + 00000004 SP_MODE_CONTROL: 0x4 + 00000068 TPL1_TP_MODE_CONTROL: 0x68 + 00188000 GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } + 00000000 UNKNOWN_2001: 0 + 00000001 GRAS_CNTL: { IJ_PERSP } !+ 00000000 GRAS_ALPHA_CONTROL: { 0 } + 00000000 GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } !+ 00000000 GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 0 | RASTER_MODE = 0 } + 00000000 GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } + 003f003f GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } + 003f003f GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } + 00000000 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } !+ 00c00000 RB_MODE_CONTROL: { WIDTH = 0 | HEIGHT = 0 | 0xc00000 } !+ 00000000 RB_RENDER_CONTROL: { 0 } !+ 00000000 RB_MSAA_CONTROL: { SAMPLES = 0 } !+ 00001000 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 | IJ_PERSP_PIXEL } !+ 0f000000 RB_MRT[0].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0xf } !+ 000400da RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB4_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE4_3 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 256 } !+ 00166000 RB_MRT[0].BASE: 0x166000 !+ 00000000 RB_MRT[0].CONTROL3: { STRIDE = 0 } + 00000000 RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } + 0f000000 RB_MRT[0x1].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0xf } + 00000e00 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } !+ ffff0000 RB_FS_OUTPUT: { ENABLE_BLEND = 0 | SAMPLE_MASK = 0xffff } + 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } + 00000001 RB_FS_OUTPUT_REG: { MRT = 1 } + 00000000 RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } + 00000000 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } !+ 42001008 VPC_ATTR: { TOTALATTR = 8 | THRDASSIGN = 1 | ENABLE | 0x40000000 } !+ 00060800 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 8 | NUMNONPOSVSVAR = 6 } !+ 0000e000 VPC_VARYING_INTERP[0].MODE: 0xe000 !+ 99999999 VPC_VARYING_PS_REPL[0].MODE: 0x99999999 + 00000000 UNKNOWN_2152: 0 + 00000000 UNKNOWN_2153: 0 + 00000000 UNKNOWN_2154: 0 + 00000000 UNKNOWN_2155: 0 + 00000000 UNKNOWN_2156: 0 + 0000001d UNKNOWN_21C3: 0x1d + 00000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 } + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + 00000000 PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } + 00000001 UNKNOWN_21E6: 0x1 + 000a0000 VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } + fc030000 VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } + fcfcfcfc VFD_CONTROL_2: 0xfcfcfcfc + fcfcfc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } + 0000fcfc VFD_CONTROL_4: 0xfcfc + 00000000 VFD_INDEX_OFFSET: 0 + 00000000 UNKNOWN_2209: 0 + 00060010 SP_SP_CTRL_REG: { 0x60010 } + 000005c3 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } + 00200c10 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } + 01000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } !+ 0020fc03 SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 2 } !+ 06071e03 SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r1.w | B_COMPMASK = 0x3 } + 00000000 SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00fcfc00 UNKNOWN_22D7: 0xfcfc00 !+ 00000c08 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 12 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } + 00000001 SP_VS_OBJ_START: 0x1 + 00000002 SP_VS_LENGTH_REG: 2 !+ 00700402 SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 0 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE | PIXLODENABLE } !+ 8010003e SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 } !+ 40420000 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 } !+ 00000001 SP_FS_OBJ_START: 0x1 + 00000001 SP_FS_LENGTH_REG: 1 !+ 00000001 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r0.x | SAMPLEMASK_REGID = r0.x } !+ 0001a000 SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = RB4_R8G8B8A8_UNORM } + 00000000 TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } !+ 00000000 0x2382: 00000000 + 00000003 TPL1_TP_FS_TEX_COUNT: 0x3 + 080004f0 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } + fcfc0120 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } + 27f3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } + fcfcfc00 HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } !+ 00fcfcfc HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } + 02010042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } !+ 0141423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 1 } + 00404200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00004200 HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } + 00000007 HLSQ_UPDATE_CONTROL: 0x7 00055b04: 0000: c0023800 00080888 00000001 00000002 t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = CACHE_FLUSH } event CACHE_FLUSH 00055b14: 0000: c0004600 00000006 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00055b1c: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0x8000012 00055b24: 0000: 00000cc6 08000012 00173000: 0000: c0013f00 000555d8 00000155 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 0017300c: 0000: c0014300 00040000 00000000 t3 opcode: (null) (1d) (2 dwords) 00173018: 0000: c0001d00 00000000 ############################################################ vertices: 0 ############################################################ cmdstream: 48 dwords t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 0016b000: 0000: c0002600 00000000 t0 write UCHE_INVALIDATE0 (0e8a) UCHE_INVALIDATE0: 0 UCHE_INVALIDATE1: 0x12 0016b008: 0000: 00010e8a 00000000 00000012 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 0016b014: 0000: c0002600 00000000 t0 write RB_MODE_CONTROL (20a0) RB_MODE_CONTROL: { WIDTH = 64 | HEIGHT = 64 | ENABLE_GMEM } 0016b01c: 0000: 000020a0 00010202 t0 write RB_FRAME_BUFFER_DIMENSION (0ce0) RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } 0016b024: 0000: 00000ce0 00400040 t0 write 0xce1 (0ce1) 0xce1: 00000001 0016b02c: 0000: 00000ce1 00000001 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 0016b034: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0 0016b03c: 0000: 00000cc6 00000000 t3 opcode: (null) (1d) (2 dwords) 0016b044: 0000: c0001d00 00000000 t0 write GRAS_SC_WINDOW_SCISSOR_BR (209c) GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 0016b04c: 0000: 0001209c 003f003f 00000000 t0 write RB_BIN_OFFSET (210d) RB_BIN_OFFSET: { X = 0 | Y = 0 } 0016b058: 0000: 0000210d 00000000 t0 write GRAS_SC_WINDOW_SCISSOR_BR (209c) GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 0016b060: 0000: 0001209c 003f003f 00000000 t0 write UNKNOWN_2157 (2157) UNKNOWN_2157: 0x1 0016b06c: 0000: 00002157 00000001 t3 opcode: (null) (64) (2 dwords) 0016b074: 0000: c0006400 00000001 t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:00054994 ibsize:000000f6 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00054994: 0000: c0002600 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x4 0005499c: 0000: 00000ec3 00000004 t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x68 000549a4: 0000: 00000f03 00000068 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 000549ac: 0000: c0002600 00000000 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } 000549b4: 0000: 000023c0 080004f0 t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = 0x1d } event (null) 000549bc: 0000: c0004600 0000001d t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = FACENESS_FLUSH } event FACENESS_FLUSH 000549c4: 0000: c0004600 0000001c t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 000549cc: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0 000549d4: 0000: 00000cc6 00000000 t0 write UNKNOWN_0E42 (0e42) UNKNOWN_0E42: 0 000549dc: 0000: 00000e42 00000000 t0 write HLSQ_MODE_CONTROL (0e05) HLSQ_MODE_CONTROL: 0x2 000549e4: 0000: 00000e05 00000002 t0 write UNKNOWN_0CC5 (0cc5) UNKNOWN_0CC5: 0x4 000549ec: 0000: 00000cc5 00000004 t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x7 000549f4: 0000: 000023db 00000007 t0 write VFD_CONTROL_2 (2202) VFD_CONTROL_2: 0xfcfcfcfc 000549fc: 0000: 00002202 fcfcfcfc t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } 00054a04: 0000: 00002203 fcfcfc00 t0 write VFD_CONTROL_4 (2204) VFD_CONTROL_4: 0xfcfc 00054a0c: 0000: 00002204 0000fcfc t0 write VFD_INDEX_OFFSET (2208) VFD_INDEX_OFFSET: 0 00054a14: 0000: 00002208 00000000 t0 write UNKNOWN_2209 (2209) UNKNOWN_2209: 0 00054a1c: 0000: 00002209 00000000 t0 write UNKNOWN_2152 (2152) UNKNOWN_2152: 0 UNKNOWN_2153: 0 00054a24: 0000: 00012152 00000000 00000000 t0 write UNKNOWN_2156 (2156) UNKNOWN_2156: 0 00054a30: 0000: 00002156 00000000 t0 write UNKNOWN_2154 (2154) UNKNOWN_2154: 0 00054a38: 0000: 00002154 00000000 t0 write UNKNOWN_2155 (2155) UNKNOWN_2155: 0 00054a40: 0000: 00002155 00000000 t0 write UNKNOWN_21C3 (21c3) UNKNOWN_21C3: 0x1d 00054a48: 0000: 000021c3 0000001d t0 write PC_PRIM_VTX_CNTL2 (21c5) PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 00054a50: 0000: 000021c5 00000012 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 00054a58: 0000: 000021e5 00000000 t0 write GRAS_SU_MODE_CONTROL (2078) GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } 00054a60: 0000: 00002078 00000000 t0 write UNKNOWN_2001 (2001) UNKNOWN_2001: 0 00054a68: 0000: 00002001 00000000 t0 write GRAS_CNTL (2003) GRAS_CNTL: { IJ_PERSP } 00054a70: 0000: 00002003 00000001 t0 write GRAS_CL_CLIP_CNTL (2000) GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } 00054a78: 0000: 00002000 00188000 t0 write TPL1_TP_TEX_COUNT (2381) TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } 00054a80: 0000: 00002381 00000000 t0 write TPL1_TP_FS_TEX_COUNT (23a0) TPL1_TP_FS_TEX_COUNT: 0x3 00054a88: 0000: 000023a0 00000003 t0 write RB_ALPHA_CONTROL (20f8) RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } 00054a90: 0000: 000020f8 00000e00 t0 write RB_RENDER_COMPONENTS (20fb) RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } 00054a98: 0000: 000020fb 0000000f t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 00054aa0: 0000: c0014300 00040000 00000000 t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } 00054aac: 0000: 00002200 000a0000 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } 00054ab4: 0000: 00002201 fc030000 t0 write SP_INSTR_CACHE_CTRL (22c1) SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } 00054abc: 0000: 000022c1 000005c3 t0 write HLSQ_CONTROL_1_REG (23c1) HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } 00054ac4: 0000: 000023c1 fcfc0120 t0 write HLSQ_CONTROL_2_REG (23c2) HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 00054acc: 0000: 000023c2 27f3f3f0 t0 write HLSQ_VS_CONTROL_REG (23c5) HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } 00054ad4: 0000: 000023c5 02010042 t0 write HLSQ_FS_CONTROL_REG (23c6) HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00054adc: 0000: 000023c6 0041423e t0 write HLSQ_HS_CONTROL_REG (23c7) HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00054ae4: 0000: 000023c7 00404200 t0 write HLSQ_DS_CONTROL_REG (23c8) HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00054aec: 0000: 000023c8 00404200 t0 write HLSQ_GS_CONTROL_REG (23c9) HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00054af4: 0000: 000023c9 00404200 t0 write HLSQ_CS_CONTROL_REG (23ca) HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } 00054afc: 0000: 000023ca 00004200 t0 write SP_SP_CTRL_REG (22c0) SP_SP_CTRL_REG: { 0x60010 } 00054b04: 0000: 000022c0 00060010 t0 write UNKNOWN_21E6 (21e6) UNKNOWN_21E6: 0x1 00054b0c: 0000: 000021e6 00000001 t0 write SP_VS_CTRL_REG0 (22c4) SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 00054b14: 0000: 000022c4 00200c10 t0 write SP_VS_CTRL_REG1 (22c5) SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } 00054b1c: 0000: 000022c5 01000042 t0 write VPC_ATTR (2140) VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | 0x40000000 } 00054b24: 0000: 00002140 40001004 t0 write VPC_PACK (2141) VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } 00054b2c: 0000: 00002141 00040400 t0 write PC_PRIM_VTX_CNTL (21c4) PC_PRIM_VTX_CNTL: { VAROUT = 1 } 00054b34: 0000: 000021c4 00000001 t0 write SP_VS_PARAM_REG (22c6) SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } UNKNOWN_22D7: 0xfcfc00 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 00054b3c: 0000: 001922c6 0010fc03 00001e03 00000000 00000000 00000000 00000000 00000000 * 00054b7c: 0040: 00000000 00000000 00fcfc00 00000008 00000000 00000000 00000000 00000000 * t0 write SP_VS_OBJ_OFFSET_REG (22e0) SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 00054ba8: 0000: 000022e0 00000000 t0 write SP_VS_OBJ_START (22e1) SP_VS_OBJ_START: 0x1 00054bb0: 0000: 000022e1 00000001 t0 write SP_VS_LENGTH_REG (22e5) SP_VS_LENGTH_REG: 2 00054bb8: 0000: 000022e5 00000002 t3 opcode: CP_LOAD_STATE4 (30) (67 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } :2:0000:0000[56d81803x_20020003x] (sy)(ss)(nop3) shl.b r0.w, r0.w, 2 :1:0001:0004[20150000x_00000003x] cov.s32s16 hr0.x, r0.w :0:0002:0005[00000200x_00000000x] (rpt2)nop :1:0003:0008[201100f4x_00000000x] mova a0.x, hr0.x :0:0004:0009[00000500x_00000000x] (rpt5)nop :1:0005:0015[20154003x_00000c20x] mov.s32s32 r0.w, c :1:0006:0016[20154004x_00000c21x] mov.s32s32 r1.x, c :1:0007:0017[20154005x_00000c22x] mov.s32s32 r1.y, c :1:0008:0018[20156006x_00000c23x] (ul)mov.s32s32 r1.z, c :0:0009:0019[03000000x_00000000x] end :2:0010:0020[46f00007x_20050000x] shr.b r1.w, r0.x, 5 :2:0011:0021[43980008x_201f0000x] (nop2) and.b r2.x, r0.x, 31 :2:0012:0024[43980807x_201f0007x] (nop3) and.b r1.w, r1.w, 31 :2:0013:0028[46100807x_20100007x] (nop1) mul.u24 r1.w, r1.w, 16 :3:0014:0030[62040007x_00071014x] mad.u24 r1.w, c5.x, r2.x, r1.w :0:0015:0031[00000500x_00000000x] (rpt5)nop :6:0016:0037[c2c60f00x_04800006x] stlw.u32 l[r1.w], r0.w, 4 :0:0017:0038[04800000x_00000000x] chmask :0:0018:0039[05000000x_00000000x] chsh Stats: - shaderdb: 40 instr, 24 nops, 16 non-nops, 5 mov, 1 cov - shaderdb: 0 last-baryf, 0 half, 2 full, 5 constlen - shaderdb: 27 cat0, 6 cat1, 5 cat2, 1 cat3, 0 cat4, 0 cat5, 1 cat6, 0 cat7 - shaderdb: 0 sstall, 1 (ss), 1 (sy) 00054bc0: 0000: c0413000 00a00000 00000000 20020003 56d81803 00000003 20150000 00000000 00054be0: 0020: 00000200 00000000 201100f4 00000000 00000500 00000c20 20154003 00000c21 00054c00: 0040: 20154004 00000c22 20154005 00000c23 20156006 00000000 03000000 20050000 00054c20: 0060: 46f00007 201f0000 43980008 201f0007 43980807 20100007 46100807 00071014 00054c40: 0080: 62040007 00000000 00000500 04800006 c2c60f00 00000000 04800000 00000000 00054c60: 00a0: 05000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 * t0 write GRAS_ALPHA_CONTROL (2073) GRAS_ALPHA_CONTROL: { 0x2 } 00054ccc: 0000: 00002073 00000002 t0 write GRAS_SC_CONTROL (207b) GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = 4 | MSAA_DISABLE | RASTER_MODE = 0 } 00054cd4: 0000: 0000207b 00000a08 t0 write RB_MSAA_CONTROL (20a2) RB_MSAA_CONTROL: { DISABLE | SAMPLES = 4 } 00054cdc: 0000: 000020a2 00009000 t0 write RB_RENDER_CONTROL (20a1) RB_RENDER_CONTROL: { DISABLE_COLOR_PIPE | 0x2 } 00054ce4: 0000: 000020a1 00000022 t0 write RB_CLEAR_COLOR_DW0 (20cc) RB_CLEAR_COLOR_DW0: 0xff000000 RB_CLEAR_COLOR_DW1: 0 RB_CLEAR_COLOR_DW2: 0 RB_CLEAR_COLOR_DW3: 0 00054cec: 0000: 000320cc ff000000 00000000 00000000 00000000 t0 write RB_COPY_CONTROL (20fc) RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_FOUR | MODE = RB_COPY_CLEAR | FASTCLEAR = 0xf | GMEM_BASE = 0 } RB_COPY_DEST_BASE: { BASE = 0x4f000 } RB_COPY_DEST_PITCH: { PITCH = 256 } RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_IF_ALPHA_OFF | COMPONENT_ENABLE = 0 | ENDIAN = ENDIAN_NONE | TILE = TILE4_3 } 00054d00: 0000: 000320fc 00000f22 0004f000 00000008 03000868 t0 write GRAS_SC_SCREEN_SCISSOR_TL (207c) GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } 00054d14: 0000: 0001207c 00000000 003f003f t0 write RB_FRAME_BUFFER_DIMENSION (0ce0) RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } 00054d20: 0000: 00000ce0 00400040 t0 write 0xce1 (0ce1) 0xce1: 00000000 00054d28: 0000: 00000ce1 00000000 t3 opcode: CP_LOAD_STATE4 (30) (11 dwords) { DST_OFF = 8 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } 00054d3c: 0.000000 0.000000 1.000000 1.000000 64.000000 64.000000 1.000000 1.000000 00054d3c: 0000: 00000000 00000000 3f800000 3f800000 42800000 42800000 3f800000 3f800000 00054d30: 0000: c0093000 00a00008 00000001 00000000 00000000 3f800000 3f800000 42800000 00054d50: 0020: 42800000 3f800000 3f800000 t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x80000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 2 } draw[85] register values + 00000004 UNKNOWN_0CC5: 0x4 + 00000000 UNKNOWN_0CC6: 0 + 00400040 RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } + 00000000 0xce1: 00000000 + 00000002 HLSQ_MODE_CONTROL: 0x2 + 00000000 UNKNOWN_0E42: 0 + 00000000 UCHE_INVALIDATE0: 0 + 00000012 UCHE_INVALIDATE1: 0x12 + 00000004 SP_MODE_CONTROL: 0x4 + 00000068 TPL1_TP_MODE_CONTROL: 0x68 + 00188000 GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } + 00000000 UNKNOWN_2001: 0 + 00000001 GRAS_CNTL: { IJ_PERSP } !+ 00000002 GRAS_ALPHA_CONTROL: { 0x2 } + 00000000 GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } !+ 00000a08 GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = 4 | MSAA_DISABLE | RASTER_MODE = 0 } + 00000000 GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } + 003f003f GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } + 003f003f GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } + 00000000 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } !+ 00010202 RB_MODE_CONTROL: { WIDTH = 64 | HEIGHT = 64 | ENABLE_GMEM } !+ 00000022 RB_RENDER_CONTROL: { DISABLE_COLOR_PIPE | 0x2 } !+ 00009000 RB_MSAA_CONTROL: { DISABLE | SAMPLES = 4 } + ff000000 RB_CLEAR_COLOR_DW0: 0xff000000 + 00000000 RB_CLEAR_COLOR_DW1: 0 + 00000000 RB_CLEAR_COLOR_DW2: 0 + 00000000 RB_CLEAR_COLOR_DW3: 0 + 00000e00 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } + 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } !+ 00000f22 RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_FOUR | MODE = RB_COPY_CLEAR | FASTCLEAR = 0xf | GMEM_BASE = 0 } + 0004f000 RB_COPY_DEST_BASE: { BASE = 0x4f000 } + 00000008 RB_COPY_DEST_PITCH: { PITCH = 256 } !+ 03000868 RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_IF_ALPHA_OFF | COMPONENT_ENABLE = 0 | ENDIAN = ENDIAN_NONE | TILE = TILE4_3 } + 00000000 RB_BIN_OFFSET: { X = 0 | Y = 0 } !+ 40001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | 0x40000000 } !+ 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } + 00000000 UNKNOWN_2152: 0 + 00000000 UNKNOWN_2153: 0 + 00000000 UNKNOWN_2154: 0 + 00000000 UNKNOWN_2155: 0 + 00000000 UNKNOWN_2156: 0 + 00000001 UNKNOWN_2157: 0x1 + 0000001d UNKNOWN_21C3: 0x1d + 00000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 } + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + 00000000 PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } + 00000001 UNKNOWN_21E6: 0x1 + 000a0000 VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } + fc030000 VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } + fcfcfcfc VFD_CONTROL_2: 0xfcfcfcfc + fcfcfc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } + 0000fcfc VFD_CONTROL_4: 0xfcfc + 00000000 VFD_INDEX_OFFSET: 0 + 00000000 UNKNOWN_2209: 0 + 00060010 SP_SP_CTRL_REG: { 0x60010 } + 000005c3 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } + 00200c10 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } + 01000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } !+ 0010fc03 SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } !+ 00001e03 SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00fcfc00 UNKNOWN_22D7: 0xfcfc00 !+ 00000008 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } + 00000001 SP_VS_OBJ_START: 0x1 + 00000002 SP_VS_LENGTH_REG: 2 + 00000000 TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } + 00000003 TPL1_TP_FS_TEX_COUNT: 0x3 + 080004f0 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } + fcfc0120 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } + 27f3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } + 02010042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } !+ 0041423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00004200 HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } + 00000007 HLSQ_UPDATE_CONTROL: 0x7 00054d5c: 0000: c0023800 00080888 00000001 00000002 0016b07c: 0000: c0013f00 00054994 000000f6 t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:00054d6c ibsize:00000037 t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } 00054d6c: 0000: 00002200 082a0008 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00054d74: 0000: c0002600 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x1e 00054d7c: 0000: 00000ec3 0000001e t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x28 00054d84: 0000: 00000f03 00000028 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00054d8c: 0000: c0002600 00000000 t0 write HLSQ_MODE_CONTROL (0e05) HLSQ_MODE_CONTROL: 0x1 00054d94: 0000: 00000e05 00000001 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0x600a0 } 00054d9c: 0000: 000023c0 080604f0 t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x7 00054da4: 0000: 000023db 00000007 t0 write PC_RESTART_INDEX (21c6) PC_RESTART_INDEX: 0xffffffff 00054dac: 0000: 000021c6 ffffffff t0 write UNKNOWN_21E6 (21e6) UNKNOWN_21E6: 0x1 00054db4: 0000: 000021e6 00000001 t0 write UNKNOWN_21C3 (21c3) UNKNOWN_21C3: 0x1f 00054dbc: 0000: 000021c3 0000001f t0 write TPL1_TP_TEX_OFFSET (2380) TPL1_TP_TEX_OFFSET: 0x808 00054dc4: 0000: 00002380 00000808 t0 write GRAS_SU_POINT_MINMAX (2070) GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 4092.000000 } GRAS_SU_POINT_SIZE: 0.500000 00054dcc: 0000: 00012070 ffc00010 00000008 t0 write UNKNOWN_2152 (2152) UNKNOWN_2152: 0 UNKNOWN_2153: 0 00054dd8: 0000: 00012152 00000000 00000000 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00054de4: 0000: c0002600 00000000 t0 write UNKNOWN_0CC5 (0cc5) UNKNOWN_0CC5: 0x4 00054dec: 0000: 00000cc5 00000004 t0 write 0xcc4 (0cc4) 0xcc4: 00000000 00054df4: 0000: 00000cc4 00000000 t0 write 0xd03 (0d03) 0xd03: 80200000 00054dfc: 0000: 00000d03 80200000 t0 write UNKNOWN_0EC2 (0ec2) UNKNOWN_0EC2: 0x40000 00054e04: 0000: 00000ec2 00040000 t0 write VPC_DEBUG_ECO_CONTROL (0e64) VPC_DEBUG_ECO_CONTROL: 0x100 00054e0c: 0000: 00000e64 00000100 t0 write UNKNOWN_0E42 (0e42) UNKNOWN_0E42: 0 00054e14: 0000: 00000e42 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x1e 00054e1c: 0000: 00000ec3 0000001e t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x28 00054e24: 0000: 00000f03 00000028 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 00054e2c: 0000: c0014300 00040000 00000000 t0 write VFD_INDEX_OFFSET (2208) VFD_INDEX_OFFSET: 0 00054e38: 0000: 00002208 00000000 t0 write UNKNOWN_2209 (2209) UNKNOWN_2209: 0 00054e40: 0000: 00002209 00000000 0016b088: 0000: c0013f00 00054d6c 00000037 t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:00055328 ibsize:000000ac t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x3 00055328: 0000: 000023db 00000003 t0 write SP_INSTR_CACHE_CTRL (22c1) SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } 00055330: 0000: 000022c1 000005c3 t0 write HLSQ_CONTROL_1_REG (23c1) HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x1008 } 00055338: 0000: 000023c1 fcfc1108 t0 write HLSQ_CONTROL_2_REG (23c2) HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 00055340: 0000: 000023c2 fff3f3f0 t0 write HLSQ_VS_CONTROL_REG (23c5) HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 2 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 1 } 00055348: 0000: 000023c5 01010002 t0 write HLSQ_HS_CONTROL_REG (23c7) HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 00055350: 0000: 000023c7 007e0200 t0 write HLSQ_DS_CONTROL_REG (23c8) HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 00055358: 0000: 000023c8 007e0200 t0 write HLSQ_GS_CONTROL_REG (23c9) HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 00055360: 0000: 000023c9 007e0200 t0 write HLSQ_FS_CONTROL_REG (23c6) HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 2 | CONSTOBJECTOFFSET = 2 | ENABLED | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 } 00055368: 0000: 000023c6 017f0202 t0 write SP_VS_OBJ_OFFSET_REG (22e0) SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 00055370: 0000: 000022e0 00000000 t0 write SP_HS_OBJ_OFFSET_REG (230d) SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } 00055378: 0000: 0000230d 7e020000 t0 write SP_DS_OBJ_OFFSET_REG (2334) SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } 00055380: 0000: 00002334 7e020000 t0 write SP_GS_OBJ_OFFSET_REG (235b) SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } 00055388: 0000: 0000235b 7e020000 t0 write SP_FS_OBJ_OFFSET_REG (22ea) SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } 00055390: 0000: 000022ea 7e020000 t0 write SP_VS_OBJ_START (22e1) SP_VS_OBJ_START: 0x49000 00049000: 0000: 00000000 13000000 00000000 00000000 00000000 00000000 00000000 00000000 * :0:0000:0000[13000000x_00000000x] (sy)end :0:0001:0001[00000000x_00000000x] nop :0:0002:0002[00000000x_00000000x] nop :0:0003:0003[00000000x_00000000x] nop :0:0004:0004[00000000x_00000000x] nop Stats: - shaderdb: 5 instr, 4 nops, 1 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 0 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 0 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) 00055398: 0000: 000022e1 00049000 t0 write SP_HS_OBJ_START (230e) SP_HS_OBJ_START: 0 000553a0: 0000: 0000230e 00000000 t0 write SP_DS_OBJ_START (2335) SP_DS_OBJ_START: 0 000553a8: 0000: 00002335 00000000 t0 write SP_GS_OBJ_START (235c) SP_GS_OBJ_START: 0 000553b0: 0000: 0000235c 00000000 t0 write SP_VS_LENGTH_REG (22e5) SP_VS_LENGTH_REG: 1 000553b8: 0000: 000022e5 00000001 t3 opcode: CP_LOAD_STATE4 (30) (3 dwords) { DST_OFF = 0 | STATE_SRC = SS4_INDIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 1 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0x49000 } :0:0000:0000[13000000x_00000000x] (sy)end :0:0001:0001[00000000x_00000000x] nop :0:0002:0002[00000000x_00000000x] nop :0:0003:0003[00000000x_00000000x] nop :0:0004:0004[00000000x_00000000x] nop Stats: - shaderdb: 5 instr, 4 nops, 1 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 0 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 0 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) 000553c0: 0000: c0013000 00620000 00049000 t0 write 0x2072 (2072) 0x2072: 00000000 000553cc: 0000: 00002072 00000000 t0 write UNKNOWN_2155 (2155) UNKNOWN_2155: 0 000553d4: 0000: 00002155 00000000 t0 write GRAS_CNTL (2003) GRAS_CNTL: { IJ_PERSP } 000553dc: 0000: 00002003 00000001 t0 write VPC_VARYING_INTERP[0].MODE (2142) VPC_VARYING_INTERP[0].MODE: 0 000553e4: 0000: 00002142 00000000 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0x600a0 } 000553ec: 0000: 000023c0 080604f0 t0 write HLSQ_CONTROL_3_REG (23c3) HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } 000553f4: 0000: 000023c3 fcfcfc00 t0 write HLSQ_CONTROL_4_REG (23c4) HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r0.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } 000553fc: 0000: 000023c4 00fcfc00 t0 write SP_FS_CTRL_REG0 (22e8) SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE } SP_FS_CTRL_REG1: { CONSTLENGTH = 2 | VARYING | 0x80000000 } 00055404: 0000: 000122e8 00340412 80100002 t0 write SP_FS_OBJ_START (22eb) SP_FS_OBJ_START: 0x46000 00046000: 0000: 00002000 5730cb00 00000000 03000000 00000000 00000000 00000000 00000000 * :2:0000:0000[5730cb00x_00002000x] (sy)(rpt3)bary.f (ei)hr0.x, (r)0, r0.x :0:0001:0004[03000000x_00000000x] end :0:0002:0005[00000000x_00000000x] nop :0:0003:0006[00000000x_00000000x] nop :0:0004:0007[00000000x_00000000x] nop :0:0005:0008[00000000x_00000000x] nop Stats: - shaderdb: 9 instr, 4 nops, 5 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 1 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 4 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) 00055410: 0000: 000022eb 00046000 t0 write SP_FS_LENGTH_REG (22ef) SP_FS_LENGTH_REG: 1 00055418: 0000: 000022ef 00000001 t0 write RB_RENDER_COMPONENTS (20fb) RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } 00055420: 0000: 000020fb 0000000f t3 opcode: CP_LOAD_STATE4 (30) (3 dwords) { DST_OFF = 0 | STATE_SRC = SS4_INDIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 1 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0x46000 } :2:0000:0000[5730cb00x_00002000x] (sy)(rpt3)bary.f (ei)hr0.x, (r)0, r0.x :0:0001:0004[03000000x_00000000x] end :0:0002:0005[00000000x_00000000x] nop :0:0003:0006[00000000x_00000000x] nop :0:0004:0007[00000000x_00000000x] nop :0:0005:0008[00000000x_00000000x] nop Stats: - shaderdb: 9 instr, 4 nops, 5 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 1 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 4 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) 00055428: 0000: c0013000 00720000 00046000 t0 write SP_SP_CTRL_REG (22c0) SP_SP_CTRL_REG: { 0x60010 } 00055434: 0000: 000022c0 00060010 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 28 | GROUP_ID = 3 } { ADDR_LO = 0x9ccf0 } 0005543c: 0000: c0014300 0300001c 0009ccf0 t0 write RB_DEPTH_INFO (2103) RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTH4_NONE | DEPTH_BASE = 0 } RB_DEPTH_PITCH: 0 RB_DEPTH_PITCH2: 0 00055448: 0000: 00022103 00000000 00000000 00000000 t0 write GRAS_DEPTH_CONTROL (2077) GRAS_DEPTH_CONTROL: { FORMAT = DEPTH4_NONE } 00055458: 0000: 00002077 00000000 t0 write RB_STENCIL_INFO (2108) RB_STENCIL_INFO: { STENCIL_BASE = 0 } RB_STENCIL_PITCH: 0 0x210a: 00000000 00055460: 0000: 00022108 00000000 00000000 00000000 t0 write 0x2002 (2002) 0x2002: 00000000 00055470: 0000: 00002002 00000000 t0 write RB_ALPHA_CONTROL (20f8) RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } 00055478: 0000: 000020f8 00000e00 t0 write RB_MRT[0].CONTROL (20a4) RB_MRT[0].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0x7 } 00055480: 0000: 000020a4 07000c00 t0 write RB_MRT[0].BLEND_CONTROL (20a8) RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } 00055488: 0000: 000020a8 00000000 t0 write GRAS_CL_CLIP_CNTL (2000) GRAS_CL_CLIP_CNTL: { 0x80000 } 00055490: 0000: 00002000 00080000 t0 write GRAS_SU_POLY_OFFSET_SCALE (2074) GRAS_SU_POLY_OFFSET_SCALE: 0.000000 GRAS_SU_POLY_OFFSET_OFFSET: 0.000000 GRAS_SU_POLY_OFFSET_CLAMP: 0.000000 00055498: 0000: 00022074 00000000 00000000 00000000 t0 write GRAS_SU_MODE_CONTROL (2078) GRAS_SU_MODE_CONTROL: { FRONT_CW | LINEHALFWIDTH = 0.500000 | MSAA_ENABLE | RENDERING_PASS } 000554a8: 0000: 00002078 00102014 t0 write GRAS_SC_SCREEN_SCISSOR_TL (207c) GRAS_SC_SCREEN_SCISSOR_TL: { X = 2 | Y = 13 } GRAS_SC_SCREEN_SCISSOR_BR: { X = 33 | Y = 44 } 000554b0: 0000: 0001207c 000d0002 002c0021 t0 write GRAS_CL_VPORT_XOFFSET_0 (2008) GRAS_CL_VPORT_XOFFSET_0: 18.000000 GRAS_CL_VPORT_XSCALE_0: 16.000000 GRAS_CL_VPORT_YOFFSET_0: 29.000000 GRAS_CL_VPORT_YSCALE_0: 16.000000 GRAS_CL_VPORT_ZOFFSET_0: 0.500000 GRAS_CL_VPORT_ZSCALE_0: 0.500000 000554bc: 0000: 00052008 41900000 41800000 41e80000 41800000 3f000000 3f000000 t0 write GRAS_CL_GB_CLIP_ADJ (2004) GRAS_CL_GB_CLIP_ADJ: { HORZ = 511 | VERT = 511 } 000554d8: 0000: 00002004 0007fdff t0 write GRAS_SC_CONTROL (207b) GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 4 | RASTER_MODE = 0 } 000554e0: 0000: 0000207b 00000200 t0 write 0x2382 (2382) 0x2382: 00000002 000554e8: 0000: 00002382 00000002 t0 write RB_MSAA_CONTROL (20a2) RB_MSAA_CONTROL: { SAMPLES = 4 } 000554f0: 0000: 000020a2 00008000 t0 write RB_RENDER_CONTROL2 (20a3) RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 4 | IJ_PERSP_PIXEL } 000554f8: 0000: 000020a3 00001200 t0 write RB_MRT[0].BUF_INFO (20a5) RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB4_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_ALWAYS | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 1024 } RB_MRT[0].BASE: 0 RB_MRT[0].CONTROL3: { STRIDE = 64 } 00055500: 0000: 000220a5 0010029a 00000000 00000200 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 43 | GROUP_ID = 2 } { ADDR_LO = 0x9cd60 } 00055510: 0000: c0014300 0200002b 0009cd60 t0 write 0x215c (215c) 0x215c: 00000000 0x215d: 00000000 0005551c: 0000: 0001215c 00000000 00000000 t0 write 0x215f (215f) 0x215f: 00000000 00055528: 0000: 0000215f 00000000 t0 write 0x215e (215e) 0x215e: 00000000 00055530: 0000: 0000215e 00000000 t0 write 0x2161 (2161) 0x2161: 00000000 0x2162: 00000000 00055538: 0000: 00012161 00000000 00000000 t0 write 0x2164 (2164) 0x2164: 00000000 00055544: 0000: 00002164 00000000 t0 write 0x2163 (2163) 0x2163: 00000000 0005554c: 0000: 00002163 00000000 t0 write 0x2166 (2166) 0x2166: 00000000 0x2167: 00000000 00055554: 0000: 00012166 00000000 00000000 t0 write 0x2169 (2169) 0x2169: 00000000 00055560: 0000: 00002169 00000000 t0 write 0x2168 (2168) 0x2168: 00000000 00055568: 0000: 00002168 00000000 t0 write 0x216b (216b) 0x216b: 00000000 0x216c: 00000000 00055570: 0000: 0001216b 00000000 00000000 t0 write VPC_SO_FLUSH_WADDR_3 (216e) VPC_SO_FLUSH_WADDR_3: 0 0005557c: 0000: 0000216e 00000000 t0 write 0x216d (216d) 0x216d: 00000000 00055584: 0000: 0000216d 00000000 t0 write UNKNOWN_2156 (2156) UNKNOWN_2156: 0 0005558c: 0000: 00002156 00000000 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 18 | GROUP_ID = 1 } { ADDR_LO = 0x9ce10 } 00055594: 0000: c0014300 01000012 0009ce10 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 15 | GROUP_ID = 0 } { ADDR_LO = 0x9ce60 } 000555a0: 0000: c0014300 0000000f 0009ce60 group_id: 0 count: 15 addr: 000000000009ce60 flags: 0 0009ce60: 0000: 00002073 00000000 00002101 00000000 00002106 00000000 000021e5 00000000 0009ce80: 0020: 0001210b 00000000 00000000 00002381 00000000 000023a0 00000000 t0 write GRAS_ALPHA_CONTROL (2073) GRAS_ALPHA_CONTROL: { 0 } 0009ce60: 0000: 00002073 00000000 t0 write RB_DEPTH_CONTROL (2101) RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } 0009ce68: 0000: 00002101 00000000 t0 write RB_STENCIL_CONTROL (2106) RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } 0009ce70: 0000: 00002106 00000000 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 0009ce78: 0000: 000021e5 00000000 t0 write RB_STENCILREFMASK (210b) RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 0009ce80: 0000: 0001210b 00000000 00000000 t0 write TPL1_TP_TEX_COUNT (2381) TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } 0009ce8c: 0000: 00002381 00000000 t0 write TPL1_TP_FS_TEX_COUNT (23a0) TPL1_TP_FS_TEX_COUNT: 0 0009ce94: 0000: 000023a0 00000000 group_id: 1 count: 18 addr: 000000000009ce10 flags: 0 0009ce10: 0000: 00002200 082a0008 00002201 fcfc0081 00002203 0000fc00 0007220a 0008080f 0009ce30: 0020: 0009cc90 00000060 00000001 0000080f 0009ccc0 00000030 00000001 0001228a 0009ce50: 0040: 7000411f 3000011f t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } 0009ce10: 0000: 00002200 082a0008 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } 0009ce18: 0000: 00002201 fcfc0081 t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } 0009ce20: 0000: 00002203 0000fc00 t0 write VFD_FETCH[0].INSTR_0 (220a) VFD_FETCH[0].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 | SWITCHNEXT } VFD_FETCH[0].INSTR_1: 0x9cc90 VFD_FETCH[0].INSTR_2: { SIZE = 0x60 } VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 } VFD_FETCH[0x1].INSTR_1: 0x9ccc0 VFD_FETCH[0x1].INSTR_2: { SIZE = 0x30 } VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } 0009ce28: 0000: 0007220a 0008080f 0009cc90 00000060 00000001 0000080f 0009ccc0 00000030 0009ce48: 0020: 00000001 t0 write VFD_DECODE[0].INSTR (228a) VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID | SWITCHNEXT } VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID } 0009ce4c: 0000: 0001228a 7000411f 3000011f group_id: 2 count: 43 addr: 000000000009cd60 flags: 0 0009cd60: 0000: 000020a1 00000000 000022f1 0001a100 000022f0 fc00fc01 00002100 00000001 0009cd80: 0020: 000021e5 00000000 000020f9 ffff0501 0000214a 00000000 00002140 42001004 0009cda0: 0040: 001922c6 0010fc04 00001e00 00000000 00000000 00000000 00000000 00000000 * 0009cde0: 0080: 00000000 00000000 00fcfc00 00000008 00000000 00000000 00000000 00000000 * t0 write RB_RENDER_CONTROL (20a1) RB_RENDER_CONTROL: { 0 } 0009cd60: 0000: 000020a1 00000000 t0 write SP_FS_MRT[0].REG (22f1) SP_FS_MRT[0].REG: { REGID = r0.x | HALF_PRECISION | MRTFORMAT = RB4_R8G8B8A8_UNORM } 0009cd68: 0000: 000022f1 0001a100 t0 write SP_FS_OUTPUT_REG (22f0) SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 0009cd70: 0000: 000022f0 fc00fc01 t0 write RB_FS_OUTPUT_REG (2100) RB_FS_OUTPUT_REG: { MRT = 1 } 0009cd78: 0000: 00002100 00000001 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 0009cd80: 0000: 000021e5 00000000 t0 write RB_FS_OUTPUT (20f9) RB_FS_OUTPUT: { ENABLE_BLEND = 0x1 | INDEPENDENT_BLEND | SAMPLE_MASK = 0xffff | 0x400 } 0009cd88: 0000: 000020f9 ffff0501 t0 write VPC_VARYING_PS_REPL[0].MODE (214a) VPC_VARYING_PS_REPL[0].MODE: 0 0009cd90: 0000: 0000214a 00000000 t0 write VPC_ATTR (2140) VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 } 0009cd98: 0000: 00002140 42001004 t0 write SP_VS_PARAM_REG (22c6) SP_VS_PARAM_REG: { POSREGID = r1.x | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } SP_VS_OUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } UNKNOWN_22D7: 0xfcfc00 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 0009cda0: 0000: 001922c6 0010fc04 00001e00 00000000 00000000 00000000 00000000 00000000 * 0009cde0: 0040: 00000000 00000000 00fcfc00 00000008 00000000 00000000 00000000 00000000 * group_id: 3 count: 28 addr: 000000000009ccf0 flags: 0 0009ccf0: 0000: 000021c4 02000001 00002141 00040400 00002001 00000000 000022c4 00200800 0009cd10: 0020: 000022c5 08000002 0000230c 00000000 00002318 00000000 00002319 00000000 0009cd30: 0040: 00002340 00000000 00002202 fcfcfcfc 00002204 0000fcfc 00002154 00000000 0009cd50: 0060: 000021e7 00000000 000021c5 00000012 t0 write PC_PRIM_VTX_CNTL (21c4) PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } 0009ccf0: 0000: 000021c4 02000001 t0 write VPC_PACK (2141) VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } 0009ccf8: 0000: 00002141 00040400 t0 write UNKNOWN_2001 (2001) UNKNOWN_2001: 0 0009cd00: 0000: 00002001 00000000 t0 write SP_VS_CTRL_REG0 (22c4) SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 2 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 0009cd08: 0000: 000022c4 00200800 t0 write SP_VS_CTRL_REG1 (22c5) SP_VS_CTRL_REG1: { CONSTLENGTH = 2 | INITIALOUTSTANDING = 8 } 0009cd10: 0000: 000022c5 08000002 t0 write 0x230c (230c) 0x230c: 00000000 0009cd18: 0000: 0000230c 00000000 t0 write 0x2318 (2318) 0x2318: 00000000 0009cd20: 0000: 00002318 00000000 t0 write 0x2319 (2319) 0x2319: 00000000 0009cd28: 0000: 00002319 00000000 t0 write 0x2340 (2340) 0x2340: 00000000 0009cd30: 0000: 00002340 00000000 t0 write VFD_CONTROL_2 (2202) VFD_CONTROL_2: 0xfcfcfcfc 0009cd38: 0000: 00002202 fcfcfcfc t0 write VFD_CONTROL_4 (2204) VFD_CONTROL_4: 0xfcfc 0009cd40: 0000: 00002204 0000fcfc t0 write UNKNOWN_2154 (2154) UNKNOWN_2154: 0 0009cd48: 0000: 00002154 00000000 t0 write PC_HS_PARAM (21e7) PC_HS_PARAM: { VERTICES_OUT = 0 | SPACING = EQUAL_SPACING } 0009cd50: 0000: 000021e7 00000000 t0 write PC_PRIM_VTX_CNTL2 (21c5) PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 0009cd58: 0000: 000021c5 00000012 t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = USE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x200000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 3 } draw[86] register values + 00000000 0xcc4: 00000000 + 00000004 UNKNOWN_0CC5: 0x4 + 80200000 0xd03: 80200000 !+ 00000001 HLSQ_MODE_CONTROL: 0x1 + 00000000 UNKNOWN_0E42: 0 + 00000100 VPC_DEBUG_ECO_CONTROL: 0x100 + 00040000 UNKNOWN_0EC2: 0x40000 !+ 0000001e SP_MODE_CONTROL: 0x1e !+ 00000028 TPL1_TP_MODE_CONTROL: 0x28 !+ 00080000 GRAS_CL_CLIP_CNTL: { 0x80000 } + 00000000 UNKNOWN_2001: 0 + 00000000 0x2002: 00000000 + 00000001 GRAS_CNTL: { IJ_PERSP } + 0007fdff GRAS_CL_GB_CLIP_ADJ: { HORZ = 511 | VERT = 511 } + 41900000 GRAS_CL_VPORT_XOFFSET_0: 18.000000 + 41800000 GRAS_CL_VPORT_XSCALE_0: 16.000000 + 41e80000 GRAS_CL_VPORT_YOFFSET_0: 29.000000 + 41800000 GRAS_CL_VPORT_YSCALE_0: 16.000000 + 3f000000 GRAS_CL_VPORT_ZOFFSET_0: 0.500000 + 3f000000 GRAS_CL_VPORT_ZSCALE_0: 0.500000 + ffc00010 GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 4092.000000 } + 00000008 GRAS_SU_POINT_SIZE: 0.500000 + 00000000 0x2072: 00000000 !+ 00000000 GRAS_ALPHA_CONTROL: { 0 } + 00000000 GRAS_SU_POLY_OFFSET_SCALE: 0.000000 + 00000000 GRAS_SU_POLY_OFFSET_OFFSET: 0.000000 + 00000000 GRAS_SU_POLY_OFFSET_CLAMP: 0.000000 + 00000000 GRAS_DEPTH_CONTROL: { FORMAT = DEPTH4_NONE } !+ 00102014 GRAS_SU_MODE_CONTROL: { FRONT_CW | LINEHALFWIDTH = 0.500000 | MSAA_ENABLE | RENDERING_PASS } !+ 00000200 GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 4 | RASTER_MODE = 0 } !+ 000d0002 GRAS_SC_SCREEN_SCISSOR_TL: { X = 2 | Y = 13 } !+ 002c0021 GRAS_SC_SCREEN_SCISSOR_BR: { X = 33 | Y = 44 } !+ 00000000 RB_RENDER_CONTROL: { 0 } !+ 00008000 RB_MSAA_CONTROL: { SAMPLES = 4 } !+ 00001200 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 4 | IJ_PERSP_PIXEL } !+ 07000c00 RB_MRT[0].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0x7 } !+ 0010029a RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB4_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_ALWAYS | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 1024 } !+ 00000000 RB_MRT[0].BASE: 0 !+ 00000200 RB_MRT[0].CONTROL3: { STRIDE = 64 } + 00000000 RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } + 00000e00 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } !+ ffff0501 RB_FS_OUTPUT: { ENABLE_BLEND = 0x1 | INDEPENDENT_BLEND | SAMPLE_MASK = 0xffff | 0x400 } + 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } + 00000001 RB_FS_OUTPUT_REG: { MRT = 1 } + 00000000 RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } + 00000000 RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTH4_NONE | DEPTH_BASE = 0 } + 00000000 RB_DEPTH_PITCH: 0 + 00000000 RB_DEPTH_PITCH2: 0 + 00000000 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } + 00000000 RB_STENCIL_INFO: { STENCIL_BASE = 0 } + 00000000 RB_STENCIL_PITCH: 0 + 00000000 0x210a: 00000000 + 00000000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } + 00000000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } !+ 42001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 } + 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } !+ 00000000 VPC_VARYING_INTERP[0].MODE: 0 !+ 00000000 VPC_VARYING_PS_REPL[0].MODE: 0 + 00000000 UNKNOWN_2152: 0 + 00000000 UNKNOWN_2153: 0 + 00000000 UNKNOWN_2154: 0 + 00000000 UNKNOWN_2155: 0 + 00000000 UNKNOWN_2156: 0 + 00000000 0x215c: 00000000 + 00000000 0x215d: 00000000 + 00000000 0x215e: 00000000 + 00000000 0x215f: 00000000 + 00000000 0x2161: 00000000 + 00000000 0x2162: 00000000 + 00000000 0x2163: 00000000 + 00000000 0x2164: 00000000 + 00000000 0x2166: 00000000 + 00000000 0x2167: 00000000 + 00000000 0x2168: 00000000 + 00000000 0x2169: 00000000 + 00000000 0x216b: 00000000 + 00000000 0x216c: 00000000 + 00000000 0x216d: 00000000 + 00000000 VPC_SO_FLUSH_WADDR_3: 0 !+ 0000001f UNKNOWN_21C3: 0x1f !+ 02000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + ffffffff PC_RESTART_INDEX: 0xffffffff + 00000000 PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } + 00000001 UNKNOWN_21E6: 0x1 + 00000000 PC_HS_PARAM: { VERTICES_OUT = 0 | SPACING = EQUAL_SPACING } !+ 082a0008 VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } !+ fcfc0081 VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } + fcfcfcfc VFD_CONTROL_2: 0xfcfcfcfc !+ 0000fc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } + 0000fcfc VFD_CONTROL_4: 0xfcfc + 00000000 VFD_INDEX_OFFSET: 0 + 00000000 UNKNOWN_2209: 0 + 0008080f VFD_FETCH[0].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 | SWITCHNEXT } !+ 0009cc90 VFD_FETCH[0].INSTR_1: 0x9cc90 + 00000060 VFD_FETCH[0].INSTR_2: { SIZE = 0x60 } + 00000001 VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } + 0000080f VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 } !+ 0009ccc0 VFD_FETCH[0x1].INSTR_1: 0x9ccc0 + 00000030 VFD_FETCH[0x1].INSTR_2: { SIZE = 0x30 } + 00000001 VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } + 7000411f VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID | SWITCHNEXT } + 3000011f VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID } + 00060010 SP_SP_CTRL_REG: { 0x60010 } + 000005c3 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } !+ 00200800 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 2 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } !+ 08000002 SP_VS_CTRL_REG1: { CONSTLENGTH = 2 | INITIALOUTSTANDING = 8 } !+ 0010fc04 SP_VS_PARAM_REG: { POSREGID = r1.x | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } !+ 00001e00 SP_VS_OUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00fcfc00 UNKNOWN_22D7: 0xfcfc00 + 00000008 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } !+ 00049000 SP_VS_OBJ_START: 0x49000 00049000: 0000: 00000000 13000000 00000000 00000000 00000000 00000000 00000000 00000000 * :0:0000:0000[13000000x_00000000x] (sy)end :0:0001:0001[00000000x_00000000x] nop :0:0002:0002[00000000x_00000000x] nop :0:0003:0003[00000000x_00000000x] nop :0:0004:0004[00000000x_00000000x] nop Stats: - shaderdb: 5 instr, 4 nops, 1 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 0 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 0 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) !+ 00000001 SP_VS_LENGTH_REG: 1 !+ 00340412 SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE } !+ 80100002 SP_FS_CTRL_REG1: { CONSTLENGTH = 2 | VARYING | 0x80000000 } !+ 7e020000 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } !+ 00046000 SP_FS_OBJ_START: 0x46000 00046000: 0000: 00002000 5730cb00 00000000 03000000 00000000 00000000 00000000 00000000 * :2:0000:0000[5730cb00x_00002000x] (sy)(rpt3)bary.f (ei)hr0.x, (r)0, r0.x :0:0001:0004[03000000x_00000000x] end :0:0002:0005[00000000x_00000000x] nop :0:0003:0006[00000000x_00000000x] nop :0:0004:0007[00000000x_00000000x] nop :0:0005:0008[00000000x_00000000x] nop Stats: - shaderdb: 9 instr, 4 nops, 5 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 1 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 4 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) + 00000001 SP_FS_LENGTH_REG: 1 !+ fc00fc01 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r63.x } !+ 0001a100 SP_FS_MRT[0].REG: { REGID = r0.x | HALF_PRECISION | MRTFORMAT = RB4_R8G8B8A8_UNORM } + 00000000 0x230c: 00000000 + 7e020000 SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } + 00000000 SP_HS_OBJ_START: 0 + 00000000 0x2318: 00000000 + 00000000 0x2319: 00000000 + 7e020000 SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } + 00000000 SP_DS_OBJ_START: 0 + 00000000 0x2340: 00000000 + 7e020000 SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } + 00000000 SP_GS_OBJ_START: 0 + 00000808 TPL1_TP_TEX_OFFSET: 0x808 + 00000000 TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } !+ 00000002 0x2382: 00000002 !+ 00000000 TPL1_TP_FS_TEX_COUNT: 0 !+ 080604f0 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0x600a0 } !+ fcfc1108 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x1008 } !+ fff3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } + fcfcfc00 HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } !+ 00fcfc00 HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r0.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } !+ 01010002 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 2 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 1 } !+ 017f0202 HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 2 | CONSTOBJECTOFFSET = 2 | ENABLED | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 } !+ 007e0200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } !+ 007e0200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } !+ 007e0200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } !+ 00000003 HLSQ_UPDATE_CONTROL: 0x3 000555ac: 0000: c0023800 00200984 00000001 00000003 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 18 | GROUP_ID = 1 } { ADDR_LO = 0x9cfd0 } 000555bc: 0000: c0014300 01000012 0009cfd0 group_id: 1 count: 18 addr: 000000000009cfd0 flags: 0 0009cfd0: 0000: 00002200 082a0008 00002201 fcfc0081 00002203 0000fc00 0007220a 0008080f 0009cff0: 0020: 0009cf70 00000060 00000001 0000080f 0009cfa0 00000030 00000001 0001228a 0009d010: 0040: 7000411f 3000011f t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } 0009cfd0: 0000: 00002200 082a0008 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } 0009cfd8: 0000: 00002201 fcfc0081 t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } 0009cfe0: 0000: 00002203 0000fc00 t0 write VFD_FETCH[0].INSTR_0 (220a) VFD_FETCH[0].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 | SWITCHNEXT } VFD_FETCH[0].INSTR_1: 0x9cf70 VFD_FETCH[0].INSTR_2: { SIZE = 0x60 } VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 } VFD_FETCH[0x1].INSTR_1: 0x9cfa0 VFD_FETCH[0x1].INSTR_2: { SIZE = 0x30 } VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } 0009cfe8: 0000: 0007220a 0008080f 0009cf70 00000060 00000001 0000080f 0009cfa0 00000030 0009d008: 0020: 00000001 t0 write VFD_DECODE[0].INSTR (228a) VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID | SWITCHNEXT } VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID } 0009d00c: 0000: 0001228a 7000411f 3000011f t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = USE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x200000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 3 } draw[87] register values + 082a0008 VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } + fcfc0081 VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } + 0000fc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } + 0008080f VFD_FETCH[0].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 | SWITCHNEXT } !+ 0009cf70 VFD_FETCH[0].INSTR_1: 0x9cf70 + 00000060 VFD_FETCH[0].INSTR_2: { SIZE = 0x60 } + 00000001 VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } + 0000080f VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 } !+ 0009cfa0 VFD_FETCH[0x1].INSTR_1: 0x9cfa0 + 00000030 VFD_FETCH[0x1].INSTR_2: { SIZE = 0x30 } + 00000001 VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } + 7000411f VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID | SWITCHNEXT } + 3000011f VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID } 000555c8: 0000: c0023800 00200984 00000001 00000003 0016b094: 0000: c0013f00 00055328 000000ac t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 0016b0a0: 0000: c0014300 00040000 00000000 t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:001702c4 ibsize:000000f7 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 001702c4: 0000: c0002600 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x4 001702cc: 0000: 00000ec3 00000004 t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x68 001702d4: 0000: 00000f03 00000068 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 001702dc: 0000: c0002600 00000000 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } 001702e4: 0000: 000023c0 080004f0 t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = 0x1d } event (null) 001702ec: 0000: c0004600 0000001d t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = FACENESS_FLUSH } event FACENESS_FLUSH 001702f4: 0000: c0004600 0000001c t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 001702fc: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0 00170304: 0000: 00000cc6 00000000 t0 write UNKNOWN_0E42 (0e42) UNKNOWN_0E42: 0 0017030c: 0000: 00000e42 00000000 t0 write HLSQ_MODE_CONTROL (0e05) HLSQ_MODE_CONTROL: 0x2 00170314: 0000: 00000e05 00000002 t0 write UNKNOWN_0CC5 (0cc5) UNKNOWN_0CC5: 0x4 0017031c: 0000: 00000cc5 00000004 t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x7 00170324: 0000: 000023db 00000007 t0 write VFD_CONTROL_2 (2202) VFD_CONTROL_2: 0xfcfcfcfc 0017032c: 0000: 00002202 fcfcfcfc t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } 00170334: 0000: 00002203 fcfcfc00 t0 write VFD_CONTROL_4 (2204) VFD_CONTROL_4: 0xfcfc 0017033c: 0000: 00002204 0000fcfc t0 write VFD_INDEX_OFFSET (2208) VFD_INDEX_OFFSET: 0 00170344: 0000: 00002208 00000000 t0 write UNKNOWN_2209 (2209) UNKNOWN_2209: 0 0017034c: 0000: 00002209 00000000 t0 write UNKNOWN_2152 (2152) UNKNOWN_2152: 0 UNKNOWN_2153: 0 00170354: 0000: 00012152 00000000 00000000 t0 write UNKNOWN_2156 (2156) UNKNOWN_2156: 0 00170360: 0000: 00002156 00000000 t0 write UNKNOWN_2154 (2154) UNKNOWN_2154: 0 00170368: 0000: 00002154 00000000 t0 write UNKNOWN_2155 (2155) UNKNOWN_2155: 0 00170370: 0000: 00002155 00000000 t0 write UNKNOWN_21C3 (21c3) UNKNOWN_21C3: 0x1d 00170378: 0000: 000021c3 0000001d t0 write PC_PRIM_VTX_CNTL2 (21c5) PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 00170380: 0000: 000021c5 00000012 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 00170388: 0000: 000021e5 00000000 t0 write GRAS_SU_MODE_CONTROL (2078) GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } 00170390: 0000: 00002078 00000000 t0 write UNKNOWN_2001 (2001) UNKNOWN_2001: 0 00170398: 0000: 00002001 00000000 t0 write GRAS_CNTL (2003) GRAS_CNTL: { IJ_PERSP } 001703a0: 0000: 00002003 00000001 t0 write GRAS_CL_CLIP_CNTL (2000) GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } 001703a8: 0000: 00002000 00188000 t0 write TPL1_TP_TEX_COUNT (2381) TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } 001703b0: 0000: 00002381 00000000 t0 write TPL1_TP_FS_TEX_COUNT (23a0) TPL1_TP_FS_TEX_COUNT: 0x3 001703b8: 0000: 000023a0 00000003 t0 write RB_ALPHA_CONTROL (20f8) RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } 001703c0: 0000: 000020f8 00000e00 t0 write RB_RENDER_COMPONENTS (20fb) RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } 001703c8: 0000: 000020fb 0000000f t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 001703d0: 0000: c0014300 00040000 00000000 t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } 001703dc: 0000: 00002200 000a0000 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } 001703e4: 0000: 00002201 fc030000 t0 write SP_INSTR_CACHE_CTRL (22c1) SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } 001703ec: 0000: 000022c1 000005c3 t0 write HLSQ_CONTROL_1_REG (23c1) HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } 001703f4: 0000: 000023c1 fcfc0120 t0 write HLSQ_CONTROL_2_REG (23c2) HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 001703fc: 0000: 000023c2 27f3f3f0 t0 write HLSQ_VS_CONTROL_REG (23c5) HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } 00170404: 0000: 000023c5 02010042 t0 write HLSQ_FS_CONTROL_REG (23c6) HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 0017040c: 0000: 000023c6 0041423e t0 write HLSQ_HS_CONTROL_REG (23c7) HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00170414: 0000: 000023c7 00404200 t0 write HLSQ_DS_CONTROL_REG (23c8) HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 0017041c: 0000: 000023c8 00404200 t0 write HLSQ_GS_CONTROL_REG (23c9) HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00170424: 0000: 000023c9 00404200 t0 write HLSQ_CS_CONTROL_REG (23ca) HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } 0017042c: 0000: 000023ca 00004200 t0 write SP_SP_CTRL_REG (22c0) SP_SP_CTRL_REG: { 0x60010 } 00170434: 0000: 000022c0 00060010 t0 write UNKNOWN_21E6 (21e6) UNKNOWN_21E6: 0x1 0017043c: 0000: 000021e6 00000001 t0 write SP_VS_CTRL_REG0 (22c4) SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 00170444: 0000: 000022c4 00200c10 t0 write SP_VS_CTRL_REG1 (22c5) SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } 0017044c: 0000: 000022c5 01000042 t0 write VPC_ATTR (2140) VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | 0x40000000 } 00170454: 0000: 00002140 40001004 t0 write VPC_PACK (2141) VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } 0017045c: 0000: 00002141 00040400 t0 write PC_PRIM_VTX_CNTL (21c4) PC_PRIM_VTX_CNTL: { VAROUT = 1 } 00170464: 0000: 000021c4 00000001 t0 write SP_VS_PARAM_REG (22c6) SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } UNKNOWN_22D7: 0xfcfc00 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 0017046c: 0000: 001922c6 0010fc03 00001e03 00000000 00000000 00000000 00000000 00000000 * 001704ac: 0040: 00000000 00000000 00fcfc00 00000008 00000000 00000000 00000000 00000000 * t0 write SP_VS_OBJ_OFFSET_REG (22e0) SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 001704d8: 0000: 000022e0 00000000 t0 write SP_VS_OBJ_START (22e1) SP_VS_OBJ_START: 0x1 001704e0: 0000: 000022e1 00000001 t0 write SP_VS_LENGTH_REG (22e5) SP_VS_LENGTH_REG: 2 001704e8: 0000: 000022e5 00000002 t3 opcode: CP_LOAD_STATE4 (30) (67 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } :2:0000:0000[56d81803x_20020003x] (sy)(ss)(nop3) shl.b r0.w, r0.w, 2 :1:0001:0004[20150000x_00000003x] cov.s32s16 hr0.x, r0.w :0:0002:0005[00000200x_00000000x] (rpt2)nop :1:0003:0008[201100f4x_00000000x] mova a0.x, hr0.x :0:0004:0009[00000500x_00000000x] (rpt5)nop :1:0005:0015[20154003x_00000c20x] mov.s32s32 r0.w, c :1:0006:0016[20154004x_00000c21x] mov.s32s32 r1.x, c :1:0007:0017[20154005x_00000c22x] mov.s32s32 r1.y, c :1:0008:0018[20156006x_00000c23x] (ul)mov.s32s32 r1.z, c :0:0009:0019[03000000x_00000000x] end :2:0010:0020[46f00007x_20050000x] shr.b r1.w, r0.x, 5 :2:0011:0021[43980008x_201f0000x] (nop2) and.b r2.x, r0.x, 31 :2:0012:0024[43980807x_201f0007x] (nop3) and.b r1.w, r1.w, 31 :2:0013:0028[46100807x_20100007x] (nop1) mul.u24 r1.w, r1.w, 16 :3:0014:0030[62040007x_00071014x] mad.u24 r1.w, c5.x, r2.x, r1.w :0:0015:0031[00000500x_00000000x] (rpt5)nop :6:0016:0037[c2c60f00x_04800006x] stlw.u32 l[r1.w], r0.w, 4 :0:0017:0038[04800000x_00000000x] chmask :0:0018:0039[05000000x_00000000x] chsh Stats: - shaderdb: 40 instr, 24 nops, 16 non-nops, 5 mov, 1 cov - shaderdb: 0 last-baryf, 0 half, 2 full, 5 constlen - shaderdb: 27 cat0, 6 cat1, 5 cat2, 1 cat3, 0 cat4, 0 cat5, 1 cat6, 0 cat7 - shaderdb: 0 sstall, 1 (ss), 1 (sy) 001704f0: 0000: c0413000 00a00000 00000000 20020003 56d81803 00000003 20150000 00000000 00170510: 0020: 00000200 00000000 201100f4 00000000 00000500 00000c20 20154003 00000c21 00170530: 0040: 20154004 00000c22 20154005 00000c23 20156006 00000000 03000000 20050000 00170550: 0060: 46f00007 201f0000 43980008 201f0007 43980807 20100007 46100807 00071014 00170570: 0080: 62040007 00000000 00000500 04800006 c2c60f00 00000000 04800000 00000000 00170590: 00a0: 05000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 * t0 write GRAS_SC_CONTROL (207b) GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = 0 | MSAA_DISABLE | RASTER_MODE = 0 } 001705fc: 0000: 0000207b 00000808 t0 write RB_MSAA_CONTROL (20a2) RB_MSAA_CONTROL: { DISABLE | SAMPLES = 0 } 00170604: 0000: 000020a2 00001000 t0 write RB_RENDER_CONTROL (20a1) RB_RENDER_CONTROL: { DISABLE_COLOR_PIPE | 0x2 } 0017060c: 0000: 000020a1 00000022 t0 write RB_DEPTH_CONTROL (2101) RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } 00170614: 0000: 00002101 00000000 t0 write GRAS_ALPHA_CONTROL (2073) GRAS_ALPHA_CONTROL: { 0x2 } 0017061c: 0000: 00002073 00000002 t0 write RB_STENCIL_CONTROL (2106) RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } 00170624: 0000: 00002106 00000000 t0 write RB_COPY_CONTROL (20fc) RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_FOUR | MODE = RB_COPY_DEPTH_STENCIL | FASTCLEAR = 0 | GMEM_BASE = 0 } RB_COPY_DEST_BASE: { BASE = 0x4f000 } RB_COPY_DEST_PITCH: { PITCH = 256 } RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_DISABLE | COMPONENT_ENABLE = 0xf | ENDIAN = ENDIAN_NONE | TILE = TILE4_3 } 0017062c: 0000: 000320fc 00000052 0004f000 00000008 0303c068 t0 write UNKNOWN_20EF (20ef) UNKNOWN_20EF: 0 00170640: 0000: 000020ef 00000000 t0 write GRAS_SC_SCREEN_SCISSOR_TL (207c) GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } 00170648: 0000: 0001207c 00000000 003f003f t0 write RB_FRAME_BUFFER_DIMENSION (0ce0) RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } 00170654: 0000: 00000ce0 00400040 t0 write 0xce1 (0ce1) 0xce1: 00000000 0017065c: 0000: 00000ce1 00000000 t3 opcode: CP_LOAD_STATE4 (30) (11 dwords) { DST_OFF = 8 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } 00170670: 0.000000 0.000000 1.000000 1.000000 64.000000 64.000000 1.000000 1.000000 00170670: 0000: 00000000 00000000 3f800000 3f800000 42800000 42800000 3f800000 3f800000 00170664: 0000: c0093000 00a00008 00000001 00000000 00000000 3f800000 3f800000 42800000 00170684: 0020: 42800000 3f800000 3f800000 t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x80000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 2 } draw[88] register values + 00000004 UNKNOWN_0CC5: 0x4 + 00000000 UNKNOWN_0CC6: 0 + 00400040 RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } + 00000000 0xce1: 00000000 !+ 00000002 HLSQ_MODE_CONTROL: 0x2 + 00000000 UNKNOWN_0E42: 0 !+ 00000004 SP_MODE_CONTROL: 0x4 !+ 00000068 TPL1_TP_MODE_CONTROL: 0x68 !+ 00188000 GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } + 00000000 UNKNOWN_2001: 0 + 00000001 GRAS_CNTL: { IJ_PERSP } !+ 00000002 GRAS_ALPHA_CONTROL: { 0x2 } !+ 00000000 GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } !+ 00000808 GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = 0 | MSAA_DISABLE | RASTER_MODE = 0 } !+ 00000000 GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } !+ 003f003f GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } !+ 00000022 RB_RENDER_CONTROL: { DISABLE_COLOR_PIPE | 0x2 } !+ 00001000 RB_MSAA_CONTROL: { DISABLE | SAMPLES = 0 } + 00000000 UNKNOWN_20EF: 0 + 00000e00 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } + 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } !+ 00000052 RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_FOUR | MODE = RB_COPY_DEPTH_STENCIL | FASTCLEAR = 0 | GMEM_BASE = 0 } + 0004f000 RB_COPY_DEST_BASE: { BASE = 0x4f000 } + 00000008 RB_COPY_DEST_PITCH: { PITCH = 256 } !+ 0303c068 RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_DISABLE | COMPONENT_ENABLE = 0xf | ENDIAN = ENDIAN_NONE | TILE = TILE4_3 } + 00000000 RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } + 00000000 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } !+ 40001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | 0x40000000 } + 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } + 00000000 UNKNOWN_2152: 0 + 00000000 UNKNOWN_2153: 0 + 00000000 UNKNOWN_2154: 0 + 00000000 UNKNOWN_2155: 0 + 00000000 UNKNOWN_2156: 0 !+ 0000001d UNKNOWN_21C3: 0x1d !+ 00000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 } + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + 00000000 PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } + 00000001 UNKNOWN_21E6: 0x1 !+ 000a0000 VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } !+ fc030000 VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } + fcfcfcfc VFD_CONTROL_2: 0xfcfcfcfc !+ fcfcfc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } + 0000fcfc VFD_CONTROL_4: 0xfcfc + 00000000 VFD_INDEX_OFFSET: 0 + 00000000 UNKNOWN_2209: 0 + 00060010 SP_SP_CTRL_REG: { 0x60010 } + 000005c3 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } !+ 00200c10 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } !+ 01000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } !+ 0010fc03 SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } !+ 00001e03 SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00fcfc00 UNKNOWN_22D7: 0xfcfc00 + 00000008 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } !+ 00000001 SP_VS_OBJ_START: 0x1 !+ 00000002 SP_VS_LENGTH_REG: 2 + 00000000 TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } !+ 00000003 TPL1_TP_FS_TEX_COUNT: 0x3 !+ 080004f0 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } !+ fcfc0120 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } !+ 27f3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } !+ 02010042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } !+ 0041423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } !+ 00404200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } !+ 00404200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } !+ 00404200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00004200 HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } !+ 00000007 HLSQ_UPDATE_CONTROL: 0x7 00170690: 0000: c0023800 00080888 00000001 00000002 0016b0ac: 0000: c0013f00 001702c4 000000f7 t3 opcode: (null) (1d) (2 dwords) 0016b0b8: 0000: c0001d00 00000000 ############################################################ vertices: 0 ############################################################ cmdstream: 8 dwords t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:000555d8 ibsize:00000155 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 000555d8: 0000: c0002600 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x4 000555e0: 0000: 00000ec3 00000004 t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x68 000555e8: 0000: 00000f03 00000068 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 000555f0: 0000: c0002600 00000000 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } 000555f8: 0000: 000023c0 080004f0 t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = 0x1d } event (null) 00055600: 0000: c0004600 0000001d t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = FACENESS_FLUSH } event FACENESS_FLUSH 00055608: 0000: c0004600 0000001c t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00055610: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0 00055618: 0000: 00000cc6 00000000 t0 write UNKNOWN_0E42 (0e42) UNKNOWN_0E42: 0 00055620: 0000: 00000e42 00000000 t0 write HLSQ_MODE_CONTROL (0e05) HLSQ_MODE_CONTROL: 0x2 00055628: 0000: 00000e05 00000002 t0 write UNKNOWN_0CC5 (0cc5) UNKNOWN_0CC5: 0x4 00055630: 0000: 00000cc5 00000004 t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x7 00055638: 0000: 000023db 00000007 t0 write VFD_CONTROL_2 (2202) VFD_CONTROL_2: 0xfcfcfcfc 00055640: 0000: 00002202 fcfcfcfc t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } 00055648: 0000: 00002203 fcfcfc00 t0 write VFD_CONTROL_4 (2204) VFD_CONTROL_4: 0xfcfc 00055650: 0000: 00002204 0000fcfc t0 write VFD_INDEX_OFFSET (2208) VFD_INDEX_OFFSET: 0 00055658: 0000: 00002208 00000000 t0 write UNKNOWN_2209 (2209) UNKNOWN_2209: 0 00055660: 0000: 00002209 00000000 t0 write UNKNOWN_2152 (2152) UNKNOWN_2152: 0 UNKNOWN_2153: 0 00055668: 0000: 00012152 00000000 00000000 t0 write UNKNOWN_2156 (2156) UNKNOWN_2156: 0 00055674: 0000: 00002156 00000000 t0 write UNKNOWN_2154 (2154) UNKNOWN_2154: 0 0005567c: 0000: 00002154 00000000 t0 write UNKNOWN_2155 (2155) UNKNOWN_2155: 0 00055684: 0000: 00002155 00000000 t0 write UNKNOWN_21C3 (21c3) UNKNOWN_21C3: 0x1d 0005568c: 0000: 000021c3 0000001d t0 write PC_PRIM_VTX_CNTL2 (21c5) PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 00055694: 0000: 000021c5 00000012 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 0005569c: 0000: 000021e5 00000000 t0 write GRAS_SU_MODE_CONTROL (2078) GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } 000556a4: 0000: 00002078 00000000 t0 write UNKNOWN_2001 (2001) UNKNOWN_2001: 0 000556ac: 0000: 00002001 00000000 t0 write GRAS_CNTL (2003) GRAS_CNTL: { IJ_PERSP } 000556b4: 0000: 00002003 00000001 t0 write GRAS_CL_CLIP_CNTL (2000) GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } 000556bc: 0000: 00002000 00188000 t0 write TPL1_TP_TEX_COUNT (2381) TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } 000556c4: 0000: 00002381 00000000 t0 write TPL1_TP_FS_TEX_COUNT (23a0) TPL1_TP_FS_TEX_COUNT: 0x3 000556cc: 0000: 000023a0 00000003 t0 write RB_ALPHA_CONTROL (20f8) RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } 000556d4: 0000: 000020f8 00000e00 t0 write RB_RENDER_COMPONENTS (20fb) RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } 000556dc: 0000: 000020fb 0000000f t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 000556e4: 0000: c0014300 00040000 00000000 t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } 000556f0: 0000: 00002200 000a0000 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } 000556f8: 0000: 00002201 fc030000 t0 write SP_INSTR_CACHE_CTRL (22c1) SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } 00055700: 0000: 000022c1 000005c3 t0 write HLSQ_CONTROL_1_REG (23c1) HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } 00055708: 0000: 000023c1 fcfc0120 t0 write HLSQ_CONTROL_2_REG (23c2) HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 00055710: 0000: 000023c2 27f3f3f0 t0 write HLSQ_VS_CONTROL_REG (23c5) HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } 00055718: 0000: 000023c5 02010042 t0 write HLSQ_FS_CONTROL_REG (23c6) HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 1 } 00055720: 0000: 000023c6 0141423e t0 write HLSQ_HS_CONTROL_REG (23c7) HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00055728: 0000: 000023c7 00404200 t0 write HLSQ_DS_CONTROL_REG (23c8) HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00055730: 0000: 000023c8 00404200 t0 write HLSQ_GS_CONTROL_REG (23c9) HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00055738: 0000: 000023c9 00404200 t0 write HLSQ_CS_CONTROL_REG (23ca) HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } 00055740: 0000: 000023ca 00004200 t0 write SP_SP_CTRL_REG (22c0) SP_SP_CTRL_REG: { 0x60010 } 00055748: 0000: 000022c0 00060010 t0 write UNKNOWN_21E6 (21e6) UNKNOWN_21E6: 0x1 00055750: 0000: 000021e6 00000001 t0 write SP_VS_CTRL_REG0 (22c4) SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 00055758: 0000: 000022c4 00200c10 t0 write SP_VS_CTRL_REG1 (22c5) SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } 00055760: 0000: 000022c5 01000042 t0 write VPC_ATTR (2140) VPC_ATTR: { TOTALATTR = 8 | THRDASSIGN = 1 | ENABLE | 0x40000000 } 00055768: 0000: 00002140 42001008 t0 write VPC_PACK (2141) VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 8 | NUMNONPOSVSVAR = 6 } 00055770: 0000: 00002141 00060800 t0 write PC_PRIM_VTX_CNTL (21c4) PC_PRIM_VTX_CNTL: { VAROUT = 1 } 00055778: 0000: 000021c4 00000001 t0 write SP_VS_PARAM_REG (22c6) SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 2 } SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r1.w | B_COMPMASK = 0x3 } SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } UNKNOWN_22D7: 0xfcfc00 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 12 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 00055780: 0000: 001922c6 0020fc03 06071e03 00000000 00000000 00000000 00000000 00000000 * 000557c0: 0040: 00000000 00000000 00fcfc00 00000c08 00000000 00000000 00000000 00000000 * t0 write SP_VS_OBJ_OFFSET_REG (22e0) SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 000557ec: 0000: 000022e0 00000000 t0 write SP_VS_OBJ_START (22e1) SP_VS_OBJ_START: 0x1 000557f4: 0000: 000022e1 00000001 t0 write SP_VS_LENGTH_REG (22e5) SP_VS_LENGTH_REG: 2 000557fc: 0000: 000022e5 00000002 t3 opcode: CP_LOAD_STATE4 (30) (67 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } :2:0000:0000[56d81803x_20020003x] (sy)(ss)(nop3) shl.b r0.w, r0.w, 2 :1:0001:0004[20150000x_00000003x] cov.s32s16 hr0.x, r0.w :0:0002:0005[00000200x_00000000x] (rpt2)nop :1:0003:0008[201100f4x_00000000x] mova a0.x, hr0.x :0:0004:0009[00000500x_00000000x] (rpt5)nop :1:0005:0015[20154003x_00000c20x] mov.s32s32 r0.w, c :1:0006:0016[20154004x_00000c21x] mov.s32s32 r1.x, c :1:0007:0017[20154007x_00000c22x] mov.s32s32 r1.w, c :1:0008:0018[20156008x_00000c23x] (ul)mov.s32s32 r2.x, c :1:0009:0019[20554005x_00000000x] mov.s32s32 r1.y, 0 :1:0010:0020[20554006x_3f800000x] mov.s32s32 r1.z, 1065353216 :0:0011:0021[03000000x_00000000x] end :2:0012:0022[46f00009x_20050000x] shr.b r2.y, r0.x, 5 :2:0013:0023[4398000ax_201f0000x] (nop2) and.b r2.z, r0.x, 31 :2:0014:0026[43980809x_201f0009x] (nop3) and.b r2.y, r2.y, 31 :2:0015:0030[46100809x_20180009x] (nop1) mul.u24 r2.y, r2.y, 24 :3:0016:0032[62050009x_00091014x] mad.u24 r2.y, c5.x, r2.z, r2.y :0:0017:0033[00000500x_00000000x] (rpt5)nop :6:0018:0039[c2c61300x_04800006x] stlw.u32 l[r2.y], r0.w, 4 :6:0019:0040[c2c61310x_0280000ex] stlw.u32 l[r2.y+16], r1.w, 2 :0:0020:0041[04800000x_00000000x] chmask :0:0021:0042[05000000x_00000000x] chsh Stats: - shaderdb: 43 instr, 24 nops, 19 non-nops, 7 mov, 1 cov - shaderdb: 0 last-baryf, 0 half, 3 full, 5 constlen - shaderdb: 27 cat0, 8 cat1, 5 cat2, 1 cat3, 0 cat4, 0 cat5, 2 cat6, 0 cat7 - shaderdb: 0 sstall, 1 (ss), 1 (sy) 00055804: 0000: c0413000 00a00000 00000000 20020003 56d81803 00000003 20150000 00000000 00055824: 0020: 00000200 00000000 201100f4 00000000 00000500 00000c20 20154003 00000c21 00055844: 0040: 20154004 00000c22 20154007 00000c23 20156008 00000000 20554005 3f800000 00055864: 0060: 20554006 00000000 03000000 20050000 46f00009 201f0000 4398000a 201f0009 00055884: 0080: 43980809 20180009 46100809 00091014 62050009 00000000 00000500 04800006 000558a4: 00a0: c2c61300 0280000e c2c61310 00000000 04800000 00000000 05000000 00000000 * t0 write HLSQ_CONTROL_3_REG (23c3) HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } 00055910: 0000: 000023c3 fcfcfc00 t0 write HLSQ_CONTROL_4_REG (23c4) HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } 00055918: 0000: 000023c4 00fcfcfc t0 write SP_FS_CTRL_REG0 (22e8) SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 0 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE | PIXLODENABLE } SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 } 00055920: 0000: 000122e8 00700402 8010003e t0 write SP_FS_OBJ_OFFSET_REG (22ea) SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 } 0005592c: 0000: 000022ea 40420000 t0 write SP_FS_OBJ_START (22eb) SP_FS_OBJ_START: 0x1 00055934: 0000: 000022eb 00000001 t0 write SP_FS_LENGTH_REG (22ef) SP_FS_LENGTH_REG: 1 0005593c: 0000: 000022ef 00000001 t0 write SP_FS_OUTPUT_REG (22f0) SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r0.x | SAMPLEMASK_REGID = r0.x } 00055944: 0000: 000022f0 00000001 t0 write VPC_VARYING_INTERP[0].MODE (2142) VPC_VARYING_INTERP[0].MODE: 0xe000 0005594c: 0000: 00002142 0000e000 t0 write RB_FS_OUTPUT_REG (2100) RB_FS_OUTPUT_REG: { MRT = 1 } 00055954: 0000: 00002100 00000001 t3 opcode: CP_LOAD_STATE4 (30) (35 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 1 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } :2:0000:0000[57309902x_00002004x] (sy)(ss)(rpt1)bary.f (ei)r0.z, (r)4, r0.x :0:0001:0002[00000500x_00000000x] (rpt5)nop :5:0002:0008[a0c01f00x_00000005x] sam (f32)(xyzw)r0.x, r0.z, s#0, t#0 :0:0003:0009[03000000x_00000000x] end :0:0004:0010[00000000x_00000000x] nop :0:0005:0011[00000000x_00000000x] nop :0:0006:0012[00000000x_00000000x] nop :0:0007:0013[00000000x_00000000x] nop Stats: - shaderdb: 14 instr, 10 nops, 4 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 0 half, 1 full, 0 constlen - shaderdb: 11 cat0, 0 cat1, 2 cat2, 0 cat3, 0 cat4, 1 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 1 (ss), 1 (sy) 0005595c: 0000: c0213000 00700000 00000000 00002004 57309902 00000000 00000500 00000005 0005597c: 0020: a0c01f00 00000000 03000000 00000000 00000000 00000000 00000000 00000000 * t0 write RB_FS_OUTPUT (20f9) RB_FS_OUTPUT: { ENABLE_BLEND = 0 | SAMPLE_MASK = 0xffff } 000559e8: 0000: 000020f9 ffff0000 t0 write RB_MRT[0].CONTROL (20a4) RB_MRT[0].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0xf } 000559f0: 0000: 000020a4 0f000000 t0 write RB_MRT[0x1].CONTROL (20a9) RB_MRT[0x1].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0xf } 000559f8: 0000: 000020a9 0f000000 t0 write RB_MRT[0].BLEND_CONTROL (20a8) RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } 00055a00: 0000: 000020a8 00000000 t3 opcode: CP_LOAD_STATE4 (30) (5 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_TEX | NUM_UNIT = 1 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } { XY_MAG = A4XX_TEX_NEAREST | XY_MIN = A4XX_TEX_NEAREST | WRAP_S = A4XX_TEX_CLAMP_TO_EDGE | WRAP_T = A4XX_TEX_CLAMP_TO_EDGE | WRAP_R = A4XX_TEX_CLAMP_TO_EDGE | ANISO = A4XX_TEX_ANISO_1 | LOD_BIAS = 0.000000 | 0x60000 } { COMPARE_FUNC = FUNC_LEQUAL | UNNORM_COORDS | MIPFILTER_LINEAR_FAR | MAX_LOD = 0.000000 | MIN_LOD = 0.000000 | 0x1 } 00055a14: 0000: 00060920 00000067 00055a08: 0000: c0033000 00500000 00000000 00060920 00000067 t0 write GRAS_SC_CONTROL (207b) GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 0 | RASTER_MODE = 0 } 00055a1c: 0000: 0000207b 00000000 t0 write RB_MSAA_CONTROL (20a2) RB_MSAA_CONTROL: { SAMPLES = 0 } 00055a24: 0000: 000020a2 00000000 t0 write RB_RENDER_CONTROL (20a1) RB_RENDER_CONTROL: { 0 } 00055a2c: 0000: 000020a1 00000000 t0 write 0x2382 (2382) 0x2382: 00000000 00055a34: 0000: 00002382 00000000 t0 write RB_DEPTH_CONTROL (2101) RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } 00055a3c: 0000: 00002101 00000000 t0 write GRAS_ALPHA_CONTROL (2073) GRAS_ALPHA_CONTROL: { 0 } 00055a44: 0000: 00002073 00000000 t0 write RB_STENCIL_CONTROL (2106) RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } 00055a4c: 0000: 00002106 00000000 t0 write SP_FS_MRT[0].REG (22f1) SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = RB4_R8G8B8A8_UNORM } 00055a54: 0000: 000022f1 0001a000 t0 write RB_MRT[0].BUF_INFO (20a5) RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB4_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE4_3 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 256 } RB_MRT[0].BASE: 0x166000 RB_MRT[0].CONTROL3: { STRIDE = 0 } 00055a5c: 0000: 000220a5 000400da 00166000 00000000 t3 opcode: CP_LOAD_STATE4 (30) (11 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_TEX | NUM_UNIT = 1 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } { TILED | SWIZ_X = A4XX_TEX_X | SWIZ_Y = A4XX_TEX_Y | SWIZ_Z = A4XX_TEX_Z | SWIZ_W = A4XX_TEX_W | MIPLVLS = 0 | FMT = TFMT4_8_8_8_8_UNORM | TYPE = A4XX_TEX_2D | 0x2 } { HEIGHT = 64 | WIDTH = 64 } { PITCHALIGN = 0 | PITCH = 256 | SWAP = WZYX } { LAYERSZ = 0 | DEPTH = 1 | 0x20000 } { LAYERSZ = 4096 | BASE = 0x4f000 } { 5 = 0 } { 6 = 0 } { 7 = 0 } 00055a78: 0000: 27006883 00200040 00020000 00060000 0004f001 00000000 00000000 00000000 00055a6c: 0000: c0093000 00500000 00000001 27006883 00200040 00020000 00060000 0004f001 * t0 write VPC_VARYING_PS_REPL[0].MODE (214a) VPC_VARYING_PS_REPL[0].MODE: 0x99999999 00055a98: 0000: 0000214a 99999999 t0 write GRAS_SC_SCREEN_SCISSOR_TL (207c) GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } 00055aa0: 0000: 0001207c 00000000 003f003f t0 write GRAS_SC_WINDOW_SCISSOR_BR (209c) GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 00055aac: 0000: 0001209c 003f003f 00000000 t0 write RB_FRAME_BUFFER_DIMENSION (0ce0) RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } 00055ab8: 0000: 00000ce0 00400040 t0 write 0xce1 (0ce1) 0xce1: 00000000 00055ac0: 0000: 00000ce1 00000000 t0 write RB_RENDER_CONTROL2 (20a3) RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 | IJ_PERSP_PIXEL } 00055ac8: 0000: 000020a3 00001000 t0 write RB_MODE_CONTROL (20a0) RB_MODE_CONTROL: { WIDTH = 0 | HEIGHT = 0 | 0xc00000 } 00055ad0: 0000: 000020a0 00c00000 t3 opcode: CP_LOAD_STATE4 (30) (11 dwords) { DST_OFF = 8 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } 00055ae4: 0.000000 0.000000 0.000000 0.000000 64.000000 64.000000 64.000000 64.000000 00055ae4: 0000: 00000000 00000000 00000000 00000000 42800000 42800000 42800000 42800000 00055ad8: 0000: c0093000 00a00008 00000001 00000000 00000000 00000000 00000000 42800000 00055af8: 0020: 42800000 42800000 42800000 t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x80000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 2 } draw[89] register values + 00000004 UNKNOWN_0CC5: 0x4 + 00000000 UNKNOWN_0CC6: 0 + 00400040 RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } + 00000000 0xce1: 00000000 + 00000002 HLSQ_MODE_CONTROL: 0x2 + 00000000 UNKNOWN_0E42: 0 + 00000004 SP_MODE_CONTROL: 0x4 + 00000068 TPL1_TP_MODE_CONTROL: 0x68 + 00188000 GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } + 00000000 UNKNOWN_2001: 0 + 00000001 GRAS_CNTL: { IJ_PERSP } !+ 00000000 GRAS_ALPHA_CONTROL: { 0 } + 00000000 GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } !+ 00000000 GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 0 | RASTER_MODE = 0 } + 00000000 GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } + 003f003f GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } + 003f003f GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } + 00000000 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } !+ 00c00000 RB_MODE_CONTROL: { WIDTH = 0 | HEIGHT = 0 | 0xc00000 } !+ 00000000 RB_RENDER_CONTROL: { 0 } !+ 00000000 RB_MSAA_CONTROL: { SAMPLES = 0 } !+ 00001000 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 | IJ_PERSP_PIXEL } !+ 0f000000 RB_MRT[0].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0xf } !+ 000400da RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB4_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE4_3 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 256 } !+ 00166000 RB_MRT[0].BASE: 0x166000 !+ 00000000 RB_MRT[0].CONTROL3: { STRIDE = 0 } + 00000000 RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } + 0f000000 RB_MRT[0x1].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0xf } + 00000e00 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } !+ ffff0000 RB_FS_OUTPUT: { ENABLE_BLEND = 0 | SAMPLE_MASK = 0xffff } + 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } + 00000001 RB_FS_OUTPUT_REG: { MRT = 1 } + 00000000 RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } + 00000000 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } !+ 42001008 VPC_ATTR: { TOTALATTR = 8 | THRDASSIGN = 1 | ENABLE | 0x40000000 } !+ 00060800 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 8 | NUMNONPOSVSVAR = 6 } !+ 0000e000 VPC_VARYING_INTERP[0].MODE: 0xe000 !+ 99999999 VPC_VARYING_PS_REPL[0].MODE: 0x99999999 + 00000000 UNKNOWN_2152: 0 + 00000000 UNKNOWN_2153: 0 + 00000000 UNKNOWN_2154: 0 + 00000000 UNKNOWN_2155: 0 + 00000000 UNKNOWN_2156: 0 + 0000001d UNKNOWN_21C3: 0x1d + 00000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 } + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + 00000000 PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } + 00000001 UNKNOWN_21E6: 0x1 + 000a0000 VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } + fc030000 VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } + fcfcfcfc VFD_CONTROL_2: 0xfcfcfcfc + fcfcfc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } + 0000fcfc VFD_CONTROL_4: 0xfcfc + 00000000 VFD_INDEX_OFFSET: 0 + 00000000 UNKNOWN_2209: 0 + 00060010 SP_SP_CTRL_REG: { 0x60010 } + 000005c3 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } + 00200c10 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } + 01000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } !+ 0020fc03 SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 2 } !+ 06071e03 SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r1.w | B_COMPMASK = 0x3 } + 00000000 SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00fcfc00 UNKNOWN_22D7: 0xfcfc00 !+ 00000c08 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 12 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } + 00000001 SP_VS_OBJ_START: 0x1 + 00000002 SP_VS_LENGTH_REG: 2 !+ 00700402 SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 0 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE | PIXLODENABLE } !+ 8010003e SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 } !+ 40420000 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 } !+ 00000001 SP_FS_OBJ_START: 0x1 + 00000001 SP_FS_LENGTH_REG: 1 !+ 00000001 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r0.x | SAMPLEMASK_REGID = r0.x } !+ 0001a000 SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = RB4_R8G8B8A8_UNORM } + 00000000 TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } !+ 00000000 0x2382: 00000000 + 00000003 TPL1_TP_FS_TEX_COUNT: 0x3 + 080004f0 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } + fcfc0120 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } + 27f3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } + fcfcfc00 HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } !+ 00fcfcfc HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } + 02010042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } !+ 0141423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 1 } + 00404200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00004200 HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } + 00000007 HLSQ_UPDATE_CONTROL: 0x7 00055b04: 0000: c0023800 00080888 00000001 00000002 t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = CACHE_FLUSH } event CACHE_FLUSH 00055b14: 0000: c0004600 00000006 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00055b1c: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0x8000012 00055b24: 0000: 00000cc6 08000012 00173000: 0000: c0013f00 000555d8 00000155 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 0017300c: 0000: c0014300 00040000 00000000 t3 opcode: (null) (1d) (2 dwords) 00173018: 0000: c0001d00 00000000 ############################################################ vertices: 0 ############################################################ cmdstream: 48 dwords t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 0016b000: 0000: c0002600 00000000 t0 write UCHE_INVALIDATE0 (0e8a) UCHE_INVALIDATE0: 0 UCHE_INVALIDATE1: 0x12 0016b008: 0000: 00010e8a 00000000 00000012 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 0016b014: 0000: c0002600 00000000 t0 write RB_MODE_CONTROL (20a0) RB_MODE_CONTROL: { WIDTH = 64 | HEIGHT = 64 | ENABLE_GMEM } 0016b01c: 0000: 000020a0 00010202 t0 write RB_FRAME_BUFFER_DIMENSION (0ce0) RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } 0016b024: 0000: 00000ce0 00400040 t0 write 0xce1 (0ce1) 0xce1: 00000001 0016b02c: 0000: 00000ce1 00000001 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 0016b034: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0 0016b03c: 0000: 00000cc6 00000000 t3 opcode: (null) (1d) (2 dwords) 0016b044: 0000: c0001d00 00000000 t0 write GRAS_SC_WINDOW_SCISSOR_BR (209c) GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 0016b04c: 0000: 0001209c 003f003f 00000000 t0 write RB_BIN_OFFSET (210d) RB_BIN_OFFSET: { X = 0 | Y = 0 } 0016b058: 0000: 0000210d 00000000 t0 write GRAS_SC_WINDOW_SCISSOR_BR (209c) GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 0016b060: 0000: 0001209c 003f003f 00000000 t0 write UNKNOWN_2157 (2157) UNKNOWN_2157: 0x1 0016b06c: 0000: 00002157 00000001 t3 opcode: (null) (64) (2 dwords) 0016b074: 0000: c0006400 00000001 t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:00054994 ibsize:000000f6 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00054994: 0000: c0002600 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x4 0005499c: 0000: 00000ec3 00000004 t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x68 000549a4: 0000: 00000f03 00000068 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 000549ac: 0000: c0002600 00000000 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } 000549b4: 0000: 000023c0 080004f0 t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = 0x1d } event (null) 000549bc: 0000: c0004600 0000001d t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = FACENESS_FLUSH } event FACENESS_FLUSH 000549c4: 0000: c0004600 0000001c t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 000549cc: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0 000549d4: 0000: 00000cc6 00000000 t0 write UNKNOWN_0E42 (0e42) UNKNOWN_0E42: 0 000549dc: 0000: 00000e42 00000000 t0 write HLSQ_MODE_CONTROL (0e05) HLSQ_MODE_CONTROL: 0x2 000549e4: 0000: 00000e05 00000002 t0 write UNKNOWN_0CC5 (0cc5) UNKNOWN_0CC5: 0x4 000549ec: 0000: 00000cc5 00000004 t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x7 000549f4: 0000: 000023db 00000007 t0 write VFD_CONTROL_2 (2202) VFD_CONTROL_2: 0xfcfcfcfc 000549fc: 0000: 00002202 fcfcfcfc t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } 00054a04: 0000: 00002203 fcfcfc00 t0 write VFD_CONTROL_4 (2204) VFD_CONTROL_4: 0xfcfc 00054a0c: 0000: 00002204 0000fcfc t0 write VFD_INDEX_OFFSET (2208) VFD_INDEX_OFFSET: 0 00054a14: 0000: 00002208 00000000 t0 write UNKNOWN_2209 (2209) UNKNOWN_2209: 0 00054a1c: 0000: 00002209 00000000 t0 write UNKNOWN_2152 (2152) UNKNOWN_2152: 0 UNKNOWN_2153: 0 00054a24: 0000: 00012152 00000000 00000000 t0 write UNKNOWN_2156 (2156) UNKNOWN_2156: 0 00054a30: 0000: 00002156 00000000 t0 write UNKNOWN_2154 (2154) UNKNOWN_2154: 0 00054a38: 0000: 00002154 00000000 t0 write UNKNOWN_2155 (2155) UNKNOWN_2155: 0 00054a40: 0000: 00002155 00000000 t0 write UNKNOWN_21C3 (21c3) UNKNOWN_21C3: 0x1d 00054a48: 0000: 000021c3 0000001d t0 write PC_PRIM_VTX_CNTL2 (21c5) PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 00054a50: 0000: 000021c5 00000012 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 00054a58: 0000: 000021e5 00000000 t0 write GRAS_SU_MODE_CONTROL (2078) GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } 00054a60: 0000: 00002078 00000000 t0 write UNKNOWN_2001 (2001) UNKNOWN_2001: 0 00054a68: 0000: 00002001 00000000 t0 write GRAS_CNTL (2003) GRAS_CNTL: { IJ_PERSP } 00054a70: 0000: 00002003 00000001 t0 write GRAS_CL_CLIP_CNTL (2000) GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } 00054a78: 0000: 00002000 00188000 t0 write TPL1_TP_TEX_COUNT (2381) TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } 00054a80: 0000: 00002381 00000000 t0 write TPL1_TP_FS_TEX_COUNT (23a0) TPL1_TP_FS_TEX_COUNT: 0x3 00054a88: 0000: 000023a0 00000003 t0 write RB_ALPHA_CONTROL (20f8) RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } 00054a90: 0000: 000020f8 00000e00 t0 write RB_RENDER_COMPONENTS (20fb) RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } 00054a98: 0000: 000020fb 0000000f t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 00054aa0: 0000: c0014300 00040000 00000000 t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } 00054aac: 0000: 00002200 000a0000 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } 00054ab4: 0000: 00002201 fc030000 t0 write SP_INSTR_CACHE_CTRL (22c1) SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } 00054abc: 0000: 000022c1 000005c3 t0 write HLSQ_CONTROL_1_REG (23c1) HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } 00054ac4: 0000: 000023c1 fcfc0120 t0 write HLSQ_CONTROL_2_REG (23c2) HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 00054acc: 0000: 000023c2 27f3f3f0 t0 write HLSQ_VS_CONTROL_REG (23c5) HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } 00054ad4: 0000: 000023c5 02010042 t0 write HLSQ_FS_CONTROL_REG (23c6) HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00054adc: 0000: 000023c6 0041423e t0 write HLSQ_HS_CONTROL_REG (23c7) HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00054ae4: 0000: 000023c7 00404200 t0 write HLSQ_DS_CONTROL_REG (23c8) HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00054aec: 0000: 000023c8 00404200 t0 write HLSQ_GS_CONTROL_REG (23c9) HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00054af4: 0000: 000023c9 00404200 t0 write HLSQ_CS_CONTROL_REG (23ca) HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } 00054afc: 0000: 000023ca 00004200 t0 write SP_SP_CTRL_REG (22c0) SP_SP_CTRL_REG: { 0x60010 } 00054b04: 0000: 000022c0 00060010 t0 write UNKNOWN_21E6 (21e6) UNKNOWN_21E6: 0x1 00054b0c: 0000: 000021e6 00000001 t0 write SP_VS_CTRL_REG0 (22c4) SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 00054b14: 0000: 000022c4 00200c10 t0 write SP_VS_CTRL_REG1 (22c5) SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } 00054b1c: 0000: 000022c5 01000042 t0 write VPC_ATTR (2140) VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | 0x40000000 } 00054b24: 0000: 00002140 40001004 t0 write VPC_PACK (2141) VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } 00054b2c: 0000: 00002141 00040400 t0 write PC_PRIM_VTX_CNTL (21c4) PC_PRIM_VTX_CNTL: { VAROUT = 1 } 00054b34: 0000: 000021c4 00000001 t0 write SP_VS_PARAM_REG (22c6) SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } UNKNOWN_22D7: 0xfcfc00 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 00054b3c: 0000: 001922c6 0010fc03 00001e03 00000000 00000000 00000000 00000000 00000000 * 00054b7c: 0040: 00000000 00000000 00fcfc00 00000008 00000000 00000000 00000000 00000000 * t0 write SP_VS_OBJ_OFFSET_REG (22e0) SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 00054ba8: 0000: 000022e0 00000000 t0 write SP_VS_OBJ_START (22e1) SP_VS_OBJ_START: 0x1 00054bb0: 0000: 000022e1 00000001 t0 write SP_VS_LENGTH_REG (22e5) SP_VS_LENGTH_REG: 2 00054bb8: 0000: 000022e5 00000002 t3 opcode: CP_LOAD_STATE4 (30) (67 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } :2:0000:0000[56d81803x_20020003x] (sy)(ss)(nop3) shl.b r0.w, r0.w, 2 :1:0001:0004[20150000x_00000003x] cov.s32s16 hr0.x, r0.w :0:0002:0005[00000200x_00000000x] (rpt2)nop :1:0003:0008[201100f4x_00000000x] mova a0.x, hr0.x :0:0004:0009[00000500x_00000000x] (rpt5)nop :1:0005:0015[20154003x_00000c20x] mov.s32s32 r0.w, c :1:0006:0016[20154004x_00000c21x] mov.s32s32 r1.x, c :1:0007:0017[20154005x_00000c22x] mov.s32s32 r1.y, c :1:0008:0018[20156006x_00000c23x] (ul)mov.s32s32 r1.z, c :0:0009:0019[03000000x_00000000x] end :2:0010:0020[46f00007x_20050000x] shr.b r1.w, r0.x, 5 :2:0011:0021[43980008x_201f0000x] (nop2) and.b r2.x, r0.x, 31 :2:0012:0024[43980807x_201f0007x] (nop3) and.b r1.w, r1.w, 31 :2:0013:0028[46100807x_20100007x] (nop1) mul.u24 r1.w, r1.w, 16 :3:0014:0030[62040007x_00071014x] mad.u24 r1.w, c5.x, r2.x, r1.w :0:0015:0031[00000500x_00000000x] (rpt5)nop :6:0016:0037[c2c60f00x_04800006x] stlw.u32 l[r1.w], r0.w, 4 :0:0017:0038[04800000x_00000000x] chmask :0:0018:0039[05000000x_00000000x] chsh Stats: - shaderdb: 40 instr, 24 nops, 16 non-nops, 5 mov, 1 cov - shaderdb: 0 last-baryf, 0 half, 2 full, 5 constlen - shaderdb: 27 cat0, 6 cat1, 5 cat2, 1 cat3, 0 cat4, 0 cat5, 1 cat6, 0 cat7 - shaderdb: 0 sstall, 1 (ss), 1 (sy) 00054bc0: 0000: c0413000 00a00000 00000000 20020003 56d81803 00000003 20150000 00000000 00054be0: 0020: 00000200 00000000 201100f4 00000000 00000500 00000c20 20154003 00000c21 00054c00: 0040: 20154004 00000c22 20154005 00000c23 20156006 00000000 03000000 20050000 00054c20: 0060: 46f00007 201f0000 43980008 201f0007 43980807 20100007 46100807 00071014 00054c40: 0080: 62040007 00000000 00000500 04800006 c2c60f00 00000000 04800000 00000000 00054c60: 00a0: 05000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 * t0 write GRAS_ALPHA_CONTROL (2073) GRAS_ALPHA_CONTROL: { 0x2 } 00054ccc: 0000: 00002073 00000002 t0 write GRAS_SC_CONTROL (207b) GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = 4 | MSAA_DISABLE | RASTER_MODE = 0 } 00054cd4: 0000: 0000207b 00000a08 t0 write RB_MSAA_CONTROL (20a2) RB_MSAA_CONTROL: { DISABLE | SAMPLES = 4 } 00054cdc: 0000: 000020a2 00009000 t0 write RB_RENDER_CONTROL (20a1) RB_RENDER_CONTROL: { DISABLE_COLOR_PIPE | 0x2 } 00054ce4: 0000: 000020a1 00000022 t0 write RB_CLEAR_COLOR_DW0 (20cc) RB_CLEAR_COLOR_DW0: 0xff000000 RB_CLEAR_COLOR_DW1: 0 RB_CLEAR_COLOR_DW2: 0 RB_CLEAR_COLOR_DW3: 0 00054cec: 0000: 000320cc ff000000 00000000 00000000 00000000 t0 write RB_COPY_CONTROL (20fc) RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_FOUR | MODE = RB_COPY_CLEAR | FASTCLEAR = 0xf | GMEM_BASE = 0 } RB_COPY_DEST_BASE: { BASE = 0x4f000 } RB_COPY_DEST_PITCH: { PITCH = 256 } RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_IF_ALPHA_OFF | COMPONENT_ENABLE = 0 | ENDIAN = ENDIAN_NONE | TILE = TILE4_3 } 00054d00: 0000: 000320fc 00000f22 0004f000 00000008 03000868 t0 write GRAS_SC_SCREEN_SCISSOR_TL (207c) GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } 00054d14: 0000: 0001207c 00000000 003f003f t0 write RB_FRAME_BUFFER_DIMENSION (0ce0) RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } 00054d20: 0000: 00000ce0 00400040 t0 write 0xce1 (0ce1) 0xce1: 00000000 00054d28: 0000: 00000ce1 00000000 t3 opcode: CP_LOAD_STATE4 (30) (11 dwords) { DST_OFF = 8 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } 00054d3c: 0.000000 0.000000 1.000000 1.000000 64.000000 64.000000 1.000000 1.000000 00054d3c: 0000: 00000000 00000000 3f800000 3f800000 42800000 42800000 3f800000 3f800000 00054d30: 0000: c0093000 00a00008 00000001 00000000 00000000 3f800000 3f800000 42800000 00054d50: 0020: 42800000 3f800000 3f800000 t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x80000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 2 } draw[90] register values + 00000004 UNKNOWN_0CC5: 0x4 + 00000000 UNKNOWN_0CC6: 0 + 00400040 RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } + 00000000 0xce1: 00000000 + 00000002 HLSQ_MODE_CONTROL: 0x2 + 00000000 UNKNOWN_0E42: 0 + 00000000 UCHE_INVALIDATE0: 0 + 00000012 UCHE_INVALIDATE1: 0x12 + 00000004 SP_MODE_CONTROL: 0x4 + 00000068 TPL1_TP_MODE_CONTROL: 0x68 + 00188000 GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } + 00000000 UNKNOWN_2001: 0 + 00000001 GRAS_CNTL: { IJ_PERSP } !+ 00000002 GRAS_ALPHA_CONTROL: { 0x2 } + 00000000 GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } !+ 00000a08 GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = 4 | MSAA_DISABLE | RASTER_MODE = 0 } + 00000000 GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } + 003f003f GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } + 003f003f GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } + 00000000 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } !+ 00010202 RB_MODE_CONTROL: { WIDTH = 64 | HEIGHT = 64 | ENABLE_GMEM } !+ 00000022 RB_RENDER_CONTROL: { DISABLE_COLOR_PIPE | 0x2 } !+ 00009000 RB_MSAA_CONTROL: { DISABLE | SAMPLES = 4 } + ff000000 RB_CLEAR_COLOR_DW0: 0xff000000 + 00000000 RB_CLEAR_COLOR_DW1: 0 + 00000000 RB_CLEAR_COLOR_DW2: 0 + 00000000 RB_CLEAR_COLOR_DW3: 0 + 00000e00 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } + 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } !+ 00000f22 RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_FOUR | MODE = RB_COPY_CLEAR | FASTCLEAR = 0xf | GMEM_BASE = 0 } + 0004f000 RB_COPY_DEST_BASE: { BASE = 0x4f000 } + 00000008 RB_COPY_DEST_PITCH: { PITCH = 256 } !+ 03000868 RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_IF_ALPHA_OFF | COMPONENT_ENABLE = 0 | ENDIAN = ENDIAN_NONE | TILE = TILE4_3 } + 00000000 RB_BIN_OFFSET: { X = 0 | Y = 0 } !+ 40001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | 0x40000000 } !+ 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } + 00000000 UNKNOWN_2152: 0 + 00000000 UNKNOWN_2153: 0 + 00000000 UNKNOWN_2154: 0 + 00000000 UNKNOWN_2155: 0 + 00000000 UNKNOWN_2156: 0 + 00000001 UNKNOWN_2157: 0x1 + 0000001d UNKNOWN_21C3: 0x1d + 00000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 } + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + 00000000 PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } + 00000001 UNKNOWN_21E6: 0x1 + 000a0000 VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } + fc030000 VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } + fcfcfcfc VFD_CONTROL_2: 0xfcfcfcfc + fcfcfc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } + 0000fcfc VFD_CONTROL_4: 0xfcfc + 00000000 VFD_INDEX_OFFSET: 0 + 00000000 UNKNOWN_2209: 0 + 00060010 SP_SP_CTRL_REG: { 0x60010 } + 000005c3 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } + 00200c10 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } + 01000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } !+ 0010fc03 SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } !+ 00001e03 SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00fcfc00 UNKNOWN_22D7: 0xfcfc00 !+ 00000008 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } + 00000001 SP_VS_OBJ_START: 0x1 + 00000002 SP_VS_LENGTH_REG: 2 + 00000000 TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } + 00000003 TPL1_TP_FS_TEX_COUNT: 0x3 + 080004f0 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } + fcfc0120 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } + 27f3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } + 02010042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } !+ 0041423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00004200 HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } + 00000007 HLSQ_UPDATE_CONTROL: 0x7 00054d5c: 0000: c0023800 00080888 00000001 00000002 0016b07c: 0000: c0013f00 00054994 000000f6 t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:00054d6c ibsize:00000037 t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } 00054d6c: 0000: 00002200 082a0008 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00054d74: 0000: c0002600 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x1e 00054d7c: 0000: 00000ec3 0000001e t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x28 00054d84: 0000: 00000f03 00000028 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00054d8c: 0000: c0002600 00000000 t0 write HLSQ_MODE_CONTROL (0e05) HLSQ_MODE_CONTROL: 0x1 00054d94: 0000: 00000e05 00000001 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0x600a0 } 00054d9c: 0000: 000023c0 080604f0 t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x7 00054da4: 0000: 000023db 00000007 t0 write PC_RESTART_INDEX (21c6) PC_RESTART_INDEX: 0xffffffff 00054dac: 0000: 000021c6 ffffffff t0 write UNKNOWN_21E6 (21e6) UNKNOWN_21E6: 0x1 00054db4: 0000: 000021e6 00000001 t0 write UNKNOWN_21C3 (21c3) UNKNOWN_21C3: 0x1f 00054dbc: 0000: 000021c3 0000001f t0 write TPL1_TP_TEX_OFFSET (2380) TPL1_TP_TEX_OFFSET: 0x808 00054dc4: 0000: 00002380 00000808 t0 write GRAS_SU_POINT_MINMAX (2070) GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 4092.000000 } GRAS_SU_POINT_SIZE: 0.500000 00054dcc: 0000: 00012070 ffc00010 00000008 t0 write UNKNOWN_2152 (2152) UNKNOWN_2152: 0 UNKNOWN_2153: 0 00054dd8: 0000: 00012152 00000000 00000000 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00054de4: 0000: c0002600 00000000 t0 write UNKNOWN_0CC5 (0cc5) UNKNOWN_0CC5: 0x4 00054dec: 0000: 00000cc5 00000004 t0 write 0xcc4 (0cc4) 0xcc4: 00000000 00054df4: 0000: 00000cc4 00000000 t0 write 0xd03 (0d03) 0xd03: 80200000 00054dfc: 0000: 00000d03 80200000 t0 write UNKNOWN_0EC2 (0ec2) UNKNOWN_0EC2: 0x40000 00054e04: 0000: 00000ec2 00040000 t0 write VPC_DEBUG_ECO_CONTROL (0e64) VPC_DEBUG_ECO_CONTROL: 0x100 00054e0c: 0000: 00000e64 00000100 t0 write UNKNOWN_0E42 (0e42) UNKNOWN_0E42: 0 00054e14: 0000: 00000e42 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x1e 00054e1c: 0000: 00000ec3 0000001e t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x28 00054e24: 0000: 00000f03 00000028 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 00054e2c: 0000: c0014300 00040000 00000000 t0 write VFD_INDEX_OFFSET (2208) VFD_INDEX_OFFSET: 0 00054e38: 0000: 00002208 00000000 t0 write UNKNOWN_2209 (2209) UNKNOWN_2209: 0 00054e40: 0000: 00002209 00000000 0016b088: 0000: c0013f00 00054d6c 00000037 t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:00055328 ibsize:000000ac t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x3 00055328: 0000: 000023db 00000003 t0 write SP_INSTR_CACHE_CTRL (22c1) SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } 00055330: 0000: 000022c1 000005c3 t0 write HLSQ_CONTROL_1_REG (23c1) HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x1008 } 00055338: 0000: 000023c1 fcfc1108 t0 write HLSQ_CONTROL_2_REG (23c2) HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 00055340: 0000: 000023c2 fff3f3f0 t0 write HLSQ_VS_CONTROL_REG (23c5) HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 2 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 1 } 00055348: 0000: 000023c5 01010002 t0 write HLSQ_HS_CONTROL_REG (23c7) HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 00055350: 0000: 000023c7 007e0200 t0 write HLSQ_DS_CONTROL_REG (23c8) HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 00055358: 0000: 000023c8 007e0200 t0 write HLSQ_GS_CONTROL_REG (23c9) HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 00055360: 0000: 000023c9 007e0200 t0 write HLSQ_FS_CONTROL_REG (23c6) HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 2 | CONSTOBJECTOFFSET = 2 | ENABLED | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 } 00055368: 0000: 000023c6 017f0202 t0 write SP_VS_OBJ_OFFSET_REG (22e0) SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 00055370: 0000: 000022e0 00000000 t0 write SP_HS_OBJ_OFFSET_REG (230d) SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } 00055378: 0000: 0000230d 7e020000 t0 write SP_DS_OBJ_OFFSET_REG (2334) SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } 00055380: 0000: 00002334 7e020000 t0 write SP_GS_OBJ_OFFSET_REG (235b) SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } 00055388: 0000: 0000235b 7e020000 t0 write SP_FS_OBJ_OFFSET_REG (22ea) SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } 00055390: 0000: 000022ea 7e020000 t0 write SP_VS_OBJ_START (22e1) SP_VS_OBJ_START: 0x49000 00049000: 0000: 00000000 13000000 00000000 00000000 00000000 00000000 00000000 00000000 * :0:0000:0000[13000000x_00000000x] (sy)end :0:0001:0001[00000000x_00000000x] nop :0:0002:0002[00000000x_00000000x] nop :0:0003:0003[00000000x_00000000x] nop :0:0004:0004[00000000x_00000000x] nop Stats: - shaderdb: 5 instr, 4 nops, 1 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 0 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 0 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) 00055398: 0000: 000022e1 00049000 t0 write SP_HS_OBJ_START (230e) SP_HS_OBJ_START: 0 000553a0: 0000: 0000230e 00000000 t0 write SP_DS_OBJ_START (2335) SP_DS_OBJ_START: 0 000553a8: 0000: 00002335 00000000 t0 write SP_GS_OBJ_START (235c) SP_GS_OBJ_START: 0 000553b0: 0000: 0000235c 00000000 t0 write SP_VS_LENGTH_REG (22e5) SP_VS_LENGTH_REG: 1 000553b8: 0000: 000022e5 00000001 t3 opcode: CP_LOAD_STATE4 (30) (3 dwords) { DST_OFF = 0 | STATE_SRC = SS4_INDIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 1 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0x49000 } :0:0000:0000[13000000x_00000000x] (sy)end :0:0001:0001[00000000x_00000000x] nop :0:0002:0002[00000000x_00000000x] nop :0:0003:0003[00000000x_00000000x] nop :0:0004:0004[00000000x_00000000x] nop Stats: - shaderdb: 5 instr, 4 nops, 1 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 0 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 0 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) 000553c0: 0000: c0013000 00620000 00049000 t0 write 0x2072 (2072) 0x2072: 00000000 000553cc: 0000: 00002072 00000000 t0 write UNKNOWN_2155 (2155) UNKNOWN_2155: 0 000553d4: 0000: 00002155 00000000 t0 write GRAS_CNTL (2003) GRAS_CNTL: { IJ_PERSP } 000553dc: 0000: 00002003 00000001 t0 write VPC_VARYING_INTERP[0].MODE (2142) VPC_VARYING_INTERP[0].MODE: 0 000553e4: 0000: 00002142 00000000 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0x600a0 } 000553ec: 0000: 000023c0 080604f0 t0 write HLSQ_CONTROL_3_REG (23c3) HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } 000553f4: 0000: 000023c3 fcfcfc00 t0 write HLSQ_CONTROL_4_REG (23c4) HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r0.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } 000553fc: 0000: 000023c4 00fcfc00 t0 write SP_FS_CTRL_REG0 (22e8) SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE } SP_FS_CTRL_REG1: { CONSTLENGTH = 2 | VARYING | 0x80000000 } 00055404: 0000: 000122e8 00340412 80100002 t0 write SP_FS_OBJ_START (22eb) SP_FS_OBJ_START: 0x46000 00046000: 0000: 00002000 5730cb00 00000000 03000000 00000000 00000000 00000000 00000000 * :2:0000:0000[5730cb00x_00002000x] (sy)(rpt3)bary.f (ei)hr0.x, (r)0, r0.x :0:0001:0004[03000000x_00000000x] end :0:0002:0005[00000000x_00000000x] nop :0:0003:0006[00000000x_00000000x] nop :0:0004:0007[00000000x_00000000x] nop :0:0005:0008[00000000x_00000000x] nop Stats: - shaderdb: 9 instr, 4 nops, 5 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 1 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 4 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) 00055410: 0000: 000022eb 00046000 t0 write SP_FS_LENGTH_REG (22ef) SP_FS_LENGTH_REG: 1 00055418: 0000: 000022ef 00000001 t0 write RB_RENDER_COMPONENTS (20fb) RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } 00055420: 0000: 000020fb 0000000f t3 opcode: CP_LOAD_STATE4 (30) (3 dwords) { DST_OFF = 0 | STATE_SRC = SS4_INDIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 1 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0x46000 } :2:0000:0000[5730cb00x_00002000x] (sy)(rpt3)bary.f (ei)hr0.x, (r)0, r0.x :0:0001:0004[03000000x_00000000x] end :0:0002:0005[00000000x_00000000x] nop :0:0003:0006[00000000x_00000000x] nop :0:0004:0007[00000000x_00000000x] nop :0:0005:0008[00000000x_00000000x] nop Stats: - shaderdb: 9 instr, 4 nops, 5 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 1 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 4 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) 00055428: 0000: c0013000 00720000 00046000 t0 write SP_SP_CTRL_REG (22c0) SP_SP_CTRL_REG: { 0x60010 } 00055434: 0000: 000022c0 00060010 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 28 | GROUP_ID = 3 } { ADDR_LO = 0x9d080 } 0005543c: 0000: c0014300 0300001c 0009d080 t0 write RB_DEPTH_INFO (2103) RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTH4_NONE | DEPTH_BASE = 0 } RB_DEPTH_PITCH: 0 RB_DEPTH_PITCH2: 0 00055448: 0000: 00022103 00000000 00000000 00000000 t0 write GRAS_DEPTH_CONTROL (2077) GRAS_DEPTH_CONTROL: { FORMAT = DEPTH4_NONE } 00055458: 0000: 00002077 00000000 t0 write RB_STENCIL_INFO (2108) RB_STENCIL_INFO: { STENCIL_BASE = 0 } RB_STENCIL_PITCH: 0 0x210a: 00000000 00055460: 0000: 00022108 00000000 00000000 00000000 t0 write 0x2002 (2002) 0x2002: 00000000 00055470: 0000: 00002002 00000000 t0 write RB_ALPHA_CONTROL (20f8) RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } 00055478: 0000: 000020f8 00000e00 t0 write RB_MRT[0].CONTROL (20a4) RB_MRT[0].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0x7 } 00055480: 0000: 000020a4 07000c00 t0 write RB_MRT[0].BLEND_CONTROL (20a8) RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } 00055488: 0000: 000020a8 00000000 t0 write GRAS_CL_CLIP_CNTL (2000) GRAS_CL_CLIP_CNTL: { 0x80000 } 00055490: 0000: 00002000 00080000 t0 write GRAS_SU_POLY_OFFSET_SCALE (2074) GRAS_SU_POLY_OFFSET_SCALE: 0.000000 GRAS_SU_POLY_OFFSET_OFFSET: 0.000000 GRAS_SU_POLY_OFFSET_CLAMP: 0.000000 00055498: 0000: 00022074 00000000 00000000 00000000 t0 write GRAS_SU_MODE_CONTROL (2078) GRAS_SU_MODE_CONTROL: { FRONT_CW | LINEHALFWIDTH = 0.500000 | MSAA_ENABLE | RENDERING_PASS } 000554a8: 0000: 00002078 00102014 t0 write GRAS_SC_SCREEN_SCISSOR_TL (207c) GRAS_SC_SCREEN_SCISSOR_TL: { X = 2 | Y = 13 } GRAS_SC_SCREEN_SCISSOR_BR: { X = 33 | Y = 44 } 000554b0: 0000: 0001207c 000d0002 002c0021 t0 write GRAS_CL_VPORT_XOFFSET_0 (2008) GRAS_CL_VPORT_XOFFSET_0: 18.000000 GRAS_CL_VPORT_XSCALE_0: 16.000000 GRAS_CL_VPORT_YOFFSET_0: 29.000000 GRAS_CL_VPORT_YSCALE_0: 16.000000 GRAS_CL_VPORT_ZOFFSET_0: 0.500000 GRAS_CL_VPORT_ZSCALE_0: 0.500000 000554bc: 0000: 00052008 41900000 41800000 41e80000 41800000 3f000000 3f000000 t0 write GRAS_CL_GB_CLIP_ADJ (2004) GRAS_CL_GB_CLIP_ADJ: { HORZ = 511 | VERT = 511 } 000554d8: 0000: 00002004 0007fdff t0 write GRAS_SC_CONTROL (207b) GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 4 | RASTER_MODE = 0 } 000554e0: 0000: 0000207b 00000200 t0 write 0x2382 (2382) 0x2382: 00000002 000554e8: 0000: 00002382 00000002 t0 write RB_MSAA_CONTROL (20a2) RB_MSAA_CONTROL: { SAMPLES = 4 } 000554f0: 0000: 000020a2 00008000 t0 write RB_RENDER_CONTROL2 (20a3) RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 4 | IJ_PERSP_PIXEL } 000554f8: 0000: 000020a3 00001200 t0 write RB_MRT[0].BUF_INFO (20a5) RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB4_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_ALWAYS | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 1024 } RB_MRT[0].BASE: 0 RB_MRT[0].CONTROL3: { STRIDE = 64 } 00055500: 0000: 000220a5 0010029a 00000000 00000200 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 43 | GROUP_ID = 2 } { ADDR_LO = 0x9d0f0 } 00055510: 0000: c0014300 0200002b 0009d0f0 t0 write 0x215c (215c) 0x215c: 00000000 0x215d: 00000000 0005551c: 0000: 0001215c 00000000 00000000 t0 write 0x215f (215f) 0x215f: 00000000 00055528: 0000: 0000215f 00000000 t0 write 0x215e (215e) 0x215e: 00000000 00055530: 0000: 0000215e 00000000 t0 write 0x2161 (2161) 0x2161: 00000000 0x2162: 00000000 00055538: 0000: 00012161 00000000 00000000 t0 write 0x2164 (2164) 0x2164: 00000000 00055544: 0000: 00002164 00000000 t0 write 0x2163 (2163) 0x2163: 00000000 0005554c: 0000: 00002163 00000000 t0 write 0x2166 (2166) 0x2166: 00000000 0x2167: 00000000 00055554: 0000: 00012166 00000000 00000000 t0 write 0x2169 (2169) 0x2169: 00000000 00055560: 0000: 00002169 00000000 t0 write 0x2168 (2168) 0x2168: 00000000 00055568: 0000: 00002168 00000000 t0 write 0x216b (216b) 0x216b: 00000000 0x216c: 00000000 00055570: 0000: 0001216b 00000000 00000000 t0 write VPC_SO_FLUSH_WADDR_3 (216e) VPC_SO_FLUSH_WADDR_3: 0 0005557c: 0000: 0000216e 00000000 t0 write 0x216d (216d) 0x216d: 00000000 00055584: 0000: 0000216d 00000000 t0 write UNKNOWN_2156 (2156) UNKNOWN_2156: 0 0005558c: 0000: 00002156 00000000 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 18 | GROUP_ID = 1 } { ADDR_LO = 0x9d1a0 } 00055594: 0000: c0014300 01000012 0009d1a0 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 15 | GROUP_ID = 0 } { ADDR_LO = 0x9d1f0 } 000555a0: 0000: c0014300 0000000f 0009d1f0 group_id: 0 count: 15 addr: 000000000009d1f0 flags: 0 0009d1f0: 0000: 00002073 00000000 00002101 00000000 00002106 00000000 000021e5 00000000 0009d210: 0020: 0001210b 00000000 00000000 00002381 00000000 000023a0 00000000 t0 write GRAS_ALPHA_CONTROL (2073) GRAS_ALPHA_CONTROL: { 0 } 0009d1f0: 0000: 00002073 00000000 t0 write RB_DEPTH_CONTROL (2101) RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } 0009d1f8: 0000: 00002101 00000000 t0 write RB_STENCIL_CONTROL (2106) RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } 0009d200: 0000: 00002106 00000000 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 0009d208: 0000: 000021e5 00000000 t0 write RB_STENCILREFMASK (210b) RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 0009d210: 0000: 0001210b 00000000 00000000 t0 write TPL1_TP_TEX_COUNT (2381) TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } 0009d21c: 0000: 00002381 00000000 t0 write TPL1_TP_FS_TEX_COUNT (23a0) TPL1_TP_FS_TEX_COUNT: 0 0009d224: 0000: 000023a0 00000000 group_id: 1 count: 18 addr: 000000000009d1a0 flags: 0 0009d1a0: 0000: 00002200 082a0008 00002201 fcfc0081 00002203 0000fc00 0007220a 0008080f 0009d1c0: 0020: 0009d020 00000060 00000001 0000080f 0009d050 00000030 00000001 0001228a 0009d1e0: 0040: 7000411f 3000011f t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } 0009d1a0: 0000: 00002200 082a0008 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } 0009d1a8: 0000: 00002201 fcfc0081 t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } 0009d1b0: 0000: 00002203 0000fc00 t0 write VFD_FETCH[0].INSTR_0 (220a) VFD_FETCH[0].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 | SWITCHNEXT } VFD_FETCH[0].INSTR_1: 0x9d020 VFD_FETCH[0].INSTR_2: { SIZE = 0x60 } VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 } VFD_FETCH[0x1].INSTR_1: 0x9d050 VFD_FETCH[0x1].INSTR_2: { SIZE = 0x30 } VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } 0009d1b8: 0000: 0007220a 0008080f 0009d020 00000060 00000001 0000080f 0009d050 00000030 0009d1d8: 0020: 00000001 t0 write VFD_DECODE[0].INSTR (228a) VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID | SWITCHNEXT } VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID } 0009d1dc: 0000: 0001228a 7000411f 3000011f group_id: 2 count: 43 addr: 000000000009d0f0 flags: 0 0009d0f0: 0000: 000020a1 00000000 000022f1 0001a100 000022f0 fc00fc01 00002100 00000001 0009d110: 0020: 000021e5 00000000 000020f9 ffff0501 0000214a 00000000 00002140 42001004 0009d130: 0040: 001922c6 0010fc04 00001e00 00000000 00000000 00000000 00000000 00000000 * 0009d170: 0080: 00000000 00000000 00fcfc00 00000008 00000000 00000000 00000000 00000000 * t0 write RB_RENDER_CONTROL (20a1) RB_RENDER_CONTROL: { 0 } 0009d0f0: 0000: 000020a1 00000000 t0 write SP_FS_MRT[0].REG (22f1) SP_FS_MRT[0].REG: { REGID = r0.x | HALF_PRECISION | MRTFORMAT = RB4_R8G8B8A8_UNORM } 0009d0f8: 0000: 000022f1 0001a100 t0 write SP_FS_OUTPUT_REG (22f0) SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 0009d100: 0000: 000022f0 fc00fc01 t0 write RB_FS_OUTPUT_REG (2100) RB_FS_OUTPUT_REG: { MRT = 1 } 0009d108: 0000: 00002100 00000001 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 0009d110: 0000: 000021e5 00000000 t0 write RB_FS_OUTPUT (20f9) RB_FS_OUTPUT: { ENABLE_BLEND = 0x1 | INDEPENDENT_BLEND | SAMPLE_MASK = 0xffff | 0x400 } 0009d118: 0000: 000020f9 ffff0501 t0 write VPC_VARYING_PS_REPL[0].MODE (214a) VPC_VARYING_PS_REPL[0].MODE: 0 0009d120: 0000: 0000214a 00000000 t0 write VPC_ATTR (2140) VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 } 0009d128: 0000: 00002140 42001004 t0 write SP_VS_PARAM_REG (22c6) SP_VS_PARAM_REG: { POSREGID = r1.x | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } SP_VS_OUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } UNKNOWN_22D7: 0xfcfc00 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 0009d130: 0000: 001922c6 0010fc04 00001e00 00000000 00000000 00000000 00000000 00000000 * 0009d170: 0040: 00000000 00000000 00fcfc00 00000008 00000000 00000000 00000000 00000000 * group_id: 3 count: 28 addr: 000000000009d080 flags: 0 0009d080: 0000: 000021c4 02000001 00002141 00040400 00002001 00000000 000022c4 00200800 0009d0a0: 0020: 000022c5 08000002 0000230c 00000000 00002318 00000000 00002319 00000000 0009d0c0: 0040: 00002340 00000000 00002202 fcfcfcfc 00002204 0000fcfc 00002154 00000000 0009d0e0: 0060: 000021e7 00000000 000021c5 00000012 t0 write PC_PRIM_VTX_CNTL (21c4) PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } 0009d080: 0000: 000021c4 02000001 t0 write VPC_PACK (2141) VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } 0009d088: 0000: 00002141 00040400 t0 write UNKNOWN_2001 (2001) UNKNOWN_2001: 0 0009d090: 0000: 00002001 00000000 t0 write SP_VS_CTRL_REG0 (22c4) SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 2 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 0009d098: 0000: 000022c4 00200800 t0 write SP_VS_CTRL_REG1 (22c5) SP_VS_CTRL_REG1: { CONSTLENGTH = 2 | INITIALOUTSTANDING = 8 } 0009d0a0: 0000: 000022c5 08000002 t0 write 0x230c (230c) 0x230c: 00000000 0009d0a8: 0000: 0000230c 00000000 t0 write 0x2318 (2318) 0x2318: 00000000 0009d0b0: 0000: 00002318 00000000 t0 write 0x2319 (2319) 0x2319: 00000000 0009d0b8: 0000: 00002319 00000000 t0 write 0x2340 (2340) 0x2340: 00000000 0009d0c0: 0000: 00002340 00000000 t0 write VFD_CONTROL_2 (2202) VFD_CONTROL_2: 0xfcfcfcfc 0009d0c8: 0000: 00002202 fcfcfcfc t0 write VFD_CONTROL_4 (2204) VFD_CONTROL_4: 0xfcfc 0009d0d0: 0000: 00002204 0000fcfc t0 write UNKNOWN_2154 (2154) UNKNOWN_2154: 0 0009d0d8: 0000: 00002154 00000000 t0 write PC_HS_PARAM (21e7) PC_HS_PARAM: { VERTICES_OUT = 0 | SPACING = EQUAL_SPACING } 0009d0e0: 0000: 000021e7 00000000 t0 write PC_PRIM_VTX_CNTL2 (21c5) PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 0009d0e8: 0000: 000021c5 00000012 t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = USE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x200000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 3 } draw[91] register values + 00000000 0xcc4: 00000000 + 00000004 UNKNOWN_0CC5: 0x4 + 80200000 0xd03: 80200000 !+ 00000001 HLSQ_MODE_CONTROL: 0x1 + 00000000 UNKNOWN_0E42: 0 + 00000100 VPC_DEBUG_ECO_CONTROL: 0x100 + 00040000 UNKNOWN_0EC2: 0x40000 !+ 0000001e SP_MODE_CONTROL: 0x1e !+ 00000028 TPL1_TP_MODE_CONTROL: 0x28 !+ 00080000 GRAS_CL_CLIP_CNTL: { 0x80000 } + 00000000 UNKNOWN_2001: 0 + 00000000 0x2002: 00000000 + 00000001 GRAS_CNTL: { IJ_PERSP } + 0007fdff GRAS_CL_GB_CLIP_ADJ: { HORZ = 511 | VERT = 511 } + 41900000 GRAS_CL_VPORT_XOFFSET_0: 18.000000 + 41800000 GRAS_CL_VPORT_XSCALE_0: 16.000000 + 41e80000 GRAS_CL_VPORT_YOFFSET_0: 29.000000 + 41800000 GRAS_CL_VPORT_YSCALE_0: 16.000000 + 3f000000 GRAS_CL_VPORT_ZOFFSET_0: 0.500000 + 3f000000 GRAS_CL_VPORT_ZSCALE_0: 0.500000 + ffc00010 GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 4092.000000 } + 00000008 GRAS_SU_POINT_SIZE: 0.500000 + 00000000 0x2072: 00000000 !+ 00000000 GRAS_ALPHA_CONTROL: { 0 } + 00000000 GRAS_SU_POLY_OFFSET_SCALE: 0.000000 + 00000000 GRAS_SU_POLY_OFFSET_OFFSET: 0.000000 + 00000000 GRAS_SU_POLY_OFFSET_CLAMP: 0.000000 + 00000000 GRAS_DEPTH_CONTROL: { FORMAT = DEPTH4_NONE } !+ 00102014 GRAS_SU_MODE_CONTROL: { FRONT_CW | LINEHALFWIDTH = 0.500000 | MSAA_ENABLE | RENDERING_PASS } !+ 00000200 GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 4 | RASTER_MODE = 0 } !+ 000d0002 GRAS_SC_SCREEN_SCISSOR_TL: { X = 2 | Y = 13 } !+ 002c0021 GRAS_SC_SCREEN_SCISSOR_BR: { X = 33 | Y = 44 } !+ 00000000 RB_RENDER_CONTROL: { 0 } !+ 00008000 RB_MSAA_CONTROL: { SAMPLES = 4 } !+ 00001200 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 4 | IJ_PERSP_PIXEL } !+ 07000c00 RB_MRT[0].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0x7 } !+ 0010029a RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB4_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_ALWAYS | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 1024 } !+ 00000000 RB_MRT[0].BASE: 0 !+ 00000200 RB_MRT[0].CONTROL3: { STRIDE = 64 } + 00000000 RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } + 00000e00 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } !+ ffff0501 RB_FS_OUTPUT: { ENABLE_BLEND = 0x1 | INDEPENDENT_BLEND | SAMPLE_MASK = 0xffff | 0x400 } + 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } + 00000001 RB_FS_OUTPUT_REG: { MRT = 1 } + 00000000 RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } + 00000000 RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTH4_NONE | DEPTH_BASE = 0 } + 00000000 RB_DEPTH_PITCH: 0 + 00000000 RB_DEPTH_PITCH2: 0 + 00000000 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } + 00000000 RB_STENCIL_INFO: { STENCIL_BASE = 0 } + 00000000 RB_STENCIL_PITCH: 0 + 00000000 0x210a: 00000000 + 00000000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } + 00000000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } !+ 42001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 } + 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } !+ 00000000 VPC_VARYING_INTERP[0].MODE: 0 !+ 00000000 VPC_VARYING_PS_REPL[0].MODE: 0 + 00000000 UNKNOWN_2152: 0 + 00000000 UNKNOWN_2153: 0 + 00000000 UNKNOWN_2154: 0 + 00000000 UNKNOWN_2155: 0 + 00000000 UNKNOWN_2156: 0 + 00000000 0x215c: 00000000 + 00000000 0x215d: 00000000 + 00000000 0x215e: 00000000 + 00000000 0x215f: 00000000 + 00000000 0x2161: 00000000 + 00000000 0x2162: 00000000 + 00000000 0x2163: 00000000 + 00000000 0x2164: 00000000 + 00000000 0x2166: 00000000 + 00000000 0x2167: 00000000 + 00000000 0x2168: 00000000 + 00000000 0x2169: 00000000 + 00000000 0x216b: 00000000 + 00000000 0x216c: 00000000 + 00000000 0x216d: 00000000 + 00000000 VPC_SO_FLUSH_WADDR_3: 0 !+ 0000001f UNKNOWN_21C3: 0x1f !+ 02000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + ffffffff PC_RESTART_INDEX: 0xffffffff + 00000000 PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } + 00000001 UNKNOWN_21E6: 0x1 + 00000000 PC_HS_PARAM: { VERTICES_OUT = 0 | SPACING = EQUAL_SPACING } !+ 082a0008 VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } !+ fcfc0081 VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } + fcfcfcfc VFD_CONTROL_2: 0xfcfcfcfc !+ 0000fc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } + 0000fcfc VFD_CONTROL_4: 0xfcfc + 00000000 VFD_INDEX_OFFSET: 0 + 00000000 UNKNOWN_2209: 0 + 0008080f VFD_FETCH[0].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 | SWITCHNEXT } !+ 0009d020 VFD_FETCH[0].INSTR_1: 0x9d020 + 00000060 VFD_FETCH[0].INSTR_2: { SIZE = 0x60 } + 00000001 VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } + 0000080f VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 } !+ 0009d050 VFD_FETCH[0x1].INSTR_1: 0x9d050 + 00000030 VFD_FETCH[0x1].INSTR_2: { SIZE = 0x30 } + 00000001 VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } + 7000411f VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID | SWITCHNEXT } + 3000011f VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID } + 00060010 SP_SP_CTRL_REG: { 0x60010 } + 000005c3 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } !+ 00200800 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 2 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } !+ 08000002 SP_VS_CTRL_REG1: { CONSTLENGTH = 2 | INITIALOUTSTANDING = 8 } !+ 0010fc04 SP_VS_PARAM_REG: { POSREGID = r1.x | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } !+ 00001e00 SP_VS_OUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00fcfc00 UNKNOWN_22D7: 0xfcfc00 + 00000008 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } !+ 00049000 SP_VS_OBJ_START: 0x49000 00049000: 0000: 00000000 13000000 00000000 00000000 00000000 00000000 00000000 00000000 * :0:0000:0000[13000000x_00000000x] (sy)end :0:0001:0001[00000000x_00000000x] nop :0:0002:0002[00000000x_00000000x] nop :0:0003:0003[00000000x_00000000x] nop :0:0004:0004[00000000x_00000000x] nop Stats: - shaderdb: 5 instr, 4 nops, 1 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 0 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 0 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) !+ 00000001 SP_VS_LENGTH_REG: 1 !+ 00340412 SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE } !+ 80100002 SP_FS_CTRL_REG1: { CONSTLENGTH = 2 | VARYING | 0x80000000 } !+ 7e020000 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } !+ 00046000 SP_FS_OBJ_START: 0x46000 00046000: 0000: 00002000 5730cb00 00000000 03000000 00000000 00000000 00000000 00000000 * :2:0000:0000[5730cb00x_00002000x] (sy)(rpt3)bary.f (ei)hr0.x, (r)0, r0.x :0:0001:0004[03000000x_00000000x] end :0:0002:0005[00000000x_00000000x] nop :0:0003:0006[00000000x_00000000x] nop :0:0004:0007[00000000x_00000000x] nop :0:0005:0008[00000000x_00000000x] nop Stats: - shaderdb: 9 instr, 4 nops, 5 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 1 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 4 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) + 00000001 SP_FS_LENGTH_REG: 1 !+ fc00fc01 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r63.x } !+ 0001a100 SP_FS_MRT[0].REG: { REGID = r0.x | HALF_PRECISION | MRTFORMAT = RB4_R8G8B8A8_UNORM } + 00000000 0x230c: 00000000 + 7e020000 SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } + 00000000 SP_HS_OBJ_START: 0 + 00000000 0x2318: 00000000 + 00000000 0x2319: 00000000 + 7e020000 SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } + 00000000 SP_DS_OBJ_START: 0 + 00000000 0x2340: 00000000 + 7e020000 SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } + 00000000 SP_GS_OBJ_START: 0 + 00000808 TPL1_TP_TEX_OFFSET: 0x808 + 00000000 TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } !+ 00000002 0x2382: 00000002 !+ 00000000 TPL1_TP_FS_TEX_COUNT: 0 !+ 080604f0 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0x600a0 } !+ fcfc1108 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x1008 } !+ fff3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } + fcfcfc00 HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } !+ 00fcfc00 HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r0.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } !+ 01010002 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 2 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 1 } !+ 017f0202 HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 2 | CONSTOBJECTOFFSET = 2 | ENABLED | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 } !+ 007e0200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } !+ 007e0200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } !+ 007e0200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } !+ 00000003 HLSQ_UPDATE_CONTROL: 0x3 000555ac: 0000: c0023800 00200984 00000001 00000003 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 18 | GROUP_ID = 1 } { ADDR_LO = 0x9d360 } 000555bc: 0000: c0014300 01000012 0009d360 group_id: 1 count: 18 addr: 000000000009d360 flags: 0 0009d360: 0000: 00002200 082a0008 00002201 fcfc0081 00002203 0000fc00 0007220a 0008080f 0009d380: 0020: 0009d300 00000060 00000001 0000080f 0009d330 00000030 00000001 0001228a 0009d3a0: 0040: 7000411f 3000011f t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } 0009d360: 0000: 00002200 082a0008 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } 0009d368: 0000: 00002201 fcfc0081 t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } 0009d370: 0000: 00002203 0000fc00 t0 write VFD_FETCH[0].INSTR_0 (220a) VFD_FETCH[0].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 | SWITCHNEXT } VFD_FETCH[0].INSTR_1: 0x9d300 VFD_FETCH[0].INSTR_2: { SIZE = 0x60 } VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 } VFD_FETCH[0x1].INSTR_1: 0x9d330 VFD_FETCH[0x1].INSTR_2: { SIZE = 0x30 } VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } 0009d378: 0000: 0007220a 0008080f 0009d300 00000060 00000001 0000080f 0009d330 00000030 0009d398: 0020: 00000001 t0 write VFD_DECODE[0].INSTR (228a) VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID | SWITCHNEXT } VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID } 0009d39c: 0000: 0001228a 7000411f 3000011f t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = USE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x200000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 3 } draw[92] register values + 082a0008 VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } + fcfc0081 VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } + 0000fc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } + 0008080f VFD_FETCH[0].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 | SWITCHNEXT } !+ 0009d300 VFD_FETCH[0].INSTR_1: 0x9d300 + 00000060 VFD_FETCH[0].INSTR_2: { SIZE = 0x60 } + 00000001 VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } + 0000080f VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 } !+ 0009d330 VFD_FETCH[0x1].INSTR_1: 0x9d330 + 00000030 VFD_FETCH[0x1].INSTR_2: { SIZE = 0x30 } + 00000001 VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } + 7000411f VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID | SWITCHNEXT } + 3000011f VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID } 000555c8: 0000: c0023800 00200984 00000001 00000003 0016b094: 0000: c0013f00 00055328 000000ac t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 0016b0a0: 0000: c0014300 00040000 00000000 t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:001706a0 ibsize:000000f7 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 001706a0: 0000: c0002600 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x4 001706a8: 0000: 00000ec3 00000004 t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x68 001706b0: 0000: 00000f03 00000068 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 001706b8: 0000: c0002600 00000000 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } 001706c0: 0000: 000023c0 080004f0 t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = 0x1d } event (null) 001706c8: 0000: c0004600 0000001d t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = FACENESS_FLUSH } event FACENESS_FLUSH 001706d0: 0000: c0004600 0000001c t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 001706d8: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0 001706e0: 0000: 00000cc6 00000000 t0 write UNKNOWN_0E42 (0e42) UNKNOWN_0E42: 0 001706e8: 0000: 00000e42 00000000 t0 write HLSQ_MODE_CONTROL (0e05) HLSQ_MODE_CONTROL: 0x2 001706f0: 0000: 00000e05 00000002 t0 write UNKNOWN_0CC5 (0cc5) UNKNOWN_0CC5: 0x4 001706f8: 0000: 00000cc5 00000004 t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x7 00170700: 0000: 000023db 00000007 t0 write VFD_CONTROL_2 (2202) VFD_CONTROL_2: 0xfcfcfcfc 00170708: 0000: 00002202 fcfcfcfc t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } 00170710: 0000: 00002203 fcfcfc00 t0 write VFD_CONTROL_4 (2204) VFD_CONTROL_4: 0xfcfc 00170718: 0000: 00002204 0000fcfc t0 write VFD_INDEX_OFFSET (2208) VFD_INDEX_OFFSET: 0 00170720: 0000: 00002208 00000000 t0 write UNKNOWN_2209 (2209) UNKNOWN_2209: 0 00170728: 0000: 00002209 00000000 t0 write UNKNOWN_2152 (2152) UNKNOWN_2152: 0 UNKNOWN_2153: 0 00170730: 0000: 00012152 00000000 00000000 t0 write UNKNOWN_2156 (2156) UNKNOWN_2156: 0 0017073c: 0000: 00002156 00000000 t0 write UNKNOWN_2154 (2154) UNKNOWN_2154: 0 00170744: 0000: 00002154 00000000 t0 write UNKNOWN_2155 (2155) UNKNOWN_2155: 0 0017074c: 0000: 00002155 00000000 t0 write UNKNOWN_21C3 (21c3) UNKNOWN_21C3: 0x1d 00170754: 0000: 000021c3 0000001d t0 write PC_PRIM_VTX_CNTL2 (21c5) PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 0017075c: 0000: 000021c5 00000012 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 00170764: 0000: 000021e5 00000000 t0 write GRAS_SU_MODE_CONTROL (2078) GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } 0017076c: 0000: 00002078 00000000 t0 write UNKNOWN_2001 (2001) UNKNOWN_2001: 0 00170774: 0000: 00002001 00000000 t0 write GRAS_CNTL (2003) GRAS_CNTL: { IJ_PERSP } 0017077c: 0000: 00002003 00000001 t0 write GRAS_CL_CLIP_CNTL (2000) GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } 00170784: 0000: 00002000 00188000 t0 write TPL1_TP_TEX_COUNT (2381) TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } 0017078c: 0000: 00002381 00000000 t0 write TPL1_TP_FS_TEX_COUNT (23a0) TPL1_TP_FS_TEX_COUNT: 0x3 00170794: 0000: 000023a0 00000003 t0 write RB_ALPHA_CONTROL (20f8) RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } 0017079c: 0000: 000020f8 00000e00 t0 write RB_RENDER_COMPONENTS (20fb) RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } 001707a4: 0000: 000020fb 0000000f t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 001707ac: 0000: c0014300 00040000 00000000 t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } 001707b8: 0000: 00002200 000a0000 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } 001707c0: 0000: 00002201 fc030000 t0 write SP_INSTR_CACHE_CTRL (22c1) SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } 001707c8: 0000: 000022c1 000005c3 t0 write HLSQ_CONTROL_1_REG (23c1) HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } 001707d0: 0000: 000023c1 fcfc0120 t0 write HLSQ_CONTROL_2_REG (23c2) HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 001707d8: 0000: 000023c2 27f3f3f0 t0 write HLSQ_VS_CONTROL_REG (23c5) HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } 001707e0: 0000: 000023c5 02010042 t0 write HLSQ_FS_CONTROL_REG (23c6) HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 001707e8: 0000: 000023c6 0041423e t0 write HLSQ_HS_CONTROL_REG (23c7) HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 001707f0: 0000: 000023c7 00404200 t0 write HLSQ_DS_CONTROL_REG (23c8) HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 001707f8: 0000: 000023c8 00404200 t0 write HLSQ_GS_CONTROL_REG (23c9) HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00170800: 0000: 000023c9 00404200 t0 write HLSQ_CS_CONTROL_REG (23ca) HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } 00170808: 0000: 000023ca 00004200 t0 write SP_SP_CTRL_REG (22c0) SP_SP_CTRL_REG: { 0x60010 } 00170810: 0000: 000022c0 00060010 t0 write UNKNOWN_21E6 (21e6) UNKNOWN_21E6: 0x1 00170818: 0000: 000021e6 00000001 t0 write SP_VS_CTRL_REG0 (22c4) SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 00170820: 0000: 000022c4 00200c10 t0 write SP_VS_CTRL_REG1 (22c5) SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } 00170828: 0000: 000022c5 01000042 t0 write VPC_ATTR (2140) VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | 0x40000000 } 00170830: 0000: 00002140 40001004 t0 write VPC_PACK (2141) VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } 00170838: 0000: 00002141 00040400 t0 write PC_PRIM_VTX_CNTL (21c4) PC_PRIM_VTX_CNTL: { VAROUT = 1 } 00170840: 0000: 000021c4 00000001 t0 write SP_VS_PARAM_REG (22c6) SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } UNKNOWN_22D7: 0xfcfc00 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 00170848: 0000: 001922c6 0010fc03 00001e03 00000000 00000000 00000000 00000000 00000000 * 00170888: 0040: 00000000 00000000 00fcfc00 00000008 00000000 00000000 00000000 00000000 * t0 write SP_VS_OBJ_OFFSET_REG (22e0) SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 001708b4: 0000: 000022e0 00000000 t0 write SP_VS_OBJ_START (22e1) SP_VS_OBJ_START: 0x1 001708bc: 0000: 000022e1 00000001 t0 write SP_VS_LENGTH_REG (22e5) SP_VS_LENGTH_REG: 2 001708c4: 0000: 000022e5 00000002 t3 opcode: CP_LOAD_STATE4 (30) (67 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } :2:0000:0000[56d81803x_20020003x] (sy)(ss)(nop3) shl.b r0.w, r0.w, 2 :1:0001:0004[20150000x_00000003x] cov.s32s16 hr0.x, r0.w :0:0002:0005[00000200x_00000000x] (rpt2)nop :1:0003:0008[201100f4x_00000000x] mova a0.x, hr0.x :0:0004:0009[00000500x_00000000x] (rpt5)nop :1:0005:0015[20154003x_00000c20x] mov.s32s32 r0.w, c :1:0006:0016[20154004x_00000c21x] mov.s32s32 r1.x, c :1:0007:0017[20154005x_00000c22x] mov.s32s32 r1.y, c :1:0008:0018[20156006x_00000c23x] (ul)mov.s32s32 r1.z, c :0:0009:0019[03000000x_00000000x] end :2:0010:0020[46f00007x_20050000x] shr.b r1.w, r0.x, 5 :2:0011:0021[43980008x_201f0000x] (nop2) and.b r2.x, r0.x, 31 :2:0012:0024[43980807x_201f0007x] (nop3) and.b r1.w, r1.w, 31 :2:0013:0028[46100807x_20100007x] (nop1) mul.u24 r1.w, r1.w, 16 :3:0014:0030[62040007x_00071014x] mad.u24 r1.w, c5.x, r2.x, r1.w :0:0015:0031[00000500x_00000000x] (rpt5)nop :6:0016:0037[c2c60f00x_04800006x] stlw.u32 l[r1.w], r0.w, 4 :0:0017:0038[04800000x_00000000x] chmask :0:0018:0039[05000000x_00000000x] chsh Stats: - shaderdb: 40 instr, 24 nops, 16 non-nops, 5 mov, 1 cov - shaderdb: 0 last-baryf, 0 half, 2 full, 5 constlen - shaderdb: 27 cat0, 6 cat1, 5 cat2, 1 cat3, 0 cat4, 0 cat5, 1 cat6, 0 cat7 - shaderdb: 0 sstall, 1 (ss), 1 (sy) 001708cc: 0000: c0413000 00a00000 00000000 20020003 56d81803 00000003 20150000 00000000 001708ec: 0020: 00000200 00000000 201100f4 00000000 00000500 00000c20 20154003 00000c21 0017090c: 0040: 20154004 00000c22 20154005 00000c23 20156006 00000000 03000000 20050000 0017092c: 0060: 46f00007 201f0000 43980008 201f0007 43980807 20100007 46100807 00071014 0017094c: 0080: 62040007 00000000 00000500 04800006 c2c60f00 00000000 04800000 00000000 0017096c: 00a0: 05000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 * t0 write GRAS_SC_CONTROL (207b) GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = 0 | MSAA_DISABLE | RASTER_MODE = 0 } 001709d8: 0000: 0000207b 00000808 t0 write RB_MSAA_CONTROL (20a2) RB_MSAA_CONTROL: { DISABLE | SAMPLES = 0 } 001709e0: 0000: 000020a2 00001000 t0 write RB_RENDER_CONTROL (20a1) RB_RENDER_CONTROL: { DISABLE_COLOR_PIPE | 0x2 } 001709e8: 0000: 000020a1 00000022 t0 write RB_DEPTH_CONTROL (2101) RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } 001709f0: 0000: 00002101 00000000 t0 write GRAS_ALPHA_CONTROL (2073) GRAS_ALPHA_CONTROL: { 0x2 } 001709f8: 0000: 00002073 00000002 t0 write RB_STENCIL_CONTROL (2106) RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } 00170a00: 0000: 00002106 00000000 t0 write RB_COPY_CONTROL (20fc) RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_FOUR | MODE = RB_COPY_DEPTH_STENCIL | FASTCLEAR = 0 | GMEM_BASE = 0 } RB_COPY_DEST_BASE: { BASE = 0x4f000 } RB_COPY_DEST_PITCH: { PITCH = 256 } RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_DISABLE | COMPONENT_ENABLE = 0xf | ENDIAN = ENDIAN_NONE | TILE = TILE4_3 } 00170a08: 0000: 000320fc 00000052 0004f000 00000008 0303c068 t0 write UNKNOWN_20EF (20ef) UNKNOWN_20EF: 0 00170a1c: 0000: 000020ef 00000000 t0 write GRAS_SC_SCREEN_SCISSOR_TL (207c) GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } 00170a24: 0000: 0001207c 00000000 003f003f t0 write RB_FRAME_BUFFER_DIMENSION (0ce0) RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } 00170a30: 0000: 00000ce0 00400040 t0 write 0xce1 (0ce1) 0xce1: 00000000 00170a38: 0000: 00000ce1 00000000 t3 opcode: CP_LOAD_STATE4 (30) (11 dwords) { DST_OFF = 8 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } 00170a4c: 0.000000 0.000000 1.000000 1.000000 64.000000 64.000000 1.000000 1.000000 00170a4c: 0000: 00000000 00000000 3f800000 3f800000 42800000 42800000 3f800000 3f800000 00170a40: 0000: c0093000 00a00008 00000001 00000000 00000000 3f800000 3f800000 42800000 00170a60: 0020: 42800000 3f800000 3f800000 t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x80000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 2 } draw[93] register values + 00000004 UNKNOWN_0CC5: 0x4 + 00000000 UNKNOWN_0CC6: 0 + 00400040 RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } + 00000000 0xce1: 00000000 !+ 00000002 HLSQ_MODE_CONTROL: 0x2 + 00000000 UNKNOWN_0E42: 0 !+ 00000004 SP_MODE_CONTROL: 0x4 !+ 00000068 TPL1_TP_MODE_CONTROL: 0x68 !+ 00188000 GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } + 00000000 UNKNOWN_2001: 0 + 00000001 GRAS_CNTL: { IJ_PERSP } !+ 00000002 GRAS_ALPHA_CONTROL: { 0x2 } !+ 00000000 GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } !+ 00000808 GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = 0 | MSAA_DISABLE | RASTER_MODE = 0 } !+ 00000000 GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } !+ 003f003f GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } !+ 00000022 RB_RENDER_CONTROL: { DISABLE_COLOR_PIPE | 0x2 } !+ 00001000 RB_MSAA_CONTROL: { DISABLE | SAMPLES = 0 } + 00000000 UNKNOWN_20EF: 0 + 00000e00 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } + 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } !+ 00000052 RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_FOUR | MODE = RB_COPY_DEPTH_STENCIL | FASTCLEAR = 0 | GMEM_BASE = 0 } + 0004f000 RB_COPY_DEST_BASE: { BASE = 0x4f000 } + 00000008 RB_COPY_DEST_PITCH: { PITCH = 256 } !+ 0303c068 RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_DISABLE | COMPONENT_ENABLE = 0xf | ENDIAN = ENDIAN_NONE | TILE = TILE4_3 } + 00000000 RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } + 00000000 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } !+ 40001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | 0x40000000 } + 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } + 00000000 UNKNOWN_2152: 0 + 00000000 UNKNOWN_2153: 0 + 00000000 UNKNOWN_2154: 0 + 00000000 UNKNOWN_2155: 0 + 00000000 UNKNOWN_2156: 0 !+ 0000001d UNKNOWN_21C3: 0x1d !+ 00000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 } + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + 00000000 PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } + 00000001 UNKNOWN_21E6: 0x1 !+ 000a0000 VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } !+ fc030000 VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } + fcfcfcfc VFD_CONTROL_2: 0xfcfcfcfc !+ fcfcfc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } + 0000fcfc VFD_CONTROL_4: 0xfcfc + 00000000 VFD_INDEX_OFFSET: 0 + 00000000 UNKNOWN_2209: 0 + 00060010 SP_SP_CTRL_REG: { 0x60010 } + 000005c3 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } !+ 00200c10 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } !+ 01000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } !+ 0010fc03 SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } !+ 00001e03 SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00fcfc00 UNKNOWN_22D7: 0xfcfc00 + 00000008 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } !+ 00000001 SP_VS_OBJ_START: 0x1 !+ 00000002 SP_VS_LENGTH_REG: 2 + 00000000 TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } !+ 00000003 TPL1_TP_FS_TEX_COUNT: 0x3 !+ 080004f0 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } !+ fcfc0120 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } !+ 27f3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } !+ 02010042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } !+ 0041423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } !+ 00404200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } !+ 00404200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } !+ 00404200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00004200 HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } !+ 00000007 HLSQ_UPDATE_CONTROL: 0x7 00170a6c: 0000: c0023800 00080888 00000001 00000002 0016b0ac: 0000: c0013f00 001706a0 000000f7 t3 opcode: (null) (1d) (2 dwords) 0016b0b8: 0000: c0001d00 00000000 ############################################################ vertices: 0 ############################################################ cmdstream: 8 dwords t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:000555d8 ibsize:00000155 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 000555d8: 0000: c0002600 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x4 000555e0: 0000: 00000ec3 00000004 t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x68 000555e8: 0000: 00000f03 00000068 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 000555f0: 0000: c0002600 00000000 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } 000555f8: 0000: 000023c0 080004f0 t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = 0x1d } event (null) 00055600: 0000: c0004600 0000001d t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = FACENESS_FLUSH } event FACENESS_FLUSH 00055608: 0000: c0004600 0000001c t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00055610: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0 00055618: 0000: 00000cc6 00000000 t0 write UNKNOWN_0E42 (0e42) UNKNOWN_0E42: 0 00055620: 0000: 00000e42 00000000 t0 write HLSQ_MODE_CONTROL (0e05) HLSQ_MODE_CONTROL: 0x2 00055628: 0000: 00000e05 00000002 t0 write UNKNOWN_0CC5 (0cc5) UNKNOWN_0CC5: 0x4 00055630: 0000: 00000cc5 00000004 t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x7 00055638: 0000: 000023db 00000007 t0 write VFD_CONTROL_2 (2202) VFD_CONTROL_2: 0xfcfcfcfc 00055640: 0000: 00002202 fcfcfcfc t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } 00055648: 0000: 00002203 fcfcfc00 t0 write VFD_CONTROL_4 (2204) VFD_CONTROL_4: 0xfcfc 00055650: 0000: 00002204 0000fcfc t0 write VFD_INDEX_OFFSET (2208) VFD_INDEX_OFFSET: 0 00055658: 0000: 00002208 00000000 t0 write UNKNOWN_2209 (2209) UNKNOWN_2209: 0 00055660: 0000: 00002209 00000000 t0 write UNKNOWN_2152 (2152) UNKNOWN_2152: 0 UNKNOWN_2153: 0 00055668: 0000: 00012152 00000000 00000000 t0 write UNKNOWN_2156 (2156) UNKNOWN_2156: 0 00055674: 0000: 00002156 00000000 t0 write UNKNOWN_2154 (2154) UNKNOWN_2154: 0 0005567c: 0000: 00002154 00000000 t0 write UNKNOWN_2155 (2155) UNKNOWN_2155: 0 00055684: 0000: 00002155 00000000 t0 write UNKNOWN_21C3 (21c3) UNKNOWN_21C3: 0x1d 0005568c: 0000: 000021c3 0000001d t0 write PC_PRIM_VTX_CNTL2 (21c5) PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 00055694: 0000: 000021c5 00000012 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 0005569c: 0000: 000021e5 00000000 t0 write GRAS_SU_MODE_CONTROL (2078) GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } 000556a4: 0000: 00002078 00000000 t0 write UNKNOWN_2001 (2001) UNKNOWN_2001: 0 000556ac: 0000: 00002001 00000000 t0 write GRAS_CNTL (2003) GRAS_CNTL: { IJ_PERSP } 000556b4: 0000: 00002003 00000001 t0 write GRAS_CL_CLIP_CNTL (2000) GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } 000556bc: 0000: 00002000 00188000 t0 write TPL1_TP_TEX_COUNT (2381) TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } 000556c4: 0000: 00002381 00000000 t0 write TPL1_TP_FS_TEX_COUNT (23a0) TPL1_TP_FS_TEX_COUNT: 0x3 000556cc: 0000: 000023a0 00000003 t0 write RB_ALPHA_CONTROL (20f8) RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } 000556d4: 0000: 000020f8 00000e00 t0 write RB_RENDER_COMPONENTS (20fb) RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } 000556dc: 0000: 000020fb 0000000f t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 000556e4: 0000: c0014300 00040000 00000000 t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } 000556f0: 0000: 00002200 000a0000 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } 000556f8: 0000: 00002201 fc030000 t0 write SP_INSTR_CACHE_CTRL (22c1) SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } 00055700: 0000: 000022c1 000005c3 t0 write HLSQ_CONTROL_1_REG (23c1) HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } 00055708: 0000: 000023c1 fcfc0120 t0 write HLSQ_CONTROL_2_REG (23c2) HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 00055710: 0000: 000023c2 27f3f3f0 t0 write HLSQ_VS_CONTROL_REG (23c5) HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } 00055718: 0000: 000023c5 02010042 t0 write HLSQ_FS_CONTROL_REG (23c6) HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 1 } 00055720: 0000: 000023c6 0141423e t0 write HLSQ_HS_CONTROL_REG (23c7) HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00055728: 0000: 000023c7 00404200 t0 write HLSQ_DS_CONTROL_REG (23c8) HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00055730: 0000: 000023c8 00404200 t0 write HLSQ_GS_CONTROL_REG (23c9) HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00055738: 0000: 000023c9 00404200 t0 write HLSQ_CS_CONTROL_REG (23ca) HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } 00055740: 0000: 000023ca 00004200 t0 write SP_SP_CTRL_REG (22c0) SP_SP_CTRL_REG: { 0x60010 } 00055748: 0000: 000022c0 00060010 t0 write UNKNOWN_21E6 (21e6) UNKNOWN_21E6: 0x1 00055750: 0000: 000021e6 00000001 t0 write SP_VS_CTRL_REG0 (22c4) SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 00055758: 0000: 000022c4 00200c10 t0 write SP_VS_CTRL_REG1 (22c5) SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } 00055760: 0000: 000022c5 01000042 t0 write VPC_ATTR (2140) VPC_ATTR: { TOTALATTR = 8 | THRDASSIGN = 1 | ENABLE | 0x40000000 } 00055768: 0000: 00002140 42001008 t0 write VPC_PACK (2141) VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 8 | NUMNONPOSVSVAR = 6 } 00055770: 0000: 00002141 00060800 t0 write PC_PRIM_VTX_CNTL (21c4) PC_PRIM_VTX_CNTL: { VAROUT = 1 } 00055778: 0000: 000021c4 00000001 t0 write SP_VS_PARAM_REG (22c6) SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 2 } SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r1.w | B_COMPMASK = 0x3 } SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } UNKNOWN_22D7: 0xfcfc00 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 12 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 00055780: 0000: 001922c6 0020fc03 06071e03 00000000 00000000 00000000 00000000 00000000 * 000557c0: 0040: 00000000 00000000 00fcfc00 00000c08 00000000 00000000 00000000 00000000 * t0 write SP_VS_OBJ_OFFSET_REG (22e0) SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 000557ec: 0000: 000022e0 00000000 t0 write SP_VS_OBJ_START (22e1) SP_VS_OBJ_START: 0x1 000557f4: 0000: 000022e1 00000001 t0 write SP_VS_LENGTH_REG (22e5) SP_VS_LENGTH_REG: 2 000557fc: 0000: 000022e5 00000002 t3 opcode: CP_LOAD_STATE4 (30) (67 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } :2:0000:0000[56d81803x_20020003x] (sy)(ss)(nop3) shl.b r0.w, r0.w, 2 :1:0001:0004[20150000x_00000003x] cov.s32s16 hr0.x, r0.w :0:0002:0005[00000200x_00000000x] (rpt2)nop :1:0003:0008[201100f4x_00000000x] mova a0.x, hr0.x :0:0004:0009[00000500x_00000000x] (rpt5)nop :1:0005:0015[20154003x_00000c20x] mov.s32s32 r0.w, c :1:0006:0016[20154004x_00000c21x] mov.s32s32 r1.x, c :1:0007:0017[20154007x_00000c22x] mov.s32s32 r1.w, c :1:0008:0018[20156008x_00000c23x] (ul)mov.s32s32 r2.x, c :1:0009:0019[20554005x_00000000x] mov.s32s32 r1.y, 0 :1:0010:0020[20554006x_3f800000x] mov.s32s32 r1.z, 1065353216 :0:0011:0021[03000000x_00000000x] end :2:0012:0022[46f00009x_20050000x] shr.b r2.y, r0.x, 5 :2:0013:0023[4398000ax_201f0000x] (nop2) and.b r2.z, r0.x, 31 :2:0014:0026[43980809x_201f0009x] (nop3) and.b r2.y, r2.y, 31 :2:0015:0030[46100809x_20180009x] (nop1) mul.u24 r2.y, r2.y, 24 :3:0016:0032[62050009x_00091014x] mad.u24 r2.y, c5.x, r2.z, r2.y :0:0017:0033[00000500x_00000000x] (rpt5)nop :6:0018:0039[c2c61300x_04800006x] stlw.u32 l[r2.y], r0.w, 4 :6:0019:0040[c2c61310x_0280000ex] stlw.u32 l[r2.y+16], r1.w, 2 :0:0020:0041[04800000x_00000000x] chmask :0:0021:0042[05000000x_00000000x] chsh Stats: - shaderdb: 43 instr, 24 nops, 19 non-nops, 7 mov, 1 cov - shaderdb: 0 last-baryf, 0 half, 3 full, 5 constlen - shaderdb: 27 cat0, 8 cat1, 5 cat2, 1 cat3, 0 cat4, 0 cat5, 2 cat6, 0 cat7 - shaderdb: 0 sstall, 1 (ss), 1 (sy) 00055804: 0000: c0413000 00a00000 00000000 20020003 56d81803 00000003 20150000 00000000 00055824: 0020: 00000200 00000000 201100f4 00000000 00000500 00000c20 20154003 00000c21 00055844: 0040: 20154004 00000c22 20154007 00000c23 20156008 00000000 20554005 3f800000 00055864: 0060: 20554006 00000000 03000000 20050000 46f00009 201f0000 4398000a 201f0009 00055884: 0080: 43980809 20180009 46100809 00091014 62050009 00000000 00000500 04800006 000558a4: 00a0: c2c61300 0280000e c2c61310 00000000 04800000 00000000 05000000 00000000 * t0 write HLSQ_CONTROL_3_REG (23c3) HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } 00055910: 0000: 000023c3 fcfcfc00 t0 write HLSQ_CONTROL_4_REG (23c4) HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } 00055918: 0000: 000023c4 00fcfcfc t0 write SP_FS_CTRL_REG0 (22e8) SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 0 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE | PIXLODENABLE } SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 } 00055920: 0000: 000122e8 00700402 8010003e t0 write SP_FS_OBJ_OFFSET_REG (22ea) SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 } 0005592c: 0000: 000022ea 40420000 t0 write SP_FS_OBJ_START (22eb) SP_FS_OBJ_START: 0x1 00055934: 0000: 000022eb 00000001 t0 write SP_FS_LENGTH_REG (22ef) SP_FS_LENGTH_REG: 1 0005593c: 0000: 000022ef 00000001 t0 write SP_FS_OUTPUT_REG (22f0) SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r0.x | SAMPLEMASK_REGID = r0.x } 00055944: 0000: 000022f0 00000001 t0 write VPC_VARYING_INTERP[0].MODE (2142) VPC_VARYING_INTERP[0].MODE: 0xe000 0005594c: 0000: 00002142 0000e000 t0 write RB_FS_OUTPUT_REG (2100) RB_FS_OUTPUT_REG: { MRT = 1 } 00055954: 0000: 00002100 00000001 t3 opcode: CP_LOAD_STATE4 (30) (35 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 1 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } :2:0000:0000[57309902x_00002004x] (sy)(ss)(rpt1)bary.f (ei)r0.z, (r)4, r0.x :0:0001:0002[00000500x_00000000x] (rpt5)nop :5:0002:0008[a0c01f00x_00000005x] sam (f32)(xyzw)r0.x, r0.z, s#0, t#0 :0:0003:0009[03000000x_00000000x] end :0:0004:0010[00000000x_00000000x] nop :0:0005:0011[00000000x_00000000x] nop :0:0006:0012[00000000x_00000000x] nop :0:0007:0013[00000000x_00000000x] nop Stats: - shaderdb: 14 instr, 10 nops, 4 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 0 half, 1 full, 0 constlen - shaderdb: 11 cat0, 0 cat1, 2 cat2, 0 cat3, 0 cat4, 1 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 1 (ss), 1 (sy) 0005595c: 0000: c0213000 00700000 00000000 00002004 57309902 00000000 00000500 00000005 0005597c: 0020: a0c01f00 00000000 03000000 00000000 00000000 00000000 00000000 00000000 * t0 write RB_FS_OUTPUT (20f9) RB_FS_OUTPUT: { ENABLE_BLEND = 0 | SAMPLE_MASK = 0xffff } 000559e8: 0000: 000020f9 ffff0000 t0 write RB_MRT[0].CONTROL (20a4) RB_MRT[0].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0xf } 000559f0: 0000: 000020a4 0f000000 t0 write RB_MRT[0x1].CONTROL (20a9) RB_MRT[0x1].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0xf } 000559f8: 0000: 000020a9 0f000000 t0 write RB_MRT[0].BLEND_CONTROL (20a8) RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } 00055a00: 0000: 000020a8 00000000 t3 opcode: CP_LOAD_STATE4 (30) (5 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_TEX | NUM_UNIT = 1 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } { XY_MAG = A4XX_TEX_NEAREST | XY_MIN = A4XX_TEX_NEAREST | WRAP_S = A4XX_TEX_CLAMP_TO_EDGE | WRAP_T = A4XX_TEX_CLAMP_TO_EDGE | WRAP_R = A4XX_TEX_CLAMP_TO_EDGE | ANISO = A4XX_TEX_ANISO_1 | LOD_BIAS = 0.000000 | 0x60000 } { COMPARE_FUNC = FUNC_LEQUAL | UNNORM_COORDS | MIPFILTER_LINEAR_FAR | MAX_LOD = 0.000000 | MIN_LOD = 0.000000 | 0x1 } 00055a14: 0000: 00060920 00000067 00055a08: 0000: c0033000 00500000 00000000 00060920 00000067 t0 write GRAS_SC_CONTROL (207b) GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 0 | RASTER_MODE = 0 } 00055a1c: 0000: 0000207b 00000000 t0 write RB_MSAA_CONTROL (20a2) RB_MSAA_CONTROL: { SAMPLES = 0 } 00055a24: 0000: 000020a2 00000000 t0 write RB_RENDER_CONTROL (20a1) RB_RENDER_CONTROL: { 0 } 00055a2c: 0000: 000020a1 00000000 t0 write 0x2382 (2382) 0x2382: 00000000 00055a34: 0000: 00002382 00000000 t0 write RB_DEPTH_CONTROL (2101) RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } 00055a3c: 0000: 00002101 00000000 t0 write GRAS_ALPHA_CONTROL (2073) GRAS_ALPHA_CONTROL: { 0 } 00055a44: 0000: 00002073 00000000 t0 write RB_STENCIL_CONTROL (2106) RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } 00055a4c: 0000: 00002106 00000000 t0 write SP_FS_MRT[0].REG (22f1) SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = RB4_R8G8B8A8_UNORM } 00055a54: 0000: 000022f1 0001a000 t0 write RB_MRT[0].BUF_INFO (20a5) RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB4_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE4_3 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 256 } RB_MRT[0].BASE: 0x166000 RB_MRT[0].CONTROL3: { STRIDE = 0 } 00055a5c: 0000: 000220a5 000400da 00166000 00000000 t3 opcode: CP_LOAD_STATE4 (30) (11 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_TEX | NUM_UNIT = 1 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } { TILED | SWIZ_X = A4XX_TEX_X | SWIZ_Y = A4XX_TEX_Y | SWIZ_Z = A4XX_TEX_Z | SWIZ_W = A4XX_TEX_W | MIPLVLS = 0 | FMT = TFMT4_8_8_8_8_UNORM | TYPE = A4XX_TEX_2D | 0x2 } { HEIGHT = 64 | WIDTH = 64 } { PITCHALIGN = 0 | PITCH = 256 | SWAP = WZYX } { LAYERSZ = 0 | DEPTH = 1 | 0x20000 } { LAYERSZ = 4096 | BASE = 0x4f000 } { 5 = 0 } { 6 = 0 } { 7 = 0 } 00055a78: 0000: 27006883 00200040 00020000 00060000 0004f001 00000000 00000000 00000000 00055a6c: 0000: c0093000 00500000 00000001 27006883 00200040 00020000 00060000 0004f001 * t0 write VPC_VARYING_PS_REPL[0].MODE (214a) VPC_VARYING_PS_REPL[0].MODE: 0x99999999 00055a98: 0000: 0000214a 99999999 t0 write GRAS_SC_SCREEN_SCISSOR_TL (207c) GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } 00055aa0: 0000: 0001207c 00000000 003f003f t0 write GRAS_SC_WINDOW_SCISSOR_BR (209c) GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 00055aac: 0000: 0001209c 003f003f 00000000 t0 write RB_FRAME_BUFFER_DIMENSION (0ce0) RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } 00055ab8: 0000: 00000ce0 00400040 t0 write 0xce1 (0ce1) 0xce1: 00000000 00055ac0: 0000: 00000ce1 00000000 t0 write RB_RENDER_CONTROL2 (20a3) RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 | IJ_PERSP_PIXEL } 00055ac8: 0000: 000020a3 00001000 t0 write RB_MODE_CONTROL (20a0) RB_MODE_CONTROL: { WIDTH = 0 | HEIGHT = 0 | 0xc00000 } 00055ad0: 0000: 000020a0 00c00000 t3 opcode: CP_LOAD_STATE4 (30) (11 dwords) { DST_OFF = 8 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } 00055ae4: 0.000000 0.000000 0.000000 0.000000 64.000000 64.000000 64.000000 64.000000 00055ae4: 0000: 00000000 00000000 00000000 00000000 42800000 42800000 42800000 42800000 00055ad8: 0000: c0093000 00a00008 00000001 00000000 00000000 00000000 00000000 42800000 00055af8: 0020: 42800000 42800000 42800000 t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x80000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 2 } draw[94] register values + 00000004 UNKNOWN_0CC5: 0x4 + 00000000 UNKNOWN_0CC6: 0 + 00400040 RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } + 00000000 0xce1: 00000000 + 00000002 HLSQ_MODE_CONTROL: 0x2 + 00000000 UNKNOWN_0E42: 0 + 00000004 SP_MODE_CONTROL: 0x4 + 00000068 TPL1_TP_MODE_CONTROL: 0x68 + 00188000 GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } + 00000000 UNKNOWN_2001: 0 + 00000001 GRAS_CNTL: { IJ_PERSP } !+ 00000000 GRAS_ALPHA_CONTROL: { 0 } + 00000000 GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } !+ 00000000 GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 0 | RASTER_MODE = 0 } + 00000000 GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } + 003f003f GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } + 003f003f GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } + 00000000 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } !+ 00c00000 RB_MODE_CONTROL: { WIDTH = 0 | HEIGHT = 0 | 0xc00000 } !+ 00000000 RB_RENDER_CONTROL: { 0 } !+ 00000000 RB_MSAA_CONTROL: { SAMPLES = 0 } !+ 00001000 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 | IJ_PERSP_PIXEL } !+ 0f000000 RB_MRT[0].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0xf } !+ 000400da RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB4_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE4_3 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 256 } !+ 00166000 RB_MRT[0].BASE: 0x166000 !+ 00000000 RB_MRT[0].CONTROL3: { STRIDE = 0 } + 00000000 RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } + 0f000000 RB_MRT[0x1].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0xf } + 00000e00 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } !+ ffff0000 RB_FS_OUTPUT: { ENABLE_BLEND = 0 | SAMPLE_MASK = 0xffff } + 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } + 00000001 RB_FS_OUTPUT_REG: { MRT = 1 } + 00000000 RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } + 00000000 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } !+ 42001008 VPC_ATTR: { TOTALATTR = 8 | THRDASSIGN = 1 | ENABLE | 0x40000000 } !+ 00060800 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 8 | NUMNONPOSVSVAR = 6 } !+ 0000e000 VPC_VARYING_INTERP[0].MODE: 0xe000 !+ 99999999 VPC_VARYING_PS_REPL[0].MODE: 0x99999999 + 00000000 UNKNOWN_2152: 0 + 00000000 UNKNOWN_2153: 0 + 00000000 UNKNOWN_2154: 0 + 00000000 UNKNOWN_2155: 0 + 00000000 UNKNOWN_2156: 0 + 0000001d UNKNOWN_21C3: 0x1d + 00000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 } + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + 00000000 PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } + 00000001 UNKNOWN_21E6: 0x1 + 000a0000 VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } + fc030000 VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } + fcfcfcfc VFD_CONTROL_2: 0xfcfcfcfc + fcfcfc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } + 0000fcfc VFD_CONTROL_4: 0xfcfc + 00000000 VFD_INDEX_OFFSET: 0 + 00000000 UNKNOWN_2209: 0 + 00060010 SP_SP_CTRL_REG: { 0x60010 } + 000005c3 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } + 00200c10 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } + 01000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } !+ 0020fc03 SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 2 } !+ 06071e03 SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r1.w | B_COMPMASK = 0x3 } + 00000000 SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00fcfc00 UNKNOWN_22D7: 0xfcfc00 !+ 00000c08 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 12 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } + 00000001 SP_VS_OBJ_START: 0x1 + 00000002 SP_VS_LENGTH_REG: 2 !+ 00700402 SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 0 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE | PIXLODENABLE } !+ 8010003e SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 } !+ 40420000 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 } !+ 00000001 SP_FS_OBJ_START: 0x1 + 00000001 SP_FS_LENGTH_REG: 1 !+ 00000001 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r0.x | SAMPLEMASK_REGID = r0.x } !+ 0001a000 SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = RB4_R8G8B8A8_UNORM } + 00000000 TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } !+ 00000000 0x2382: 00000000 + 00000003 TPL1_TP_FS_TEX_COUNT: 0x3 + 080004f0 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } + fcfc0120 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } + 27f3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } + fcfcfc00 HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } !+ 00fcfcfc HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } + 02010042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } !+ 0141423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 1 } + 00404200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00004200 HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } + 00000007 HLSQ_UPDATE_CONTROL: 0x7 00055b04: 0000: c0023800 00080888 00000001 00000002 t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = CACHE_FLUSH } event CACHE_FLUSH 00055b14: 0000: c0004600 00000006 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00055b1c: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0x8000012 00055b24: 0000: 00000cc6 08000012 00173000: 0000: c0013f00 000555d8 00000155 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 0017300c: 0000: c0014300 00040000 00000000 t3 opcode: (null) (1d) (2 dwords) 00173018: 0000: c0001d00 00000000 ############################################################ vertices: 0 ############################################################ cmdstream: 48 dwords t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 0016b000: 0000: c0002600 00000000 t0 write UCHE_INVALIDATE0 (0e8a) UCHE_INVALIDATE0: 0 UCHE_INVALIDATE1: 0x12 0016b008: 0000: 00010e8a 00000000 00000012 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 0016b014: 0000: c0002600 00000000 t0 write RB_MODE_CONTROL (20a0) RB_MODE_CONTROL: { WIDTH = 64 | HEIGHT = 64 | ENABLE_GMEM } 0016b01c: 0000: 000020a0 00010202 t0 write RB_FRAME_BUFFER_DIMENSION (0ce0) RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } 0016b024: 0000: 00000ce0 00400040 t0 write 0xce1 (0ce1) 0xce1: 00000001 0016b02c: 0000: 00000ce1 00000001 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 0016b034: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0 0016b03c: 0000: 00000cc6 00000000 t3 opcode: (null) (1d) (2 dwords) 0016b044: 0000: c0001d00 00000000 t0 write GRAS_SC_WINDOW_SCISSOR_BR (209c) GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 0016b04c: 0000: 0001209c 003f003f 00000000 t0 write RB_BIN_OFFSET (210d) RB_BIN_OFFSET: { X = 0 | Y = 0 } 0016b058: 0000: 0000210d 00000000 t0 write GRAS_SC_WINDOW_SCISSOR_BR (209c) GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 0016b060: 0000: 0001209c 003f003f 00000000 t0 write UNKNOWN_2157 (2157) UNKNOWN_2157: 0x1 0016b06c: 0000: 00002157 00000001 t3 opcode: (null) (64) (2 dwords) 0016b074: 0000: c0006400 00000001 t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:00054994 ibsize:000000f6 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00054994: 0000: c0002600 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x4 0005499c: 0000: 00000ec3 00000004 t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x68 000549a4: 0000: 00000f03 00000068 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 000549ac: 0000: c0002600 00000000 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } 000549b4: 0000: 000023c0 080004f0 t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = 0x1d } event (null) 000549bc: 0000: c0004600 0000001d t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = FACENESS_FLUSH } event FACENESS_FLUSH 000549c4: 0000: c0004600 0000001c t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 000549cc: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0 000549d4: 0000: 00000cc6 00000000 t0 write UNKNOWN_0E42 (0e42) UNKNOWN_0E42: 0 000549dc: 0000: 00000e42 00000000 t0 write HLSQ_MODE_CONTROL (0e05) HLSQ_MODE_CONTROL: 0x2 000549e4: 0000: 00000e05 00000002 t0 write UNKNOWN_0CC5 (0cc5) UNKNOWN_0CC5: 0x4 000549ec: 0000: 00000cc5 00000004 t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x7 000549f4: 0000: 000023db 00000007 t0 write VFD_CONTROL_2 (2202) VFD_CONTROL_2: 0xfcfcfcfc 000549fc: 0000: 00002202 fcfcfcfc t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } 00054a04: 0000: 00002203 fcfcfc00 t0 write VFD_CONTROL_4 (2204) VFD_CONTROL_4: 0xfcfc 00054a0c: 0000: 00002204 0000fcfc t0 write VFD_INDEX_OFFSET (2208) VFD_INDEX_OFFSET: 0 00054a14: 0000: 00002208 00000000 t0 write UNKNOWN_2209 (2209) UNKNOWN_2209: 0 00054a1c: 0000: 00002209 00000000 t0 write UNKNOWN_2152 (2152) UNKNOWN_2152: 0 UNKNOWN_2153: 0 00054a24: 0000: 00012152 00000000 00000000 t0 write UNKNOWN_2156 (2156) UNKNOWN_2156: 0 00054a30: 0000: 00002156 00000000 t0 write UNKNOWN_2154 (2154) UNKNOWN_2154: 0 00054a38: 0000: 00002154 00000000 t0 write UNKNOWN_2155 (2155) UNKNOWN_2155: 0 00054a40: 0000: 00002155 00000000 t0 write UNKNOWN_21C3 (21c3) UNKNOWN_21C3: 0x1d 00054a48: 0000: 000021c3 0000001d t0 write PC_PRIM_VTX_CNTL2 (21c5) PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 00054a50: 0000: 000021c5 00000012 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 00054a58: 0000: 000021e5 00000000 t0 write GRAS_SU_MODE_CONTROL (2078) GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } 00054a60: 0000: 00002078 00000000 t0 write UNKNOWN_2001 (2001) UNKNOWN_2001: 0 00054a68: 0000: 00002001 00000000 t0 write GRAS_CNTL (2003) GRAS_CNTL: { IJ_PERSP } 00054a70: 0000: 00002003 00000001 t0 write GRAS_CL_CLIP_CNTL (2000) GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } 00054a78: 0000: 00002000 00188000 t0 write TPL1_TP_TEX_COUNT (2381) TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } 00054a80: 0000: 00002381 00000000 t0 write TPL1_TP_FS_TEX_COUNT (23a0) TPL1_TP_FS_TEX_COUNT: 0x3 00054a88: 0000: 000023a0 00000003 t0 write RB_ALPHA_CONTROL (20f8) RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } 00054a90: 0000: 000020f8 00000e00 t0 write RB_RENDER_COMPONENTS (20fb) RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } 00054a98: 0000: 000020fb 0000000f t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 00054aa0: 0000: c0014300 00040000 00000000 t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } 00054aac: 0000: 00002200 000a0000 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } 00054ab4: 0000: 00002201 fc030000 t0 write SP_INSTR_CACHE_CTRL (22c1) SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } 00054abc: 0000: 000022c1 000005c3 t0 write HLSQ_CONTROL_1_REG (23c1) HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } 00054ac4: 0000: 000023c1 fcfc0120 t0 write HLSQ_CONTROL_2_REG (23c2) HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 00054acc: 0000: 000023c2 27f3f3f0 t0 write HLSQ_VS_CONTROL_REG (23c5) HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } 00054ad4: 0000: 000023c5 02010042 t0 write HLSQ_FS_CONTROL_REG (23c6) HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00054adc: 0000: 000023c6 0041423e t0 write HLSQ_HS_CONTROL_REG (23c7) HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00054ae4: 0000: 000023c7 00404200 t0 write HLSQ_DS_CONTROL_REG (23c8) HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00054aec: 0000: 000023c8 00404200 t0 write HLSQ_GS_CONTROL_REG (23c9) HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00054af4: 0000: 000023c9 00404200 t0 write HLSQ_CS_CONTROL_REG (23ca) HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } 00054afc: 0000: 000023ca 00004200 t0 write SP_SP_CTRL_REG (22c0) SP_SP_CTRL_REG: { 0x60010 } 00054b04: 0000: 000022c0 00060010 t0 write UNKNOWN_21E6 (21e6) UNKNOWN_21E6: 0x1 00054b0c: 0000: 000021e6 00000001 t0 write SP_VS_CTRL_REG0 (22c4) SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 00054b14: 0000: 000022c4 00200c10 t0 write SP_VS_CTRL_REG1 (22c5) SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } 00054b1c: 0000: 000022c5 01000042 t0 write VPC_ATTR (2140) VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | 0x40000000 } 00054b24: 0000: 00002140 40001004 t0 write VPC_PACK (2141) VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } 00054b2c: 0000: 00002141 00040400 t0 write PC_PRIM_VTX_CNTL (21c4) PC_PRIM_VTX_CNTL: { VAROUT = 1 } 00054b34: 0000: 000021c4 00000001 t0 write SP_VS_PARAM_REG (22c6) SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } UNKNOWN_22D7: 0xfcfc00 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 00054b3c: 0000: 001922c6 0010fc03 00001e03 00000000 00000000 00000000 00000000 00000000 * 00054b7c: 0040: 00000000 00000000 00fcfc00 00000008 00000000 00000000 00000000 00000000 * t0 write SP_VS_OBJ_OFFSET_REG (22e0) SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 00054ba8: 0000: 000022e0 00000000 t0 write SP_VS_OBJ_START (22e1) SP_VS_OBJ_START: 0x1 00054bb0: 0000: 000022e1 00000001 t0 write SP_VS_LENGTH_REG (22e5) SP_VS_LENGTH_REG: 2 00054bb8: 0000: 000022e5 00000002 t3 opcode: CP_LOAD_STATE4 (30) (67 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } :2:0000:0000[56d81803x_20020003x] (sy)(ss)(nop3) shl.b r0.w, r0.w, 2 :1:0001:0004[20150000x_00000003x] cov.s32s16 hr0.x, r0.w :0:0002:0005[00000200x_00000000x] (rpt2)nop :1:0003:0008[201100f4x_00000000x] mova a0.x, hr0.x :0:0004:0009[00000500x_00000000x] (rpt5)nop :1:0005:0015[20154003x_00000c20x] mov.s32s32 r0.w, c :1:0006:0016[20154004x_00000c21x] mov.s32s32 r1.x, c :1:0007:0017[20154005x_00000c22x] mov.s32s32 r1.y, c :1:0008:0018[20156006x_00000c23x] (ul)mov.s32s32 r1.z, c :0:0009:0019[03000000x_00000000x] end :2:0010:0020[46f00007x_20050000x] shr.b r1.w, r0.x, 5 :2:0011:0021[43980008x_201f0000x] (nop2) and.b r2.x, r0.x, 31 :2:0012:0024[43980807x_201f0007x] (nop3) and.b r1.w, r1.w, 31 :2:0013:0028[46100807x_20100007x] (nop1) mul.u24 r1.w, r1.w, 16 :3:0014:0030[62040007x_00071014x] mad.u24 r1.w, c5.x, r2.x, r1.w :0:0015:0031[00000500x_00000000x] (rpt5)nop :6:0016:0037[c2c60f00x_04800006x] stlw.u32 l[r1.w], r0.w, 4 :0:0017:0038[04800000x_00000000x] chmask :0:0018:0039[05000000x_00000000x] chsh Stats: - shaderdb: 40 instr, 24 nops, 16 non-nops, 5 mov, 1 cov - shaderdb: 0 last-baryf, 0 half, 2 full, 5 constlen - shaderdb: 27 cat0, 6 cat1, 5 cat2, 1 cat3, 0 cat4, 0 cat5, 1 cat6, 0 cat7 - shaderdb: 0 sstall, 1 (ss), 1 (sy) 00054bc0: 0000: c0413000 00a00000 00000000 20020003 56d81803 00000003 20150000 00000000 00054be0: 0020: 00000200 00000000 201100f4 00000000 00000500 00000c20 20154003 00000c21 00054c00: 0040: 20154004 00000c22 20154005 00000c23 20156006 00000000 03000000 20050000 00054c20: 0060: 46f00007 201f0000 43980008 201f0007 43980807 20100007 46100807 00071014 00054c40: 0080: 62040007 00000000 00000500 04800006 c2c60f00 00000000 04800000 00000000 00054c60: 00a0: 05000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 * t0 write GRAS_ALPHA_CONTROL (2073) GRAS_ALPHA_CONTROL: { 0x2 } 00054ccc: 0000: 00002073 00000002 t0 write GRAS_SC_CONTROL (207b) GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = 4 | MSAA_DISABLE | RASTER_MODE = 0 } 00054cd4: 0000: 0000207b 00000a08 t0 write RB_MSAA_CONTROL (20a2) RB_MSAA_CONTROL: { DISABLE | SAMPLES = 4 } 00054cdc: 0000: 000020a2 00009000 t0 write RB_RENDER_CONTROL (20a1) RB_RENDER_CONTROL: { DISABLE_COLOR_PIPE | 0x2 } 00054ce4: 0000: 000020a1 00000022 t0 write RB_CLEAR_COLOR_DW0 (20cc) RB_CLEAR_COLOR_DW0: 0xff000000 RB_CLEAR_COLOR_DW1: 0 RB_CLEAR_COLOR_DW2: 0 RB_CLEAR_COLOR_DW3: 0 00054cec: 0000: 000320cc ff000000 00000000 00000000 00000000 t0 write RB_COPY_CONTROL (20fc) RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_FOUR | MODE = RB_COPY_CLEAR | FASTCLEAR = 0xf | GMEM_BASE = 0 } RB_COPY_DEST_BASE: { BASE = 0x4f000 } RB_COPY_DEST_PITCH: { PITCH = 256 } RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_IF_ALPHA_OFF | COMPONENT_ENABLE = 0 | ENDIAN = ENDIAN_NONE | TILE = TILE4_3 } 00054d00: 0000: 000320fc 00000f22 0004f000 00000008 03000868 t0 write GRAS_SC_SCREEN_SCISSOR_TL (207c) GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } 00054d14: 0000: 0001207c 00000000 003f003f t0 write RB_FRAME_BUFFER_DIMENSION (0ce0) RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } 00054d20: 0000: 00000ce0 00400040 t0 write 0xce1 (0ce1) 0xce1: 00000000 00054d28: 0000: 00000ce1 00000000 t3 opcode: CP_LOAD_STATE4 (30) (11 dwords) { DST_OFF = 8 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } 00054d3c: 0.000000 0.000000 1.000000 1.000000 64.000000 64.000000 1.000000 1.000000 00054d3c: 0000: 00000000 00000000 3f800000 3f800000 42800000 42800000 3f800000 3f800000 00054d30: 0000: c0093000 00a00008 00000001 00000000 00000000 3f800000 3f800000 42800000 00054d50: 0020: 42800000 3f800000 3f800000 t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x80000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 2 } draw[95] register values + 00000004 UNKNOWN_0CC5: 0x4 + 00000000 UNKNOWN_0CC6: 0 + 00400040 RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } + 00000000 0xce1: 00000000 + 00000002 HLSQ_MODE_CONTROL: 0x2 + 00000000 UNKNOWN_0E42: 0 + 00000000 UCHE_INVALIDATE0: 0 + 00000012 UCHE_INVALIDATE1: 0x12 + 00000004 SP_MODE_CONTROL: 0x4 + 00000068 TPL1_TP_MODE_CONTROL: 0x68 + 00188000 GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } + 00000000 UNKNOWN_2001: 0 + 00000001 GRAS_CNTL: { IJ_PERSP } !+ 00000002 GRAS_ALPHA_CONTROL: { 0x2 } + 00000000 GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } !+ 00000a08 GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = 4 | MSAA_DISABLE | RASTER_MODE = 0 } + 00000000 GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } + 003f003f GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } + 003f003f GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } + 00000000 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } !+ 00010202 RB_MODE_CONTROL: { WIDTH = 64 | HEIGHT = 64 | ENABLE_GMEM } !+ 00000022 RB_RENDER_CONTROL: { DISABLE_COLOR_PIPE | 0x2 } !+ 00009000 RB_MSAA_CONTROL: { DISABLE | SAMPLES = 4 } + ff000000 RB_CLEAR_COLOR_DW0: 0xff000000 + 00000000 RB_CLEAR_COLOR_DW1: 0 + 00000000 RB_CLEAR_COLOR_DW2: 0 + 00000000 RB_CLEAR_COLOR_DW3: 0 + 00000e00 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } + 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } !+ 00000f22 RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_FOUR | MODE = RB_COPY_CLEAR | FASTCLEAR = 0xf | GMEM_BASE = 0 } + 0004f000 RB_COPY_DEST_BASE: { BASE = 0x4f000 } + 00000008 RB_COPY_DEST_PITCH: { PITCH = 256 } !+ 03000868 RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_IF_ALPHA_OFF | COMPONENT_ENABLE = 0 | ENDIAN = ENDIAN_NONE | TILE = TILE4_3 } + 00000000 RB_BIN_OFFSET: { X = 0 | Y = 0 } !+ 40001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | 0x40000000 } !+ 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } + 00000000 UNKNOWN_2152: 0 + 00000000 UNKNOWN_2153: 0 + 00000000 UNKNOWN_2154: 0 + 00000000 UNKNOWN_2155: 0 + 00000000 UNKNOWN_2156: 0 + 00000001 UNKNOWN_2157: 0x1 + 0000001d UNKNOWN_21C3: 0x1d + 00000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 } + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + 00000000 PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } + 00000001 UNKNOWN_21E6: 0x1 + 000a0000 VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } + fc030000 VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } + fcfcfcfc VFD_CONTROL_2: 0xfcfcfcfc + fcfcfc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } + 0000fcfc VFD_CONTROL_4: 0xfcfc + 00000000 VFD_INDEX_OFFSET: 0 + 00000000 UNKNOWN_2209: 0 + 00060010 SP_SP_CTRL_REG: { 0x60010 } + 000005c3 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } + 00200c10 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } + 01000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } !+ 0010fc03 SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } !+ 00001e03 SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00fcfc00 UNKNOWN_22D7: 0xfcfc00 !+ 00000008 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } + 00000001 SP_VS_OBJ_START: 0x1 + 00000002 SP_VS_LENGTH_REG: 2 + 00000000 TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } + 00000003 TPL1_TP_FS_TEX_COUNT: 0x3 + 080004f0 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } + fcfc0120 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } + 27f3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } + 02010042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } !+ 0041423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00004200 HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } + 00000007 HLSQ_UPDATE_CONTROL: 0x7 00054d5c: 0000: c0023800 00080888 00000001 00000002 0016b07c: 0000: c0013f00 00054994 000000f6 t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:00054d6c ibsize:00000037 t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } 00054d6c: 0000: 00002200 082a0008 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00054d74: 0000: c0002600 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x1e 00054d7c: 0000: 00000ec3 0000001e t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x28 00054d84: 0000: 00000f03 00000028 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00054d8c: 0000: c0002600 00000000 t0 write HLSQ_MODE_CONTROL (0e05) HLSQ_MODE_CONTROL: 0x1 00054d94: 0000: 00000e05 00000001 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0x600a0 } 00054d9c: 0000: 000023c0 080604f0 t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x7 00054da4: 0000: 000023db 00000007 t0 write PC_RESTART_INDEX (21c6) PC_RESTART_INDEX: 0xffffffff 00054dac: 0000: 000021c6 ffffffff t0 write UNKNOWN_21E6 (21e6) UNKNOWN_21E6: 0x1 00054db4: 0000: 000021e6 00000001 t0 write UNKNOWN_21C3 (21c3) UNKNOWN_21C3: 0x1f 00054dbc: 0000: 000021c3 0000001f t0 write TPL1_TP_TEX_OFFSET (2380) TPL1_TP_TEX_OFFSET: 0x808 00054dc4: 0000: 00002380 00000808 t0 write GRAS_SU_POINT_MINMAX (2070) GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 4092.000000 } GRAS_SU_POINT_SIZE: 0.500000 00054dcc: 0000: 00012070 ffc00010 00000008 t0 write UNKNOWN_2152 (2152) UNKNOWN_2152: 0 UNKNOWN_2153: 0 00054dd8: 0000: 00012152 00000000 00000000 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00054de4: 0000: c0002600 00000000 t0 write UNKNOWN_0CC5 (0cc5) UNKNOWN_0CC5: 0x4 00054dec: 0000: 00000cc5 00000004 t0 write 0xcc4 (0cc4) 0xcc4: 00000000 00054df4: 0000: 00000cc4 00000000 t0 write 0xd03 (0d03) 0xd03: 80200000 00054dfc: 0000: 00000d03 80200000 t0 write UNKNOWN_0EC2 (0ec2) UNKNOWN_0EC2: 0x40000 00054e04: 0000: 00000ec2 00040000 t0 write VPC_DEBUG_ECO_CONTROL (0e64) VPC_DEBUG_ECO_CONTROL: 0x100 00054e0c: 0000: 00000e64 00000100 t0 write UNKNOWN_0E42 (0e42) UNKNOWN_0E42: 0 00054e14: 0000: 00000e42 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x1e 00054e1c: 0000: 00000ec3 0000001e t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x28 00054e24: 0000: 00000f03 00000028 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 00054e2c: 0000: c0014300 00040000 00000000 t0 write VFD_INDEX_OFFSET (2208) VFD_INDEX_OFFSET: 0 00054e38: 0000: 00002208 00000000 t0 write UNKNOWN_2209 (2209) UNKNOWN_2209: 0 00054e40: 0000: 00002209 00000000 0016b088: 0000: c0013f00 00054d6c 00000037 t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:00055328 ibsize:000000ac t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x3 00055328: 0000: 000023db 00000003 t0 write SP_INSTR_CACHE_CTRL (22c1) SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } 00055330: 0000: 000022c1 000005c3 t0 write HLSQ_CONTROL_1_REG (23c1) HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x1008 } 00055338: 0000: 000023c1 fcfc1108 t0 write HLSQ_CONTROL_2_REG (23c2) HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 00055340: 0000: 000023c2 fff3f3f0 t0 write HLSQ_VS_CONTROL_REG (23c5) HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 2 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 1 } 00055348: 0000: 000023c5 01010002 t0 write HLSQ_HS_CONTROL_REG (23c7) HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 00055350: 0000: 000023c7 007e0200 t0 write HLSQ_DS_CONTROL_REG (23c8) HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 00055358: 0000: 000023c8 007e0200 t0 write HLSQ_GS_CONTROL_REG (23c9) HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 00055360: 0000: 000023c9 007e0200 t0 write HLSQ_FS_CONTROL_REG (23c6) HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 2 | CONSTOBJECTOFFSET = 2 | ENABLED | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 } 00055368: 0000: 000023c6 017f0202 t0 write SP_VS_OBJ_OFFSET_REG (22e0) SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 00055370: 0000: 000022e0 00000000 t0 write SP_HS_OBJ_OFFSET_REG (230d) SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } 00055378: 0000: 0000230d 7e020000 t0 write SP_DS_OBJ_OFFSET_REG (2334) SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } 00055380: 0000: 00002334 7e020000 t0 write SP_GS_OBJ_OFFSET_REG (235b) SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } 00055388: 0000: 0000235b 7e020000 t0 write SP_FS_OBJ_OFFSET_REG (22ea) SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } 00055390: 0000: 000022ea 7e020000 t0 write SP_VS_OBJ_START (22e1) SP_VS_OBJ_START: 0x49000 00049000: 0000: 00000000 13000000 00000000 00000000 00000000 00000000 00000000 00000000 * :0:0000:0000[13000000x_00000000x] (sy)end :0:0001:0001[00000000x_00000000x] nop :0:0002:0002[00000000x_00000000x] nop :0:0003:0003[00000000x_00000000x] nop :0:0004:0004[00000000x_00000000x] nop Stats: - shaderdb: 5 instr, 4 nops, 1 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 0 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 0 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) 00055398: 0000: 000022e1 00049000 t0 write SP_HS_OBJ_START (230e) SP_HS_OBJ_START: 0 000553a0: 0000: 0000230e 00000000 t0 write SP_DS_OBJ_START (2335) SP_DS_OBJ_START: 0 000553a8: 0000: 00002335 00000000 t0 write SP_GS_OBJ_START (235c) SP_GS_OBJ_START: 0 000553b0: 0000: 0000235c 00000000 t0 write SP_VS_LENGTH_REG (22e5) SP_VS_LENGTH_REG: 1 000553b8: 0000: 000022e5 00000001 t3 opcode: CP_LOAD_STATE4 (30) (3 dwords) { DST_OFF = 0 | STATE_SRC = SS4_INDIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 1 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0x49000 } :0:0000:0000[13000000x_00000000x] (sy)end :0:0001:0001[00000000x_00000000x] nop :0:0002:0002[00000000x_00000000x] nop :0:0003:0003[00000000x_00000000x] nop :0:0004:0004[00000000x_00000000x] nop Stats: - shaderdb: 5 instr, 4 nops, 1 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 0 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 0 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) 000553c0: 0000: c0013000 00620000 00049000 t0 write 0x2072 (2072) 0x2072: 00000000 000553cc: 0000: 00002072 00000000 t0 write UNKNOWN_2155 (2155) UNKNOWN_2155: 0 000553d4: 0000: 00002155 00000000 t0 write GRAS_CNTL (2003) GRAS_CNTL: { IJ_PERSP } 000553dc: 0000: 00002003 00000001 t0 write VPC_VARYING_INTERP[0].MODE (2142) VPC_VARYING_INTERP[0].MODE: 0 000553e4: 0000: 00002142 00000000 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0x600a0 } 000553ec: 0000: 000023c0 080604f0 t0 write HLSQ_CONTROL_3_REG (23c3) HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } 000553f4: 0000: 000023c3 fcfcfc00 t0 write HLSQ_CONTROL_4_REG (23c4) HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r0.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } 000553fc: 0000: 000023c4 00fcfc00 t0 write SP_FS_CTRL_REG0 (22e8) SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE } SP_FS_CTRL_REG1: { CONSTLENGTH = 2 | VARYING | 0x80000000 } 00055404: 0000: 000122e8 00340412 80100002 t0 write SP_FS_OBJ_START (22eb) SP_FS_OBJ_START: 0x46000 00046000: 0000: 00002000 5730cb00 00000000 03000000 00000000 00000000 00000000 00000000 * :2:0000:0000[5730cb00x_00002000x] (sy)(rpt3)bary.f (ei)hr0.x, (r)0, r0.x :0:0001:0004[03000000x_00000000x] end :0:0002:0005[00000000x_00000000x] nop :0:0003:0006[00000000x_00000000x] nop :0:0004:0007[00000000x_00000000x] nop :0:0005:0008[00000000x_00000000x] nop Stats: - shaderdb: 9 instr, 4 nops, 5 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 1 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 4 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) 00055410: 0000: 000022eb 00046000 t0 write SP_FS_LENGTH_REG (22ef) SP_FS_LENGTH_REG: 1 00055418: 0000: 000022ef 00000001 t0 write RB_RENDER_COMPONENTS (20fb) RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } 00055420: 0000: 000020fb 0000000f t3 opcode: CP_LOAD_STATE4 (30) (3 dwords) { DST_OFF = 0 | STATE_SRC = SS4_INDIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 1 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0x46000 } :2:0000:0000[5730cb00x_00002000x] (sy)(rpt3)bary.f (ei)hr0.x, (r)0, r0.x :0:0001:0004[03000000x_00000000x] end :0:0002:0005[00000000x_00000000x] nop :0:0003:0006[00000000x_00000000x] nop :0:0004:0007[00000000x_00000000x] nop :0:0005:0008[00000000x_00000000x] nop Stats: - shaderdb: 9 instr, 4 nops, 5 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 1 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 4 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) 00055428: 0000: c0013000 00720000 00046000 t0 write SP_SP_CTRL_REG (22c0) SP_SP_CTRL_REG: { 0x60010 } 00055434: 0000: 000022c0 00060010 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 28 | GROUP_ID = 3 } { ADDR_LO = 0x9d410 } 0005543c: 0000: c0014300 0300001c 0009d410 t0 write RB_DEPTH_INFO (2103) RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTH4_NONE | DEPTH_BASE = 0 } RB_DEPTH_PITCH: 0 RB_DEPTH_PITCH2: 0 00055448: 0000: 00022103 00000000 00000000 00000000 t0 write GRAS_DEPTH_CONTROL (2077) GRAS_DEPTH_CONTROL: { FORMAT = DEPTH4_NONE } 00055458: 0000: 00002077 00000000 t0 write RB_STENCIL_INFO (2108) RB_STENCIL_INFO: { STENCIL_BASE = 0 } RB_STENCIL_PITCH: 0 0x210a: 00000000 00055460: 0000: 00022108 00000000 00000000 00000000 t0 write 0x2002 (2002) 0x2002: 00000000 00055470: 0000: 00002002 00000000 t0 write RB_ALPHA_CONTROL (20f8) RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } 00055478: 0000: 000020f8 00000e00 t0 write RB_MRT[0].CONTROL (20a4) RB_MRT[0].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0x7 } 00055480: 0000: 000020a4 07000c00 t0 write RB_MRT[0].BLEND_CONTROL (20a8) RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } 00055488: 0000: 000020a8 00000000 t0 write GRAS_CL_CLIP_CNTL (2000) GRAS_CL_CLIP_CNTL: { 0x80000 } 00055490: 0000: 00002000 00080000 t0 write GRAS_SU_POLY_OFFSET_SCALE (2074) GRAS_SU_POLY_OFFSET_SCALE: 0.000000 GRAS_SU_POLY_OFFSET_OFFSET: 0.000000 GRAS_SU_POLY_OFFSET_CLAMP: 0.000000 00055498: 0000: 00022074 00000000 00000000 00000000 t0 write GRAS_SU_MODE_CONTROL (2078) GRAS_SU_MODE_CONTROL: { FRONT_CW | LINEHALFWIDTH = 0.500000 | MSAA_ENABLE | RENDERING_PASS } 000554a8: 0000: 00002078 00102014 t0 write GRAS_SC_SCREEN_SCISSOR_TL (207c) GRAS_SC_SCREEN_SCISSOR_TL: { X = 2 | Y = 13 } GRAS_SC_SCREEN_SCISSOR_BR: { X = 33 | Y = 44 } 000554b0: 0000: 0001207c 000d0002 002c0021 t0 write GRAS_CL_VPORT_XOFFSET_0 (2008) GRAS_CL_VPORT_XOFFSET_0: 18.000000 GRAS_CL_VPORT_XSCALE_0: 16.000000 GRAS_CL_VPORT_YOFFSET_0: 29.000000 GRAS_CL_VPORT_YSCALE_0: 16.000000 GRAS_CL_VPORT_ZOFFSET_0: 0.500000 GRAS_CL_VPORT_ZSCALE_0: 0.500000 000554bc: 0000: 00052008 41900000 41800000 41e80000 41800000 3f000000 3f000000 t0 write GRAS_CL_GB_CLIP_ADJ (2004) GRAS_CL_GB_CLIP_ADJ: { HORZ = 511 | VERT = 511 } 000554d8: 0000: 00002004 0007fdff t0 write GRAS_SC_CONTROL (207b) GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 4 | RASTER_MODE = 0 } 000554e0: 0000: 0000207b 00000200 t0 write 0x2382 (2382) 0x2382: 00000002 000554e8: 0000: 00002382 00000002 t0 write RB_MSAA_CONTROL (20a2) RB_MSAA_CONTROL: { SAMPLES = 4 } 000554f0: 0000: 000020a2 00008000 t0 write RB_RENDER_CONTROL2 (20a3) RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 4 | IJ_PERSP_PIXEL } 000554f8: 0000: 000020a3 00001200 t0 write RB_MRT[0].BUF_INFO (20a5) RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB4_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_ALWAYS | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 1024 } RB_MRT[0].BASE: 0 RB_MRT[0].CONTROL3: { STRIDE = 64 } 00055500: 0000: 000220a5 0010029a 00000000 00000200 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 43 | GROUP_ID = 2 } { ADDR_LO = 0x9d480 } 00055510: 0000: c0014300 0200002b 0009d480 t0 write 0x215c (215c) 0x215c: 00000000 0x215d: 00000000 0005551c: 0000: 0001215c 00000000 00000000 t0 write 0x215f (215f) 0x215f: 00000000 00055528: 0000: 0000215f 00000000 t0 write 0x215e (215e) 0x215e: 00000000 00055530: 0000: 0000215e 00000000 t0 write 0x2161 (2161) 0x2161: 00000000 0x2162: 00000000 00055538: 0000: 00012161 00000000 00000000 t0 write 0x2164 (2164) 0x2164: 00000000 00055544: 0000: 00002164 00000000 t0 write 0x2163 (2163) 0x2163: 00000000 0005554c: 0000: 00002163 00000000 t0 write 0x2166 (2166) 0x2166: 00000000 0x2167: 00000000 00055554: 0000: 00012166 00000000 00000000 t0 write 0x2169 (2169) 0x2169: 00000000 00055560: 0000: 00002169 00000000 t0 write 0x2168 (2168) 0x2168: 00000000 00055568: 0000: 00002168 00000000 t0 write 0x216b (216b) 0x216b: 00000000 0x216c: 00000000 00055570: 0000: 0001216b 00000000 00000000 t0 write VPC_SO_FLUSH_WADDR_3 (216e) VPC_SO_FLUSH_WADDR_3: 0 0005557c: 0000: 0000216e 00000000 t0 write 0x216d (216d) 0x216d: 00000000 00055584: 0000: 0000216d 00000000 t0 write UNKNOWN_2156 (2156) UNKNOWN_2156: 0 0005558c: 0000: 00002156 00000000 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 18 | GROUP_ID = 1 } { ADDR_LO = 0x9d530 } 00055594: 0000: c0014300 01000012 0009d530 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 15 | GROUP_ID = 0 } { ADDR_LO = 0x9d580 } 000555a0: 0000: c0014300 0000000f 0009d580 group_id: 0 count: 15 addr: 000000000009d580 flags: 0 0009d580: 0000: 00002073 00000000 00002101 00000000 00002106 00000000 000021e5 00000000 0009d5a0: 0020: 0001210b 00000000 00000000 00002381 00000000 000023a0 00000000 t0 write GRAS_ALPHA_CONTROL (2073) GRAS_ALPHA_CONTROL: { 0 } 0009d580: 0000: 00002073 00000000 t0 write RB_DEPTH_CONTROL (2101) RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } 0009d588: 0000: 00002101 00000000 t0 write RB_STENCIL_CONTROL (2106) RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } 0009d590: 0000: 00002106 00000000 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 0009d598: 0000: 000021e5 00000000 t0 write RB_STENCILREFMASK (210b) RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 0009d5a0: 0000: 0001210b 00000000 00000000 t0 write TPL1_TP_TEX_COUNT (2381) TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } 0009d5ac: 0000: 00002381 00000000 t0 write TPL1_TP_FS_TEX_COUNT (23a0) TPL1_TP_FS_TEX_COUNT: 0 0009d5b4: 0000: 000023a0 00000000 group_id: 1 count: 18 addr: 000000000009d530 flags: 0 0009d530: 0000: 00002200 082a0008 00002201 fcfc0081 00002203 0000fc00 0007220a 0008080f 0009d550: 0020: 0009d3b0 00000060 00000001 0000080f 0009d3e0 00000030 00000001 0001228a 0009d570: 0040: 7000411f 3000011f t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } 0009d530: 0000: 00002200 082a0008 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } 0009d538: 0000: 00002201 fcfc0081 t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } 0009d540: 0000: 00002203 0000fc00 t0 write VFD_FETCH[0].INSTR_0 (220a) VFD_FETCH[0].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 | SWITCHNEXT } VFD_FETCH[0].INSTR_1: 0x9d3b0 VFD_FETCH[0].INSTR_2: { SIZE = 0x60 } VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 } VFD_FETCH[0x1].INSTR_1: 0x9d3e0 VFD_FETCH[0x1].INSTR_2: { SIZE = 0x30 } VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } 0009d548: 0000: 0007220a 0008080f 0009d3b0 00000060 00000001 0000080f 0009d3e0 00000030 0009d568: 0020: 00000001 t0 write VFD_DECODE[0].INSTR (228a) VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID | SWITCHNEXT } VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID } 0009d56c: 0000: 0001228a 7000411f 3000011f group_id: 2 count: 43 addr: 000000000009d480 flags: 0 0009d480: 0000: 000020a1 00000000 000022f1 0001a100 000022f0 fc00fc01 00002100 00000001 0009d4a0: 0020: 000021e5 00000000 000020f9 ffff0501 0000214a 00000000 00002140 42001004 0009d4c0: 0040: 001922c6 0010fc04 00001e00 00000000 00000000 00000000 00000000 00000000 * 0009d500: 0080: 00000000 00000000 00fcfc00 00000008 00000000 00000000 00000000 00000000 * t0 write RB_RENDER_CONTROL (20a1) RB_RENDER_CONTROL: { 0 } 0009d480: 0000: 000020a1 00000000 t0 write SP_FS_MRT[0].REG (22f1) SP_FS_MRT[0].REG: { REGID = r0.x | HALF_PRECISION | MRTFORMAT = RB4_R8G8B8A8_UNORM } 0009d488: 0000: 000022f1 0001a100 t0 write SP_FS_OUTPUT_REG (22f0) SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 0009d490: 0000: 000022f0 fc00fc01 t0 write RB_FS_OUTPUT_REG (2100) RB_FS_OUTPUT_REG: { MRT = 1 } 0009d498: 0000: 00002100 00000001 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 0009d4a0: 0000: 000021e5 00000000 t0 write RB_FS_OUTPUT (20f9) RB_FS_OUTPUT: { ENABLE_BLEND = 0x1 | INDEPENDENT_BLEND | SAMPLE_MASK = 0xffff | 0x400 } 0009d4a8: 0000: 000020f9 ffff0501 t0 write VPC_VARYING_PS_REPL[0].MODE (214a) VPC_VARYING_PS_REPL[0].MODE: 0 0009d4b0: 0000: 0000214a 00000000 t0 write VPC_ATTR (2140) VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 } 0009d4b8: 0000: 00002140 42001004 t0 write SP_VS_PARAM_REG (22c6) SP_VS_PARAM_REG: { POSREGID = r1.x | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } SP_VS_OUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } UNKNOWN_22D7: 0xfcfc00 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 0009d4c0: 0000: 001922c6 0010fc04 00001e00 00000000 00000000 00000000 00000000 00000000 * 0009d500: 0040: 00000000 00000000 00fcfc00 00000008 00000000 00000000 00000000 00000000 * group_id: 3 count: 28 addr: 000000000009d410 flags: 0 0009d410: 0000: 000021c4 02000001 00002141 00040400 00002001 00000000 000022c4 00200800 0009d430: 0020: 000022c5 08000002 0000230c 00000000 00002318 00000000 00002319 00000000 0009d450: 0040: 00002340 00000000 00002202 fcfcfcfc 00002204 0000fcfc 00002154 00000000 0009d470: 0060: 000021e7 00000000 000021c5 00000012 t0 write PC_PRIM_VTX_CNTL (21c4) PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } 0009d410: 0000: 000021c4 02000001 t0 write VPC_PACK (2141) VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } 0009d418: 0000: 00002141 00040400 t0 write UNKNOWN_2001 (2001) UNKNOWN_2001: 0 0009d420: 0000: 00002001 00000000 t0 write SP_VS_CTRL_REG0 (22c4) SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 2 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 0009d428: 0000: 000022c4 00200800 t0 write SP_VS_CTRL_REG1 (22c5) SP_VS_CTRL_REG1: { CONSTLENGTH = 2 | INITIALOUTSTANDING = 8 } 0009d430: 0000: 000022c5 08000002 t0 write 0x230c (230c) 0x230c: 00000000 0009d438: 0000: 0000230c 00000000 t0 write 0x2318 (2318) 0x2318: 00000000 0009d440: 0000: 00002318 00000000 t0 write 0x2319 (2319) 0x2319: 00000000 0009d448: 0000: 00002319 00000000 t0 write 0x2340 (2340) 0x2340: 00000000 0009d450: 0000: 00002340 00000000 t0 write VFD_CONTROL_2 (2202) VFD_CONTROL_2: 0xfcfcfcfc 0009d458: 0000: 00002202 fcfcfcfc t0 write VFD_CONTROL_4 (2204) VFD_CONTROL_4: 0xfcfc 0009d460: 0000: 00002204 0000fcfc t0 write UNKNOWN_2154 (2154) UNKNOWN_2154: 0 0009d468: 0000: 00002154 00000000 t0 write PC_HS_PARAM (21e7) PC_HS_PARAM: { VERTICES_OUT = 0 | SPACING = EQUAL_SPACING } 0009d470: 0000: 000021e7 00000000 t0 write PC_PRIM_VTX_CNTL2 (21c5) PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 0009d478: 0000: 000021c5 00000012 t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = USE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x200000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 3 } draw[96] register values + 00000000 0xcc4: 00000000 + 00000004 UNKNOWN_0CC5: 0x4 + 80200000 0xd03: 80200000 !+ 00000001 HLSQ_MODE_CONTROL: 0x1 + 00000000 UNKNOWN_0E42: 0 + 00000100 VPC_DEBUG_ECO_CONTROL: 0x100 + 00040000 UNKNOWN_0EC2: 0x40000 !+ 0000001e SP_MODE_CONTROL: 0x1e !+ 00000028 TPL1_TP_MODE_CONTROL: 0x28 !+ 00080000 GRAS_CL_CLIP_CNTL: { 0x80000 } + 00000000 UNKNOWN_2001: 0 + 00000000 0x2002: 00000000 + 00000001 GRAS_CNTL: { IJ_PERSP } + 0007fdff GRAS_CL_GB_CLIP_ADJ: { HORZ = 511 | VERT = 511 } + 41900000 GRAS_CL_VPORT_XOFFSET_0: 18.000000 + 41800000 GRAS_CL_VPORT_XSCALE_0: 16.000000 + 41e80000 GRAS_CL_VPORT_YOFFSET_0: 29.000000 + 41800000 GRAS_CL_VPORT_YSCALE_0: 16.000000 + 3f000000 GRAS_CL_VPORT_ZOFFSET_0: 0.500000 + 3f000000 GRAS_CL_VPORT_ZSCALE_0: 0.500000 + ffc00010 GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 4092.000000 } + 00000008 GRAS_SU_POINT_SIZE: 0.500000 + 00000000 0x2072: 00000000 !+ 00000000 GRAS_ALPHA_CONTROL: { 0 } + 00000000 GRAS_SU_POLY_OFFSET_SCALE: 0.000000 + 00000000 GRAS_SU_POLY_OFFSET_OFFSET: 0.000000 + 00000000 GRAS_SU_POLY_OFFSET_CLAMP: 0.000000 + 00000000 GRAS_DEPTH_CONTROL: { FORMAT = DEPTH4_NONE } !+ 00102014 GRAS_SU_MODE_CONTROL: { FRONT_CW | LINEHALFWIDTH = 0.500000 | MSAA_ENABLE | RENDERING_PASS } !+ 00000200 GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 4 | RASTER_MODE = 0 } !+ 000d0002 GRAS_SC_SCREEN_SCISSOR_TL: { X = 2 | Y = 13 } !+ 002c0021 GRAS_SC_SCREEN_SCISSOR_BR: { X = 33 | Y = 44 } !+ 00000000 RB_RENDER_CONTROL: { 0 } !+ 00008000 RB_MSAA_CONTROL: { SAMPLES = 4 } !+ 00001200 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 4 | IJ_PERSP_PIXEL } !+ 07000c00 RB_MRT[0].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0x7 } !+ 0010029a RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB4_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_ALWAYS | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 1024 } !+ 00000000 RB_MRT[0].BASE: 0 !+ 00000200 RB_MRT[0].CONTROL3: { STRIDE = 64 } + 00000000 RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } + 00000e00 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } !+ ffff0501 RB_FS_OUTPUT: { ENABLE_BLEND = 0x1 | INDEPENDENT_BLEND | SAMPLE_MASK = 0xffff | 0x400 } + 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } + 00000001 RB_FS_OUTPUT_REG: { MRT = 1 } + 00000000 RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } + 00000000 RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTH4_NONE | DEPTH_BASE = 0 } + 00000000 RB_DEPTH_PITCH: 0 + 00000000 RB_DEPTH_PITCH2: 0 + 00000000 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } + 00000000 RB_STENCIL_INFO: { STENCIL_BASE = 0 } + 00000000 RB_STENCIL_PITCH: 0 + 00000000 0x210a: 00000000 + 00000000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } + 00000000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } !+ 42001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 } + 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } !+ 00000000 VPC_VARYING_INTERP[0].MODE: 0 !+ 00000000 VPC_VARYING_PS_REPL[0].MODE: 0 + 00000000 UNKNOWN_2152: 0 + 00000000 UNKNOWN_2153: 0 + 00000000 UNKNOWN_2154: 0 + 00000000 UNKNOWN_2155: 0 + 00000000 UNKNOWN_2156: 0 + 00000000 0x215c: 00000000 + 00000000 0x215d: 00000000 + 00000000 0x215e: 00000000 + 00000000 0x215f: 00000000 + 00000000 0x2161: 00000000 + 00000000 0x2162: 00000000 + 00000000 0x2163: 00000000 + 00000000 0x2164: 00000000 + 00000000 0x2166: 00000000 + 00000000 0x2167: 00000000 + 00000000 0x2168: 00000000 + 00000000 0x2169: 00000000 + 00000000 0x216b: 00000000 + 00000000 0x216c: 00000000 + 00000000 0x216d: 00000000 + 00000000 VPC_SO_FLUSH_WADDR_3: 0 !+ 0000001f UNKNOWN_21C3: 0x1f !+ 02000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + ffffffff PC_RESTART_INDEX: 0xffffffff + 00000000 PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } + 00000001 UNKNOWN_21E6: 0x1 + 00000000 PC_HS_PARAM: { VERTICES_OUT = 0 | SPACING = EQUAL_SPACING } !+ 082a0008 VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } !+ fcfc0081 VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } + fcfcfcfc VFD_CONTROL_2: 0xfcfcfcfc !+ 0000fc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } + 0000fcfc VFD_CONTROL_4: 0xfcfc + 00000000 VFD_INDEX_OFFSET: 0 + 00000000 UNKNOWN_2209: 0 + 0008080f VFD_FETCH[0].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 | SWITCHNEXT } !+ 0009d3b0 VFD_FETCH[0].INSTR_1: 0x9d3b0 + 00000060 VFD_FETCH[0].INSTR_2: { SIZE = 0x60 } + 00000001 VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } + 0000080f VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 } !+ 0009d3e0 VFD_FETCH[0x1].INSTR_1: 0x9d3e0 + 00000030 VFD_FETCH[0x1].INSTR_2: { SIZE = 0x30 } + 00000001 VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } + 7000411f VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID | SWITCHNEXT } + 3000011f VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID } + 00060010 SP_SP_CTRL_REG: { 0x60010 } + 000005c3 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } !+ 00200800 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 2 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } !+ 08000002 SP_VS_CTRL_REG1: { CONSTLENGTH = 2 | INITIALOUTSTANDING = 8 } !+ 0010fc04 SP_VS_PARAM_REG: { POSREGID = r1.x | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } !+ 00001e00 SP_VS_OUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00fcfc00 UNKNOWN_22D7: 0xfcfc00 + 00000008 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } !+ 00049000 SP_VS_OBJ_START: 0x49000 00049000: 0000: 00000000 13000000 00000000 00000000 00000000 00000000 00000000 00000000 * :0:0000:0000[13000000x_00000000x] (sy)end :0:0001:0001[00000000x_00000000x] nop :0:0002:0002[00000000x_00000000x] nop :0:0003:0003[00000000x_00000000x] nop :0:0004:0004[00000000x_00000000x] nop Stats: - shaderdb: 5 instr, 4 nops, 1 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 0 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 0 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) !+ 00000001 SP_VS_LENGTH_REG: 1 !+ 00340412 SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE } !+ 80100002 SP_FS_CTRL_REG1: { CONSTLENGTH = 2 | VARYING | 0x80000000 } !+ 7e020000 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } !+ 00046000 SP_FS_OBJ_START: 0x46000 00046000: 0000: 00002000 5730cb00 00000000 03000000 00000000 00000000 00000000 00000000 * :2:0000:0000[5730cb00x_00002000x] (sy)(rpt3)bary.f (ei)hr0.x, (r)0, r0.x :0:0001:0004[03000000x_00000000x] end :0:0002:0005[00000000x_00000000x] nop :0:0003:0006[00000000x_00000000x] nop :0:0004:0007[00000000x_00000000x] nop :0:0005:0008[00000000x_00000000x] nop Stats: - shaderdb: 9 instr, 4 nops, 5 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 1 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 4 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 1 (sy) + 00000001 SP_FS_LENGTH_REG: 1 !+ fc00fc01 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r63.x } !+ 0001a100 SP_FS_MRT[0].REG: { REGID = r0.x | HALF_PRECISION | MRTFORMAT = RB4_R8G8B8A8_UNORM } + 00000000 0x230c: 00000000 + 7e020000 SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } + 00000000 SP_HS_OBJ_START: 0 + 00000000 0x2318: 00000000 + 00000000 0x2319: 00000000 + 7e020000 SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } + 00000000 SP_DS_OBJ_START: 0 + 00000000 0x2340: 00000000 + 7e020000 SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 } + 00000000 SP_GS_OBJ_START: 0 + 00000808 TPL1_TP_TEX_OFFSET: 0x808 + 00000000 TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } !+ 00000002 0x2382: 00000002 !+ 00000000 TPL1_TP_FS_TEX_COUNT: 0 !+ 080604f0 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0x600a0 } !+ fcfc1108 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x1008 } !+ fff3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } + fcfcfc00 HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } !+ 00fcfc00 HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r0.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } !+ 01010002 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 2 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 1 } !+ 017f0202 HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 2 | CONSTOBJECTOFFSET = 2 | ENABLED | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 } !+ 007e0200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } !+ 007e0200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } !+ 007e0200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 2 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } !+ 00000003 HLSQ_UPDATE_CONTROL: 0x3 000555ac: 0000: c0023800 00200984 00000001 00000003 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 18 | GROUP_ID = 1 } { ADDR_LO = 0x9d6f0 } 000555bc: 0000: c0014300 01000012 0009d6f0 group_id: 1 count: 18 addr: 000000000009d6f0 flags: 0 0009d6f0: 0000: 00002200 082a0008 00002201 fcfc0081 00002203 0000fc00 0007220a 0008080f 0009d710: 0020: 0009d690 00000060 00000001 0000080f 0009d6c0 00000030 00000001 0001228a 0009d730: 0040: 7000411f 3000011f t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } 0009d6f0: 0000: 00002200 082a0008 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } 0009d6f8: 0000: 00002201 fcfc0081 t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } 0009d700: 0000: 00002203 0000fc00 t0 write VFD_FETCH[0].INSTR_0 (220a) VFD_FETCH[0].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 | SWITCHNEXT } VFD_FETCH[0].INSTR_1: 0x9d690 VFD_FETCH[0].INSTR_2: { SIZE = 0x60 } VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 } VFD_FETCH[0x1].INSTR_1: 0x9d6c0 VFD_FETCH[0x1].INSTR_2: { SIZE = 0x30 } VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } 0009d708: 0000: 0007220a 0008080f 0009d690 00000060 00000001 0000080f 0009d6c0 00000030 0009d728: 0020: 00000001 t0 write VFD_DECODE[0].INSTR (228a) VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID | SWITCHNEXT } VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID } 0009d72c: 0000: 0001228a 7000411f 3000011f t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = USE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x200000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 3 } draw[97] register values + 082a0008 VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } + fcfc0081 VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } + 0000fc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } + 0008080f VFD_FETCH[0].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 | SWITCHNEXT } !+ 0009d690 VFD_FETCH[0].INSTR_1: 0x9d690 + 00000060 VFD_FETCH[0].INSTR_2: { SIZE = 0x60 } + 00000001 VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } + 0000080f VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 15 | BUFSTRIDE = 16 } !+ 0009d6c0 VFD_FETCH[0x1].INSTR_1: 0x9d6c0 + 00000030 VFD_FETCH[0x1].INSTR_2: { SIZE = 0x30 } + 00000001 VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } + 7000411f VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID | SWITCHNEXT } + 3000011f VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 16 | LASTCOMPVALID } 000555c8: 0000: c0023800 00200984 00000001 00000003 0016b094: 0000: c0013f00 00055328 000000ac t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 0016b0a0: 0000: c0014300 00040000 00000000 t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:00170a7c ibsize:000000f7 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00170a7c: 0000: c0002600 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x4 00170a84: 0000: 00000ec3 00000004 t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x68 00170a8c: 0000: 00000f03 00000068 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00170a94: 0000: c0002600 00000000 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } 00170a9c: 0000: 000023c0 080004f0 t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = 0x1d } event (null) 00170aa4: 0000: c0004600 0000001d t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = FACENESS_FLUSH } event FACENESS_FLUSH 00170aac: 0000: c0004600 0000001c t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00170ab4: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0 00170abc: 0000: 00000cc6 00000000 t0 write UNKNOWN_0E42 (0e42) UNKNOWN_0E42: 0 00170ac4: 0000: 00000e42 00000000 t0 write HLSQ_MODE_CONTROL (0e05) HLSQ_MODE_CONTROL: 0x2 00170acc: 0000: 00000e05 00000002 t0 write UNKNOWN_0CC5 (0cc5) UNKNOWN_0CC5: 0x4 00170ad4: 0000: 00000cc5 00000004 t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x7 00170adc: 0000: 000023db 00000007 t0 write VFD_CONTROL_2 (2202) VFD_CONTROL_2: 0xfcfcfcfc 00170ae4: 0000: 00002202 fcfcfcfc t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } 00170aec: 0000: 00002203 fcfcfc00 t0 write VFD_CONTROL_4 (2204) VFD_CONTROL_4: 0xfcfc 00170af4: 0000: 00002204 0000fcfc t0 write VFD_INDEX_OFFSET (2208) VFD_INDEX_OFFSET: 0 00170afc: 0000: 00002208 00000000 t0 write UNKNOWN_2209 (2209) UNKNOWN_2209: 0 00170b04: 0000: 00002209 00000000 t0 write UNKNOWN_2152 (2152) UNKNOWN_2152: 0 UNKNOWN_2153: 0 00170b0c: 0000: 00012152 00000000 00000000 t0 write UNKNOWN_2156 (2156) UNKNOWN_2156: 0 00170b18: 0000: 00002156 00000000 t0 write UNKNOWN_2154 (2154) UNKNOWN_2154: 0 00170b20: 0000: 00002154 00000000 t0 write UNKNOWN_2155 (2155) UNKNOWN_2155: 0 00170b28: 0000: 00002155 00000000 t0 write UNKNOWN_21C3 (21c3) UNKNOWN_21C3: 0x1d 00170b30: 0000: 000021c3 0000001d t0 write PC_PRIM_VTX_CNTL2 (21c5) PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 00170b38: 0000: 000021c5 00000012 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 00170b40: 0000: 000021e5 00000000 t0 write GRAS_SU_MODE_CONTROL (2078) GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } 00170b48: 0000: 00002078 00000000 t0 write UNKNOWN_2001 (2001) UNKNOWN_2001: 0 00170b50: 0000: 00002001 00000000 t0 write GRAS_CNTL (2003) GRAS_CNTL: { IJ_PERSP } 00170b58: 0000: 00002003 00000001 t0 write GRAS_CL_CLIP_CNTL (2000) GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } 00170b60: 0000: 00002000 00188000 t0 write TPL1_TP_TEX_COUNT (2381) TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } 00170b68: 0000: 00002381 00000000 t0 write TPL1_TP_FS_TEX_COUNT (23a0) TPL1_TP_FS_TEX_COUNT: 0x3 00170b70: 0000: 000023a0 00000003 t0 write RB_ALPHA_CONTROL (20f8) RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } 00170b78: 0000: 000020f8 00000e00 t0 write RB_RENDER_COMPONENTS (20fb) RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } 00170b80: 0000: 000020fb 0000000f t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 00170b88: 0000: c0014300 00040000 00000000 t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } 00170b94: 0000: 00002200 000a0000 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } 00170b9c: 0000: 00002201 fc030000 t0 write SP_INSTR_CACHE_CTRL (22c1) SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } 00170ba4: 0000: 000022c1 000005c3 t0 write HLSQ_CONTROL_1_REG (23c1) HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } 00170bac: 0000: 000023c1 fcfc0120 t0 write HLSQ_CONTROL_2_REG (23c2) HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 00170bb4: 0000: 000023c2 27f3f3f0 t0 write HLSQ_VS_CONTROL_REG (23c5) HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } 00170bbc: 0000: 000023c5 02010042 t0 write HLSQ_FS_CONTROL_REG (23c6) HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00170bc4: 0000: 000023c6 0041423e t0 write HLSQ_HS_CONTROL_REG (23c7) HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00170bcc: 0000: 000023c7 00404200 t0 write HLSQ_DS_CONTROL_REG (23c8) HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00170bd4: 0000: 000023c8 00404200 t0 write HLSQ_GS_CONTROL_REG (23c9) HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00170bdc: 0000: 000023c9 00404200 t0 write HLSQ_CS_CONTROL_REG (23ca) HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } 00170be4: 0000: 000023ca 00004200 t0 write SP_SP_CTRL_REG (22c0) SP_SP_CTRL_REG: { 0x60010 } 00170bec: 0000: 000022c0 00060010 t0 write UNKNOWN_21E6 (21e6) UNKNOWN_21E6: 0x1 00170bf4: 0000: 000021e6 00000001 t0 write SP_VS_CTRL_REG0 (22c4) SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 00170bfc: 0000: 000022c4 00200c10 t0 write SP_VS_CTRL_REG1 (22c5) SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } 00170c04: 0000: 000022c5 01000042 t0 write VPC_ATTR (2140) VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | 0x40000000 } 00170c0c: 0000: 00002140 40001004 t0 write VPC_PACK (2141) VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } 00170c14: 0000: 00002141 00040400 t0 write PC_PRIM_VTX_CNTL (21c4) PC_PRIM_VTX_CNTL: { VAROUT = 1 } 00170c1c: 0000: 000021c4 00000001 t0 write SP_VS_PARAM_REG (22c6) SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } UNKNOWN_22D7: 0xfcfc00 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 00170c24: 0000: 001922c6 0010fc03 00001e03 00000000 00000000 00000000 00000000 00000000 * 00170c64: 0040: 00000000 00000000 00fcfc00 00000008 00000000 00000000 00000000 00000000 * t0 write SP_VS_OBJ_OFFSET_REG (22e0) SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 00170c90: 0000: 000022e0 00000000 t0 write SP_VS_OBJ_START (22e1) SP_VS_OBJ_START: 0x1 00170c98: 0000: 000022e1 00000001 t0 write SP_VS_LENGTH_REG (22e5) SP_VS_LENGTH_REG: 2 00170ca0: 0000: 000022e5 00000002 t3 opcode: CP_LOAD_STATE4 (30) (67 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } :2:0000:0000[56d81803x_20020003x] (sy)(ss)(nop3) shl.b r0.w, r0.w, 2 :1:0001:0004[20150000x_00000003x] cov.s32s16 hr0.x, r0.w :0:0002:0005[00000200x_00000000x] (rpt2)nop :1:0003:0008[201100f4x_00000000x] mova a0.x, hr0.x :0:0004:0009[00000500x_00000000x] (rpt5)nop :1:0005:0015[20154003x_00000c20x] mov.s32s32 r0.w, c :1:0006:0016[20154004x_00000c21x] mov.s32s32 r1.x, c :1:0007:0017[20154005x_00000c22x] mov.s32s32 r1.y, c :1:0008:0018[20156006x_00000c23x] (ul)mov.s32s32 r1.z, c :0:0009:0019[03000000x_00000000x] end :2:0010:0020[46f00007x_20050000x] shr.b r1.w, r0.x, 5 :2:0011:0021[43980008x_201f0000x] (nop2) and.b r2.x, r0.x, 31 :2:0012:0024[43980807x_201f0007x] (nop3) and.b r1.w, r1.w, 31 :2:0013:0028[46100807x_20100007x] (nop1) mul.u24 r1.w, r1.w, 16 :3:0014:0030[62040007x_00071014x] mad.u24 r1.w, c5.x, r2.x, r1.w :0:0015:0031[00000500x_00000000x] (rpt5)nop :6:0016:0037[c2c60f00x_04800006x] stlw.u32 l[r1.w], r0.w, 4 :0:0017:0038[04800000x_00000000x] chmask :0:0018:0039[05000000x_00000000x] chsh Stats: - shaderdb: 40 instr, 24 nops, 16 non-nops, 5 mov, 1 cov - shaderdb: 0 last-baryf, 0 half, 2 full, 5 constlen - shaderdb: 27 cat0, 6 cat1, 5 cat2, 1 cat3, 0 cat4, 0 cat5, 1 cat6, 0 cat7 - shaderdb: 0 sstall, 1 (ss), 1 (sy) 00170ca8: 0000: c0413000 00a00000 00000000 20020003 56d81803 00000003 20150000 00000000 00170cc8: 0020: 00000200 00000000 201100f4 00000000 00000500 00000c20 20154003 00000c21 00170ce8: 0040: 20154004 00000c22 20154005 00000c23 20156006 00000000 03000000 20050000 00170d08: 0060: 46f00007 201f0000 43980008 201f0007 43980807 20100007 46100807 00071014 00170d28: 0080: 62040007 00000000 00000500 04800006 c2c60f00 00000000 04800000 00000000 00170d48: 00a0: 05000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 * t0 write GRAS_SC_CONTROL (207b) GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = 0 | MSAA_DISABLE | RASTER_MODE = 0 } 00170db4: 0000: 0000207b 00000808 t0 write RB_MSAA_CONTROL (20a2) RB_MSAA_CONTROL: { DISABLE | SAMPLES = 0 } 00170dbc: 0000: 000020a2 00001000 t0 write RB_RENDER_CONTROL (20a1) RB_RENDER_CONTROL: { DISABLE_COLOR_PIPE | 0x2 } 00170dc4: 0000: 000020a1 00000022 t0 write RB_DEPTH_CONTROL (2101) RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } 00170dcc: 0000: 00002101 00000000 t0 write GRAS_ALPHA_CONTROL (2073) GRAS_ALPHA_CONTROL: { 0x2 } 00170dd4: 0000: 00002073 00000002 t0 write RB_STENCIL_CONTROL (2106) RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } 00170ddc: 0000: 00002106 00000000 t0 write RB_COPY_CONTROL (20fc) RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_FOUR | MODE = RB_COPY_DEPTH_STENCIL | FASTCLEAR = 0 | GMEM_BASE = 0 } RB_COPY_DEST_BASE: { BASE = 0x4f000 } RB_COPY_DEST_PITCH: { PITCH = 256 } RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_DISABLE | COMPONENT_ENABLE = 0xf | ENDIAN = ENDIAN_NONE | TILE = TILE4_3 } 00170de4: 0000: 000320fc 00000052 0004f000 00000008 0303c068 t0 write UNKNOWN_20EF (20ef) UNKNOWN_20EF: 0 00170df8: 0000: 000020ef 00000000 t0 write GRAS_SC_SCREEN_SCISSOR_TL (207c) GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } 00170e00: 0000: 0001207c 00000000 003f003f t0 write RB_FRAME_BUFFER_DIMENSION (0ce0) RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } 00170e0c: 0000: 00000ce0 00400040 t0 write 0xce1 (0ce1) 0xce1: 00000000 00170e14: 0000: 00000ce1 00000000 t3 opcode: CP_LOAD_STATE4 (30) (11 dwords) { DST_OFF = 8 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } 00170e28: 0.000000 0.000000 1.000000 1.000000 64.000000 64.000000 1.000000 1.000000 00170e28: 0000: 00000000 00000000 3f800000 3f800000 42800000 42800000 3f800000 3f800000 00170e1c: 0000: c0093000 00a00008 00000001 00000000 00000000 3f800000 3f800000 42800000 00170e3c: 0020: 42800000 3f800000 3f800000 t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x80000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 2 } draw[98] register values + 00000004 UNKNOWN_0CC5: 0x4 + 00000000 UNKNOWN_0CC6: 0 + 00400040 RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } + 00000000 0xce1: 00000000 !+ 00000002 HLSQ_MODE_CONTROL: 0x2 + 00000000 UNKNOWN_0E42: 0 !+ 00000004 SP_MODE_CONTROL: 0x4 !+ 00000068 TPL1_TP_MODE_CONTROL: 0x68 !+ 00188000 GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } + 00000000 UNKNOWN_2001: 0 + 00000001 GRAS_CNTL: { IJ_PERSP } !+ 00000002 GRAS_ALPHA_CONTROL: { 0x2 } !+ 00000000 GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } !+ 00000808 GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = 0 | MSAA_DISABLE | RASTER_MODE = 0 } !+ 00000000 GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } !+ 003f003f GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } !+ 00000022 RB_RENDER_CONTROL: { DISABLE_COLOR_PIPE | 0x2 } !+ 00001000 RB_MSAA_CONTROL: { DISABLE | SAMPLES = 0 } + 00000000 UNKNOWN_20EF: 0 + 00000e00 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } + 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } !+ 00000052 RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_FOUR | MODE = RB_COPY_DEPTH_STENCIL | FASTCLEAR = 0 | GMEM_BASE = 0 } + 0004f000 RB_COPY_DEST_BASE: { BASE = 0x4f000 } + 00000008 RB_COPY_DEST_PITCH: { PITCH = 256 } !+ 0303c068 RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_DISABLE | COMPONENT_ENABLE = 0xf | ENDIAN = ENDIAN_NONE | TILE = TILE4_3 } + 00000000 RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } + 00000000 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } !+ 40001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | 0x40000000 } + 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } + 00000000 UNKNOWN_2152: 0 + 00000000 UNKNOWN_2153: 0 + 00000000 UNKNOWN_2154: 0 + 00000000 UNKNOWN_2155: 0 + 00000000 UNKNOWN_2156: 0 !+ 0000001d UNKNOWN_21C3: 0x1d !+ 00000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 } + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + 00000000 PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } + 00000001 UNKNOWN_21E6: 0x1 !+ 000a0000 VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } !+ fc030000 VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } + fcfcfcfc VFD_CONTROL_2: 0xfcfcfcfc !+ fcfcfc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } + 0000fcfc VFD_CONTROL_4: 0xfcfc + 00000000 VFD_INDEX_OFFSET: 0 + 00000000 UNKNOWN_2209: 0 + 00060010 SP_SP_CTRL_REG: { 0x60010 } + 000005c3 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } !+ 00200c10 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } !+ 01000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } !+ 0010fc03 SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } !+ 00001e03 SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00fcfc00 UNKNOWN_22D7: 0xfcfc00 + 00000008 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } !+ 00000001 SP_VS_OBJ_START: 0x1 !+ 00000002 SP_VS_LENGTH_REG: 2 + 00000000 TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } !+ 00000003 TPL1_TP_FS_TEX_COUNT: 0x3 !+ 080004f0 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } !+ fcfc0120 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } !+ 27f3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } !+ 02010042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } !+ 0041423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } !+ 00404200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } !+ 00404200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } !+ 00404200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00004200 HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } !+ 00000007 HLSQ_UPDATE_CONTROL: 0x7 00170e48: 0000: c0023800 00080888 00000001 00000002 0016b0ac: 0000: c0013f00 00170a7c 000000f7 t3 opcode: (null) (1d) (2 dwords) 0016b0b8: 0000: c0001d00 00000000 ############################################################ vertices: 0 ############################################################ cmdstream: 8 dwords t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) ibaddr:000555d8 ibsize:00000155 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 000555d8: 0000: c0002600 00000000 t0 write SP_MODE_CONTROL (0ec3) SP_MODE_CONTROL: 0x4 000555e0: 0000: 00000ec3 00000004 t0 write TPL1_TP_MODE_CONTROL (0f03) TPL1_TP_MODE_CONTROL: 0x68 000555e8: 0000: 00000f03 00000068 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 000555f0: 0000: c0002600 00000000 t0 write HLSQ_CONTROL_0_REG (23c0) HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } 000555f8: 0000: 000023c0 080004f0 t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = 0x1d } event (null) 00055600: 0000: c0004600 0000001d t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = FACENESS_FLUSH } event FACENESS_FLUSH 00055608: 0000: c0004600 0000001c t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00055610: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0 00055618: 0000: 00000cc6 00000000 t0 write UNKNOWN_0E42 (0e42) UNKNOWN_0E42: 0 00055620: 0000: 00000e42 00000000 t0 write HLSQ_MODE_CONTROL (0e05) HLSQ_MODE_CONTROL: 0x2 00055628: 0000: 00000e05 00000002 t0 write UNKNOWN_0CC5 (0cc5) UNKNOWN_0CC5: 0x4 00055630: 0000: 00000cc5 00000004 t0 write HLSQ_UPDATE_CONTROL (23db) HLSQ_UPDATE_CONTROL: 0x7 00055638: 0000: 000023db 00000007 t0 write VFD_CONTROL_2 (2202) VFD_CONTROL_2: 0xfcfcfcfc 00055640: 0000: 00002202 fcfcfcfc t0 write VFD_CONTROL_3 (2203) VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } 00055648: 0000: 00002203 fcfcfc00 t0 write VFD_CONTROL_4 (2204) VFD_CONTROL_4: 0xfcfc 00055650: 0000: 00002204 0000fcfc t0 write VFD_INDEX_OFFSET (2208) VFD_INDEX_OFFSET: 0 00055658: 0000: 00002208 00000000 t0 write UNKNOWN_2209 (2209) UNKNOWN_2209: 0 00055660: 0000: 00002209 00000000 t0 write UNKNOWN_2152 (2152) UNKNOWN_2152: 0 UNKNOWN_2153: 0 00055668: 0000: 00012152 00000000 00000000 t0 write UNKNOWN_2156 (2156) UNKNOWN_2156: 0 00055674: 0000: 00002156 00000000 t0 write UNKNOWN_2154 (2154) UNKNOWN_2154: 0 0005567c: 0000: 00002154 00000000 t0 write UNKNOWN_2155 (2155) UNKNOWN_2155: 0 00055684: 0000: 00002155 00000000 t0 write UNKNOWN_21C3 (21c3) UNKNOWN_21C3: 0x1d 0005568c: 0000: 000021c3 0000001d t0 write PC_PRIM_VTX_CNTL2 (21c5) PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 00055694: 0000: 000021c5 00000012 t0 write PC_GS_PARAM (21e5) PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 0005569c: 0000: 000021e5 00000000 t0 write GRAS_SU_MODE_CONTROL (2078) GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } 000556a4: 0000: 00002078 00000000 t0 write UNKNOWN_2001 (2001) UNKNOWN_2001: 0 000556ac: 0000: 00002001 00000000 t0 write GRAS_CNTL (2003) GRAS_CNTL: { IJ_PERSP } 000556b4: 0000: 00002003 00000001 t0 write GRAS_CL_CLIP_CNTL (2000) GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } 000556bc: 0000: 00002000 00188000 t0 write TPL1_TP_TEX_COUNT (2381) TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } 000556c4: 0000: 00002381 00000000 t0 write TPL1_TP_FS_TEX_COUNT (23a0) TPL1_TP_FS_TEX_COUNT: 0x3 000556cc: 0000: 000023a0 00000003 t0 write RB_ALPHA_CONTROL (20f8) RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } 000556d4: 0000: 000020f8 00000e00 t0 write RB_RENDER_COMPONENTS (20fb) RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } 000556dc: 0000: 000020fb 0000000f t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 000556e4: 0000: c0014300 00040000 00000000 t0 write VFD_CONTROL_0 (2200) VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } 000556f0: 0000: 00002200 000a0000 t0 write VFD_CONTROL_1 (2201) VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } 000556f8: 0000: 00002201 fc030000 t0 write SP_INSTR_CACHE_CTRL (22c1) SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } 00055700: 0000: 000022c1 000005c3 t0 write HLSQ_CONTROL_1_REG (23c1) HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } 00055708: 0000: 000023c1 fcfc0120 t0 write HLSQ_CONTROL_2_REG (23c2) HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 00055710: 0000: 000023c2 27f3f3f0 t0 write HLSQ_VS_CONTROL_REG (23c5) HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } 00055718: 0000: 000023c5 02010042 t0 write HLSQ_FS_CONTROL_REG (23c6) HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 1 } 00055720: 0000: 000023c6 0141423e t0 write HLSQ_HS_CONTROL_REG (23c7) HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00055728: 0000: 000023c7 00404200 t0 write HLSQ_DS_CONTROL_REG (23c8) HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00055730: 0000: 000023c8 00404200 t0 write HLSQ_GS_CONTROL_REG (23c9) HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } 00055738: 0000: 000023c9 00404200 t0 write HLSQ_CS_CONTROL_REG (23ca) HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } 00055740: 0000: 000023ca 00004200 t0 write SP_SP_CTRL_REG (22c0) SP_SP_CTRL_REG: { 0x60010 } 00055748: 0000: 000022c0 00060010 t0 write UNKNOWN_21E6 (21e6) UNKNOWN_21E6: 0x1 00055750: 0000: 000021e6 00000001 t0 write SP_VS_CTRL_REG0 (22c4) SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 00055758: 0000: 000022c4 00200c10 t0 write SP_VS_CTRL_REG1 (22c5) SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } 00055760: 0000: 000022c5 01000042 t0 write VPC_ATTR (2140) VPC_ATTR: { TOTALATTR = 8 | THRDASSIGN = 1 | ENABLE | 0x40000000 } 00055768: 0000: 00002140 42001008 t0 write VPC_PACK (2141) VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 8 | NUMNONPOSVSVAR = 6 } 00055770: 0000: 00002141 00060800 t0 write PC_PRIM_VTX_CNTL (21c4) PC_PRIM_VTX_CNTL: { VAROUT = 1 } 00055778: 0000: 000021c4 00000001 t0 write SP_VS_PARAM_REG (22c6) SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 2 } SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r1.w | B_COMPMASK = 0x3 } SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } UNKNOWN_22D7: 0xfcfc00 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 12 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 00055780: 0000: 001922c6 0020fc03 06071e03 00000000 00000000 00000000 00000000 00000000 * 000557c0: 0040: 00000000 00000000 00fcfc00 00000c08 00000000 00000000 00000000 00000000 * t0 write SP_VS_OBJ_OFFSET_REG (22e0) SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 000557ec: 0000: 000022e0 00000000 t0 write SP_VS_OBJ_START (22e1) SP_VS_OBJ_START: 0x1 000557f4: 0000: 000022e1 00000001 t0 write SP_VS_LENGTH_REG (22e5) SP_VS_LENGTH_REG: 2 000557fc: 0000: 000022e5 00000002 t3 opcode: CP_LOAD_STATE4 (30) (67 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } :2:0000:0000[56d81803x_20020003x] (sy)(ss)(nop3) shl.b r0.w, r0.w, 2 :1:0001:0004[20150000x_00000003x] cov.s32s16 hr0.x, r0.w :0:0002:0005[00000200x_00000000x] (rpt2)nop :1:0003:0008[201100f4x_00000000x] mova a0.x, hr0.x :0:0004:0009[00000500x_00000000x] (rpt5)nop :1:0005:0015[20154003x_00000c20x] mov.s32s32 r0.w, c :1:0006:0016[20154004x_00000c21x] mov.s32s32 r1.x, c :1:0007:0017[20154007x_00000c22x] mov.s32s32 r1.w, c :1:0008:0018[20156008x_00000c23x] (ul)mov.s32s32 r2.x, c :1:0009:0019[20554005x_00000000x] mov.s32s32 r1.y, 0 :1:0010:0020[20554006x_3f800000x] mov.s32s32 r1.z, 1065353216 :0:0011:0021[03000000x_00000000x] end :2:0012:0022[46f00009x_20050000x] shr.b r2.y, r0.x, 5 :2:0013:0023[4398000ax_201f0000x] (nop2) and.b r2.z, r0.x, 31 :2:0014:0026[43980809x_201f0009x] (nop3) and.b r2.y, r2.y, 31 :2:0015:0030[46100809x_20180009x] (nop1) mul.u24 r2.y, r2.y, 24 :3:0016:0032[62050009x_00091014x] mad.u24 r2.y, c5.x, r2.z, r2.y :0:0017:0033[00000500x_00000000x] (rpt5)nop :6:0018:0039[c2c61300x_04800006x] stlw.u32 l[r2.y], r0.w, 4 :6:0019:0040[c2c61310x_0280000ex] stlw.u32 l[r2.y+16], r1.w, 2 :0:0020:0041[04800000x_00000000x] chmask :0:0021:0042[05000000x_00000000x] chsh Stats: - shaderdb: 43 instr, 24 nops, 19 non-nops, 7 mov, 1 cov - shaderdb: 0 last-baryf, 0 half, 3 full, 5 constlen - shaderdb: 27 cat0, 8 cat1, 5 cat2, 1 cat3, 0 cat4, 0 cat5, 2 cat6, 0 cat7 - shaderdb: 0 sstall, 1 (ss), 1 (sy) 00055804: 0000: c0413000 00a00000 00000000 20020003 56d81803 00000003 20150000 00000000 00055824: 0020: 00000200 00000000 201100f4 00000000 00000500 00000c20 20154003 00000c21 00055844: 0040: 20154004 00000c22 20154007 00000c23 20156008 00000000 20554005 3f800000 00055864: 0060: 20554006 00000000 03000000 20050000 46f00009 201f0000 4398000a 201f0009 00055884: 0080: 43980809 20180009 46100809 00091014 62050009 00000000 00000500 04800006 000558a4: 00a0: c2c61300 0280000e c2c61310 00000000 04800000 00000000 05000000 00000000 * t0 write HLSQ_CONTROL_3_REG (23c3) HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } 00055910: 0000: 000023c3 fcfcfc00 t0 write HLSQ_CONTROL_4_REG (23c4) HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } 00055918: 0000: 000023c4 00fcfcfc t0 write SP_FS_CTRL_REG0 (22e8) SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 0 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE | PIXLODENABLE } SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 } 00055920: 0000: 000122e8 00700402 8010003e t0 write SP_FS_OBJ_OFFSET_REG (22ea) SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 } 0005592c: 0000: 000022ea 40420000 t0 write SP_FS_OBJ_START (22eb) SP_FS_OBJ_START: 0x1 00055934: 0000: 000022eb 00000001 t0 write SP_FS_LENGTH_REG (22ef) SP_FS_LENGTH_REG: 1 0005593c: 0000: 000022ef 00000001 t0 write SP_FS_OUTPUT_REG (22f0) SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r0.x | SAMPLEMASK_REGID = r0.x } 00055944: 0000: 000022f0 00000001 t0 write VPC_VARYING_INTERP[0].MODE (2142) VPC_VARYING_INTERP[0].MODE: 0xe000 0005594c: 0000: 00002142 0000e000 t0 write RB_FS_OUTPUT_REG (2100) RB_FS_OUTPUT_REG: { MRT = 1 } 00055954: 0000: 00002100 00000001 t3 opcode: CP_LOAD_STATE4 (30) (35 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 1 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } :2:0000:0000[57309902x_00002004x] (sy)(ss)(rpt1)bary.f (ei)r0.z, (r)4, r0.x :0:0001:0002[00000500x_00000000x] (rpt5)nop :5:0002:0008[a0c01f00x_00000005x] sam (f32)(xyzw)r0.x, r0.z, s#0, t#0 :0:0003:0009[03000000x_00000000x] end :0:0004:0010[00000000x_00000000x] nop :0:0005:0011[00000000x_00000000x] nop :0:0006:0012[00000000x_00000000x] nop :0:0007:0013[00000000x_00000000x] nop Stats: - shaderdb: 14 instr, 10 nops, 4 non-nops, 0 mov, 0 cov - shaderdb: 0 last-baryf, 0 half, 1 full, 0 constlen - shaderdb: 11 cat0, 0 cat1, 2 cat2, 0 cat3, 0 cat4, 1 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 1 (ss), 1 (sy) 0005595c: 0000: c0213000 00700000 00000000 00002004 57309902 00000000 00000500 00000005 0005597c: 0020: a0c01f00 00000000 03000000 00000000 00000000 00000000 00000000 00000000 * t0 write RB_FS_OUTPUT (20f9) RB_FS_OUTPUT: { ENABLE_BLEND = 0 | SAMPLE_MASK = 0xffff } 000559e8: 0000: 000020f9 ffff0000 t0 write RB_MRT[0].CONTROL (20a4) RB_MRT[0].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0xf } 000559f0: 0000: 000020a4 0f000000 t0 write RB_MRT[0x1].CONTROL (20a9) RB_MRT[0x1].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0xf } 000559f8: 0000: 000020a9 0f000000 t0 write RB_MRT[0].BLEND_CONTROL (20a8) RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } 00055a00: 0000: 000020a8 00000000 t3 opcode: CP_LOAD_STATE4 (30) (5 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_TEX | NUM_UNIT = 1 } { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } { XY_MAG = A4XX_TEX_NEAREST | XY_MIN = A4XX_TEX_NEAREST | WRAP_S = A4XX_TEX_CLAMP_TO_EDGE | WRAP_T = A4XX_TEX_CLAMP_TO_EDGE | WRAP_R = A4XX_TEX_CLAMP_TO_EDGE | ANISO = A4XX_TEX_ANISO_1 | LOD_BIAS = 0.000000 | 0x60000 } { COMPARE_FUNC = FUNC_LEQUAL | UNNORM_COORDS | MIPFILTER_LINEAR_FAR | MAX_LOD = 0.000000 | MIN_LOD = 0.000000 | 0x1 } 00055a14: 0000: 00060920 00000067 00055a08: 0000: c0033000 00500000 00000000 00060920 00000067 t0 write GRAS_SC_CONTROL (207b) GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 0 | RASTER_MODE = 0 } 00055a1c: 0000: 0000207b 00000000 t0 write RB_MSAA_CONTROL (20a2) RB_MSAA_CONTROL: { SAMPLES = 0 } 00055a24: 0000: 000020a2 00000000 t0 write RB_RENDER_CONTROL (20a1) RB_RENDER_CONTROL: { 0 } 00055a2c: 0000: 000020a1 00000000 t0 write 0x2382 (2382) 0x2382: 00000000 00055a34: 0000: 00002382 00000000 t0 write RB_DEPTH_CONTROL (2101) RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } 00055a3c: 0000: 00002101 00000000 t0 write GRAS_ALPHA_CONTROL (2073) GRAS_ALPHA_CONTROL: { 0 } 00055a44: 0000: 00002073 00000000 t0 write RB_STENCIL_CONTROL (2106) RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } 00055a4c: 0000: 00002106 00000000 t0 write SP_FS_MRT[0].REG (22f1) SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = RB4_R8G8B8A8_UNORM } 00055a54: 0000: 000022f1 0001a000 t0 write RB_MRT[0].BUF_INFO (20a5) RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB4_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE4_3 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 256 } RB_MRT[0].BASE: 0x166000 RB_MRT[0].CONTROL3: { STRIDE = 0 } 00055a5c: 0000: 000220a5 000400da 00166000 00000000 t3 opcode: CP_LOAD_STATE4 (30) (11 dwords) { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_TEX | NUM_UNIT = 1 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } { TILED | SWIZ_X = A4XX_TEX_X | SWIZ_Y = A4XX_TEX_Y | SWIZ_Z = A4XX_TEX_Z | SWIZ_W = A4XX_TEX_W | MIPLVLS = 0 | FMT = TFMT4_8_8_8_8_UNORM | TYPE = A4XX_TEX_2D | 0x2 } { HEIGHT = 64 | WIDTH = 64 } { PITCHALIGN = 0 | PITCH = 256 | SWAP = WZYX } { LAYERSZ = 0 | DEPTH = 1 | 0x20000 } { LAYERSZ = 4096 | BASE = 0x4f000 } { 5 = 0 } { 6 = 0 } { 7 = 0 } 00055a78: 0000: 27006883 00200040 00020000 00060000 0004f001 00000000 00000000 00000000 00055a6c: 0000: c0093000 00500000 00000001 27006883 00200040 00020000 00060000 0004f001 * t0 write VPC_VARYING_PS_REPL[0].MODE (214a) VPC_VARYING_PS_REPL[0].MODE: 0x99999999 00055a98: 0000: 0000214a 99999999 t0 write GRAS_SC_SCREEN_SCISSOR_TL (207c) GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } 00055aa0: 0000: 0001207c 00000000 003f003f t0 write GRAS_SC_WINDOW_SCISSOR_BR (209c) GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 00055aac: 0000: 0001209c 003f003f 00000000 t0 write RB_FRAME_BUFFER_DIMENSION (0ce0) RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } 00055ab8: 0000: 00000ce0 00400040 t0 write 0xce1 (0ce1) 0xce1: 00000000 00055ac0: 0000: 00000ce1 00000000 t0 write RB_RENDER_CONTROL2 (20a3) RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 | IJ_PERSP_PIXEL } 00055ac8: 0000: 000020a3 00001000 t0 write RB_MODE_CONTROL (20a0) RB_MODE_CONTROL: { WIDTH = 0 | HEIGHT = 0 | 0xc00000 } 00055ad0: 0000: 000020a0 00c00000 t3 opcode: CP_LOAD_STATE4 (30) (11 dwords) { DST_OFF = 8 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 2 } { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } 00055ae4: 0.000000 0.000000 0.000000 0.000000 64.000000 64.000000 64.000000 64.000000 00055ae4: 0000: 00000000 00000000 00000000 00000000 42800000 42800000 42800000 42800000 00055ad8: 0000: c0093000 00a00008 00000001 00000000 00000000 00000000 00000000 42800000 00055af8: 0020: 42800000 42800000 42800000 t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) { PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS | 0x80000 } { NUM_INSTANCES = 1 } { NUM_INDICES = 2 } draw[99] register values + 00000004 UNKNOWN_0CC5: 0x4 + 00000000 UNKNOWN_0CC6: 0 + 00400040 RB_FRAME_BUFFER_DIMENSION: { WIDTH = 64 | HEIGHT = 64 } + 00000000 0xce1: 00000000 + 00000002 HLSQ_MODE_CONTROL: 0x2 + 00000000 UNKNOWN_0E42: 0 + 00000004 SP_MODE_CONTROL: 0x4 + 00000068 TPL1_TP_MODE_CONTROL: 0x68 + 00188000 GRAS_CL_CLIP_CNTL: { CLIP_DISABLE | 0x180000 } + 00000000 UNKNOWN_2001: 0 + 00000001 GRAS_CNTL: { IJ_PERSP } !+ 00000000 GRAS_ALPHA_CONTROL: { 0 } + 00000000 GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } !+ 00000000 GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 0 | RASTER_MODE = 0 } + 00000000 GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } + 003f003f GRAS_SC_SCREEN_SCISSOR_BR: { X = 63 | Y = 63 } + 003f003f GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } + 00000000 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } !+ 00c00000 RB_MODE_CONTROL: { WIDTH = 0 | HEIGHT = 0 | 0xc00000 } !+ 00000000 RB_RENDER_CONTROL: { 0 } !+ 00000000 RB_MSAA_CONTROL: { SAMPLES = 0 } !+ 00001000 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 | IJ_PERSP_PIXEL } !+ 0f000000 RB_MRT[0].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0xf } !+ 000400da RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB4_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE4_3 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 256 } !+ 00166000 RB_MRT[0].BASE: 0x166000 !+ 00000000 RB_MRT[0].CONTROL3: { STRIDE = 0 } + 00000000 RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } + 0f000000 RB_MRT[0x1].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0xf } + 00000e00 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } !+ ffff0000 RB_FS_OUTPUT: { ENABLE_BLEND = 0 | SAMPLE_MASK = 0xffff } + 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } + 00000001 RB_FS_OUTPUT_REG: { MRT = 1 } + 00000000 RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } + 00000000 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } !+ 42001008 VPC_ATTR: { TOTALATTR = 8 | THRDASSIGN = 1 | ENABLE | 0x40000000 } !+ 00060800 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 8 | NUMNONPOSVSVAR = 6 } !+ 0000e000 VPC_VARYING_INTERP[0].MODE: 0xe000 !+ 99999999 VPC_VARYING_PS_REPL[0].MODE: 0x99999999 + 00000000 UNKNOWN_2152: 0 + 00000000 UNKNOWN_2153: 0 + 00000000 UNKNOWN_2154: 0 + 00000000 UNKNOWN_2155: 0 + 00000000 UNKNOWN_2156: 0 + 0000001d UNKNOWN_21C3: 0x1d + 00000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 } + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + 00000000 PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } + 00000001 UNKNOWN_21E6: 0x1 + 000a0000 VFD_CONTROL_0: { TOTALATTRTOVS = 0 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 0 | STRMFETCHINSTRCNT = 0 | 0xa0000 } + fc030000 VFD_CONTROL_1: { MAXSTORAGE = 0 | REGID4VTX = r0.w | REGID4INST = r63.x } + fcfcfcfc VFD_CONTROL_2: 0xfcfcfcfc + fcfcfc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x } + 0000fcfc VFD_CONTROL_4: 0xfcfc + 00000000 VFD_INDEX_OFFSET: 0 + 00000000 UNKNOWN_2209: 0 + 00060010 SP_SP_CTRL_REG: { 0x60010 } + 000005c3 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x43 } + 00200c10 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } + 01000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 1 } !+ 0020fc03 SP_VS_PARAM_REG: { POSREGID = r0.w | PSIZEREGID = r63.x | TOTALVSOUTVAR = 2 } !+ 06071e03 SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r1.w | B_COMPMASK = 0x3 } + 00000000 SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00fcfc00 UNKNOWN_22D7: 0xfcfc00 !+ 00000c08 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 12 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } + 00000001 SP_VS_OBJ_START: 0x1 + 00000002 SP_VS_LENGTH_REG: 2 !+ 00700402 SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 0 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE | PIXLODENABLE } !+ 8010003e SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 } !+ 40420000 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 } !+ 00000001 SP_FS_OBJ_START: 0x1 + 00000001 SP_FS_LENGTH_REG: 1 !+ 00000001 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r0.x | SAMPLEMASK_REGID = r0.x } !+ 0001a000 SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = RB4_R8G8B8A8_UNORM } + 00000000 TPL1_TP_TEX_COUNT: { VS = 0 | HS = 0 | DS = 0 | GS = 0 } !+ 00000000 0x2382: 00000000 + 00000003 TPL1_TP_FS_TEX_COUNT: 0x3 + 080004f0 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | RESERVED2 | CONSTMODE = 1 | 0xa0 } + fcfc0120 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x | 0x20 } + 27f3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 9 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } + fcfcfc00 HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } !+ 00fcfcfc HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } + 02010042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | ENABLED | SHADEROBJOFFSET = 0 | INSTRLENGTH = 2 } !+ 0141423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | ENABLED | SHADEROBJOFFSET = 32 | INSTRLENGTH = 1 } + 00404200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00404200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 32 | INSTRLENGTH = 0 } + 00004200 HLSQ_CS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 0 } + 00000007 HLSQ_UPDATE_CONTROL: 0x7 00055b04: 0000: c0023800 00080888 00000001 00000002 t3 opcode: CP_EVENT_WRITE (46) (2 dwords) { EVENT = CACHE_FLUSH } event CACHE_FLUSH 00055b14: 0000: c0004600 00000006 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 00055b1c: 0000: c0002600 00000000 t0 write UNKNOWN_0CC6 (0cc6) UNKNOWN_0CC6: 0x8000012 00055b24: 0000: 00000cc6 08000012 00173000: 0000: c0013f00 000555d8 00000155 t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } { ADDR_LO = 0 } 0017300c: 0000: c0014300 00040000 00000000 t3 opcode: (null) (1d) (2 dwords) 00173018: 0000: c0001d00 00000000 ############################################################ vertices: 0 ############################################################ cmdstream: 2 dwords t3 opcode: CP_NOP (10) (2 dwords) 0016b000: 0000: c0001000 00000000 ############################################################ vertices: 0 cmd: perfcounter_put: groupid=27, countable=0 ############################################################ cmdstream: 2 dwords t3 opcode: CP_NOP (10) (2 dwords) 00208000: 0000: c0001000 00000000 ############################################################ vertices: 0 cmd: perfcounter_put: groupid=27, countable=0