Results for texturing/gen-compressed-teximage

Overview

Status: warn
Result: warn

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Details

Detail	Value
returncode	0
time	0.303216218948
errors_ignored	Mesa: CPU vendor: GenuineIntel Mesa: CPU name: Intel(R) Pentium(R) 4 CPU 3.00GHz Mesa: Mesa 7.8-devel DEBUG build Jan 22 2010 09:05:14 Mesa warning: software DXTn compression/decompression available Mesa: MMX cpu detected. Mesa: SSE cpu detected. Mesa: Not testing OS support for SSE, leaving enabled.
errors	dxt5 tex width 128 tex height 128 dstRowStride 512 dxt5 tex width 64 tex height 64 dstRowStride 256 dxt5 tex width 32 tex height 32 dstRowStride 128 dxt5 tex width 16 tex height 16 dstRowStride 64 dxt5 tex width 8 tex height 8 dstRowStride 32 dxt5 tex width 4 tex height 4 dstRowStride 16 dxt5 tex width 2 tex height 2 dstRowStride 16 dxt5 tex width 1 tex height 1 dstRowStride 16 dxt5 tex width 128 tex height 128 dstRowStride 512 dxt5 tex width 64 tex height 64 dstRowStride 256 dxt5 tex width 32 tex height 32 dstRowStride 128 dxt5 tex width 16 tex height 16 dstRowStride 64 dxt5 tex width 8 tex height 8 dstRowStride 32 dxt5 tex width 4 tex height 4 dstRowStride 32 dxt5 tex width 2 tex height 2 dstRowStride 32 dxt5 tex width 1 tex height 1 dstRowStride 32 dxt5 tex width 128 tex height 128 dstRowStride 512 dxt5 tex width 64 tex height 64 dstRowStride 256 dxt5 tex width 32 tex height 32 dstRowStride 128 dxt5 tex width 16 tex height 16 dstRowStride 64 dxt5 tex width 8 tex height 8 dstRowStride 32 dxt5 tex width 4 tex height 4 dstRowStride 16 dxt5 tex width 2 tex height 2 dstRowStride 16 dxt5 tex width 1 tex height 1 dstRowStride 16
info	Returncode: 0 Errors: Mesa: CPU vendor: GenuineIntel Mesa: CPU name: Intel(R) Pentium(R) 4 CPU 3.00GHz Mesa: Mesa 7.8-devel DEBUG build Jan 22 2010 09:05:14 Mesa warning: software DXTn compression/decompression available Mesa: MMX cpu detected. Mesa: SSE cpu detected. Mesa: Not testing OS support for SSE, leaving enabled. dxt5 tex width 128 tex height 128 dstRowStride 512 dxt5 tex width 64 tex height 64 dstRowStride 256 dxt5 tex width 32 tex height 32 dstRowStride 128 dxt5 tex width 16 tex height 16 dstRowStride 64 dxt5 tex width 8 tex height 8 dstRowStride 32 dxt5 tex width 4 tex height 4 dstRowStride 16 dxt5 tex width 2 tex height 2 dstRowStride 16 dxt5 tex width 1 tex height 1 dstRowStride 16 dxt5 tex width 128 tex height 128 dstRowStride 512 dxt5 tex width 64 tex height 64 dstRowStride 256 dxt5 tex width 32 tex height 32 dstRowStride 128 dxt5 tex width 16 tex height 16 dstRowStride 64 dxt5 tex width 8 tex height 8 dstRowStride 32 dxt5 tex width 4 tex height 4 dstRowStride 32 dxt5 tex width 2 tex height 2 dstRowStride 32 dxt5 tex width 1 tex height 1 dstRowStride 32 dxt5 tex width 128 tex height 128 dstRowStride 512 dxt5 tex width 64 tex height 64 dstRowStride 256 dxt5 tex width 32 tex height 32 dstRowStride 128 dxt5 tex width 16 tex height 16 dstRowStride 64 dxt5 tex width 8 tex height 8 dstRowStride 32 dxt5 tex width 4 tex height 4 dstRowStride 16 dxt5 tex width 2 tex height 2 dstRowStride 16 dxt5 tex width 1 tex height 1 dstRowStride 16 Output:

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