From 798f4a36b84a5e66fb4861f09aabe84ac9b26801 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 3 Feb 2010 22:45:48 -0500 Subject: [PATCH] r600: curb excessive cache flushing Let the drm do the flushing when we emit the fence. Gives a nice performance boost. --- src/mesa/drivers/dri/r600/r600_blit.c | 4 ++-- src/mesa/drivers/dri/r600/r700_render.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/mesa/drivers/dri/r600/r600_blit.c b/src/mesa/drivers/dri/r600/r600_blit.c index d7cd59a..8ac06e6 100644 --- a/src/mesa/drivers/dri/r600/r600_blit.c +++ b/src/mesa/drivers/dri/r600/r600_blit.c @@ -1605,7 +1605,7 @@ unsigned r600_blit(GLcontext *ctx, /* Flush is needed to make sure that source buffer has correct data */ radeonFlush(ctx); - rcommonEnsureCmdBufSpace(&context->radeon, 304, __FUNCTION__); + rcommonEnsureCmdBufSpace(&context->radeon, 299, __FUNCTION__); /* load shaders */ load_shaders(context->radeon.glCtx); @@ -1652,7 +1652,7 @@ unsigned r600_blit(GLcontext *ctx, CB_ACTION_ENA_bit | (1 << (id + 6))); /* 5 */ - r700WaitForIdleClean(context); + //r700WaitForIdleClean(context); radeonFlush(ctx); diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index 96c12ce..81ed2f0 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -116,7 +116,7 @@ void r700Start3D(context_t *context) COMMIT_BATCH(); - r700WaitForIdleClean(context); + //r700WaitForIdleClean(context); } GLboolean r700SyncSurf(context_t *context, @@ -934,7 +934,7 @@ static GLboolean r700TryDrawPrims(GLcontext *ctx, radeon_debug_remove_indent(); /* Flush render op cached for last several quads. */ - r700WaitForIdleClean(context); + //r700WaitForIdleClean(context); rrb = radeon_get_colorbuffer(&context->radeon); if (rrb && rrb->bo) -- 1.5.6.3