From 24f4166e95de2f57173b6ba8280ce4917f06a491 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 3 Feb 2010 22:44:09 -0500 Subject: [PATCH] r600: curb excess gpu cache flushing Let the drm flush when the fence is emitted. Gives a nice performance boost. --- src/r6xx_accel.c | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/r6xx_accel.c b/src/r6xx_accel.c index 7a225e5..0034af0 100644 --- a/src/r6xx_accel.c +++ b/src/r6xx_accel.c @@ -159,7 +159,7 @@ start_3d(ScrnInfoPtr pScrn, drmBufPtr ib) E32(ib, 0x80000000); END_BATCH(); - wait_3d_idle_clean (pScrn, ib); + //wait_3d_idle_clean (pScrn, ib); } /* @@ -1279,14 +1279,14 @@ void r600_finish_op(ScrnInfoPtr pScrn, int vtx_size) draw_auto(pScrn, accel_state->ib, &draw_conf); - wait_3d_idle_clean(pScrn, accel_state->ib); + //wait_3d_idle_clean(pScrn, accel_state->ib); /* sync dst surface */ cp_set_surface_sync(pScrn, accel_state->ib, (CB_ACTION_ENA_bit | CB0_DEST_BASE_ENA_bit), accel_state->dst_size, accel_state->dst_mc_addr, accel_state->dst_bo, RADEON_GEM_DOMAIN_VRAM, 0); - wait_3d_idle_clean(pScrn, accel_state->ib); + //wait_3d_idle_clean(pScrn, accel_state->ib); accel_state->vb_start_op = -1; accel_state->ib_reset_op = 0; -- 1.5.6.3