From 784feded2b1fb94df5b2d810f286462719c7f5f1 Mon Sep 17 00:00:00 2001
From: Pierre-Eric Pelloux-Prayer <pelloux@gmail.com>
Date: Wed, 3 Aug 2011 11:03:28 -0400
Subject: [PATCH 3/5] r600g: check bo size before enabling HiZ

This will avoid the risk of breaking command stream
if HiZ is enabled for a depth buffer without extra
htile space.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 src/gallium/drivers/r600/r600_state.c |   12 +++++++-----
 1 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index b18d73e..86c67e5 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -1557,11 +1557,13 @@ static void r600_db(struct r600_pipe_context *rctx, struct r600_pipe_state *rsta
 
 	if (1) {
 		htile_offset = ((surf->aligned_height * rtex->pitch_in_bytes[level]) + 255) & ~255;
-		r600_pipe_state_add_reg(rstate, R_028014_DB_HTILE_DATA_BASE,
-					(offset + htile_offset) >> 8, 0xFFFFFFFF, rbuffer->bo);
-		r600_pipe_state_add_reg(rstate, R_028D24_DB_HTILE_SURFACE,
-					r600_htile_settings(rctx, state->zsbuf->texture), 0xFFFFFFFF, NULL);
-		db_depth_info |= S_028010_TILE_SURFACE_ENABLE(1);
+		if (offset + htile_offset < r600_bo_size(rbuffer->bo)) {
+			r600_pipe_state_add_reg(rstate, R_028014_DB_HTILE_DATA_BASE,
+						(offset + htile_offset) >> 8, 0xFFFFFFFF, rbuffer->bo);
+			r600_pipe_state_add_reg(rstate, R_028D24_DB_HTILE_SURFACE,
+						r600_htile_settings(rctx, state->zsbuf->texture), 0xFFFFFFFF, NULL);
+			db_depth_info |= S_028010_TILE_SURFACE_ENABLE(1);
+		}
 	}
 
 	r600_pipe_state_add_reg(rstate, R_02800C_DB_DEPTH_BASE,
-- 
1.7.1.1

