From 92575a91ff1b55f9d0a6488f73204e0ee98c9166 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 16 Jun 2011 13:03:18 -0400 Subject: [PATCH] dri2: add support for htile buffers For R6xx+ for HiZ/HiS and fast Z/S support. The htile buffer needs to be available for the life of the Z/S buffer, so allocate it here like we do for stencil on evergreen. Signed-off-by: Alex Deucher --- src/radeon_dri2.c | 28 ++++++++++++++++++---------- 1 files changed, 18 insertions(+), 10 deletions(-) diff --git a/src/radeon_dri2.c b/src/radeon_dri2.c index 46573a7..268b48d 100644 --- a/src/radeon_dri2.c +++ b/src/radeon_dri2.c @@ -128,8 +128,7 @@ radeon_dri2_create_buffers(DrawablePtr drawable, * fallbacks in mesa still has issues on some configurations */ flags = RADEON_CREATE_PIXMAP_TILING_MICRO; - if (info->ChipFamily >= CHIP_FAMILY_CEDAR) - need_enlarge = 1; + need_enlarge = 1; } else flags = RADEON_CREATE_PIXMAP_TILING_MACRO | RADEON_CREATE_PIXMAP_TILING_MICRO; break; @@ -157,7 +156,7 @@ radeon_dri2_create_buffers(DrawablePtr drawable, if (need_enlarge) { /* evergreen uses separate allocations for depth and stencil * so we make an extra large depth buffer to cover stencil - * as well. + * as well. Also allocate htile space for r6xx+. */ unsigned aligned_width = drawable->width; unsigned width_align = drmmode_get_pitch_align(pScrn, drawable->depth / 8, tiling); @@ -174,8 +173,13 @@ radeon_dri2_create_buffers(DrawablePtr drawable, aligned_height = RADEON_ALIGN(drawable->height, height_align); size = pitch_bytes * aligned_height; size = RADEON_ALIGN(size, base_align); - /* add additional size for stencil */ - size += aligned_width * aligned_height; + /* add additional size for stencil on eg+ */ + if (info->ChipFamily >= CHIP_FAMILY_CEDAR) { + size += aligned_width * aligned_height; + size = RADEON_ALIGN(size, base_align); + } + /* htile */ + size += ((aligned_width * aligned_height) / (4 * 4)) * 4; aligned_height = RADEON_ALIGN(size / pitch_bytes, height_align); pixmap = (*pScreen->CreatePixmap)(pScreen, @@ -280,8 +284,7 @@ radeon_dri2_create_buffer(DrawablePtr drawable, */ if (info->ChipFamily >= CHIP_FAMILY_R600) { flags = RADEON_CREATE_PIXMAP_TILING_MICRO; - if (info->ChipFamily >= CHIP_FAMILY_CEDAR) - need_enlarge = 1; + need_enlarge = 1; } else flags = RADEON_CREATE_PIXMAP_TILING_MACRO | RADEON_CREATE_PIXMAP_TILING_MICRO; break; @@ -309,7 +312,7 @@ radeon_dri2_create_buffer(DrawablePtr drawable, if (need_enlarge) { /* evergreen uses separate allocations for depth and stencil * so we make an extra large depth buffer to cover stencil - * as well. + * as well. Also allocate htile space for r6xx+. */ int depth = (format != 0) ? format : drawable->depth; unsigned aligned_width = drawable->width; @@ -327,8 +330,13 @@ radeon_dri2_create_buffer(DrawablePtr drawable, aligned_height = RADEON_ALIGN(drawable->height, height_align); size = pitch_bytes * aligned_height; size = RADEON_ALIGN(size, base_align); - /* add additional size for stencil */ - size += aligned_width * aligned_height; + /* add additional size for stencil on eg+ */ + if (info->ChipFamily >= CHIP_FAMILY_CEDAR) { + size += aligned_width * aligned_height; + size = RADEON_ALIGN(size, base_align); + } + /* htile */ + size += ((aligned_width * aligned_height) / (4 * 4)) * 4; aligned_height = RADEON_ALIGN(size / pitch_bytes, height_align); pixmap = (*pScreen->CreatePixmap)(pScreen, -- 1.7.1.1