19:15 Lynne: "Any member of a push constant block that is declared as an array must only be accessed with dynamically uniform indices."
19:16 Lynne: so layout(push_constant) uniform PushConstants { int test[4]; } can only be addressed via a for loop, rather than test[gl_InstanceIndex]?
19:18 Lynne: the validation layer doesn't catch that, so I'm assuming this is some theoretical problem some antique byzantian hardware had at some point 9 years ago
19:34 dj-death: Lynne: the NIR divergence analysis pass takes this seriously
19:35 Lynne: I see
19:35 Lynne: what is the source of this limitation? its only memory at the end of the day
19:36 dj-death: I bet it helps a bunch of HW with scalar register files
19:37 dj-death: I don't really know the other GPU's push constant path, for Intel this restriction doesn't matter much
19:37 dj-death: apart from the NIR assumption which will break a bunch of stuff
19:37 dj-death: if you try test[gl_InstanceIndex]
19:40 HdkR: You usually want it to be dynamically uniform on NVIDIA hardware anyway, otherwise performance falls off a cliff.
19:41 Lynne: afaik on AMD it just gets inlined into the shader itself
19:41 HdkR: Same on NVIDIA, turns in to an LDC (or equivalent) instruction. If the UBO offset is a constant then it can get inlined in to the instruction.
19:43 HdkR: Unless you mean like the UBO constant value itself gets compiled in to to the shader. Which...PS3 says hello I guess.
19:49 HdkR: I do love how older harder gets really squirrely with UBOs, since that era cared more about raw uniforms more. :D
19:51 HdkR: older hardware*
21:22 alyssa: squirrelly is such a lovely word
22:03 HdkR: alyssa: You know how much I love silly words.
22:52 mareko: load_push_constant is indeed always uniform, the limitation certainly doesn't come from AMD
22:54 mareko: unless it was meant to be in user SGPRs, which are indeed non-indexable non-uniformly