This is a DRAM tuning/overclocking stability report for various Allwinner A10/A13/A20 based devices. It can be automatically generated by the tools from https://github.com/ssvb/a10-meminfo. Here we primarily focus on finding optimal dram_tpr3 values, tuned individually for every sunxi device. Currently these values need to be hardcoded into the sources of the u-boot-sunxi bootloader. The dram_tpr3 parameter is just a hexadecimal number, composed of the following bit-fields:

• bits [22:20] - MFWDLY of the command lane
• bits [18:16] - MFBDLY of the command lane
• bits [15:12] - SDPHASE of the byte lane 3
• bits [11:8] - SDPHASE of the byte lane 2
• bits [7:4] - SDPHASE of the byte lane 1
• bits [3:0] - SDPHASE of the byte lane 0

Results interpretation:

• The shades of pure RED mean hardware deadlocks. Too many of them sometimes indicate insufficient dcdc3 voltage, which is configured as dcdc3_vol variable in fex files.
• The shades of RED/ORANGE/YELLOW mean data corruption on read operations. This may be attributed to other reasons. Including, but not limited to phase misalignment between different byte lanes. See the Figure 6 from Altera - Utilizing Leveling Techniques in DDR3 SDRAM Memory Interfaces as a reasonaby good illustration.
• The shades of RED/PURPLE/MAGENTA mean data corruption on write operations.
• LIGHTGREEN - no problems detected during only a few minutes of running lima-memtester.
• DARKGREEN - no problems detected during up to roughly half an hour run of lima-memtester (these extra 'hardening' tests are performed after all the preliminary data has been collected). But even these dram_tpr3 values still need thorough verification by a much longer run of lima-memtester (8-10 hours is reasonable) and other stress tests.
• Some digits of the dram_tpr3 values in the table(s) below may be shown using bold font. This indicates data corruption problem detected in the corresponding byte lane(s).

Mele A2000

Mele A2000