This is a DRAM tuning/overclocking stability report for various Allwinner A10/A13/A20 based devices.It can be automatically generated by the tools from https://github.com/ssvb/a10-meminfo. Here we primarily focus on finding optimal dram_tpr3 values, tuned individually for every sunxi device. Currently these values need to be hardcoded into the sources of the u-boot-sunxi bootloader. The dram_tpr3 parameter is just a hexadecimal number with the following bit fields:
Results interpretation:
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| Lane phase adjustments: [0, 0, 0, 0] Error statistics from memtester: [solidbits=17, bitflip=13, bitspread=11] Best number of successful memtester runs, which span over 1 columns (3-3): 60 Best number of successful memtester runs, which span over 2 columns (2-3): 96 Best number of successful memtester runs, which span over 3 columns (1-3): 122 Best number of successful memtester runs, which span over 4 columns (1-4): 131 Best number of successful memtester runs, which span over 5 columns (1-5): 131 Best number of successful memtester runs, which span over 6 columns (0-5): 131 Errors per lane: [20, 14, 27, 22]. Lane 1 is the most noisy/problematic. Errors from the lane 0 are 63.6% eclipsed by the worst lane 1. Errors from the lane 2 are 100.0% eclipsed by the worst lane 1. Errors from the lane 3 are 70.0% eclipsed by the worst lane 1. |
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| Lane phase adjustments: [0, 0, 0, 0] Error statistics from memtester: [solidbits=17, bitspread=12, bitflip=4] Best number of successful memtester runs, which span over 1 columns (3-3): 150 Best number of successful memtester runs, which span over 2 columns (2-3): 300 Best number of successful memtester runs, which span over 3 columns (1-3): 450 Best number of successful memtester runs, which span over 4 columns (1-4): 480 Best number of successful memtester runs, which span over 5 columns (0-4): 482 Best number of successful memtester runs, which span over 6 columns (0-5): 482 Errors per lane: [8, 0, 17, 8]. Lane 1 is the most noisy/problematic. Errors from the lane 0 are not intersecting with the errors from the worst line 1. Errors from the lane 3 are not intersecting with the errors from the worst line 1. |
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| Lane phase adjustments: [0, 0, 0, 0] Error statistics from memtester: [bitspread=10, solidbits=5, bitflip=4] Best number of successful memtester runs, which span over 1 columns (1-1): 99 Best number of successful memtester runs, which span over 2 columns (0-1): 198 Best number of successful memtester runs, which span over 3 columns (0-2): 275 Best number of successful memtester runs, which span over 4 columns (0-3): 312 Best number of successful memtester runs, which span over 5 columns (0-4): 312 Best number of successful memtester runs, which span over 6 columns (0-5): 312 Errors per lane: [5, 7, 6, 16]. Lane 0 is the most noisy/problematic. Errors from the lane 1 are 100.0% eclipsed by the worst lane 0. Errors from the lane 2 are 57.1% eclipsed by the worst lane 0. Errors from the lane 3 are 80.0% eclipsed by the worst lane 0. |
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| Lane phase adjustments: [0, 0, 0, 0] Error statistics from memtester: [bitspread=10, solidbits=7, bitflip=4] Best number of successful memtester runs, which span over 1 columns (2-2): 115 Best number of successful memtester runs, which span over 2 columns (1-2): 223 Best number of successful memtester runs, which span over 3 columns (0-2): 336 Best number of successful memtester runs, which span over 4 columns (0-3): 424 Best number of successful memtester runs, which span over 5 columns (0-4): 441 Best number of successful memtester runs, which span over 6 columns (0-5): 441 Errors per lane: [8, 6, 4, 16]. Lane 0 is the most noisy/problematic. Errors from the lane 1 are 100.0% eclipsed by the worst lane 0. Errors from the lane 2 are 50.0% eclipsed by the worst lane 0. Errors from the lane 3 are 37.5% eclipsed by the worst lane 0. |
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| Lane phase adjustments: [0, 0, 0, 0] Error statistics from memtester: [solidbits=8, bitspread=3, bitflip=1] Best number of successful memtester runs, which span over 1 columns (0-0): 51 Best number of successful memtester runs, which span over 2 columns (0-1): 77 Best number of successful memtester runs, which span over 3 columns (0-2): 77 Best number of successful memtester runs, which span over 4 columns (0-3): 79 Best number of successful memtester runs, which span over 5 columns (0-4): 79 Errors per lane: [2, 0, 1, 9]. Lane 0 is the most noisy/problematic. Errors from the lane 1 are not intersecting with the errors from the worst line 0. Errors from the lane 3 are not intersecting with the errors from the worst line 0. |
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| Lane phase adjustments: [0, 0, 0, 0] Error statistics from memtester: [solidbits=14, bitspread=7, bitflip=1] Best number of successful memtester runs, which span over 1 columns (0-0): 60 Best number of successful memtester runs, which span over 2 columns (0-1): 104 Best number of successful memtester runs, which span over 3 columns (0-2): 121 Best number of successful memtester runs, which span over 4 columns (0-3): 141 Best number of successful memtester runs, which span over 5 columns (0-4): 142 Best number of successful memtester runs, which span over 6 columns (0-5): 142 Errors per lane: [3, 1, 3, 15]. Lane 0 is the most noisy/problematic. Errors from the lane 1 are not intersecting with the errors from the worst line 0. Errors from the lane 2 are not intersecting with the errors from the worst line 0. Errors from the lane 3 are not intersecting with the errors from the worst line 0. |
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| Lane phase adjustments: [0, 0, 0, 0] Error statistics from memtester: [solidbits=15, bitspread=8, bitflip=7] Best number of successful memtester runs, which span over 1 columns (0-0): 150 Best number of successful memtester runs, which span over 2 columns (0-1): 261 Best number of successful memtester runs, which span over 3 columns (0-2): 386 Best number of successful memtester runs, which span over 4 columns (0-3): 502 Best number of successful memtester runs, which span over 5 columns (0-4): 613 Best number of successful memtester runs, which span over 6 columns (0-5): 626 Errors per lane: [7, 19, 11, 9]. Lane 2 is the most noisy/problematic. Errors from the lane 0 are not intersecting with the errors from the worst line 2. Errors from the lane 1 are not intersecting with the errors from the worst line 2. Errors from the lane 3 are 100.0% eclipsed by the worst lane 2. |
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| Lane phase adjustments: [0, 0, 0, 0] Error statistics from memtester: [solidbits=30, bitflip=23, bitspread=5, xor=1, sub=1] Best number of successful memtester runs, which span over 1 columns (0-0): 85 Best number of successful memtester runs, which span over 2 columns (0-1): 144 Best number of successful memtester runs, which span over 3 columns (0-2): 206 Best number of successful memtester runs, which span over 4 columns (0-3): 267 Best number of successful memtester runs, which span over 5 columns (0-4): 311 Best number of successful memtester runs, which span over 6 columns (0-5): 321 Errors per lane: [7, 38, 21, 20]. Lane 2 is the most noisy/problematic. Errors from the lane 0 are not intersecting with the errors from the worst line 2. Errors from the lane 1 are not intersecting with the errors from the worst line 2. Errors from the lane 3 are 85.7% eclipsed by the worst lane 2. |