This is a DRAM tuning/overclocking stability report for various Allwinner A10/A13/A20 based devices.It can be automatically generated by the tools from https://github.com/ssvb/a10-meminfo. Here we primarily focus on finding optimal dram_tpr3 values, tuned individually for every sunxi device. Currently these values need to be hardcoded into the sources of the u-boot-sunxi bootloader. The dram_tpr3 parameter is just a hexadecimal number with the following bit fields:

bits [22:20] - MFWDLY of the command lane
bits [18:16] - MFBDLY of the command lane
bits [15:12] - SDPHASE of the byte lane 3
bits [11:8] - SDPHASE of the byte lane 2
bits [7:4] - SDPHASE of the byte lane 1
bits [3:0] - SDPHASE of the byte lane 0

The RK30XX manual can be checked for more details about the MFWDLY, MFBDLY and SDPHASE bit fields. The Rockchip 30XX family of SoCs is apparently using the same DRAM controller IP.

Results interpretation:

The shades of RED/PURPLE/MAGENTA - hardware deadlocks, this usually indicates insufficient dcdc3 voltage.
The shades of RED/ORANGE/YELLOW - data corruption, this may be attributed to other reasons. Including, but not limited to phase misalignment between different byte lanes. See the Figure 6 from Altera - Utilizing Leveling Techniques in DDR3 SDRAM Memory Interfaces as a reasonaby good illustration.
GREEN - no problems detected during just a few minutes of running lima-memtester. These dram_tpr3 values still need thorough verification by a much longer run of lima-memtester (8-10 hours is reasonable) and other stress tests.

Cubieboard1, dram_clk=540MHz

dcdc3_vol = 1250
dram_clk = 540
dram_type = 3
dram_rank_num = 1
dram_chip_density = 4096
dram_io_width = 16
dram_bus_width = 32
dram_cas = 9
dram_zq = 0x7f
dram_odt_en = 0
dram_tpr0 = 0x42d899b7
dram_tpr1 = 0xa090
dram_tpr2 = 0x22a00
dram_tpr3 = 0x0
dram_emr1 = 0x4
dram_emr2 = 0x10
dram_emr3 = 0x0

mfxdly	phase=36	phase=54	phase=72	phase=90	phase=108	phase=126
0x07	0x073333	0x072222	0x071111	0x070000	0x07EEEE	0x07DDDD
0x06	0x063333	0x062222	0x061111	0x060000	0x06EEEE	0x06DDDD
0x05	0x053333	0x052222	0x051111	0x050000	0x05EEEE	0x05DDDD
0x04	0x043333	0x042222	0x041111	0x040000	0x04EEEE	0x04DDDD
0x03	0x033333	0x032222	0x031111	0x030000	0x03EEEE	0x03DDDD
0x02	0x023333	0x022222	0x021111	0x020000	0x02EEEE	0x02DDDD
0x01	0x013333	0x012222	0x011111	0x010000	0x01EEEE	0x01DDDD
0x00	0x003333	0x002222	0x001111	0x000000	0x00EEEE	0x00DDDD
0x08	0x083333	0x082222	0x081111	0x080000	0x08EEEE	0x08DDDD
0x10	0x103333	0x102222	0x101111	0x100000	0x10EEEE	0x10DDDD
0x18	0x183333	0x182222	0x181111	0x180000	0x18EEEE	0x18DDDD
0x20	0x203333	0x202222	0x201111	0x200000	0x20EEEE	0x20DDDD
0x28	0x283333	0x282222	0x281111	0x280000	0x28EEEE	0x28DDDD
0x30	0x303333	0x302222	0x301111	0x300000	0x30EEEE	0x30DDDD
0x38	0x383333	0x382222	0x381111	0x380000	0x38EEEE	0x38DDDD

Lane phase adjustments: [0, 0, 0, 0]

Error statistics from memtester: [solidbits=17, bitflip=13, bitspread=11]

Best number of successful memtester runs, which span over 1 columns (3-3): 60
Best number of successful memtester runs, which span over 2 columns (2-3): 96
Best number of successful memtester runs, which span over 3 columns (1-3): 122
Best number of successful memtester runs, which span over 4 columns (1-4): 131
Best number of successful memtester runs, which span over 5 columns (1-5): 131
Best number of successful memtester runs, which span over 6 columns (0-5): 131

Errors per lane: [20, 14, 27, 22]. Lane 1 is the most noisy/problematic.

Errors from the lane 0 are 63.6% eclipsed by the worst lane 1.
Errors from the lane 2 are 100.0% eclipsed by the worst lane 1.
Errors from the lane 3 are 70.0% eclipsed by the worst lane 1.

mfxdly	phase=36	phase=54	phase=72	phase=90	phase=108
0x07	0x072232	0x071121	0x070010	0x07EE0E	0x07DDED
0x06	0x062232	0x061121	0x060010	0x06EE0E	0x06DDED
0x05	0x052232	0x051121	0x050010	0x05EE0E	0x05DDED
0x04	0x042232	0x041121	0x040010	0x04EE0E	0x04DDED
0x03	0x032232	0x031121	0x030010	0x03EE0E	0x03DDED
0x02	0x022232	0x021121	0x020010	0x02EE0E	0x02DDED
0x01	0x012232	0x011121	0x010010	0x01EE0E	0x01DDED
0x00	0x002232	0x001121	0x000010	0x00EE0E	0x00DDED
0x08	0x082232	0x081121	0x080010	0x08EE0E	0x08DDED
0x10	0x102232	0x101121	0x100010	0x10EE0E	0x10DDED
0x18	0x182232	0x181121	0x180010	0x18EE0E	0x18DDED
0x20	0x202232	0x201121	0x200010	0x20EE0E	0x20DDED
0x28	0x282232	0x281121	0x280010	0x28EE0E	0x28DDED
0x30	0x302232	0x301121	0x300010	0x30EE0E	0x30DDED
0x38	0x382232	0x381121	0x380010	0x38EE0E	0x38DDED

Lane phase adjustments: [1, 1, 0, 1]

Error statistics from memtester: [solidbits=13, bitflip=10, bitspread=9]

Best number of successful memtester runs, which span over 1 columns (2-2): 18
Best number of successful memtester runs, which span over 2 columns (1-2): 36
Best number of successful memtester runs, which span over 3 columns (1-3): 39
Best number of successful memtester runs, which span over 4 columns (0-3): 42
Best number of successful memtester runs, which span over 5 columns (0-4): 42

Errors per lane: [16, 10, 19, 14]. Lane 1 is the most noisy/problematic.

Errors from the lane 0 are 64.3% eclipsed by the worst lane 1.
Errors from the lane 2 are 90.0% eclipsed by the worst lane 1.
Errors from the lane 3 are 56.2% eclipsed by the worst lane 1.

mfxdly	phase=36	phase=54	phase=72	phase=90
0x07	0x071131	0x070020	0x07EE1E	0x07DD0D
0x06	0x061131	0x060020	0x06EE1E	0x06DD0D
0x05	0x051131	0x050020	0x05EE1E	0x05DD0D
0x04	0x041131	0x040020	0x04EE1E	0x04DD0D
0x03	0x031131	0x030020	0x03EE1E	0x03DD0D
0x02	0x021131	0x020020	0x02EE1E	0x02DD0D
0x01	0x011131	0x010020	0x01EE1E	0x01DD0D
0x00	0x001131	0x000020	0x00EE1E	0x00DD0D
0x08	0x081131	0x080020	0x08EE1E	0x08DD0D
0x10	0x101131	0x100020	0x10EE1E	0x10DD0D
0x18	0x181131	0x180020	0x18EE1E	0x18DD0D
0x20	0x201131	0x200020	0x20EE1E	0x20DD0D
0x28	0x281131	0x280020	0x28EE1E	0x28DD0D
0x30	0x301131	0x300020	0x30EE1E	0x30DD0D
0x38	0x381131	0x380020	0x38EE1E	0x38DD0D

Lane phase adjustments: [2, 2, 0, 2]

Error statistics from memtester: [solidbits=14, bitspread=11, bitflip=3]

Best number of successful memtester runs, which span over 1 columns (1-1): 37
Best number of successful memtester runs, which span over 2 columns (0-1): 43
Best number of successful memtester runs, which span over 3 columns (0-2): 45
Best number of successful memtester runs, which span over 4 columns (0-3): 45

Errors per lane: [7, 2, 14, 11]. Lane 1 is the most noisy/problematic.

Errors from the lane 0 are 18.2% eclipsed by the worst lane 1.
Errors from the lane 2 are 100.0% eclipsed by the worst lane 1.
Errors from the lane 3 are 28.6% eclipsed by the worst lane 1.

mfxdly	phase=54	phase=72	phase=90	phase=108	phase=126
0x07	0x073323	0x072212	0x071101	0x0700E0	0x07EEDE
0x06	0x063323	0x062212	0x061101	0x0600E0	0x06EEDE
0x05	0x053323	0x052212	0x051101	0x0500E0	0x05EEDE
0x04	0x043323	0x042212	0x041101	0x0400E0	0x04EEDE
0x03	0x033323	0x032212	0x031101	0x0300E0	0x03EEDE
0x02	0x023323	0x022212	0x021101	0x0200E0	0x02EEDE
0x01	0x013323	0x012212	0x011101	0x0100E0	0x01EEDE
0x00	0x003323	0x002212	0x001101	0x0000E0	0x00EEDE
0x08	0x083323	0x082212	0x081101	0x0800E0	0x08EEDE
0x10	0x103323	0x102212	0x101101	0x1000E0	0x10EEDE
0x18	0x183323	0x182212	0x181101	0x1800E0	0x18EEDE
0x20	0x203323	0x202212	0x201101	0x2000E0	0x20EEDE
0x28	0x283323	0x282212	0x281101	0x2800E0	0x28EEDE
0x30	0x303323	0x302212	0x301101	0x3000E0	0x30EEDE
0x38	0x383323	0x382212	0x381101	0x3800E0	0x38EEDE

Lane phase adjustments: [-1, -1, 0, -1]

Error statistics from memtester: [bitspread=22, bitflip=10]

Best number of successful memtester runs, which span over 1 columns (0-0): 29
Best number of successful memtester runs, which span over 2 columns (0-1): 43
Best number of successful memtester runs, which span over 3 columns (0-2): 61
Best number of successful memtester runs, which span over 4 columns (0-3): 66
Best number of successful memtester runs, which span over 5 columns (0-4): 66

Errors per lane: [7, 7, 27, 12]. Lane 1 is the most noisy/problematic.

Errors from the lane 0 are 58.3% eclipsed by the worst lane 1.
Errors from the lane 2 are 100.0% eclipsed by the worst lane 1.
Errors from the lane 3 are 100.0% eclipsed by the worst lane 1.

mfxdly	phase=72	phase=90	phase=108	phase=126
0x07	0x073313	0x072202	0x0711E1	0x0700D0
0x06	0x063313	0x062202	0x0611E1	0x0600D0
0x05	0x053313	0x052202	0x0511E1	0x0500D0
0x04	0x043313	0x042202	0x0411E1	0x0400D0
0x03	0x033313	0x032202	0x0311E1	0x0300D0
0x02	0x023313	0x022202	0x0211E1	0x0200D0
0x01	0x013313	0x012202	0x0111E1	0x0100D0
0x00	0x003313	0x002202	0x0011E1	0x0000D0
0x08	0x083313	0x082202	0x0811E1	0x0800D0
0x10	0x103313	0x102202	0x1011E1	0x1000D0
0x18	0x183313	0x182202	0x1811E1	0x1800D0
0x20	0x203313	0x202202	0x2011E1	0x2000D0
0x28	0x283313	0x282202	0x2811E1	0x2800D0
0x30	0x303313	0x302202	0x3011E1	0x3000D0
0x38	0x383313	0x382202	0x3811E1	0x3800D0

Lane phase adjustments: [-2, -2, 0, -2]

Error statistics from memtester: [bitspread=17, bitflip=12, solidbits=1]

Best number of successful memtester runs, which span over 1 columns (1-1): 20
Best number of successful memtester runs, which span over 2 columns (0-1): 38
Best number of successful memtester runs, which span over 3 columns (0-2): 40
Best number of successful memtester runs, which span over 4 columns (0-3): 40

Errors per lane: [8, 8, 29, 7]. Lane 1 is the most noisy/problematic.

Errors from the lane 0 are 100.0% eclipsed by the worst lane 1.
Errors from the lane 2 are 87.5% eclipsed by the worst lane 1.
Errors from the lane 3 are 87.5% eclipsed by the worst lane 1.

mfxdly	phase=72	phase=90	phase=108	phase=126
0x07	0x072113	0x071002	0x070EE1	0x07EDD0
0x06	0x062113	0x061002	0x060EE1	0x06EDD0
0x05	0x052113	0x051002	0x050EE1	0x05EDD0
0x04	0x042113	0x041002	0x040EE1	0x04EDD0
0x03	0x032113	0x031002	0x030EE1	0x03EDD0
0x02	0x022113	0x021002	0x020EE1	0x02EDD0
0x01	0x012113	0x011002	0x010EE1	0x01EDD0
0x00	0x002113	0x001002	0x000EE1	0x00EDD0
0x08	0x082113	0x081002	0x080EE1	0x08EDD0
0x10	0x102113	0x101002	0x100EE1	0x10EDD0
0x18	0x182113	0x181002	0x180EE1	0x18EDD0
0x20	0x202113	0x201002	0x200EE1	0x20EDD0
0x28	0x282113	0x281002	0x280EE1	0x28EDD0
0x30	0x302113	0x301002	0x300EE1	0x30EDD0
0x38	0x382113	0x381002	0x380EE1	0x38EDD0

Lane phase adjustments: [-1, 0, 0, -2]

Error statistics from memtester: [bitspread=18, bitflip=15, solidbits=3]

Best number of successful memtester runs, which span over 1 columns (1-1): 20
Best number of successful memtester runs, which span over 2 columns (0-1): 35
Best number of successful memtester runs, which span over 3 columns (0-2): 41
Best number of successful memtester runs, which span over 4 columns (0-3): 41

Errors per lane: [13, 13, 36, 13]. Lane 1 is the most noisy/problematic.

Errors from the lane 0 are 100.0% eclipsed by the worst lane 1.
Errors from the lane 2 are 100.0% eclipsed by the worst lane 1.
Errors from the lane 3 are 100.0% eclipsed by the worst lane 1.